dp_tx.c 95 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #ifdef TX_PER_PDEV_DESC_POOL
  32. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  33. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  34. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  35. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  36. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  37. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  38. #else
  39. #ifdef TX_PER_VDEV_DESC_POOL
  40. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  41. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  42. #else
  43. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  44. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  45. #endif /* TX_PER_VDEV_DESC_POOL */
  46. #endif /* TX_PER_PDEV_DESC_POOL */
  47. /* TODO Add support in TSO */
  48. #define DP_DESC_NUM_FRAG(x) 0
  49. /* disable TQM_BYPASS */
  50. #define TQM_BYPASS_WAR 0
  51. /* invalid peer id for reinject*/
  52. #define DP_INVALID_PEER 0XFFFE
  53. /*mapping between hal encrypt type and cdp_sec_type*/
  54. #define MAX_CDP_SEC_TYPE 12
  55. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  56. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  57. HAL_TX_ENCRYPT_TYPE_WEP_128,
  58. HAL_TX_ENCRYPT_TYPE_WEP_104,
  59. HAL_TX_ENCRYPT_TYPE_WEP_40,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  61. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  62. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  63. HAL_TX_ENCRYPT_TYPE_WAPI,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  66. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  68. /**
  69. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  70. * @vdev: DP Virtual device handle
  71. * @nbuf: Buffer pointer
  72. * @queue: queue ids container for nbuf
  73. *
  74. * TX packet queue has 2 instances, software descriptors id and dma ring id
  75. * Based on tx feature and hardware configuration queue id combination could be
  76. * different.
  77. * For example -
  78. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  79. * With no XPS,lock based resource protection, Descriptor pool ids are different
  80. * for each vdev, dma ring id will be same as single pdev id
  81. *
  82. * Return: None
  83. */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_desc_release() - Release the tso segment
  98. * after unmapping all the fragments
  99. *
  100. * @pdev - physical device handle
  101. * @tx_desc - Tx software descriptor
  102. */
  103. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  104. struct dp_tx_desc_s *tx_desc)
  105. {
  106. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  107. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  109. "%s %d TSO desc is NULL!",
  110. __func__, __LINE__);
  111. qdf_assert(0);
  112. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  113. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  114. "%s %d TSO common info is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  121. tso_num_desc->num_seg.tso_cmn_num_seg--;
  122. qdf_nbuf_unmap_tso_segment(soc->osdev,
  123. tx_desc->tso_desc, false);
  124. } else {
  125. tso_num_desc->num_seg.tso_cmn_num_seg--;
  126. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  127. qdf_nbuf_unmap_tso_segment(soc->osdev,
  128. tx_desc->tso_desc, true);
  129. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  130. tx_desc->tso_num_desc);
  131. tx_desc->tso_num_desc = NULL;
  132. }
  133. dp_tx_tso_desc_free(soc,
  134. tx_desc->pool_id, tx_desc->tso_desc);
  135. tx_desc->tso_desc = NULL;
  136. }
  137. }
  138. #else
  139. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  140. struct dp_tx_desc_s *tx_desc)
  141. {
  142. return;
  143. }
  144. #endif
  145. /**
  146. * dp_tx_desc_release() - Release Tx Descriptor
  147. * @tx_desc : Tx Descriptor
  148. * @desc_pool_id: Descriptor Pool ID
  149. *
  150. * Deallocate all resources attached to Tx descriptor and free the Tx
  151. * descriptor.
  152. *
  153. * Return:
  154. */
  155. static void
  156. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  157. {
  158. struct dp_pdev *pdev = tx_desc->pdev;
  159. struct dp_soc *soc;
  160. uint8_t comp_status = 0;
  161. qdf_assert(pdev);
  162. soc = pdev->soc;
  163. if (tx_desc->frm_type == dp_tx_frm_tso)
  164. dp_tx_tso_desc_release(soc, tx_desc);
  165. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  166. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  168. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  169. qdf_atomic_dec(&pdev->num_tx_outstanding);
  170. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  171. qdf_atomic_dec(&pdev->num_tx_exception);
  172. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  173. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  174. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  175. else
  176. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  178. "Tx Completion Release desc %d status %d outstanding %d",
  179. tx_desc->id, comp_status,
  180. qdf_atomic_read(&pdev->num_tx_outstanding));
  181. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  182. return;
  183. }
  184. /**
  185. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  186. * @vdev: DP vdev Handle
  187. * @nbuf: skb
  188. *
  189. * Prepares and fills HTT metadata in the frame pre-header for special frames
  190. * that should be transmitted using varying transmit parameters.
  191. * There are 2 VDEV modes that currently needs this special metadata -
  192. * 1) Mesh Mode
  193. * 2) DSRC Mode
  194. *
  195. * Return: HTT metadata size
  196. *
  197. */
  198. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  199. uint32_t *meta_data)
  200. {
  201. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  202. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  203. uint8_t htt_desc_size;
  204. /* Size rounded of multiple of 8 bytes */
  205. uint8_t htt_desc_size_aligned;
  206. uint8_t *hdr = NULL;
  207. /*
  208. * Metadata - HTT MSDU Extension header
  209. */
  210. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  211. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  212. if (vdev->mesh_vdev) {
  213. /* Fill and add HTT metaheader */
  214. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  215. if (hdr == NULL) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "Error in filling HTT metadata\n");
  218. return 0;
  219. }
  220. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  221. } else if (vdev->opmode == wlan_op_mode_ocb) {
  222. /* Todo - Add support for DSRC */
  223. }
  224. return htt_desc_size_aligned;
  225. }
  226. /**
  227. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  228. * @tso_seg: TSO segment to process
  229. * @ext_desc: Pointer to MSDU extension descriptor
  230. *
  231. * Return: void
  232. */
  233. #if defined(FEATURE_TSO)
  234. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  235. void *ext_desc)
  236. {
  237. uint8_t num_frag;
  238. uint32_t tso_flags;
  239. /*
  240. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  241. * tcp_flag_mask
  242. *
  243. * Checksum enable flags are set in TCL descriptor and not in Extension
  244. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  245. */
  246. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  247. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  248. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  249. tso_seg->tso_flags.ip_len);
  250. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  251. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  252. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  253. uint32_t lo = 0;
  254. uint32_t hi = 0;
  255. qdf_dmaaddr_to_32s(
  256. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  257. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  258. tso_seg->tso_frags[num_frag].length);
  259. }
  260. return;
  261. }
  262. #else
  263. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  264. void *ext_desc)
  265. {
  266. return;
  267. }
  268. #endif
  269. #if defined(FEATURE_TSO)
  270. /**
  271. * dp_tx_free_tso_seg() - Loop through the tso segments
  272. * allocated and free them
  273. *
  274. * @soc: soc handle
  275. * @free_seg: list of tso segments
  276. * @msdu_info: msdu descriptor
  277. *
  278. * Return - void
  279. */
  280. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  281. struct qdf_tso_seg_elem_t *free_seg,
  282. struct dp_tx_msdu_info_s *msdu_info)
  283. {
  284. struct qdf_tso_seg_elem_t *next_seg;
  285. while (free_seg) {
  286. next_seg = free_seg->next;
  287. dp_tx_tso_desc_free(soc,
  288. msdu_info->tx_queue.desc_pool_id,
  289. free_seg);
  290. free_seg = next_seg;
  291. }
  292. }
  293. /**
  294. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  295. * allocated and free them
  296. *
  297. * @soc: soc handle
  298. * @free_seg: list of tso segments
  299. * @msdu_info: msdu descriptor
  300. * Return - void
  301. */
  302. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  303. struct qdf_tso_num_seg_elem_t *free_seg,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. struct qdf_tso_num_seg_elem_t *next_seg;
  307. while (free_seg) {
  308. next_seg = free_seg->next;
  309. dp_tso_num_seg_free(soc,
  310. msdu_info->tx_queue.desc_pool_id,
  311. free_seg);
  312. free_seg = next_seg;
  313. }
  314. }
  315. /**
  316. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  317. * @vdev: virtual device handle
  318. * @msdu: network buffer
  319. * @msdu_info: meta data associated with the msdu
  320. *
  321. * Return: QDF_STATUS_SUCCESS success
  322. */
  323. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  324. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  325. {
  326. struct qdf_tso_seg_elem_t *tso_seg;
  327. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  328. struct dp_soc *soc = vdev->pdev->soc;
  329. struct qdf_tso_info_t *tso_info;
  330. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  331. tso_info = &msdu_info->u.tso_info;
  332. tso_info->curr_seg = NULL;
  333. tso_info->tso_seg_list = NULL;
  334. tso_info->num_segs = num_seg;
  335. msdu_info->frm_type = dp_tx_frm_tso;
  336. tso_info->tso_num_seg_list = NULL;
  337. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  338. while (num_seg) {
  339. tso_seg = dp_tx_tso_desc_alloc(
  340. soc, msdu_info->tx_queue.desc_pool_id);
  341. if (tso_seg) {
  342. tso_seg->next = tso_info->tso_seg_list;
  343. tso_info->tso_seg_list = tso_seg;
  344. num_seg--;
  345. } else {
  346. struct qdf_tso_seg_elem_t *free_seg =
  347. tso_info->tso_seg_list;
  348. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  349. return QDF_STATUS_E_NOMEM;
  350. }
  351. }
  352. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  353. tso_num_seg = dp_tso_num_seg_alloc(soc,
  354. msdu_info->tx_queue.desc_pool_id);
  355. if (tso_num_seg) {
  356. tso_num_seg->next = tso_info->tso_num_seg_list;
  357. tso_info->tso_num_seg_list = tso_num_seg;
  358. } else {
  359. /* Bug: free tso_num_seg and tso_seg */
  360. /* Free the already allocated num of segments */
  361. struct qdf_tso_seg_elem_t *free_seg =
  362. tso_info->tso_seg_list;
  363. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  364. __func__);
  365. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  366. return QDF_STATUS_E_NOMEM;
  367. }
  368. msdu_info->num_seg =
  369. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  370. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  371. msdu_info->num_seg);
  372. if (!(msdu_info->num_seg)) {
  373. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  374. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  375. msdu_info);
  376. return QDF_STATUS_E_INVAL;
  377. }
  378. tso_info->curr_seg = tso_info->tso_seg_list;
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. #else
  382. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  383. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. return QDF_STATUS_E_NOMEM;
  386. }
  387. #endif
  388. /**
  389. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  390. * @vdev: DP Vdev handle
  391. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  392. * @desc_pool_id: Descriptor Pool ID
  393. *
  394. * Return:
  395. */
  396. static
  397. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  398. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  399. {
  400. uint8_t i;
  401. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  402. struct dp_tx_seg_info_s *seg_info;
  403. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  404. struct dp_soc *soc = vdev->pdev->soc;
  405. /* Allocate an extension descriptor */
  406. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  407. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  408. if (!msdu_ext_desc) {
  409. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  410. return NULL;
  411. }
  412. if (msdu_info->exception_fw &&
  413. qdf_unlikely(vdev->mesh_vdev)) {
  414. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  415. &msdu_info->meta_data[0],
  416. sizeof(struct htt_tx_msdu_desc_ext2_t));
  417. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  418. }
  419. switch (msdu_info->frm_type) {
  420. case dp_tx_frm_sg:
  421. case dp_tx_frm_me:
  422. case dp_tx_frm_raw:
  423. seg_info = msdu_info->u.sg_info.curr_seg;
  424. /* Update the buffer pointers in MSDU Extension Descriptor */
  425. for (i = 0; i < seg_info->frag_cnt; i++) {
  426. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  427. seg_info->frags[i].paddr_lo,
  428. seg_info->frags[i].paddr_hi,
  429. seg_info->frags[i].len);
  430. }
  431. break;
  432. case dp_tx_frm_tso:
  433. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  434. &cached_ext_desc[0]);
  435. break;
  436. default:
  437. break;
  438. }
  439. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  440. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  441. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  442. msdu_ext_desc->vaddr);
  443. return msdu_ext_desc;
  444. }
  445. /**
  446. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  447. * @vdev: DP vdev handle
  448. * @nbuf: skb
  449. * @desc_pool_id: Descriptor pool ID
  450. * @meta_data: Metadata to the fw
  451. * @tx_exc_metadata: Handle that holds exception path metadata
  452. * Allocate and prepare Tx descriptor with msdu information.
  453. *
  454. * Return: Pointer to Tx Descriptor on success,
  455. * NULL on failure
  456. */
  457. static
  458. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  459. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  460. struct dp_tx_msdu_info_s *msdu_info,
  461. struct cdp_tx_exception_metadata *tx_exc_metadata)
  462. {
  463. uint8_t align_pad;
  464. uint8_t is_exception = 0;
  465. uint8_t htt_hdr_size;
  466. struct ether_header *eh;
  467. struct dp_tx_desc_s *tx_desc;
  468. struct dp_pdev *pdev = vdev->pdev;
  469. struct dp_soc *soc = pdev->soc;
  470. /* Allocate software Tx descriptor */
  471. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  472. if (qdf_unlikely(!tx_desc)) {
  473. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  474. return NULL;
  475. }
  476. /* Flow control/Congestion Control counters */
  477. qdf_atomic_inc(&pdev->num_tx_outstanding);
  478. /* Initialize the SW tx descriptor */
  479. tx_desc->nbuf = nbuf;
  480. tx_desc->frm_type = dp_tx_frm_std;
  481. tx_desc->tx_encap_type = (tx_exc_metadata ?
  482. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  483. tx_desc->vdev = vdev;
  484. tx_desc->pdev = pdev;
  485. tx_desc->msdu_ext_desc = NULL;
  486. tx_desc->pkt_offset = 0;
  487. /*
  488. * For special modes (vdev_type == ocb or mesh), data frames should be
  489. * transmitted using varying transmit parameters (tx spec) which include
  490. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  491. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  492. * These frames are sent as exception packets to firmware.
  493. *
  494. * HW requirement is that metadata should always point to a
  495. * 8-byte aligned address. So we add alignment pad to start of buffer.
  496. * HTT Metadata should be ensured to be multiple of 8-bytes,
  497. * to get 8-byte aligned start address along with align_pad added
  498. *
  499. * |-----------------------------|
  500. * | |
  501. * |-----------------------------| <-----Buffer Pointer Address given
  502. * | | ^ in HW descriptor (aligned)
  503. * | HTT Metadata | |
  504. * | | |
  505. * | | | Packet Offset given in descriptor
  506. * | | |
  507. * |-----------------------------| |
  508. * | Alignment Pad | v
  509. * |-----------------------------| <----- Actual buffer start address
  510. * | SKB Data | (Unaligned)
  511. * | |
  512. * | |
  513. * | |
  514. * | |
  515. * | |
  516. * |-----------------------------|
  517. */
  518. if (qdf_unlikely((msdu_info->exception_fw)) ||
  519. (vdev->opmode == wlan_op_mode_ocb)) {
  520. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  521. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  523. "qdf_nbuf_push_head failed\n");
  524. goto failure;
  525. }
  526. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  527. msdu_info->meta_data);
  528. if (htt_hdr_size == 0)
  529. goto failure;
  530. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  531. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  532. is_exception = 1;
  533. }
  534. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  535. qdf_nbuf_map(soc->osdev, nbuf,
  536. QDF_DMA_TO_DEVICE))) {
  537. /* Handle failure */
  538. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  539. "qdf_nbuf_map failed\n");
  540. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  541. goto failure;
  542. }
  543. if (qdf_unlikely(vdev->nawds_enabled)) {
  544. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  545. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  546. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  547. is_exception = 1;
  548. }
  549. }
  550. #if !TQM_BYPASS_WAR
  551. if (is_exception || tx_exc_metadata)
  552. #endif
  553. {
  554. /* Temporary WAR due to TQM VP issues */
  555. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  556. qdf_atomic_inc(&pdev->num_tx_exception);
  557. }
  558. return tx_desc;
  559. failure:
  560. dp_tx_desc_release(tx_desc, desc_pool_id);
  561. return NULL;
  562. }
  563. /**
  564. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  565. * @vdev: DP vdev handle
  566. * @nbuf: skb
  567. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  568. * @desc_pool_id : Descriptor Pool ID
  569. *
  570. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  571. * information. For frames wth fragments, allocate and prepare
  572. * an MSDU extension descriptor
  573. *
  574. * Return: Pointer to Tx Descriptor on success,
  575. * NULL on failure
  576. */
  577. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  578. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  579. uint8_t desc_pool_id)
  580. {
  581. struct dp_tx_desc_s *tx_desc;
  582. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  583. struct dp_pdev *pdev = vdev->pdev;
  584. struct dp_soc *soc = pdev->soc;
  585. /* Allocate software Tx descriptor */
  586. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  587. if (!tx_desc) {
  588. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  589. return NULL;
  590. }
  591. /* Flow control/Congestion Control counters */
  592. qdf_atomic_inc(&pdev->num_tx_outstanding);
  593. /* Initialize the SW tx descriptor */
  594. tx_desc->nbuf = nbuf;
  595. tx_desc->frm_type = msdu_info->frm_type;
  596. tx_desc->tx_encap_type = vdev->tx_encap_type;
  597. tx_desc->vdev = vdev;
  598. tx_desc->pdev = pdev;
  599. tx_desc->pkt_offset = 0;
  600. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  601. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  602. /* Handle scattered frames - TSO/SG/ME */
  603. /* Allocate and prepare an extension descriptor for scattered frames */
  604. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  605. if (!msdu_ext_desc) {
  606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  607. "%s Tx Extension Descriptor Alloc Fail\n",
  608. __func__);
  609. goto failure;
  610. }
  611. #if TQM_BYPASS_WAR
  612. /* Temporary WAR due to TQM VP issues */
  613. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  614. qdf_atomic_inc(&pdev->num_tx_exception);
  615. #endif
  616. if (qdf_unlikely(msdu_info->exception_fw))
  617. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  618. tx_desc->msdu_ext_desc = msdu_ext_desc;
  619. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  620. return tx_desc;
  621. failure:
  622. dp_tx_desc_release(tx_desc, desc_pool_id);
  623. return NULL;
  624. }
  625. /**
  626. * dp_tx_prepare_raw() - Prepare RAW packet TX
  627. * @vdev: DP vdev handle
  628. * @nbuf: buffer pointer
  629. * @seg_info: Pointer to Segment info Descriptor to be prepared
  630. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  631. * descriptor
  632. *
  633. * Return:
  634. */
  635. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  636. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  637. {
  638. qdf_nbuf_t curr_nbuf = NULL;
  639. uint16_t total_len = 0;
  640. qdf_dma_addr_t paddr;
  641. int32_t i;
  642. int32_t mapped_buf_num = 0;
  643. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  644. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  645. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  646. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  647. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  648. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  649. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  650. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  651. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  652. QDF_DMA_TO_DEVICE)) {
  653. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  654. "%s dma map error \n", __func__);
  655. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  656. mapped_buf_num = i;
  657. goto error;
  658. }
  659. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  660. seg_info->frags[i].paddr_lo = paddr;
  661. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  662. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  663. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  664. total_len += qdf_nbuf_len(curr_nbuf);
  665. }
  666. seg_info->frag_cnt = i;
  667. seg_info->total_len = total_len;
  668. seg_info->next = NULL;
  669. sg_info->curr_seg = seg_info;
  670. msdu_info->frm_type = dp_tx_frm_raw;
  671. msdu_info->num_seg = 1;
  672. return nbuf;
  673. error:
  674. i = 0;
  675. while (nbuf) {
  676. curr_nbuf = nbuf;
  677. if (i < mapped_buf_num) {
  678. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  679. i++;
  680. }
  681. nbuf = qdf_nbuf_next(nbuf);
  682. qdf_nbuf_free(curr_nbuf);
  683. }
  684. return NULL;
  685. }
  686. /**
  687. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  688. * @soc: DP Soc Handle
  689. * @vdev: DP vdev handle
  690. * @tx_desc: Tx Descriptor Handle
  691. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  692. * @fw_metadata: Metadata to send to Target Firmware along with frame
  693. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  694. * @tx_exc_metadata: Handle that holds exception path meta data
  695. *
  696. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  697. * from software Tx descriptor
  698. *
  699. * Return:
  700. */
  701. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  702. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  703. uint16_t fw_metadata, uint8_t ring_id,
  704. struct cdp_tx_exception_metadata
  705. *tx_exc_metadata)
  706. {
  707. uint8_t type;
  708. uint16_t length;
  709. void *hal_tx_desc, *hal_tx_desc_cached;
  710. qdf_dma_addr_t dma_addr;
  711. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  712. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  713. tx_exc_metadata->sec_type : vdev->sec_type);
  714. /* Return Buffer Manager ID */
  715. uint8_t bm_id = ring_id;
  716. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  717. hal_tx_desc_cached = (void *) cached_desc;
  718. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  719. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  720. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  721. type = HAL_TX_BUF_TYPE_EXT_DESC;
  722. dma_addr = tx_desc->msdu_ext_desc->paddr;
  723. } else {
  724. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  725. type = HAL_TX_BUF_TYPE_BUFFER;
  726. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  727. }
  728. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  729. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  730. dma_addr , bm_id, tx_desc->id, type);
  731. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  732. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  733. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  734. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  735. HAL_TX_DESC_DEFAULT_LMAC_ID);
  736. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  737. vdev->dscp_tid_map_id);
  738. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  739. sec_type_map[sec_type]);
  740. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  741. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  742. __func__, length, type, (uint64_t)dma_addr,
  743. tx_desc->pkt_offset, tx_desc->id);
  744. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  745. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  746. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  747. vdev->hal_desc_addr_search_flags);
  748. /* verify checksum offload configuration*/
  749. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  750. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  751. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  752. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  753. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  754. }
  755. if (tid != HTT_TX_EXT_TID_INVALID)
  756. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  757. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  758. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  759. /* Sync cached descriptor with HW */
  760. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  761. if (!hal_tx_desc) {
  762. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  763. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  764. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  765. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  766. return QDF_STATUS_E_RESOURCES;
  767. }
  768. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  769. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  770. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  771. /*
  772. * If one packet is enqueued in HW, PM usage count needs to be
  773. * incremented by one to prevent future runtime suspend. This
  774. * should be tied with the success of enqueuing. It will be
  775. * decremented after the packet has been sent.
  776. */
  777. hif_pm_runtime_get_noresume(soc->hif_handle);
  778. return QDF_STATUS_SUCCESS;
  779. }
  780. /**
  781. * dp_cce_classify() - Classify the frame based on CCE rules
  782. * @vdev: DP vdev handle
  783. * @nbuf: skb
  784. *
  785. * Classify frames based on CCE rules
  786. * Return: bool( true if classified,
  787. * else false)
  788. */
  789. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  790. {
  791. struct ether_header *eh = NULL;
  792. uint16_t ether_type;
  793. qdf_llc_t *llcHdr;
  794. qdf_nbuf_t nbuf_clone = NULL;
  795. qdf_dot3_qosframe_t *qos_wh = NULL;
  796. /* for mesh packets don't do any classification */
  797. if (qdf_unlikely(vdev->mesh_vdev))
  798. return false;
  799. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  800. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  801. ether_type = eh->ether_type;
  802. llcHdr = (qdf_llc_t *)(nbuf->data +
  803. sizeof(struct ether_header));
  804. } else {
  805. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  806. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  807. if (qdf_unlikely(
  808. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  809. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  810. ether_type = *(uint16_t *)(nbuf->data
  811. + QDF_IEEE80211_4ADDR_HDR_LEN
  812. + sizeof(qdf_llc_t)
  813. - sizeof(ether_type));
  814. llcHdr = (qdf_llc_t *)(nbuf->data +
  815. QDF_IEEE80211_4ADDR_HDR_LEN);
  816. } else {
  817. ether_type = *(uint16_t *)(nbuf->data
  818. + QDF_IEEE80211_3ADDR_HDR_LEN
  819. + sizeof(qdf_llc_t)
  820. - sizeof(ether_type));
  821. llcHdr = (qdf_llc_t *)(nbuf->data +
  822. QDF_IEEE80211_3ADDR_HDR_LEN);
  823. }
  824. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  825. && (ether_type ==
  826. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  827. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  828. return true;
  829. }
  830. }
  831. return false;
  832. }
  833. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  834. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  835. sizeof(*llcHdr));
  836. nbuf_clone = qdf_nbuf_clone(nbuf);
  837. if (qdf_unlikely(nbuf_clone)) {
  838. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  839. if (ether_type == htons(ETHERTYPE_8021Q)) {
  840. qdf_nbuf_pull_head(nbuf_clone,
  841. sizeof(qdf_net_vlanhdr_t));
  842. }
  843. }
  844. } else {
  845. if (ether_type == htons(ETHERTYPE_8021Q)) {
  846. nbuf_clone = qdf_nbuf_clone(nbuf);
  847. if (qdf_unlikely(nbuf_clone)) {
  848. qdf_nbuf_pull_head(nbuf_clone,
  849. sizeof(qdf_net_vlanhdr_t));
  850. }
  851. }
  852. }
  853. if (qdf_unlikely(nbuf_clone))
  854. nbuf = nbuf_clone;
  855. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  856. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  857. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  858. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  859. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  860. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  861. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  862. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  863. if (qdf_unlikely(nbuf_clone != NULL))
  864. qdf_nbuf_free(nbuf_clone);
  865. return true;
  866. }
  867. if (qdf_unlikely(nbuf_clone != NULL))
  868. qdf_nbuf_free(nbuf_clone);
  869. return false;
  870. }
  871. /**
  872. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  873. * @vdev: DP vdev handle
  874. * @nbuf: skb
  875. *
  876. * Extract the DSCP or PCP information from frame and map into TID value.
  877. * Software based TID classification is required when more than 2 DSCP-TID
  878. * mapping tables are needed.
  879. * Hardware supports 2 DSCP-TID mapping tables
  880. *
  881. * Return: void
  882. */
  883. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  884. struct dp_tx_msdu_info_s *msdu_info)
  885. {
  886. uint8_t tos = 0, dscp_tid_override = 0;
  887. uint8_t *hdr_ptr, *L3datap;
  888. uint8_t is_mcast = 0;
  889. struct ether_header *eh = NULL;
  890. qdf_ethervlan_header_t *evh = NULL;
  891. uint16_t ether_type;
  892. qdf_llc_t *llcHdr;
  893. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  894. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  895. if (vdev->dscp_tid_map_id <= 1)
  896. return;
  897. /* for mesh packets don't do any classification */
  898. if (qdf_unlikely(vdev->mesh_vdev))
  899. return;
  900. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  901. eh = (struct ether_header *) nbuf->data;
  902. hdr_ptr = eh->ether_dhost;
  903. L3datap = hdr_ptr + sizeof(struct ether_header);
  904. } else {
  905. qdf_dot3_qosframe_t *qos_wh =
  906. (qdf_dot3_qosframe_t *) nbuf->data;
  907. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  908. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  909. return;
  910. }
  911. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  912. ether_type = eh->ether_type;
  913. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  914. /*
  915. * Check if packet is dot3 or eth2 type.
  916. */
  917. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  918. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  919. sizeof(*llcHdr));
  920. if (ether_type == htons(ETHERTYPE_8021Q)) {
  921. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  922. sizeof(*llcHdr);
  923. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  924. + sizeof(*llcHdr) +
  925. sizeof(qdf_net_vlanhdr_t));
  926. } else {
  927. L3datap = hdr_ptr + sizeof(struct ether_header) +
  928. sizeof(*llcHdr);
  929. }
  930. } else {
  931. if (ether_type == htons(ETHERTYPE_8021Q)) {
  932. evh = (qdf_ethervlan_header_t *) eh;
  933. ether_type = evh->ether_type;
  934. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  935. }
  936. }
  937. /*
  938. * Find priority from IP TOS DSCP field
  939. */
  940. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  941. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  942. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  943. /* Only for unicast frames */
  944. if (!is_mcast) {
  945. /* send it on VO queue */
  946. msdu_info->tid = DP_VO_TID;
  947. }
  948. } else {
  949. /*
  950. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  951. * from TOS byte.
  952. */
  953. tos = ip->ip_tos;
  954. dscp_tid_override = 1;
  955. }
  956. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  957. /* TODO
  958. * use flowlabel
  959. *igmpmld cases to be handled in phase 2
  960. */
  961. unsigned long ver_pri_flowlabel;
  962. unsigned long pri;
  963. ver_pri_flowlabel = *(unsigned long *) L3datap;
  964. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  965. DP_IPV6_PRIORITY_SHIFT;
  966. tos = pri;
  967. dscp_tid_override = 1;
  968. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  969. msdu_info->tid = DP_VO_TID;
  970. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  971. /* Only for unicast frames */
  972. if (!is_mcast) {
  973. /* send ucast arp on VO queue */
  974. msdu_info->tid = DP_VO_TID;
  975. }
  976. }
  977. /*
  978. * Assign all MCAST packets to BE
  979. */
  980. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  981. if (is_mcast) {
  982. tos = 0;
  983. dscp_tid_override = 1;
  984. }
  985. }
  986. if (dscp_tid_override == 1) {
  987. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  988. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  989. }
  990. return;
  991. }
  992. #ifdef CONVERGED_TDLS_ENABLE
  993. /**
  994. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  995. * @tx_desc: TX descriptor
  996. *
  997. * Return: None
  998. */
  999. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1000. {
  1001. if (tx_desc->vdev) {
  1002. if (tx_desc->vdev->is_tdls_frame)
  1003. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1004. tx_desc->vdev->is_tdls_frame = false;
  1005. }
  1006. }
  1007. /**
  1008. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1009. * @tx_desc: TX descriptor
  1010. * @vdev: datapath vdev handle
  1011. *
  1012. * Return: None
  1013. */
  1014. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1015. struct dp_vdev *vdev)
  1016. {
  1017. struct hal_tx_completion_status ts = {0};
  1018. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1019. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1020. if (vdev->tx_non_std_data_callback.func) {
  1021. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1022. vdev->tx_non_std_data_callback.func(
  1023. vdev->tx_non_std_data_callback.ctxt,
  1024. nbuf, ts.status);
  1025. return;
  1026. }
  1027. }
  1028. #endif
  1029. /**
  1030. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1031. * @vdev: DP vdev handle
  1032. * @nbuf: skb
  1033. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1034. * @meta_data: Metadata to the fw
  1035. * @tx_q: Tx queue to be used for this Tx frame
  1036. * @peer_id: peer_id of the peer in case of NAWDS frames
  1037. * @tx_exc_metadata: Handle that holds exception path metadata
  1038. *
  1039. * Return: NULL on success,
  1040. * nbuf when it fails to send
  1041. */
  1042. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1043. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1044. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1045. {
  1046. struct dp_pdev *pdev = vdev->pdev;
  1047. struct dp_soc *soc = pdev->soc;
  1048. struct dp_tx_desc_s *tx_desc;
  1049. QDF_STATUS status;
  1050. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1051. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1052. uint16_t htt_tcl_metadata = 0;
  1053. uint8_t tid = msdu_info->tid;
  1054. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1055. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1056. msdu_info, tx_exc_metadata);
  1057. if (!tx_desc) {
  1058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1059. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1060. __func__, vdev, tx_q->desc_pool_id);
  1061. return nbuf;
  1062. }
  1063. if (qdf_unlikely(soc->cce_disable)) {
  1064. if (dp_cce_classify(vdev, nbuf) == true) {
  1065. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1066. tid = DP_VO_TID;
  1067. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1068. }
  1069. }
  1070. dp_tx_update_tdls_flags(tx_desc);
  1071. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1072. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1073. "%s %d : HAL RING Access Failed -- %pK\n",
  1074. __func__, __LINE__, hal_srng);
  1075. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1076. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1077. goto fail_return;
  1078. }
  1079. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1080. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1081. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1082. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1083. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1084. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1085. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1086. peer_id);
  1087. } else
  1088. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1089. if (msdu_info->exception_fw) {
  1090. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1091. }
  1092. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1093. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1094. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1095. if (status != QDF_STATUS_SUCCESS) {
  1096. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1097. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1098. __func__, tx_desc, tx_q->ring_id);
  1099. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1100. goto fail_return;
  1101. }
  1102. nbuf = NULL;
  1103. fail_return:
  1104. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1105. hal_srng_access_end(soc->hal_soc, hal_srng);
  1106. hif_pm_runtime_put(soc->hif_handle);
  1107. } else {
  1108. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1109. }
  1110. return nbuf;
  1111. }
  1112. /**
  1113. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1114. * @vdev: DP vdev handle
  1115. * @nbuf: skb
  1116. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1117. *
  1118. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1119. *
  1120. * Return: NULL on success,
  1121. * nbuf when it fails to send
  1122. */
  1123. #if QDF_LOCK_STATS
  1124. static noinline
  1125. #else
  1126. static
  1127. #endif
  1128. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1129. struct dp_tx_msdu_info_s *msdu_info)
  1130. {
  1131. uint8_t i;
  1132. struct dp_pdev *pdev = vdev->pdev;
  1133. struct dp_soc *soc = pdev->soc;
  1134. struct dp_tx_desc_s *tx_desc;
  1135. bool is_cce_classified = false;
  1136. QDF_STATUS status;
  1137. uint16_t htt_tcl_metadata = 0;
  1138. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1139. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1140. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1141. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1142. "%s %d : HAL RING Access Failed -- %pK\n",
  1143. __func__, __LINE__, hal_srng);
  1144. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1145. return nbuf;
  1146. }
  1147. if (qdf_unlikely(soc->cce_disable)) {
  1148. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1149. if (is_cce_classified) {
  1150. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1151. msdu_info->tid = DP_VO_TID;
  1152. }
  1153. }
  1154. if (msdu_info->frm_type == dp_tx_frm_me)
  1155. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1156. i = 0;
  1157. /* Print statement to track i and num_seg */
  1158. /*
  1159. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1160. * descriptors using information in msdu_info
  1161. */
  1162. while (i < msdu_info->num_seg) {
  1163. /*
  1164. * Setup Tx descriptor for an MSDU, and MSDU extension
  1165. * descriptor
  1166. */
  1167. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1168. tx_q->desc_pool_id);
  1169. if (!tx_desc) {
  1170. if (msdu_info->frm_type == dp_tx_frm_me) {
  1171. dp_tx_me_free_buf(pdev,
  1172. (void *)(msdu_info->u.sg_info
  1173. .curr_seg->frags[0].vaddr));
  1174. }
  1175. goto done;
  1176. }
  1177. if (msdu_info->frm_type == dp_tx_frm_me) {
  1178. tx_desc->me_buffer =
  1179. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1180. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1181. }
  1182. if (is_cce_classified)
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1184. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1185. if (msdu_info->exception_fw) {
  1186. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1187. }
  1188. /*
  1189. * Enqueue the Tx MSDU descriptor to HW for transmit
  1190. */
  1191. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1192. htt_tcl_metadata, tx_q->ring_id, NULL);
  1193. if (status != QDF_STATUS_SUCCESS) {
  1194. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1195. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1196. __func__, tx_desc, tx_q->ring_id);
  1197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1198. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1199. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1200. goto done;
  1201. }
  1202. /*
  1203. * TODO
  1204. * if tso_info structure can be modified to have curr_seg
  1205. * as first element, following 2 blocks of code (for TSO and SG)
  1206. * can be combined into 1
  1207. */
  1208. /*
  1209. * For frames with multiple segments (TSO, ME), jump to next
  1210. * segment.
  1211. */
  1212. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1213. if (msdu_info->u.tso_info.curr_seg->next) {
  1214. msdu_info->u.tso_info.curr_seg =
  1215. msdu_info->u.tso_info.curr_seg->next;
  1216. /*
  1217. * If this is a jumbo nbuf, then increment the number of
  1218. * nbuf users for each additional segment of the msdu.
  1219. * This will ensure that the skb is freed only after
  1220. * receiving tx completion for all segments of an nbuf
  1221. */
  1222. qdf_nbuf_inc_users(nbuf);
  1223. /* Check with MCL if this is needed */
  1224. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1225. }
  1226. }
  1227. /*
  1228. * For Multicast-Unicast converted packets,
  1229. * each converted frame (for a client) is represented as
  1230. * 1 segment
  1231. */
  1232. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1233. (msdu_info->frm_type == dp_tx_frm_me)) {
  1234. if (msdu_info->u.sg_info.curr_seg->next) {
  1235. msdu_info->u.sg_info.curr_seg =
  1236. msdu_info->u.sg_info.curr_seg->next;
  1237. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1238. }
  1239. }
  1240. i++;
  1241. }
  1242. nbuf = NULL;
  1243. done:
  1244. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1245. hal_srng_access_end(soc->hal_soc, hal_srng);
  1246. hif_pm_runtime_put(soc->hif_handle);
  1247. } else {
  1248. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1249. }
  1250. return nbuf;
  1251. }
  1252. /**
  1253. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1254. * for SG frames
  1255. * @vdev: DP vdev handle
  1256. * @nbuf: skb
  1257. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1258. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1259. *
  1260. * Return: NULL on success,
  1261. * nbuf when it fails to send
  1262. */
  1263. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1264. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1265. {
  1266. uint32_t cur_frag, nr_frags;
  1267. qdf_dma_addr_t paddr;
  1268. struct dp_tx_sg_info_s *sg_info;
  1269. sg_info = &msdu_info->u.sg_info;
  1270. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1271. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1272. QDF_DMA_TO_DEVICE)) {
  1273. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1274. "dma map error\n");
  1275. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1276. qdf_nbuf_free(nbuf);
  1277. return NULL;
  1278. }
  1279. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1280. seg_info->frags[0].paddr_lo = paddr;
  1281. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1282. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1283. seg_info->frags[0].vaddr = (void *) nbuf;
  1284. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1285. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1286. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1288. "frag dma map error\n");
  1289. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1290. qdf_nbuf_free(nbuf);
  1291. return NULL;
  1292. }
  1293. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1294. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1295. seg_info->frags[cur_frag + 1].paddr_hi =
  1296. ((uint64_t) paddr) >> 32;
  1297. seg_info->frags[cur_frag + 1].len =
  1298. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1299. }
  1300. seg_info->frag_cnt = (cur_frag + 1);
  1301. seg_info->total_len = qdf_nbuf_len(nbuf);
  1302. seg_info->next = NULL;
  1303. sg_info->curr_seg = seg_info;
  1304. msdu_info->frm_type = dp_tx_frm_sg;
  1305. msdu_info->num_seg = 1;
  1306. return nbuf;
  1307. }
  1308. #ifdef MESH_MODE_SUPPORT
  1309. /**
  1310. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1311. and prepare msdu_info for mesh frames.
  1312. * @vdev: DP vdev handle
  1313. * @nbuf: skb
  1314. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1315. *
  1316. * Return: NULL on failure,
  1317. * nbuf when extracted successfully
  1318. */
  1319. static
  1320. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1321. struct dp_tx_msdu_info_s *msdu_info)
  1322. {
  1323. struct meta_hdr_s *mhdr;
  1324. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1325. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1326. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1327. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1328. msdu_info->exception_fw = 0;
  1329. goto remove_meta_hdr;
  1330. }
  1331. msdu_info->exception_fw = 1;
  1332. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1333. meta_data->host_tx_desc_pool = 1;
  1334. meta_data->update_peer_cache = 1;
  1335. meta_data->learning_frame = 1;
  1336. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1337. meta_data->power = mhdr->power;
  1338. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1339. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1340. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1341. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1342. meta_data->dyn_bw = 1;
  1343. meta_data->valid_pwr = 1;
  1344. meta_data->valid_mcs_mask = 1;
  1345. meta_data->valid_nss_mask = 1;
  1346. meta_data->valid_preamble_type = 1;
  1347. meta_data->valid_retries = 1;
  1348. meta_data->valid_bw_info = 1;
  1349. }
  1350. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1351. meta_data->encrypt_type = 0;
  1352. meta_data->valid_encrypt_type = 1;
  1353. meta_data->learning_frame = 0;
  1354. }
  1355. meta_data->valid_key_flags = 1;
  1356. meta_data->key_flags = (mhdr->keyix & 0x3);
  1357. remove_meta_hdr:
  1358. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1360. "qdf_nbuf_pull_head failed\n");
  1361. qdf_nbuf_free(nbuf);
  1362. return NULL;
  1363. }
  1364. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1365. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1366. else
  1367. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1368. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1369. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1370. " tid %d to_fw %d\n",
  1371. __func__, msdu_info->meta_data[0],
  1372. msdu_info->meta_data[1],
  1373. msdu_info->meta_data[2],
  1374. msdu_info->meta_data[3],
  1375. msdu_info->meta_data[4],
  1376. msdu_info->meta_data[5],
  1377. msdu_info->tid, msdu_info->exception_fw);
  1378. return nbuf;
  1379. }
  1380. #else
  1381. static
  1382. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1383. struct dp_tx_msdu_info_s *msdu_info)
  1384. {
  1385. return nbuf;
  1386. }
  1387. #endif
  1388. #ifdef DP_FEATURE_NAWDS_TX
  1389. /**
  1390. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1391. * @vdev: dp_vdev handle
  1392. * @nbuf: skb
  1393. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1394. * @tx_q: Tx queue to be used for this Tx frame
  1395. * @meta_data: Meta date for mesh
  1396. * @peer_id: peer_id of the peer in case of NAWDS frames
  1397. *
  1398. * return: NULL on success nbuf on failure
  1399. */
  1400. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1401. struct dp_tx_msdu_info_s *msdu_info)
  1402. {
  1403. struct dp_peer *peer = NULL;
  1404. struct dp_soc *soc = vdev->pdev->soc;
  1405. struct dp_ast_entry *ast_entry = NULL;
  1406. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1407. uint16_t peer_id = HTT_INVALID_PEER;
  1408. struct dp_peer *sa_peer = NULL;
  1409. qdf_nbuf_t nbuf_copy;
  1410. qdf_spin_lock_bh(&(soc->ast_lock));
  1411. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1412. if (ast_entry)
  1413. sa_peer = ast_entry->peer;
  1414. qdf_spin_unlock_bh(&(soc->ast_lock));
  1415. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1416. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1417. (peer->nawds_enabled)) {
  1418. if (sa_peer == peer) {
  1419. QDF_TRACE(QDF_MODULE_ID_DP,
  1420. QDF_TRACE_LEVEL_DEBUG,
  1421. " %s: broadcast multicast packet",
  1422. __func__);
  1423. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1424. continue;
  1425. }
  1426. nbuf_copy = qdf_nbuf_copy(nbuf);
  1427. if (!nbuf_copy) {
  1428. QDF_TRACE(QDF_MODULE_ID_DP,
  1429. QDF_TRACE_LEVEL_ERROR,
  1430. "nbuf copy failed");
  1431. }
  1432. peer_id = peer->peer_ids[0];
  1433. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1434. msdu_info, peer_id, NULL);
  1435. if (nbuf_copy != NULL) {
  1436. qdf_nbuf_free(nbuf_copy);
  1437. continue;
  1438. }
  1439. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1440. 1, qdf_nbuf_len(nbuf));
  1441. }
  1442. }
  1443. if (peer_id == HTT_INVALID_PEER)
  1444. return nbuf;
  1445. return NULL;
  1446. }
  1447. #endif
  1448. /**
  1449. * dp_check_exc_metadata() - Checks if parameters are valid
  1450. * @tx_exc - holds all exception path parameters
  1451. *
  1452. * Returns true when all the parameters are valid else false
  1453. *
  1454. */
  1455. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1456. {
  1457. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1458. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1459. tx_exc->sec_type > cdp_num_sec_types) {
  1460. return false;
  1461. }
  1462. return true;
  1463. }
  1464. /**
  1465. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1466. * @vap_dev: DP vdev handle
  1467. * @nbuf: skb
  1468. * @tx_exc_metadata: Handle that holds exception path meta data
  1469. *
  1470. * Entry point for Core Tx layer (DP_TX) invoked from
  1471. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1472. *
  1473. * Return: NULL on success,
  1474. * nbuf when it fails to send
  1475. */
  1476. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1477. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1478. {
  1479. struct ether_header *eh = NULL;
  1480. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1481. struct dp_tx_msdu_info_s msdu_info;
  1482. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1483. msdu_info.tid = tx_exc_metadata->tid;
  1484. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1486. "%s , skb %pM",
  1487. __func__, nbuf->data);
  1488. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1489. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1491. "Invalid parameters in exception path");
  1492. goto fail;
  1493. }
  1494. /* Basic sanity checks for unsupported packets */
  1495. /* MESH mode */
  1496. if (qdf_unlikely(vdev->mesh_vdev)) {
  1497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1498. "Mesh mode is not supported in exception path");
  1499. goto fail;
  1500. }
  1501. /* TSO or SG */
  1502. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1503. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1505. "TSO and SG are not supported in exception path");
  1506. goto fail;
  1507. }
  1508. /* RAW */
  1509. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1511. "Raw frame is not supported in exception path");
  1512. goto fail;
  1513. }
  1514. /* Mcast enhancement*/
  1515. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1516. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1518. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1519. }
  1520. }
  1521. /*
  1522. * Get HW Queue to use for this frame.
  1523. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1524. * dedicated for data and 1 for command.
  1525. * "queue_id" maps to one hardware ring.
  1526. * With each ring, we also associate a unique Tx descriptor pool
  1527. * to minimize lock contention for these resources.
  1528. */
  1529. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1530. /* Reset the control block */
  1531. qdf_nbuf_reset_ctxt(nbuf);
  1532. /* Single linear frame */
  1533. /*
  1534. * If nbuf is a simple linear frame, use send_single function to
  1535. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1536. * SRNG. There is no need to setup a MSDU extension descriptor.
  1537. */
  1538. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1539. tx_exc_metadata->peer_id, tx_exc_metadata);
  1540. return nbuf;
  1541. fail:
  1542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1543. "pkt send failed");
  1544. return nbuf;
  1545. }
  1546. /**
  1547. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1548. * @vap_dev: DP vdev handle
  1549. * @nbuf: skb
  1550. *
  1551. * Entry point for Core Tx layer (DP_TX) invoked from
  1552. * hard_start_xmit in OSIF/HDD
  1553. *
  1554. * Return: NULL on success,
  1555. * nbuf when it fails to send
  1556. */
  1557. #ifdef MESH_MODE_SUPPORT
  1558. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1559. {
  1560. struct meta_hdr_s *mhdr;
  1561. qdf_nbuf_t nbuf_mesh = NULL;
  1562. qdf_nbuf_t nbuf_clone = NULL;
  1563. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1564. uint8_t no_enc_frame = 0;
  1565. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1566. if (nbuf_mesh == NULL) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1568. "qdf_nbuf_unshare failed\n");
  1569. return nbuf;
  1570. }
  1571. nbuf = nbuf_mesh;
  1572. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1573. if ((vdev->sec_type != cdp_sec_type_none) &&
  1574. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1575. no_enc_frame = 1;
  1576. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1577. !no_enc_frame) {
  1578. nbuf_clone = qdf_nbuf_clone(nbuf);
  1579. if (nbuf_clone == NULL) {
  1580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1581. "qdf_nbuf_clone failed\n");
  1582. return nbuf;
  1583. }
  1584. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1585. }
  1586. if (nbuf_clone) {
  1587. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1588. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1589. } else
  1590. qdf_nbuf_free(nbuf_clone);
  1591. }
  1592. if (no_enc_frame)
  1593. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1594. else
  1595. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1596. nbuf = dp_tx_send(vap_dev, nbuf);
  1597. if ((nbuf == NULL) && no_enc_frame) {
  1598. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1599. }
  1600. return nbuf;
  1601. }
  1602. #else
  1603. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1604. {
  1605. return dp_tx_send(vap_dev, nbuf);
  1606. }
  1607. #endif
  1608. /**
  1609. * dp_tx_send() - Transmit a frame on a given VAP
  1610. * @vap_dev: DP vdev handle
  1611. * @nbuf: skb
  1612. *
  1613. * Entry point for Core Tx layer (DP_TX) invoked from
  1614. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1615. * cases
  1616. *
  1617. * Return: NULL on success,
  1618. * nbuf when it fails to send
  1619. */
  1620. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1621. {
  1622. struct ether_header *eh = NULL;
  1623. struct dp_tx_msdu_info_s msdu_info;
  1624. struct dp_tx_seg_info_s seg_info;
  1625. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1626. uint16_t peer_id = HTT_INVALID_PEER;
  1627. qdf_nbuf_t nbuf_mesh = NULL;
  1628. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1629. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1630. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1632. "%s , skb %pM",
  1633. __func__, nbuf->data);
  1634. /*
  1635. * Set Default Host TID value to invalid TID
  1636. * (TID override disabled)
  1637. */
  1638. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1639. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1640. if (qdf_unlikely(vdev->mesh_vdev)) {
  1641. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1642. &msdu_info);
  1643. if (nbuf_mesh == NULL) {
  1644. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1645. "Extracting mesh metadata failed\n");
  1646. return nbuf;
  1647. }
  1648. nbuf = nbuf_mesh;
  1649. }
  1650. /*
  1651. * Get HW Queue to use for this frame.
  1652. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1653. * dedicated for data and 1 for command.
  1654. * "queue_id" maps to one hardware ring.
  1655. * With each ring, we also associate a unique Tx descriptor pool
  1656. * to minimize lock contention for these resources.
  1657. */
  1658. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1659. /*
  1660. * TCL H/W supports 2 DSCP-TID mapping tables.
  1661. * Table 1 - Default DSCP-TID mapping table
  1662. * Table 2 - 1 DSCP-TID override table
  1663. *
  1664. * If we need a different DSCP-TID mapping for this vap,
  1665. * call tid_classify to extract DSCP/ToS from frame and
  1666. * map to a TID and store in msdu_info. This is later used
  1667. * to fill in TCL Input descriptor (per-packet TID override).
  1668. */
  1669. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1670. /* Reset the control block */
  1671. qdf_nbuf_reset_ctxt(nbuf);
  1672. /*
  1673. * Classify the frame and call corresponding
  1674. * "prepare" function which extracts the segment (TSO)
  1675. * and fragmentation information (for TSO , SG, ME, or Raw)
  1676. * into MSDU_INFO structure which is later used to fill
  1677. * SW and HW descriptors.
  1678. */
  1679. if (qdf_nbuf_is_tso(nbuf)) {
  1680. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1681. "%s TSO frame %pK\n", __func__, vdev);
  1682. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1683. qdf_nbuf_len(nbuf));
  1684. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1685. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1686. return nbuf;
  1687. }
  1688. goto send_multiple;
  1689. }
  1690. /* SG */
  1691. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1692. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1693. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1694. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1695. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1696. qdf_nbuf_len(nbuf));
  1697. goto send_multiple;
  1698. }
  1699. #ifdef ATH_SUPPORT_IQUE
  1700. /* Mcast to Ucast Conversion*/
  1701. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1702. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1703. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1704. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1705. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1706. DP_STATS_INC_PKT(vdev,
  1707. tx_i.mcast_en.mcast_pkt, 1,
  1708. qdf_nbuf_len(nbuf));
  1709. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1710. QDF_STATUS_SUCCESS) {
  1711. return NULL;
  1712. }
  1713. }
  1714. }
  1715. #endif
  1716. /* RAW */
  1717. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1718. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1719. if (nbuf == NULL)
  1720. return NULL;
  1721. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1722. "%s Raw frame %pK\n", __func__, vdev);
  1723. goto send_multiple;
  1724. }
  1725. /* Single linear frame */
  1726. /*
  1727. * If nbuf is a simple linear frame, use send_single function to
  1728. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1729. * SRNG. There is no need to setup a MSDU extension descriptor.
  1730. */
  1731. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1732. return nbuf;
  1733. send_multiple:
  1734. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1735. return nbuf;
  1736. }
  1737. /**
  1738. * dp_tx_reinject_handler() - Tx Reinject Handler
  1739. * @tx_desc: software descriptor head pointer
  1740. * @status : Tx completion status from HTT descriptor
  1741. *
  1742. * This function reinjects frames back to Target.
  1743. * Todo - Host queue needs to be added
  1744. *
  1745. * Return: none
  1746. */
  1747. static
  1748. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1749. {
  1750. struct dp_vdev *vdev;
  1751. struct dp_peer *peer = NULL;
  1752. uint32_t peer_id = HTT_INVALID_PEER;
  1753. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1754. qdf_nbuf_t nbuf_copy = NULL;
  1755. struct dp_tx_msdu_info_s msdu_info;
  1756. struct dp_peer *sa_peer = NULL;
  1757. struct dp_ast_entry *ast_entry = NULL;
  1758. struct dp_soc *soc = NULL;
  1759. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1760. #ifdef WDS_VENDOR_EXTENSION
  1761. int is_mcast = 0, is_ucast = 0;
  1762. int num_peers_3addr = 0;
  1763. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1764. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1765. #endif
  1766. vdev = tx_desc->vdev;
  1767. soc = vdev->pdev->soc;
  1768. qdf_assert(vdev);
  1769. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1770. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1772. "%s Tx reinject path\n", __func__);
  1773. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1774. qdf_nbuf_len(tx_desc->nbuf));
  1775. qdf_spin_lock_bh(&(soc->ast_lock));
  1776. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1777. if (ast_entry)
  1778. sa_peer = ast_entry->peer;
  1779. qdf_spin_unlock_bh(&(soc->ast_lock));
  1780. #ifdef WDS_VENDOR_EXTENSION
  1781. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1782. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1783. } else {
  1784. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1785. }
  1786. is_ucast = !is_mcast;
  1787. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1788. if (peer->bss_peer)
  1789. continue;
  1790. /* Detect wds peers that use 3-addr framing for mcast.
  1791. * if there are any, the bss_peer is used to send the
  1792. * the mcast frame using 3-addr format. all wds enabled
  1793. * peers that use 4-addr framing for mcast frames will
  1794. * be duplicated and sent as 4-addr frames below.
  1795. */
  1796. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1797. num_peers_3addr = 1;
  1798. break;
  1799. }
  1800. }
  1801. #endif
  1802. if (qdf_unlikely(vdev->mesh_vdev)) {
  1803. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1804. } else {
  1805. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1806. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1807. #ifdef WDS_VENDOR_EXTENSION
  1808. /*
  1809. * . if 3-addr STA, then send on BSS Peer
  1810. * . if Peer WDS enabled and accept 4-addr mcast,
  1811. * send mcast on that peer only
  1812. * . if Peer WDS enabled and accept 4-addr ucast,
  1813. * send ucast on that peer only
  1814. */
  1815. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1816. (peer->wds_enabled &&
  1817. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1818. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1819. #else
  1820. ((peer->bss_peer &&
  1821. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1822. peer->nawds_enabled)) {
  1823. #endif
  1824. peer_id = DP_INVALID_PEER;
  1825. if (peer->nawds_enabled) {
  1826. peer_id = peer->peer_ids[0];
  1827. if (sa_peer == peer) {
  1828. QDF_TRACE(
  1829. QDF_MODULE_ID_DP,
  1830. QDF_TRACE_LEVEL_DEBUG,
  1831. " %s: multicast packet",
  1832. __func__);
  1833. DP_STATS_INC(peer,
  1834. tx.nawds_mcast_drop, 1);
  1835. continue;
  1836. }
  1837. }
  1838. nbuf_copy = qdf_nbuf_copy(nbuf);
  1839. if (!nbuf_copy) {
  1840. QDF_TRACE(QDF_MODULE_ID_DP,
  1841. QDF_TRACE_LEVEL_DEBUG,
  1842. FL("nbuf copy failed"));
  1843. break;
  1844. }
  1845. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1846. nbuf_copy,
  1847. &msdu_info,
  1848. peer_id,
  1849. NULL);
  1850. if (nbuf_copy) {
  1851. QDF_TRACE(QDF_MODULE_ID_DP,
  1852. QDF_TRACE_LEVEL_DEBUG,
  1853. FL("pkt send failed"));
  1854. qdf_nbuf_free(nbuf_copy);
  1855. } else {
  1856. if (peer_id != DP_INVALID_PEER)
  1857. DP_STATS_INC_PKT(peer,
  1858. tx.nawds_mcast,
  1859. 1, qdf_nbuf_len(nbuf));
  1860. }
  1861. }
  1862. }
  1863. }
  1864. if (vdev->nawds_enabled) {
  1865. peer_id = DP_INVALID_PEER;
  1866. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1867. 1, qdf_nbuf_len(nbuf));
  1868. nbuf = dp_tx_send_msdu_single(vdev,
  1869. nbuf,
  1870. &msdu_info,
  1871. peer_id, NULL);
  1872. if (nbuf) {
  1873. QDF_TRACE(QDF_MODULE_ID_DP,
  1874. QDF_TRACE_LEVEL_DEBUG,
  1875. FL("pkt send failed"));
  1876. qdf_nbuf_free(nbuf);
  1877. }
  1878. } else
  1879. qdf_nbuf_free(nbuf);
  1880. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1881. }
  1882. /**
  1883. * dp_tx_inspect_handler() - Tx Inspect Handler
  1884. * @tx_desc: software descriptor head pointer
  1885. * @status : Tx completion status from HTT descriptor
  1886. *
  1887. * Handles Tx frames sent back to Host for inspection
  1888. * (ProxyARP)
  1889. *
  1890. * Return: none
  1891. */
  1892. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1893. {
  1894. struct dp_soc *soc;
  1895. struct dp_pdev *pdev = tx_desc->pdev;
  1896. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1897. "%s Tx inspect path\n",
  1898. __func__);
  1899. qdf_assert(pdev);
  1900. soc = pdev->soc;
  1901. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1902. qdf_nbuf_len(tx_desc->nbuf));
  1903. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1904. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1905. }
  1906. #ifdef FEATURE_PERPKT_INFO
  1907. /**
  1908. * dp_get_completion_indication_for_stack() - send completion to stack
  1909. * @soc : dp_soc handle
  1910. * @pdev: dp_pdev handle
  1911. * @peer_id: peer_id of the peer for which completion came
  1912. * @ppdu_id: ppdu_id
  1913. * @first_msdu: first msdu
  1914. * @last_msdu: last msdu
  1915. * @netbuf: Buffer pointer for free
  1916. *
  1917. * This function is used for indication whether buffer needs to be
  1918. * send to stack for free or not
  1919. */
  1920. QDF_STATUS
  1921. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1922. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1923. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1924. {
  1925. struct tx_capture_hdr *ppdu_hdr;
  1926. struct dp_peer *peer = NULL;
  1927. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1928. return QDF_STATUS_E_NOSUPPORT;
  1929. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1930. dp_peer_find_by_id(soc, peer_id);
  1931. if (!peer) {
  1932. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1933. FL("Peer Invalid"));
  1934. return QDF_STATUS_E_INVAL;
  1935. }
  1936. if (pdev->mcopy_mode) {
  1937. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1938. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1939. return QDF_STATUS_E_INVAL;
  1940. }
  1941. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1942. pdev->m_copy_id.tx_peer_id = peer_id;
  1943. }
  1944. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1945. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1946. FL("No headroom"));
  1947. return QDF_STATUS_E_NOMEM;
  1948. }
  1949. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1950. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1951. IEEE80211_ADDR_LEN);
  1952. ppdu_hdr->ppdu_id = ppdu_id;
  1953. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1954. IEEE80211_ADDR_LEN);
  1955. ppdu_hdr->peer_id = peer_id;
  1956. ppdu_hdr->first_msdu = first_msdu;
  1957. ppdu_hdr->last_msdu = last_msdu;
  1958. return QDF_STATUS_SUCCESS;
  1959. }
  1960. /**
  1961. * dp_send_completion_to_stack() - send completion to stack
  1962. * @soc : dp_soc handle
  1963. * @pdev: dp_pdev handle
  1964. * @peer_id: peer_id of the peer for which completion came
  1965. * @ppdu_id: ppdu_id
  1966. * @netbuf: Buffer pointer for free
  1967. *
  1968. * This function is used to send completion to stack
  1969. * to free buffer
  1970. */
  1971. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1972. uint16_t peer_id, uint32_t ppdu_id,
  1973. qdf_nbuf_t netbuf)
  1974. {
  1975. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1976. netbuf, peer_id,
  1977. WDI_NO_VAL, pdev->pdev_id);
  1978. }
  1979. #else
  1980. static QDF_STATUS
  1981. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1982. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1983. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1984. {
  1985. return QDF_STATUS_E_NOSUPPORT;
  1986. }
  1987. static void
  1988. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1989. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1990. {
  1991. }
  1992. #endif
  1993. /**
  1994. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1995. * @soc: Soc handle
  1996. * @desc: software Tx descriptor to be processed
  1997. *
  1998. * Return: none
  1999. */
  2000. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2001. struct dp_tx_desc_s *desc)
  2002. {
  2003. struct dp_vdev *vdev = desc->vdev;
  2004. qdf_nbuf_t nbuf = desc->nbuf;
  2005. /* If it is TDLS mgmt, don't unmap or free the frame */
  2006. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2007. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2008. /* 0 : MSDU buffer, 1 : MLE */
  2009. if (desc->msdu_ext_desc) {
  2010. /* TSO free */
  2011. if (hal_tx_ext_desc_get_tso_enable(
  2012. desc->msdu_ext_desc->vaddr)) {
  2013. /* If remaining number of segment is 0
  2014. * actual TSO may unmap and free */
  2015. if (qdf_nbuf_get_users(nbuf) == 1)
  2016. __qdf_nbuf_unmap_single(soc->osdev,
  2017. nbuf,
  2018. QDF_DMA_TO_DEVICE);
  2019. qdf_nbuf_free(nbuf);
  2020. return;
  2021. }
  2022. }
  2023. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2024. if (qdf_likely(!vdev->mesh_vdev))
  2025. qdf_nbuf_free(nbuf);
  2026. else {
  2027. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2028. qdf_nbuf_free(nbuf);
  2029. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2030. } else
  2031. vdev->osif_tx_free_ext((nbuf));
  2032. }
  2033. }
  2034. /**
  2035. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2036. * @vdev: pointer to dp dev handler
  2037. * @status : Tx completion status from HTT descriptor
  2038. *
  2039. * Handles MEC notify event sent from fw to Host
  2040. *
  2041. * Return: none
  2042. */
  2043. #ifdef FEATURE_WDS
  2044. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2045. {
  2046. struct dp_soc *soc;
  2047. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2048. struct dp_peer *peer;
  2049. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2050. if (!vdev->wds_enabled)
  2051. return;
  2052. soc = vdev->pdev->soc;
  2053. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2054. peer = TAILQ_FIRST(&vdev->peer_list);
  2055. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2056. if (!peer) {
  2057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2058. FL("peer is NULL"));
  2059. return;
  2060. }
  2061. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2062. "%s Tx MEC Handler\n",
  2063. __func__);
  2064. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2065. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2066. status[(DP_MAC_ADDR_LEN - 2) + i];
  2067. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2068. dp_peer_add_ast(soc,
  2069. peer,
  2070. mac_addr,
  2071. CDP_TXRX_AST_TYPE_MEC,
  2072. flags);
  2073. }
  2074. #endif
  2075. /**
  2076. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2077. * @tx_desc: software descriptor head pointer
  2078. * @status : Tx completion status from HTT descriptor
  2079. *
  2080. * This function will process HTT Tx indication messages from Target
  2081. *
  2082. * Return: none
  2083. */
  2084. static
  2085. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2086. {
  2087. uint8_t tx_status;
  2088. struct dp_pdev *pdev;
  2089. struct dp_vdev *vdev;
  2090. struct dp_soc *soc;
  2091. uint32_t *htt_status_word = (uint32_t *) status;
  2092. qdf_assert(tx_desc->pdev);
  2093. pdev = tx_desc->pdev;
  2094. vdev = tx_desc->vdev;
  2095. soc = pdev->soc;
  2096. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2097. switch (tx_status) {
  2098. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2099. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2100. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2101. {
  2102. dp_tx_comp_free_buf(soc, tx_desc);
  2103. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2104. break;
  2105. }
  2106. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2107. {
  2108. dp_tx_reinject_handler(tx_desc, status);
  2109. break;
  2110. }
  2111. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2112. {
  2113. dp_tx_inspect_handler(tx_desc, status);
  2114. break;
  2115. }
  2116. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2117. {
  2118. dp_tx_mec_handler(vdev, status);
  2119. break;
  2120. }
  2121. default:
  2122. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2123. "%s Invalid HTT tx_status %d\n",
  2124. __func__, tx_status);
  2125. break;
  2126. }
  2127. }
  2128. #ifdef MESH_MODE_SUPPORT
  2129. /**
  2130. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2131. * in mesh meta header
  2132. * @tx_desc: software descriptor head pointer
  2133. * @ts: pointer to tx completion stats
  2134. * Return: none
  2135. */
  2136. static
  2137. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2138. struct hal_tx_completion_status *ts)
  2139. {
  2140. struct meta_hdr_s *mhdr;
  2141. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2142. if (!tx_desc->msdu_ext_desc) {
  2143. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2144. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2145. "netbuf %pK offset %d\n",
  2146. netbuf, tx_desc->pkt_offset);
  2147. return;
  2148. }
  2149. }
  2150. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2151. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2152. "netbuf %pK offset %d\n", netbuf,
  2153. sizeof(struct meta_hdr_s));
  2154. return;
  2155. }
  2156. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2157. mhdr->rssi = ts->ack_frame_rssi;
  2158. mhdr->channel = tx_desc->pdev->operating_channel;
  2159. }
  2160. #else
  2161. static
  2162. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2163. struct hal_tx_completion_status *ts)
  2164. {
  2165. }
  2166. #endif
  2167. /**
  2168. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2169. * @peer: Handle to DP peer
  2170. * @ts: pointer to HAL Tx completion stats
  2171. * @length: MSDU length
  2172. *
  2173. * Return: None
  2174. */
  2175. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2176. struct hal_tx_completion_status *ts, uint32_t length)
  2177. {
  2178. struct dp_pdev *pdev = peer->vdev->pdev;
  2179. struct dp_soc *soc = pdev->soc;
  2180. uint8_t mcs, pkt_type;
  2181. mcs = ts->mcs;
  2182. pkt_type = ts->pkt_type;
  2183. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2184. return;
  2185. if (peer->bss_peer) {
  2186. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2187. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2188. } else {
  2189. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2190. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2191. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2192. }
  2193. }
  2194. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2195. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2196. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2197. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2198. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2199. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2200. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2201. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2202. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2203. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2204. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2205. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2206. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2207. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2208. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2209. return;
  2210. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2211. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2212. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2213. if (!(soc->process_tx_status))
  2214. return;
  2215. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2216. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2217. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2218. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2219. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2220. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2221. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2222. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2223. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2224. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2225. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2226. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2227. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2228. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2229. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2230. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2231. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2232. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2233. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2234. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2235. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2236. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2237. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2238. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2239. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2240. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2241. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2242. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2243. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2244. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2245. &peer->stats, ts->peer_id,
  2246. UPDATE_PEER_STATS);
  2247. }
  2248. }
  2249. /**
  2250. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2251. * @tx_desc: software descriptor head pointer
  2252. * @length: packet length
  2253. *
  2254. * Return: none
  2255. */
  2256. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2257. uint32_t length)
  2258. {
  2259. struct hal_tx_completion_status ts;
  2260. struct dp_soc *soc = NULL;
  2261. struct dp_vdev *vdev = tx_desc->vdev;
  2262. struct dp_peer *peer = NULL;
  2263. struct ether_header *eh =
  2264. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2265. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2267. "-------------------- \n"
  2268. "Tx Completion Stats: \n"
  2269. "-------------------- \n"
  2270. "ack_frame_rssi = %d \n"
  2271. "first_msdu = %d \n"
  2272. "last_msdu = %d \n"
  2273. "msdu_part_of_amsdu = %d \n"
  2274. "rate_stats valid = %d \n"
  2275. "bw = %d \n"
  2276. "pkt_type = %d \n"
  2277. "stbc = %d \n"
  2278. "ldpc = %d \n"
  2279. "sgi = %d \n"
  2280. "mcs = %d \n"
  2281. "ofdma = %d \n"
  2282. "tones_in_ru = %d \n"
  2283. "tsf = %d \n"
  2284. "ppdu_id = %d \n"
  2285. "transmit_cnt = %d \n"
  2286. "tid = %d \n"
  2287. "peer_id = %d \n",
  2288. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2289. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2290. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2291. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2292. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2293. ts.peer_id);
  2294. if (!vdev) {
  2295. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2296. "invalid vdev");
  2297. goto out;
  2298. }
  2299. soc = vdev->pdev->soc;
  2300. /* Update SoC level stats */
  2301. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2302. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2303. /* Update per-packet stats */
  2304. if (qdf_unlikely(vdev->mesh_vdev) &&
  2305. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2306. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2307. /* Update peer level stats */
  2308. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2309. if (!peer) {
  2310. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2311. "invalid peer");
  2312. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2313. goto out;
  2314. }
  2315. if (qdf_likely(peer->vdev->tx_encap_type ==
  2316. htt_cmn_pkt_type_ethernet)) {
  2317. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2318. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2319. }
  2320. dp_tx_update_peer_stats(peer, &ts, length);
  2321. out:
  2322. return;
  2323. }
  2324. /**
  2325. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2326. * @soc: core txrx main context
  2327. * @comp_head: software descriptor head pointer
  2328. *
  2329. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2330. * and release the software descriptors after processing is complete
  2331. *
  2332. * Return: none
  2333. */
  2334. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2335. struct dp_tx_desc_s *comp_head)
  2336. {
  2337. struct dp_tx_desc_s *desc;
  2338. struct dp_tx_desc_s *next;
  2339. struct hal_tx_completion_status ts = {0};
  2340. uint32_t length;
  2341. struct dp_peer *peer;
  2342. DP_HIST_INIT();
  2343. desc = comp_head;
  2344. while (desc) {
  2345. hal_tx_comp_get_status(&desc->comp, &ts);
  2346. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2347. length = qdf_nbuf_len(desc->nbuf);
  2348. dp_tx_comp_process_tx_status(desc, length);
  2349. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2350. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2351. desc->pdev, ts.peer_id, ts.ppdu_id,
  2352. ts.first_msdu, ts.last_msdu,
  2353. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2354. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2355. QDF_DMA_TO_DEVICE);
  2356. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2357. ts.ppdu_id, desc->nbuf);
  2358. } else {
  2359. dp_tx_comp_free_buf(soc, desc);
  2360. }
  2361. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2362. next = desc->next;
  2363. dp_tx_desc_release(desc, desc->pool_id);
  2364. desc = next;
  2365. }
  2366. DP_TX_HIST_STATS_PER_PDEV();
  2367. }
  2368. /**
  2369. * dp_tx_comp_handler() - Tx completion handler
  2370. * @soc: core txrx main context
  2371. * @ring_id: completion ring id
  2372. * @quota: No. of packets/descriptors that can be serviced in one loop
  2373. *
  2374. * This function will collect hardware release ring element contents and
  2375. * handle descriptor contents. Based on contents, free packet or handle error
  2376. * conditions
  2377. *
  2378. * Return: none
  2379. */
  2380. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2381. {
  2382. void *tx_comp_hal_desc;
  2383. uint8_t buffer_src;
  2384. uint8_t pool_id;
  2385. uint32_t tx_desc_id;
  2386. struct dp_tx_desc_s *tx_desc = NULL;
  2387. struct dp_tx_desc_s *head_desc = NULL;
  2388. struct dp_tx_desc_s *tail_desc = NULL;
  2389. uint32_t num_processed;
  2390. uint32_t count;
  2391. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2392. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2393. "%s %d : HAL RING Access Failed -- %pK\n",
  2394. __func__, __LINE__, hal_srng);
  2395. return 0;
  2396. }
  2397. num_processed = 0;
  2398. count = 0;
  2399. /* Find head descriptor from completion ring */
  2400. while (qdf_likely(tx_comp_hal_desc =
  2401. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2402. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2403. /* If this buffer was not released by TQM or FW, then it is not
  2404. * Tx completion indication, assert */
  2405. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2406. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2407. QDF_TRACE(QDF_MODULE_ID_DP,
  2408. QDF_TRACE_LEVEL_FATAL,
  2409. "Tx comp release_src != TQM | FW");
  2410. qdf_assert_always(0);
  2411. }
  2412. /* Get descriptor id */
  2413. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2414. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2415. DP_TX_DESC_ID_POOL_OS;
  2416. /* Pool ID is out of limit. Error */
  2417. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2418. soc->wlan_cfg_ctx)) {
  2419. QDF_TRACE(QDF_MODULE_ID_DP,
  2420. QDF_TRACE_LEVEL_FATAL,
  2421. "Tx Comp pool id %d not valid",
  2422. pool_id);
  2423. qdf_assert_always(0);
  2424. }
  2425. /* Find Tx descriptor */
  2426. tx_desc = dp_tx_desc_find(soc, pool_id,
  2427. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2428. DP_TX_DESC_ID_PAGE_OS,
  2429. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2430. DP_TX_DESC_ID_OFFSET_OS);
  2431. /*
  2432. * If the release source is FW, process the HTT status
  2433. */
  2434. if (qdf_unlikely(buffer_src ==
  2435. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2436. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2437. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2438. htt_tx_status);
  2439. dp_tx_process_htt_completion(tx_desc,
  2440. htt_tx_status);
  2441. } else {
  2442. /* Pool id is not matching. Error */
  2443. if (tx_desc->pool_id != pool_id) {
  2444. QDF_TRACE(QDF_MODULE_ID_DP,
  2445. QDF_TRACE_LEVEL_FATAL,
  2446. "Tx Comp pool id %d not matched %d",
  2447. pool_id, tx_desc->pool_id);
  2448. qdf_assert_always(0);
  2449. }
  2450. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2451. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2452. QDF_TRACE(QDF_MODULE_ID_DP,
  2453. QDF_TRACE_LEVEL_FATAL,
  2454. "Txdesc invalid, flgs = %x,id = %d",
  2455. tx_desc->flags, tx_desc_id);
  2456. qdf_assert_always(0);
  2457. }
  2458. /* First ring descriptor on the cycle */
  2459. if (!head_desc) {
  2460. head_desc = tx_desc;
  2461. tail_desc = tx_desc;
  2462. }
  2463. tail_desc->next = tx_desc;
  2464. tx_desc->next = NULL;
  2465. tail_desc = tx_desc;
  2466. /* Collect hw completion contents */
  2467. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2468. &tx_desc->comp, 1);
  2469. }
  2470. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2471. /* Decrement PM usage count if the packet has been sent.*/
  2472. hif_pm_runtime_put(soc->hif_handle);
  2473. /*
  2474. * Processed packet count is more than given quota
  2475. * stop to processing
  2476. */
  2477. if ((num_processed >= quota))
  2478. break;
  2479. count++;
  2480. }
  2481. hal_srng_access_end(soc->hal_soc, hal_srng);
  2482. /* Process the reaped descriptors */
  2483. if (head_desc)
  2484. dp_tx_comp_process_desc(soc, head_desc);
  2485. return num_processed;
  2486. }
  2487. #ifdef CONVERGED_TDLS_ENABLE
  2488. /**
  2489. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2490. *
  2491. * @data_vdev - which vdev should transmit the tx data frames
  2492. * @tx_spec - what non-standard handling to apply to the tx data frames
  2493. * @msdu_list - NULL-terminated list of tx MSDUs
  2494. *
  2495. * Return: NULL on success,
  2496. * nbuf when it fails to send
  2497. */
  2498. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2499. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2500. {
  2501. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2502. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2503. vdev->is_tdls_frame = true;
  2504. return dp_tx_send(vdev_handle, msdu_list);
  2505. }
  2506. #endif
  2507. /**
  2508. * dp_tx_vdev_attach() - attach vdev to dp tx
  2509. * @vdev: virtual device instance
  2510. *
  2511. * Return: QDF_STATUS_SUCCESS: success
  2512. * QDF_STATUS_E_RESOURCES: Error return
  2513. */
  2514. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2515. {
  2516. /*
  2517. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2518. */
  2519. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2520. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2521. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2522. vdev->vdev_id);
  2523. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2524. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2525. /*
  2526. * Set HTT Extension Valid bit to 0 by default
  2527. */
  2528. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2529. dp_tx_vdev_update_search_flags(vdev);
  2530. return QDF_STATUS_SUCCESS;
  2531. }
  2532. /**
  2533. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2534. * @vdev: virtual device instance
  2535. *
  2536. * Return: void
  2537. *
  2538. */
  2539. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2540. {
  2541. /*
  2542. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2543. * for TDLS link
  2544. *
  2545. * Enable AddrY (SA based search) only for non-WDS STA and
  2546. * ProxySTA VAP modes.
  2547. *
  2548. * In all other VAP modes, only DA based search should be
  2549. * enabled
  2550. */
  2551. if (vdev->opmode == wlan_op_mode_sta &&
  2552. vdev->tdls_link_connected)
  2553. vdev->hal_desc_addr_search_flags =
  2554. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2555. else if ((vdev->opmode == wlan_op_mode_sta &&
  2556. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2557. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2558. else
  2559. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2560. }
  2561. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2562. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2563. {
  2564. }
  2565. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2566. /* dp_tx_desc_flush() - release resources associated
  2567. * to tx_desc
  2568. * @vdev: virtual device instance
  2569. *
  2570. * This function will free all outstanding Tx buffers,
  2571. * including ME buffer for which either free during
  2572. * completion didn't happened or completion is not
  2573. * received.
  2574. */
  2575. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2576. {
  2577. uint8_t i, num_pool;
  2578. uint32_t j;
  2579. uint32_t num_desc;
  2580. struct dp_soc *soc = vdev->pdev->soc;
  2581. struct dp_tx_desc_s *tx_desc = NULL;
  2582. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2583. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2584. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2585. for (i = 0; i < num_pool; i++) {
  2586. for (j = 0; j < num_desc; j++) {
  2587. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2588. if (tx_desc_pool &&
  2589. tx_desc_pool->desc_pages.cacheable_pages) {
  2590. tx_desc = dp_tx_desc_find(soc, i,
  2591. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2592. DP_TX_DESC_ID_PAGE_OS,
  2593. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2594. DP_TX_DESC_ID_OFFSET_OS);
  2595. if (tx_desc && (tx_desc->vdev == vdev) &&
  2596. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2597. dp_tx_comp_free_buf(soc, tx_desc);
  2598. dp_tx_desc_release(tx_desc, i);
  2599. }
  2600. }
  2601. }
  2602. }
  2603. }
  2604. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2605. /**
  2606. * dp_tx_vdev_detach() - detach vdev from dp tx
  2607. * @vdev: virtual device instance
  2608. *
  2609. * Return: QDF_STATUS_SUCCESS: success
  2610. * QDF_STATUS_E_RESOURCES: Error return
  2611. */
  2612. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2613. {
  2614. dp_tx_desc_flush(vdev);
  2615. return QDF_STATUS_SUCCESS;
  2616. }
  2617. /**
  2618. * dp_tx_pdev_attach() - attach pdev to dp tx
  2619. * @pdev: physical device instance
  2620. *
  2621. * Return: QDF_STATUS_SUCCESS: success
  2622. * QDF_STATUS_E_RESOURCES: Error return
  2623. */
  2624. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2625. {
  2626. struct dp_soc *soc = pdev->soc;
  2627. /* Initialize Flow control counters */
  2628. qdf_atomic_init(&pdev->num_tx_exception);
  2629. qdf_atomic_init(&pdev->num_tx_outstanding);
  2630. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2631. /* Initialize descriptors in TCL Ring */
  2632. hal_tx_init_data_ring(soc->hal_soc,
  2633. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2634. }
  2635. return QDF_STATUS_SUCCESS;
  2636. }
  2637. /**
  2638. * dp_tx_pdev_detach() - detach pdev from dp tx
  2639. * @pdev: physical device instance
  2640. *
  2641. * Return: QDF_STATUS_SUCCESS: success
  2642. * QDF_STATUS_E_RESOURCES: Error return
  2643. */
  2644. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2645. {
  2646. dp_tx_me_exit(pdev);
  2647. return QDF_STATUS_SUCCESS;
  2648. }
  2649. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2650. /* Pools will be allocated dynamically */
  2651. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2652. int num_desc)
  2653. {
  2654. uint8_t i;
  2655. for (i = 0; i < num_pool; i++) {
  2656. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2657. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2658. }
  2659. return 0;
  2660. }
  2661. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2662. {
  2663. uint8_t i;
  2664. for (i = 0; i < num_pool; i++)
  2665. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2666. }
  2667. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2668. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2669. int num_desc)
  2670. {
  2671. uint8_t i;
  2672. /* Allocate software Tx descriptor pools */
  2673. for (i = 0; i < num_pool; i++) {
  2674. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2675. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2676. "%s Tx Desc Pool alloc %d failed %pK\n",
  2677. __func__, i, soc);
  2678. return ENOMEM;
  2679. }
  2680. }
  2681. return 0;
  2682. }
  2683. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2684. {
  2685. uint8_t i;
  2686. for (i = 0; i < num_pool; i++) {
  2687. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2688. if (dp_tx_desc_pool_free(soc, i)) {
  2689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2690. "%s Tx Desc Pool Free failed\n", __func__);
  2691. }
  2692. }
  2693. }
  2694. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2695. /**
  2696. * dp_tx_soc_detach() - detach soc from dp tx
  2697. * @soc: core txrx main context
  2698. *
  2699. * This function will detach dp tx into main device context
  2700. * will free dp tx resource and initialize resources
  2701. *
  2702. * Return: QDF_STATUS_SUCCESS: success
  2703. * QDF_STATUS_E_RESOURCES: Error return
  2704. */
  2705. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2706. {
  2707. uint8_t num_pool;
  2708. uint16_t num_desc;
  2709. uint16_t num_ext_desc;
  2710. uint8_t i;
  2711. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2712. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2713. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2714. dp_tx_flow_control_deinit(soc);
  2715. dp_tx_delete_static_pools(soc, num_pool);
  2716. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2717. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2718. __func__, num_pool, num_desc);
  2719. for (i = 0; i < num_pool; i++) {
  2720. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2721. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2722. "%s Tx Ext Desc Pool Free failed\n",
  2723. __func__);
  2724. return QDF_STATUS_E_RESOURCES;
  2725. }
  2726. }
  2727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2728. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2729. __func__, num_pool, num_ext_desc);
  2730. for (i = 0; i < num_pool; i++) {
  2731. dp_tx_tso_desc_pool_free(soc, i);
  2732. }
  2733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2734. "%s TSO Desc Pool %d Free descs = %d\n",
  2735. __func__, num_pool, num_desc);
  2736. for (i = 0; i < num_pool; i++)
  2737. dp_tx_tso_num_seg_pool_free(soc, i);
  2738. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2739. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2740. __func__, num_pool, num_desc);
  2741. return QDF_STATUS_SUCCESS;
  2742. }
  2743. /**
  2744. * dp_tx_soc_attach() - attach soc to dp tx
  2745. * @soc: core txrx main context
  2746. *
  2747. * This function will attach dp tx into main device context
  2748. * will allocate dp tx resource and initialize resources
  2749. *
  2750. * Return: QDF_STATUS_SUCCESS: success
  2751. * QDF_STATUS_E_RESOURCES: Error return
  2752. */
  2753. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2754. {
  2755. uint8_t i;
  2756. uint8_t num_pool;
  2757. uint32_t num_desc;
  2758. uint32_t num_ext_desc;
  2759. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2760. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2761. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2762. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2763. goto fail;
  2764. dp_tx_flow_control_init(soc);
  2765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2766. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2767. __func__, num_pool, num_desc);
  2768. /* Allocate extension tx descriptor pools */
  2769. for (i = 0; i < num_pool; i++) {
  2770. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2772. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2773. i, soc);
  2774. goto fail;
  2775. }
  2776. }
  2777. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2778. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2779. __func__, num_pool, num_ext_desc);
  2780. for (i = 0; i < num_pool; i++) {
  2781. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2783. "TSO Desc Pool alloc %d failed %pK\n",
  2784. i, soc);
  2785. goto fail;
  2786. }
  2787. }
  2788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2789. "%s TSO Desc Alloc %d, descs = %d\n",
  2790. __func__, num_pool, num_desc);
  2791. for (i = 0; i < num_pool; i++) {
  2792. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2794. "TSO Num of seg Pool alloc %d failed %pK\n",
  2795. i, soc);
  2796. goto fail;
  2797. }
  2798. }
  2799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2800. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2801. __func__, num_pool, num_desc);
  2802. /* Initialize descriptors in TCL Rings */
  2803. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2804. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2805. hal_tx_init_data_ring(soc->hal_soc,
  2806. soc->tcl_data_ring[i].hal_srng);
  2807. }
  2808. }
  2809. /*
  2810. * todo - Add a runtime config option to enable this.
  2811. */
  2812. /*
  2813. * Due to multiple issues on NPR EMU, enable it selectively
  2814. * only for NPR EMU, should be removed, once NPR platforms
  2815. * are stable.
  2816. */
  2817. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2818. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2819. "%s HAL Tx init Success\n", __func__);
  2820. return QDF_STATUS_SUCCESS;
  2821. fail:
  2822. /* Detach will take care of freeing only allocated resources */
  2823. dp_tx_soc_detach(soc);
  2824. return QDF_STATUS_E_RESOURCES;
  2825. }
  2826. /*
  2827. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2828. * pdev: pointer to DP PDEV structure
  2829. * seg_info_head: Pointer to the head of list
  2830. *
  2831. * return: void
  2832. */
  2833. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2834. struct dp_tx_seg_info_s *seg_info_head)
  2835. {
  2836. struct dp_tx_me_buf_t *mc_uc_buf;
  2837. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2838. qdf_nbuf_t nbuf = NULL;
  2839. uint64_t phy_addr;
  2840. while (seg_info_head) {
  2841. nbuf = seg_info_head->nbuf;
  2842. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2843. seg_info_head->frags[0].vaddr;
  2844. phy_addr = seg_info_head->frags[0].paddr_hi;
  2845. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2846. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2847. phy_addr,
  2848. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2849. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2850. qdf_nbuf_free(nbuf);
  2851. seg_info_new = seg_info_head;
  2852. seg_info_head = seg_info_head->next;
  2853. qdf_mem_free(seg_info_new);
  2854. }
  2855. }
  2856. /**
  2857. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2858. * @vdev: DP VDEV handle
  2859. * @nbuf: Multicast nbuf
  2860. * @newmac: Table of the clients to which packets have to be sent
  2861. * @new_mac_cnt: No of clients
  2862. *
  2863. * return: no of converted packets
  2864. */
  2865. uint16_t
  2866. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2867. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2868. {
  2869. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2870. struct dp_pdev *pdev = vdev->pdev;
  2871. struct ether_header *eh;
  2872. uint8_t *data;
  2873. uint16_t len;
  2874. /* reference to frame dst addr */
  2875. uint8_t *dstmac;
  2876. /* copy of original frame src addr */
  2877. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2878. /* local index into newmac */
  2879. uint8_t new_mac_idx = 0;
  2880. struct dp_tx_me_buf_t *mc_uc_buf;
  2881. qdf_nbuf_t nbuf_clone;
  2882. struct dp_tx_msdu_info_s msdu_info;
  2883. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2884. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2885. struct dp_tx_seg_info_s *seg_info_new;
  2886. struct dp_tx_frag_info_s data_frag;
  2887. qdf_dma_addr_t paddr_data;
  2888. qdf_dma_addr_t paddr_mcbuf = 0;
  2889. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2890. QDF_STATUS status;
  2891. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2892. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2893. eh = (struct ether_header *) nbuf;
  2894. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2895. len = qdf_nbuf_len(nbuf);
  2896. data = qdf_nbuf_data(nbuf);
  2897. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2898. QDF_DMA_TO_DEVICE);
  2899. if (status) {
  2900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2901. "Mapping failure Error:%d", status);
  2902. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2903. qdf_nbuf_free(nbuf);
  2904. return 1;
  2905. }
  2906. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2907. /*preparing data fragment*/
  2908. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2909. data_frag.paddr_lo = (uint32_t)paddr_data;
  2910. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2911. data_frag.len = len - DP_MAC_ADDR_LEN;
  2912. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2913. dstmac = newmac[new_mac_idx];
  2914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2915. "added mac addr (%pM)", dstmac);
  2916. /* Check for NULL Mac Address */
  2917. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2918. continue;
  2919. /* frame to self mac. skip */
  2920. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2921. continue;
  2922. /*
  2923. * TODO: optimize to avoid malloc in per-packet path
  2924. * For eg. seg_pool can be made part of vdev structure
  2925. */
  2926. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2927. if (!seg_info_new) {
  2928. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2929. "alloc failed");
  2930. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2931. goto fail_seg_alloc;
  2932. }
  2933. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2934. if (mc_uc_buf == NULL)
  2935. goto fail_buf_alloc;
  2936. /*
  2937. * TODO: Check if we need to clone the nbuf
  2938. * Or can we just use the reference for all cases
  2939. */
  2940. if (new_mac_idx < (new_mac_cnt - 1)) {
  2941. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2942. if (nbuf_clone == NULL) {
  2943. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2944. goto fail_clone;
  2945. }
  2946. } else {
  2947. /*
  2948. * Update the ref
  2949. * to account for frame sent without cloning
  2950. */
  2951. qdf_nbuf_ref(nbuf);
  2952. nbuf_clone = nbuf;
  2953. }
  2954. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2955. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2956. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2957. &paddr_mcbuf);
  2958. if (status) {
  2959. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2960. "Mapping failure Error:%d", status);
  2961. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2962. goto fail_map;
  2963. }
  2964. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2965. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2966. seg_info_new->frags[0].paddr_hi =
  2967. ((uint64_t) paddr_mcbuf >> 32);
  2968. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2969. seg_info_new->frags[1] = data_frag;
  2970. seg_info_new->nbuf = nbuf_clone;
  2971. seg_info_new->frag_cnt = 2;
  2972. seg_info_new->total_len = len;
  2973. seg_info_new->next = NULL;
  2974. if (seg_info_head == NULL)
  2975. seg_info_head = seg_info_new;
  2976. else
  2977. seg_info_tail->next = seg_info_new;
  2978. seg_info_tail = seg_info_new;
  2979. }
  2980. if (!seg_info_head) {
  2981. goto free_return;
  2982. }
  2983. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2984. msdu_info.num_seg = new_mac_cnt;
  2985. msdu_info.frm_type = dp_tx_frm_me;
  2986. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2987. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2988. while (seg_info_head->next) {
  2989. seg_info_new = seg_info_head;
  2990. seg_info_head = seg_info_head->next;
  2991. qdf_mem_free(seg_info_new);
  2992. }
  2993. qdf_mem_free(seg_info_head);
  2994. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2995. qdf_nbuf_free(nbuf);
  2996. return new_mac_cnt;
  2997. fail_map:
  2998. qdf_nbuf_free(nbuf_clone);
  2999. fail_clone:
  3000. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3001. fail_buf_alloc:
  3002. qdf_mem_free(seg_info_new);
  3003. fail_seg_alloc:
  3004. dp_tx_me_mem_free(pdev, seg_info_head);
  3005. free_return:
  3006. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3007. qdf_nbuf_free(nbuf);
  3008. return 1;
  3009. }