main.c 129 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/thermal.h>
  20. #include <linux/version.h>
  21. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  22. #include <linux/panic_notifier.h>
  23. #endif
  24. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  25. #include <soc/qcom/minidump.h>
  26. #endif
  27. #include "cnss_plat_ipc_qmi.h"
  28. #include "cnss_utils.h"
  29. #include "main.h"
  30. #include "bus.h"
  31. #include "debug.h"
  32. #include "genl.h"
  33. #include "reg.h"
  34. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  35. #include "smcinvoke.h"
  36. #include "smcinvoke_object.h"
  37. #include "IClientEnv.h"
  38. #define HW_STATE_UID 0x108
  39. #define HW_OP_GET_STATE 1
  40. #define HW_WIFI_UID 0x508
  41. #define FEATURE_NOT_SUPPORTED 12
  42. #define PERIPHERAL_NOT_FOUND 10
  43. #endif
  44. #define CNSS_DUMP_FORMAT_VER 0x11
  45. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  46. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  47. #define CNSS_DUMP_NAME "CNSS_WLAN"
  48. #define CNSS_DUMP_DESC_SIZE 0x1000
  49. #define CNSS_DUMP_SEG_VER 0x1
  50. #define FILE_SYSTEM_READY 1
  51. #define FW_READY_TIMEOUT 20000
  52. #define FW_ASSERT_TIMEOUT 5000
  53. #define CNSS_EVENT_PENDING 2989
  54. #define POWER_RESET_MIN_DELAY_MS 100
  55. #define CNSS_QUIRKS_DEFAULT 0
  56. #ifdef CONFIG_CNSS_EMULATION
  57. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  58. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  59. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  60. #else
  61. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  62. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  63. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  64. #endif
  65. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  66. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  67. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  68. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  69. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  70. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  71. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  72. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  73. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  74. enum cnss_cal_db_op {
  75. CNSS_CAL_DB_UPLOAD,
  76. CNSS_CAL_DB_DOWNLOAD,
  77. CNSS_CAL_DB_INVALID_OP,
  78. };
  79. enum cnss_recovery_type {
  80. CNSS_WLAN_RECOVERY = 0x1,
  81. CNSS_PCSS_RECOVERY = 0x2,
  82. };
  83. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  84. #define CNSS_MAX_DEV_NUM 2
  85. static struct cnss_plat_data *plat_env[CNSS_MAX_DEV_NUM];
  86. static int plat_env_count;
  87. #else
  88. static struct cnss_plat_data *plat_env;
  89. #endif
  90. static bool cnss_allow_driver_loading;
  91. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  92. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  93. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  94. };
  95. static struct cnss_fw_files FW_FILES_DEFAULT = {
  96. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  97. "utfbd.bin", "epping.bin", "evicted.bin"
  98. };
  99. struct cnss_driver_event {
  100. struct list_head list;
  101. enum cnss_driver_event_type type;
  102. bool sync;
  103. struct completion complete;
  104. int ret;
  105. void *data;
  106. };
  107. bool cnss_check_driver_loading_allowed(void)
  108. {
  109. return cnss_allow_driver_loading;
  110. }
  111. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  112. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  113. struct cnss_plat_data *plat_priv)
  114. {
  115. cnss_pr_dbg("Set plat_priv at %d", plat_env_count);
  116. if (plat_priv) {
  117. plat_priv->plat_idx = plat_env_count;
  118. plat_env[plat_priv->plat_idx] = plat_priv;
  119. plat_env_count++;
  120. }
  121. }
  122. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device
  123. *plat_dev)
  124. {
  125. int i;
  126. if (!plat_dev)
  127. return NULL;
  128. for (i = 0; i < plat_env_count; i++) {
  129. if (plat_env[i]->plat_dev == plat_dev)
  130. return plat_env[i];
  131. }
  132. return NULL;
  133. }
  134. struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device
  135. *plat_dev)
  136. {
  137. int i;
  138. if (!plat_dev) {
  139. for (i = 0; i < plat_env_count; i++) {
  140. if (plat_env[i])
  141. return plat_env[i];
  142. }
  143. }
  144. return NULL;
  145. }
  146. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  147. {
  148. cnss_pr_dbg("Clear plat_priv at %d", plat_priv->plat_idx);
  149. plat_env[plat_priv->plat_idx] = NULL;
  150. plat_env_count--;
  151. }
  152. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  153. {
  154. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  155. "wlan_%d", plat_priv->plat_idx);
  156. return 0;
  157. }
  158. static int cnss_plat_env_available(void)
  159. {
  160. int ret = 0;
  161. if (plat_env_count >= CNSS_MAX_DEV_NUM) {
  162. cnss_pr_err("ERROR: No space to store plat_priv\n");
  163. ret = -ENOMEM;
  164. }
  165. return ret;
  166. }
  167. int cnss_get_plat_env_count(void)
  168. {
  169. return plat_env_count;
  170. }
  171. struct cnss_plat_data *cnss_get_plat_env(int index)
  172. {
  173. return plat_env[index];
  174. }
  175. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  176. {
  177. int i;
  178. for (i = 0; i < plat_env_count; i++) {
  179. if (plat_env[i]->rc_num == rc_num)
  180. return plat_env[i];
  181. }
  182. return NULL;
  183. }
  184. static inline int
  185. cnss_get_qrtr_node_id(struct cnss_plat_data *plat_priv)
  186. {
  187. return of_property_read_u32(plat_priv->dev_node,
  188. "qcom,qrtr_node_id", &plat_priv->qrtr_node_id);
  189. }
  190. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  191. {
  192. int ret = 0;
  193. ret = cnss_get_qrtr_node_id(plat_priv);
  194. if (ret) {
  195. cnss_pr_warn("Failed to find qrtr_node_id err=%d\n", ret);
  196. plat_priv->qrtr_node_id = 0;
  197. plat_priv->wlfw_service_instance_id = 0;
  198. } else {
  199. plat_priv->wlfw_service_instance_id = plat_priv->qrtr_node_id +
  200. QRTR_NODE_FW_ID_BASE;
  201. cnss_pr_dbg("service_instance_id=0x%x\n",
  202. plat_priv->wlfw_service_instance_id);
  203. }
  204. }
  205. static inline int
  206. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  207. {
  208. return of_property_read_string(plat_priv->plat_dev->dev.of_node,
  209. "qcom,pld_bus_ops_name",
  210. &plat_priv->pld_bus_ops_name);
  211. }
  212. #else
  213. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  214. struct cnss_plat_data *plat_priv)
  215. {
  216. plat_env = plat_priv;
  217. }
  218. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  219. {
  220. return plat_env;
  221. }
  222. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  223. {
  224. plat_env = NULL;
  225. }
  226. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  227. {
  228. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  229. "wlan");
  230. return 0;
  231. }
  232. static int cnss_plat_env_available(void)
  233. {
  234. return 0;
  235. }
  236. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  237. {
  238. return cnss_bus_dev_to_plat_priv(NULL);
  239. }
  240. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  241. {
  242. }
  243. static int
  244. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  245. {
  246. return 0;
  247. }
  248. #endif
  249. void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv)
  250. {
  251. plat_priv->sleep_clk = of_property_read_bool(plat_priv->dev_node,
  252. "qcom,sleep-clk-support");
  253. cnss_pr_dbg("qcom,sleep-clk-support is %d\n",
  254. plat_priv->sleep_clk);
  255. }
  256. void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv)
  257. {
  258. plat_priv->no_bwscale = of_property_read_bool(plat_priv->dev_node,
  259. "qcom,no-bwscale");
  260. }
  261. static inline int
  262. cnss_get_rc_num(struct cnss_plat_data *plat_priv)
  263. {
  264. return of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  265. "qcom,wlan-rc-num", &plat_priv->rc_num);
  266. }
  267. bool cnss_is_dual_wlan_enabled(void)
  268. {
  269. return IS_ENABLED(CONFIG_CNSS_SUPPORT_DUAL_DEV);
  270. }
  271. /**
  272. * cnss_get_mem_seg_count - Get segment count of memory
  273. * @type: memory type
  274. * @seg: segment count
  275. *
  276. * Return: 0 on success, negative value on failure
  277. */
  278. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  279. {
  280. struct cnss_plat_data *plat_priv;
  281. plat_priv = cnss_get_plat_priv(NULL);
  282. if (!plat_priv)
  283. return -ENODEV;
  284. switch (type) {
  285. case CNSS_REMOTE_MEM_TYPE_FW:
  286. *seg = plat_priv->fw_mem_seg_len;
  287. break;
  288. case CNSS_REMOTE_MEM_TYPE_QDSS:
  289. *seg = plat_priv->qdss_mem_seg_len;
  290. break;
  291. default:
  292. return -EINVAL;
  293. }
  294. return 0;
  295. }
  296. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  297. /**
  298. * cnss_get_wifi_kobject -return wifi kobject
  299. * Return: Null, to maintain driver comnpatibilty
  300. */
  301. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  302. {
  303. struct cnss_plat_data *plat_priv;
  304. plat_priv = cnss_get_plat_priv(NULL);
  305. if (!plat_priv)
  306. return NULL;
  307. return plat_priv->wifi_kobj;
  308. }
  309. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  310. /**
  311. * cnss_get_mem_segment_info - Get memory info of different type
  312. * @type: memory type
  313. * @segment: array to save the segment info
  314. * @seg: segment count
  315. *
  316. * Return: 0 on success, negative value on failure
  317. */
  318. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  319. struct cnss_mem_segment segment[],
  320. u32 segment_count)
  321. {
  322. struct cnss_plat_data *plat_priv;
  323. u32 i;
  324. plat_priv = cnss_get_plat_priv(NULL);
  325. if (!plat_priv)
  326. return -ENODEV;
  327. switch (type) {
  328. case CNSS_REMOTE_MEM_TYPE_FW:
  329. if (segment_count > plat_priv->fw_mem_seg_len)
  330. segment_count = plat_priv->fw_mem_seg_len;
  331. for (i = 0; i < segment_count; i++) {
  332. segment[i].size = plat_priv->fw_mem[i].size;
  333. segment[i].va = plat_priv->fw_mem[i].va;
  334. segment[i].pa = plat_priv->fw_mem[i].pa;
  335. }
  336. break;
  337. case CNSS_REMOTE_MEM_TYPE_QDSS:
  338. if (segment_count > plat_priv->qdss_mem_seg_len)
  339. segment_count = plat_priv->qdss_mem_seg_len;
  340. for (i = 0; i < segment_count; i++) {
  341. segment[i].size = plat_priv->qdss_mem[i].size;
  342. segment[i].va = plat_priv->qdss_mem[i].va;
  343. segment[i].pa = plat_priv->qdss_mem[i].pa;
  344. }
  345. break;
  346. default:
  347. return -EINVAL;
  348. }
  349. return 0;
  350. }
  351. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  352. static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
  353. {
  354. struct device_node *audio_ion_node;
  355. struct platform_device *audio_ion_pdev;
  356. audio_ion_node = of_find_compatible_node(NULL, NULL,
  357. "qcom,msm-audio-ion");
  358. if (!audio_ion_node) {
  359. cnss_pr_err("Unable to get Audio ion node");
  360. return -EINVAL;
  361. }
  362. audio_ion_pdev = of_find_device_by_node(audio_ion_node);
  363. of_node_put(audio_ion_node);
  364. if (!audio_ion_pdev) {
  365. cnss_pr_err("Unable to get Audio ion platform device");
  366. return -EINVAL;
  367. }
  368. plat_priv->audio_iommu_domain =
  369. iommu_get_domain_for_dev(&audio_ion_pdev->dev);
  370. put_device(&audio_ion_pdev->dev);
  371. if (!plat_priv->audio_iommu_domain) {
  372. cnss_pr_err("Unable to get Audio ion iommu domain");
  373. return -EINVAL;
  374. }
  375. return 0;
  376. }
  377. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  378. enum cnss_feature_v01 feature)
  379. {
  380. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  381. return -EINVAL;
  382. plat_priv->feature_list |= 1 << feature;
  383. return 0;
  384. }
  385. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  386. enum cnss_feature_v01 feature)
  387. {
  388. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  389. return -EINVAL;
  390. plat_priv->feature_list &= ~(1 << feature);
  391. return 0;
  392. }
  393. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  394. u64 *feature_list)
  395. {
  396. if (unlikely(!plat_priv))
  397. return -EINVAL;
  398. *feature_list = plat_priv->feature_list;
  399. return 0;
  400. }
  401. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  402. {
  403. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  404. return;
  405. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  406. plat_priv->driver_state,
  407. atomic_read(&plat_priv->pm_count));
  408. pm_stay_awake(&plat_priv->plat_dev->dev);
  409. }
  410. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  411. {
  412. int r = atomic_dec_return(&plat_priv->pm_count);
  413. WARN_ON(r < 0);
  414. if (r != 0)
  415. return;
  416. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  417. plat_priv->driver_state,
  418. atomic_read(&plat_priv->pm_count));
  419. pm_relax(&plat_priv->plat_dev->dev);
  420. }
  421. int cnss_get_fw_files_for_target(struct device *dev,
  422. struct cnss_fw_files *pfw_files,
  423. u32 target_type, u32 target_version)
  424. {
  425. if (!pfw_files)
  426. return -ENODEV;
  427. switch (target_version) {
  428. case QCA6174_REV3_VERSION:
  429. case QCA6174_REV3_2_VERSION:
  430. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  431. break;
  432. default:
  433. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  434. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  435. target_type, target_version);
  436. break;
  437. }
  438. return 0;
  439. }
  440. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  441. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  442. {
  443. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  444. if (!plat_priv)
  445. return -ENODEV;
  446. if (!cap)
  447. return -EINVAL;
  448. *cap = plat_priv->cap;
  449. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  450. return 0;
  451. }
  452. EXPORT_SYMBOL(cnss_get_platform_cap);
  453. /**
  454. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  455. * @dev: Device
  456. * @fw_cap: FW Capability which needs to be checked
  457. *
  458. * Return: TRUE if supported, FALSE on failure or if not supported
  459. */
  460. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  461. {
  462. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  463. bool is_supported = false;
  464. if (!plat_priv)
  465. return is_supported;
  466. if (!plat_priv->fw_caps)
  467. return is_supported;
  468. switch (fw_cap) {
  469. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  470. is_supported = !!(plat_priv->fw_caps &
  471. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  472. if (is_supported && cnss_get_audio_iommu_domain(plat_priv))
  473. is_supported = false;
  474. break;
  475. default:
  476. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  477. }
  478. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  479. is_supported ? "supported" : "not supported");
  480. return is_supported;
  481. }
  482. EXPORT_SYMBOL(cnss_get_fw_cap);
  483. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  484. {
  485. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  486. if (!plat_priv)
  487. return;
  488. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  489. }
  490. EXPORT_SYMBOL(cnss_request_pm_qos);
  491. void cnss_remove_pm_qos(struct device *dev)
  492. {
  493. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  494. if (!plat_priv)
  495. return;
  496. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  497. }
  498. EXPORT_SYMBOL(cnss_remove_pm_qos);
  499. int cnss_wlan_enable(struct device *dev,
  500. struct cnss_wlan_enable_cfg *config,
  501. enum cnss_driver_mode mode,
  502. const char *host_version)
  503. {
  504. int ret = 0;
  505. struct cnss_plat_data *plat_priv;
  506. if (!dev) {
  507. cnss_pr_err("Invalid dev pointer\n");
  508. return -EINVAL;
  509. }
  510. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  511. if (!plat_priv)
  512. return -ENODEV;
  513. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  514. return 0;
  515. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  516. return 0;
  517. if (!config || !host_version) {
  518. cnss_pr_err("Invalid config or host_version pointer\n");
  519. return -EINVAL;
  520. }
  521. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  522. mode, config, host_version);
  523. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  524. goto skip_cfg;
  525. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  526. config->send_msi_ce = true;
  527. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  528. if (ret)
  529. goto out;
  530. skip_cfg:
  531. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  532. out:
  533. return ret;
  534. }
  535. EXPORT_SYMBOL(cnss_wlan_enable);
  536. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  537. {
  538. int ret = 0;
  539. struct cnss_plat_data *plat_priv;
  540. if (!dev) {
  541. cnss_pr_err("Invalid dev pointer\n");
  542. return -EINVAL;
  543. }
  544. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  545. if (!plat_priv)
  546. return -ENODEV;
  547. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  548. return 0;
  549. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  550. return 0;
  551. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  552. cnss_bus_free_qdss_mem(plat_priv);
  553. return ret;
  554. }
  555. EXPORT_SYMBOL(cnss_wlan_disable);
  556. int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  557. dma_addr_t iova, size_t size)
  558. {
  559. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  560. uint32_t page_offset;
  561. if (!plat_priv)
  562. return -ENODEV;
  563. if (!plat_priv->audio_iommu_domain)
  564. return -EINVAL;
  565. page_offset = iova & (PAGE_SIZE - 1);
  566. if (page_offset + size > PAGE_SIZE)
  567. size += PAGE_SIZE;
  568. iova -= page_offset;
  569. paddr -= page_offset;
  570. return iommu_map(plat_priv->audio_iommu_domain, iova, paddr,
  571. roundup(size, PAGE_SIZE), IOMMU_READ | IOMMU_WRITE |
  572. IOMMU_CACHE);
  573. }
  574. EXPORT_SYMBOL(cnss_audio_smmu_map);
  575. void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
  576. {
  577. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  578. uint32_t page_offset;
  579. if (!plat_priv)
  580. return;
  581. if (!plat_priv->audio_iommu_domain)
  582. return;
  583. page_offset = iova & (PAGE_SIZE - 1);
  584. if (page_offset + size > PAGE_SIZE)
  585. size += PAGE_SIZE;
  586. iova -= page_offset;
  587. iommu_unmap(plat_priv->audio_iommu_domain, iova,
  588. roundup(size, PAGE_SIZE));
  589. }
  590. EXPORT_SYMBOL(cnss_audio_smmu_unmap);
  591. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  592. u32 data_len, u8 *output)
  593. {
  594. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  595. int ret = 0;
  596. if (!plat_priv) {
  597. cnss_pr_err("plat_priv is NULL!\n");
  598. return -EINVAL;
  599. }
  600. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  601. return 0;
  602. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  603. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  604. plat_priv->driver_state);
  605. ret = -EINVAL;
  606. goto out;
  607. }
  608. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  609. data_len, output);
  610. out:
  611. return ret;
  612. }
  613. EXPORT_SYMBOL(cnss_athdiag_read);
  614. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  615. u32 data_len, u8 *input)
  616. {
  617. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  618. int ret = 0;
  619. if (!plat_priv) {
  620. cnss_pr_err("plat_priv is NULL!\n");
  621. return -EINVAL;
  622. }
  623. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  624. return 0;
  625. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  626. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  627. plat_priv->driver_state);
  628. ret = -EINVAL;
  629. goto out;
  630. }
  631. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  632. data_len, input);
  633. out:
  634. return ret;
  635. }
  636. EXPORT_SYMBOL(cnss_athdiag_write);
  637. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  638. {
  639. struct cnss_plat_data *plat_priv;
  640. if (!dev) {
  641. cnss_pr_err("Invalid dev pointer\n");
  642. return -EINVAL;
  643. }
  644. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  645. if (!plat_priv)
  646. return -ENODEV;
  647. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  648. return 0;
  649. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  650. }
  651. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  652. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  653. {
  654. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  655. if (!plat_priv)
  656. return -EINVAL;
  657. if (!plat_priv->fw_pcie_gen_switch) {
  658. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  659. return -EOPNOTSUPP;
  660. }
  661. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  662. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  663. return -EINVAL;
  664. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  665. plat_priv->pcie_gen_speed = pcie_gen_speed;
  666. return 0;
  667. }
  668. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  669. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  670. {
  671. int ret = 0;
  672. if (!plat_priv)
  673. return -ENODEV;
  674. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  675. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  676. if (ret)
  677. goto out;
  678. if (plat_priv->hds_enabled)
  679. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  680. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  681. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  682. plat_priv->ctrl_params.bdf_type = CNSS_BDF_BIN;
  683. cnss_wlfw_ini_file_send_sync(plat_priv, WLFW_CONN_ROAM_INI_V01);
  684. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  685. plat_priv->ctrl_params.bdf_type);
  686. if (ret)
  687. goto out;
  688. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  689. return 0;
  690. ret = cnss_bus_load_m3(plat_priv);
  691. if (ret)
  692. goto out;
  693. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  694. if (ret)
  695. goto out;
  696. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  697. return 0;
  698. out:
  699. return ret;
  700. }
  701. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  702. {
  703. int ret = 0;
  704. if (!plat_priv->antenna) {
  705. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  706. if (ret)
  707. goto out;
  708. }
  709. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  710. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  711. if (ret)
  712. goto out;
  713. }
  714. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  715. if (ret)
  716. goto out;
  717. return 0;
  718. out:
  719. return ret;
  720. }
  721. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  722. {
  723. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  724. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  725. }
  726. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  727. {
  728. u32 i;
  729. int ret = 0;
  730. struct cnss_plat_ipc_daemon_config *cfg;
  731. ret = cnss_qmi_get_dms_mac(plat_priv);
  732. if (ret == 0 && plat_priv->dms.mac_valid)
  733. goto qmi_send;
  734. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  735. * Thus assert on failure to get MAC from DMS even after retries
  736. */
  737. if (plat_priv->use_nv_mac) {
  738. /* Check if Daemon says platform support DMS MAC provisioning */
  739. cfg = cnss_plat_ipc_qmi_daemon_config();
  740. if (cfg) {
  741. if (!cfg->dms_mac_addr_supported) {
  742. cnss_pr_err("DMS MAC address not supported\n");
  743. CNSS_ASSERT(0);
  744. return -EINVAL;
  745. }
  746. }
  747. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  748. if (plat_priv->dms.mac_valid)
  749. break;
  750. ret = cnss_qmi_get_dms_mac(plat_priv);
  751. if (ret == 0)
  752. break;
  753. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  754. }
  755. if (!plat_priv->dms.mac_valid) {
  756. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  757. CNSS_ASSERT(0);
  758. return -EINVAL;
  759. }
  760. }
  761. qmi_send:
  762. if (plat_priv->dms.mac_valid)
  763. ret =
  764. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  765. ARRAY_SIZE(plat_priv->dms.mac));
  766. return ret;
  767. }
  768. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  769. enum cnss_cal_db_op op, u32 *size)
  770. {
  771. int ret = 0;
  772. u32 timeout = cnss_get_timeout(plat_priv,
  773. CNSS_TIMEOUT_DAEMON_CONNECTION);
  774. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  775. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  776. if (op >= CNSS_CAL_DB_INVALID_OP)
  777. return -EINVAL;
  778. if (!plat_priv->cbc_file_download) {
  779. cnss_pr_info("CAL DB file not required as per BDF\n");
  780. return 0;
  781. }
  782. if (*size == 0) {
  783. cnss_pr_err("Invalid cal file size\n");
  784. return -EINVAL;
  785. }
  786. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  787. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  788. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  789. msecs_to_jiffies(timeout));
  790. if (!ret) {
  791. cnss_pr_err("Daemon not yet connected\n");
  792. CNSS_ASSERT(0);
  793. return ret;
  794. }
  795. }
  796. if (!plat_priv->cal_mem->va) {
  797. cnss_pr_err("CAL DB Memory not setup for FW\n");
  798. return -EINVAL;
  799. }
  800. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  801. if (op == CNSS_CAL_DB_DOWNLOAD) {
  802. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  803. ret = cnss_plat_ipc_qmi_file_download(client_id,
  804. CNSS_CAL_DB_FILE_NAME,
  805. plat_priv->cal_mem->va,
  806. size);
  807. } else {
  808. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  809. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  810. CNSS_CAL_DB_FILE_NAME,
  811. plat_priv->cal_mem->va,
  812. *size);
  813. }
  814. if (ret)
  815. cnss_pr_err("Cal DB file %s %s failure\n",
  816. CNSS_CAL_DB_FILE_NAME,
  817. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  818. else
  819. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  820. CNSS_CAL_DB_FILE_NAME,
  821. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  822. *size);
  823. return ret;
  824. }
  825. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  826. {
  827. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  828. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  829. return -EINVAL;
  830. }
  831. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  832. &plat_priv->cal_file_size);
  833. }
  834. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  835. u32 *cal_file_size)
  836. {
  837. /* To download pass the total size of cal DB mem allocated.
  838. * After cal file is download to mem, its size is updated in
  839. * return pointer
  840. */
  841. *cal_file_size = plat_priv->cal_mem->size;
  842. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  843. cal_file_size);
  844. }
  845. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  846. {
  847. int ret = 0;
  848. u32 cal_file_size = 0;
  849. if (!plat_priv)
  850. return -ENODEV;
  851. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  852. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  853. return -EINVAL;
  854. }
  855. cnss_pr_dbg("Processing FW Init Done..\n");
  856. del_timer(&plat_priv->fw_boot_timer);
  857. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  858. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  859. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  860. cnss_send_subsys_restart_level_msg(plat_priv);
  861. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  862. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  863. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  864. }
  865. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  866. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  867. CNSS_WALTEST);
  868. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  869. cnss_request_antenna_sharing(plat_priv);
  870. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  871. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  872. plat_priv->cal_time = jiffies;
  873. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  874. CNSS_CALIBRATION);
  875. } else {
  876. ret = cnss_setup_dms_mac(plat_priv);
  877. ret = cnss_bus_call_driver_probe(plat_priv);
  878. }
  879. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  880. goto out;
  881. else if (ret)
  882. goto shutdown;
  883. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  884. return 0;
  885. shutdown:
  886. cnss_bus_dev_shutdown(plat_priv);
  887. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  888. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  889. out:
  890. return ret;
  891. }
  892. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  893. {
  894. switch (type) {
  895. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  896. return "SERVER_ARRIVE";
  897. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  898. return "SERVER_EXIT";
  899. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  900. return "REQUEST_MEM";
  901. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  902. return "FW_MEM_READY";
  903. case CNSS_DRIVER_EVENT_FW_READY:
  904. return "FW_READY";
  905. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  906. return "COLD_BOOT_CAL_START";
  907. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  908. return "COLD_BOOT_CAL_DONE";
  909. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  910. return "REGISTER_DRIVER";
  911. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  912. return "UNREGISTER_DRIVER";
  913. case CNSS_DRIVER_EVENT_RECOVERY:
  914. return "RECOVERY";
  915. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  916. return "FORCE_FW_ASSERT";
  917. case CNSS_DRIVER_EVENT_POWER_UP:
  918. return "POWER_UP";
  919. case CNSS_DRIVER_EVENT_POWER_DOWN:
  920. return "POWER_DOWN";
  921. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  922. return "IDLE_RESTART";
  923. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  924. return "IDLE_SHUTDOWN";
  925. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  926. return "IMS_WFC_CALL_IND";
  927. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  928. return "WLFW_TWC_CFG_IND";
  929. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  930. return "QDSS_TRACE_REQ_MEM";
  931. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  932. return "FW_MEM_FILE_SAVE";
  933. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  934. return "QDSS_TRACE_FREE";
  935. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  936. return "QDSS_TRACE_REQ_DATA";
  937. case CNSS_DRIVER_EVENT_MAX:
  938. return "EVENT_MAX";
  939. }
  940. return "UNKNOWN";
  941. };
  942. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  943. enum cnss_driver_event_type type,
  944. u32 flags, void *data)
  945. {
  946. struct cnss_driver_event *event;
  947. unsigned long irq_flags;
  948. int gfp = GFP_KERNEL;
  949. int ret = 0;
  950. if (!plat_priv)
  951. return -ENODEV;
  952. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  953. cnss_driver_event_to_str(type), type,
  954. flags ? "-sync" : "", plat_priv->driver_state, flags);
  955. if (type >= CNSS_DRIVER_EVENT_MAX) {
  956. cnss_pr_err("Invalid Event type: %d, can't post", type);
  957. return -EINVAL;
  958. }
  959. if (in_interrupt() || irqs_disabled())
  960. gfp = GFP_ATOMIC;
  961. event = kzalloc(sizeof(*event), gfp);
  962. if (!event)
  963. return -ENOMEM;
  964. cnss_pm_stay_awake(plat_priv);
  965. event->type = type;
  966. event->data = data;
  967. init_completion(&event->complete);
  968. event->ret = CNSS_EVENT_PENDING;
  969. event->sync = !!(flags & CNSS_EVENT_SYNC);
  970. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  971. list_add_tail(&event->list, &plat_priv->event_list);
  972. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  973. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  974. if (!(flags & CNSS_EVENT_SYNC))
  975. goto out;
  976. if (flags & CNSS_EVENT_UNKILLABLE)
  977. wait_for_completion(&event->complete);
  978. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  979. ret = wait_for_completion_killable(&event->complete);
  980. else
  981. ret = wait_for_completion_interruptible(&event->complete);
  982. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  983. cnss_driver_event_to_str(type), type,
  984. plat_priv->driver_state, ret, event->ret);
  985. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  986. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  987. event->sync = false;
  988. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  989. ret = -EINTR;
  990. goto out;
  991. }
  992. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  993. ret = event->ret;
  994. kfree(event);
  995. out:
  996. cnss_pm_relax(plat_priv);
  997. return ret;
  998. }
  999. /**
  1000. * cnss_get_timeout - Get timeout for corresponding type.
  1001. * @plat_priv: Pointer to platform driver context.
  1002. * @cnss_timeout_type: Timeout type.
  1003. *
  1004. * Return: Timeout in milliseconds.
  1005. */
  1006. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  1007. enum cnss_timeout_type timeout_type)
  1008. {
  1009. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  1010. switch (timeout_type) {
  1011. case CNSS_TIMEOUT_QMI:
  1012. return qmi_timeout;
  1013. case CNSS_TIMEOUT_POWER_UP:
  1014. return (qmi_timeout << 2);
  1015. case CNSS_TIMEOUT_IDLE_RESTART:
  1016. /* In idle restart power up sequence, we have fw_boot_timer to
  1017. * handle FW initialization failure.
  1018. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  1019. * account for FW dump collection and FW re-initialization on
  1020. * retry.
  1021. */
  1022. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  1023. case CNSS_TIMEOUT_CALIBRATION:
  1024. /* Similar to mission mode, in CBC if FW init fails
  1025. * fw recovery is tried. Thus return 2x the CBC timeout.
  1026. */
  1027. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  1028. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  1029. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  1030. case CNSS_TIMEOUT_RDDM:
  1031. return CNSS_RDDM_TIMEOUT_MS;
  1032. case CNSS_TIMEOUT_RECOVERY:
  1033. return RECOVERY_TIMEOUT;
  1034. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  1035. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  1036. default:
  1037. return qmi_timeout;
  1038. }
  1039. }
  1040. unsigned int cnss_get_boot_timeout(struct device *dev)
  1041. {
  1042. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1043. if (!plat_priv) {
  1044. cnss_pr_err("plat_priv is NULL\n");
  1045. return 0;
  1046. }
  1047. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  1048. }
  1049. EXPORT_SYMBOL(cnss_get_boot_timeout);
  1050. int cnss_power_up(struct device *dev)
  1051. {
  1052. int ret = 0;
  1053. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1054. unsigned int timeout;
  1055. if (!plat_priv) {
  1056. cnss_pr_err("plat_priv is NULL\n");
  1057. return -ENODEV;
  1058. }
  1059. cnss_pr_dbg("Powering up device\n");
  1060. ret = cnss_driver_event_post(plat_priv,
  1061. CNSS_DRIVER_EVENT_POWER_UP,
  1062. CNSS_EVENT_SYNC, NULL);
  1063. if (ret)
  1064. goto out;
  1065. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1066. goto out;
  1067. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  1068. reinit_completion(&plat_priv->power_up_complete);
  1069. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1070. msecs_to_jiffies(timeout));
  1071. if (!ret) {
  1072. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  1073. timeout);
  1074. ret = -EAGAIN;
  1075. goto out;
  1076. }
  1077. return 0;
  1078. out:
  1079. return ret;
  1080. }
  1081. EXPORT_SYMBOL(cnss_power_up);
  1082. int cnss_power_down(struct device *dev)
  1083. {
  1084. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1085. if (!plat_priv) {
  1086. cnss_pr_err("plat_priv is NULL\n");
  1087. return -ENODEV;
  1088. }
  1089. cnss_pr_dbg("Powering down device\n");
  1090. return cnss_driver_event_post(plat_priv,
  1091. CNSS_DRIVER_EVENT_POWER_DOWN,
  1092. CNSS_EVENT_SYNC, NULL);
  1093. }
  1094. EXPORT_SYMBOL(cnss_power_down);
  1095. int cnss_idle_restart(struct device *dev)
  1096. {
  1097. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1098. unsigned int timeout;
  1099. int ret = 0;
  1100. if (!plat_priv) {
  1101. cnss_pr_err("plat_priv is NULL\n");
  1102. return -ENODEV;
  1103. }
  1104. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  1105. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  1106. return -EBUSY;
  1107. }
  1108. cnss_pr_dbg("Doing idle restart\n");
  1109. reinit_completion(&plat_priv->power_up_complete);
  1110. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1111. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1112. ret = -EINVAL;
  1113. goto out;
  1114. }
  1115. ret = cnss_driver_event_post(plat_priv,
  1116. CNSS_DRIVER_EVENT_IDLE_RESTART,
  1117. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1118. if (ret == -EINTR && plat_priv->device_id != QCA6174_DEVICE_ID)
  1119. cnss_pr_err("Idle restart has been interrupted but device power up is still in progress");
  1120. else if (ret)
  1121. goto out;
  1122. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1123. ret = cnss_bus_call_driver_probe(plat_priv);
  1124. goto out;
  1125. }
  1126. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  1127. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1128. msecs_to_jiffies(timeout));
  1129. if (plat_priv->power_up_error) {
  1130. ret = plat_priv->power_up_error;
  1131. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1132. cnss_pr_dbg("Power up error:%d, exiting\n",
  1133. plat_priv->power_up_error);
  1134. goto out;
  1135. }
  1136. if (!ret) {
  1137. /* This exception occurs after attempting retry of FW recovery.
  1138. * Thus we can safely power off the device.
  1139. */
  1140. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  1141. timeout);
  1142. ret = -ETIMEDOUT;
  1143. cnss_power_down(dev);
  1144. CNSS_ASSERT(0);
  1145. goto out;
  1146. }
  1147. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1148. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1149. del_timer(&plat_priv->fw_boot_timer);
  1150. ret = -EINVAL;
  1151. goto out;
  1152. }
  1153. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  1154. * non-DRV is supported only once after device reboots and before wifi
  1155. * is turned on. We do not allow switching back to DRV.
  1156. * To bring device back into DRV, user needs to reboot device.
  1157. */
  1158. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  1159. cnss_pr_dbg("DRV is disabled\n");
  1160. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  1161. }
  1162. mutex_unlock(&plat_priv->driver_ops_lock);
  1163. return 0;
  1164. out:
  1165. mutex_unlock(&plat_priv->driver_ops_lock);
  1166. return ret;
  1167. }
  1168. EXPORT_SYMBOL(cnss_idle_restart);
  1169. int cnss_idle_shutdown(struct device *dev)
  1170. {
  1171. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1172. if (!plat_priv) {
  1173. cnss_pr_err("plat_priv is NULL\n");
  1174. return -ENODEV;
  1175. }
  1176. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  1177. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  1178. return -EAGAIN;
  1179. }
  1180. cnss_pr_dbg("Doing idle shutdown\n");
  1181. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) ||
  1182. test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) {
  1183. cnss_pr_dbg("Recovery in progress. Ignore IDLE Shutdown\n");
  1184. return -EBUSY;
  1185. }
  1186. return cnss_driver_event_post(plat_priv,
  1187. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  1188. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1189. }
  1190. EXPORT_SYMBOL(cnss_idle_shutdown);
  1191. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  1192. {
  1193. int ret = 0;
  1194. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1195. if (ret < 0) {
  1196. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  1197. goto out;
  1198. }
  1199. ret = cnss_get_clk(plat_priv);
  1200. if (ret) {
  1201. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  1202. goto put_vreg;
  1203. }
  1204. ret = cnss_get_pinctrl(plat_priv);
  1205. if (ret) {
  1206. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  1207. goto put_clk;
  1208. }
  1209. return 0;
  1210. put_clk:
  1211. cnss_put_clk(plat_priv);
  1212. put_vreg:
  1213. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1214. out:
  1215. return ret;
  1216. }
  1217. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  1218. {
  1219. cnss_put_clk(plat_priv);
  1220. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1221. }
  1222. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1223. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  1224. unsigned long code,
  1225. void *ss_handle)
  1226. {
  1227. struct cnss_plat_data *plat_priv =
  1228. container_of(nb, struct cnss_plat_data, modem_nb);
  1229. struct cnss_esoc_info *esoc_info;
  1230. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  1231. if (!plat_priv)
  1232. return NOTIFY_DONE;
  1233. esoc_info = &plat_priv->esoc_info;
  1234. if (code == SUBSYS_AFTER_POWERUP)
  1235. esoc_info->modem_current_status = 1;
  1236. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1237. esoc_info->modem_current_status = 0;
  1238. else
  1239. return NOTIFY_DONE;
  1240. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1241. esoc_info->modem_current_status))
  1242. return NOTIFY_DONE;
  1243. return NOTIFY_OK;
  1244. }
  1245. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1246. {
  1247. int ret = 0;
  1248. struct device *dev;
  1249. struct cnss_esoc_info *esoc_info;
  1250. struct esoc_desc *esoc_desc;
  1251. const char *client_desc;
  1252. dev = &plat_priv->plat_dev->dev;
  1253. esoc_info = &plat_priv->esoc_info;
  1254. esoc_info->notify_modem_status =
  1255. of_property_read_bool(dev->of_node,
  1256. "qcom,notify-modem-status");
  1257. if (!esoc_info->notify_modem_status)
  1258. goto out;
  1259. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1260. &client_desc);
  1261. if (ret) {
  1262. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1263. } else {
  1264. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1265. if (IS_ERR_OR_NULL(esoc_desc)) {
  1266. ret = PTR_RET(esoc_desc);
  1267. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1268. ret);
  1269. goto out;
  1270. }
  1271. esoc_info->esoc_desc = esoc_desc;
  1272. }
  1273. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1274. esoc_info->modem_current_status = 0;
  1275. esoc_info->modem_notify_handler =
  1276. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1277. esoc_info->esoc_desc->name :
  1278. "modem", &plat_priv->modem_nb);
  1279. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1280. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1281. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1282. ret);
  1283. goto unreg_esoc;
  1284. }
  1285. return 0;
  1286. unreg_esoc:
  1287. if (esoc_info->esoc_desc)
  1288. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1289. out:
  1290. return ret;
  1291. }
  1292. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1293. {
  1294. struct device *dev;
  1295. struct cnss_esoc_info *esoc_info;
  1296. dev = &plat_priv->plat_dev->dev;
  1297. esoc_info = &plat_priv->esoc_info;
  1298. if (esoc_info->notify_modem_status)
  1299. subsys_notif_unregister_notifier
  1300. (esoc_info->modem_notify_handler,
  1301. &plat_priv->modem_nb);
  1302. if (esoc_info->esoc_desc)
  1303. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1304. }
  1305. #else
  1306. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1307. {
  1308. return 0;
  1309. }
  1310. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1311. #endif
  1312. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1313. {
  1314. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1315. int ret = 0;
  1316. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1317. return 0;
  1318. enable_irq(sol_gpio->dev_sol_irq);
  1319. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1320. if (ret)
  1321. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1322. ret);
  1323. return ret;
  1324. }
  1325. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1326. {
  1327. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1328. int ret = 0;
  1329. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1330. return 0;
  1331. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1332. if (ret)
  1333. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1334. ret);
  1335. disable_irq(sol_gpio->dev_sol_irq);
  1336. return ret;
  1337. }
  1338. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1339. {
  1340. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1341. if (sol_gpio->dev_sol_gpio < 0)
  1342. return -EINVAL;
  1343. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1344. }
  1345. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1346. {
  1347. struct cnss_plat_data *plat_priv = data;
  1348. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1349. sol_gpio->dev_sol_counter++;
  1350. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1351. irq, sol_gpio->dev_sol_counter);
  1352. /* Make sure abort current suspend */
  1353. cnss_pm_stay_awake(plat_priv);
  1354. cnss_pm_relax(plat_priv);
  1355. pm_system_wakeup();
  1356. cnss_bus_handle_dev_sol_irq(plat_priv);
  1357. return IRQ_HANDLED;
  1358. }
  1359. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1360. {
  1361. struct device *dev = &plat_priv->plat_dev->dev;
  1362. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1363. int ret = 0;
  1364. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1365. "wlan-dev-sol-gpio", 0);
  1366. if (sol_gpio->dev_sol_gpio < 0)
  1367. goto out;
  1368. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1369. sol_gpio->dev_sol_gpio);
  1370. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1371. if (ret) {
  1372. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1373. ret);
  1374. goto out;
  1375. }
  1376. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1377. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1378. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1379. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1380. if (ret) {
  1381. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1382. goto free_gpio;
  1383. }
  1384. return 0;
  1385. free_gpio:
  1386. gpio_free(sol_gpio->dev_sol_gpio);
  1387. out:
  1388. return ret;
  1389. }
  1390. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1391. {
  1392. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1393. if (sol_gpio->dev_sol_gpio < 0)
  1394. return;
  1395. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1396. gpio_free(sol_gpio->dev_sol_gpio);
  1397. }
  1398. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1399. {
  1400. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1401. if (sol_gpio->host_sol_gpio < 0)
  1402. return -EINVAL;
  1403. if (value)
  1404. cnss_pr_dbg("Assert host SOL GPIO\n");
  1405. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1406. return 0;
  1407. }
  1408. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1409. {
  1410. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1411. if (sol_gpio->host_sol_gpio < 0)
  1412. return -EINVAL;
  1413. return gpio_get_value(sol_gpio->host_sol_gpio);
  1414. }
  1415. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1416. {
  1417. struct device *dev = &plat_priv->plat_dev->dev;
  1418. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1419. int ret = 0;
  1420. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1421. "wlan-host-sol-gpio", 0);
  1422. if (sol_gpio->host_sol_gpio < 0)
  1423. goto out;
  1424. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1425. sol_gpio->host_sol_gpio);
  1426. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1427. if (ret) {
  1428. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1429. ret);
  1430. goto out;
  1431. }
  1432. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1433. return 0;
  1434. out:
  1435. return ret;
  1436. }
  1437. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1438. {
  1439. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1440. if (sol_gpio->host_sol_gpio < 0)
  1441. return;
  1442. gpio_free(sol_gpio->host_sol_gpio);
  1443. }
  1444. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1445. {
  1446. int ret;
  1447. ret = cnss_init_dev_sol_gpio(plat_priv);
  1448. if (ret)
  1449. goto out;
  1450. ret = cnss_init_host_sol_gpio(plat_priv);
  1451. if (ret)
  1452. goto deinit_dev_sol;
  1453. return 0;
  1454. deinit_dev_sol:
  1455. cnss_deinit_dev_sol_gpio(plat_priv);
  1456. out:
  1457. return ret;
  1458. }
  1459. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1460. {
  1461. cnss_deinit_host_sol_gpio(plat_priv);
  1462. cnss_deinit_dev_sol_gpio(plat_priv);
  1463. }
  1464. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1465. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1466. {
  1467. struct cnss_plat_data *plat_priv;
  1468. int ret = 0;
  1469. if (!subsys_desc->dev) {
  1470. cnss_pr_err("dev from subsys_desc is NULL\n");
  1471. return -ENODEV;
  1472. }
  1473. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1474. if (!plat_priv) {
  1475. cnss_pr_err("plat_priv is NULL\n");
  1476. return -ENODEV;
  1477. }
  1478. if (!plat_priv->driver_state) {
  1479. cnss_pr_dbg("subsys powerup is ignored\n");
  1480. return 0;
  1481. }
  1482. ret = cnss_bus_dev_powerup(plat_priv);
  1483. if (ret)
  1484. __pm_relax(plat_priv->recovery_ws);
  1485. return ret;
  1486. }
  1487. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1488. bool force_stop)
  1489. {
  1490. struct cnss_plat_data *plat_priv;
  1491. if (!subsys_desc->dev) {
  1492. cnss_pr_err("dev from subsys_desc is NULL\n");
  1493. return -ENODEV;
  1494. }
  1495. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1496. if (!plat_priv) {
  1497. cnss_pr_err("plat_priv is NULL\n");
  1498. return -ENODEV;
  1499. }
  1500. if (!plat_priv->driver_state) {
  1501. cnss_pr_dbg("subsys shutdown is ignored\n");
  1502. return 0;
  1503. }
  1504. return cnss_bus_dev_shutdown(plat_priv);
  1505. }
  1506. void cnss_device_crashed(struct device *dev)
  1507. {
  1508. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1509. struct cnss_subsys_info *subsys_info;
  1510. if (!plat_priv)
  1511. return;
  1512. subsys_info = &plat_priv->subsys_info;
  1513. if (subsys_info->subsys_device) {
  1514. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1515. subsys_set_crash_status(subsys_info->subsys_device, true);
  1516. subsystem_restart_dev(subsys_info->subsys_device);
  1517. }
  1518. }
  1519. EXPORT_SYMBOL(cnss_device_crashed);
  1520. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1521. {
  1522. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1523. if (!plat_priv) {
  1524. cnss_pr_err("plat_priv is NULL\n");
  1525. return;
  1526. }
  1527. cnss_bus_dev_crash_shutdown(plat_priv);
  1528. }
  1529. static int cnss_subsys_ramdump(int enable,
  1530. const struct subsys_desc *subsys_desc)
  1531. {
  1532. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1533. if (!plat_priv) {
  1534. cnss_pr_err("plat_priv is NULL\n");
  1535. return -ENODEV;
  1536. }
  1537. if (!enable)
  1538. return 0;
  1539. return cnss_bus_dev_ramdump(plat_priv);
  1540. }
  1541. static void cnss_recovery_work_handler(struct work_struct *work)
  1542. {
  1543. }
  1544. #else
  1545. static void cnss_recovery_work_handler(struct work_struct *work)
  1546. {
  1547. int ret;
  1548. struct cnss_plat_data *plat_priv =
  1549. container_of(work, struct cnss_plat_data, recovery_work);
  1550. if (!plat_priv->recovery_enabled)
  1551. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1552. cnss_bus_dev_shutdown(plat_priv);
  1553. cnss_bus_dev_ramdump(plat_priv);
  1554. msleep(POWER_RESET_MIN_DELAY_MS);
  1555. ret = cnss_bus_dev_powerup(plat_priv);
  1556. if (ret)
  1557. __pm_relax(plat_priv->recovery_ws);
  1558. return;
  1559. }
  1560. void cnss_device_crashed(struct device *dev)
  1561. {
  1562. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1563. if (!plat_priv)
  1564. return;
  1565. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1566. schedule_work(&plat_priv->recovery_work);
  1567. }
  1568. EXPORT_SYMBOL(cnss_device_crashed);
  1569. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1570. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1571. {
  1572. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1573. struct cnss_ramdump_info *ramdump_info;
  1574. if (!plat_priv)
  1575. return NULL;
  1576. ramdump_info = &plat_priv->ramdump_info;
  1577. *size = ramdump_info->ramdump_size;
  1578. return ramdump_info->ramdump_va;
  1579. }
  1580. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1581. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1582. {
  1583. switch (reason) {
  1584. case CNSS_REASON_DEFAULT:
  1585. return "DEFAULT";
  1586. case CNSS_REASON_LINK_DOWN:
  1587. return "LINK_DOWN";
  1588. case CNSS_REASON_RDDM:
  1589. return "RDDM";
  1590. case CNSS_REASON_TIMEOUT:
  1591. return "TIMEOUT";
  1592. }
  1593. return "UNKNOWN";
  1594. };
  1595. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1596. enum cnss_recovery_reason reason)
  1597. {
  1598. plat_priv->recovery_count++;
  1599. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1600. goto self_recovery;
  1601. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1602. cnss_pr_dbg("Skip device recovery\n");
  1603. return 0;
  1604. }
  1605. /* FW recovery sequence has multiple steps and firmware load requires
  1606. * linux PM in awake state. Thus hold the cnss wake source until
  1607. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1608. * time taken in this process.
  1609. */
  1610. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1611. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1612. true);
  1613. switch (reason) {
  1614. case CNSS_REASON_LINK_DOWN:
  1615. if (!cnss_bus_check_link_status(plat_priv)) {
  1616. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1617. return 0;
  1618. }
  1619. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1620. &plat_priv->ctrl_params.quirks))
  1621. goto self_recovery;
  1622. if (!cnss_bus_recover_link_down(plat_priv)) {
  1623. /* clear recovery bit here to avoid skipping
  1624. * the recovery work for RDDM later
  1625. */
  1626. clear_bit(CNSS_DRIVER_RECOVERY,
  1627. &plat_priv->driver_state);
  1628. return 0;
  1629. }
  1630. break;
  1631. case CNSS_REASON_RDDM:
  1632. cnss_bus_collect_dump_info(plat_priv, false);
  1633. break;
  1634. case CNSS_REASON_DEFAULT:
  1635. case CNSS_REASON_TIMEOUT:
  1636. break;
  1637. default:
  1638. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1639. cnss_recovery_reason_to_str(reason), reason);
  1640. break;
  1641. }
  1642. cnss_bus_device_crashed(plat_priv);
  1643. return 0;
  1644. self_recovery:
  1645. cnss_pr_dbg("Going for self recovery\n");
  1646. cnss_bus_dev_shutdown(plat_priv);
  1647. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1648. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1649. &plat_priv->ctrl_params.quirks);
  1650. cnss_bus_dev_powerup(plat_priv);
  1651. return 0;
  1652. }
  1653. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1654. void *data)
  1655. {
  1656. struct cnss_recovery_data *recovery_data = data;
  1657. int ret = 0;
  1658. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1659. cnss_recovery_reason_to_str(recovery_data->reason),
  1660. recovery_data->reason);
  1661. if (!plat_priv->driver_state) {
  1662. cnss_pr_err("Improper driver state, ignore recovery\n");
  1663. ret = -EINVAL;
  1664. goto out;
  1665. }
  1666. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1667. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1668. ret = -EINVAL;
  1669. goto out;
  1670. }
  1671. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1672. cnss_pr_err("Recovery is already in progress\n");
  1673. CNSS_ASSERT(0);
  1674. ret = -EINVAL;
  1675. goto out;
  1676. }
  1677. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1678. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1679. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1680. ret = -EINVAL;
  1681. goto out;
  1682. }
  1683. switch (plat_priv->device_id) {
  1684. case QCA6174_DEVICE_ID:
  1685. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1686. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1687. &plat_priv->driver_state)) {
  1688. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1689. ret = -EINVAL;
  1690. goto out;
  1691. }
  1692. break;
  1693. default:
  1694. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1695. set_bit(CNSS_FW_BOOT_RECOVERY,
  1696. &plat_priv->driver_state);
  1697. }
  1698. break;
  1699. }
  1700. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1701. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1702. out:
  1703. kfree(data);
  1704. return ret;
  1705. }
  1706. int cnss_self_recovery(struct device *dev,
  1707. enum cnss_recovery_reason reason)
  1708. {
  1709. cnss_schedule_recovery(dev, reason);
  1710. return 0;
  1711. }
  1712. EXPORT_SYMBOL(cnss_self_recovery);
  1713. void cnss_schedule_recovery(struct device *dev,
  1714. enum cnss_recovery_reason reason)
  1715. {
  1716. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1717. struct cnss_recovery_data *data;
  1718. int gfp = GFP_KERNEL;
  1719. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1720. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1721. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1722. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1723. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1724. return;
  1725. }
  1726. if (in_interrupt() || irqs_disabled())
  1727. gfp = GFP_ATOMIC;
  1728. data = kzalloc(sizeof(*data), gfp);
  1729. if (!data)
  1730. return;
  1731. data->reason = reason;
  1732. cnss_driver_event_post(plat_priv,
  1733. CNSS_DRIVER_EVENT_RECOVERY,
  1734. 0, data);
  1735. }
  1736. EXPORT_SYMBOL(cnss_schedule_recovery);
  1737. int cnss_force_fw_assert(struct device *dev)
  1738. {
  1739. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1740. if (!plat_priv) {
  1741. cnss_pr_err("plat_priv is NULL\n");
  1742. return -ENODEV;
  1743. }
  1744. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1745. cnss_pr_info("Forced FW assert is not supported\n");
  1746. return -EOPNOTSUPP;
  1747. }
  1748. if (cnss_bus_is_device_down(plat_priv)) {
  1749. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1750. return 0;
  1751. }
  1752. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1753. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1754. return 0;
  1755. }
  1756. if (in_interrupt() || irqs_disabled())
  1757. cnss_driver_event_post(plat_priv,
  1758. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1759. 0, NULL);
  1760. else
  1761. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1762. return 0;
  1763. }
  1764. EXPORT_SYMBOL(cnss_force_fw_assert);
  1765. int cnss_force_collect_rddm(struct device *dev)
  1766. {
  1767. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1768. unsigned int timeout;
  1769. int ret = 0;
  1770. if (!plat_priv) {
  1771. cnss_pr_err("plat_priv is NULL\n");
  1772. return -ENODEV;
  1773. }
  1774. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1775. cnss_pr_info("Force collect rddm is not supported\n");
  1776. return -EOPNOTSUPP;
  1777. }
  1778. if (cnss_bus_is_device_down(plat_priv)) {
  1779. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1780. goto wait_rddm;
  1781. }
  1782. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1783. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1784. goto wait_rddm;
  1785. }
  1786. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1787. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1788. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1789. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1790. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1791. return 0;
  1792. }
  1793. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1794. if (ret)
  1795. return ret;
  1796. wait_rddm:
  1797. reinit_completion(&plat_priv->rddm_complete);
  1798. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1799. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1800. msecs_to_jiffies(timeout));
  1801. if (!ret) {
  1802. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1803. timeout);
  1804. ret = -ETIMEDOUT;
  1805. } else if (ret > 0) {
  1806. ret = 0;
  1807. }
  1808. return ret;
  1809. }
  1810. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1811. int cnss_qmi_send_get(struct device *dev)
  1812. {
  1813. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1814. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1815. return 0;
  1816. return cnss_bus_qmi_send_get(plat_priv);
  1817. }
  1818. EXPORT_SYMBOL(cnss_qmi_send_get);
  1819. int cnss_qmi_send_put(struct device *dev)
  1820. {
  1821. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1822. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1823. return 0;
  1824. return cnss_bus_qmi_send_put(plat_priv);
  1825. }
  1826. EXPORT_SYMBOL(cnss_qmi_send_put);
  1827. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1828. int cmd_len, void *cb_ctx,
  1829. int (*cb)(void *ctx, void *event, int event_len))
  1830. {
  1831. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1832. int ret;
  1833. if (!plat_priv)
  1834. return -ENODEV;
  1835. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1836. return -EINVAL;
  1837. plat_priv->get_info_cb = cb;
  1838. plat_priv->get_info_cb_ctx = cb_ctx;
  1839. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1840. if (ret) {
  1841. plat_priv->get_info_cb = NULL;
  1842. plat_priv->get_info_cb_ctx = NULL;
  1843. }
  1844. return ret;
  1845. }
  1846. EXPORT_SYMBOL(cnss_qmi_send);
  1847. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1848. {
  1849. int ret = 0;
  1850. u32 retry = 0, timeout;
  1851. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1852. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1853. goto out;
  1854. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1855. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1856. goto out;
  1857. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  1858. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  1859. goto out;
  1860. }
  1861. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1862. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1863. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1864. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1865. CNSS_ASSERT(0);
  1866. return -EINVAL;
  1867. }
  1868. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1869. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1870. break;
  1871. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1872. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1873. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1874. CNSS_ASSERT(0);
  1875. ret = -EINVAL;
  1876. goto mark_cal_fail;
  1877. }
  1878. }
  1879. switch (plat_priv->device_id) {
  1880. case QCA6290_DEVICE_ID:
  1881. case QCA6390_DEVICE_ID:
  1882. case QCA6490_DEVICE_ID:
  1883. case KIWI_DEVICE_ID:
  1884. case MANGO_DEVICE_ID:
  1885. case PEACH_DEVICE_ID:
  1886. break;
  1887. default:
  1888. cnss_pr_err("Not supported for device ID 0x%lx\n",
  1889. plat_priv->device_id);
  1890. ret = -EINVAL;
  1891. goto mark_cal_fail;
  1892. }
  1893. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1894. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1895. timeout = cnss_get_timeout(plat_priv,
  1896. CNSS_TIMEOUT_CALIBRATION);
  1897. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1898. timeout / 1000);
  1899. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1900. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1901. msecs_to_jiffies(timeout));
  1902. }
  1903. reinit_completion(&plat_priv->cal_complete);
  1904. ret = cnss_bus_dev_powerup(plat_priv);
  1905. mark_cal_fail:
  1906. if (ret) {
  1907. complete(&plat_priv->cal_complete);
  1908. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1909. /* Set CBC done in driver state to mark attempt and note error
  1910. * since calibration cannot be retried at boot.
  1911. */
  1912. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1913. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1914. if (plat_priv->device_id == QCA6174_DEVICE_ID ||
  1915. plat_priv->device_id == QCN7605_DEVICE_ID) {
  1916. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1917. goto out;
  1918. cnss_pr_info("Schedule WLAN driver load\n");
  1919. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1920. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1921. 0);
  1922. }
  1923. }
  1924. out:
  1925. return ret;
  1926. }
  1927. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1928. void *data)
  1929. {
  1930. struct cnss_cal_info *cal_info = data;
  1931. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1932. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1933. goto out;
  1934. switch (cal_info->cal_status) {
  1935. case CNSS_CAL_DONE:
  1936. cnss_pr_dbg("Calibration completed successfully\n");
  1937. plat_priv->cal_done = true;
  1938. break;
  1939. case CNSS_CAL_TIMEOUT:
  1940. case CNSS_CAL_FAILURE:
  1941. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1942. cal_info->cal_status);
  1943. break;
  1944. default:
  1945. cnss_pr_err("Unknown calibration status: %u\n",
  1946. cal_info->cal_status);
  1947. break;
  1948. }
  1949. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1950. cnss_bus_free_qdss_mem(plat_priv);
  1951. cnss_release_antenna_sharing(plat_priv);
  1952. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  1953. goto skip_shutdown;
  1954. cnss_bus_dev_shutdown(plat_priv);
  1955. msleep(POWER_RESET_MIN_DELAY_MS);
  1956. skip_shutdown:
  1957. complete(&plat_priv->cal_complete);
  1958. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1959. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1960. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1961. cnss_cal_mem_upload_to_file(plat_priv);
  1962. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1963. goto out;
  1964. cnss_pr_dbg("Schedule WLAN driver load\n");
  1965. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1966. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1967. 0);
  1968. }
  1969. out:
  1970. kfree(data);
  1971. return 0;
  1972. }
  1973. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1974. {
  1975. int ret;
  1976. ret = cnss_bus_dev_powerup(plat_priv);
  1977. if (ret)
  1978. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1979. return ret;
  1980. }
  1981. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1982. {
  1983. cnss_bus_dev_shutdown(plat_priv);
  1984. return 0;
  1985. }
  1986. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1987. {
  1988. int ret = 0;
  1989. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1990. if (ret < 0)
  1991. return ret;
  1992. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1993. }
  1994. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1995. u32 mem_seg_len, u64 pa, u32 size)
  1996. {
  1997. int i = 0;
  1998. u64 offset = 0;
  1999. void *va = NULL;
  2000. u64 local_pa;
  2001. u32 local_size;
  2002. for (i = 0; i < mem_seg_len; i++) {
  2003. local_pa = (u64)fw_mem[i].pa;
  2004. local_size = (u32)fw_mem[i].size;
  2005. if (pa == local_pa && size <= local_size) {
  2006. va = fw_mem[i].va;
  2007. break;
  2008. }
  2009. if (pa > local_pa &&
  2010. pa < local_pa + local_size &&
  2011. pa + size <= local_pa + local_size) {
  2012. offset = pa - local_pa;
  2013. va = fw_mem[i].va + offset;
  2014. break;
  2015. }
  2016. }
  2017. return va;
  2018. }
  2019. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  2020. void *data)
  2021. {
  2022. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2023. struct cnss_fw_mem *fw_mem_seg;
  2024. int ret = 0L;
  2025. void *va = NULL;
  2026. u32 i, fw_mem_seg_len;
  2027. switch (event_data->mem_type) {
  2028. case QMI_WLFW_MEM_TYPE_DDR_V01:
  2029. if (!plat_priv->fw_mem_seg_len)
  2030. goto invalid_mem_save;
  2031. fw_mem_seg = plat_priv->fw_mem;
  2032. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  2033. break;
  2034. case QMI_WLFW_MEM_QDSS_V01:
  2035. if (!plat_priv->qdss_mem_seg_len)
  2036. goto invalid_mem_save;
  2037. fw_mem_seg = plat_priv->qdss_mem;
  2038. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  2039. break;
  2040. default:
  2041. goto invalid_mem_save;
  2042. }
  2043. for (i = 0; i < event_data->mem_seg_len; i++) {
  2044. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  2045. event_data->mem_seg[i].addr,
  2046. event_data->mem_seg[i].size);
  2047. if (!va) {
  2048. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  2049. &event_data->mem_seg[i].addr,
  2050. event_data->mem_type);
  2051. ret = -EINVAL;
  2052. break;
  2053. }
  2054. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  2055. event_data->file_name,
  2056. event_data->mem_seg[i].size);
  2057. if (ret < 0) {
  2058. cnss_pr_err("Fail to save fw mem data: %d\n",
  2059. ret);
  2060. break;
  2061. }
  2062. }
  2063. kfree(data);
  2064. return ret;
  2065. invalid_mem_save:
  2066. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  2067. event_data->mem_type);
  2068. kfree(data);
  2069. return -EINVAL;
  2070. }
  2071. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  2072. {
  2073. cnss_bus_free_qdss_mem(plat_priv);
  2074. return 0;
  2075. }
  2076. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  2077. void *data)
  2078. {
  2079. int ret = 0;
  2080. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2081. if (!plat_priv)
  2082. return -ENODEV;
  2083. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  2084. event_data->total_size);
  2085. kfree(data);
  2086. return ret;
  2087. }
  2088. static void cnss_driver_event_work(struct work_struct *work)
  2089. {
  2090. struct cnss_plat_data *plat_priv =
  2091. container_of(work, struct cnss_plat_data, event_work);
  2092. struct cnss_driver_event *event;
  2093. unsigned long flags;
  2094. int ret = 0;
  2095. if (!plat_priv) {
  2096. cnss_pr_err("plat_priv is NULL!\n");
  2097. return;
  2098. }
  2099. cnss_pm_stay_awake(plat_priv);
  2100. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2101. while (!list_empty(&plat_priv->event_list)) {
  2102. event = list_first_entry(&plat_priv->event_list,
  2103. struct cnss_driver_event, list);
  2104. list_del(&event->list);
  2105. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2106. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  2107. cnss_driver_event_to_str(event->type),
  2108. event->sync ? "-sync" : "", event->type,
  2109. plat_priv->driver_state);
  2110. switch (event->type) {
  2111. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  2112. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  2113. break;
  2114. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  2115. ret = cnss_wlfw_server_exit(plat_priv);
  2116. break;
  2117. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  2118. ret = cnss_bus_alloc_fw_mem(plat_priv);
  2119. if (ret)
  2120. break;
  2121. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  2122. break;
  2123. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  2124. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  2125. break;
  2126. case CNSS_DRIVER_EVENT_FW_READY:
  2127. ret = cnss_fw_ready_hdlr(plat_priv);
  2128. break;
  2129. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  2130. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  2131. break;
  2132. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  2133. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  2134. event->data);
  2135. break;
  2136. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  2137. ret = cnss_bus_register_driver_hdlr(plat_priv,
  2138. event->data);
  2139. break;
  2140. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  2141. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  2142. break;
  2143. case CNSS_DRIVER_EVENT_RECOVERY:
  2144. ret = cnss_driver_recovery_hdlr(plat_priv,
  2145. event->data);
  2146. break;
  2147. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  2148. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  2149. break;
  2150. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  2151. set_bit(CNSS_DRIVER_IDLE_RESTART,
  2152. &plat_priv->driver_state);
  2153. fallthrough;
  2154. case CNSS_DRIVER_EVENT_POWER_UP:
  2155. ret = cnss_power_up_hdlr(plat_priv);
  2156. break;
  2157. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  2158. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  2159. &plat_priv->driver_state);
  2160. fallthrough;
  2161. case CNSS_DRIVER_EVENT_POWER_DOWN:
  2162. ret = cnss_power_down_hdlr(plat_priv);
  2163. break;
  2164. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  2165. ret = cnss_process_wfc_call_ind_event(plat_priv,
  2166. event->data);
  2167. break;
  2168. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  2169. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  2170. event->data);
  2171. break;
  2172. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  2173. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  2174. break;
  2175. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  2176. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  2177. event->data);
  2178. break;
  2179. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  2180. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  2181. break;
  2182. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  2183. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  2184. event->data);
  2185. break;
  2186. default:
  2187. cnss_pr_err("Invalid driver event type: %d",
  2188. event->type);
  2189. kfree(event);
  2190. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2191. continue;
  2192. }
  2193. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2194. if (event->sync) {
  2195. event->ret = ret;
  2196. complete(&event->complete);
  2197. continue;
  2198. }
  2199. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2200. kfree(event);
  2201. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2202. }
  2203. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2204. cnss_pm_relax(plat_priv);
  2205. }
  2206. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  2207. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2208. {
  2209. int ret = 0;
  2210. struct cnss_subsys_info *subsys_info;
  2211. subsys_info = &plat_priv->subsys_info;
  2212. subsys_info->subsys_desc.name = plat_priv->device_name;
  2213. subsys_info->subsys_desc.owner = THIS_MODULE;
  2214. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  2215. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  2216. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  2217. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  2218. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  2219. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  2220. if (IS_ERR(subsys_info->subsys_device)) {
  2221. ret = PTR_ERR(subsys_info->subsys_device);
  2222. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  2223. goto out;
  2224. }
  2225. subsys_info->subsys_handle =
  2226. subsystem_get(subsys_info->subsys_desc.name);
  2227. if (!subsys_info->subsys_handle) {
  2228. cnss_pr_err("Failed to get subsys_handle!\n");
  2229. ret = -EINVAL;
  2230. goto unregister_subsys;
  2231. } else if (IS_ERR(subsys_info->subsys_handle)) {
  2232. ret = PTR_ERR(subsys_info->subsys_handle);
  2233. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  2234. goto unregister_subsys;
  2235. }
  2236. return 0;
  2237. unregister_subsys:
  2238. subsys_unregister(subsys_info->subsys_device);
  2239. out:
  2240. return ret;
  2241. }
  2242. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2243. {
  2244. struct cnss_subsys_info *subsys_info;
  2245. subsys_info = &plat_priv->subsys_info;
  2246. subsystem_put(subsys_info->subsys_handle);
  2247. subsys_unregister(subsys_info->subsys_device);
  2248. }
  2249. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2250. {
  2251. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2252. return create_ramdump_device(subsys_info->subsys_desc.name,
  2253. subsys_info->subsys_desc.dev);
  2254. }
  2255. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2256. void *ramdump_dev)
  2257. {
  2258. destroy_ramdump_device(ramdump_dev);
  2259. }
  2260. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2261. {
  2262. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2263. struct ramdump_segment segment;
  2264. memset(&segment, 0, sizeof(segment));
  2265. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2266. segment.size = ramdump_info->ramdump_size;
  2267. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2268. }
  2269. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2270. {
  2271. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2272. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2273. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2274. struct ramdump_segment *ramdump_segs, *s;
  2275. struct cnss_dump_meta_info meta_info = {0};
  2276. int i, ret = 0;
  2277. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2278. sizeof(*ramdump_segs),
  2279. GFP_KERNEL);
  2280. if (!ramdump_segs)
  2281. return -ENOMEM;
  2282. s = ramdump_segs + 1;
  2283. for (i = 0; i < dump_data->nentries; i++) {
  2284. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2285. cnss_pr_err("Unsupported dump type: %d",
  2286. dump_seg->type);
  2287. continue;
  2288. }
  2289. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2290. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2291. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2292. }
  2293. meta_info.entry[dump_seg->type].entry_num++;
  2294. s->address = dump_seg->address;
  2295. s->v_address = (void __iomem *)dump_seg->v_address;
  2296. s->size = dump_seg->size;
  2297. s++;
  2298. dump_seg++;
  2299. }
  2300. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2301. meta_info.version = CNSS_RAMDUMP_VERSION;
  2302. meta_info.chipset = plat_priv->device_id;
  2303. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2304. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2305. ramdump_segs->size = sizeof(meta_info);
  2306. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2307. dump_data->nentries + 1);
  2308. kfree(ramdump_segs);
  2309. return ret;
  2310. }
  2311. #else
  2312. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2313. void *data)
  2314. {
  2315. struct cnss_plat_data *plat_priv =
  2316. container_of(nb, struct cnss_plat_data, panic_nb);
  2317. cnss_bus_dev_crash_shutdown(plat_priv);
  2318. return NOTIFY_DONE;
  2319. }
  2320. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2321. {
  2322. int ret;
  2323. if (!plat_priv)
  2324. return -ENODEV;
  2325. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2326. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2327. &plat_priv->panic_nb);
  2328. if (ret) {
  2329. cnss_pr_err("Failed to register panic handler\n");
  2330. return -EINVAL;
  2331. }
  2332. return 0;
  2333. }
  2334. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2335. {
  2336. int ret;
  2337. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2338. &plat_priv->panic_nb);
  2339. if (ret)
  2340. cnss_pr_err("Failed to unregister panic handler\n");
  2341. }
  2342. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2343. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2344. {
  2345. return &plat_priv->plat_dev->dev;
  2346. }
  2347. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2348. void *ramdump_dev)
  2349. {
  2350. }
  2351. #endif
  2352. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2353. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2354. {
  2355. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2356. struct qcom_dump_segment segment;
  2357. struct list_head head;
  2358. INIT_LIST_HEAD(&head);
  2359. memset(&segment, 0, sizeof(segment));
  2360. segment.va = ramdump_info->ramdump_va;
  2361. segment.size = ramdump_info->ramdump_size;
  2362. list_add(&segment.node, &head);
  2363. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2364. }
  2365. #else
  2366. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2367. {
  2368. return 0;
  2369. }
  2370. /* Using completion event inside dynamically allocated ramdump_desc
  2371. * may result a race between freeing the event after setting it to
  2372. * complete inside dev coredump free callback and the thread that is
  2373. * waiting for completion.
  2374. */
  2375. DECLARE_COMPLETION(dump_done);
  2376. #define TIMEOUT_SAVE_DUMP_MS 30000
  2377. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2378. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2379. { \
  2380. if (class == ELFCLASS32) \
  2381. return sizeof(struct elf32_##__xhdr); \
  2382. else \
  2383. return sizeof(struct elf64_##__xhdr); \
  2384. }
  2385. SIZEOF_ELF_STRUCT(phdr)
  2386. SIZEOF_ELF_STRUCT(hdr)
  2387. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2388. do { \
  2389. if (class == ELFCLASS32) \
  2390. ((struct elf32_##__xhdr *)arg)->member = value; \
  2391. else \
  2392. ((struct elf64_##__xhdr *)arg)->member = value; \
  2393. } while (0)
  2394. #define set_ehdr_property(arg, class, member, value) \
  2395. set_xhdr_property(hdr, arg, class, member, value)
  2396. #define set_phdr_property(arg, class, member, value) \
  2397. set_xhdr_property(phdr, arg, class, member, value)
  2398. /* These replace qcom_ramdump driver APIs called from common API
  2399. * cnss_do_elf_dump() by the ones defined here.
  2400. */
  2401. #define qcom_dump_segment cnss_qcom_dump_segment
  2402. #define qcom_elf_dump cnss_qcom_elf_dump
  2403. #define dump_enabled cnss_dump_enabled
  2404. struct cnss_qcom_dump_segment {
  2405. struct list_head node;
  2406. dma_addr_t da;
  2407. void *va;
  2408. size_t size;
  2409. };
  2410. struct cnss_qcom_ramdump_desc {
  2411. void *data;
  2412. struct completion dump_done;
  2413. };
  2414. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2415. void *data, size_t datalen)
  2416. {
  2417. struct cnss_qcom_ramdump_desc *desc = data;
  2418. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2419. datalen);
  2420. }
  2421. static void cnss_qcom_devcd_freev(void *data)
  2422. {
  2423. struct cnss_qcom_ramdump_desc *desc = data;
  2424. cnss_pr_dbg("Free dump data for dev coredump\n");
  2425. complete(&dump_done);
  2426. vfree(desc->data);
  2427. kfree(desc);
  2428. }
  2429. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2430. gfp_t gfp)
  2431. {
  2432. struct cnss_qcom_ramdump_desc *desc;
  2433. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2434. int ret;
  2435. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2436. if (!desc)
  2437. return -ENOMEM;
  2438. desc->data = data;
  2439. reinit_completion(&dump_done);
  2440. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2441. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2442. ret = wait_for_completion_timeout(&dump_done,
  2443. msecs_to_jiffies(timeout));
  2444. if (!ret)
  2445. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2446. timeout);
  2447. return ret ? 0 : -ETIMEDOUT;
  2448. }
  2449. /* Since the elf32 and elf64 identification is identical apart from
  2450. * the class, use elf32 by default.
  2451. */
  2452. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2453. {
  2454. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2455. ehdr->e_ident[EI_CLASS] = class;
  2456. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2457. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2458. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2459. }
  2460. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2461. unsigned char class)
  2462. {
  2463. struct cnss_qcom_dump_segment *segment;
  2464. void *phdr, *ehdr;
  2465. size_t data_size, offset;
  2466. int phnum = 0;
  2467. void *data;
  2468. void __iomem *ptr;
  2469. if (!segs || list_empty(segs))
  2470. return -EINVAL;
  2471. data_size = sizeof_elf_hdr(class);
  2472. list_for_each_entry(segment, segs, node) {
  2473. data_size += sizeof_elf_phdr(class) + segment->size;
  2474. phnum++;
  2475. }
  2476. data = vmalloc(data_size);
  2477. if (!data)
  2478. return -ENOMEM;
  2479. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2480. ehdr = data;
  2481. memset(ehdr, 0, sizeof_elf_hdr(class));
  2482. init_elf_identification(ehdr, class);
  2483. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2484. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2485. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2486. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2487. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2488. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2489. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2490. phdr = data + sizeof_elf_hdr(class);
  2491. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2492. list_for_each_entry(segment, segs, node) {
  2493. memset(phdr, 0, sizeof_elf_phdr(class));
  2494. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2495. set_phdr_property(phdr, class, p_offset, offset);
  2496. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2497. set_phdr_property(phdr, class, p_paddr, segment->da);
  2498. set_phdr_property(phdr, class, p_filesz, segment->size);
  2499. set_phdr_property(phdr, class, p_memsz, segment->size);
  2500. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2501. set_phdr_property(phdr, class, p_align, 0);
  2502. if (segment->va) {
  2503. memcpy(data + offset, segment->va, segment->size);
  2504. } else {
  2505. ptr = devm_ioremap(dev, segment->da, segment->size);
  2506. if (!ptr) {
  2507. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2508. &segment->da, segment->size);
  2509. memset(data + offset, 0xff, segment->size);
  2510. } else {
  2511. memcpy_fromio(data + offset, ptr,
  2512. segment->size);
  2513. }
  2514. }
  2515. offset += segment->size;
  2516. phdr += sizeof_elf_phdr(class);
  2517. }
  2518. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2519. }
  2520. /* Saving dump to file system is always needed in this case. */
  2521. static bool cnss_dump_enabled(void)
  2522. {
  2523. return true;
  2524. }
  2525. #endif /* CONFIG_QCOM_RAMDUMP */
  2526. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2527. {
  2528. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2529. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2530. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2531. struct qcom_dump_segment *seg;
  2532. struct cnss_dump_meta_info meta_info = {0};
  2533. struct list_head head;
  2534. int i, ret = 0;
  2535. if (!dump_enabled()) {
  2536. cnss_pr_info("Dump collection is not enabled\n");
  2537. return ret;
  2538. }
  2539. INIT_LIST_HEAD(&head);
  2540. for (i = 0; i < dump_data->nentries; i++) {
  2541. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2542. cnss_pr_err("Unsupported dump type: %d",
  2543. dump_seg->type);
  2544. continue;
  2545. }
  2546. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2547. if (!seg) {
  2548. cnss_pr_err("%s: Failed to allocate mem for seg %d\n",
  2549. __func__, i);
  2550. continue;
  2551. }
  2552. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2553. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2554. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2555. }
  2556. meta_info.entry[dump_seg->type].entry_num++;
  2557. seg->da = dump_seg->address;
  2558. seg->va = dump_seg->v_address;
  2559. seg->size = dump_seg->size;
  2560. list_add_tail(&seg->node, &head);
  2561. dump_seg++;
  2562. }
  2563. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2564. if (!seg) {
  2565. cnss_pr_err("%s: Failed to allocate mem for elf ramdump seg\n",
  2566. __func__);
  2567. goto skip_elf_dump;
  2568. }
  2569. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2570. meta_info.version = CNSS_RAMDUMP_VERSION;
  2571. meta_info.chipset = plat_priv->device_id;
  2572. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2573. seg->va = &meta_info;
  2574. seg->size = sizeof(meta_info);
  2575. list_add(&seg->node, &head);
  2576. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2577. skip_elf_dump:
  2578. while (!list_empty(&head)) {
  2579. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2580. list_del(&seg->node);
  2581. kfree(seg);
  2582. }
  2583. return ret;
  2584. }
  2585. #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
  2586. int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
  2587. struct cnss_ssr_driver_dump_entry *ssr_entry,
  2588. size_t num_entries_loaded)
  2589. {
  2590. struct qcom_dump_segment *seg;
  2591. struct cnss_host_dump_meta_info meta_info = {0};
  2592. struct list_head head;
  2593. int dev_ret = 0;
  2594. struct device *new_device;
  2595. static const char * const wlan_str[] = {
  2596. [CNSS_HOST_WLAN_LOGS] = "wlan_logs",
  2597. [CNSS_HOST_HTC_CREDIT] = "htc_credit",
  2598. [CNSS_HOST_WMI_TX_CMP] = "wmi_tx_cmp",
  2599. [CNSS_HOST_WMI_COMMAND_LOG] = "wmi_command_log",
  2600. [CNSS_HOST_WMI_EVENT_LOG] = "wmi_event_log",
  2601. [CNSS_HOST_WMI_RX_EVENT] = "wmi_rx_event",
  2602. [CNSS_HOST_HAL_SOC] = "hal_soc",
  2603. [CNSS_HOST_GWLAN_LOGGING] = "gwlan_logging",
  2604. [CNSS_HOST_WMI_DEBUG_LOG_INFO] = "wmi_debug_log_info",
  2605. [CNSS_HOST_HTC_CREDIT_IDX] = "htc_credit_history_idx",
  2606. [CNSS_HOST_HTC_CREDIT_LEN] = "htc_credit_history_length",
  2607. [CNSS_HOST_WMI_TX_CMP_IDX] = "wmi_tx_cmp_idx",
  2608. [CNSS_HOST_WMI_COMMAND_LOG_IDX] = "wmi_command_log_idx",
  2609. [CNSS_HOST_WMI_EVENT_LOG_IDX] = "wmi_event_log_idx",
  2610. [CNSS_HOST_WMI_RX_EVENT_IDX] = "wmi_rx_event_idx",
  2611. [CNSS_HOST_HIF_CE_DESC_HISTORY] = "hif_ce_desc_history",
  2612. [CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF] = "hif_ce_desc_history_buff",
  2613. [CNSS_HOST_HANG_EVENT_DATA] = "hang_event_data"
  2614. };
  2615. int i;
  2616. int ret = 0;
  2617. enum cnss_host_dump_type j;
  2618. if (!dump_enabled()) {
  2619. cnss_pr_info("Dump collection is not enabled\n");
  2620. return ret;
  2621. }
  2622. new_device = kcalloc(1, sizeof(*new_device), GFP_KERNEL);
  2623. if (!new_device) {
  2624. cnss_pr_err("Failed to alloc device mem\n");
  2625. return -ENOMEM;
  2626. }
  2627. device_initialize(new_device);
  2628. dev_set_name(new_device, "wlan_driver");
  2629. dev_ret = device_add(new_device);
  2630. if (dev_ret) {
  2631. cnss_pr_err("Failed to add new device\n");
  2632. goto put_device;
  2633. }
  2634. INIT_LIST_HEAD(&head);
  2635. for (i = 0; i < num_entries_loaded; i++) {
  2636. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2637. if (!seg) {
  2638. cnss_pr_err("Failed to alloc seg entry %d\n", i);
  2639. continue;
  2640. }
  2641. seg->va = ssr_entry[i].buffer_pointer;
  2642. seg->da = (dma_addr_t)ssr_entry[i].buffer_pointer;
  2643. seg->size = ssr_entry[i].buffer_size;
  2644. for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
  2645. if (strncmp(ssr_entry[i].region_name, wlan_str[j],
  2646. strlen(wlan_str[j])) == 0) {
  2647. meta_info.entry[i].type = j;
  2648. }
  2649. }
  2650. meta_info.entry[i].entry_start = i + 1;
  2651. meta_info.entry[i].entry_num++;
  2652. list_add_tail(&seg->node, &head);
  2653. }
  2654. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2655. if (!seg) {
  2656. cnss_pr_err("%s: Failed to allocate mem for host dump seg\n",
  2657. __func__);
  2658. goto skip_host_dump;
  2659. }
  2660. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2661. meta_info.version = CNSS_RAMDUMP_VERSION;
  2662. meta_info.chipset = plat_priv->device_id;
  2663. meta_info.total_entries = num_entries_loaded;
  2664. seg->va = &meta_info;
  2665. seg->da = (dma_addr_t)&meta_info;
  2666. seg->size = sizeof(meta_info);
  2667. list_add(&seg->node, &head);
  2668. ret = qcom_elf_dump(&head, new_device, ELF_CLASS);
  2669. skip_host_dump:
  2670. while (!list_empty(&head)) {
  2671. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2672. list_del(&seg->node);
  2673. kfree(seg);
  2674. }
  2675. device_del(new_device);
  2676. put_device:
  2677. put_device(new_device);
  2678. kfree(new_device);
  2679. return ret;
  2680. }
  2681. #endif
  2682. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2683. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2684. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2685. {
  2686. struct cnss_ramdump_info *ramdump_info;
  2687. struct msm_dump_entry dump_entry;
  2688. ramdump_info = &plat_priv->ramdump_info;
  2689. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2690. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2691. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2692. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2693. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2694. sizeof(ramdump_info->dump_data.name));
  2695. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2696. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2697. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2698. &dump_entry);
  2699. }
  2700. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2701. {
  2702. int ret = 0;
  2703. struct device *dev;
  2704. struct cnss_ramdump_info *ramdump_info;
  2705. u32 ramdump_size = 0;
  2706. dev = &plat_priv->plat_dev->dev;
  2707. ramdump_info = &plat_priv->ramdump_info;
  2708. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2709. /* dt type: legacy or converged */
  2710. ret = of_property_read_u32(dev->of_node,
  2711. "qcom,wlan-ramdump-dynamic",
  2712. &ramdump_size);
  2713. } else {
  2714. ret = of_property_read_u32(plat_priv->dev_node,
  2715. "qcom,wlan-ramdump-dynamic",
  2716. &ramdump_size);
  2717. }
  2718. if (ret == 0) {
  2719. ramdump_info->ramdump_va =
  2720. dma_alloc_coherent(dev, ramdump_size,
  2721. &ramdump_info->ramdump_pa,
  2722. GFP_KERNEL);
  2723. if (ramdump_info->ramdump_va)
  2724. ramdump_info->ramdump_size = ramdump_size;
  2725. }
  2726. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2727. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2728. if (ramdump_info->ramdump_size == 0) {
  2729. cnss_pr_info("Ramdump will not be collected");
  2730. goto out;
  2731. }
  2732. ret = cnss_init_dump_entry(plat_priv);
  2733. if (ret) {
  2734. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2735. goto free_ramdump;
  2736. }
  2737. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2738. if (!ramdump_info->ramdump_dev) {
  2739. cnss_pr_err("Failed to create ramdump device!");
  2740. ret = -ENOMEM;
  2741. goto free_ramdump;
  2742. }
  2743. return 0;
  2744. free_ramdump:
  2745. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2746. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2747. out:
  2748. return ret;
  2749. }
  2750. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2751. {
  2752. struct device *dev;
  2753. struct cnss_ramdump_info *ramdump_info;
  2754. dev = &plat_priv->plat_dev->dev;
  2755. ramdump_info = &plat_priv->ramdump_info;
  2756. if (ramdump_info->ramdump_dev)
  2757. cnss_destroy_ramdump_device(plat_priv,
  2758. ramdump_info->ramdump_dev);
  2759. if (ramdump_info->ramdump_va)
  2760. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2761. ramdump_info->ramdump_va,
  2762. ramdump_info->ramdump_pa);
  2763. }
  2764. /**
  2765. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2766. * @ret: Error returned by msm_dump_data_register_nominidump
  2767. *
  2768. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2769. * ignore failure.
  2770. *
  2771. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2772. */
  2773. static int cnss_ignore_dump_data_reg_fail(int ret)
  2774. {
  2775. return ret;
  2776. }
  2777. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2778. {
  2779. int ret = 0;
  2780. struct cnss_ramdump_info_v2 *info_v2;
  2781. struct cnss_dump_data *dump_data;
  2782. struct msm_dump_entry dump_entry;
  2783. struct device *dev = &plat_priv->plat_dev->dev;
  2784. u32 ramdump_size = 0;
  2785. info_v2 = &plat_priv->ramdump_info_v2;
  2786. dump_data = &info_v2->dump_data;
  2787. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2788. /* dt type: legacy or converged */
  2789. ret = of_property_read_u32(dev->of_node,
  2790. "qcom,wlan-ramdump-dynamic",
  2791. &ramdump_size);
  2792. } else {
  2793. ret = of_property_read_u32(plat_priv->dev_node,
  2794. "qcom,wlan-ramdump-dynamic",
  2795. &ramdump_size);
  2796. }
  2797. if (ret == 0)
  2798. info_v2->ramdump_size = ramdump_size;
  2799. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2800. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2801. if (!info_v2->dump_data_vaddr)
  2802. return -ENOMEM;
  2803. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2804. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2805. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2806. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2807. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2808. sizeof(dump_data->name));
  2809. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2810. dump_entry.addr = virt_to_phys(dump_data);
  2811. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2812. &dump_entry);
  2813. if (ret) {
  2814. ret = cnss_ignore_dump_data_reg_fail(ret);
  2815. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2816. ret ? "Error" : "Ignoring", ret);
  2817. goto free_ramdump;
  2818. }
  2819. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2820. if (!info_v2->ramdump_dev) {
  2821. cnss_pr_err("Failed to create ramdump device!\n");
  2822. ret = -ENOMEM;
  2823. goto free_ramdump;
  2824. }
  2825. return 0;
  2826. free_ramdump:
  2827. kfree(info_v2->dump_data_vaddr);
  2828. info_v2->dump_data_vaddr = NULL;
  2829. return ret;
  2830. }
  2831. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2832. {
  2833. struct cnss_ramdump_info_v2 *info_v2;
  2834. info_v2 = &plat_priv->ramdump_info_v2;
  2835. if (info_v2->ramdump_dev)
  2836. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2837. kfree(info_v2->dump_data_vaddr);
  2838. info_v2->dump_data_vaddr = NULL;
  2839. info_v2->dump_data_valid = false;
  2840. }
  2841. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2842. {
  2843. int ret = 0;
  2844. switch (plat_priv->device_id) {
  2845. case QCA6174_DEVICE_ID:
  2846. ret = cnss_register_ramdump_v1(plat_priv);
  2847. break;
  2848. case QCA6290_DEVICE_ID:
  2849. case QCA6390_DEVICE_ID:
  2850. case QCN7605_DEVICE_ID:
  2851. case QCA6490_DEVICE_ID:
  2852. case KIWI_DEVICE_ID:
  2853. case MANGO_DEVICE_ID:
  2854. case PEACH_DEVICE_ID:
  2855. ret = cnss_register_ramdump_v2(plat_priv);
  2856. break;
  2857. default:
  2858. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2859. ret = -ENODEV;
  2860. break;
  2861. }
  2862. return ret;
  2863. }
  2864. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2865. {
  2866. switch (plat_priv->device_id) {
  2867. case QCA6174_DEVICE_ID:
  2868. cnss_unregister_ramdump_v1(plat_priv);
  2869. break;
  2870. case QCA6290_DEVICE_ID:
  2871. case QCA6390_DEVICE_ID:
  2872. case QCN7605_DEVICE_ID:
  2873. case QCA6490_DEVICE_ID:
  2874. case KIWI_DEVICE_ID:
  2875. case MANGO_DEVICE_ID:
  2876. case PEACH_DEVICE_ID:
  2877. cnss_unregister_ramdump_v2(plat_priv);
  2878. break;
  2879. default:
  2880. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2881. break;
  2882. }
  2883. }
  2884. #else
  2885. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2886. {
  2887. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2888. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2889. struct device *dev = &plat_priv->plat_dev->dev;
  2890. u32 ramdump_size = 0;
  2891. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2892. &ramdump_size) == 0)
  2893. info_v2->ramdump_size = ramdump_size;
  2894. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2895. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2896. if (!info_v2->dump_data_vaddr)
  2897. return -ENOMEM;
  2898. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2899. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2900. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2901. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2902. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2903. sizeof(dump_data->name));
  2904. info_v2->ramdump_dev = dev;
  2905. return 0;
  2906. }
  2907. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2908. {
  2909. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2910. info_v2->ramdump_dev = NULL;
  2911. kfree(info_v2->dump_data_vaddr);
  2912. info_v2->dump_data_vaddr = NULL;
  2913. info_v2->dump_data_valid = false;
  2914. }
  2915. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2916. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2917. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2918. phys_addr_t *pa, unsigned long attrs)
  2919. {
  2920. struct sg_table sgt;
  2921. int ret;
  2922. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2923. if (ret) {
  2924. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2925. va, &dma, size, attrs);
  2926. return -EINVAL;
  2927. }
  2928. *pa = page_to_phys(sg_page(sgt.sgl));
  2929. sg_free_table(&sgt);
  2930. return 0;
  2931. }
  2932. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2933. enum cnss_fw_dump_type type, int seg_no,
  2934. void *va, phys_addr_t pa, size_t size)
  2935. {
  2936. struct md_region md_entry;
  2937. int ret;
  2938. switch (type) {
  2939. case CNSS_FW_IMAGE:
  2940. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2941. seg_no);
  2942. break;
  2943. case CNSS_FW_RDDM:
  2944. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2945. seg_no);
  2946. break;
  2947. case CNSS_FW_REMOTE_HEAP:
  2948. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2949. seg_no);
  2950. break;
  2951. default:
  2952. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2953. return -EINVAL;
  2954. }
  2955. md_entry.phys_addr = pa;
  2956. md_entry.virt_addr = (uintptr_t)va;
  2957. md_entry.size = size;
  2958. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2959. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2960. md_entry.name, va, &pa, size);
  2961. ret = msm_minidump_add_region(&md_entry);
  2962. if (ret < 0)
  2963. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2964. return ret;
  2965. }
  2966. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2967. enum cnss_fw_dump_type type, int seg_no,
  2968. void *va, phys_addr_t pa, size_t size)
  2969. {
  2970. struct md_region md_entry;
  2971. int ret;
  2972. switch (type) {
  2973. case CNSS_FW_IMAGE:
  2974. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2975. seg_no);
  2976. break;
  2977. case CNSS_FW_RDDM:
  2978. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2979. seg_no);
  2980. break;
  2981. case CNSS_FW_REMOTE_HEAP:
  2982. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2983. seg_no);
  2984. break;
  2985. default:
  2986. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2987. return -EINVAL;
  2988. }
  2989. md_entry.phys_addr = pa;
  2990. md_entry.virt_addr = (uintptr_t)va;
  2991. md_entry.size = size;
  2992. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2993. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2994. md_entry.name, va, &pa, size);
  2995. ret = msm_minidump_remove_region(&md_entry);
  2996. if (ret)
  2997. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2998. ret);
  2999. return ret;
  3000. }
  3001. #else
  3002. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  3003. phys_addr_t *pa, unsigned long attrs)
  3004. {
  3005. return 0;
  3006. }
  3007. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3008. enum cnss_fw_dump_type type, int seg_no,
  3009. void *va, phys_addr_t pa, size_t size)
  3010. {
  3011. return 0;
  3012. }
  3013. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3014. enum cnss_fw_dump_type type, int seg_no,
  3015. void *va, phys_addr_t pa, size_t size)
  3016. {
  3017. return 0;
  3018. }
  3019. #endif /* CONFIG_QCOM_MINIDUMP */
  3020. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  3021. const struct firmware **fw_entry,
  3022. const char *filename)
  3023. {
  3024. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  3025. return request_firmware_direct(fw_entry, filename,
  3026. &plat_priv->plat_dev->dev);
  3027. else
  3028. return firmware_request_nowarn(fw_entry, filename,
  3029. &plat_priv->plat_dev->dev);
  3030. }
  3031. #if IS_ENABLED(CONFIG_INTERCONNECT)
  3032. /**
  3033. * cnss_register_bus_scale() - Setup interconnect voting data
  3034. * @plat_priv: Platform data structure
  3035. *
  3036. * For different interconnect path configured in device tree setup voting data
  3037. * for list of bandwidth requirements.
  3038. *
  3039. * Result: 0 for success. -EINVAL if not configured
  3040. */
  3041. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3042. {
  3043. int ret = -EINVAL;
  3044. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  3045. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3046. struct device *dev = &plat_priv->plat_dev->dev;
  3047. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  3048. ret = of_property_read_u32(dev->of_node,
  3049. "qcom,icc-path-count",
  3050. &plat_priv->icc.path_count);
  3051. if (ret) {
  3052. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  3053. return 0;
  3054. }
  3055. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  3056. "qcom,bus-bw-cfg-count",
  3057. &plat_priv->icc.bus_bw_cfg_count);
  3058. if (ret) {
  3059. cnss_pr_err("Failed to get Bus BW Config table size\n");
  3060. goto cleanup;
  3061. }
  3062. cfg_arr_size = plat_priv->icc.path_count *
  3063. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  3064. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  3065. if (!cfg_arr) {
  3066. cnss_pr_err("Failed to alloc cfg table mem\n");
  3067. ret = -ENOMEM;
  3068. goto cleanup;
  3069. }
  3070. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  3071. "qcom,bus-bw-cfg", cfg_arr,
  3072. cfg_arr_size);
  3073. if (ret) {
  3074. cnss_pr_err("Invalid Bus BW Config Table\n");
  3075. goto cleanup;
  3076. }
  3077. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  3078. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  3079. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  3080. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  3081. GFP_KERNEL);
  3082. if (!bus_bw_info) {
  3083. ret = -ENOMEM;
  3084. goto out;
  3085. }
  3086. ret = of_property_read_string_index(dev->of_node,
  3087. "interconnect-names", idx,
  3088. &bus_bw_info->icc_name);
  3089. if (ret)
  3090. goto out;
  3091. bus_bw_info->icc_path =
  3092. of_icc_get(&plat_priv->plat_dev->dev,
  3093. bus_bw_info->icc_name);
  3094. if (IS_ERR(bus_bw_info->icc_path)) {
  3095. ret = PTR_ERR(bus_bw_info->icc_path);
  3096. if (ret != -EPROBE_DEFER) {
  3097. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  3098. bus_bw_info->icc_name, ret);
  3099. goto out;
  3100. }
  3101. }
  3102. bus_bw_info->cfg_table =
  3103. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  3104. sizeof(*bus_bw_info->cfg_table),
  3105. GFP_KERNEL);
  3106. if (!bus_bw_info->cfg_table) {
  3107. ret = -ENOMEM;
  3108. goto out;
  3109. }
  3110. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  3111. bus_bw_info->icc_name);
  3112. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  3113. CNSS_ICC_VOTE_MAX);
  3114. i < plat_priv->icc.bus_bw_cfg_count;
  3115. i++, j += 2) {
  3116. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  3117. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  3118. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  3119. i, bus_bw_info->cfg_table[i].avg_bw,
  3120. bus_bw_info->cfg_table[i].peak_bw);
  3121. }
  3122. list_add_tail(&bus_bw_info->list,
  3123. &plat_priv->icc.list_head);
  3124. }
  3125. kfree(cfg_arr);
  3126. return 0;
  3127. out:
  3128. list_for_each_entry_safe(bus_bw_info, tmp,
  3129. &plat_priv->icc.list_head, list) {
  3130. list_del(&bus_bw_info->list);
  3131. }
  3132. cleanup:
  3133. kfree(cfg_arr);
  3134. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3135. return ret;
  3136. }
  3137. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  3138. {
  3139. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3140. list_for_each_entry_safe(bus_bw_info, tmp,
  3141. &plat_priv->icc.list_head, list) {
  3142. list_del(&bus_bw_info->list);
  3143. if (bus_bw_info->icc_path)
  3144. icc_put(bus_bw_info->icc_path);
  3145. }
  3146. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3147. }
  3148. #else
  3149. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3150. {
  3151. return 0;
  3152. }
  3153. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  3154. #endif /* CONFIG_INTERCONNECT */
  3155. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  3156. {
  3157. struct cnss_plat_data *plat_priv = cb_ctx;
  3158. if (!plat_priv) {
  3159. cnss_pr_err("%s: Invalid context\n", __func__);
  3160. return;
  3161. }
  3162. if (status) {
  3163. cnss_pr_info("CNSS Daemon connected\n");
  3164. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3165. complete(&plat_priv->daemon_connected);
  3166. } else {
  3167. cnss_pr_info("CNSS Daemon disconnected\n");
  3168. reinit_completion(&plat_priv->daemon_connected);
  3169. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3170. }
  3171. }
  3172. static ssize_t enable_hds_store(struct device *dev,
  3173. struct device_attribute *attr,
  3174. const char *buf, size_t count)
  3175. {
  3176. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3177. unsigned int enable_hds = 0;
  3178. if (!plat_priv)
  3179. return -ENODEV;
  3180. if (sscanf(buf, "%du", &enable_hds) != 1) {
  3181. cnss_pr_err("Invalid enable_hds sysfs command\n");
  3182. return -EINVAL;
  3183. }
  3184. if (enable_hds)
  3185. plat_priv->hds_enabled = true;
  3186. else
  3187. plat_priv->hds_enabled = false;
  3188. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  3189. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  3190. return count;
  3191. }
  3192. static ssize_t recovery_show(struct device *dev,
  3193. struct device_attribute *attr,
  3194. char *buf)
  3195. {
  3196. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3197. u32 buf_size = PAGE_SIZE;
  3198. u32 curr_len = 0;
  3199. u32 buf_written = 0;
  3200. if (!plat_priv)
  3201. return -ENODEV;
  3202. buf_written = scnprintf(buf, buf_size,
  3203. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  3204. "BIT0 -- wlan fw recovery\n"
  3205. "BIT1 -- wlan pcss recovery\n"
  3206. "---------------------------------\n");
  3207. curr_len += buf_written;
  3208. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3209. "WLAN recovery %s[%d]\n",
  3210. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  3211. plat_priv->recovery_enabled);
  3212. curr_len += buf_written;
  3213. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3214. "WLAN PCSS recovery %s[%d]\n",
  3215. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  3216. plat_priv->recovery_pcss_enabled);
  3217. curr_len += buf_written;
  3218. /*
  3219. * Now size of curr_len is not over page size for sure,
  3220. * later if new item or none-fixed size item added, need
  3221. * add check to make sure curr_len is not over page size.
  3222. */
  3223. return curr_len;
  3224. }
  3225. static ssize_t time_sync_period_show(struct device *dev,
  3226. struct device_attribute *attr,
  3227. char *buf)
  3228. {
  3229. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3230. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  3231. plat_priv->ctrl_params.time_sync_period);
  3232. }
  3233. static ssize_t time_sync_period_store(struct device *dev,
  3234. struct device_attribute *attr,
  3235. const char *buf, size_t count)
  3236. {
  3237. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3238. unsigned int time_sync_period = 0;
  3239. if (!plat_priv)
  3240. return -ENODEV;
  3241. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  3242. cnss_pr_err("Invalid time sync sysfs command\n");
  3243. return -EINVAL;
  3244. }
  3245. if (time_sync_period >= CNSS_MIN_TIME_SYNC_PERIOD)
  3246. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3247. return count;
  3248. }
  3249. static ssize_t recovery_store(struct device *dev,
  3250. struct device_attribute *attr,
  3251. const char *buf, size_t count)
  3252. {
  3253. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3254. unsigned int recovery = 0;
  3255. if (!plat_priv)
  3256. return -ENODEV;
  3257. if (sscanf(buf, "%du", &recovery) != 1) {
  3258. cnss_pr_err("Invalid recovery sysfs command\n");
  3259. return -EINVAL;
  3260. }
  3261. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  3262. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  3263. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  3264. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  3265. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  3266. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  3267. cnss_send_subsys_restart_level_msg(plat_priv);
  3268. return count;
  3269. }
  3270. static ssize_t shutdown_store(struct device *dev,
  3271. struct device_attribute *attr,
  3272. const char *buf, size_t count)
  3273. {
  3274. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3275. if (plat_priv) {
  3276. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3277. del_timer(&plat_priv->fw_boot_timer);
  3278. complete_all(&plat_priv->power_up_complete);
  3279. complete_all(&plat_priv->cal_complete);
  3280. }
  3281. cnss_pr_dbg("Received shutdown notification\n");
  3282. return count;
  3283. }
  3284. static ssize_t fs_ready_store(struct device *dev,
  3285. struct device_attribute *attr,
  3286. const char *buf, size_t count)
  3287. {
  3288. int fs_ready = 0;
  3289. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3290. if (sscanf(buf, "%du", &fs_ready) != 1)
  3291. return -EINVAL;
  3292. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  3293. fs_ready, count);
  3294. if (!plat_priv) {
  3295. cnss_pr_err("plat_priv is NULL\n");
  3296. return count;
  3297. }
  3298. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  3299. cnss_pr_dbg("QMI is bypassed\n");
  3300. return count;
  3301. }
  3302. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  3303. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  3304. cnss_driver_event_post(plat_priv,
  3305. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3306. 0, NULL);
  3307. }
  3308. return count;
  3309. }
  3310. static ssize_t qdss_trace_start_store(struct device *dev,
  3311. struct device_attribute *attr,
  3312. const char *buf, size_t count)
  3313. {
  3314. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3315. wlfw_qdss_trace_start(plat_priv);
  3316. cnss_pr_dbg("Received QDSS start command\n");
  3317. return count;
  3318. }
  3319. static ssize_t qdss_trace_stop_store(struct device *dev,
  3320. struct device_attribute *attr,
  3321. const char *buf, size_t count)
  3322. {
  3323. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3324. u32 option = 0;
  3325. if (sscanf(buf, "%du", &option) != 1)
  3326. return -EINVAL;
  3327. wlfw_qdss_trace_stop(plat_priv, option);
  3328. cnss_pr_dbg("Received QDSS stop command\n");
  3329. return count;
  3330. }
  3331. static ssize_t qdss_conf_download_store(struct device *dev,
  3332. struct device_attribute *attr,
  3333. const char *buf, size_t count)
  3334. {
  3335. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3336. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  3337. cnss_pr_dbg("Received QDSS download config command\n");
  3338. return count;
  3339. }
  3340. static ssize_t hw_trace_override_store(struct device *dev,
  3341. struct device_attribute *attr,
  3342. const char *buf, size_t count)
  3343. {
  3344. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3345. int tmp = 0;
  3346. if (sscanf(buf, "%du", &tmp) != 1)
  3347. return -EINVAL;
  3348. plat_priv->hw_trc_override = tmp;
  3349. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3350. return count;
  3351. }
  3352. static ssize_t charger_mode_store(struct device *dev,
  3353. struct device_attribute *attr,
  3354. const char *buf, size_t count)
  3355. {
  3356. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3357. int tmp = 0;
  3358. if (sscanf(buf, "%du", &tmp) != 1)
  3359. return -EINVAL;
  3360. plat_priv->charger_mode = tmp;
  3361. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3362. return count;
  3363. }
  3364. static DEVICE_ATTR_WO(fs_ready);
  3365. static DEVICE_ATTR_WO(shutdown);
  3366. static DEVICE_ATTR_RW(recovery);
  3367. static DEVICE_ATTR_WO(enable_hds);
  3368. static DEVICE_ATTR_WO(qdss_trace_start);
  3369. static DEVICE_ATTR_WO(qdss_trace_stop);
  3370. static DEVICE_ATTR_WO(qdss_conf_download);
  3371. static DEVICE_ATTR_WO(hw_trace_override);
  3372. static DEVICE_ATTR_WO(charger_mode);
  3373. static DEVICE_ATTR_RW(time_sync_period);
  3374. static struct attribute *cnss_attrs[] = {
  3375. &dev_attr_fs_ready.attr,
  3376. &dev_attr_shutdown.attr,
  3377. &dev_attr_recovery.attr,
  3378. &dev_attr_enable_hds.attr,
  3379. &dev_attr_qdss_trace_start.attr,
  3380. &dev_attr_qdss_trace_stop.attr,
  3381. &dev_attr_qdss_conf_download.attr,
  3382. &dev_attr_hw_trace_override.attr,
  3383. &dev_attr_charger_mode.attr,
  3384. &dev_attr_time_sync_period.attr,
  3385. NULL,
  3386. };
  3387. static struct attribute_group cnss_attr_group = {
  3388. .attrs = cnss_attrs,
  3389. };
  3390. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3391. {
  3392. struct device *dev = &plat_priv->plat_dev->dev;
  3393. int ret;
  3394. char cnss_name[CNSS_FS_NAME_SIZE];
  3395. char shutdown_name[32];
  3396. if (cnss_is_dual_wlan_enabled()) {
  3397. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3398. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3399. snprintf(shutdown_name, sizeof(shutdown_name),
  3400. "shutdown_wlan_%d", plat_priv->plat_idx);
  3401. } else {
  3402. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3403. snprintf(shutdown_name, sizeof(shutdown_name),
  3404. "shutdown_wlan");
  3405. }
  3406. ret = sysfs_create_link(kernel_kobj, &dev->kobj, cnss_name);
  3407. if (ret) {
  3408. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3409. ret);
  3410. goto out;
  3411. }
  3412. /* This is only for backward compatibility. */
  3413. ret = sysfs_create_link(kernel_kobj, &dev->kobj, shutdown_name);
  3414. if (ret) {
  3415. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3416. ret);
  3417. goto rm_cnss_link;
  3418. }
  3419. return 0;
  3420. rm_cnss_link:
  3421. sysfs_remove_link(kernel_kobj, cnss_name);
  3422. out:
  3423. return ret;
  3424. }
  3425. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3426. {
  3427. char cnss_name[CNSS_FS_NAME_SIZE];
  3428. char shutdown_name[32];
  3429. if (cnss_is_dual_wlan_enabled()) {
  3430. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3431. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3432. snprintf(shutdown_name, sizeof(shutdown_name),
  3433. "shutdown_wlan_%d", plat_priv->plat_idx);
  3434. } else {
  3435. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3436. snprintf(shutdown_name, sizeof(shutdown_name),
  3437. "shutdown_wlan");
  3438. }
  3439. sysfs_remove_link(kernel_kobj, shutdown_name);
  3440. sysfs_remove_link(kernel_kobj, cnss_name);
  3441. }
  3442. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3443. {
  3444. int ret = 0;
  3445. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3446. &cnss_attr_group);
  3447. if (ret) {
  3448. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3449. ret);
  3450. goto out;
  3451. }
  3452. cnss_create_sysfs_link(plat_priv);
  3453. return 0;
  3454. out:
  3455. return ret;
  3456. }
  3457. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3458. {
  3459. cnss_remove_sysfs_link(plat_priv);
  3460. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3461. }
  3462. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3463. {
  3464. spin_lock_init(&plat_priv->event_lock);
  3465. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3466. WQ_UNBOUND, 1);
  3467. if (!plat_priv->event_wq) {
  3468. cnss_pr_err("Failed to create event workqueue!\n");
  3469. return -EFAULT;
  3470. }
  3471. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3472. INIT_LIST_HEAD(&plat_priv->event_list);
  3473. return 0;
  3474. }
  3475. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3476. {
  3477. destroy_workqueue(plat_priv->event_wq);
  3478. }
  3479. static int cnss_reboot_notifier(struct notifier_block *nb,
  3480. unsigned long action,
  3481. void *data)
  3482. {
  3483. struct cnss_plat_data *plat_priv =
  3484. container_of(nb, struct cnss_plat_data, reboot_nb);
  3485. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3486. del_timer(&plat_priv->fw_boot_timer);
  3487. complete_all(&plat_priv->power_up_complete);
  3488. complete_all(&plat_priv->cal_complete);
  3489. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3490. return NOTIFY_DONE;
  3491. }
  3492. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3493. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3494. {
  3495. struct Object client_env;
  3496. struct Object app_object;
  3497. u32 wifi_uid = HW_WIFI_UID;
  3498. union ObjectArg obj_arg[2] = {{{0, 0}}};
  3499. int ret;
  3500. u8 state = 0;
  3501. /* Once this flag is set, secure peripheral feature
  3502. * will not be supported till next reboot
  3503. */
  3504. if (plat_priv->sec_peri_feature_disable)
  3505. return 0;
  3506. /* get rootObj */
  3507. ret = get_client_env_object(&client_env);
  3508. if (ret) {
  3509. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  3510. goto end;
  3511. }
  3512. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  3513. if (ret) {
  3514. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  3515. if (ret == FEATURE_NOT_SUPPORTED) {
  3516. ret = 0; /* Do not Assert */
  3517. plat_priv->sec_peri_feature_disable = true;
  3518. cnss_pr_dbg("Secure HW feature not supported\n");
  3519. }
  3520. goto exit_release_clientenv;
  3521. }
  3522. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  3523. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  3524. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  3525. ObjectCounts_pack(1, 1, 0, 0));
  3526. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  3527. if (ret) {
  3528. if (ret == PERIPHERAL_NOT_FOUND) {
  3529. ret = 0; /* Do not Assert */
  3530. plat_priv->sec_peri_feature_disable = true;
  3531. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  3532. }
  3533. goto exit_release_app_obj;
  3534. }
  3535. if (state == 1)
  3536. set_bit(CNSS_WLAN_HW_DISABLED,
  3537. &plat_priv->driver_state);
  3538. else
  3539. clear_bit(CNSS_WLAN_HW_DISABLED,
  3540. &plat_priv->driver_state);
  3541. exit_release_app_obj:
  3542. Object_release(app_object);
  3543. exit_release_clientenv:
  3544. Object_release(client_env);
  3545. end:
  3546. if (ret) {
  3547. cnss_pr_err("Unable to get HW disable status\n");
  3548. CNSS_ASSERT(0);
  3549. }
  3550. return ret;
  3551. }
  3552. #else
  3553. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3554. {
  3555. return 0;
  3556. }
  3557. #endif
  3558. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  3559. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  3560. {
  3561. }
  3562. #else
  3563. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  3564. {
  3565. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  3566. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  3567. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  3568. }
  3569. #endif
  3570. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  3571. {
  3572. int ret;
  3573. ret = cnss_init_sol_gpio(plat_priv);
  3574. if (ret)
  3575. return ret;
  3576. timer_setup(&plat_priv->fw_boot_timer,
  3577. cnss_bus_fw_boot_timeout_hdlr, 0);
  3578. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  3579. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  3580. if (ret)
  3581. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  3582. ret);
  3583. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  3584. if (ret)
  3585. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3586. ret);
  3587. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  3588. init_completion(&plat_priv->power_up_complete);
  3589. init_completion(&plat_priv->cal_complete);
  3590. init_completion(&plat_priv->rddm_complete);
  3591. init_completion(&plat_priv->recovery_complete);
  3592. init_completion(&plat_priv->daemon_connected);
  3593. mutex_init(&plat_priv->dev_lock);
  3594. mutex_init(&plat_priv->driver_ops_lock);
  3595. plat_priv->recovery_ws =
  3596. wakeup_source_register(&plat_priv->plat_dev->dev,
  3597. "CNSS_FW_RECOVERY");
  3598. if (!plat_priv->recovery_ws)
  3599. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3600. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3601. cnss_daemon_connection_update_cb,
  3602. plat_priv);
  3603. if (ret)
  3604. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3605. ret);
  3606. cnss_sram_dump_init(plat_priv);
  3607. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3608. "qcom,rc-ep-short-channel"))
  3609. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  3610. return 0;
  3611. }
  3612. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  3613. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  3614. {
  3615. }
  3616. #else
  3617. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  3618. {
  3619. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  3620. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  3621. kfree(plat_priv->sram_dump);
  3622. }
  3623. #endif
  3624. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3625. {
  3626. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3627. plat_priv);
  3628. complete_all(&plat_priv->recovery_complete);
  3629. complete_all(&plat_priv->rddm_complete);
  3630. complete_all(&plat_priv->cal_complete);
  3631. complete_all(&plat_priv->power_up_complete);
  3632. complete_all(&plat_priv->daemon_connected);
  3633. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3634. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3635. del_timer(&plat_priv->fw_boot_timer);
  3636. wakeup_source_unregister(plat_priv->recovery_ws);
  3637. cnss_deinit_sol_gpio(plat_priv);
  3638. cnss_sram_dump_deinit(plat_priv);
  3639. kfree(plat_priv->on_chip_pmic_board_ids);
  3640. }
  3641. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3642. {
  3643. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3644. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3645. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3646. "qcom,wlan-cbc-enabled");
  3647. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3648. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3649. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3650. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3651. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3652. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3653. * enabled by default
  3654. */
  3655. plat_priv->adsp_pc_enabled = true;
  3656. }
  3657. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3658. {
  3659. struct device *dev = &plat_priv->plat_dev->dev;
  3660. plat_priv->use_pm_domain =
  3661. of_property_read_bool(dev->of_node, "use-pm-domain");
  3662. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3663. }
  3664. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3665. {
  3666. struct device *dev = &plat_priv->plat_dev->dev;
  3667. plat_priv->set_wlaon_pwr_ctrl =
  3668. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3669. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3670. plat_priv->set_wlaon_pwr_ctrl);
  3671. }
  3672. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3673. {
  3674. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3675. "qcom,converged-dt") ||
  3676. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3677. "qcom,same-dt-multi-dev") ||
  3678. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3679. "qcom,multi-wlan-exchg"));
  3680. }
  3681. static const struct platform_device_id cnss_platform_id_table[] = {
  3682. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3683. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3684. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3685. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3686. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3687. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  3688. { .name = "peach", .driver_data = PEACH_DEVICE_ID, },
  3689. { .name = "qcaconv", .driver_data = 0, },
  3690. { },
  3691. };
  3692. static const struct of_device_id cnss_of_match_table[] = {
  3693. {
  3694. .compatible = "qcom,cnss",
  3695. .data = (void *)&cnss_platform_id_table[0]},
  3696. {
  3697. .compatible = "qcom,cnss-qca6290",
  3698. .data = (void *)&cnss_platform_id_table[1]},
  3699. {
  3700. .compatible = "qcom,cnss-qca6390",
  3701. .data = (void *)&cnss_platform_id_table[2]},
  3702. {
  3703. .compatible = "qcom,cnss-qca6490",
  3704. .data = (void *)&cnss_platform_id_table[3]},
  3705. {
  3706. .compatible = "qcom,cnss-kiwi",
  3707. .data = (void *)&cnss_platform_id_table[4]},
  3708. {
  3709. .compatible = "qcom,cnss-mango",
  3710. .data = (void *)&cnss_platform_id_table[5]},
  3711. {
  3712. .compatible = "qcom,cnss-peach",
  3713. .data = (void *)&cnss_platform_id_table[6]},
  3714. {
  3715. .compatible = "qcom,cnss-qca-converged",
  3716. .data = (void *)&cnss_platform_id_table[7]},
  3717. { },
  3718. };
  3719. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3720. static inline bool
  3721. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3722. {
  3723. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3724. "use-nv-mac");
  3725. }
  3726. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3727. {
  3728. struct device_node *child;
  3729. u32 id, i;
  3730. int id_n, device_identifier_gpio, ret;
  3731. u8 gpio_value;
  3732. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  3733. return 0;
  3734. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  3735. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  3736. if (ret) {
  3737. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  3738. return ret;
  3739. }
  3740. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3741. gpio_value = gpio_get_value(device_identifier_gpio);
  3742. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  3743. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3744. child) {
  3745. if (strcmp(child->name, "chip_cfg"))
  3746. continue;
  3747. id_n = of_property_count_u32_elems(child, "supported-ids");
  3748. if (id_n <= 0) {
  3749. cnss_pr_err("Device id is NOT set\n");
  3750. return -EINVAL;
  3751. }
  3752. for (i = 0; i < id_n; i++) {
  3753. ret = of_property_read_u32_index(child,
  3754. "supported-ids",
  3755. i, &id);
  3756. if (ret) {
  3757. cnss_pr_err("Failed to read supported ids\n");
  3758. return -EINVAL;
  3759. }
  3760. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3761. plat_priv->plat_dev->dev.of_node = child;
  3762. plat_priv->device_id = QCA6490_DEVICE_ID;
  3763. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3764. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3765. child->name, i, id);
  3766. return 0;
  3767. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3768. plat_priv->plat_dev->dev.of_node = child;
  3769. plat_priv->device_id = KIWI_DEVICE_ID;
  3770. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3771. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3772. child->name, i, id);
  3773. return 0;
  3774. }
  3775. }
  3776. }
  3777. return -EINVAL;
  3778. }
  3779. static inline u32
  3780. cnss_dt_type(struct cnss_plat_data *plat_priv)
  3781. {
  3782. bool is_converged_dt = of_property_read_bool(
  3783. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  3784. bool is_multi_wlan_xchg;
  3785. if (is_converged_dt)
  3786. return CNSS_DTT_CONVERGED;
  3787. is_multi_wlan_xchg = of_property_read_bool(
  3788. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  3789. if (is_multi_wlan_xchg)
  3790. return CNSS_DTT_MULTIEXCHG;
  3791. return CNSS_DTT_LEGACY;
  3792. }
  3793. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  3794. {
  3795. int ret = 0;
  3796. int retry = 0;
  3797. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3798. return 0;
  3799. retry:
  3800. ret = cnss_power_on_device(plat_priv, true);
  3801. if (ret)
  3802. goto end;
  3803. ret = cnss_bus_init(plat_priv);
  3804. if (ret) {
  3805. if ((ret != -EPROBE_DEFER) &&
  3806. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3807. cnss_power_off_device(plat_priv);
  3808. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3809. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3810. goto retry;
  3811. }
  3812. goto power_off;
  3813. }
  3814. return 0;
  3815. power_off:
  3816. cnss_power_off_device(plat_priv);
  3817. end:
  3818. return ret;
  3819. }
  3820. int cnss_wlan_hw_enable(void)
  3821. {
  3822. struct cnss_plat_data *plat_priv;
  3823. int ret = 0;
  3824. if (cnss_is_dual_wlan_enabled())
  3825. plat_priv = cnss_get_first_plat_priv(NULL);
  3826. else
  3827. plat_priv = cnss_get_plat_priv(NULL);
  3828. if (!plat_priv)
  3829. return -ENODEV;
  3830. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  3831. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  3832. goto register_driver;
  3833. ret = cnss_wlan_device_init(plat_priv);
  3834. if (ret) {
  3835. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  3836. CNSS_ASSERT(0);
  3837. return ret;
  3838. }
  3839. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  3840. cnss_driver_event_post(plat_priv,
  3841. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3842. 0, NULL);
  3843. register_driver:
  3844. if (plat_priv->driver_ops)
  3845. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  3846. return ret;
  3847. }
  3848. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  3849. int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg)
  3850. {
  3851. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3852. int ret = 0;
  3853. if (!plat_priv)
  3854. return -ENODEV;
  3855. /* If IMS server is connected, return success without QMI send */
  3856. if (test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  3857. cnss_pr_dbg("Ignore host request as IMS server is connected");
  3858. return ret;
  3859. }
  3860. ret = cnss_wlfw_send_host_wfc_call_status(plat_priv, cfg);
  3861. return ret;
  3862. }
  3863. EXPORT_SYMBOL(cnss_set_wfc_mode);
  3864. static int cnss_tcdev_get_max_state(struct thermal_cooling_device *tcdev,
  3865. unsigned long *thermal_state)
  3866. {
  3867. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  3868. if (!tcdev || !tcdev->devdata) {
  3869. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  3870. return -EINVAL;
  3871. }
  3872. cnss_tcdev = tcdev->devdata;
  3873. *thermal_state = cnss_tcdev->max_thermal_state;
  3874. return 0;
  3875. }
  3876. static int cnss_tcdev_get_cur_state(struct thermal_cooling_device *tcdev,
  3877. unsigned long *thermal_state)
  3878. {
  3879. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  3880. if (!tcdev || !tcdev->devdata) {
  3881. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  3882. return -EINVAL;
  3883. }
  3884. cnss_tcdev = tcdev->devdata;
  3885. *thermal_state = cnss_tcdev->curr_thermal_state;
  3886. return 0;
  3887. }
  3888. static int cnss_tcdev_set_cur_state(struct thermal_cooling_device *tcdev,
  3889. unsigned long thermal_state)
  3890. {
  3891. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  3892. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3893. int ret = 0;
  3894. if (!tcdev || !tcdev->devdata) {
  3895. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  3896. return -EINVAL;
  3897. }
  3898. cnss_tcdev = tcdev->devdata;
  3899. if (thermal_state > cnss_tcdev->max_thermal_state)
  3900. return -EINVAL;
  3901. cnss_pr_vdbg("Cooling device set current state: %ld,for cdev id %d",
  3902. thermal_state, cnss_tcdev->tcdev_id);
  3903. mutex_lock(&plat_priv->tcdev_lock);
  3904. ret = cnss_bus_set_therm_cdev_state(plat_priv,
  3905. thermal_state,
  3906. cnss_tcdev->tcdev_id);
  3907. if (!ret)
  3908. cnss_tcdev->curr_thermal_state = thermal_state;
  3909. mutex_unlock(&plat_priv->tcdev_lock);
  3910. if (ret) {
  3911. cnss_pr_err("Setting Current Thermal State Failed: %d,for cdev id %d",
  3912. ret, cnss_tcdev->tcdev_id);
  3913. return ret;
  3914. }
  3915. return 0;
  3916. }
  3917. static struct thermal_cooling_device_ops cnss_cooling_ops = {
  3918. .get_max_state = cnss_tcdev_get_max_state,
  3919. .get_cur_state = cnss_tcdev_get_cur_state,
  3920. .set_cur_state = cnss_tcdev_set_cur_state,
  3921. };
  3922. int cnss_thermal_cdev_register(struct device *dev, unsigned long max_state,
  3923. int tcdev_id)
  3924. {
  3925. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  3926. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  3927. char cdev_node_name[THERMAL_NAME_LENGTH] = "";
  3928. struct device_node *dev_node;
  3929. int ret = 0;
  3930. if (!priv) {
  3931. cnss_pr_err("Platform driver is not initialized!\n");
  3932. return -ENODEV;
  3933. }
  3934. cnss_tcdev = kzalloc(sizeof(*cnss_tcdev), GFP_KERNEL);
  3935. if (!cnss_tcdev) {
  3936. cnss_pr_err("Failed to allocate cnss_tcdev object!\n");
  3937. return -ENOMEM;
  3938. }
  3939. cnss_tcdev->tcdev_id = tcdev_id;
  3940. cnss_tcdev->max_thermal_state = max_state;
  3941. snprintf(cdev_node_name, THERMAL_NAME_LENGTH,
  3942. "qcom,cnss_cdev%d", tcdev_id);
  3943. dev_node = of_find_node_by_name(NULL, cdev_node_name);
  3944. if (!dev_node) {
  3945. cnss_pr_err("Failed to get cooling device node\n");
  3946. kfree(cnss_tcdev);
  3947. return -EINVAL;
  3948. }
  3949. cnss_pr_dbg("tcdev node->name=%s\n", dev_node->name);
  3950. if (of_find_property(dev_node, "#cooling-cells", NULL)) {
  3951. cnss_tcdev->tcdev = thermal_of_cooling_device_register(dev_node,
  3952. cdev_node_name,
  3953. cnss_tcdev,
  3954. &cnss_cooling_ops);
  3955. if (IS_ERR_OR_NULL(cnss_tcdev->tcdev)) {
  3956. ret = PTR_ERR(cnss_tcdev->tcdev);
  3957. cnss_pr_err("Cooling device register failed: %d, for cdev id %d\n",
  3958. ret, cnss_tcdev->tcdev_id);
  3959. kfree(cnss_tcdev);
  3960. } else {
  3961. cnss_pr_dbg("Cooling device registered for cdev id %d",
  3962. cnss_tcdev->tcdev_id);
  3963. mutex_lock(&priv->tcdev_lock);
  3964. list_add(&cnss_tcdev->tcdev_list,
  3965. &priv->cnss_tcdev_list);
  3966. mutex_unlock(&priv->tcdev_lock);
  3967. }
  3968. } else {
  3969. cnss_pr_dbg("Cooling device registration not supported");
  3970. kfree(cnss_tcdev);
  3971. ret = -EOPNOTSUPP;
  3972. }
  3973. return ret;
  3974. }
  3975. EXPORT_SYMBOL(cnss_thermal_cdev_register);
  3976. void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id)
  3977. {
  3978. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  3979. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  3980. if (!priv) {
  3981. cnss_pr_err("Platform driver is not initialized!\n");
  3982. return;
  3983. }
  3984. mutex_lock(&priv->tcdev_lock);
  3985. while (!list_empty(&priv->cnss_tcdev_list)) {
  3986. cnss_tcdev = list_first_entry(&priv->cnss_tcdev_list,
  3987. struct cnss_thermal_cdev,
  3988. tcdev_list);
  3989. thermal_cooling_device_unregister(cnss_tcdev->tcdev);
  3990. list_del(&cnss_tcdev->tcdev_list);
  3991. kfree(cnss_tcdev);
  3992. }
  3993. mutex_unlock(&priv->tcdev_lock);
  3994. }
  3995. EXPORT_SYMBOL(cnss_thermal_cdev_unregister);
  3996. int cnss_get_curr_therm_cdev_state(struct device *dev,
  3997. unsigned long *thermal_state,
  3998. int tcdev_id)
  3999. {
  4000. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4001. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4002. if (!priv) {
  4003. cnss_pr_err("Platform driver is not initialized!\n");
  4004. return -ENODEV;
  4005. }
  4006. mutex_lock(&priv->tcdev_lock);
  4007. list_for_each_entry(cnss_tcdev, &priv->cnss_tcdev_list, tcdev_list) {
  4008. if (cnss_tcdev->tcdev_id != tcdev_id)
  4009. continue;
  4010. *thermal_state = cnss_tcdev->curr_thermal_state;
  4011. mutex_unlock(&priv->tcdev_lock);
  4012. cnss_pr_dbg("Cooling device current state: %ld, for cdev id %d",
  4013. cnss_tcdev->curr_thermal_state, tcdev_id);
  4014. return 0;
  4015. }
  4016. mutex_unlock(&priv->tcdev_lock);
  4017. cnss_pr_dbg("Cooling device ID not found: %d", tcdev_id);
  4018. return -EINVAL;
  4019. }
  4020. EXPORT_SYMBOL(cnss_get_curr_therm_cdev_state);
  4021. static int cnss_probe(struct platform_device *plat_dev)
  4022. {
  4023. int ret = 0;
  4024. struct cnss_plat_data *plat_priv;
  4025. const struct of_device_id *of_id;
  4026. const struct platform_device_id *device_id;
  4027. if (cnss_get_plat_priv(plat_dev)) {
  4028. cnss_pr_err("Driver is already initialized!\n");
  4029. ret = -EEXIST;
  4030. goto out;
  4031. }
  4032. ret = cnss_plat_env_available();
  4033. if (ret)
  4034. goto out;
  4035. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  4036. if (!of_id || !of_id->data) {
  4037. cnss_pr_err("Failed to find of match device!\n");
  4038. ret = -ENODEV;
  4039. goto out;
  4040. }
  4041. device_id = of_id->data;
  4042. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  4043. GFP_KERNEL);
  4044. if (!plat_priv) {
  4045. ret = -ENOMEM;
  4046. goto out;
  4047. }
  4048. plat_priv->plat_dev = plat_dev;
  4049. plat_priv->dev_node = NULL;
  4050. plat_priv->device_id = device_id->driver_data;
  4051. plat_priv->dt_type = cnss_dt_type(plat_priv);
  4052. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  4053. plat_priv->dt_type);
  4054. plat_priv->use_fw_path_with_prefix =
  4055. cnss_use_fw_path_with_prefix(plat_priv);
  4056. ret = cnss_get_dev_cfg_node(plat_priv);
  4057. if (ret) {
  4058. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  4059. goto reset_plat_dev;
  4060. }
  4061. cnss_initialize_prealloc_pool(plat_priv->device_id);
  4062. ret = cnss_get_pld_bus_ops_name(plat_priv);
  4063. if (ret)
  4064. cnss_pr_err("Failed to find bus ops name, err = %d\n",
  4065. ret);
  4066. ret = cnss_get_rc_num(plat_priv);
  4067. if (ret)
  4068. cnss_pr_err("Failed to find PCIe RC number, err = %d\n", ret);
  4069. cnss_pr_dbg("rc_num=%d\n", plat_priv->rc_num);
  4070. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  4071. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  4072. plat_priv->driver_mode = CNSS_DRIVER_MODE_MAX;
  4073. cnss_set_plat_priv(plat_dev, plat_priv);
  4074. cnss_set_device_name(plat_priv);
  4075. platform_set_drvdata(plat_dev, plat_priv);
  4076. INIT_LIST_HEAD(&plat_priv->vreg_list);
  4077. INIT_LIST_HEAD(&plat_priv->clk_list);
  4078. cnss_get_pm_domain_info(plat_priv);
  4079. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  4080. cnss_power_misc_params_init(plat_priv);
  4081. cnss_get_tcs_info(plat_priv);
  4082. cnss_get_cpr_info(plat_priv);
  4083. cnss_aop_mbox_init(plat_priv);
  4084. cnss_init_control_params(plat_priv);
  4085. ret = cnss_get_resources(plat_priv);
  4086. if (ret)
  4087. goto reset_ctx;
  4088. ret = cnss_register_esoc(plat_priv);
  4089. if (ret)
  4090. goto free_res;
  4091. ret = cnss_register_bus_scale(plat_priv);
  4092. if (ret)
  4093. goto unreg_esoc;
  4094. ret = cnss_create_sysfs(plat_priv);
  4095. if (ret)
  4096. goto unreg_bus_scale;
  4097. ret = cnss_event_work_init(plat_priv);
  4098. if (ret)
  4099. goto remove_sysfs;
  4100. ret = cnss_dms_init(plat_priv);
  4101. if (ret)
  4102. goto deinit_event_work;
  4103. ret = cnss_debugfs_create(plat_priv);
  4104. if (ret)
  4105. goto deinit_dms;
  4106. ret = cnss_misc_init(plat_priv);
  4107. if (ret)
  4108. goto destroy_debugfs;
  4109. ret = cnss_wlan_hw_disable_check(plat_priv);
  4110. if (ret)
  4111. goto deinit_misc;
  4112. /* Make sure all platform related init are done before
  4113. * device power on and bus init.
  4114. */
  4115. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  4116. ret = cnss_wlan_device_init(plat_priv);
  4117. if (ret)
  4118. goto deinit_misc;
  4119. } else {
  4120. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  4121. }
  4122. cnss_register_coex_service(plat_priv);
  4123. cnss_register_ims_service(plat_priv);
  4124. mutex_init(&plat_priv->tcdev_lock);
  4125. INIT_LIST_HEAD(&plat_priv->cnss_tcdev_list);
  4126. cnss_pr_info("Platform driver probed successfully.\n");
  4127. return 0;
  4128. deinit_misc:
  4129. cnss_misc_deinit(plat_priv);
  4130. destroy_debugfs:
  4131. cnss_debugfs_destroy(plat_priv);
  4132. deinit_dms:
  4133. cnss_dms_deinit(plat_priv);
  4134. deinit_event_work:
  4135. cnss_event_work_deinit(plat_priv);
  4136. remove_sysfs:
  4137. cnss_remove_sysfs(plat_priv);
  4138. unreg_bus_scale:
  4139. cnss_unregister_bus_scale(plat_priv);
  4140. unreg_esoc:
  4141. cnss_unregister_esoc(plat_priv);
  4142. free_res:
  4143. cnss_put_resources(plat_priv);
  4144. reset_ctx:
  4145. platform_set_drvdata(plat_dev, NULL);
  4146. cnss_deinitialize_prealloc_pool();
  4147. reset_plat_dev:
  4148. cnss_clear_plat_priv(plat_priv);
  4149. out:
  4150. return ret;
  4151. }
  4152. static int cnss_remove(struct platform_device *plat_dev)
  4153. {
  4154. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  4155. plat_priv->audio_iommu_domain = NULL;
  4156. cnss_genl_exit();
  4157. cnss_unregister_ims_service(plat_priv);
  4158. cnss_unregister_coex_service(plat_priv);
  4159. cnss_bus_deinit(plat_priv);
  4160. cnss_misc_deinit(plat_priv);
  4161. cnss_debugfs_destroy(plat_priv);
  4162. cnss_dms_deinit(plat_priv);
  4163. cnss_qmi_deinit(plat_priv);
  4164. cnss_event_work_deinit(plat_priv);
  4165. cnss_cancel_dms_work();
  4166. cnss_remove_sysfs(plat_priv);
  4167. cnss_unregister_bus_scale(plat_priv);
  4168. cnss_unregister_esoc(plat_priv);
  4169. cnss_put_resources(plat_priv);
  4170. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  4171. mbox_free_channel(plat_priv->mbox_chan);
  4172. cnss_deinitialize_prealloc_pool();
  4173. platform_set_drvdata(plat_dev, NULL);
  4174. cnss_clear_plat_priv(plat_priv);
  4175. return 0;
  4176. }
  4177. static struct platform_driver cnss_platform_driver = {
  4178. .probe = cnss_probe,
  4179. .remove = cnss_remove,
  4180. .driver = {
  4181. .name = "cnss2",
  4182. .of_match_table = cnss_of_match_table,
  4183. #ifdef CONFIG_CNSS_ASYNC
  4184. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  4185. #endif
  4186. },
  4187. };
  4188. static bool cnss_check_compatible_node(void)
  4189. {
  4190. struct device_node *dn = NULL;
  4191. for_each_matching_node(dn, cnss_of_match_table) {
  4192. if (of_device_is_available(dn)) {
  4193. cnss_allow_driver_loading = true;
  4194. return true;
  4195. }
  4196. }
  4197. return false;
  4198. }
  4199. /**
  4200. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  4201. *
  4202. * Valid device tree node means a node with "compatible" property from the
  4203. * device match table and "status" property is not disabled.
  4204. *
  4205. * Return: true if valid device tree node found, false if not found
  4206. */
  4207. static bool cnss_is_valid_dt_node_found(void)
  4208. {
  4209. struct device_node *dn = NULL;
  4210. for_each_matching_node(dn, cnss_of_match_table) {
  4211. if (of_device_is_available(dn))
  4212. break;
  4213. }
  4214. if (dn)
  4215. return true;
  4216. return false;
  4217. }
  4218. static int __init cnss_initialize(void)
  4219. {
  4220. int ret = 0;
  4221. if (!cnss_is_valid_dt_node_found())
  4222. return -ENODEV;
  4223. if (!cnss_check_compatible_node())
  4224. return ret;
  4225. cnss_debug_init();
  4226. ret = platform_driver_register(&cnss_platform_driver);
  4227. if (ret)
  4228. cnss_debug_deinit();
  4229. ret = cnss_genl_init();
  4230. if (ret < 0)
  4231. cnss_pr_err("CNSS genl init failed %d\n", ret);
  4232. return ret;
  4233. }
  4234. static void __exit cnss_exit(void)
  4235. {
  4236. cnss_genl_exit();
  4237. platform_driver_unregister(&cnss_platform_driver);
  4238. cnss_debug_deinit();
  4239. }
  4240. module_init(cnss_initialize);
  4241. module_exit(cnss_exit);
  4242. MODULE_LICENSE("GPL v2");
  4243. MODULE_DESCRIPTION("CNSS2 Platform Driver");