77c4aea5e9
Add support for BT Soundwire clock. Change-Id: I27879c2f04144b81fcaf057db1810fb9b80267b4 Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
30 خطوط
1.4 KiB
C
30 خطوط
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
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/* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.*/
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#ifndef __AUDIO_EXT_CLK_H
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#define __AUDIO_EXT_CLK_H
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/* Audio External Clocks */
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#define AUDIO_PMI_CLK 0
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#define AUDIO_PMIC_LNBB_CLK 1
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#define AUDIO_LPASS_MCLK 2 /* VA CORE CLK */
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#define AUDIO_LPASS_MCLK_2 3 /* WSA1 CORE CLK */
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#define AUDIO_LPASS_MCLK_3 4 /* WSA1 NPL CLK */
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#define AUDIO_LPASS_MCLK_4 5 /* RX CORE CLK */
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#define AUDIO_LPASS_MCLK_5 6 /* RX NPL CLK */
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#define AUDIO_LPASS_MCLK_6 7 /* TX CORE CLK */
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#define AUDIO_LPASS_MCLK_7 8 /* TX NPL CLK */
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#define AUDIO_LPASS_CORE_HW_VOTE 9
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#define AUDIO_LPASS_MCLK_8 10 /* VA NPL CLK */
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#define AUDIO_LPASS_AUDIO_HW_VOTE 11
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#define AUDIO_LPASS_MCLK_9 12 /* WSA2 CORE CLK */
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#define AUDIO_LPASS_MCLK_10 13 /* RX_TX CORE CLK */
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#define AUDIO_LPASS_MCLK_11 14 /* WSA_TX CORE CLK */
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#define AUDIO_LPASS_MCLK_12 15 /* WSA2_TX CORE CLK */
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#define AUDIO_LPASS_MCLK_13 16 /* RX_MCLK2 2X CLK */
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#define AUDIO_LPASS_MCLK_14 17 /* HW SEQUNCER MCLK */
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#define AUDIO_LPASS_MCLK_15 18 /* BT_SWR CLK */
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#define AUDIO_LPASS_MCLK_16 19 /* BT_SWR 2X CLK */
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#endif
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