wcd9378.c 132 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define SWR_BASECLK_19P2MHZ (0x01)
  31. #define SWR_BASECLK_24P576MHZ (0x03)
  32. #define SWR_BASECLK_22P5792MHZ (0x04)
  33. #define SWR_CLKSCALE_DIV2 (0x02)
  34. #define ADC_MODE_VAL_HIFI 0x01
  35. #define ADC_MODE_VAL_NORMAL 0x03
  36. #define ADC_MODE_VAL_LP 0x05
  37. #define PWR_LEVEL_LOHIFI_VAL 0x00
  38. #define PWR_LEVEL_LP_VAL 0x01
  39. #define PWR_LEVEL_HIFI_VAL 0x02
  40. #define PWR_LEVEL_ULP_VAL 0x03
  41. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  42. #define MICB_USAGE_VAL_DISABLE 0x00
  43. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  44. #define MICB_USAGE_VAL_1P2V 0x02
  45. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  46. #define MICB_USAGE_VAL_2P5V 0x04
  47. #define MICB_USAGE_VAL_2P75V 0x05
  48. #define MICB_USAGE_VAL_2P2V 0xF0
  49. #define MICB_USAGE_VAL_2P7V 0xF1
  50. #define MICB_USAGE_VAL_2P8V 0xF2
  51. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  52. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  53. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  54. #define MICB_NUM_MAX 3
  55. #define NUM_ATTEMPTS 20
  56. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  57. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  58. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  59. SNDRV_PCM_RATE_384000)
  60. /* Fractional Rates */
  61. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  62. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  63. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  64. SNDRV_PCM_FMTBIT_S24_LE |\
  65. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  66. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  67. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  68. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  69. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  70. .tlv.p = (tlv_array), \
  71. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  72. .put = wcd9378_ear_pa_put_gain, \
  73. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  74. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  75. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  76. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  77. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  78. .tlv.p = (tlv_array), \
  79. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  80. .put = wcd9378_aux_pa_put_gain, \
  81. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  82. enum {
  83. CODEC_TX = 0,
  84. CODEC_RX,
  85. };
  86. enum {
  87. RX2_HP_MODE,
  88. RX2_NORMAL_MODE,
  89. };
  90. enum {
  91. CLASS_AB_EN = 0,
  92. TX1_FOR_JACK,
  93. TX2_AMIC4_EN,
  94. TX2_AMIC1_EN,
  95. TX1_AMIC3_EN,
  96. TX1_AMIC2_EN,
  97. TX0_AMIC2_EN,
  98. TX0_AMIC1_EN,
  99. RX2_EAR_EN,
  100. RX2_AUX_EN,
  101. RX1_AUX_EN,
  102. RX0_EAR_EN,
  103. RX0_RX1_HPH_EN,
  104. };
  105. enum {
  106. WCD_ADC1 = 0,
  107. WCD_ADC2,
  108. WCD_ADC3,
  109. WCD_ADC4,
  110. ALLOW_BUCK_DISABLE,
  111. HPH_COMP_DELAY,
  112. HPH_PA_DELAY,
  113. AMIC2_BCS_ENABLE,
  114. WCD_SUPPLIES_LPM_MODE,
  115. WCD_ADC1_MODE,
  116. WCD_ADC2_MODE,
  117. WCD_ADC3_MODE,
  118. WCD_ADC4_MODE,
  119. WCD_AUX_EN,
  120. WCD_EAR_EN,
  121. };
  122. enum {
  123. SYS_USAGE_0,
  124. SYS_USAGE_1,
  125. SYS_USAGE_2,
  126. SYS_USAGE_3,
  127. SYS_USAGE_4,
  128. SYS_USAGE_5,
  129. SYS_USAGE_6,
  130. SYS_USAGE_7,
  131. SYS_USAGE_8,
  132. SYS_USAGE_9,
  133. SYS_USAGE_10,
  134. SYS_USAGE_11,
  135. SYS_USAGE_12,
  136. SYS_USAGE_NUM,
  137. };
  138. enum {
  139. NO_MICB_USED,
  140. MICB1,
  141. MICB2,
  142. MICB3,
  143. MICB_NUM,
  144. };
  145. enum {
  146. ADC_MODE_INVALID = 0,
  147. ADC_MODE_HIFI,
  148. ADC_MODE_NORMAL,
  149. ADC_MODE_LP,
  150. };
  151. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  152. static int wcd9378_reset(struct device *dev);
  153. static int wcd9378_reset_low(struct device *dev);
  154. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  155. static void wcd9378_class_load(struct snd_soc_component *component);
  156. /* sys_usage:
  157. * rx0_rx1_hph_en,
  158. * rx0_ear_en, rx1_aux_en, rx2_aux_en, rx2_ear_en,
  159. * tx0_amic1_en, tx0_amic2_en, tx1_amic2_en, tx1_amic3_en,
  160. * tx2_amic1_en, tx2_amic4_en, tx1_for_jack, class_ab_en;
  161. */
  162. static const int sys_usage[SYS_USAGE_NUM] = {
  163. [SYS_USAGE_0] = 0x0c95, /*0b0 1100 1001 0101*/
  164. [SYS_USAGE_1] = 0x12a7, /*0b1 0010 1010 0111*/
  165. [SYS_USAGE_2] = 0x0c99, /*0b0 1100 1001 1001*/
  166. [SYS_USAGE_3] = 0x1aab, /*0b1 1010 1010 1011*/
  167. [SYS_USAGE_4] = 0x0894, /*0b0 1000 1001 0100*/
  168. [SYS_USAGE_5] = 0x11a6, /*0b1 0001 1010 0110*/
  169. [SYS_USAGE_6] = 0x0898, /*0b0 1000 1001 1000*/
  170. [SYS_USAGE_7] = 0x11ab, /*0b1 0001 1010 1011*/
  171. [SYS_USAGE_8] = 0x126a, /*0b1 0010 0110 1010*/
  172. [SYS_USAGE_9] = 0x116b, /*0b1 0001 0110 1011*/
  173. [SYS_USAGE_10] = 0x1ca7, /*0b1 1100 1010 0111*/
  174. [SYS_USAGE_11] = 0x1195, /*0b1 0001 1001 0101*/
  175. [SYS_USAGE_12] = 0x1296, /*0b1 0010 1001 0101*/
  176. };
  177. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  178. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  179. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  180. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  181. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  182. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  183. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  184. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  185. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  186. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  187. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  188. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  189. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  190. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  191. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  192. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  193. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  194. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  195. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  196. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  197. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  198. REGMAP_IRQ_REG(WCD9378_IRQ_SAPU_PROT_MODE_CHG, 2, 0x40),
  199. };
  200. static int wcd9378_handle_post_irq(void *data)
  201. {
  202. struct wcd9378_priv *wcd9378 = data;
  203. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  204. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, 0xff);
  205. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, 0xff);
  206. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, 0xff);
  207. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  208. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  209. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  210. wcd9378->tx_swr_dev->slave_irq_pending =
  211. ((sts1 || sts2 || sts3) ? true : false);
  212. return IRQ_HANDLED;
  213. }
  214. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  215. .name = "wcd9378",
  216. .irqs = wcd9378_regmap_irqs,
  217. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  218. .num_regs = 3,
  219. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  220. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  221. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  222. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  223. .use_ack = 1,
  224. .runtime_pm = false,
  225. .handle_post_irq = wcd9378_handle_post_irq,
  226. .irq_drv_data = NULL,
  227. };
  228. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  229. {
  230. int ret = 0;
  231. int bank = 0;
  232. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  233. if (ret)
  234. return -EINVAL;
  235. return ((bank & 0x40) ? 1 : 0);
  236. }
  237. static int wcd9378_init_reg(struct snd_soc_component *component)
  238. {
  239. struct wcd9378_priv *wcd9378 =
  240. snd_soc_component_get_drvdata(component);
  241. u32 val = 0;
  242. val = snd_soc_component_read(component, WCD9378_EFUSE_REG_16);
  243. if (!val)
  244. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  245. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  246. 0x03);
  247. else
  248. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  249. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  250. 0x01);
  251. /*0.9 Volts*/
  252. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  253. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  254. /*BG_EN ENABLE*/
  255. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  256. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  257. usleep_range(1000, 1010);
  258. /*LDOL_BG_SEL SLEEP_BG*/
  259. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  260. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  261. usleep_range(1000, 1010);
  262. /*Start up analog master bias. Sequence cannot change*/
  263. /*VBG_FINE_ADJ 0.005 Volts*/
  264. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  265. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  266. /*ANALOG_BIAS_EN ENABLE*/
  267. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  268. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  269. /*PRECHRG_EN ENABLE*/
  270. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  271. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  272. usleep_range(10000, 10010);
  273. /*PRECHRG_EN DISABLE*/
  274. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  275. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  276. /*End Analog Master Bias enable*/
  277. /*ANA_TXSCBIAS_CLK_EN ENABLE*/
  278. snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
  279. WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK, 0x01);
  280. /*SEQ_BYPASS ENABLE*/
  281. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  282. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  283. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  284. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  285. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  286. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  287. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  288. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  289. /*IBIAS_LDO_DRIVER 5e-06*/
  290. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  291. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  292. /*IBIAS_LDO_DRIVER 5e-06*/
  293. snd_soc_component_update_bits(component, WCD9378_MICB2_TEST_CTL_2,
  294. WCD9378_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  295. /*IBIAS_LDO_DRIVER 5e-06*/
  296. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  297. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  298. /*HD2_RES_DIV_CTL_L 82.77*/
  299. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  300. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  301. /*HD2_RES_DIV_CTL_R 82.77*/
  302. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  303. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  304. /*RDAC_GAINCTL 0.55*/
  305. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  306. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  307. /*HPH_UP_T0: 0.002*/
  308. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  309. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  310. /*HPH_UP_T9: 0.002*/
  311. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  312. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  313. /*HPH_DN_T0: 0.007*/
  314. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  315. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  316. /*SM0 MB SEL:MB1*/
  317. snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
  318. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, 0x01);
  319. /*SM1 MB SEL:MB2*/
  320. snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
  321. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, 0x02);
  322. /*SM2 MB SEL:MB3*/
  323. snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
  324. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, 0x03);
  325. /*INIT SYS_USAGE*/
  326. snd_soc_component_update_bits(component,
  327. WCD9378_SYS_USAGE_CTRL,
  328. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  329. 0);
  330. wcd9378->sys_usage = 0;
  331. wcd9378_class_load(component);
  332. return 0;
  333. }
  334. static int wcd9378_set_port_params(struct snd_soc_component *component,
  335. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  336. u8 *ch_mask, u32 *ch_rate,
  337. u8 *port_type, u8 path)
  338. {
  339. int i, j;
  340. u8 num_ports = 0;
  341. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  342. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  343. switch (path) {
  344. case CODEC_RX:
  345. map = &wcd9378->rx_port_mapping;
  346. num_ports = wcd9378->num_rx_ports;
  347. break;
  348. case CODEC_TX:
  349. map = &wcd9378->tx_port_mapping;
  350. num_ports = wcd9378->num_tx_ports;
  351. break;
  352. default:
  353. dev_err(component->dev, "%s Invalid path selected %u\n",
  354. __func__, path);
  355. return -EINVAL;
  356. }
  357. for (i = 0; i <= num_ports; i++) {
  358. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  359. if ((*map)[i][j].slave_port_type == slv_prt_type)
  360. goto found;
  361. }
  362. }
  363. found:
  364. if (i > num_ports || j == MAX_CH_PER_PORT) {
  365. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  366. __func__, slv_prt_type);
  367. return -EINVAL;
  368. }
  369. *port_id = i;
  370. *num_ch = (*map)[i][j].num_ch;
  371. *ch_mask = (*map)[i][j].ch_mask;
  372. *ch_rate = (*map)[i][j].ch_rate;
  373. *port_type = (*map)[i][j].master_port_type;
  374. return 0;
  375. }
  376. static int wcd9378_parse_port_params(struct device *dev,
  377. char *prop, u8 path)
  378. {
  379. u32 *dt_array, map_size, max_uc;
  380. int ret = 0;
  381. u32 cnt = 0;
  382. u32 i, j;
  383. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  384. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  385. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  386. switch (path) {
  387. case CODEC_TX:
  388. map = &wcd9378->tx_port_params;
  389. map_uc = &wcd9378->swr_tx_port_params;
  390. break;
  391. default:
  392. ret = -EINVAL;
  393. goto err_port_map;
  394. }
  395. if (!of_find_property(dev->of_node, prop,
  396. &map_size)) {
  397. dev_err(dev, "missing port mapping prop %s\n", prop);
  398. ret = -EINVAL;
  399. goto err_port_map;
  400. }
  401. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  402. if (max_uc != SWR_UC_MAX) {
  403. dev_err(dev, "%s: port params not provided for all usecases\n",
  404. __func__);
  405. ret = -EINVAL;
  406. goto err_port_map;
  407. }
  408. dt_array = kzalloc(map_size, GFP_KERNEL);
  409. if (!dt_array) {
  410. ret = -ENOMEM;
  411. goto err_alloc;
  412. }
  413. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  414. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  415. if (ret) {
  416. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  417. __func__, prop);
  418. goto err_pdata_fail;
  419. }
  420. for (i = 0; i < max_uc; i++) {
  421. for (j = 0; j < SWR_NUM_PORTS; j++) {
  422. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  423. (*map)[i][j].offset1 = dt_array[cnt];
  424. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  425. }
  426. (*map_uc)[i].pp = &(*map)[i][0];
  427. }
  428. kfree(dt_array);
  429. return 0;
  430. err_pdata_fail:
  431. kfree(dt_array);
  432. err_alloc:
  433. err_port_map:
  434. return ret;
  435. }
  436. static int wcd9378_parse_port_mapping(struct device *dev,
  437. char *prop, u8 path)
  438. {
  439. u32 *dt_array, map_size, map_length;
  440. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  441. u32 slave_port_type, master_port_type;
  442. u32 i, ch_iter = 0;
  443. int ret = 0;
  444. u8 *num_ports = NULL;
  445. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  446. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  447. switch (path) {
  448. case CODEC_RX:
  449. map = &wcd9378->rx_port_mapping;
  450. num_ports = &wcd9378->num_rx_ports;
  451. break;
  452. case CODEC_TX:
  453. map = &wcd9378->tx_port_mapping;
  454. num_ports = &wcd9378->num_tx_ports;
  455. break;
  456. default:
  457. dev_err(dev, "%s Invalid path selected %u\n",
  458. __func__, path);
  459. return -EINVAL;
  460. }
  461. if (!of_find_property(dev->of_node, prop,
  462. &map_size)) {
  463. dev_err(dev, "missing port mapping prop %s\n", prop);
  464. ret = -EINVAL;
  465. goto err_port_map;
  466. }
  467. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  468. dt_array = kzalloc(map_size, GFP_KERNEL);
  469. if (!dt_array) {
  470. ret = -ENOMEM;
  471. goto err_alloc;
  472. }
  473. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  474. NUM_SWRS_DT_PARAMS * map_length);
  475. if (ret) {
  476. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  477. __func__, prop);
  478. goto err_pdata_fail;
  479. }
  480. for (i = 0; i < map_length; i++) {
  481. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  482. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  483. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  484. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  485. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  486. if (port_num != old_port_num)
  487. ch_iter = 0;
  488. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  489. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  490. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  491. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  492. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  493. old_port_num = port_num;
  494. }
  495. *num_ports = port_num;
  496. kfree(dt_array);
  497. return 0;
  498. err_pdata_fail:
  499. kfree(dt_array);
  500. err_alloc:
  501. err_port_map:
  502. return ret;
  503. }
  504. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  505. u8 slv_port_type, int clk_rate,
  506. u8 enable)
  507. {
  508. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  509. u8 port_id, num_ch, ch_mask;
  510. u8 ch_type = 0;
  511. u32 ch_rate;
  512. int slave_ch_idx;
  513. u8 num_port = 1;
  514. int ret = 0;
  515. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  516. &num_ch, &ch_mask, &ch_rate,
  517. &ch_type, CODEC_TX);
  518. if (ret)
  519. return ret;
  520. if (clk_rate)
  521. ch_rate = clk_rate;
  522. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  523. if (slave_ch_idx != -EINVAL)
  524. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  525. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  526. __func__, slave_ch_idx, ch_type);
  527. if (enable)
  528. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  529. num_port, &ch_mask, &ch_rate,
  530. &num_ch, &ch_type);
  531. else
  532. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  533. num_port, &ch_mask, &ch_type);
  534. return ret;
  535. }
  536. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  537. u8 slv_port_type, u8 enable)
  538. {
  539. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  540. u8 port_id, num_ch, ch_mask, port_type;
  541. u32 ch_rate;
  542. u8 num_port = 1;
  543. int ret = 0;
  544. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  545. &num_ch, &ch_mask, &ch_rate,
  546. &port_type, CODEC_RX);
  547. if (ret)
  548. return ret;
  549. if (enable)
  550. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  551. num_port, &ch_mask, &ch_rate,
  552. &num_ch, &port_type);
  553. else
  554. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  555. num_port, &ch_mask, &port_type);
  556. return ret;
  557. }
  558. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  559. struct snd_kcontrol *kcontrol,
  560. int event)
  561. {
  562. struct snd_soc_component *component =
  563. snd_soc_dapm_to_component(w->dapm);
  564. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  565. int mode = wcd9378->hph_mode;
  566. int ret = 0;
  567. int bank = 0;
  568. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  569. w->name, event);
  570. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  571. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  572. wcd9378_rx_connect_port(component, CLSH,
  573. SND_SOC_DAPM_EVENT_ON(event));
  574. }
  575. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  576. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  577. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  578. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  579. ret = swr_slvdev_datapath_control(
  580. wcd9378->rx_swr_dev,
  581. wcd9378->rx_swr_dev->dev_num,
  582. false);
  583. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  584. }
  585. return ret;
  586. }
  587. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  588. struct snd_kcontrol *kcontrol,
  589. int event)
  590. {
  591. struct snd_soc_component *component =
  592. snd_soc_dapm_to_component(w->dapm);
  593. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  594. u32 dmic_clk_reg, dmic_clk_en_reg;
  595. s32 *dmic_clk_cnt;
  596. u8 dmic_ctl_shift = 0;
  597. u8 dmic_clk_shift = 0;
  598. u8 dmic_clk_mask = 0;
  599. u32 dmic2_left_en = 0;
  600. int ret = 0;
  601. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  602. w->name, event);
  603. switch (w->shift) {
  604. case 0:
  605. case 1:
  606. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  607. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  608. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  609. dmic_clk_mask = 0x0F;
  610. dmic_clk_shift = 0x00;
  611. dmic_ctl_shift = 0x00;
  612. break;
  613. case 2:
  614. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  615. fallthrough;
  616. case 3:
  617. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  618. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  619. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  620. dmic_clk_mask = 0xF0;
  621. dmic_clk_shift = 0x04;
  622. dmic_ctl_shift = 0x01;
  623. break;
  624. case 4:
  625. case 5:
  626. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  627. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  628. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  629. dmic_clk_mask = 0x0F;
  630. dmic_clk_shift = 0x00;
  631. dmic_ctl_shift = 0x02;
  632. break;
  633. default:
  634. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  635. __func__);
  636. return -EINVAL;
  637. };
  638. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  639. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  640. switch (event) {
  641. case SND_SOC_DAPM_PRE_PMU:
  642. snd_soc_component_update_bits(component,
  643. WCD9378_CDC_AMIC_CTL,
  644. (0x01 << dmic_ctl_shift), 0x00);
  645. /* 250us sleep as per HW requirement */
  646. usleep_range(250, 260);
  647. if (dmic2_left_en)
  648. snd_soc_component_update_bits(component,
  649. dmic2_left_en, 0x80, 0x80);
  650. /* Setting DMIC clock rate to 2.4MHz */
  651. snd_soc_component_update_bits(component,
  652. dmic_clk_reg, dmic_clk_mask,
  653. (0x03 << dmic_clk_shift));
  654. snd_soc_component_update_bits(component,
  655. dmic_clk_en_reg, 0x08, 0x08);
  656. /* enable clock scaling */
  657. snd_soc_component_update_bits(component,
  658. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  659. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  660. wcd9378->tx_swr_dev->dev_num,
  661. true);
  662. break;
  663. case SND_SOC_DAPM_POST_PMD:
  664. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  665. false);
  666. snd_soc_component_update_bits(component,
  667. WCD9378_CDC_AMIC_CTL,
  668. (0x01 << dmic_ctl_shift),
  669. (0x01 << dmic_ctl_shift));
  670. if (dmic2_left_en)
  671. snd_soc_component_update_bits(component,
  672. dmic2_left_en, 0x80, 0x00);
  673. snd_soc_component_update_bits(component,
  674. dmic_clk_en_reg, 0x08, 0x00);
  675. break;
  676. };
  677. return ret;
  678. }
  679. /*
  680. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  681. * @micb_mv: micbias in mv
  682. *
  683. * return register value converted
  684. */
  685. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  686. {
  687. /* min micbias voltage is 1V and maximum is 2.85V */
  688. if (micb_mv < 1000 || micb_mv > 2850) {
  689. pr_err("%s: unsupported micbias voltage\n", __func__);
  690. return -EINVAL;
  691. }
  692. return (micb_mv - 1000) / 50;
  693. }
  694. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  695. /*
  696. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  697. * @component: handle to snd_soc_component *
  698. * @req_volt: micbias voltage to be set
  699. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  700. *
  701. * return 0 if adjustment is success or error code in case of failure
  702. */
  703. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  704. u32 micb_mv, int micb_num)
  705. {
  706. int vcout_ctl;
  707. switch (micb_mv) {
  708. case 2200:
  709. return MICB_USAGE_VAL_2P2V;
  710. case 2700:
  711. return MICB_USAGE_VAL_2P7V;
  712. case 2800:
  713. return MICB_USAGE_VAL_2P8V;
  714. default:
  715. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  716. if (micb_num == MIC_BIAS_1) {
  717. snd_soc_component_update_bits(component,
  718. WCD9378_MICB_REMAP_TABLE_VAL_3,
  719. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  720. vcout_ctl);
  721. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  722. } else if (micb_num == MIC_BIAS_2) {
  723. snd_soc_component_update_bits(component,
  724. WCD9378_MICB_REMAP_TABLE_VAL_4,
  725. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  726. vcout_ctl);
  727. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  728. } else if (micb_num == MIC_BIAS_3) {
  729. snd_soc_component_update_bits(component,
  730. WCD9378_MICB_REMAP_TABLE_VAL_5,
  731. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  732. vcout_ctl);
  733. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  734. }
  735. }
  736. return 0;
  737. }
  738. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  739. u32 micb_mv, int micb_num)
  740. {
  741. switch (micb_mv) {
  742. case 0:
  743. return MICB_USAGE_VAL_PULL_DOWN;
  744. case 1200:
  745. return MICB_USAGE_VAL_1P2V;
  746. case 1800:
  747. return MICB_USAGE_VAL_1P8VORPULLUP;
  748. case 2500:
  749. return MICB_USAGE_VAL_2P5V;
  750. case 2750:
  751. return MICB_USAGE_VAL_2P75V;
  752. default:
  753. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  754. }
  755. return MICB_USAGE_VAL_DISABLE;
  756. }
  757. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  758. int req_volt, int micb_num)
  759. {
  760. struct wcd9378_priv *wcd9378 =
  761. snd_soc_component_get_drvdata(component);
  762. int micb_usage = 0, micb_mask = 0, req_vout_ctl = 0;
  763. if (wcd9378 == NULL) {
  764. dev_err(component->dev,
  765. "%s: wcd9378 private data is NULL\n", __func__);
  766. return -EINVAL;
  767. }
  768. switch (micb_num) {
  769. case MIC_BIAS_1:
  770. micb_usage = WCD9378_IT11_USAGE;
  771. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  772. break;
  773. case MIC_BIAS_2:
  774. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  775. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  776. break;
  777. case MIC_BIAS_3:
  778. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  779. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  780. break;
  781. default:
  782. dev_err(component->dev,
  783. "%s: wcd9378 private data is NULL\n", __func__);
  784. break;
  785. }
  786. mutex_lock(&wcd9378->micb_lock);
  787. req_vout_ctl =
  788. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  789. snd_soc_component_update_bits(component,
  790. micb_usage, micb_mask, req_vout_ctl);
  791. if (micb_num == MIC_BIAS_2) {
  792. dev_err(component->dev,
  793. "%s: sj micbias set\n", __func__);
  794. snd_soc_component_update_bits(component,
  795. WCD9378_IT31_MICB,
  796. WCD9378_IT31_MICB_IT31_MICB_MASK,
  797. req_vout_ctl);
  798. wcd9378->curr_micbias2 = req_volt;
  799. }
  800. mutex_unlock(&wcd9378->micb_lock);
  801. return 0;
  802. }
  803. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  804. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  805. bool bcs_disable)
  806. {
  807. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  808. if (wcd9378->update_wcd_event) {
  809. if (bcs_disable)
  810. wcd9378->update_wcd_event(wcd9378->handle,
  811. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  812. else
  813. wcd9378->update_wcd_event(wcd9378->handle,
  814. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  815. }
  816. }
  817. static int wcd9378_get_clk_rate(int mode)
  818. {
  819. int rate;
  820. switch (mode) {
  821. case ADC_MODE_LP:
  822. rate = SWR_CLK_RATE_4P8MHZ;
  823. break;
  824. case ADC_MODE_INVALID:
  825. case ADC_MODE_NORMAL:
  826. case ADC_MODE_HIFI:
  827. default:
  828. rate = SWR_CLK_RATE_9P6MHZ;
  829. break;
  830. }
  831. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  832. return rate;
  833. }
  834. static int wcd9378_get_adc_mode_val(int mode)
  835. {
  836. int ret = 0;
  837. switch (mode) {
  838. case ADC_MODE_INVALID:
  839. case ADC_MODE_NORMAL:
  840. ret = ADC_MODE_VAL_NORMAL;
  841. break;
  842. case ADC_MODE_HIFI:
  843. ret = ADC_MODE_VAL_HIFI;
  844. break;
  845. case ADC_MODE_LP:
  846. ret = ADC_MODE_VAL_LP;
  847. break;
  848. default:
  849. ret = -EINVAL;
  850. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  851. break;
  852. }
  853. return ret;
  854. }
  855. static int wcd9378_sys_usage_auto_udpate(struct snd_soc_component *component,
  856. int sys_usage_bit, bool set_enable)
  857. {
  858. struct wcd9378_priv *wcd9378 =
  859. snd_soc_component_get_drvdata(component);
  860. int i = 0;
  861. dev_dbg(component->dev,
  862. "%s: enter, current sys_usage: %d, sys_usage_status: 0x%x, sys_usage_bit: %d, set_enable: %d\n",
  863. __func__, wcd9378->sys_usage,
  864. wcd9378->sys_usage_status,
  865. sys_usage_bit, set_enable);
  866. mutex_lock(&wcd9378->sys_usage_lock);
  867. if (set_enable) {
  868. set_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  869. if ((sys_usage[wcd9378->sys_usage] &
  870. wcd9378->sys_usage_status) == wcd9378->sys_usage_status)
  871. goto exit;
  872. for (i = 0; i < SYS_USAGE_NUM; i++) {
  873. if ((sys_usage[i] & wcd9378->sys_usage_status)
  874. == wcd9378->sys_usage_status) {
  875. snd_soc_component_update_bits(component,
  876. WCD9378_SYS_USAGE_CTRL,
  877. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  878. i);
  879. wcd9378->sys_usage = i;
  880. dev_dbg(component->dev, "%s: update sys_usage: %d\n",
  881. __func__, wcd9378->sys_usage);
  882. goto exit;
  883. }
  884. }
  885. dev_dbg(component->dev, "%s: cannot find sys_usage\n",
  886. __func__);
  887. } else {
  888. clear_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  889. }
  890. exit:
  891. mutex_unlock(&wcd9378->sys_usage_lock);
  892. return 0;
  893. }
  894. static int wcd9378_sys_usage_bit_get(
  895. struct snd_soc_component *component, u32 w_shift,
  896. int *sys_usage_bit, int event)
  897. {
  898. struct wcd9378_priv *wcd9378 =
  899. snd_soc_component_get_drvdata(component);
  900. dev_dbg(component->dev, "%s: wshift: %d event: %d\n", __func__,
  901. w_shift, event);
  902. switch (event) {
  903. case SND_SOC_DAPM_PRE_PMU:
  904. switch (w_shift) {
  905. case ADC1:
  906. if ((snd_soc_component_read(component,
  907. WCD9378_TX_NEW_TX_CH12_MUX) &
  908. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x01) {
  909. *sys_usage_bit = TX0_AMIC1_EN;
  910. } else if ((snd_soc_component_read(component,
  911. WCD9378_TX_NEW_TX_CH12_MUX) &
  912. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x02) {
  913. *sys_usage_bit = TX0_AMIC2_EN;
  914. } else {
  915. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  916. __func__);
  917. return -EINVAL;
  918. }
  919. break;
  920. case ADC2:
  921. if ((snd_soc_component_read(component,
  922. WCD9378_TX_NEW_TX_CH12_MUX) &
  923. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  924. *sys_usage_bit = TX1_AMIC2_EN;
  925. } else if ((snd_soc_component_read(component,
  926. WCD9378_TX_NEW_TX_CH12_MUX) &
  927. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x18) {
  928. *sys_usage_bit = TX1_AMIC3_EN;
  929. } else {
  930. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  931. __func__);
  932. return -EINVAL;
  933. }
  934. break;
  935. case ADC3:
  936. if ((snd_soc_component_read(component,
  937. WCD9378_TX_NEW_TX_CH34_MUX) &
  938. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x01) {
  939. *sys_usage_bit = TX2_AMIC1_EN;
  940. } else if ((snd_soc_component_read(component,
  941. WCD9378_TX_NEW_TX_CH34_MUX) &
  942. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x03) {
  943. *sys_usage_bit = TX2_AMIC4_EN;
  944. } else {
  945. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  946. __func__);
  947. return -EINVAL;
  948. }
  949. break;
  950. default:
  951. break;
  952. }
  953. break;
  954. case SND_SOC_DAPM_POST_PMD:
  955. switch (w_shift) {
  956. case ADC1:
  957. if (test_bit(TX0_AMIC1_EN, &wcd9378->sys_usage_status))
  958. *sys_usage_bit = TX0_AMIC1_EN;
  959. if (test_bit(TX0_AMIC2_EN, &wcd9378->sys_usage_status))
  960. *sys_usage_bit = TX0_AMIC2_EN;
  961. break;
  962. case ADC2:
  963. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  964. *sys_usage_bit = TX1_AMIC2_EN;
  965. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status))
  966. *sys_usage_bit = TX1_AMIC3_EN;
  967. break;
  968. case ADC3:
  969. if (test_bit(TX2_AMIC1_EN, &wcd9378->sys_usage_status))
  970. *sys_usage_bit = TX2_AMIC1_EN;
  971. if (test_bit(TX2_AMIC4_EN, &wcd9378->sys_usage_status))
  972. *sys_usage_bit = TX2_AMIC4_EN;
  973. break;
  974. default:
  975. break;
  976. }
  977. break;
  978. default:
  979. break;
  980. }
  981. dev_dbg(component->dev, "%s: done, event: %d, sys_usage_bit: %d\n",
  982. __func__, event, *sys_usage_bit);
  983. return 0;
  984. }
  985. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  986. struct snd_kcontrol *kcontrol, int event)
  987. {
  988. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  989. struct wcd9378_priv *wcd9378 =
  990. snd_soc_component_get_drvdata(component);
  991. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  992. int act_ps = 0, sys_usage_bit = 0;
  993. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  994. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  995. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  996. w->name, w->shift, event);
  997. ret = wcd9378_sys_usage_bit_get(component, w->shift, &sys_usage_bit, event);
  998. if (ret < 0)
  999. return ret;
  1000. switch (event) {
  1001. case SND_SOC_DAPM_PRE_PMU:
  1002. /*Update sys_usage*/
  1003. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, true);
  1004. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  1005. if (mode_val < 0) {
  1006. dev_dbg(component->dev,
  1007. "%s: invalid mode, setting to normal mode\n",
  1008. __func__);
  1009. mode_val = ADC_MODE_VAL_NORMAL;
  1010. }
  1011. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  1012. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  1013. WCD9378_TX_NEW_TX_CH12_MUX) &
  1014. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  1015. if (!wcd9378->bcs_dis) {
  1016. wcd9378_tx_connect_port(component, MBHC,
  1017. SWR_CLK_RATE_4P8MHZ, true);
  1018. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1019. }
  1020. }
  1021. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  1022. wcd9378_tx_connect_port(component, w->shift, rate,
  1023. true);
  1024. switch (w->shift) {
  1025. case ADC1:
  1026. /*SMP MIC0 IT11 USAGE SET*/
  1027. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  1028. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  1029. /*Hold TXFE in Initialization During Startup*/
  1030. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1031. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  1032. /*Power up TX0 sequencer*/
  1033. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1034. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1035. break;
  1036. case ADC2:
  1037. /*Check if amic2 is connected to ADC2 MUX*/
  1038. if ((snd_soc_component_read(component,
  1039. WCD9378_TX_NEW_TX_CH12_MUX) &
  1040. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  1041. /*SMP JACK IT31 USAGE SET*/
  1042. snd_soc_component_update_bits(component,
  1043. WCD9378_IT31_USAGE,
  1044. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  1045. /*Power up TX1 sequencer*/
  1046. snd_soc_component_update_bits(component,
  1047. WCD9378_PDE34_REQ_PS,
  1048. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  1049. } else {
  1050. snd_soc_component_update_bits(component,
  1051. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  1052. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  1053. mode_val);
  1054. /*Hold TXFE in Initialization During Startup*/
  1055. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1056. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  1057. /*Power up TX1 sequencer*/
  1058. snd_soc_component_update_bits(component,
  1059. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1060. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1061. 0x00);
  1062. }
  1063. break;
  1064. case ADC3:
  1065. /*SMP MIC2 IT11 USAGE SET*/
  1066. snd_soc_component_update_bits(component,
  1067. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  1068. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  1069. mode_val);
  1070. /*Hold TXFE in Initialization During Startup*/
  1071. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1072. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  1073. /*Power up TX2 sequencer*/
  1074. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1075. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1076. break;
  1077. default:
  1078. break;
  1079. }
  1080. /*default delay 800us*/
  1081. usleep_range(800, 810);
  1082. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  1083. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1084. wcd9378->tx_swr_dev->dev_num,
  1085. true);
  1086. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  1087. switch (w->shift) {
  1088. case ADC1:
  1089. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1090. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1091. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  1092. if (act_ps)
  1093. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  1094. __func__, act_ps);
  1095. else
  1096. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  1097. __func__, act_ps);
  1098. break;
  1099. case ADC2:
  1100. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1101. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  1102. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1103. act_ps = snd_soc_component_read(component,
  1104. WCD9378_PDE34_ACT_PS);
  1105. else
  1106. act_ps = snd_soc_component_read(component,
  1107. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  1108. if (act_ps)
  1109. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  1110. __func__, act_ps);
  1111. else
  1112. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  1113. __func__, act_ps);
  1114. break;
  1115. case ADC3:
  1116. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1117. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1118. act_ps = snd_soc_component_read(component,
  1119. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  1120. if (act_ps)
  1121. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  1122. __func__, act_ps);
  1123. else
  1124. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  1125. __func__, act_ps);
  1126. break;
  1127. };
  1128. break;
  1129. case SND_SOC_DAPM_POST_PMD:
  1130. wcd9378_tx_connect_port(component, w->shift, 0, false);
  1131. if (w->shift == ADC2 &&
  1132. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  1133. wcd9378_tx_connect_port(component, MBHC, 0,
  1134. false);
  1135. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1136. }
  1137. switch (w->shift) {
  1138. case ADC1:
  1139. /*Normal TXFE Startup*/
  1140. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1141. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1142. /*tear down TX0 sequencer*/
  1143. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1144. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1145. break;
  1146. case ADC2:
  1147. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1148. /*tear down TX1 sequencer*/
  1149. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  1150. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  1151. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
  1152. /*Normal TXFE Startup*/
  1153. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1154. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1155. /*tear down TX1 sequencer*/
  1156. snd_soc_component_update_bits(component,
  1157. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1158. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1159. 0x03);
  1160. }
  1161. break;
  1162. case ADC3:
  1163. /*Normal TXFE Startup*/
  1164. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1165. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1166. /*tear down TX2 sequencer*/
  1167. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1168. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1169. break;
  1170. default:
  1171. break;
  1172. }
  1173. /*default delay 800us*/
  1174. usleep_range(800, 810);
  1175. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  1176. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1177. wcd9378->tx_swr_dev->dev_num,
  1178. false);
  1179. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  1180. /*Disable sys_usage_status*/
  1181. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, false);
  1182. break;
  1183. default:
  1184. break;
  1185. }
  1186. return ret;
  1187. }
  1188. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1189. struct snd_kcontrol *kcontrol,
  1190. int event)
  1191. {
  1192. struct snd_soc_component *component =
  1193. snd_soc_dapm_to_component(w->dapm);
  1194. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1195. int ret = 0;
  1196. switch (event) {
  1197. case SND_SOC_DAPM_PRE_PMU:
  1198. wcd9378_tx_connect_port(component, w->shift,
  1199. SWR_CLK_RATE_2P4MHZ, true);
  1200. break;
  1201. case SND_SOC_DAPM_POST_PMD:
  1202. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1203. wcd9378->tx_swr_dev->dev_num,
  1204. false);
  1205. break;
  1206. };
  1207. return ret;
  1208. }
  1209. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1210. struct snd_kcontrol *kcontrol,
  1211. int event)
  1212. {
  1213. struct snd_soc_component *component =
  1214. snd_soc_dapm_to_component(w->dapm);
  1215. int micb_num = 0;
  1216. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1217. __func__, w->name, event);
  1218. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1219. micb_num = MIC_BIAS_1;
  1220. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1221. micb_num = MIC_BIAS_2;
  1222. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1223. micb_num = MIC_BIAS_3;
  1224. else
  1225. return -EINVAL;
  1226. switch (event) {
  1227. case SND_SOC_DAPM_PRE_PMU:
  1228. wcd9378_micbias_control(component, micb_num,
  1229. MICB_ENABLE, true);
  1230. break;
  1231. case SND_SOC_DAPM_POST_PMU:
  1232. usleep_range(1000, 1100);
  1233. break;
  1234. case SND_SOC_DAPM_POST_PMD:
  1235. wcd9378_micbias_control(component, micb_num,
  1236. MICB_DISABLE, true);
  1237. break;
  1238. };
  1239. return 0;
  1240. }
  1241. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1242. struct snd_kcontrol *kcontrol,
  1243. int event)
  1244. {
  1245. struct snd_soc_component *component =
  1246. snd_soc_dapm_to_component(w->dapm);
  1247. int micb_num = 0;
  1248. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1249. __func__, w->name, event);
  1250. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1251. micb_num = MIC_BIAS_1;
  1252. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1253. micb_num = MIC_BIAS_2;
  1254. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1255. micb_num = MIC_BIAS_3;
  1256. else
  1257. return -EINVAL;
  1258. switch (event) {
  1259. case SND_SOC_DAPM_PRE_PMU:
  1260. wcd9378_micbias_control(component, micb_num,
  1261. MICB_PULLUP_ENABLE, true);
  1262. break;
  1263. case SND_SOC_DAPM_POST_PMU:
  1264. usleep_range(1000, 1100);
  1265. break;
  1266. case SND_SOC_DAPM_POST_PMD:
  1267. wcd9378_micbias_control(component, micb_num,
  1268. MICB_PULLUP_DISABLE, true);
  1269. break;
  1270. };
  1271. return 0;
  1272. }
  1273. /*
  1274. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1275. * @component: handle to snd_soc_component *
  1276. *
  1277. * return wcd9378_mbhc handle or error code in case of failure
  1278. */
  1279. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1280. {
  1281. struct wcd9378_priv *wcd9378;
  1282. if (!component) {
  1283. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1284. return NULL;
  1285. }
  1286. wcd9378 = snd_soc_component_get_drvdata(component);
  1287. if (!wcd9378) {
  1288. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1289. return NULL;
  1290. }
  1291. return wcd9378->mbhc;
  1292. }
  1293. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1294. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1295. struct snd_kcontrol *kcontrol,
  1296. int event)
  1297. {
  1298. struct snd_soc_component *component =
  1299. snd_soc_dapm_to_component(w->dapm);
  1300. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1301. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1302. w->name, event);
  1303. switch (event) {
  1304. case SND_SOC_DAPM_PRE_PMU:
  1305. /*OCP FSM EN*/
  1306. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1307. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1308. /*SCD OP EN*/
  1309. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1310. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1311. /*HPHL ENABLE*/
  1312. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1313. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1314. /*OPAMP_CHOP_CLK DISABLE*/
  1315. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1316. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1317. wcd9378_rx_connect_port(component, HPH_L, true);
  1318. if (wcd9378->comp1_enable) {
  1319. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1320. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1321. wcd9378_rx_connect_port(component, COMP_L, true);
  1322. }
  1323. if (wcd9378->update_wcd_event)
  1324. wcd9378->update_wcd_event(wcd9378->handle,
  1325. SLV_BOLERO_EVT_RX_MUTE,
  1326. (WCD_RX1 << 0x10));
  1327. break;
  1328. case SND_SOC_DAPM_POST_PMD:
  1329. /*OCP FSM DISABLE*/
  1330. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1331. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1332. /*SCD OP DISABLE*/
  1333. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1334. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1335. /*HPHL DISABLE*/
  1336. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1337. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1338. wcd9378_rx_connect_port(component, HPH_L, false);
  1339. if (wcd9378->comp1_enable) {
  1340. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1341. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1342. wcd9378_rx_connect_port(component, COMP_R, false);
  1343. }
  1344. break;
  1345. default:
  1346. break;
  1347. };
  1348. return 0;
  1349. }
  1350. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1351. struct snd_kcontrol *kcontrol,
  1352. int event)
  1353. {
  1354. struct snd_soc_component *component =
  1355. snd_soc_dapm_to_component(w->dapm);
  1356. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1357. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1358. w->name, event);
  1359. switch (event) {
  1360. case SND_SOC_DAPM_PRE_PMU:
  1361. /*OCP FSM EN*/
  1362. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1363. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1364. /*SCD OP EN*/
  1365. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1366. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1367. /*HPHR ENABLE*/
  1368. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1369. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1370. /*OPAMP_CHOP_CLK DISABLE*/
  1371. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1372. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1373. wcd9378_rx_connect_port(component, HPH_R, true);
  1374. if (wcd9378->comp2_enable) {
  1375. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1376. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1377. wcd9378_rx_connect_port(component, COMP_R, true);
  1378. }
  1379. break;
  1380. case SND_SOC_DAPM_POST_PMD:
  1381. /*OCP FSM DISABLE*/
  1382. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1383. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1384. /*SCD OP DISABLE*/
  1385. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1386. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1387. /*HPHR DISABLE*/
  1388. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1389. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1390. wcd9378_rx_connect_port(component, HPH_R, false);
  1391. if (wcd9378->comp2_enable) {
  1392. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1393. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1394. wcd9378_rx_connect_port(component, COMP_R, false);
  1395. }
  1396. break;
  1397. default:
  1398. break;
  1399. };
  1400. return 0;
  1401. }
  1402. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1403. struct snd_kcontrol *kcontrol,
  1404. int event)
  1405. {
  1406. struct snd_soc_component *component =
  1407. snd_soc_dapm_to_component(w->dapm);
  1408. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1409. int bank = 0;
  1410. int act_ps = 0;
  1411. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1412. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1413. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1414. w->name, event);
  1415. switch (event) {
  1416. case SND_SOC_DAPM_PRE_PMU:
  1417. if (wcd9378->update_wcd_event)
  1418. wcd9378->update_wcd_event(wcd9378->handle,
  1419. SLV_BOLERO_EVT_RX_MUTE,
  1420. (WCD_RX1 << 0x10 | 0x01));
  1421. if (wcd9378->update_wcd_event)
  1422. wcd9378->update_wcd_event(wcd9378->handle,
  1423. SLV_BOLERO_EVT_RX_MUTE,
  1424. (WCD_RX1 << 0x10));
  1425. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1426. if (act_ps)
  1427. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1428. __func__, act_ps);
  1429. else
  1430. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1431. __func__, act_ps);
  1432. break;
  1433. case SND_SOC_DAPM_POST_PMD:
  1434. if (wcd9378->update_wcd_event)
  1435. wcd9378->update_wcd_event(wcd9378->handle,
  1436. SLV_BOLERO_EVT_RX_MUTE,
  1437. (WCD_RX1 << 0x10 | 0x1));
  1438. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1439. wcd9378->update_wcd_event(wcd9378->handle,
  1440. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1441. (WCD_RX1 << 0x10));
  1442. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1443. WCD_EVENT_POST_HPHL_PA_OFF,
  1444. &wcd9378->mbhc->wcd_mbhc);
  1445. break;
  1446. default:
  1447. break;
  1448. };
  1449. return 0;
  1450. }
  1451. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1452. struct snd_kcontrol *kcontrol,
  1453. int event)
  1454. {
  1455. struct snd_soc_component *component =
  1456. snd_soc_dapm_to_component(w->dapm);
  1457. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1458. int act_ps = 0;
  1459. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1460. w->name, event);
  1461. switch (event) {
  1462. case SND_SOC_DAPM_PRE_PMU:
  1463. if (wcd9378->update_wcd_event)
  1464. wcd9378->update_wcd_event(wcd9378->handle,
  1465. SLV_BOLERO_EVT_RX_MUTE,
  1466. (WCD_RX2 << 0x10 | 0x1));
  1467. if (wcd9378->update_wcd_event)
  1468. wcd9378->update_wcd_event(wcd9378->handle,
  1469. SLV_BOLERO_EVT_RX_MUTE,
  1470. (WCD_RX2 << 0x10));
  1471. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1472. if (act_ps)
  1473. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1474. __func__, act_ps);
  1475. else
  1476. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1477. __func__, act_ps);
  1478. break;
  1479. case SND_SOC_DAPM_POST_PMD:
  1480. if (wcd9378->update_wcd_event)
  1481. wcd9378->update_wcd_event(wcd9378->handle,
  1482. SLV_BOLERO_EVT_RX_MUTE,
  1483. (WCD_RX2 << 0x10 | 0x1));
  1484. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1485. wcd9378->update_wcd_event(wcd9378->handle,
  1486. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1487. (WCD_RX2 << 0x10));
  1488. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1489. WCD_EVENT_POST_HPHR_PA_OFF,
  1490. &wcd9378->mbhc->wcd_mbhc);
  1491. break;
  1492. default:
  1493. break;
  1494. };
  1495. return 0;
  1496. }
  1497. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1498. struct snd_kcontrol *kcontrol,
  1499. int event)
  1500. {
  1501. struct snd_soc_component *component =
  1502. snd_soc_dapm_to_component(w->dapm);
  1503. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1504. int ret = 0;
  1505. int bank = 0;
  1506. int act_ps = 0;
  1507. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1508. w->name, event);
  1509. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1510. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1511. switch (event) {
  1512. case SND_SOC_DAPM_PRE_PMU:
  1513. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1514. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1515. wcd9378->rx_swr_dev->dev_num,
  1516. true);
  1517. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1518. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1519. if (wcd9378->update_wcd_event)
  1520. wcd9378->update_wcd_event(wcd9378->handle,
  1521. SLV_BOLERO_EVT_RX_MUTE,
  1522. (WCD_RX2 << 0x10));
  1523. } else {
  1524. if (wcd9378->update_wcd_event)
  1525. wcd9378->update_wcd_event(wcd9378->handle,
  1526. SLV_BOLERO_EVT_RX_MUTE,
  1527. (WCD_RX3 << 0x10));
  1528. }
  1529. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1530. if (act_ps)
  1531. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1532. __func__, act_ps);
  1533. else
  1534. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1535. __func__, act_ps);
  1536. break;
  1537. case SND_SOC_DAPM_POST_PMD:
  1538. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1539. if (wcd9378->update_wcd_event)
  1540. wcd9378->update_wcd_event(wcd9378->handle,
  1541. SLV_BOLERO_EVT_RX_MUTE,
  1542. (WCD_RX2 << 0x10 | 0x1));
  1543. } else {
  1544. if (wcd9378->update_wcd_event)
  1545. wcd9378->update_wcd_event(wcd9378->handle,
  1546. SLV_BOLERO_EVT_RX_MUTE,
  1547. (WCD_RX3 << 0x10 | 0x1));
  1548. }
  1549. break;
  1550. };
  1551. return ret;
  1552. }
  1553. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1554. struct snd_kcontrol *kcontrol,
  1555. int event)
  1556. {
  1557. struct snd_soc_component *component =
  1558. snd_soc_dapm_to_component(w->dapm);
  1559. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1560. int ret = 0, bank = 0;
  1561. int act_ps = 0;
  1562. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1563. w->name, event);
  1564. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1565. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1566. switch (event) {
  1567. case SND_SOC_DAPM_PRE_PMU:
  1568. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1569. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1570. wcd9378->rx_swr_dev->dev_num,
  1571. true);
  1572. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1573. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1574. if (wcd9378->update_wcd_event)
  1575. wcd9378->update_wcd_event(wcd9378->handle,
  1576. SLV_BOLERO_EVT_RX_MUTE,
  1577. (WCD_RX1 << 0x10));
  1578. } else {
  1579. if (wcd9378->update_wcd_event)
  1580. wcd9378->update_wcd_event(wcd9378->handle,
  1581. SLV_BOLERO_EVT_RX_MUTE,
  1582. (WCD_RX3 << 0x10));
  1583. }
  1584. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1585. if (act_ps)
  1586. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1587. __func__, act_ps);
  1588. else
  1589. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1590. __func__, act_ps);
  1591. break;
  1592. case SND_SOC_DAPM_POST_PMD:
  1593. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1594. if (wcd9378->update_wcd_event)
  1595. wcd9378->update_wcd_event(wcd9378->handle,
  1596. SLV_BOLERO_EVT_RX_MUTE,
  1597. (WCD_RX1 << 0x10 | 0x1));
  1598. } else {
  1599. if (wcd9378->update_wcd_event)
  1600. wcd9378->update_wcd_event(wcd9378->handle,
  1601. SLV_BOLERO_EVT_RX_MUTE,
  1602. (WCD_RX3 << 0x10 | 0x1));
  1603. }
  1604. break;
  1605. };
  1606. return ret;
  1607. }
  1608. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1609. {
  1610. switch (hph_mode) {
  1611. case CLS_H_LOHIFI:
  1612. case CLS_AB_LOHIFI:
  1613. return PWR_LEVEL_LOHIFI_VAL;
  1614. case CLS_H_LP:
  1615. case CLS_AB_LP:
  1616. return PWR_LEVEL_LP_VAL;
  1617. case CLS_H_HIFI:
  1618. case CLS_AB_HIFI:
  1619. return PWR_LEVEL_HIFI_VAL;
  1620. case CLS_H_ULP:
  1621. case CLS_AB:
  1622. case CLS_H_NORMAL:
  1623. default:
  1624. return PWR_LEVEL_ULP_VAL;
  1625. }
  1626. return PWR_LEVEL_ULP_VAL;
  1627. }
  1628. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1629. {
  1630. struct wcd9378_priv *wcd9378 =
  1631. snd_soc_component_get_drvdata(component);
  1632. if ((!wcd9378->comp1_enable) &&
  1633. (!wcd9378->comp2_enable)) {
  1634. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1635. snd_soc_component_update_bits(component,
  1636. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1637. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1638. wcd9378->hph_gain >> 8);
  1639. snd_soc_component_update_bits(component,
  1640. WCD9378_FU42_CH_VOL_CH1,
  1641. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1642. wcd9378->hph_gain & 0x00ff);
  1643. snd_soc_component_update_bits(component,
  1644. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1645. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1646. wcd9378->hph_gain >> 8);
  1647. snd_soc_component_update_bits(component,
  1648. WCD9378_FU42_CH_VOL_CH2,
  1649. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1650. wcd9378->hph_gain & 0x00ff);
  1651. }
  1652. }
  1653. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1654. {
  1655. u16 clk_scale_reg = 0;
  1656. u8 clk_rst = 0x00, scale_rst = 0x00;
  1657. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1658. struct wcd9378_priv *wcd9378 = NULL;
  1659. struct swr_device *swr_dev = NULL;
  1660. wcd9378 = dev_get_drvdata(dev);
  1661. if (!wcd9378)
  1662. return -EINVAL;
  1663. if (path == RX_PATH) {
  1664. swr_dev = wcd9378->rx_swr_dev;
  1665. swr_base_clk = wcd9378->swr_base_clk;
  1666. swr_clk_scale = wcd9378->swr_clk_scale;
  1667. } else {
  1668. swr_dev = wcd9378->tx_swr_dev;
  1669. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1670. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1671. }
  1672. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1673. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1674. if (enable) {
  1675. swr_write(swr_dev, swr_dev->dev_num,
  1676. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1677. swr_write(swr_dev, swr_dev->dev_num,
  1678. clk_scale_reg, &swr_clk_scale);
  1679. } else {
  1680. swr_write(swr_dev, swr_dev->dev_num,
  1681. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1682. swr_write(swr_dev, swr_dev->dev_num,
  1683. clk_scale_reg, &scale_rst);
  1684. }
  1685. return 0;
  1686. }
  1687. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1688. struct snd_kcontrol *kcontrol, int event)
  1689. {
  1690. struct snd_soc_component *component =
  1691. snd_soc_dapm_to_component(w->dapm);
  1692. struct wcd9378_priv *wcd9378 =
  1693. snd_soc_component_get_drvdata(component);
  1694. int power_level, bank = 0;
  1695. int ret = 0;
  1696. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1697. u8 scp_commit_val = 0x2;
  1698. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1699. w->name, event);
  1700. switch (event) {
  1701. case SND_SOC_DAPM_PRE_PMU:
  1702. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true);
  1703. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1704. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1705. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1706. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1707. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1708. }
  1709. if ((wcd9378->hph_mode == CLS_AB) ||
  1710. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1711. (wcd9378->hph_mode == CLS_AB_LP) ||
  1712. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1713. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1714. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1715. /*GET HPH_MODE*/
  1716. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1717. /*SET HPH_MODE*/
  1718. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1719. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1720. /*TURN ON HPH SEQUENCER*/
  1721. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1722. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1723. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1724. wcd9378_hph_set_channel_volume(component);
  1725. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1726. /*PA delay is 22400us*/
  1727. usleep_range(22500, 22510);
  1728. else
  1729. /*COMP delay is 9400us*/
  1730. usleep_range(9500, 9510);
  1731. /*RX0 unmute*/
  1732. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1733. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1734. /*RX1 unmute*/
  1735. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1736. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1737. if (wcd9378->sys_usage == SYS_USAGE_10)
  1738. /*FU23 UNMUTE*/
  1739. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1740. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1741. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1742. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1743. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1744. wcd9378->rx_swr_dev->dev_num,
  1745. true);
  1746. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1747. break;
  1748. case SND_SOC_DAPM_POST_PMD:
  1749. /*RX0 mute*/
  1750. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1751. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1752. /*RX1 mute*/
  1753. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1754. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1755. /*TEAR DOWN HPH SEQUENCER*/
  1756. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1757. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1758. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1759. /*PA delay is 24250us*/
  1760. usleep_range(24300, 24310);
  1761. else
  1762. /*COMP delay is 11250us*/
  1763. usleep_range(11300, 11310);
  1764. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, false);
  1765. break;
  1766. default:
  1767. break;
  1768. };
  1769. return ret;
  1770. }
  1771. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1772. struct snd_kcontrol *kcontrol,
  1773. int event)
  1774. {
  1775. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1776. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1777. int ear_rx2 = 0;
  1778. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1779. w->name, event);
  1780. ear_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1781. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1782. switch (event) {
  1783. case SND_SOC_DAPM_PRE_PMU:
  1784. /*SHORT_PROT_EN ENABLE*/
  1785. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1786. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  1787. if (!ear_rx2) {
  1788. /*RX0 ENABLE*/
  1789. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1790. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1791. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, true);
  1792. if (wcd9378->comp1_enable) {
  1793. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1794. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1795. wcd9378_rx_connect_port(component, COMP_L, true);
  1796. }
  1797. wcd9378_rx_connect_port(component, HPH_L, true);
  1798. } else {
  1799. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, true);
  1800. /*FORCE CLASS_AB EN*/
  1801. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1802. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1803. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1804. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1805. if (wcd9378->rx2_clk_mode)
  1806. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1807. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1808. wcd9378_rx_connect_port(component, LO, true);
  1809. }
  1810. break;
  1811. case SND_SOC_DAPM_POST_PMD:
  1812. /*SHORT_PROT_EN DISABLE*/
  1813. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1814. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x00);
  1815. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1816. /*RX0 DISABLE*/
  1817. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1818. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1819. wcd9378_rx_connect_port(component, HPH_L, false);
  1820. if (wcd9378->comp1_enable) {
  1821. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1822. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1823. wcd9378_rx_connect_port(component, COMP_L, false);
  1824. }
  1825. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, false);
  1826. } else {
  1827. wcd9378_rx_connect_port(component, LO, false);
  1828. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, false);
  1829. }
  1830. break;
  1831. };
  1832. return 0;
  1833. }
  1834. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1835. struct snd_kcontrol *kcontrol,
  1836. int event)
  1837. {
  1838. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1839. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1840. int aux_rx2 = 0;
  1841. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1842. w->name, event);
  1843. aux_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1844. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1845. switch (event) {
  1846. case SND_SOC_DAPM_PRE_PMU:
  1847. /*AUXPA SHORT PROT ENABLE*/
  1848. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1849. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x40);
  1850. if (!aux_rx2) {
  1851. /*RX1 ENABLE*/
  1852. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1853. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1854. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, true);
  1855. wcd9378_rx_connect_port(component, HPH_R, true);
  1856. } else {
  1857. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, true);
  1858. if (wcd9378->rx2_clk_mode)
  1859. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1860. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1861. wcd9378_rx_connect_port(component, LO, true);
  1862. }
  1863. break;
  1864. case SND_SOC_DAPM_POST_PMD:
  1865. /*AUXPA SHORT PROT DISABLE*/
  1866. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1867. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x00);
  1868. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1869. wcd9378_rx_connect_port(component, HPH_R, false);
  1870. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, false);
  1871. } else {
  1872. wcd9378_rx_connect_port(component, LO, false);
  1873. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, false);
  1874. }
  1875. break;
  1876. };
  1877. return 0;
  1878. }
  1879. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1880. struct snd_kcontrol *kcontrol, int event)
  1881. {
  1882. struct snd_soc_component *component =
  1883. snd_soc_dapm_to_component(w->dapm);
  1884. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1885. w->name, event);
  1886. switch (event) {
  1887. case SND_SOC_DAPM_PRE_PMU:
  1888. /*TURN ON AMP SEQUENCER*/
  1889. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1890. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1891. /*default delay 8550us*/
  1892. usleep_range(8600, 8610);
  1893. /*FU23 UNMUTE*/
  1894. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1895. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1896. break;
  1897. case SND_SOC_DAPM_POST_PMD:
  1898. /*FU23 MUTE*/
  1899. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1900. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1901. /*TEAR DOWN AMP SEQUENCER*/
  1902. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1903. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1904. /*default delay 1530us*/
  1905. usleep_range(15400, 15410);
  1906. break;
  1907. default:
  1908. break;
  1909. };
  1910. return 0;
  1911. }
  1912. int wcd9378_micbias_control(struct snd_soc_component *component,
  1913. int micb_num, int req, bool is_dapm)
  1914. {
  1915. struct wcd9378_priv *wcd9378 =
  1916. snd_soc_component_get_drvdata(component);
  1917. struct wcd9378_pdata *pdata =
  1918. dev_get_platdata(wcd9378->dev);
  1919. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1920. int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1921. int pre_off_event = 0, post_off_event = 0;
  1922. int post_on_event = 0, post_dapm_off = 0;
  1923. int post_dapm_on = 0;
  1924. int pull_up_mask = 0, pull_up_en = 0;
  1925. int micb_index = 0, ret = 0;
  1926. switch (micb_num) {
  1927. case MIC_BIAS_1:
  1928. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1929. pull_up_en = 0x01;
  1930. micb_usage = WCD9378_IT11_MICB;
  1931. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1932. micb_usage_val = mb->micb1_usage_val;
  1933. break;
  1934. case MIC_BIAS_2:
  1935. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1936. pull_up_en = 0x02;
  1937. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1938. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1939. micb_usage_val = mb->micb2_usage_val;
  1940. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1941. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1942. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1943. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1944. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1945. break;
  1946. case MIC_BIAS_3:
  1947. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1948. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1949. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1950. pull_up_en = 0x04;
  1951. micb_usage_val = mb->micb3_usage_val;
  1952. break;
  1953. default:
  1954. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1955. __func__, micb_num);
  1956. return -EINVAL;
  1957. }
  1958. mutex_lock(&wcd9378->micb_lock);
  1959. micb_index = micb_num - 1;
  1960. switch (req) {
  1961. case MICB_PULLUP_ENABLE:
  1962. wcd9378->pullup_ref[micb_index]++;
  1963. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1964. (wcd9378->micb_ref[micb_index] == 0)) {
  1965. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1966. pull_up_mask, pull_up_en);
  1967. snd_soc_component_update_bits(component,
  1968. micb_usage, micb_mask, 0x03);
  1969. if (micb_num == MIC_BIAS_2) {
  1970. dev_dbg(component->dev, "%s: pull up sj micbias\n",
  1971. __func__);
  1972. snd_soc_component_update_bits(component,
  1973. WCD9378_IT31_MICB,
  1974. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1975. 0x03);
  1976. wcd9378->curr_micbias2 = 1800;
  1977. }
  1978. }
  1979. break;
  1980. case MICB_PULLUP_DISABLE:
  1981. if (wcd9378->pullup_ref[micb_index] > 0)
  1982. wcd9378->pullup_ref[micb_index]--;
  1983. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1984. (wcd9378->micb_ref[micb_index] == 0)) {
  1985. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1986. if (micb_num == MIC_BIAS_2) {
  1987. dev_dbg(component->dev, "%s: pull down sj micbias\n",
  1988. __func__);
  1989. snd_soc_component_update_bits(component,
  1990. WCD9378_IT31_MICB,
  1991. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1992. 0x01);
  1993. wcd9378->curr_micbias2 = 0;
  1994. }
  1995. }
  1996. break;
  1997. case MICB_ENABLE:
  1998. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1999. __func__);
  2000. if (!wcd9378->dev_up) {
  2001. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2002. __func__, req);
  2003. ret = -ENODEV;
  2004. goto done;
  2005. }
  2006. wcd9378->micb_ref[micb_index]++;
  2007. if (wcd9378->micb_ref[micb_index] == 1) {
  2008. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  2009. __func__, micb_usage, micb_usage_val);
  2010. snd_soc_component_update_bits(component,
  2011. micb_usage, micb_mask, micb_usage_val);
  2012. if (micb_num == MIC_BIAS_2) {
  2013. dev_dbg(component->dev, "%s: enable sj micbias\n",
  2014. __func__);
  2015. snd_soc_component_update_bits(component,
  2016. WCD9378_IT31_MICB,
  2017. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2018. micb_usage_val);
  2019. wcd9378->curr_micbias2 = 1800;
  2020. }
  2021. if (post_on_event)
  2022. blocking_notifier_call_chain(
  2023. &wcd9378->mbhc->notifier,
  2024. post_on_event,
  2025. &wcd9378->mbhc->wcd_mbhc);
  2026. }
  2027. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  2028. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2029. post_dapm_on,
  2030. &wcd9378->mbhc->wcd_mbhc);
  2031. break;
  2032. case MICB_DISABLE:
  2033. dev_dbg(component->dev, "%s: micbias disable enter\n",
  2034. __func__);
  2035. if (wcd9378->micb_ref[micb_index] > 0)
  2036. wcd9378->micb_ref[micb_index]--;
  2037. if ((wcd9378->micb_ref[micb_index] == 0) &&
  2038. (wcd9378->pullup_ref[micb_index] > 0)) {
  2039. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  2040. pull_up_mask, pull_up_en);
  2041. if (micb_num == MIC_BIAS_2)
  2042. wcd9378->curr_micbias2 = 1800;
  2043. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  2044. (wcd9378->pullup_ref[micb_index] == 0)) {
  2045. if (pre_off_event && wcd9378->mbhc)
  2046. blocking_notifier_call_chain(
  2047. &wcd9378->mbhc->notifier,
  2048. pre_off_event,
  2049. &wcd9378->mbhc->wcd_mbhc);
  2050. snd_soc_component_update_bits(component, micb_usage,
  2051. micb_mask, 0x00);
  2052. if (micb_num == MIC_BIAS_2) {
  2053. snd_soc_component_update_bits(component,
  2054. WCD9378_IT31_MICB,
  2055. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2056. 0x00);
  2057. wcd9378->curr_micbias2 = 0;
  2058. }
  2059. if (post_off_event && wcd9378->mbhc)
  2060. blocking_notifier_call_chain(
  2061. &wcd9378->mbhc->notifier,
  2062. post_off_event,
  2063. &wcd9378->mbhc->wcd_mbhc);
  2064. }
  2065. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  2066. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2067. post_dapm_off,
  2068. &wcd9378->mbhc->wcd_mbhc);
  2069. break;
  2070. default:
  2071. dev_err(component->dev, "%s: Invalid req event: %d\n",
  2072. __func__, req);
  2073. return -EINVAL;
  2074. }
  2075. dev_dbg(component->dev,
  2076. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2077. __func__, micb_num, wcd9378->micb_ref[micb_index],
  2078. wcd9378->pullup_ref[micb_index]);
  2079. done:
  2080. mutex_unlock(&wcd9378->micb_lock);
  2081. return ret;
  2082. }
  2083. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  2084. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  2085. {
  2086. int ret = 0;
  2087. uint8_t devnum = 0;
  2088. int num_retry = NUM_ATTEMPTS;
  2089. do {
  2090. /* retry after 4ms */
  2091. usleep_range(4000, 4010);
  2092. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2093. } while (ret && --num_retry);
  2094. if (ret)
  2095. dev_err(&swr_dev->dev,
  2096. "%s get devnum %d for dev addr %llx failed\n",
  2097. __func__, devnum, swr_dev->addr);
  2098. swr_dev->dev_num = devnum;
  2099. return 0;
  2100. }
  2101. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2102. struct wcd_mbhc_config *mbhc_cfg)
  2103. {
  2104. if (mbhc_cfg->enable_usbc_analog) {
  2105. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  2106. & 0x20))
  2107. return true;
  2108. }
  2109. return false;
  2110. }
  2111. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  2112. struct notifier_block *nblock,
  2113. bool enable)
  2114. {
  2115. struct wcd9378_priv *wcd9378_priv = NULL;
  2116. if (component == NULL) {
  2117. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  2118. return -EINVAL;
  2119. }
  2120. wcd9378_priv = snd_soc_component_get_drvdata(component);
  2121. wcd9378_priv->notify_swr_dmic = enable;
  2122. if (enable)
  2123. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  2124. nblock);
  2125. else
  2126. return blocking_notifier_chain_unregister(
  2127. &wcd9378_priv->notifier, nblock);
  2128. }
  2129. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  2130. static int wcd9378_event_notify(struct notifier_block *block,
  2131. unsigned long val,
  2132. void *data)
  2133. {
  2134. u16 event = (val & 0xffff);
  2135. int ret = 0;
  2136. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  2137. struct snd_soc_component *component = wcd9378->component;
  2138. struct wcd_mbhc *mbhc;
  2139. int rx_clk_type;
  2140. switch (event) {
  2141. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2142. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  2143. snd_soc_component_update_bits(component,
  2144. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  2145. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  2146. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  2147. }
  2148. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  2149. snd_soc_component_update_bits(component,
  2150. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  2151. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  2152. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  2153. }
  2154. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  2155. snd_soc_component_update_bits(component,
  2156. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  2157. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  2158. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  2159. }
  2160. break;
  2161. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2162. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  2163. 0xC0, 0x00);
  2164. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  2165. 0x80, 0x00);
  2166. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  2167. 0x80, 0x00);
  2168. break;
  2169. case BOLERO_SLV_EVT_SSR_DOWN:
  2170. wcd9378->dev_up = false;
  2171. if (wcd9378->notify_swr_dmic)
  2172. blocking_notifier_call_chain(&wcd9378->notifier,
  2173. WCD9378_EVT_SSR_DOWN,
  2174. NULL);
  2175. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  2176. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2177. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  2178. mbhc->mbhc_cfg);
  2179. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  2180. wcd9378_reset_low(wcd9378->dev);
  2181. break;
  2182. case BOLERO_SLV_EVT_SSR_UP:
  2183. wcd9378_reset(wcd9378->dev);
  2184. /* allow reset to take effect */
  2185. usleep_range(10000, 10010);
  2186. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  2187. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  2188. wcd9378->tx_swr_dev->scp1_val = 0;
  2189. wcd9378->tx_swr_dev->scp2_val = 0;
  2190. wcd9378->rx_swr_dev->scp1_val = 0;
  2191. wcd9378->rx_swr_dev->scp2_val = 0;
  2192. wcd9378_init_reg(component);
  2193. regcache_mark_dirty(wcd9378->regmap);
  2194. regcache_sync(wcd9378->regmap);
  2195. /* Initialize MBHC module */
  2196. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2197. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2198. if (ret) {
  2199. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2200. __func__);
  2201. } else {
  2202. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2203. }
  2204. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2205. wcd9378->dev_up = true;
  2206. if (wcd9378->notify_swr_dmic)
  2207. blocking_notifier_call_chain(&wcd9378->notifier,
  2208. WCD9378_EVT_SSR_UP,
  2209. NULL);
  2210. if (wcd9378->usbc_hs_status)
  2211. mdelay(500);
  2212. break;
  2213. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2214. snd_soc_component_update_bits(component,
  2215. WCD9378_TOP_CLK_CFG, 0x06,
  2216. ((val >> 0x10) << 0x01));
  2217. rx_clk_type = (val >> 0x10);
  2218. switch (rx_clk_type) {
  2219. case RX_CLK_12P288MHZ:
  2220. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2221. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2222. break;
  2223. case RX_CLK_11P2896MHZ:
  2224. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2225. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2226. break;
  2227. default:
  2228. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2229. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2230. break;
  2231. }
  2232. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2233. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2234. break;
  2235. default:
  2236. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2237. break;
  2238. }
  2239. return 0;
  2240. }
  2241. static int wcd9378_wakeup(void *handle, bool enable)
  2242. {
  2243. struct wcd9378_priv *priv;
  2244. int ret = 0;
  2245. if (!handle) {
  2246. pr_err("%s: NULL handle\n", __func__);
  2247. return -EINVAL;
  2248. }
  2249. priv = (struct wcd9378_priv *)handle;
  2250. if (!priv->tx_swr_dev) {
  2251. pr_err("%s: tx swr dev is NULL\n", __func__);
  2252. return -EINVAL;
  2253. }
  2254. mutex_lock(&priv->wakeup_lock);
  2255. if (enable)
  2256. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2257. else
  2258. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2259. mutex_unlock(&priv->wakeup_lock);
  2260. return ret;
  2261. }
  2262. static inline int wcd9378_tx_path_get(const char *wname,
  2263. unsigned int *path_num)
  2264. {
  2265. int ret = 0;
  2266. char *widget_name = NULL;
  2267. char *w_name = NULL;
  2268. char *path_num_char = NULL;
  2269. char *path_name = NULL;
  2270. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2271. if (!widget_name)
  2272. return -EINVAL;
  2273. w_name = widget_name;
  2274. path_name = strsep(&widget_name, " ");
  2275. if (!path_name) {
  2276. pr_err("%s: Invalid widget name = %s\n",
  2277. __func__, widget_name);
  2278. ret = -EINVAL;
  2279. goto err;
  2280. }
  2281. path_num_char = strpbrk(path_name, "0123");
  2282. if (!path_num_char) {
  2283. pr_err("%s: tx path index not found\n",
  2284. __func__);
  2285. ret = -EINVAL;
  2286. goto err;
  2287. }
  2288. ret = kstrtouint(path_num_char, 10, path_num);
  2289. if (ret < 0)
  2290. pr_err("%s: Invalid tx path = %s\n",
  2291. __func__, w_name);
  2292. err:
  2293. kfree(w_name);
  2294. return ret;
  2295. }
  2296. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2297. struct snd_ctl_elem_value *ucontrol)
  2298. {
  2299. struct snd_soc_component *component =
  2300. snd_soc_kcontrol_component(kcontrol);
  2301. struct wcd9378_priv *wcd9378 = NULL;
  2302. int ret = 0;
  2303. unsigned int path = 0;
  2304. if (!component)
  2305. return -EINVAL;
  2306. wcd9378 = snd_soc_component_get_drvdata(component);
  2307. if (!wcd9378)
  2308. return -EINVAL;
  2309. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2310. if (ret < 0)
  2311. return ret;
  2312. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2313. return 0;
  2314. }
  2315. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2316. struct snd_ctl_elem_value *ucontrol)
  2317. {
  2318. struct snd_soc_component *component =
  2319. snd_soc_kcontrol_component(kcontrol);
  2320. struct wcd9378_priv *wcd9378 = NULL;
  2321. u32 mode_val;
  2322. unsigned int path = 0;
  2323. int ret = 0;
  2324. if (!component)
  2325. return -EINVAL;
  2326. wcd9378 = snd_soc_component_get_drvdata(component);
  2327. if (!wcd9378)
  2328. return -EINVAL;
  2329. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2330. if (ret)
  2331. return ret;
  2332. mode_val = ucontrol->value.enumerated.item[0];
  2333. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2334. wcd9378->tx_mode[path] = mode_val;
  2335. return 0;
  2336. }
  2337. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2338. struct snd_ctl_elem_value *ucontrol)
  2339. {
  2340. struct snd_soc_component *component =
  2341. snd_soc_kcontrol_component(kcontrol);
  2342. u32 loopback_mode = 0;
  2343. if (!component)
  2344. return -EINVAL;
  2345. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2346. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2347. ucontrol->value.integer.value[0] = loopback_mode;
  2348. return 0;
  2349. }
  2350. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2351. struct snd_ctl_elem_value *ucontrol)
  2352. {
  2353. struct snd_soc_component *component =
  2354. snd_soc_kcontrol_component(kcontrol);
  2355. u32 loopback_mode = 0;
  2356. if (!component)
  2357. return -EINVAL;
  2358. loopback_mode = ucontrol->value.enumerated.item[0];
  2359. snd_soc_component_update_bits(component,
  2360. WCD9378_LOOP_BACK_MODE,
  2361. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2362. loopback_mode);
  2363. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2364. __func__, loopback_mode);
  2365. return 0;
  2366. }
  2367. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2368. struct snd_ctl_elem_value *ucontrol)
  2369. {
  2370. struct snd_soc_component *component =
  2371. snd_soc_kcontrol_component(kcontrol);
  2372. u32 aux_dsm_in = 0;
  2373. if (!component)
  2374. return -EINVAL;
  2375. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2376. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2377. ucontrol->value.integer.value[0] = aux_dsm_in;
  2378. return 0;
  2379. }
  2380. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2381. struct snd_ctl_elem_value *ucontrol)
  2382. {
  2383. struct snd_soc_component *component =
  2384. snd_soc_kcontrol_component(kcontrol);
  2385. u32 aux_dsm_in = 0;
  2386. if (!component)
  2387. return -EINVAL;
  2388. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2389. snd_soc_component_update_bits(component,
  2390. WCD9378_LB_IN_SEL_CTL,
  2391. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2392. aux_dsm_in);
  2393. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2394. __func__, aux_dsm_in);
  2395. return 0;
  2396. }
  2397. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2398. struct snd_ctl_elem_value *ucontrol)
  2399. {
  2400. struct snd_soc_component *component =
  2401. snd_soc_kcontrol_component(kcontrol);
  2402. u32 hph_dsm_in = 0;
  2403. if (!component)
  2404. return -EINVAL;
  2405. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2406. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2407. ucontrol->value.integer.value[0] = hph_dsm_in;
  2408. return 0;
  2409. }
  2410. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2411. struct snd_ctl_elem_value *ucontrol)
  2412. {
  2413. struct snd_soc_component *component =
  2414. snd_soc_kcontrol_component(kcontrol);
  2415. u32 hph_dsm_in = 0;
  2416. if (!component)
  2417. return -EINVAL;
  2418. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2419. snd_soc_component_update_bits(component,
  2420. WCD9378_LB_IN_SEL_CTL,
  2421. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2422. hph_dsm_in);
  2423. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2424. __func__, hph_dsm_in);
  2425. return 0;
  2426. }
  2427. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2428. struct snd_ctl_elem_value *ucontrol)
  2429. {
  2430. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2431. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2432. u16 offset = ucontrol->value.enumerated.item[0];
  2433. u32 temp = 0;
  2434. temp = 0x00 - offset * 0x180;
  2435. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2436. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2437. return 0;
  2438. }
  2439. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2440. struct snd_ctl_elem_value *ucontrol)
  2441. {
  2442. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2443. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2444. u32 temp = 0;
  2445. u16 offset = 0;
  2446. temp = 0 - wcd9378->hph_gain;
  2447. offset = (u16)(temp & 0xffff);
  2448. offset /= 0x180;
  2449. ucontrol->value.enumerated.item[0] = offset;
  2450. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2451. return 0;
  2452. }
  2453. static int wcd9378_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2454. struct snd_ctl_elem_value *ucontrol)
  2455. {
  2456. struct snd_soc_component *component =
  2457. snd_soc_kcontrol_component(kcontrol);
  2458. int ear_gain = 0;
  2459. if (component == NULL)
  2460. return -EINVAL;
  2461. ear_gain =
  2462. snd_soc_component_read(component, WCD9378_ANA_EAR_COMPANDER_CTL) &
  2463. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK;
  2464. ucontrol->value.enumerated.item[0] = ear_gain;
  2465. dev_dbg(component->dev, "%s: get ear_gain val: 0x%x\n",
  2466. __func__, ear_gain);
  2467. return 0;
  2468. }
  2469. static int wcd9378_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2470. struct snd_ctl_elem_value *ucontrol)
  2471. {
  2472. struct snd_soc_component *component =
  2473. snd_soc_kcontrol_component(kcontrol);
  2474. int ear_gain = 0;
  2475. if (component == NULL)
  2476. return -EINVAL;
  2477. if (ucontrol->value.integer.value[0] < 0 ||
  2478. ucontrol->value.integer.value[0] > 0x10) {
  2479. dev_err(component->dev, "%s: Unsupported gain val %ld\n",
  2480. __func__, ucontrol->value.integer.value[0]);
  2481. return -EINVAL;
  2482. }
  2483. ear_gain = ucontrol->value.integer.value[0];
  2484. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2485. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2486. ear_gain);
  2487. dev_dbg(component->dev, "%s: set ear_gain val: 0x%x\n",
  2488. __func__, ear_gain);
  2489. return 0;
  2490. }
  2491. static int wcd9378_aux_pa_gain_get(struct snd_kcontrol *kcontrol,
  2492. struct snd_ctl_elem_value *ucontrol)
  2493. {
  2494. struct snd_soc_component *component =
  2495. snd_soc_kcontrol_component(kcontrol);
  2496. int aux_gain = 0;
  2497. if (component == NULL)
  2498. return -EINVAL;
  2499. aux_gain = snd_soc_component_read(component, WCD9378_AUX_INT_MISC) &
  2500. WCD9378_AUX_INT_MISC_PA_GAIN_MASK;
  2501. ucontrol->value.enumerated.item[0] = aux_gain;
  2502. dev_dbg(component->dev, "%s: get aux_gain val: 0x%x\n",
  2503. __func__, aux_gain);
  2504. return 0;
  2505. }
  2506. static int wcd9378_aux_pa_gain_put(struct snd_kcontrol *kcontrol,
  2507. struct snd_ctl_elem_value *ucontrol)
  2508. {
  2509. struct snd_soc_component *component =
  2510. snd_soc_kcontrol_component(kcontrol);
  2511. int aux_gain = 0;
  2512. if (component == NULL)
  2513. return -EINVAL;
  2514. if (ucontrol->value.integer.value[0] < 0 ||
  2515. ucontrol->value.integer.value[0] > 0x8) {
  2516. dev_err(component->dev, "%s: Unsupported gain val %ld\n",
  2517. __func__, ucontrol->value.integer.value[0]);
  2518. return -EINVAL;
  2519. }
  2520. aux_gain = ucontrol->value.integer.value[0];
  2521. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2522. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2523. aux_gain);
  2524. dev_dbg(component->dev, "%s: set aux_gain val: 0x%x\n",
  2525. __func__, aux_gain);
  2526. return 0;
  2527. }
  2528. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2529. struct snd_ctl_elem_value *ucontrol)
  2530. {
  2531. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2532. struct wcd9378_priv *wcd9378 =
  2533. snd_soc_component_get_drvdata(component);
  2534. if (ucontrol->value.enumerated.item[0])
  2535. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2536. else
  2537. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2538. return 1;
  2539. }
  2540. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2541. struct snd_ctl_elem_value *ucontrol)
  2542. {
  2543. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2544. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2545. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2546. return 0;
  2547. }
  2548. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2549. struct snd_ctl_elem_value *ucontrol)
  2550. {
  2551. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2552. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2553. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2554. return 0;
  2555. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2556. return 1;
  2557. }
  2558. /* wcd9378_codec_get_dev_num - returns swr device number
  2559. * @component: Codec instance
  2560. *
  2561. * Return: swr device number on success or negative error
  2562. * code on failure.
  2563. */
  2564. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2565. {
  2566. struct wcd9378_priv *wcd9378;
  2567. if (!component)
  2568. return -EINVAL;
  2569. wcd9378 = snd_soc_component_get_drvdata(component);
  2570. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2571. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2572. return -EINVAL;
  2573. }
  2574. return wcd9378->rx_swr_dev->dev_num;
  2575. }
  2576. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2577. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2578. struct snd_ctl_elem_value *ucontrol)
  2579. {
  2580. struct snd_soc_component *component =
  2581. snd_soc_kcontrol_component(kcontrol);
  2582. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2583. bool hphr;
  2584. struct soc_multi_mixer_control *mc;
  2585. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2586. hphr = mc->shift;
  2587. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2588. wcd9378->comp1_enable;
  2589. return 0;
  2590. }
  2591. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2592. struct snd_ctl_elem_value *ucontrol)
  2593. {
  2594. struct snd_soc_component *component =
  2595. snd_soc_kcontrol_component(kcontrol);
  2596. struct wcd9378_priv *wcd9378 =
  2597. snd_soc_component_get_drvdata(component);
  2598. int value = ucontrol->value.integer.value[0];
  2599. bool hphr;
  2600. struct soc_multi_mixer_control *mc;
  2601. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2602. hphr = mc->shift;
  2603. if (hphr)
  2604. wcd9378->comp2_enable = value;
  2605. else
  2606. wcd9378->comp1_enable = value;
  2607. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2608. return 0;
  2609. }
  2610. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2611. struct snd_kcontrol *kcontrol,
  2612. int event)
  2613. {
  2614. struct snd_soc_component *component =
  2615. snd_soc_dapm_to_component(w->dapm);
  2616. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2617. struct wcd9378_pdata *pdata = NULL;
  2618. int ret = 0;
  2619. pdata = dev_get_platdata(wcd9378->dev);
  2620. if (!pdata) {
  2621. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2622. return -EINVAL;
  2623. }
  2624. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2625. wcd9378->supplies,
  2626. pdata->regulator,
  2627. pdata->num_supplies,
  2628. "cdc-vdd-buck"))
  2629. return 0;
  2630. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2631. w->name, event);
  2632. switch (event) {
  2633. case SND_SOC_DAPM_PRE_PMU:
  2634. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2635. dev_dbg(component->dev,
  2636. "%s: buck already in enabled state\n",
  2637. __func__);
  2638. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2639. return 0;
  2640. }
  2641. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2642. wcd9378->supplies,
  2643. pdata->regulator,
  2644. pdata->num_supplies,
  2645. "cdc-vdd-buck");
  2646. if (ret == -EINVAL) {
  2647. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2648. __func__);
  2649. return ret;
  2650. }
  2651. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2652. /*
  2653. * 200us sleep is required after LDO is enabled as per
  2654. * HW requirement
  2655. */
  2656. usleep_range(200, 250);
  2657. break;
  2658. case SND_SOC_DAPM_POST_PMD:
  2659. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2660. break;
  2661. }
  2662. return 0;
  2663. }
  2664. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2665. {
  2666. u8 ch_type = 0;
  2667. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2668. ch_type = ADC1;
  2669. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2670. ch_type = ADC2;
  2671. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2672. ch_type = ADC3;
  2673. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2674. ch_type = ADC4;
  2675. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2676. ch_type = DMIC0;
  2677. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2678. ch_type = DMIC1;
  2679. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2680. ch_type = MBHC;
  2681. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2682. ch_type = DMIC2;
  2683. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2684. ch_type = DMIC3;
  2685. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2686. ch_type = DMIC4;
  2687. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2688. ch_type = DMIC5;
  2689. else
  2690. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2691. if (ch_type)
  2692. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2693. else
  2694. *ch_idx = -EINVAL;
  2695. }
  2696. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2697. struct snd_ctl_elem_value *ucontrol)
  2698. {
  2699. struct snd_soc_component *component =
  2700. snd_soc_kcontrol_component(kcontrol);
  2701. struct wcd9378_priv *wcd9378 = NULL;
  2702. int slave_ch_idx = -EINVAL;
  2703. if (component == NULL)
  2704. return -EINVAL;
  2705. wcd9378 = snd_soc_component_get_drvdata(component);
  2706. if (wcd9378 == NULL)
  2707. return -EINVAL;
  2708. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2709. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2710. return -EINVAL;
  2711. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2712. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2713. return 0;
  2714. }
  2715. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2716. struct snd_ctl_elem_value *ucontrol)
  2717. {
  2718. struct snd_soc_component *component =
  2719. snd_soc_kcontrol_component(kcontrol);
  2720. struct wcd9378_priv *wcd9378 = NULL;
  2721. int slave_ch_idx = -EINVAL, idx = 0;
  2722. if (component == NULL)
  2723. return -EINVAL;
  2724. wcd9378 = snd_soc_component_get_drvdata(component);
  2725. if (wcd9378 == NULL)
  2726. return -EINVAL;
  2727. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2728. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2729. return -EINVAL;
  2730. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2731. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2732. __func__, ucontrol->value.enumerated.item[0]);
  2733. idx = ucontrol->value.enumerated.item[0];
  2734. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2735. return -EINVAL;
  2736. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2737. return 0;
  2738. }
  2739. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2740. struct snd_ctl_elem_value *ucontrol)
  2741. {
  2742. struct snd_soc_component *component =
  2743. snd_soc_kcontrol_component(kcontrol);
  2744. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2745. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2746. return 0;
  2747. }
  2748. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2749. struct snd_ctl_elem_value *ucontrol)
  2750. {
  2751. struct snd_soc_component *component =
  2752. snd_soc_kcontrol_component(kcontrol);
  2753. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2754. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2755. return 0;
  2756. }
  2757. static const char * const loopback_mode_text[] = {
  2758. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2759. };
  2760. static const struct soc_enum loopback_mode_enum =
  2761. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2762. loopback_mode_text);
  2763. static const char * const aux_dsm_text[] = {
  2764. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2765. };
  2766. static const struct soc_enum aux_dsm_enum =
  2767. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2768. aux_dsm_text);
  2769. static const char * const hph_dsm_text[] = {
  2770. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2771. };
  2772. static const struct soc_enum hph_dsm_enum =
  2773. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2774. hph_dsm_text);
  2775. static const char * const tx_mode_mux_text[] = {
  2776. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2777. };
  2778. static const struct soc_enum tx_mode_mux_enum =
  2779. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2780. tx_mode_mux_text);
  2781. static const char * const rx2_mode_text[] = {
  2782. "HP", "NORMAL",
  2783. };
  2784. static const struct soc_enum rx2_mode_enum =
  2785. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2786. rx2_mode_text);
  2787. static const char * const rx_hph_mode_mux_text[] = {
  2788. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2789. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2790. };
  2791. static const struct soc_enum rx_hph_mode_mux_enum =
  2792. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2793. rx_hph_mode_mux_text);
  2794. static const char * const ear_pa_gain_text[] = {
  2795. "GAIN_6DB", "GAIN_4P5DB", "GAIN_3DB", "GAIN_1P5DB", "GAIN_0DB",
  2796. "GAIN_M1P5DB", "GAIN_M3DB", "GAIN_M4P5DB", "GAIN_M6DB",
  2797. "GAIN_M7P5DB", "GAIN_M9DB", "GAIN_M10P5DB", "GAIN_M12DB",
  2798. "GAIN_M13P5DB", "GAIN_M15DB", "GAIN_M16P5DB", "GAIN_M18DB",
  2799. };
  2800. static const struct soc_enum ear_pa_gain_enum =
  2801. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ear_pa_gain_text),
  2802. ear_pa_gain_text);
  2803. static const char * const aux_pa_gain_text[] = {
  2804. "GAIN_6DB", "GAIN_4P5DB", "GAIN_3DB", "GAIN_1P5DB", "GAIN_0DB",
  2805. "GAIN_M1P5DB", "GAIN_M3DB", "GAIN_M4P5DB", "GAIN_M6DB",
  2806. };
  2807. static const struct soc_enum aux_pa_gain_enum =
  2808. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_pa_gain_text),
  2809. aux_pa_gain_text);
  2810. const char * const tx_master_ch_text[] = {
  2811. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2812. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2813. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2814. "SWRM_PCM_IN",
  2815. };
  2816. const struct soc_enum tx_master_ch_enum =
  2817. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2818. tx_master_ch_text);
  2819. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2820. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2821. wcd9378_get_compander, wcd9378_set_compander),
  2822. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2823. wcd9378_get_compander, wcd9378_set_compander),
  2824. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2825. wcd9378_bcs_get, wcd9378_bcs_put),
  2826. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2827. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2828. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2829. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2830. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2831. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2832. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2833. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2834. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2835. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2836. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2837. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2838. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2839. NULL, wcd9378_rx2_mode_put),
  2840. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2841. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2842. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2843. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2844. SOC_ENUM_EXT("EAR_PA Gain", ear_pa_gain_enum,
  2845. wcd9378_ear_pa_gain_get, wcd9378_ear_pa_gain_put),
  2846. SOC_ENUM_EXT("AUX_PA Gain", aux_pa_gain_enum,
  2847. wcd9378_aux_pa_gain_get, wcd9378_aux_pa_gain_put),
  2848. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2849. analog_gain),
  2850. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2851. analog_gain),
  2852. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2853. analog_gain),
  2854. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2855. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2856. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2857. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2858. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2859. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2860. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2861. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2862. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2863. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2864. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2865. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2866. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2867. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2868. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2869. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2870. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2871. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2872. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2873. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2874. };
  2875. static const struct snd_kcontrol_new amic1_switch[] = {
  2876. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2877. };
  2878. static const struct snd_kcontrol_new amic2_switch[] = {
  2879. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2880. };
  2881. static const struct snd_kcontrol_new amic3_switch[] = {
  2882. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2883. };
  2884. static const struct snd_kcontrol_new amic4_switch[] = {
  2885. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2886. };
  2887. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2888. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2889. };
  2890. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2891. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2892. };
  2893. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2894. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2895. };
  2896. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2897. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2898. };
  2899. static const struct snd_kcontrol_new dmic1_switch[] = {
  2900. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2901. };
  2902. static const struct snd_kcontrol_new dmic2_switch[] = {
  2903. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2904. };
  2905. static const struct snd_kcontrol_new dmic3_switch[] = {
  2906. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2907. };
  2908. static const struct snd_kcontrol_new dmic4_switch[] = {
  2909. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2910. };
  2911. static const struct snd_kcontrol_new dmic5_switch[] = {
  2912. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2913. };
  2914. static const struct snd_kcontrol_new dmic6_switch[] = {
  2915. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2916. };
  2917. static const char * const adc1_mux_text[] = {
  2918. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2919. };
  2920. static const char * const adc2_mux_text[] = {
  2921. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2922. };
  2923. static const char * const adc3_mux_text[] = {
  2924. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4"
  2925. };
  2926. static const char * const ear_mux_text[] = {
  2927. "RX0", "RX2"
  2928. };
  2929. static const char * const aux_mux_text[] = {
  2930. "RX1", "RX2"
  2931. };
  2932. static const struct soc_enum adc1_enum =
  2933. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2934. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2935. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2936. static const struct soc_enum adc2_enum =
  2937. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2938. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2939. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2940. static const struct soc_enum adc3_enum =
  2941. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2942. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2943. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2944. static const struct soc_enum ear_enum =
  2945. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2946. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2947. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2948. static const struct soc_enum aux_enum =
  2949. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2950. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2951. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2952. static const struct snd_kcontrol_new tx_adc1_mux =
  2953. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2954. static const struct snd_kcontrol_new tx_adc2_mux =
  2955. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2956. static const struct snd_kcontrol_new tx_adc3_mux =
  2957. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2958. static const struct snd_kcontrol_new ear_mux =
  2959. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2960. static const struct snd_kcontrol_new aux_mux =
  2961. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2962. static const struct snd_kcontrol_new dac1_switch[] = {
  2963. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2964. };
  2965. static const struct snd_kcontrol_new dac2_switch[] = {
  2966. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2967. };
  2968. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2969. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2970. };
  2971. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2972. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2973. };
  2974. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2975. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2976. };
  2977. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2978. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2979. };
  2980. static const struct snd_kcontrol_new rx0_switch[] = {
  2981. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2982. };
  2983. static const struct snd_kcontrol_new rx1_switch[] = {
  2984. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2985. };
  2986. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2987. /*input widgets*/
  2988. SND_SOC_DAPM_INPUT("AMIC1"),
  2989. SND_SOC_DAPM_INPUT("AMIC2"),
  2990. SND_SOC_DAPM_INPUT("AMIC3"),
  2991. SND_SOC_DAPM_INPUT("AMIC4"),
  2992. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2993. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2994. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2995. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2996. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2997. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2998. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2999. /*tx widgets*/
  3000. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  3001. NULL, 0, wcd9378_tx_sequencer_enable,
  3002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3003. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  3004. NULL, 0, wcd9378_tx_sequencer_enable,
  3005. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3006. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  3007. NULL, 0, wcd9378_tx_sequencer_enable,
  3008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3009. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3010. &tx_adc1_mux),
  3011. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3012. &tx_adc2_mux),
  3013. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3014. &tx_adc3_mux),
  3015. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3016. wcd9378_codec_enable_dmic,
  3017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3018. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3019. wcd9378_codec_enable_dmic,
  3020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3021. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3022. wcd9378_codec_enable_dmic,
  3023. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3024. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3025. wcd9378_codec_enable_dmic,
  3026. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3027. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3028. wcd9378_codec_enable_dmic,
  3029. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3030. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3031. wcd9378_codec_enable_dmic,
  3032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3033. /*rx widgets*/
  3034. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3035. wcd9378_codec_hphl_dac_event,
  3036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3037. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3038. wcd9378_codec_hphr_dac_event,
  3039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3040. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  3041. wcd9378_hph_sequencer_enable,
  3042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3043. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3044. wcd9378_codec_enable_hphl_pa,
  3045. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3046. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3047. wcd9378_codec_enable_hphr_pa,
  3048. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3049. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  3050. NULL, 0, wcd9378_sa_sequencer_enable,
  3051. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3052. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  3053. wcd9378_codec_ear_dac_event,
  3054. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3055. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  3056. wcd9378_codec_aux_dac_event,
  3057. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3058. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3059. wcd9378_codec_enable_ear_pa,
  3060. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3061. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3062. wcd9378_codec_enable_aux_pa,
  3063. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3064. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3065. wcd9378_codec_enable_vdd_buck,
  3066. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3067. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3068. wcd9378_enable_clsh,
  3069. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3070. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3071. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3072. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3073. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3074. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3075. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3076. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3077. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3079. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3080. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3082. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3083. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3084. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3085. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3086. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3087. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3088. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3089. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3090. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3091. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3092. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3093. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3094. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3095. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3096. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3097. SND_SOC_DAPM_POST_PMD),
  3098. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3099. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3100. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3101. SND_SOC_DAPM_POST_PMD),
  3102. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3103. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3104. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3105. SND_SOC_DAPM_POST_PMD),
  3106. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3107. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3108. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3109. SND_SOC_DAPM_POST_PMD),
  3110. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3111. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3112. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3113. SND_SOC_DAPM_POST_PMD),
  3114. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3115. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3116. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3117. SND_SOC_DAPM_POST_PMD),
  3118. /* micbias widgets*/
  3119. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3120. wcd9378_codec_enable_micbias,
  3121. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3122. SND_SOC_DAPM_POST_PMD),
  3123. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3124. wcd9378_codec_enable_micbias,
  3125. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3126. SND_SOC_DAPM_POST_PMD),
  3127. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3128. wcd9378_codec_enable_micbias,
  3129. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3130. SND_SOC_DAPM_POST_PMD),
  3131. /* micbias pull up widgets*/
  3132. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3133. wcd9378_codec_enable_micbias_pullup,
  3134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3135. SND_SOC_DAPM_POST_PMD),
  3136. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3137. wcd9378_codec_enable_micbias_pullup,
  3138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3139. SND_SOC_DAPM_POST_PMD),
  3140. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3141. wcd9378_codec_enable_micbias_pullup,
  3142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3143. SND_SOC_DAPM_POST_PMD),
  3144. /* rx mixer widgets*/
  3145. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3146. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3147. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3148. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3149. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3150. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3151. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3152. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3153. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3154. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3155. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3156. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3157. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3158. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3159. /*output widgets tx*/
  3160. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3161. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3162. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3163. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3164. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3165. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3166. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3167. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3168. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3169. /*output widgets rx*/
  3170. SND_SOC_DAPM_OUTPUT("EAR"),
  3171. SND_SOC_DAPM_OUTPUT("AUX"),
  3172. SND_SOC_DAPM_OUTPUT("HPHL"),
  3173. SND_SOC_DAPM_OUTPUT("HPHR"),
  3174. };
  3175. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3176. /*ADC-1 (channel-1)*/
  3177. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3178. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3179. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3180. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3181. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3182. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3183. /*ADC-2 (channel-2)*/
  3184. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3185. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3186. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3187. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3188. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3189. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3190. /*ADC-3 (channel-3)*/
  3191. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3192. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3193. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3194. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3195. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3196. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3197. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3198. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3199. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3200. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3201. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3202. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3203. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3204. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3205. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3206. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3207. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3208. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3209. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3210. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3211. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3212. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3213. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3214. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3215. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3216. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3217. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3218. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3219. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3220. /*Headphone playback*/
  3221. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3222. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3223. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3224. {"RDAC1", NULL, "HPH SEQUENCER"},
  3225. {"HPHL_RDAC", "Switch", "RDAC1"},
  3226. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3227. {"HPHL", NULL, "HPHL PGA"},
  3228. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3229. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3230. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3231. {"RDAC2", NULL, "HPH SEQUENCER"},
  3232. {"HPHR_RDAC", "Switch", "RDAC2"},
  3233. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3234. {"HPHR", NULL, "HPHR PGA"},
  3235. /*Amplier playback*/
  3236. {"IN3_AUX", NULL, "VDD_BUCK"},
  3237. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3238. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3239. {"EAR_MUX", "RX2", "IN3_AUX"},
  3240. {"DAC1", "Switch", "EAR_MUX"},
  3241. {"EAR_RDAC", NULL, "DAC1"},
  3242. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3243. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3244. {"EAR PGA", NULL, "EAR_MIXER"},
  3245. {"EAR", NULL, "EAR PGA"},
  3246. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3247. {"AUX_MUX", "RX2", "IN3_AUX"},
  3248. {"DAC2", "Switch", "AUX_MUX"},
  3249. {"AUX_RDAC", NULL, "DAC2"},
  3250. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3251. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3252. {"AUX PGA", NULL, "AUX_MIXER"},
  3253. {"AUX", NULL, "AUX PGA"},
  3254. };
  3255. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3256. void *file_private_data,
  3257. struct file *file,
  3258. char __user *buf, size_t count,
  3259. loff_t pos)
  3260. {
  3261. struct wcd9378_priv *priv;
  3262. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3263. int len = 0;
  3264. priv = (struct wcd9378_priv *) entry->private_data;
  3265. if (!priv) {
  3266. pr_err("%s: wcd9378 priv is null\n", __func__);
  3267. return -EINVAL;
  3268. }
  3269. switch (priv->version) {
  3270. case WCD9378_VERSION_1_0:
  3271. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3272. break;
  3273. default:
  3274. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3275. }
  3276. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3277. }
  3278. static struct snd_info_entry_ops wcd9378_info_ops = {
  3279. .read = wcd9378_version_read,
  3280. };
  3281. /*
  3282. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3283. * @codec_root: The parent directory
  3284. * @component: component instance
  3285. *
  3286. * Creates wcd9378 module, version entry under the given
  3287. * parent directory.
  3288. *
  3289. * Return: 0 on success or negative error code on failure.
  3290. */
  3291. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3292. struct snd_soc_component *component)
  3293. {
  3294. struct snd_info_entry *version_entry;
  3295. struct wcd9378_priv *priv;
  3296. struct snd_soc_card *card;
  3297. if (!codec_root || !component)
  3298. return -EINVAL;
  3299. priv = snd_soc_component_get_drvdata(component);
  3300. if (priv->entry) {
  3301. dev_dbg(priv->dev,
  3302. "%s:wcd9378 module already created\n", __func__);
  3303. return 0;
  3304. }
  3305. card = component->card;
  3306. priv->entry = snd_info_create_module_entry(codec_root->module,
  3307. "wcd9378", codec_root);
  3308. if (!priv->entry) {
  3309. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3310. __func__);
  3311. return -ENOMEM;
  3312. }
  3313. priv->entry->mode = S_IFDIR | 0555;
  3314. if (snd_info_register(priv->entry) < 0) {
  3315. snd_info_free_entry(priv->entry);
  3316. return -ENOMEM;
  3317. }
  3318. version_entry = snd_info_create_card_entry(card->snd_card,
  3319. "version",
  3320. priv->entry);
  3321. if (!version_entry) {
  3322. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3323. __func__);
  3324. snd_info_free_entry(priv->entry);
  3325. return -ENOMEM;
  3326. }
  3327. version_entry->private_data = priv;
  3328. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3329. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3330. version_entry->c.ops = &wcd9378_info_ops;
  3331. if (snd_info_register(version_entry) < 0) {
  3332. snd_info_free_entry(version_entry);
  3333. snd_info_free_entry(priv->entry);
  3334. return -ENOMEM;
  3335. }
  3336. priv->version_entry = version_entry;
  3337. return 0;
  3338. }
  3339. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3340. static void wcd9378_class_load(struct snd_soc_component *component)
  3341. {
  3342. /*SMP AMP CLASS LOADING*/
  3343. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3344. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3345. usleep_range(20000, 20010);
  3346. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3347. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3348. /*SMP JACK CLASS LOADING*/
  3349. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3350. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3351. usleep_range(30000, 30010);
  3352. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3353. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3354. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3355. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3356. /*SMP MIC0 CLASS LOADING*/
  3357. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3358. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3359. usleep_range(5000, 5010);
  3360. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3361. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3362. /*SMP MIC1 CLASS LOADING*/
  3363. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3364. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3365. usleep_range(5000, 5010);
  3366. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3367. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3368. /*SMP MIC2 CLASS LOADING*/
  3369. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3370. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3371. usleep_range(5000, 5010);
  3372. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3373. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3374. }
  3375. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3376. {
  3377. struct wcd9378_priv *wcd9378 =
  3378. snd_soc_component_get_drvdata(component);
  3379. struct wcd9378_pdata *pdata =
  3380. dev_get_platdata(wcd9378->dev);
  3381. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3382. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3383. mb->micb1_mv, MIC_BIAS_1);
  3384. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3385. mb->micb2_mv, MIC_BIAS_2);
  3386. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3387. mb->micb3_mv, MIC_BIAS_3);
  3388. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3389. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3390. }
  3391. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3392. {
  3393. struct wcd9378_priv *wcd9378 =
  3394. snd_soc_component_get_drvdata(component);
  3395. if (snd_soc_component_read(component,
  3396. WCD9378_EFUSE_REG_29)
  3397. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3398. if (((snd_soc_component_read(component,
  3399. WCD9378_EFUSE_REG_29) &
  3400. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3401. return true;
  3402. else
  3403. return false;
  3404. } else {
  3405. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3406. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3407. return true;
  3408. else
  3409. return false;
  3410. }
  3411. return 0;
  3412. }
  3413. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3414. {
  3415. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3416. struct snd_soc_dapm_context *dapm =
  3417. snd_soc_component_get_dapm(component);
  3418. int ret = -EINVAL;
  3419. wcd9378 = snd_soc_component_get_drvdata(component);
  3420. if (!wcd9378)
  3421. return -EINVAL;
  3422. wcd9378->component = component;
  3423. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3424. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3425. ret = wcd9378_wcd_mode_check(component);
  3426. if (!ret) {
  3427. dev_err(component->dev, "wcd mode check failed\n");
  3428. ret = -EINVAL;
  3429. goto exit;
  3430. }
  3431. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3432. if (ret) {
  3433. pr_err("%s: mbhc initialization failed\n", __func__);
  3434. ret = -EINVAL;
  3435. goto exit;
  3436. }
  3437. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3438. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3439. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3440. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3441. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3442. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3443. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3444. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3445. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3446. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3447. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3448. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3449. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3450. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3451. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3452. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3453. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3454. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3455. snd_soc_dapm_sync(dapm);
  3456. wcd_cls_h_init(&wcd9378->clsh_info);
  3457. wcd9378_init_reg(component);
  3458. wcd9378_micb_value_convert(component);
  3459. wcd9378->version = WCD9378_VERSION_1_0;
  3460. /* Register event notifier */
  3461. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3462. if (wcd9378->register_notifier) {
  3463. ret = wcd9378->register_notifier(wcd9378->handle,
  3464. &wcd9378->nblock,
  3465. true);
  3466. if (ret) {
  3467. dev_err(component->dev,
  3468. "%s: Failed to register notifier %d\n",
  3469. __func__, ret);
  3470. return ret;
  3471. }
  3472. }
  3473. exit:
  3474. return ret;
  3475. }
  3476. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3477. {
  3478. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3479. if (!wcd9378) {
  3480. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3481. __func__);
  3482. return;
  3483. }
  3484. if (wcd9378->register_notifier)
  3485. wcd9378->register_notifier(wcd9378->handle,
  3486. &wcd9378->nblock,
  3487. false);
  3488. }
  3489. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3490. {
  3491. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3492. if (!wcd9378)
  3493. return 0;
  3494. wcd9378->dapm_bias_off = true;
  3495. return 0;
  3496. }
  3497. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3498. {
  3499. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3500. if (!wcd9378)
  3501. return 0;
  3502. wcd9378->dapm_bias_off = false;
  3503. return 0;
  3504. }
  3505. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3506. .name = WCD9378_DRV_NAME,
  3507. .probe = wcd9378_soc_codec_probe,
  3508. .remove = wcd9378_soc_codec_remove,
  3509. .controls = wcd9378_snd_controls,
  3510. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3511. .dapm_widgets = wcd9378_dapm_widgets,
  3512. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3513. .dapm_routes = wcd9378_audio_map,
  3514. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3515. .suspend = wcd9378_soc_codec_suspend,
  3516. .resume = wcd9378_soc_codec_resume,
  3517. };
  3518. static int wcd9378_reset(struct device *dev)
  3519. {
  3520. struct wcd9378_priv *wcd9378 = NULL;
  3521. int rc = 0;
  3522. int value = 0;
  3523. if (!dev)
  3524. return -ENODEV;
  3525. wcd9378 = dev_get_drvdata(dev);
  3526. if (!wcd9378)
  3527. return -EINVAL;
  3528. if (!wcd9378->rst_np) {
  3529. dev_err(dev, "%s: reset gpio device node not specified\n",
  3530. __func__);
  3531. return -EINVAL;
  3532. }
  3533. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3534. if (value > 0)
  3535. return 0;
  3536. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3537. if (rc) {
  3538. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3539. __func__);
  3540. return -EPROBE_DEFER;
  3541. }
  3542. /* 20us sleep required after pulling the reset gpio to LOW */
  3543. usleep_range(20, 30);
  3544. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3545. if (rc) {
  3546. dev_err(dev, "%s: wcd active state request fail!\n",
  3547. __func__);
  3548. return -EPROBE_DEFER;
  3549. }
  3550. /* 20us sleep required after pulling the reset gpio to HIGH */
  3551. usleep_range(20, 30);
  3552. return rc;
  3553. }
  3554. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3555. u32 *val)
  3556. {
  3557. int rc = 0;
  3558. rc = of_property_read_u32(dev->of_node, name, val);
  3559. if (rc)
  3560. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3561. __func__, name, dev->of_node->full_name);
  3562. return rc;
  3563. }
  3564. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3565. struct wcd9378_micbias_setting *mb)
  3566. {
  3567. u32 prop_val = 0;
  3568. int rc = 0;
  3569. /* MB1 */
  3570. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3571. NULL)) {
  3572. rc = wcd9378_read_of_property_u32(dev,
  3573. "qcom,cdc-micbias1-mv",
  3574. &prop_val);
  3575. if (!rc)
  3576. mb->micb1_mv = prop_val;
  3577. } else {
  3578. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3579. __func__);
  3580. }
  3581. /* MB2 */
  3582. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3583. NULL)) {
  3584. rc = wcd9378_read_of_property_u32(dev,
  3585. "qcom,cdc-micbias2-mv",
  3586. &prop_val);
  3587. if (!rc)
  3588. mb->micb2_mv = prop_val;
  3589. } else {
  3590. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3591. __func__);
  3592. }
  3593. /* MB3 */
  3594. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3595. NULL)) {
  3596. rc = wcd9378_read_of_property_u32(dev,
  3597. "qcom,cdc-micbias3-mv",
  3598. &prop_val);
  3599. if (!rc)
  3600. mb->micb3_mv = prop_val;
  3601. } else {
  3602. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3603. __func__);
  3604. }
  3605. }
  3606. static int wcd9378_reset_low(struct device *dev)
  3607. {
  3608. struct wcd9378_priv *wcd9378 = NULL;
  3609. int rc = 0;
  3610. if (!dev)
  3611. return -ENODEV;
  3612. wcd9378 = dev_get_drvdata(dev);
  3613. if (!wcd9378)
  3614. return -EINVAL;
  3615. if (!wcd9378->rst_np) {
  3616. dev_err(dev, "%s: reset gpio device node not specified\n",
  3617. __func__);
  3618. return -EINVAL;
  3619. }
  3620. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3621. if (rc) {
  3622. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3623. __func__);
  3624. return rc;
  3625. }
  3626. /* 20us sleep required after pulling the reset gpio to LOW */
  3627. usleep_range(20, 30);
  3628. return rc;
  3629. }
  3630. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3631. {
  3632. struct wcd9378_pdata *pdata = NULL;
  3633. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3634. GFP_KERNEL);
  3635. if (!pdata)
  3636. return NULL;
  3637. pdata->rst_np = of_parse_phandle(dev->of_node,
  3638. "qcom,wcd-rst-gpio-node", 0);
  3639. if (!pdata->rst_np) {
  3640. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3641. __func__, "qcom,wcd-rst-gpio-node",
  3642. dev->of_node->full_name);
  3643. return NULL;
  3644. }
  3645. /* Parse power supplies */
  3646. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3647. &pdata->num_supplies);
  3648. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3649. dev_err(dev, "%s: no power supplies defined for codec\n",
  3650. __func__);
  3651. return NULL;
  3652. }
  3653. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3654. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3655. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3656. return pdata;
  3657. }
  3658. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3659. {
  3660. .name = "wcd9378_cdc",
  3661. .playback = {
  3662. .stream_name = "WCD9378_AIF Playback",
  3663. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3664. .formats = WCD9378_FORMATS,
  3665. .rate_max = 384000,
  3666. .rate_min = 8000,
  3667. .channels_min = 1,
  3668. .channels_max = 4,
  3669. },
  3670. .capture = {
  3671. .stream_name = "WCD9378_AIF Capture",
  3672. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3673. .formats = WCD9378_FORMATS,
  3674. .rate_max = 384000,
  3675. .rate_min = 8000,
  3676. .channels_min = 1,
  3677. .channels_max = 4,
  3678. },
  3679. },
  3680. };
  3681. static int wcd9378_bind(struct device *dev)
  3682. {
  3683. int ret = 0;
  3684. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3685. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3686. /*
  3687. * Add 5msec delay to provide sufficient time for
  3688. * soundwire auto enumeration of slave devices as
  3689. * per HW requirement.
  3690. */
  3691. usleep_range(5000, 5010);
  3692. ret = component_bind_all(dev, wcd9378);
  3693. if (ret) {
  3694. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3695. __func__, ret);
  3696. return ret;
  3697. }
  3698. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3699. if (!wcd9378->rx_swr_dev) {
  3700. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3701. __func__);
  3702. ret = -ENODEV;
  3703. goto err;
  3704. }
  3705. wcd9378->rx_swr_dev->paging_support = true;
  3706. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3707. if (!wcd9378->tx_swr_dev) {
  3708. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3709. __func__);
  3710. ret = -ENODEV;
  3711. goto err;
  3712. }
  3713. wcd9378->tx_swr_dev->paging_support = true;
  3714. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3715. wcd9378->swr_tx_port_params);
  3716. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3717. &wcd9378_regmap_config);
  3718. if (!wcd9378->regmap) {
  3719. dev_err(dev, "%s: Regmap init failed\n",
  3720. __func__);
  3721. goto err;
  3722. }
  3723. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3724. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3725. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3726. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3727. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3728. wcd9378->irq_info.codec_name = "WCD9378";
  3729. wcd9378->irq_info.regmap = wcd9378->regmap;
  3730. wcd9378->irq_info.dev = dev;
  3731. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3732. if (ret) {
  3733. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3734. __func__, ret);
  3735. goto err;
  3736. }
  3737. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3738. __func__);
  3739. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3740. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3741. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3742. if (ret) {
  3743. dev_err(dev, "%s: Codec registration failed\n",
  3744. __func__);
  3745. goto err_irq;
  3746. }
  3747. wcd9378->dev_up = true;
  3748. return ret;
  3749. err_irq:
  3750. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3751. err:
  3752. component_unbind_all(dev, wcd9378);
  3753. return ret;
  3754. }
  3755. static void wcd9378_unbind(struct device *dev)
  3756. {
  3757. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3758. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3759. snd_soc_unregister_component(dev);
  3760. component_unbind_all(dev, wcd9378);
  3761. }
  3762. static const struct of_device_id wcd9378_dt_match[] = {
  3763. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3764. {}
  3765. };
  3766. static const struct component_master_ops wcd9378_comp_ops = {
  3767. .bind = wcd9378_bind,
  3768. .unbind = wcd9378_unbind,
  3769. };
  3770. static int wcd9378_compare_of(struct device *dev, void *data)
  3771. {
  3772. return dev->of_node == data;
  3773. }
  3774. static void wcd9378_release_of(struct device *dev, void *data)
  3775. {
  3776. of_node_put(data);
  3777. }
  3778. static int wcd9378_add_slave_components(struct device *dev,
  3779. struct component_match **matchptr)
  3780. {
  3781. struct device_node *np, *rx_node, *tx_node;
  3782. np = dev->of_node;
  3783. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3784. if (!rx_node) {
  3785. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3786. return -ENODEV;
  3787. }
  3788. of_node_get(rx_node);
  3789. component_match_add_release(dev, matchptr,
  3790. wcd9378_release_of,
  3791. wcd9378_compare_of,
  3792. rx_node);
  3793. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3794. if (!tx_node) {
  3795. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3796. return -ENODEV;
  3797. }
  3798. of_node_get(tx_node);
  3799. component_match_add_release(dev, matchptr,
  3800. wcd9378_release_of,
  3801. wcd9378_compare_of,
  3802. tx_node);
  3803. return 0;
  3804. }
  3805. static int wcd9378_probe(struct platform_device *pdev)
  3806. {
  3807. struct component_match *match = NULL;
  3808. struct wcd9378_priv *wcd9378 = NULL;
  3809. struct wcd9378_pdata *pdata = NULL;
  3810. struct wcd_ctrl_platform_data *plat_data = NULL;
  3811. struct device *dev = &pdev->dev;
  3812. int ret;
  3813. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3814. GFP_KERNEL);
  3815. if (!wcd9378)
  3816. return -ENOMEM;
  3817. dev_set_drvdata(dev, wcd9378);
  3818. wcd9378->dev = dev;
  3819. pdata = wcd9378_populate_dt_data(dev);
  3820. if (!pdata) {
  3821. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3822. return -EINVAL;
  3823. }
  3824. dev->platform_data = pdata;
  3825. wcd9378->rst_np = pdata->rst_np;
  3826. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3827. pdata->regulator, pdata->num_supplies);
  3828. if (!wcd9378->supplies) {
  3829. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3830. __func__);
  3831. return ret;
  3832. }
  3833. plat_data = dev_get_platdata(dev->parent);
  3834. if (!plat_data) {
  3835. dev_err(dev, "%s: platform data from parent is NULL\n",
  3836. __func__);
  3837. return -EINVAL;
  3838. }
  3839. wcd9378->handle = (void *)plat_data->handle;
  3840. if (!wcd9378->handle) {
  3841. dev_err(dev, "%s: handle is NULL\n", __func__);
  3842. return -EINVAL;
  3843. }
  3844. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3845. if (!wcd9378->update_wcd_event) {
  3846. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3847. __func__);
  3848. return -EINVAL;
  3849. }
  3850. wcd9378->register_notifier = plat_data->register_notifier;
  3851. if (!wcd9378->register_notifier) {
  3852. dev_err(dev, "%s: register_notifier api is null!\n",
  3853. __func__);
  3854. return -EINVAL;
  3855. }
  3856. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3857. &wcd9378->wcd_mode);
  3858. if (ret) {
  3859. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3860. __func__);
  3861. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3862. }
  3863. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3864. pdata->regulator,
  3865. pdata->num_supplies);
  3866. if (ret) {
  3867. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3868. __func__);
  3869. return ret;
  3870. }
  3871. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3872. CODEC_RX);
  3873. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3874. CODEC_TX);
  3875. if (ret) {
  3876. dev_err(dev, "Failed to read port mapping\n");
  3877. goto err;
  3878. }
  3879. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3880. CODEC_TX);
  3881. if (ret) {
  3882. dev_err(dev, "Failed to read port params\n");
  3883. goto err;
  3884. }
  3885. mutex_init(&wcd9378->wakeup_lock);
  3886. mutex_init(&wcd9378->micb_lock);
  3887. mutex_init(&wcd9378->sys_usage_lock);
  3888. ret = wcd9378_add_slave_components(dev, &match);
  3889. if (ret)
  3890. goto err_lock_init;
  3891. ret = wcd9378_reset(dev);
  3892. if (ret == -EPROBE_DEFER) {
  3893. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3894. goto err_lock_init;
  3895. }
  3896. wcd9378->wakeup = wcd9378_wakeup;
  3897. return component_master_add_with_match(dev,
  3898. &wcd9378_comp_ops, match);
  3899. err_lock_init:
  3900. mutex_destroy(&wcd9378->micb_lock);
  3901. mutex_destroy(&wcd9378->wakeup_lock);
  3902. mutex_destroy(&wcd9378->sys_usage_lock);
  3903. err:
  3904. return ret;
  3905. }
  3906. static int wcd9378_remove(struct platform_device *pdev)
  3907. {
  3908. struct wcd9378_priv *wcd9378 = NULL;
  3909. wcd9378 = platform_get_drvdata(pdev);
  3910. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3911. mutex_destroy(&wcd9378->micb_lock);
  3912. mutex_destroy(&wcd9378->wakeup_lock);
  3913. mutex_destroy(&wcd9378->sys_usage_lock);
  3914. dev_set_drvdata(&pdev->dev, NULL);
  3915. return 0;
  3916. }
  3917. #ifdef CONFIG_PM_SLEEP
  3918. static int wcd9378_suspend(struct device *dev)
  3919. {
  3920. struct wcd9378_priv *wcd9378 = NULL;
  3921. int ret = 0;
  3922. struct wcd9378_pdata *pdata = NULL;
  3923. if (!dev)
  3924. return -ENODEV;
  3925. wcd9378 = dev_get_drvdata(dev);
  3926. if (!wcd9378)
  3927. return -EINVAL;
  3928. pdata = dev_get_platdata(wcd9378->dev);
  3929. if (!pdata) {
  3930. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3931. return -EINVAL;
  3932. }
  3933. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3934. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3935. wcd9378->supplies,
  3936. pdata->regulator,
  3937. pdata->num_supplies,
  3938. "cdc-vdd-buck");
  3939. if (ret == -EINVAL) {
  3940. dev_err(dev, "%s: vdd buck is not disabled\n",
  3941. __func__);
  3942. return 0;
  3943. }
  3944. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3945. }
  3946. if (wcd9378->dapm_bias_off) {
  3947. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3948. wcd9378->supplies,
  3949. pdata->regulator,
  3950. pdata->num_supplies,
  3951. true);
  3952. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3953. }
  3954. return 0;
  3955. }
  3956. static int wcd9378_resume(struct device *dev)
  3957. {
  3958. struct wcd9378_priv *wcd9378 = NULL;
  3959. struct wcd9378_pdata *pdata = NULL;
  3960. if (!dev)
  3961. return -ENODEV;
  3962. wcd9378 = dev_get_drvdata(dev);
  3963. if (!wcd9378)
  3964. return -EINVAL;
  3965. pdata = dev_get_platdata(wcd9378->dev);
  3966. if (!pdata) {
  3967. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3968. return -EINVAL;
  3969. }
  3970. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3971. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3972. wcd9378->supplies,
  3973. pdata->regulator,
  3974. pdata->num_supplies,
  3975. false);
  3976. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3977. }
  3978. return 0;
  3979. }
  3980. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3981. .suspend_late = wcd9378_suspend,
  3982. .resume_early = wcd9378_resume,
  3983. };
  3984. #endif
  3985. static struct platform_driver wcd9378_codec_driver = {
  3986. .probe = wcd9378_probe,
  3987. .remove = wcd9378_remove,
  3988. .driver = {
  3989. .name = "wcd9378_codec",
  3990. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3991. #ifdef CONFIG_PM_SLEEP
  3992. .pm = &wcd9378_dev_pm_ops,
  3993. #endif
  3994. .suppress_bind_attrs = true,
  3995. },
  3996. };
  3997. module_platform_driver(wcd9378_codec_driver);
  3998. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3999. MODULE_LICENSE("GPL");