dp_power.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/pm_runtime.h>
  7. #include <drm/drmP.h>
  8. #include "dp_power.h"
  9. #include "dp_catalog.h"
  10. #include "dp_debug.h"
  11. #include "dp_pll.h"
  12. #define DP_CLIENT_NAME_SIZE 20
  13. struct dp_power_private {
  14. struct dp_parser *parser;
  15. struct dp_pll *pll;
  16. struct platform_device *pdev;
  17. struct clk *pixel_clk_rcg;
  18. struct clk *pixel_parent;
  19. struct clk *pixel1_clk_rcg;
  20. struct dp_power dp_power;
  21. bool core_clks_on;
  22. bool link_clks_on;
  23. bool strm0_clks_on;
  24. bool strm1_clks_on;
  25. };
  26. static int dp_power_regulator_init(struct dp_power_private *power)
  27. {
  28. int rc = 0, i = 0, j = 0;
  29. struct platform_device *pdev;
  30. struct dp_parser *parser;
  31. parser = power->parser;
  32. pdev = power->pdev;
  33. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  34. rc = msm_dss_get_vreg(&pdev->dev,
  35. parser->mp[i].vreg_config,
  36. parser->mp[i].num_vreg, 1);
  37. if (rc) {
  38. DP_ERR("failed to init vregs for %s\n",
  39. dp_parser_pm_name(i));
  40. for (j = i - 1; j >= DP_CORE_PM; j--) {
  41. msm_dss_get_vreg(&pdev->dev,
  42. parser->mp[j].vreg_config,
  43. parser->mp[j].num_vreg, 0);
  44. }
  45. goto error;
  46. }
  47. }
  48. error:
  49. return rc;
  50. }
  51. static void dp_power_regulator_deinit(struct dp_power_private *power)
  52. {
  53. int rc = 0, i = 0;
  54. struct platform_device *pdev;
  55. struct dp_parser *parser;
  56. parser = power->parser;
  57. pdev = power->pdev;
  58. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  59. rc = msm_dss_get_vreg(&pdev->dev,
  60. parser->mp[i].vreg_config,
  61. parser->mp[i].num_vreg, 0);
  62. if (rc)
  63. DP_ERR("failed to deinit vregs for %s\n",
  64. dp_parser_pm_name(i));
  65. }
  66. }
  67. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  68. {
  69. int rc = 0, i = 0, j = 0;
  70. struct dp_parser *parser;
  71. parser = power->parser;
  72. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  73. /*
  74. * The DP_PLL_PM regulator is controlled by dp_display based
  75. * on the link configuration.
  76. */
  77. if (i == DP_PLL_PM) {
  78. DP_DEBUG("skipping: '%s' vregs for %s\n",
  79. enable ? "enable" : "disable",
  80. dp_parser_pm_name(i));
  81. continue;
  82. }
  83. rc = msm_dss_enable_vreg(
  84. parser->mp[i].vreg_config,
  85. parser->mp[i].num_vreg, enable);
  86. if (rc) {
  87. DP_ERR("failed to '%s' vregs for %s\n",
  88. enable ? "enable" : "disable",
  89. dp_parser_pm_name(i));
  90. if (enable) {
  91. for (j = i-1; j >= DP_CORE_PM; j--) {
  92. msm_dss_enable_vreg(
  93. parser->mp[j].vreg_config,
  94. parser->mp[j].num_vreg, 0);
  95. }
  96. }
  97. goto error;
  98. }
  99. }
  100. error:
  101. return rc;
  102. }
  103. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  104. {
  105. int rc = -EFAULT;
  106. struct pinctrl_state *pin_state;
  107. struct dp_parser *parser;
  108. parser = power->parser;
  109. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  110. return 0;
  111. if (parser->no_aux_switch && parser->lphw_hpd) {
  112. pin_state = active ? parser->pinctrl.state_hpd_ctrl
  113. : parser->pinctrl.state_hpd_tlmm;
  114. if (!IS_ERR_OR_NULL(pin_state)) {
  115. rc = pinctrl_select_state(parser->pinctrl.pin,
  116. pin_state);
  117. if (rc) {
  118. DP_ERR("cannot direct hpd line to %s\n",
  119. active ? "ctrl" : "tlmm");
  120. return rc;
  121. }
  122. }
  123. }
  124. if (parser->no_aux_switch)
  125. return 0;
  126. pin_state = active ? parser->pinctrl.state_active
  127. : parser->pinctrl.state_suspend;
  128. if (!IS_ERR_OR_NULL(pin_state)) {
  129. rc = pinctrl_select_state(parser->pinctrl.pin,
  130. pin_state);
  131. if (rc)
  132. DP_ERR("can not set %s pins\n",
  133. active ? "dp_active"
  134. : "dp_sleep");
  135. } else {
  136. DP_ERR("invalid '%s' pinstate\n",
  137. active ? "dp_active"
  138. : "dp_sleep");
  139. }
  140. return rc;
  141. }
  142. static void dp_power_clk_put(struct dp_power_private *power)
  143. {
  144. enum dp_pm_type module;
  145. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  146. struct dss_module_power *pm = &power->parser->mp[module];
  147. if (!pm->num_clk)
  148. continue;
  149. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  150. }
  151. }
  152. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  153. {
  154. int rc = 0;
  155. struct device *dev;
  156. enum dp_pm_type module;
  157. dev = &power->pdev->dev;
  158. if (enable) {
  159. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  160. struct dss_module_power *pm =
  161. &power->parser->mp[module];
  162. if (!pm->num_clk)
  163. continue;
  164. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  165. if (rc) {
  166. DP_ERR("failed to get %s clk. err=%d\n",
  167. dp_parser_pm_name(module), rc);
  168. goto exit;
  169. }
  170. }
  171. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  172. if (IS_ERR(power->pixel_clk_rcg)) {
  173. DP_ERR("Unable to get DP pixel clk RCG: %d\n",
  174. PTR_ERR(power->pixel_clk_rcg));
  175. rc = PTR_ERR(power->pixel_clk_rcg);
  176. power->pixel_clk_rcg = NULL;
  177. goto err_pixel_clk_rcg;
  178. }
  179. power->pixel_parent = clk_get(dev, "pixel_parent");
  180. if (IS_ERR(power->pixel_parent)) {
  181. DP_DEBUG("Unable to get DP pixel RCG parent: %d\n",
  182. PTR_ERR(power->pixel_parent));
  183. rc = PTR_ERR(power->pixel_parent);
  184. power->pixel_parent = NULL;
  185. goto err_pixel_parent;
  186. }
  187. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  188. if (IS_ERR(power->pixel1_clk_rcg)) {
  189. DP_DEBUG("Unable to get DP pixel1 clk RCG: %d\n",
  190. PTR_ERR(power->pixel1_clk_rcg));
  191. rc = PTR_ERR(power->pixel1_clk_rcg);
  192. power->pixel1_clk_rcg = NULL;
  193. goto err_pixel1_clk_rcg;
  194. }
  195. } else {
  196. if (power->pixel1_clk_rcg)
  197. clk_put(power->pixel1_clk_rcg);
  198. if (power->pixel_parent)
  199. clk_put(power->pixel_parent);
  200. if (power->pixel_clk_rcg)
  201. clk_put(power->pixel_clk_rcg);
  202. dp_power_clk_put(power);
  203. }
  204. return rc;
  205. err_pixel1_clk_rcg:
  206. clk_put(power->pixel_parent);
  207. err_pixel_parent:
  208. clk_put(power->pixel_clk_rcg);
  209. err_pixel_clk_rcg:
  210. dp_power_clk_put(power);
  211. exit:
  212. return rc;
  213. }
  214. static int dp_power_clk_set_rate(struct dp_power_private *power,
  215. enum dp_pm_type module, bool enable)
  216. {
  217. int rc = 0;
  218. struct dss_module_power *mp;
  219. if (!power) {
  220. DP_ERR("invalid power data\n");
  221. rc = -EINVAL;
  222. goto exit;
  223. }
  224. mp = &power->parser->mp[module];
  225. if (enable) {
  226. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  227. if (rc) {
  228. DP_ERR("failed to set clks rate.\n");
  229. goto exit;
  230. }
  231. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  232. if (rc) {
  233. DP_ERR("failed to enable clks\n");
  234. goto exit;
  235. }
  236. } else {
  237. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  238. if (rc) {
  239. DP_ERR("failed to disable clks\n");
  240. goto exit;
  241. }
  242. }
  243. exit:
  244. return rc;
  245. }
  246. static int dp_power_clk_enable(struct dp_power *dp_power,
  247. enum dp_pm_type pm_type, bool enable)
  248. {
  249. int rc = 0;
  250. struct dss_module_power *mp;
  251. struct dp_power_private *power;
  252. if (!dp_power) {
  253. DP_ERR("invalid power data\n");
  254. rc = -EINVAL;
  255. goto error;
  256. }
  257. power = container_of(dp_power, struct dp_power_private, dp_power);
  258. mp = &power->parser->mp[pm_type];
  259. if (pm_type >= DP_MAX_PM) {
  260. DP_ERR("unsupported power module: %s\n",
  261. dp_parser_pm_name(pm_type));
  262. return -EINVAL;
  263. }
  264. if (enable) {
  265. if (pm_type == DP_CORE_PM && power->core_clks_on) {
  266. DP_DEBUG("core clks already enabled\n");
  267. return 0;
  268. }
  269. if ((pm_type == DP_STREAM0_PM) && (power->strm0_clks_on)) {
  270. DP_DEBUG("strm0 clks already enabled\n");
  271. return 0;
  272. }
  273. if ((pm_type == DP_STREAM1_PM) && (power->strm1_clks_on)) {
  274. DP_DEBUG("strm1 clks already enabled\n");
  275. return 0;
  276. }
  277. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  278. DP_DEBUG("Need to enable core clks before link clks\n");
  279. rc = dp_power_clk_set_rate(power, pm_type, enable);
  280. if (rc) {
  281. DP_ERR("failed to enable clks: %s. err=%d\n",
  282. dp_parser_pm_name(DP_CORE_PM), rc);
  283. goto error;
  284. } else {
  285. power->core_clks_on = true;
  286. }
  287. }
  288. if (pm_type == DP_LINK_PM && power->link_clks_on) {
  289. DP_DEBUG("links clks already enabled\n");
  290. return 0;
  291. }
  292. }
  293. rc = dp_power_clk_set_rate(power, pm_type, enable);
  294. if (rc) {
  295. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  296. enable ? "enable" : "disable",
  297. dp_parser_pm_name(pm_type), rc);
  298. goto error;
  299. }
  300. if (pm_type == DP_CORE_PM)
  301. power->core_clks_on = enable;
  302. else if (pm_type == DP_STREAM0_PM)
  303. power->strm0_clks_on = enable;
  304. else if (pm_type == DP_STREAM1_PM)
  305. power->strm1_clks_on = enable;
  306. else if (pm_type == DP_LINK_PM)
  307. power->link_clks_on = enable;
  308. /*
  309. * This log is printed only when user connects or disconnects
  310. * a DP cable. As this is a user-action and not a frequent
  311. * usecase, it is not going to flood the kernel logs. Also,
  312. * helpful in debugging the NOC issues.
  313. */
  314. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  315. power->core_clks_on ? "on" : "off",
  316. power->link_clks_on ? "on" : "off",
  317. power->strm0_clks_on ? "on" : "off",
  318. power->strm1_clks_on ? "on" : "off");
  319. error:
  320. return rc;
  321. }
  322. static int dp_power_request_gpios(struct dp_power_private *power)
  323. {
  324. int rc = 0, i;
  325. struct device *dev;
  326. struct dss_module_power *mp;
  327. static const char * const gpio_names[] = {
  328. "aux_enable", "aux_sel", "usbplug_cc",
  329. };
  330. if (!power) {
  331. DP_ERR("invalid power data\n");
  332. return -EINVAL;
  333. }
  334. dev = &power->pdev->dev;
  335. mp = &power->parser->mp[DP_CORE_PM];
  336. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  337. unsigned int gpio = mp->gpio_config[i].gpio;
  338. if (gpio_is_valid(gpio)) {
  339. rc = gpio_request(gpio, gpio_names[i]);
  340. if (rc) {
  341. DP_ERR("request %s gpio failed, rc=%d\n",
  342. gpio_names[i], rc);
  343. goto error;
  344. }
  345. }
  346. }
  347. return 0;
  348. error:
  349. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  350. unsigned int gpio = mp->gpio_config[i].gpio;
  351. if (gpio_is_valid(gpio))
  352. gpio_free(gpio);
  353. }
  354. return rc;
  355. }
  356. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  357. {
  358. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  359. }
  360. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  361. {
  362. int i;
  363. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  364. struct dss_gpio *config = mp->gpio_config;
  365. for (i = 0; i < mp->num_gpio; i++) {
  366. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  367. config->value = flip;
  368. if (gpio_is_valid(config->gpio)) {
  369. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  370. config->value);
  371. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  372. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  373. gpio_direction_output(config->gpio,
  374. config->value);
  375. else
  376. gpio_set_value(config->gpio, config->value);
  377. }
  378. config++;
  379. }
  380. }
  381. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  382. bool enable)
  383. {
  384. int rc = 0, i;
  385. struct dss_module_power *mp;
  386. struct dss_gpio *config;
  387. if (power->parser->no_aux_switch)
  388. return 0;
  389. mp = &power->parser->mp[DP_CORE_PM];
  390. config = mp->gpio_config;
  391. if (enable) {
  392. rc = dp_power_request_gpios(power);
  393. if (rc) {
  394. DP_ERR("gpio request failed\n");
  395. return rc;
  396. }
  397. dp_power_set_gpio(power, flip);
  398. } else {
  399. for (i = 0; i < mp->num_gpio; i++) {
  400. if (gpio_is_valid(config[i].gpio)) {
  401. gpio_set_value(config[i].gpio, 0);
  402. gpio_free(config[i].gpio);
  403. }
  404. }
  405. }
  406. return 0;
  407. }
  408. static int dp_power_client_init(struct dp_power *dp_power,
  409. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  410. {
  411. int rc = 0;
  412. struct dp_power_private *power;
  413. if (!drm_dev) {
  414. DP_ERR("invalid drm_dev\n");
  415. return -EINVAL;
  416. }
  417. power = container_of(dp_power, struct dp_power_private, dp_power);
  418. rc = dp_power_regulator_init(power);
  419. if (rc) {
  420. DP_ERR("failed to init regulators\n");
  421. goto error_power;
  422. }
  423. rc = dp_power_clk_init(power, true);
  424. if (rc) {
  425. DP_ERR("failed to init clocks\n");
  426. goto error_clk;
  427. }
  428. dp_power->phandle = phandle;
  429. dp_power->drm_dev = drm_dev;
  430. return 0;
  431. error_clk:
  432. dp_power_regulator_deinit(power);
  433. error_power:
  434. return rc;
  435. }
  436. static void dp_power_client_deinit(struct dp_power *dp_power)
  437. {
  438. struct dp_power_private *power;
  439. if (!dp_power) {
  440. DP_ERR("invalid power data\n");
  441. return;
  442. }
  443. power = container_of(dp_power, struct dp_power_private, dp_power);
  444. dp_power_clk_init(power, false);
  445. dp_power_regulator_deinit(power);
  446. }
  447. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  448. {
  449. int rc = 0;
  450. struct dp_power_private *power;
  451. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  452. DP_ERR("invalid power data. stream %d\n", strm_id);
  453. rc = -EINVAL;
  454. goto exit;
  455. }
  456. power = container_of(dp_power, struct dp_power_private, dp_power);
  457. if (strm_id == DP_STREAM_0) {
  458. if (power->pixel_clk_rcg && power->pixel_parent)
  459. rc = clk_set_parent(power->pixel_clk_rcg,
  460. power->pixel_parent);
  461. else
  462. DP_WARN("skipped for strm_id=%d\n", strm_id);
  463. } else if (strm_id == DP_STREAM_1) {
  464. if (power->pixel1_clk_rcg && power->pixel_parent)
  465. rc = clk_set_parent(power->pixel1_clk_rcg,
  466. power->pixel_parent);
  467. else
  468. DP_WARN("skipped for strm_id=%d\n", strm_id);
  469. }
  470. if (rc)
  471. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  472. exit:
  473. return rc;
  474. }
  475. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  476. {
  477. size_t i;
  478. enum dp_pm_type j;
  479. struct dss_module_power *mp;
  480. struct dp_power_private *power;
  481. bool clk_found = false;
  482. u64 rate = 0;
  483. if (!clk_name) {
  484. DP_ERR("invalid pointer for clk_name\n");
  485. return 0;
  486. }
  487. power = container_of(dp_power, struct dp_power_private, dp_power);
  488. mp = &dp_power->phandle->mp;
  489. for (i = 0; i < mp->num_clk; i++) {
  490. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  491. rate = clk_get_rate(mp->clk_config[i].clk);
  492. clk_found = true;
  493. break;
  494. }
  495. }
  496. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  497. mp = &power->parser->mp[j];
  498. for (i = 0; i < mp->num_clk; i++) {
  499. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  500. rate = clk_get_rate(mp->clk_config[i].clk);
  501. clk_found = true;
  502. break;
  503. }
  504. }
  505. }
  506. return rate;
  507. }
  508. static int dp_power_init(struct dp_power *dp_power, bool flip)
  509. {
  510. int rc = 0;
  511. struct dp_power_private *power;
  512. if (!dp_power) {
  513. DP_ERR("invalid power data\n");
  514. rc = -EINVAL;
  515. goto exit;
  516. }
  517. power = container_of(dp_power, struct dp_power_private, dp_power);
  518. rc = dp_power_regulator_ctrl(power, true);
  519. if (rc) {
  520. DP_ERR("failed to enable regulators\n");
  521. goto exit;
  522. }
  523. rc = dp_power_pinctrl_set(power, true);
  524. if (rc) {
  525. DP_ERR("failed to set pinctrl state\n");
  526. goto err_pinctrl;
  527. }
  528. rc = dp_power_config_gpios(power, flip, true);
  529. if (rc) {
  530. DP_ERR("failed to enable gpios\n");
  531. goto err_gpio;
  532. }
  533. rc = pm_runtime_get_sync(dp_power->drm_dev->dev);
  534. if (rc < 0) {
  535. DP_ERR("Power resource enable failed\n");
  536. goto err_sde_power;
  537. }
  538. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  539. if (rc) {
  540. DP_ERR("failed to enable DP core clocks\n");
  541. goto err_clk;
  542. }
  543. return 0;
  544. err_clk:
  545. pm_runtime_put_sync(dp_power->drm_dev->dev);
  546. err_sde_power:
  547. dp_power_config_gpios(power, flip, false);
  548. err_gpio:
  549. dp_power_pinctrl_set(power, false);
  550. err_pinctrl:
  551. dp_power_regulator_ctrl(power, false);
  552. exit:
  553. return rc;
  554. }
  555. static int dp_power_deinit(struct dp_power *dp_power)
  556. {
  557. int rc = 0;
  558. struct dp_power_private *power;
  559. if (!dp_power) {
  560. DP_ERR("invalid power data\n");
  561. rc = -EINVAL;
  562. goto exit;
  563. }
  564. power = container_of(dp_power, struct dp_power_private, dp_power);
  565. if (power->link_clks_on)
  566. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  567. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  568. pm_runtime_put_sync(dp_power->drm_dev->dev);
  569. dp_power_config_gpios(power, false, false);
  570. dp_power_pinctrl_set(power, false);
  571. dp_power_regulator_ctrl(power, false);
  572. exit:
  573. return rc;
  574. }
  575. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  576. {
  577. int rc = 0;
  578. struct dp_power_private *power;
  579. struct dp_power *dp_power;
  580. if (!parser || !pll) {
  581. DP_ERR("invalid input\n");
  582. rc = -EINVAL;
  583. goto error;
  584. }
  585. power = kzalloc(sizeof(*power), GFP_KERNEL);
  586. if (!power) {
  587. rc = -ENOMEM;
  588. goto error;
  589. }
  590. power->parser = parser;
  591. power->pll = pll;
  592. power->pdev = parser->pdev;
  593. dp_power = &power->dp_power;
  594. dp_power->init = dp_power_init;
  595. dp_power->deinit = dp_power_deinit;
  596. dp_power->clk_enable = dp_power_clk_enable;
  597. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  598. dp_power->clk_get_rate = dp_power_clk_get_rate;
  599. dp_power->power_client_init = dp_power_client_init;
  600. dp_power->power_client_deinit = dp_power_client_deinit;
  601. return dp_power;
  602. error:
  603. return ERR_PTR(rc);
  604. }
  605. void dp_power_put(struct dp_power *dp_power)
  606. {
  607. struct dp_power_private *power = NULL;
  608. if (!dp_power)
  609. return;
  610. power = container_of(dp_power, struct dp_power_private, dp_power);
  611. kfree(power);
  612. }