sde_plane.c 134 KB

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  1. /*
  2. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  52. /**
  53. * enum sde_plane_qos - Different qos configurations for each pipe
  54. *
  55. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  56. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  57. * this configuration is mutually exclusive from VBLANK_CTRL.
  58. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  59. */
  60. enum sde_plane_qos {
  61. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  62. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  63. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  64. };
  65. /*
  66. * struct sde_plane - local sde plane structure
  67. * @aspace: address space pointer
  68. * @csc_cfg: Decoded user configuration for csc
  69. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  70. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  71. * @mplane_list: List of multirect planes of the same pipe
  72. * @catalog: Points to sde catalog structure
  73. * @revalidate: force revalidation of all the plane properties
  74. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  75. * @blob_rot_caps: Pointer to rotator capability blob
  76. */
  77. struct sde_plane {
  78. struct drm_plane base;
  79. struct mutex lock;
  80. enum sde_sspp pipe;
  81. uint64_t features; /* capabilities from catalog */
  82. uint32_t perf_features; /* perf capabilities from catalog */
  83. uint32_t nformats;
  84. uint32_t formats[64];
  85. struct sde_hw_pipe *pipe_hw;
  86. struct sde_hw_pipe_cfg pipe_cfg;
  87. struct sde_hw_sharp_cfg sharp_cfg;
  88. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  89. uint32_t color_fill;
  90. bool is_error;
  91. bool is_rt_pipe;
  92. bool is_virtual;
  93. struct list_head mplane_list;
  94. struct sde_mdss_cfg *catalog;
  95. bool revalidate;
  96. bool xin_halt_forced_clk;
  97. struct sde_csc_cfg csc_cfg;
  98. struct sde_csc_cfg *csc_usr_ptr;
  99. struct sde_csc_cfg *csc_ptr;
  100. const struct sde_sspp_sub_blks *pipe_sblk;
  101. char pipe_name[SDE_NAME_SIZE];
  102. struct msm_property_info property_info;
  103. struct msm_property_data property_data[PLANE_PROP_COUNT];
  104. struct drm_property_blob *blob_info;
  105. struct drm_property_blob *blob_rot_caps;
  106. /* debugfs related stuff */
  107. struct dentry *debugfs_root;
  108. bool debugfs_default_scale;
  109. };
  110. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  111. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  112. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  113. {
  114. struct msm_drm_private *priv;
  115. if (!plane || !plane->dev)
  116. return NULL;
  117. priv = plane->dev->dev_private;
  118. if (!priv)
  119. return NULL;
  120. return to_sde_kms(priv->kms);
  121. }
  122. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  123. {
  124. struct drm_plane_state *pstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. struct sde_crtc *sde_crtc = NULL;
  127. struct sde_crtc_mixer *mixer = NULL;
  128. struct sde_hw_ctl *ctl = NULL;
  129. if (!plane) {
  130. DRM_ERROR("Invalid plane %pK\n", plane);
  131. return NULL;
  132. }
  133. pstate = plane->state;
  134. if (!pstate) {
  135. DRM_ERROR("Invalid plane state %pK\n", pstate);
  136. return NULL;
  137. }
  138. drm_crtc = pstate->crtc;
  139. if (!drm_crtc) {
  140. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  141. return NULL;
  142. }
  143. sde_crtc = to_sde_crtc(drm_crtc);
  144. if (!sde_crtc) {
  145. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  146. return NULL;
  147. }
  148. /* it will always return the first mixer and single CTL */
  149. mixer = sde_crtc->mixers;
  150. if (!mixer) {
  151. DRM_ERROR("invalid mixer %pK\n", mixer);
  152. return NULL;
  153. }
  154. ctl = mixer->hw_ctl;
  155. if (!mixer) {
  156. DRM_ERROR("invalid ctl %pK\n", ctl);
  157. return NULL;
  158. }
  159. return ctl;
  160. }
  161. static bool sde_plane_enabled(const struct drm_plane_state *state)
  162. {
  163. return state && state->fb && state->crtc;
  164. }
  165. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  166. {
  167. struct sde_plane *psde;
  168. if (!plane)
  169. return false;
  170. psde = to_sde_plane(plane);
  171. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  172. }
  173. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  174. enum sde_sspp_multirect_index rect_mode, bool enable)
  175. {
  176. struct sde_plane *psde;
  177. if (!plane)
  178. return;
  179. psde = to_sde_plane(plane);
  180. if (psde->pipe_hw->ops.set_src_split_order)
  181. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  182. rect_mode, enable);
  183. }
  184. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  185. {
  186. struct sde_plane *psde;
  187. struct sde_kms *sde_kms;
  188. struct msm_drm_private *priv;
  189. if (!plane || !plane->dev) {
  190. SDE_ERROR("invalid plane\n");
  191. return;
  192. }
  193. priv = plane->dev->dev_private;
  194. if (!priv || !priv->kms) {
  195. SDE_ERROR("invalid KMS reference\n");
  196. return;
  197. }
  198. sde_kms = to_sde_kms(priv->kms);
  199. psde = to_sde_plane(plane);
  200. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  201. }
  202. void _sde_plane_set_qos_lut(struct drm_plane *plane,
  203. struct drm_crtc *crtc,
  204. struct drm_framebuffer *fb)
  205. {
  206. struct sde_plane *psde;
  207. const struct sde_format *fmt = NULL;
  208. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, index;
  209. struct sde_perf_cfg *perf;
  210. struct sde_plane_state *pstate;
  211. bool inline_rot = false;
  212. if (!plane || !fb) {
  213. SDE_ERROR("invalid arguments\n");
  214. return;
  215. }
  216. psde = to_sde_plane(plane);
  217. pstate = to_sde_plane_state(plane->state);
  218. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  219. SDE_ERROR("invalid arguments\n");
  220. return;
  221. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  222. return;
  223. }
  224. frame_rate = drm_mode_vrefresh(&crtc->mode);
  225. perf = &psde->catalog->perf;
  226. qos_count = perf->qos_refresh_count;
  227. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  228. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  229. (fps_index == qos_count - 1))
  230. break;
  231. fps_index++;
  232. }
  233. if (psde->is_rt_pipe) {
  234. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  235. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  236. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  237. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  238. else if (inline_rot)
  239. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  240. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  241. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  242. else
  243. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  244. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  245. if (pstate->scaler3_cfg.enable)
  246. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  247. } else {
  248. lut_index = SDE_QOS_LUT_USAGE_NRT;
  249. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  250. }
  251. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  252. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  253. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  254. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX);
  255. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  256. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  257. (fmt) ? fmt->base.pixel_format : 0,
  258. (fmt) ? fmt->fetch_mode : 0,
  259. psde->pipe_qos_cfg.danger_lut,
  260. psde->pipe_qos_cfg.safe_lut,
  261. psde->pipe_qos_cfg.creq_lut);
  262. SDE_DEBUG(
  263. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  264. plane->base.id,
  265. psde->pipe - SSPP_VIG0,
  266. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  267. fmt ? fmt->fetch_mode : -1,
  268. psde->pipe_qos_cfg.danger_lut,
  269. psde->pipe_qos_cfg.safe_lut,
  270. psde->pipe_qos_cfg.creq_lut);
  271. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  272. }
  273. /**
  274. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  275. * @plane: Pointer to drm plane
  276. * @enable: true to enable QoS control
  277. * @flags: QoS control mode (enum sde_plane_qos)
  278. */
  279. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  280. bool enable, u32 flags)
  281. {
  282. struct sde_plane *psde;
  283. if (!plane) {
  284. SDE_ERROR("invalid arguments\n");
  285. return;
  286. }
  287. psde = to_sde_plane(plane);
  288. if (!psde->pipe_hw || !psde->pipe_sblk) {
  289. SDE_ERROR("invalid arguments\n");
  290. return;
  291. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  292. return;
  293. }
  294. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  295. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  296. psde->pipe_qos_cfg.danger_vblank =
  297. psde->pipe_sblk->danger_vblank;
  298. psde->pipe_qos_cfg.vblank_en = enable;
  299. }
  300. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  301. /* this feature overrules previous VBLANK_CTRL */
  302. psde->pipe_qos_cfg.vblank_en = false;
  303. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  304. }
  305. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  306. psde->pipe_qos_cfg.danger_safe_en = enable;
  307. if (!psde->is_rt_pipe) {
  308. psde->pipe_qos_cfg.vblank_en = false;
  309. psde->pipe_qos_cfg.danger_safe_en = false;
  310. }
  311. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  312. plane->base.id,
  313. psde->pipe - SSPP_VIG0,
  314. psde->pipe_qos_cfg.danger_safe_en,
  315. psde->pipe_qos_cfg.vblank_en,
  316. psde->pipe_qos_cfg.creq_vblank,
  317. psde->pipe_qos_cfg.danger_vblank,
  318. psde->is_rt_pipe);
  319. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  320. &psde->pipe_qos_cfg);
  321. }
  322. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  323. {
  324. struct sde_plane *psde;
  325. if (!plane)
  326. return;
  327. psde = to_sde_plane(plane);
  328. psde->revalidate = enable;
  329. }
  330. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  331. {
  332. struct sde_plane *psde;
  333. int rc;
  334. if (!plane) {
  335. SDE_ERROR("invalid arguments\n");
  336. return -EINVAL;
  337. }
  338. psde = to_sde_plane(plane);
  339. if (!psde->is_rt_pipe)
  340. goto end;
  341. rc = pm_runtime_get_sync(plane->dev->dev);
  342. if (rc < 0) {
  343. SDE_ERROR("failed to enable power resource %d\n", rc);
  344. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  345. return rc;
  346. }
  347. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  348. pm_runtime_put_sync(plane->dev->dev);
  349. end:
  350. return 0;
  351. }
  352. /**
  353. * _sde_plane_set_ot_limit - set OT limit for the given plane
  354. * @plane: Pointer to drm plane
  355. * @crtc: Pointer to drm crtc
  356. */
  357. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  358. struct drm_crtc *crtc)
  359. {
  360. struct sde_plane *psde;
  361. struct sde_vbif_set_ot_params ot_params;
  362. struct msm_drm_private *priv;
  363. struct sde_kms *sde_kms;
  364. if (!plane || !plane->dev || !crtc) {
  365. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  366. !plane, !crtc);
  367. return;
  368. }
  369. priv = plane->dev->dev_private;
  370. if (!priv || !priv->kms) {
  371. SDE_ERROR("invalid KMS reference\n");
  372. return;
  373. }
  374. sde_kms = to_sde_kms(priv->kms);
  375. psde = to_sde_plane(plane);
  376. if (!psde->pipe_hw) {
  377. SDE_ERROR("invalid pipe reference\n");
  378. return;
  379. }
  380. memset(&ot_params, 0, sizeof(ot_params));
  381. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  382. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  383. ot_params.width = psde->pipe_cfg.src_rect.w;
  384. ot_params.height = psde->pipe_cfg.src_rect.h;
  385. ot_params.is_wfd = !psde->is_rt_pipe;
  386. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  387. ot_params.vbif_idx = VBIF_RT;
  388. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  389. ot_params.rd = true;
  390. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  391. }
  392. /**
  393. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  394. * @plane: Pointer to drm plane
  395. */
  396. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  397. {
  398. struct sde_plane *psde;
  399. struct sde_vbif_set_qos_params qos_params;
  400. struct msm_drm_private *priv;
  401. struct sde_kms *sde_kms;
  402. if (!plane || !plane->dev) {
  403. SDE_ERROR("invalid arguments\n");
  404. return;
  405. }
  406. priv = plane->dev->dev_private;
  407. if (!priv || !priv->kms) {
  408. SDE_ERROR("invalid KMS reference\n");
  409. return;
  410. }
  411. sde_kms = to_sde_kms(priv->kms);
  412. psde = to_sde_plane(plane);
  413. if (!psde->pipe_hw) {
  414. SDE_ERROR("invalid pipe reference\n");
  415. return;
  416. }
  417. memset(&qos_params, 0, sizeof(qos_params));
  418. qos_params.vbif_idx = VBIF_RT;
  419. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  420. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  421. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  422. qos_params.client_type = psde->is_rt_pipe ?
  423. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  424. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  425. plane->base.id, qos_params.num,
  426. qos_params.vbif_idx,
  427. qos_params.xin_id, qos_params.client_type,
  428. qos_params.clk_ctrl);
  429. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  430. }
  431. /**
  432. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  433. * @plane: Pointer to drm plane
  434. * @pstate: Pointer to sde plane state
  435. */
  436. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  437. struct sde_plane_state *pstate)
  438. {
  439. struct sde_plane *psde;
  440. struct sde_hw_pipe_ts_cfg cfg;
  441. struct msm_drm_private *priv;
  442. struct sde_kms *sde_kms;
  443. if (!plane || !plane->dev) {
  444. SDE_ERROR("invalid arguments");
  445. return;
  446. }
  447. priv = plane->dev->dev_private;
  448. if (!priv || !priv->kms) {
  449. SDE_ERROR("invalid KMS reference\n");
  450. return;
  451. }
  452. sde_kms = to_sde_kms(priv->kms);
  453. psde = to_sde_plane(plane);
  454. if (!psde->pipe_hw) {
  455. SDE_ERROR("invalid pipe reference\n");
  456. return;
  457. }
  458. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  459. return;
  460. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  461. memset(&cfg, 0, sizeof(cfg));
  462. cfg.size = sde_plane_get_property(pstate,
  463. PLANE_PROP_PREFILL_SIZE);
  464. cfg.time = sde_plane_get_property(pstate,
  465. PLANE_PROP_PREFILL_TIME);
  466. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  467. plane->base.id, cfg.size, cfg.time);
  468. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  469. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  470. pstate->multirect_index);
  471. }
  472. /* helper to update a state's input fence pointer from the property */
  473. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  474. struct sde_plane_state *pstate, uint64_t fd)
  475. {
  476. if (!psde || !pstate) {
  477. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  478. !psde, !pstate);
  479. return;
  480. }
  481. /* clear previous reference */
  482. if (pstate->input_fence)
  483. sde_sync_put(pstate->input_fence);
  484. /* get fence pointer for later */
  485. if (fd == 0)
  486. pstate->input_fence = NULL;
  487. else
  488. pstate->input_fence = sde_sync_get(fd);
  489. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  490. }
  491. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  492. {
  493. struct sde_plane *psde;
  494. struct sde_plane_state *pstate;
  495. uint32_t prefix;
  496. void *input_fence;
  497. int ret = -EINVAL;
  498. signed long rc;
  499. if (!plane) {
  500. SDE_ERROR("invalid plane\n");
  501. } else if (!plane->state) {
  502. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  503. } else {
  504. psde = to_sde_plane(plane);
  505. pstate = to_sde_plane_state(plane->state);
  506. input_fence = pstate->input_fence;
  507. if (input_fence) {
  508. prefix = sde_sync_get_name_prefix(input_fence);
  509. rc = sde_sync_wait(input_fence, wait_ms);
  510. switch (rc) {
  511. case 0:
  512. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  513. wait_ms, prefix, sde_plane_get_property(pstate,
  514. PLANE_PROP_INPUT_FENCE));
  515. psde->is_error = true;
  516. sde_kms_timeline_status(plane->dev);
  517. ret = -ETIMEDOUT;
  518. break;
  519. case -ERESTARTSYS:
  520. SDE_ERROR_PLANE(psde,
  521. "%ums wait interrupted on %08X\n",
  522. wait_ms, prefix);
  523. psde->is_error = true;
  524. ret = -ERESTARTSYS;
  525. break;
  526. case -EINVAL:
  527. SDE_ERROR_PLANE(psde,
  528. "invalid fence param for %08X\n",
  529. prefix);
  530. psde->is_error = true;
  531. ret = -EINVAL;
  532. break;
  533. default:
  534. SDE_DEBUG_PLANE(psde, "signaled\n");
  535. ret = 0;
  536. break;
  537. }
  538. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  539. } else {
  540. ret = 0;
  541. }
  542. }
  543. return ret;
  544. }
  545. /**
  546. * _sde_plane_get_aspace: gets the address space based on the
  547. * fb_translation mode property
  548. */
  549. static int _sde_plane_get_aspace(
  550. struct sde_plane *psde,
  551. struct sde_plane_state *pstate,
  552. struct msm_gem_address_space **aspace)
  553. {
  554. struct sde_kms *kms;
  555. int mode;
  556. if (!psde || !pstate || !aspace) {
  557. SDE_ERROR("invalid parameters\n");
  558. return -EINVAL;
  559. }
  560. kms = _sde_plane_get_kms(&psde->base);
  561. if (!kms) {
  562. SDE_ERROR("invalid kms\n");
  563. return -EINVAL;
  564. }
  565. mode = sde_plane_get_property(pstate,
  566. PLANE_PROP_FB_TRANSLATION_MODE);
  567. switch (mode) {
  568. case SDE_DRM_FB_NON_SEC:
  569. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  570. if (!aspace)
  571. return -EINVAL;
  572. break;
  573. case SDE_DRM_FB_SEC:
  574. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  575. if (!aspace)
  576. return -EINVAL;
  577. break;
  578. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  579. case SDE_DRM_FB_SEC_DIR_TRANS:
  580. *aspace = NULL;
  581. break;
  582. default:
  583. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  584. return -EFAULT;
  585. }
  586. return 0;
  587. }
  588. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  589. struct sde_plane_state *pstate,
  590. struct sde_hw_pipe_cfg *pipe_cfg,
  591. struct drm_framebuffer *fb)
  592. {
  593. struct sde_plane *psde;
  594. struct msm_gem_address_space *aspace = NULL;
  595. int ret, mode;
  596. bool secure = false;
  597. if (!plane || !pstate || !pipe_cfg || !fb) {
  598. SDE_ERROR(
  599. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  600. !plane, !pstate, !pipe_cfg, !fb);
  601. return;
  602. }
  603. psde = to_sde_plane(plane);
  604. if (!psde->pipe_hw) {
  605. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  606. return;
  607. }
  608. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  609. if (ret) {
  610. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  611. return;
  612. }
  613. /*
  614. * framebuffer prepare is deferred for prepare_fb calls that
  615. * happen during the transition from secure to non-secure.
  616. * Handle the prepare at this point for such cases. This can be
  617. * expected for one or two frames during the transition.
  618. */
  619. if (aspace && pstate->defer_prepare_fb) {
  620. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  621. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  622. if (ret) {
  623. SDE_ERROR_PLANE(psde,
  624. "failed to prepare framebuffer %d\n", ret);
  625. return;
  626. }
  627. pstate->defer_prepare_fb = false;
  628. }
  629. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  630. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  631. secure = true;
  632. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  633. if (ret == -EAGAIN)
  634. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  635. else if (ret) {
  636. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  637. /*
  638. * Force solid fill color on error. This is to prevent
  639. * smmu faults during secure session transition.
  640. */
  641. psde->is_error = true;
  642. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  643. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  644. pipe_cfg->layout.width,
  645. pipe_cfg->layout.height,
  646. pipe_cfg->layout.plane_addr[0],
  647. pipe_cfg->layout.plane_size[0],
  648. pipe_cfg->layout.plane_addr[1],
  649. pipe_cfg->layout.plane_size[1],
  650. pipe_cfg->layout.plane_addr[2],
  651. pipe_cfg->layout.plane_size[2],
  652. pipe_cfg->layout.plane_addr[3],
  653. pipe_cfg->layout.plane_size[3],
  654. pstate->multirect_index,
  655. secure);
  656. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  657. pstate->multirect_index);
  658. }
  659. }
  660. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  661. struct sde_plane_state *pstate)
  662. {
  663. struct sde_hw_scaler3_cfg *cfg;
  664. int ret = 0;
  665. if (!psde || !pstate) {
  666. SDE_ERROR("invalid args\n");
  667. return -EINVAL;
  668. }
  669. cfg = &pstate->scaler3_cfg;
  670. cfg->dir_lut = msm_property_get_blob(
  671. &psde->property_info,
  672. &pstate->property_state, &cfg->dir_len,
  673. PLANE_PROP_SCALER_LUT_ED);
  674. cfg->cir_lut = msm_property_get_blob(
  675. &psde->property_info,
  676. &pstate->property_state, &cfg->cir_len,
  677. PLANE_PROP_SCALER_LUT_CIR);
  678. cfg->sep_lut = msm_property_get_blob(
  679. &psde->property_info,
  680. &pstate->property_state, &cfg->sep_len,
  681. PLANE_PROP_SCALER_LUT_SEP);
  682. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  683. ret = -ENODATA;
  684. return ret;
  685. }
  686. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  687. struct sde_plane_state *pstate)
  688. {
  689. struct sde_hw_scaler3_cfg *cfg;
  690. cfg = &pstate->scaler3_cfg;
  691. cfg->sep_lut = msm_property_get_blob(
  692. &psde->property_info,
  693. &pstate->property_state, &cfg->sep_len,
  694. PLANE_PROP_SCALER_LUT_SEP);
  695. return cfg->sep_lut ? 0 : -ENODATA;
  696. }
  697. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  698. struct sde_plane_state *pstate, const struct sde_format *fmt,
  699. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  700. {
  701. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  702. struct sde_hw_scaler3_cfg *scale_cfg;
  703. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  704. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  705. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  706. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  707. chroma_subsmpl_h, chroma_subsmpl_v);
  708. return;
  709. }
  710. scale_cfg = &pstate->scaler3_cfg;
  711. src_w = psde->pipe_cfg.src_rect.w;
  712. src_h = psde->pipe_cfg.src_rect.h;
  713. dst_w = psde->pipe_cfg.dst_rect.w;
  714. dst_h = psde->pipe_cfg.dst_rect.h;
  715. memset(scale_cfg, 0, sizeof(*scale_cfg));
  716. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  717. /*
  718. * For inline rotation cases, scaler config is post-rotation,
  719. * so swap the dimensions here. However, pixel extension will
  720. * need pre-rotation settings, this will be corrected below
  721. * when calculating pixel extension settings.
  722. */
  723. if (inline_rotation)
  724. swap(src_w, src_h);
  725. decimated = DECIMATED_DIMENSION(src_w,
  726. psde->pipe_cfg.horz_decimation);
  727. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  728. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  729. decimated = DECIMATED_DIMENSION(src_h,
  730. psde->pipe_cfg.vert_decimation);
  731. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  732. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  733. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  734. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  735. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  736. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  738. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  739. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  740. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  741. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  742. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  744. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  745. for (i = 0; i < SDE_MAX_PLANES; i++) {
  746. /*
  747. * For inline rotation cases with pre-downscaling enabled
  748. * set x pre-downscale value if required. Only x direction
  749. * is currently supported. Use src_h as values have been swapped
  750. * and x direction corresponds to height value.
  751. */
  752. src_h_pre_down = src_h;
  753. if (pre_down_supported && inline_rotation) {
  754. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  755. src_h_pre_down = src_h / 2;
  756. }
  757. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  758. psde->pipe_cfg.horz_decimation);
  759. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  760. psde->pipe_cfg.vert_decimation);
  761. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  762. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  763. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  764. }
  765. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  766. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  767. /* For pixel extension we need the pre-rotated orientation */
  768. if (inline_rotation) {
  769. pstate->pixel_ext.num_ext_pxls_top[i] =
  770. scale_cfg->src_width[i];
  771. pstate->pixel_ext.num_ext_pxls_left[i] =
  772. scale_cfg->src_height[i];
  773. } else {
  774. pstate->pixel_ext.num_ext_pxls_top[i] =
  775. scale_cfg->src_height[i];
  776. pstate->pixel_ext.num_ext_pxls_left[i] =
  777. scale_cfg->src_width[i];
  778. }
  779. }
  780. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  781. && (src_w == dst_w) && !inline_rotation) ||
  782. pstate->multirect_mode)
  783. return;
  784. SDE_DEBUG_PLANE(psde,
  785. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  786. src_w, src_h, dst_w, dst_h,
  787. chroma_subsmpl_v, chroma_subsmpl_h,
  788. fmt->base.pixel_format);
  789. scale_cfg->dst_width = dst_w;
  790. scale_cfg->dst_height = dst_h;
  791. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  792. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  793. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  794. scale_cfg->lut_flag = 0;
  795. scale_cfg->blend_cfg = 1;
  796. scale_cfg->enable = 1;
  797. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  798. }
  799. /**
  800. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  801. * @psde: Pointer to SDE plane object
  802. * @src: Source size
  803. * @dst: Destination size
  804. * @phase_steps: Pointer to output array for phase steps
  805. * @filter: Pointer to output array for filter type
  806. * @fmt: Pointer to format definition
  807. * @chroma_subsampling: Subsampling amount for chroma channel
  808. *
  809. * Returns: 0 on success
  810. */
  811. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  812. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  813. enum sde_hw_filter *filter, const struct sde_format *fmt,
  814. uint32_t chroma_subsampling)
  815. {
  816. if (!psde || !phase_steps || !filter || !fmt) {
  817. SDE_ERROR(
  818. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  819. !psde, !phase_steps, !filter, !fmt);
  820. return -EINVAL;
  821. }
  822. /* calculate phase steps, leave init phase as zero */
  823. phase_steps[SDE_SSPP_COMP_0] =
  824. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  825. phase_steps[SDE_SSPP_COMP_1_2] =
  826. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  827. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  828. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  829. /* calculate scaler config, if necessary */
  830. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  831. filter[SDE_SSPP_COMP_3] =
  832. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  833. SDE_SCALE_FILTER_PCMN;
  834. if (SDE_FORMAT_IS_YUV(fmt)) {
  835. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  836. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  837. } else {
  838. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  839. filter[SDE_SSPP_COMP_1_2] =
  840. SDE_SCALE_FILTER_NEAREST;
  841. }
  842. } else {
  843. /* disable scaler */
  844. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  845. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  846. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  847. }
  848. return 0;
  849. }
  850. /**
  851. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  852. * @psde: Pointer to SDE plane object
  853. * @src: Source size
  854. * @dst: Destination size
  855. * @decimated_src: Source size after decimation, if any
  856. * @phase_steps: Pointer to output array for phase steps
  857. * @out_src: Output array for pixel extension values
  858. * @out_edge1: Output array for pixel extension first edge
  859. * @out_edge2: Output array for pixel extension second edge
  860. * @filter: Pointer to array for filter type
  861. * @fmt: Pointer to format definition
  862. * @chroma_subsampling: Subsampling amount for chroma channel
  863. * @post_compare: Whether to chroma subsampled source size for comparisions
  864. */
  865. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  866. uint32_t src, uint32_t dst, uint32_t decimated_src,
  867. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  868. int *out_edge2, enum sde_hw_filter *filter,
  869. const struct sde_format *fmt, uint32_t chroma_subsampling,
  870. bool post_compare)
  871. {
  872. int64_t edge1, edge2, caf;
  873. uint32_t src_work;
  874. int i, tmp;
  875. if (psde && phase_steps && out_src && out_edge1 &&
  876. out_edge2 && filter && fmt) {
  877. /* handle CAF for YUV formats */
  878. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  879. caf = PHASE_STEP_UNIT_SCALE;
  880. else
  881. caf = 0;
  882. for (i = 0; i < SDE_MAX_PLANES; i++) {
  883. src_work = decimated_src;
  884. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  885. src_work /= chroma_subsampling;
  886. if (post_compare)
  887. src = src_work;
  888. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  889. /* unity */
  890. edge1 = 0;
  891. edge2 = 0;
  892. } else if (dst >= src) {
  893. /* upscale */
  894. edge1 = (1 << PHASE_RESIDUAL);
  895. edge1 -= caf;
  896. edge2 = (1 << PHASE_RESIDUAL);
  897. edge2 += (dst - 1) * *(phase_steps + i);
  898. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  899. edge2 += caf;
  900. edge2 = -(edge2);
  901. } else {
  902. /* downscale */
  903. edge1 = 0;
  904. edge2 = (dst - 1) * *(phase_steps + i);
  905. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  906. edge2 += *(phase_steps + i);
  907. edge2 = -(edge2);
  908. }
  909. /* only enable CAF for luma plane */
  910. caf = 0;
  911. /* populate output arrays */
  912. *(out_src + i) = src_work;
  913. /* edge updates taken from __pxl_extn_helper */
  914. if (edge1 >= 0) {
  915. tmp = (uint32_t)edge1;
  916. tmp >>= PHASE_STEP_SHIFT;
  917. *(out_edge1 + i) = -tmp;
  918. } else {
  919. tmp = (uint32_t)(-edge1);
  920. *(out_edge1 + i) =
  921. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  922. PHASE_STEP_SHIFT;
  923. }
  924. if (edge2 >= 0) {
  925. tmp = (uint32_t)edge2;
  926. tmp >>= PHASE_STEP_SHIFT;
  927. *(out_edge2 + i) = -tmp;
  928. } else {
  929. tmp = (uint32_t)(-edge2);
  930. *(out_edge2 + i) =
  931. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  932. PHASE_STEP_SHIFT;
  933. }
  934. }
  935. }
  936. }
  937. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  938. {
  939. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  940. {
  941. /* S15.16 format */
  942. 0x00012A00, 0x00000000, 0x00019880,
  943. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  944. 0x00012A00, 0x00020480, 0x00000000,
  945. },
  946. /* signed bias */
  947. { 0xfff0, 0xff80, 0xff80,},
  948. { 0x0, 0x0, 0x0,},
  949. /* unsigned clamp */
  950. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  951. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  952. };
  953. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  954. {
  955. /* S15.16 format */
  956. 0x00012A00, 0x00000000, 0x00019880,
  957. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  958. 0x00012A00, 0x00020480, 0x00000000,
  959. },
  960. /* signed bias */
  961. { 0xffc0, 0xfe00, 0xfe00,},
  962. { 0x0, 0x0, 0x0,},
  963. /* unsigned clamp */
  964. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  965. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  966. };
  967. if (!psde) {
  968. SDE_ERROR("invalid plane\n");
  969. return;
  970. }
  971. /* revert to kernel default if override not available */
  972. if (psde->csc_usr_ptr)
  973. psde->csc_ptr = psde->csc_usr_ptr;
  974. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  975. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  976. else
  977. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  978. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  979. psde->csc_ptr->csc_mv[0],
  980. psde->csc_ptr->csc_mv[1],
  981. psde->csc_ptr->csc_mv[2]);
  982. }
  983. static void sde_color_process_plane_setup(struct drm_plane *plane)
  984. {
  985. struct sde_plane *psde;
  986. struct sde_plane_state *pstate;
  987. uint32_t hue, saturation, value, contrast;
  988. struct drm_msm_memcol *memcol = NULL;
  989. struct drm_msm_3d_gamut *vig_gamut = NULL;
  990. struct drm_msm_igc_lut *igc = NULL;
  991. struct drm_msm_pgc_lut *gc = NULL;
  992. size_t memcol_sz = 0, size = 0;
  993. struct sde_hw_cp_cfg hw_cfg = {};
  994. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  995. bool fp16_igc, fp16_unmult;
  996. struct drm_msm_fp16_gc *fp16_gc = NULL;
  997. struct drm_msm_fp16_csc *fp16_csc = NULL;
  998. psde = to_sde_plane(plane);
  999. pstate = to_sde_plane_state(plane->state);
  1000. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1001. if (psde->pipe_hw->ops.setup_pa_hue)
  1002. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1003. saturation = (uint32_t) sde_plane_get_property(pstate,
  1004. PLANE_PROP_SATURATION_ADJUST);
  1005. if (psde->pipe_hw->ops.setup_pa_sat)
  1006. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1007. value = (uint32_t) sde_plane_get_property(pstate,
  1008. PLANE_PROP_VALUE_ADJUST);
  1009. if (psde->pipe_hw->ops.setup_pa_val)
  1010. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1011. contrast = (uint32_t) sde_plane_get_property(pstate,
  1012. PLANE_PROP_CONTRAST_ADJUST);
  1013. if (psde->pipe_hw->ops.setup_pa_cont)
  1014. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1015. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1016. /* Skin memory color setup */
  1017. memcol = msm_property_get_blob(&psde->property_info,
  1018. &pstate->property_state,
  1019. &memcol_sz,
  1020. PLANE_PROP_SKIN_COLOR);
  1021. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1022. MEMCOLOR_SKIN, memcol);
  1023. /* Sky memory color setup */
  1024. memcol = msm_property_get_blob(&psde->property_info,
  1025. &pstate->property_state,
  1026. &memcol_sz,
  1027. PLANE_PROP_SKY_COLOR);
  1028. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1029. MEMCOLOR_SKY, memcol);
  1030. /* Foliage memory color setup */
  1031. memcol = msm_property_get_blob(&psde->property_info,
  1032. &pstate->property_state,
  1033. &memcol_sz,
  1034. PLANE_PROP_FOLIAGE_COLOR);
  1035. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1036. MEMCOLOR_FOLIAGE, memcol);
  1037. }
  1038. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1039. psde->pipe_hw->ops.setup_vig_gamut) {
  1040. vig_gamut = msm_property_get_blob(&psde->property_info,
  1041. &pstate->property_state,
  1042. &size,
  1043. PLANE_PROP_VIG_GAMUT);
  1044. hw_cfg.last_feature = 0;
  1045. hw_cfg.ctl = ctl;
  1046. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1047. hw_cfg.payload = vig_gamut;
  1048. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1049. }
  1050. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1051. psde->pipe_hw->ops.setup_vig_igc) {
  1052. igc = msm_property_get_blob(&psde->property_info,
  1053. &pstate->property_state,
  1054. &size,
  1055. PLANE_PROP_VIG_IGC);
  1056. hw_cfg.last_feature = 0;
  1057. hw_cfg.ctl = ctl;
  1058. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1059. hw_cfg.payload = igc;
  1060. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1061. }
  1062. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1063. psde->pipe_hw->ops.setup_dma_igc) {
  1064. igc = msm_property_get_blob(&psde->property_info,
  1065. &pstate->property_state,
  1066. &size,
  1067. PLANE_PROP_DMA_IGC);
  1068. hw_cfg.last_feature = 0;
  1069. hw_cfg.ctl = ctl;
  1070. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1071. hw_cfg.payload = igc;
  1072. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1073. pstate->multirect_index);
  1074. }
  1075. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1076. psde->pipe_hw->ops.setup_dma_gc) {
  1077. gc = msm_property_get_blob(&psde->property_info,
  1078. &pstate->property_state,
  1079. &size,
  1080. PLANE_PROP_DMA_GC);
  1081. hw_cfg.last_feature = 0;
  1082. hw_cfg.ctl = ctl;
  1083. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1084. hw_cfg.payload = gc;
  1085. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1086. pstate->multirect_index);
  1087. }
  1088. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1089. psde->pipe_hw->ops.setup_fp16_igc) {
  1090. fp16_igc = !!sde_plane_get_property(pstate,
  1091. PLANE_PROP_FP16_IGC);
  1092. hw_cfg.last_feature = 0;
  1093. hw_cfg.ctl = ctl;
  1094. hw_cfg.len = sizeof(bool);
  1095. hw_cfg.payload = &fp16_igc;
  1096. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1097. pstate->multirect_index, &hw_cfg);
  1098. }
  1099. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1100. psde->pipe_hw->ops.setup_fp16_gc) {
  1101. fp16_gc = msm_property_get_blob(&psde->property_info,
  1102. &pstate->property_state,
  1103. &size,
  1104. PLANE_PROP_FP16_GC);
  1105. hw_cfg.last_feature = 0;
  1106. hw_cfg.ctl = ctl;
  1107. hw_cfg.len = size;
  1108. hw_cfg.payload = fp16_gc;
  1109. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1110. pstate->multirect_index, &hw_cfg);
  1111. }
  1112. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1113. psde->pipe_hw->ops.setup_fp16_csc) {
  1114. fp16_csc = msm_property_get_blob(&psde->property_info,
  1115. &pstate->property_state,
  1116. &size,
  1117. PLANE_PROP_FP16_CSC);
  1118. hw_cfg.last_feature = 0;
  1119. hw_cfg.ctl = ctl;
  1120. hw_cfg.len = size;
  1121. hw_cfg.payload = fp16_csc;
  1122. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1123. pstate->multirect_index, &hw_cfg);
  1124. }
  1125. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1126. psde->pipe_hw->ops.setup_fp16_unmult) {
  1127. fp16_unmult = !!sde_plane_get_property(pstate,
  1128. PLANE_PROP_FP16_UNMULT);
  1129. hw_cfg.last_feature = 0;
  1130. hw_cfg.ctl = ctl;
  1131. hw_cfg.len = sizeof(bool);
  1132. hw_cfg.payload = &fp16_unmult;
  1133. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1134. pstate->multirect_index, &hw_cfg);
  1135. }
  1136. }
  1137. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1138. struct sde_plane_state *pstate,
  1139. const struct sde_format *fmt, bool color_fill)
  1140. {
  1141. struct sde_hw_pixel_ext *pe;
  1142. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1143. const struct drm_format_info *info = NULL;
  1144. if (!psde || !fmt || !pstate) {
  1145. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1146. !psde, !fmt, !pstate);
  1147. return;
  1148. }
  1149. info = drm_format_info(fmt->base.pixel_format);
  1150. pe = &pstate->pixel_ext;
  1151. psde->pipe_cfg.horz_decimation =
  1152. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1153. psde->pipe_cfg.vert_decimation =
  1154. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1155. /* don't chroma subsample if decimating */
  1156. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1157. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1158. /* update scaler */
  1159. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1160. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1161. int rc = -EINVAL;
  1162. if (!color_fill && !psde->debugfs_default_scale)
  1163. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1164. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1165. _sde_plane_setup_scaler3_lut(psde, pstate);
  1166. if (rc || pstate->scaler_check_state !=
  1167. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1168. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1169. pstate->scaler_check_state,
  1170. psde->debugfs_default_scale, rc,
  1171. psde->pipe_cfg.src_rect.w,
  1172. psde->pipe_cfg.src_rect.h,
  1173. psde->pipe_cfg.dst_rect.w,
  1174. psde->pipe_cfg.dst_rect.h,
  1175. pstate->multirect_mode);
  1176. /* calculate default config for QSEED3 */
  1177. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1178. chroma_subsmpl_h, chroma_subsmpl_v);
  1179. }
  1180. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1181. color_fill || psde->debugfs_default_scale) {
  1182. uint32_t deci_dim, i;
  1183. /* calculate default configuration for QSEED2 */
  1184. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1185. SDE_DEBUG_PLANE(psde, "default config\n");
  1186. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1187. psde->pipe_cfg.horz_decimation);
  1188. _sde_plane_setup_scaler2(psde,
  1189. deci_dim,
  1190. psde->pipe_cfg.dst_rect.w,
  1191. pe->phase_step_x,
  1192. pe->horz_filter, fmt, chroma_subsmpl_h);
  1193. if (SDE_FORMAT_IS_YUV(fmt))
  1194. deci_dim &= ~0x1;
  1195. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1196. psde->pipe_cfg.dst_rect.w, deci_dim,
  1197. pe->phase_step_x,
  1198. pe->roi_w,
  1199. pe->num_ext_pxls_left,
  1200. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1201. chroma_subsmpl_h, 0);
  1202. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1203. psde->pipe_cfg.vert_decimation);
  1204. _sde_plane_setup_scaler2(psde,
  1205. deci_dim,
  1206. psde->pipe_cfg.dst_rect.h,
  1207. pe->phase_step_y,
  1208. pe->vert_filter, fmt, chroma_subsmpl_v);
  1209. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1210. psde->pipe_cfg.dst_rect.h, deci_dim,
  1211. pe->phase_step_y,
  1212. pe->roi_h,
  1213. pe->num_ext_pxls_top,
  1214. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1215. chroma_subsmpl_v, 1);
  1216. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1217. if (pe->num_ext_pxls_left[i] >= 0)
  1218. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1219. else
  1220. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1221. if (pe->num_ext_pxls_right[i] >= 0)
  1222. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1223. else
  1224. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1225. if (pe->num_ext_pxls_top[i] >= 0)
  1226. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1227. else
  1228. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1229. if (pe->num_ext_pxls_btm[i] >= 0)
  1230. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1231. else
  1232. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1233. }
  1234. }
  1235. if (psde->pipe_hw->ops.setup_pre_downscale)
  1236. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1237. &pstate->pre_down);
  1238. }
  1239. /**
  1240. * _sde_plane_color_fill - enables color fill on plane
  1241. * @psde: Pointer to SDE plane object
  1242. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1243. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1244. * Returns: 0 on success
  1245. */
  1246. static int _sde_plane_color_fill(struct sde_plane *psde,
  1247. uint32_t color, uint32_t alpha)
  1248. {
  1249. const struct sde_format *fmt;
  1250. const struct drm_plane *plane;
  1251. struct sde_plane_state *pstate;
  1252. bool blend_enable = true;
  1253. if (!psde || !psde->base.state) {
  1254. SDE_ERROR("invalid plane\n");
  1255. return -EINVAL;
  1256. }
  1257. if (!psde->pipe_hw) {
  1258. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1259. return -EINVAL;
  1260. }
  1261. plane = &psde->base;
  1262. pstate = to_sde_plane_state(plane->state);
  1263. SDE_DEBUG_PLANE(psde, "\n");
  1264. /*
  1265. * select fill format to match user property expectation,
  1266. * h/w only supports RGB variants
  1267. */
  1268. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1269. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1270. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1271. /* update sspp */
  1272. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1273. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1274. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1275. pstate->multirect_index);
  1276. /* override scaler/decimation if solid fill */
  1277. psde->pipe_cfg.src_rect.x = 0;
  1278. psde->pipe_cfg.src_rect.y = 0;
  1279. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1280. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1281. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1282. if (psde->pipe_hw->ops.setup_format)
  1283. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1284. fmt, blend_enable,
  1285. SDE_SSPP_SOLID_FILL,
  1286. pstate->multirect_index);
  1287. if (psde->pipe_hw->ops.setup_rects)
  1288. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1289. &psde->pipe_cfg,
  1290. pstate->multirect_index);
  1291. if (psde->pipe_hw->ops.setup_pe)
  1292. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1293. &pstate->pixel_ext);
  1294. if (psde->pipe_hw->ops.setup_scaler &&
  1295. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1296. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1297. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1298. &psde->pipe_cfg, &pstate->pixel_ext,
  1299. &pstate->scaler3_cfg);
  1300. }
  1301. }
  1302. return 0;
  1303. }
  1304. /**
  1305. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1306. * @plane: Pointer to drm plane
  1307. * @state: Pointer to drm plane state to be validated
  1308. * return: 0 if success; error code otherwise
  1309. */
  1310. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1311. struct drm_plane_state *state)
  1312. {
  1313. struct sde_plane *psde;
  1314. struct sde_plane_state *pstate, *old_pstate;
  1315. int ret = 0;
  1316. u32 rotation;
  1317. if (!plane || !state) {
  1318. SDE_ERROR("invalid plane/state\n");
  1319. return -EINVAL;
  1320. }
  1321. psde = to_sde_plane(plane);
  1322. pstate = to_sde_plane_state(state);
  1323. old_pstate = to_sde_plane_state(plane->state);
  1324. /* check inline rotation and simplify the transform */
  1325. rotation = drm_rotation_simplify(
  1326. state->rotation,
  1327. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1328. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1329. if ((rotation & DRM_MODE_ROTATE_180) ||
  1330. (rotation & DRM_MODE_ROTATE_270)) {
  1331. SDE_ERROR_PLANE(psde,
  1332. "invalid rotation transform must be simplified 0x%x\n",
  1333. rotation);
  1334. ret = -EINVAL;
  1335. goto exit;
  1336. }
  1337. if (rotation & DRM_MODE_ROTATE_90) {
  1338. struct msm_drm_private *priv = plane->dev->dev_private;
  1339. struct sde_kms *sde_kms;
  1340. const struct msm_format *msm_fmt;
  1341. const struct sde_format *fmt;
  1342. struct sde_rect src;
  1343. bool q16_data = true;
  1344. POPULATE_RECT(&src, state->src_x, state->src_y,
  1345. state->src_w, state->src_h, q16_data);
  1346. /*
  1347. * DRM framework expects rotation flag in counter-clockwise
  1348. * direction and the HW expects in clockwise direction.
  1349. * Flip the flags to match with HW.
  1350. */
  1351. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1352. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1353. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1354. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1355. !psde->pipe_sblk->in_rot_maxheight ||
  1356. !psde->pipe_sblk->in_rot_format_list ||
  1357. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1358. SDE_ERROR_PLANE(psde,
  1359. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1360. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1361. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1362. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1363. !psde->pipe_sblk->in_rot_format_list,
  1364. !psde->pipe_sblk->in_rot_maxheight,
  1365. psde->features);
  1366. ret = -EINVAL;
  1367. goto exit;
  1368. }
  1369. /* check for valid height */
  1370. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1371. SDE_ERROR_PLANE(psde,
  1372. "invalid height for inline rot:%d max:%d\n",
  1373. src.h, psde->pipe_sblk->in_rot_maxheight);
  1374. ret = -EINVAL;
  1375. goto exit;
  1376. }
  1377. if (!sde_plane_enabled(state))
  1378. goto exit;
  1379. /* check for valid formats supported by inline rot */
  1380. sde_kms = to_sde_kms(priv->kms);
  1381. msm_fmt = msm_framebuffer_format(state->fb);
  1382. fmt = to_sde_format(msm_fmt);
  1383. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1384. psde->pipe_sblk->in_rot_format_list);
  1385. }
  1386. exit:
  1387. pstate->rotation = rotation;
  1388. return ret;
  1389. }
  1390. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1391. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1392. {
  1393. struct sde_plane *psde;
  1394. struct msm_drm_private *priv;
  1395. struct sde_vbif_set_xin_halt_params halt_params;
  1396. if (!plane || !plane->dev) {
  1397. SDE_ERROR("invalid arguments\n");
  1398. return false;
  1399. }
  1400. psde = to_sde_plane(plane);
  1401. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1402. SDE_ERROR("invalid pipe reference\n");
  1403. return false;
  1404. }
  1405. priv = plane->dev->dev_private;
  1406. if (!priv || !priv->kms) {
  1407. SDE_ERROR("invalid KMS reference\n");
  1408. return false;
  1409. }
  1410. memset(&halt_params, 0, sizeof(halt_params));
  1411. halt_params.vbif_idx = VBIF_RT;
  1412. halt_params.xin_id = xin_id;
  1413. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1414. halt_params.forced_on = halt_forced_clk;
  1415. halt_params.enable = enable;
  1416. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1417. }
  1418. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1419. {
  1420. struct sde_plane *psde;
  1421. if (!plane) {
  1422. SDE_ERROR("invalid plane\n");
  1423. return;
  1424. }
  1425. psde = to_sde_plane(plane);
  1426. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1427. SDE_ERROR("invalid pipe reference\n");
  1428. return;
  1429. }
  1430. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1431. psde->xin_halt_forced_clk =
  1432. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1433. psde->xin_halt_forced_clk, enable);
  1434. }
  1435. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1436. struct drm_crtc *crtc)
  1437. {
  1438. struct sde_plane *psde;
  1439. if (!plane || !crtc) {
  1440. SDE_ERROR("invalid plane/crtc\n");
  1441. return;
  1442. }
  1443. psde = to_sde_plane(plane);
  1444. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1445. return;
  1446. /* do all VBIF programming for the sec-ui allowed SSPP */
  1447. _sde_plane_set_qos_remap(plane);
  1448. _sde_plane_set_ot_limit(plane, crtc);
  1449. }
  1450. /**
  1451. * sde_plane_rot_install_properties - install plane rotator properties
  1452. * @plane: Pointer to drm plane
  1453. * @catalog: Pointer to mdss configuration
  1454. * return: none
  1455. */
  1456. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1457. struct sde_mdss_cfg *catalog)
  1458. {
  1459. struct sde_plane *psde = to_sde_plane(plane);
  1460. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1461. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1462. int ret = 0;
  1463. if (!plane || !psde) {
  1464. SDE_ERROR("invalid plane\n");
  1465. return;
  1466. } else if (!catalog) {
  1467. SDE_ERROR("invalid catalog\n");
  1468. return;
  1469. }
  1470. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1471. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1472. ret = drm_plane_create_rotation_property(plane,
  1473. DRM_MODE_ROTATE_0, supported_rotations);
  1474. if (ret) {
  1475. DRM_ERROR("create rotation property failed: %d\n", ret);
  1476. return;
  1477. }
  1478. }
  1479. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1480. {
  1481. struct sde_plane_state *pstate;
  1482. if (!drm_state)
  1483. return;
  1484. pstate = to_sde_plane_state(drm_state);
  1485. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1486. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1487. }
  1488. /**
  1489. * multi_rect validate API allows to validate only R0 and R1 RECT
  1490. * passing for each plane. Client of this API must not pass multiple
  1491. * plane which are not sharing same XIN client. Such calls will fail
  1492. * even though kernel client is passing valid multirect configuration.
  1493. */
  1494. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1495. {
  1496. struct sde_plane_state *pstate[R_MAX];
  1497. const struct drm_plane_state *drm_state[R_MAX];
  1498. struct sde_rect src[R_MAX], dst[R_MAX];
  1499. struct sde_plane *sde_plane[R_MAX];
  1500. const struct sde_format *fmt[R_MAX];
  1501. int xin_id[R_MAX];
  1502. bool q16_data = true;
  1503. int i, j, buffer_lines, width_threshold[R_MAX];
  1504. unsigned int max_tile_height = 1;
  1505. bool parallel_fetch_qualified = true;
  1506. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1507. const struct msm_format *msm_fmt;
  1508. bool const_alpha_enable = true;
  1509. for (i = 0; i < R_MAX; i++) {
  1510. drm_state[i] = i ? plane->r1 : plane->r0;
  1511. if (!drm_state[i]) {
  1512. SDE_ERROR("drm plane state is NULL\n");
  1513. return -EINVAL;
  1514. }
  1515. pstate[i] = to_sde_plane_state(drm_state[i]);
  1516. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1517. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1518. for (j = 0; j < i; j++) {
  1519. if (xin_id[i] != xin_id[j]) {
  1520. SDE_ERROR_PLANE(sde_plane[i],
  1521. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1522. j, xin_id[j], i, xin_id[i]);
  1523. return -EINVAL;
  1524. }
  1525. }
  1526. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1527. if (!msm_fmt) {
  1528. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1529. return -EINVAL;
  1530. }
  1531. fmt[i] = to_sde_format(msm_fmt);
  1532. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1533. (fmt[i]->tile_height > max_tile_height))
  1534. max_tile_height = fmt[i]->tile_height;
  1535. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1536. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1537. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1538. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1539. drm_state[i]->crtc_h, !q16_data);
  1540. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1541. SDE_ERROR_PLANE(sde_plane[i],
  1542. "scaling is not supported in multirect mode\n");
  1543. return -EINVAL;
  1544. }
  1545. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1546. SDE_ERROR_PLANE(sde_plane[i],
  1547. "inline rotation is not supported in mulirect mode\n");
  1548. return -EINVAL;
  1549. }
  1550. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1551. SDE_ERROR_PLANE(sde_plane[i],
  1552. "Unsupported format for multirect mode\n");
  1553. return -EINVAL;
  1554. }
  1555. /**
  1556. * SSPP PD_MEM is split half - one for each RECT.
  1557. * Tiled formats need 5 lines of buffering while fetching
  1558. * whereas linear formats need only 2 lines.
  1559. * So we cannot support more than half of the supported SSPP
  1560. * width for tiled formats.
  1561. */
  1562. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1563. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1564. width_threshold[i] /= 2;
  1565. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1566. parallel_fetch_qualified = false;
  1567. if (sde_plane[i]->is_virtual)
  1568. mode = sde_plane_get_property(pstate[i],
  1569. PLANE_PROP_MULTIRECT_MODE);
  1570. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1571. const_alpha_enable = false;
  1572. }
  1573. buffer_lines = 2 * max_tile_height;
  1574. /**
  1575. * fallback to driver mode selection logic if client is using
  1576. * multirect plane without setting property.
  1577. *
  1578. * validate multirect mode configuration based on rectangle
  1579. */
  1580. switch (mode) {
  1581. case SDE_SSPP_MULTIRECT_NONE:
  1582. if (parallel_fetch_qualified)
  1583. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1584. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1585. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1586. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1587. else
  1588. SDE_ERROR(
  1589. "planes(%d - %d) multirect mode selection fail\n",
  1590. drm_state[R0]->plane->base.id,
  1591. drm_state[R1]->plane->base.id);
  1592. break;
  1593. case SDE_SSPP_MULTIRECT_PARALLEL:
  1594. if (!parallel_fetch_qualified) {
  1595. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1596. drm_state[R0]->plane->base.id,
  1597. width_threshold[R0], src[R0].w);
  1598. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1599. drm_state[R1]->plane->base.id,
  1600. width_threshold[R1], src[R1].w);
  1601. SDE_ERROR("parallel fetch not qualified\n");
  1602. mode = SDE_SSPP_MULTIRECT_NONE;
  1603. }
  1604. break;
  1605. case SDE_SSPP_MULTIRECT_TIME_MX:
  1606. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1607. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1608. SDE_ERROR(
  1609. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1610. buffer_lines, drm_state[R0]->plane->base.id,
  1611. dst[R0].y, dst[R0].h);
  1612. SDE_ERROR(
  1613. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1614. buffer_lines, drm_state[R1]->plane->base.id,
  1615. dst[R1].y, dst[R1].h);
  1616. SDE_ERROR("time multiplexed fetch not qualified\n");
  1617. mode = SDE_SSPP_MULTIRECT_NONE;
  1618. }
  1619. break;
  1620. default:
  1621. SDE_ERROR("bad mode:%d selection\n", mode);
  1622. mode = SDE_SSPP_MULTIRECT_NONE;
  1623. break;
  1624. }
  1625. for (i = 0; i < R_MAX; i++) {
  1626. pstate[i]->multirect_mode = mode;
  1627. pstate[i]->const_alpha_en = const_alpha_enable;
  1628. }
  1629. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1630. return -EINVAL;
  1631. if (sde_plane[R0]->is_virtual) {
  1632. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1633. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1634. } else {
  1635. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1636. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1637. }
  1638. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1639. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1640. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1641. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1642. return 0;
  1643. }
  1644. /**
  1645. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1646. * @plane: Pointer to drm plane structure
  1647. * @ctl: Pointer to hardware control driver
  1648. * @set: set if true else clear
  1649. */
  1650. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1651. bool set)
  1652. {
  1653. if (!plane || !ctl) {
  1654. SDE_ERROR("invalid parameters\n");
  1655. return;
  1656. }
  1657. if (!ctl->ops.update_bitmask_sspp) {
  1658. SDE_ERROR("invalid ops\n");
  1659. return;
  1660. }
  1661. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1662. }
  1663. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1664. struct drm_plane_state *new_state)
  1665. {
  1666. struct drm_framebuffer *fb = new_state->fb;
  1667. struct sde_plane *psde = to_sde_plane(plane);
  1668. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1669. struct sde_hw_fmt_layout layout;
  1670. struct msm_gem_address_space *aspace;
  1671. int ret;
  1672. if (!fb)
  1673. return 0;
  1674. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1675. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1676. if (ret) {
  1677. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1678. return ret;
  1679. }
  1680. /* cache aspace */
  1681. pstate->aspace = aspace;
  1682. /*
  1683. * when transitioning from secure to non-secure,
  1684. * plane->prepare_fb happens before the commit. In such case,
  1685. * defer the prepare_fb and handled it late, during the commit
  1686. * after attaching the domains as part of the transition
  1687. */
  1688. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1689. true : false;
  1690. if (pstate->defer_prepare_fb) {
  1691. SDE_EVT32(DRMID(plane), psde->pipe);
  1692. SDE_DEBUG_PLANE(psde,
  1693. "domain not attached, prepare_fb handled later\n");
  1694. return 0;
  1695. }
  1696. if (pstate->aspace && fb) {
  1697. ret = msm_framebuffer_prepare(fb,
  1698. pstate->aspace);
  1699. if (ret) {
  1700. SDE_ERROR("failed to prepare framebuffer\n");
  1701. return ret;
  1702. }
  1703. }
  1704. /* validate framebuffer layout before commit */
  1705. ret = sde_format_populate_layout(pstate->aspace,
  1706. fb, &layout);
  1707. if (ret) {
  1708. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1709. return ret;
  1710. }
  1711. return 0;
  1712. }
  1713. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1714. struct drm_plane_state *old_state)
  1715. {
  1716. struct sde_plane *psde = to_sde_plane(plane);
  1717. struct sde_plane_state *old_pstate;
  1718. if (!old_state || !old_state->fb || !plane)
  1719. return;
  1720. old_pstate = to_sde_plane_state(old_state);
  1721. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1722. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1723. }
  1724. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1725. struct drm_plane_state *state,
  1726. struct drm_plane_state *old_state)
  1727. {
  1728. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1729. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1730. struct drm_framebuffer *fb, *old_fb;
  1731. /* no need to check it again */
  1732. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1733. return;
  1734. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1735. || psde->is_error) {
  1736. SDE_DEBUG_PLANE(psde,
  1737. "enabling/disabling full modeset required\n");
  1738. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1739. } else if (to_sde_plane_state(old_state)->pending) {
  1740. SDE_DEBUG_PLANE(psde, "still pending\n");
  1741. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1742. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1743. pstate->multirect_mode != old_pstate->multirect_mode) {
  1744. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1745. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1746. } else if (state->src_w != old_state->src_w ||
  1747. state->src_h != old_state->src_h ||
  1748. state->src_x != old_state->src_x ||
  1749. state->src_y != old_state->src_y) {
  1750. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1751. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1752. } else if (state->crtc_w != old_state->crtc_w ||
  1753. state->crtc_h != old_state->crtc_h ||
  1754. state->crtc_x != old_state->crtc_x ||
  1755. state->crtc_y != old_state->crtc_y) {
  1756. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1757. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1758. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1759. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1760. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1761. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1762. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1763. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1764. } else if (pstate->rotation != old_pstate->rotation) {
  1765. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1766. pstate->rotation, old_pstate->rotation);
  1767. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1768. }
  1769. fb = state->fb;
  1770. old_fb = old_state->fb;
  1771. if (!fb || !old_fb) {
  1772. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1773. } else if ((fb->format->format != old_fb->format->format) ||
  1774. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1775. SDE_DEBUG_PLANE(psde, "format change\n");
  1776. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1777. } else {
  1778. uint64_t new_mod = fb->modifier;
  1779. uint64_t old_mod = old_fb->modifier;
  1780. uint32_t *new_pitches = fb->pitches;
  1781. uint32_t *old_pitches = old_fb->pitches;
  1782. uint32_t *new_offset = fb->offsets;
  1783. uint32_t *old_offset = old_fb->offsets;
  1784. int i;
  1785. if (new_mod != old_mod) {
  1786. SDE_DEBUG_PLANE(psde,
  1787. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1788. new_mod, old_mod);
  1789. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1790. SDE_PLANE_DIRTY_RECTS;
  1791. }
  1792. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1793. if (new_pitches[i] != old_pitches[i]) {
  1794. SDE_DEBUG_PLANE(psde,
  1795. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1796. i, old_pitches[i], new_pitches[i]);
  1797. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1798. break;
  1799. }
  1800. }
  1801. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1802. if (new_offset[i] != old_offset[i]) {
  1803. SDE_DEBUG_PLANE(psde,
  1804. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1805. i, old_offset[i], new_offset[i]);
  1806. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1807. SDE_PLANE_DIRTY_RECTS;
  1808. break;
  1809. }
  1810. }
  1811. }
  1812. }
  1813. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1814. unsigned long base_addr, u32 size)
  1815. {
  1816. int ret = -EINVAL;
  1817. u32 addr;
  1818. struct sde_plane *psde = to_sde_plane(plane);
  1819. if (!psde || !base_addr || !size) {
  1820. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1821. return ret;
  1822. }
  1823. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1824. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1825. is_sde_plane_virtual(plane));
  1826. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1827. ret = 0;
  1828. }
  1829. return ret;
  1830. }
  1831. static inline bool _sde_plane_is_pre_downscale_enabled(
  1832. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1833. {
  1834. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1835. }
  1836. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1837. struct sde_plane_state *pstate,
  1838. const struct sde_format *fmt,
  1839. uint32_t img_w, uint32_t img_h,
  1840. uint32_t src_w, uint32_t src_h,
  1841. uint32_t deci_w, uint32_t deci_h)
  1842. {
  1843. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1844. bool pre_down_en;
  1845. int i;
  1846. if (!psde || !pstate || !fmt) {
  1847. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1848. return -EINVAL;
  1849. }
  1850. if (psde->debugfs_default_scale ||
  1851. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1852. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1853. return 0;
  1854. pd_cfg = &pstate->pre_down;
  1855. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1856. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1857. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1858. uint32_t hor_req_pixels, hor_fetch_pixels;
  1859. uint32_t vert_req_pixels, vert_fetch_pixels;
  1860. uint32_t src_w_tmp, src_h_tmp;
  1861. uint32_t scaler_w, scaler_h;
  1862. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1863. bool rot;
  1864. /* re-use color plane 1's config for plane 2 */
  1865. if (i == 2)
  1866. continue;
  1867. if (pre_down_en) {
  1868. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1869. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1870. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1871. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1872. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1873. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1874. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1875. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1876. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1877. i, pre_down_ratio_x, pre_down_ratio_y);
  1878. }
  1879. src_w_tmp = src_w;
  1880. src_h_tmp = src_h;
  1881. /*
  1882. * For chroma plane, width is half for the following sub sampled
  1883. * formats. Except in case of decimation, where hardware avoids
  1884. * 1 line of decimation instead of downsampling.
  1885. */
  1886. if (i == 1) {
  1887. if (!deci_w &&
  1888. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1889. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1890. src_w_tmp >>= 1;
  1891. if (!deci_h &&
  1892. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1893. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1894. src_h_tmp >>= 1;
  1895. }
  1896. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1897. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1898. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1899. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1900. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1901. deci_w);
  1902. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1903. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1904. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1905. deci_h);
  1906. if ((hor_req_pixels != hor_fetch_pixels) ||
  1907. (hor_fetch_pixels > img_w) ||
  1908. (vert_req_pixels != vert_fetch_pixels) ||
  1909. (vert_fetch_pixels > img_h)) {
  1910. SDE_ERROR_PLANE(psde,
  1911. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1912. hor_req_pixels, vert_req_pixels,
  1913. hor_fetch_pixels, vert_fetch_pixels,
  1914. img_w, img_h);
  1915. return -EINVAL;
  1916. }
  1917. /*
  1918. * swap the scaler src width & height for inline-rotation 90
  1919. * comparison with Pixel-Extension, as PE is based on
  1920. * pre-rotation and QSEED is based on post-rotation
  1921. */
  1922. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1923. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1924. : pstate->scaler3_cfg.src_width[i];
  1925. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1926. : pstate->scaler3_cfg.src_height[i];
  1927. /*
  1928. * Alpha plane can only be scaled using bilinear or pixel
  1929. * repeat/drop, src_width and src_height are only specified
  1930. * for Y and UV plane
  1931. */
  1932. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1933. vert_req_pixels / pre_down_ratio_y !=
  1934. scaler_h)) {
  1935. SDE_ERROR_PLANE(psde,
  1936. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1937. i, pstate->pixel_ext.roi_w[i],
  1938. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1939. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1940. return -EINVAL;
  1941. }
  1942. /*
  1943. * SSPP fetch , unpack output and QSEED3 input lines need
  1944. * to match for Y plane
  1945. */
  1946. if (i == 0 &&
  1947. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1948. BIT(SDE_DRM_DEINTERLACE)) &&
  1949. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1950. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1951. SDE_ERROR_PLANE(psde,
  1952. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1953. i, pstate->pixel_ext.roi_w[i],
  1954. pstate->pixel_ext.roi_h[i],
  1955. pstate->scaler3_cfg.src_width[i],
  1956. pstate->scaler3_cfg.src_height[i],
  1957. src_w, src_h);
  1958. return -EINVAL;
  1959. }
  1960. }
  1961. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1962. return 0;
  1963. }
  1964. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1965. {
  1966. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1967. }
  1968. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1969. struct sde_plane_state *pstate, struct sde_rect *dst,
  1970. u32 src_w, u32 src_h)
  1971. {
  1972. int ret = 0;
  1973. u32 min_ratio_numer, min_ratio_denom;
  1974. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1975. bool pd_x;
  1976. bool pd_y;
  1977. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1978. return ret;
  1979. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1980. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1981. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1982. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1983. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1984. SDE_ERROR_PLANE(psde,
  1985. "hw does not support pre-downscale X: 0x%x\n",
  1986. psde->features);
  1987. ret = -EINVAL;
  1988. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1989. SDE_ERROR_PLANE(psde,
  1990. "hw does not support pre-downscale Y: 0x%x\n",
  1991. psde->features);
  1992. ret = -EINVAL;
  1993. } else if (!min_ratio_numer || !min_ratio_denom) {
  1994. SDE_ERROR_PLANE(psde,
  1995. "min downscale ratio not set! %u / %u\n",
  1996. min_ratio_numer, min_ratio_denom);
  1997. ret = -EINVAL;
  1998. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  1999. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2000. min_ratio_denom))) {
  2001. SDE_ERROR_PLANE(psde,
  2002. "failed min downscale-x check %u->%u, %u/%u\n",
  2003. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2004. ret = -EINVAL;
  2005. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2006. min_ratio_denom))) {
  2007. SDE_ERROR_PLANE(psde,
  2008. "failed min downscale-y check %u->%u, %u/%u\n",
  2009. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2010. ret = -EINVAL;
  2011. }
  2012. return ret;
  2013. }
  2014. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2015. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2016. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2017. u32 *max_numer_h, u32 *max_denom_h)
  2018. {
  2019. bool rotated, has_predown, default_scale;
  2020. const struct sde_sspp_sub_blks *sblk;
  2021. struct sde_hw_inline_pre_downscale_cfg *pd;
  2022. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2023. sblk = psde->pipe_sblk;
  2024. *max_numer_w = sblk->maxdwnscale;
  2025. *max_denom_w = 1;
  2026. *max_numer_h = sblk->maxdwnscale;
  2027. *max_denom_h = 1;
  2028. has_predown = _sde_plane_has_pre_downscale(psde);
  2029. if (has_predown)
  2030. pd = &pstate->pre_down;
  2031. default_scale = psde->debugfs_default_scale ||
  2032. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2033. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2034. /**
  2035. * Inline rotation has different max vertical downscaling limits since
  2036. * the source-width becomes the scaler's pre-downscaled source-height.
  2037. **/
  2038. if (rotated) {
  2039. if (pd != NULL && rt_client && has_predown) {
  2040. if (default_scale)
  2041. pd->pre_downscale_x_0 = (src_h >
  2042. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2043. *max_numer_h = pd->pre_downscale_x_0 ?
  2044. sblk->in_rot_maxdwnscale_rt_num :
  2045. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2046. *max_denom_h = pd->pre_downscale_x_0 ?
  2047. sblk->in_rot_maxdwnscale_rt_denom :
  2048. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2049. } else if (rt_client) {
  2050. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2051. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2052. } else {
  2053. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2054. }
  2055. }
  2056. }
  2057. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2058. struct sde_plane *psde, const struct sde_format *fmt,
  2059. struct sde_plane_state *pstate, struct sde_rect *src,
  2060. struct sde_rect *dst, u32 width, u32 height)
  2061. {
  2062. int ret = 0;
  2063. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2064. uint32_t scaler_src_w, scaler_src_h;
  2065. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2066. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2067. uint32_t max_upscale, max_linewidth;
  2068. bool inline_rotation, rt_client;
  2069. struct drm_crtc *crtc;
  2070. struct drm_crtc_state *new_cstate;
  2071. const struct sde_sspp_sub_blks *sblk;
  2072. if (!state || !state->state || !state->crtc) {
  2073. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2074. return -EINVAL;
  2075. }
  2076. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2077. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2078. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2079. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2080. /* with inline rotator, the source of the scaler is post-rotated */
  2081. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2082. if (inline_rotation) {
  2083. scaler_src_w = src_deci_h;
  2084. scaler_src_h = src_deci_w;
  2085. } else {
  2086. scaler_src_w = src_deci_w;
  2087. scaler_src_h = src_deci_h;
  2088. }
  2089. sblk = psde->pipe_sblk;
  2090. max_upscale = sblk->maxupscale;
  2091. if (inline_rotation)
  2092. max_linewidth = sblk->in_rot_maxheight;
  2093. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2094. max_linewidth = sblk->scaling_linewidth;
  2095. else
  2096. max_linewidth = sblk->maxlinewidth;
  2097. crtc = state->crtc;
  2098. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2099. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2100. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2101. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2102. &max_downscale_num_h, &max_downscale_denom_h);
  2103. /* decimation validation */
  2104. if ((deci_w || deci_h)
  2105. && ((deci_w > sblk->maxhdeciexp)
  2106. || (deci_h > sblk->maxvdeciexp))) {
  2107. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2108. ret = -EINVAL;
  2109. } else if ((deci_w || deci_h)
  2110. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2111. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2112. ret = -EINVAL;
  2113. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2114. ((src->w != dst->w) || (src->h != dst->h))) {
  2115. SDE_ERROR_PLANE(psde,
  2116. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2117. src->w, src->h, dst->w, dst->h);
  2118. ret = -EINVAL;
  2119. /* check scaler source width */
  2120. } else if (scaler_src_w > max_linewidth) {
  2121. SDE_ERROR_PLANE(psde,
  2122. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2123. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2124. ret = -E2BIG;
  2125. /* check max scaler capability */
  2126. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2127. ((scaler_src_h * max_upscale) < dst->h) ||
  2128. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2129. < scaler_src_w) ||
  2130. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2131. < scaler_src_h)) {
  2132. SDE_ERROR_PLANE(psde,
  2133. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2134. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2135. inline_rotation, max_downscale_num_w,
  2136. max_downscale_denom_w, max_downscale_num_h,
  2137. max_downscale_denom_h);
  2138. ret = -E2BIG;
  2139. /* check inline pre-downscale support */
  2140. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2141. pstate, dst, src_deci_w, src_deci_h)) {
  2142. ret = -EINVAL;
  2143. /* QSEED validation */
  2144. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2145. width, height, src->w, src->h,
  2146. deci_w, deci_h)) {
  2147. ret = -EINVAL;
  2148. }
  2149. return ret;
  2150. }
  2151. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2152. struct sde_plane_state *pstate, struct sde_rect *src,
  2153. const struct sde_format *fmt, int ret)
  2154. {
  2155. /* check excl rect configs */
  2156. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2157. struct sde_rect intersect;
  2158. /*
  2159. * Check exclusion rect against src rect.
  2160. * it must intersect with source rect.
  2161. */
  2162. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2163. if (intersect.w != pstate->excl_rect.w ||
  2164. intersect.h != pstate->excl_rect.h ||
  2165. SDE_FORMAT_IS_YUV(fmt)) {
  2166. SDE_ERROR_PLANE(psde,
  2167. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2168. pstate->excl_rect.x, pstate->excl_rect.y,
  2169. pstate->excl_rect.w, pstate->excl_rect.h,
  2170. src->x, src->y, src->w, src->h,
  2171. (char *)&fmt->base.pixel_format);
  2172. ret = -EINVAL;
  2173. }
  2174. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2175. pstate->excl_rect.x, pstate->excl_rect.y,
  2176. pstate->excl_rect.w, pstate->excl_rect.h);
  2177. }
  2178. return ret;
  2179. }
  2180. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2181. struct drm_plane_state *state)
  2182. {
  2183. struct sde_kms *sde_kms;
  2184. struct sde_splash_display *splash_display;
  2185. int i, j;
  2186. sde_kms = _sde_plane_get_kms(&psde->base);
  2187. if (!sde_kms || !state->crtc)
  2188. return 0;
  2189. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2190. splash_display = &sde_kms->splash_data.splash_display[i];
  2191. if (splash_display && splash_display->cont_splash_enabled &&
  2192. splash_display->encoder &&
  2193. state->crtc != splash_display->encoder->crtc) {
  2194. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2195. if (splash_display->pipes[j].sspp ==
  2196. psde->pipe) {
  2197. SDE_ERROR_PLANE(psde,
  2198. "pipe:%d used in cont-splash on crtc:%d\n",
  2199. psde->pipe,
  2200. splash_display->encoder->crtc->base.id);
  2201. return -EINVAL;
  2202. }
  2203. }
  2204. }
  2205. }
  2206. return 0;
  2207. }
  2208. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2209. const struct sde_format *fmt,
  2210. struct sde_rect src, struct sde_rect dst,
  2211. u32 width, u32 height)
  2212. {
  2213. int ret = 0;
  2214. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2215. if (SDE_FORMAT_IS_YUV(fmt) &&
  2216. (!(psde->features & SDE_SSPP_SCALER) ||
  2217. !(psde->features & (BIT(SDE_SSPP_CSC)
  2218. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2219. SDE_ERROR_PLANE(psde,
  2220. "plane doesn't have scaler/csc for yuv\n");
  2221. ret = -EINVAL;
  2222. /* check src bounds */
  2223. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2224. src.w < min_src_size || src.h < min_src_size ||
  2225. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2226. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2227. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2228. src.x, src.y, src.w, src.h);
  2229. ret = -E2BIG;
  2230. /* valid yuv image */
  2231. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2232. (src.w & 0x1) || (src.h & 0x1))) {
  2233. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2234. src.x, src.y, src.w, src.h);
  2235. ret = -EINVAL;
  2236. /* min dst support */
  2237. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2238. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2239. dst.x, dst.y, dst.w, dst.h);
  2240. ret = -EINVAL;
  2241. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2242. !psde->catalog->ubwc_version) {
  2243. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2244. ret = -EINVAL;
  2245. }
  2246. return ret;
  2247. }
  2248. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2249. struct drm_plane_state *state)
  2250. {
  2251. int ret = 0;
  2252. struct sde_plane *psde;
  2253. struct sde_plane_state *pstate;
  2254. const struct msm_format *msm_fmt;
  2255. const struct sde_format *fmt;
  2256. struct sde_rect src, dst;
  2257. bool q16_data = true;
  2258. struct drm_framebuffer *fb;
  2259. u32 width;
  2260. u32 height;
  2261. psde = to_sde_plane(plane);
  2262. pstate = to_sde_plane_state(state);
  2263. if (!psde->pipe_sblk) {
  2264. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2265. return -EINVAL;
  2266. }
  2267. /* src values are in Q16 fixed point, convert to integer */
  2268. POPULATE_RECT(&src, state->src_x, state->src_y,
  2269. state->src_w, state->src_h, q16_data);
  2270. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2271. state->crtc_h, !q16_data);
  2272. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2273. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2274. if (!sde_plane_enabled(state))
  2275. goto modeset_update;
  2276. fb = state->fb;
  2277. width = fb ? state->fb->width : 0x0;
  2278. height = fb ? state->fb->height : 0x0;
  2279. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2280. plane->base.id,
  2281. pstate->rotation,
  2282. width, height,
  2283. fb ? (char *) &state->fb->format->format : 0x0,
  2284. fb ? state->fb->modifier : 0x0);
  2285. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2286. state->src_w >> 16, state->src_h >> 16,
  2287. state->src_x >> 16, state->src_y >> 16,
  2288. state->crtc_w, state->crtc_h,
  2289. state->crtc_x, state->crtc_y);
  2290. msm_fmt = msm_framebuffer_format(fb);
  2291. fmt = to_sde_format(msm_fmt);
  2292. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2293. height);
  2294. if (ret)
  2295. return ret;
  2296. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2297. &src, &dst, width, height);
  2298. if (ret)
  2299. return ret;
  2300. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2301. &src, fmt, ret);
  2302. if (ret)
  2303. return ret;
  2304. ret = _sde_plane_validate_shared_crtc(psde, state);
  2305. if (ret)
  2306. return ret;
  2307. pstate->const_alpha_en = fmt->alpha_enable &&
  2308. (SDE_DRM_BLEND_OP_OPAQUE !=
  2309. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2310. (pstate->stage != SDE_STAGE_0);
  2311. modeset_update:
  2312. if (!ret)
  2313. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2314. state, plane->state);
  2315. return ret;
  2316. }
  2317. static int sde_plane_atomic_check(struct drm_plane *plane,
  2318. struct drm_plane_state *state)
  2319. {
  2320. int ret = 0;
  2321. struct sde_plane *psde;
  2322. struct sde_plane_state *pstate;
  2323. if (!plane || !state) {
  2324. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2325. !plane, !state);
  2326. ret = -EINVAL;
  2327. goto exit;
  2328. }
  2329. psde = to_sde_plane(plane);
  2330. pstate = to_sde_plane_state(state);
  2331. SDE_DEBUG_PLANE(psde, "\n");
  2332. ret = sde_plane_rot_atomic_check(plane, state);
  2333. if (ret)
  2334. goto exit;
  2335. ret = sde_plane_sspp_atomic_check(plane, state);
  2336. exit:
  2337. return ret;
  2338. }
  2339. void sde_plane_flush(struct drm_plane *plane)
  2340. {
  2341. struct sde_plane *psde;
  2342. struct sde_plane_state *pstate;
  2343. if (!plane || !plane->state) {
  2344. SDE_ERROR("invalid plane\n");
  2345. return;
  2346. }
  2347. psde = to_sde_plane(plane);
  2348. pstate = to_sde_plane_state(plane->state);
  2349. /*
  2350. * These updates have to be done immediately before the plane flush
  2351. * timing, and may not be moved to the atomic_update/mode_set functions.
  2352. */
  2353. if (psde->is_error)
  2354. /* force white frame with 100% alpha pipe output on error */
  2355. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2356. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2357. /* force 100% alpha */
  2358. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2359. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2360. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2361. /* flag h/w flush complete */
  2362. if (plane->state)
  2363. pstate->pending = false;
  2364. }
  2365. /**
  2366. * sde_plane_set_error: enable/disable error condition
  2367. * @plane: pointer to drm_plane structure
  2368. */
  2369. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2370. {
  2371. struct sde_plane *psde;
  2372. if (!plane)
  2373. return;
  2374. psde = to_sde_plane(plane);
  2375. psde->is_error = error;
  2376. }
  2377. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2378. struct sde_plane_state *pstate)
  2379. {
  2380. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2381. bool prev_rd_en;
  2382. /* Only display system cache is currently supported */
  2383. if (!sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2384. return;
  2385. prev_rd_en = pstate->sc_cfg.rd_en;
  2386. SDE_DEBUG_PLANE(psde, "features:0x%x\n", psde->features);
  2387. pstate->sc_cfg.rd_en = false;
  2388. pstate->sc_cfg.rd_scid = 0x0;
  2389. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2390. SSPP_SYS_CACHE_SCID;
  2391. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2392. if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE) {
  2393. pstate->sc_cfg.rd_en = true;
  2394. pstate->sc_cfg.rd_scid =
  2395. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2396. pstate->sc_cfg.rd_noallocate = false;
  2397. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2398. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2399. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2400. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ) {
  2401. pstate->sc_cfg.rd_en = true;
  2402. pstate->sc_cfg.rd_scid =
  2403. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2404. pstate->sc_cfg.rd_noallocate = true;
  2405. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2406. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2407. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2408. }
  2409. if (!pstate->sc_cfg.rd_en && !prev_rd_en)
  2410. return;
  2411. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2412. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2413. psde->pipe_hw->ops.setup_sys_cache(
  2414. psde->pipe_hw, &pstate->sc_cfg);
  2415. }
  2416. void sde_plane_static_img_control(struct drm_plane *plane,
  2417. enum sde_crtc_cache_state state)
  2418. {
  2419. struct sde_plane *psde;
  2420. struct sde_plane_state *pstate;
  2421. if (!plane || !plane->state) {
  2422. SDE_ERROR("invalid plane\n");
  2423. return;
  2424. }
  2425. psde = to_sde_plane(plane);
  2426. pstate = to_sde_plane_state(plane->state);
  2427. pstate->static_cache_state = state;
  2428. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2429. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2430. }
  2431. static void _sde_plane_map_prop_to_dirty_bits(void)
  2432. {
  2433. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2434. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2435. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2436. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2437. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2438. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2439. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2440. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2441. plane_prop_array[PLANE_PROP_ZPOS] =
  2442. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2443. SDE_PLANE_DIRTY_RECTS;
  2444. plane_prop_array[PLANE_PROP_CSC_V1] =
  2445. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2446. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2447. SDE_PLANE_DIRTY_FORMAT;
  2448. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2449. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2450. SDE_PLANE_DIRTY_ALL;
  2451. /* no special action required */
  2452. plane_prop_array[PLANE_PROP_INFO] =
  2453. plane_prop_array[PLANE_PROP_ALPHA] =
  2454. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2455. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2456. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2457. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2458. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2459. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2460. SDE_PLANE_DIRTY_PERF;
  2461. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2462. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2463. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2464. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2465. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2466. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2467. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2468. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2469. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2470. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2471. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2472. SDE_PLANE_DIRTY_ALL;
  2473. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2474. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2475. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2476. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2477. }
  2478. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2479. struct sde_rect *src, struct sde_rect *dst)
  2480. {
  2481. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2482. u32 downscale = (src->h * 1000)/dst->h;
  2483. return (downscale > max_downscale) ? false : true;
  2484. }
  2485. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2486. struct sde_plane *psde, struct sde_plane_state *pstate,
  2487. struct sde_rect *src, struct sde_rect *dst)
  2488. {
  2489. struct sde_hw_pipe_uidle_cfg cfg;
  2490. u32 line_time = sde_crtc_get_line_time(crtc);
  2491. u32 fal1_target_idle_time_ns =
  2492. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2493. u32 fal10_target_idle_time_ns =
  2494. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2495. u32 fal10_threshold =
  2496. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2497. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2498. fal1_target_idle_time_ns) {
  2499. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2500. cfg.fal10_threshold = fal10_threshold;
  2501. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2502. cfg.fal1_threshold = min(1 +
  2503. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2504. psde->catalog->uidle_cfg.fal1_max_threshold);
  2505. cfg.fal_allowed_threshold = fal10_threshold +
  2506. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2507. } else {
  2508. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2509. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2510. fal1_target_idle_time_ns);
  2511. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2512. }
  2513. SDE_DEBUG_PLANE(psde,
  2514. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2515. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2516. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2517. SDE_DEBUG_PLANE(psde,
  2518. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2519. line_time, fal1_target_idle_time_ns,
  2520. fal10_target_idle_time_ns,
  2521. psde->catalog->uidle_cfg.max_dwnscale);
  2522. SDE_EVT32_VERBOSE(cfg.enable,
  2523. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2524. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2525. psde->catalog->uidle_cfg.max_dwnscale);
  2526. psde->pipe_hw->ops.setup_uidle(
  2527. psde->pipe_hw, &cfg,
  2528. pstate->multirect_index);
  2529. }
  2530. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2531. struct sde_plane_state *pstate)
  2532. {
  2533. bool enable = false;
  2534. int mode = sde_plane_get_property(pstate,
  2535. PLANE_PROP_FB_TRANSLATION_MODE);
  2536. if ((mode == SDE_DRM_FB_SEC) ||
  2537. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2538. enable = true;
  2539. /* update secure session flag */
  2540. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2541. pstate->multirect_index,
  2542. enable);
  2543. }
  2544. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2545. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2546. {
  2547. const struct sde_format *fmt;
  2548. const struct msm_format *msm_fmt;
  2549. struct sde_plane *psde;
  2550. struct drm_plane_state *state;
  2551. struct sde_plane_state *pstate;
  2552. struct sde_rect src, dst;
  2553. const struct sde_rect *crtc_roi;
  2554. bool q16_data = true;
  2555. int idx;
  2556. psde = to_sde_plane(plane);
  2557. state = plane->state;
  2558. pstate = to_sde_plane_state(state);
  2559. msm_fmt = msm_framebuffer_format(fb);
  2560. if (!msm_fmt) {
  2561. SDE_ERROR("crtc%d plane%d: null format\n",
  2562. DRMID(crtc), DRMID(plane));
  2563. return;
  2564. }
  2565. fmt = to_sde_format(msm_fmt);
  2566. POPULATE_RECT(&src, state->src_x, state->src_y,
  2567. state->src_w, state->src_h, q16_data);
  2568. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2569. state->crtc_w, state->crtc_h, !q16_data);
  2570. SDE_DEBUG_PLANE(psde,
  2571. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2572. fb->base.id, src.x, src.y, src.w, src.h,
  2573. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2574. (char *)&fmt->base.pixel_format,
  2575. SDE_FORMAT_IS_UBWC(fmt));
  2576. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2577. BIT(SDE_DRM_DEINTERLACE)) {
  2578. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2579. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2580. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2581. src.h /= 2;
  2582. src.y = DIV_ROUND_UP(src.y, 2);
  2583. src.y &= ~0x1;
  2584. }
  2585. /*
  2586. * adjust layer mixer position of the sspp in the presence
  2587. * of a partial update to the active lm origin
  2588. */
  2589. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2590. dst.x -= crtc_roi->x;
  2591. dst.y -= crtc_roi->y;
  2592. /* check for UIDLE */
  2593. if (psde->pipe_hw->ops.setup_uidle)
  2594. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2595. psde->pipe_cfg.src_rect = src;
  2596. psde->pipe_cfg.dst_rect = dst;
  2597. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2598. /* check for color fill */
  2599. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2600. PLANE_PROP_COLOR_FILL);
  2601. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2602. /* skip remaining processing on color fill */
  2603. pstate->dirty = 0x0;
  2604. } else if (psde->pipe_hw->ops.setup_rects) {
  2605. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2606. &psde->pipe_cfg,
  2607. pstate->multirect_index);
  2608. }
  2609. if (psde->pipe_hw->ops.setup_pe &&
  2610. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2611. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2612. &pstate->pixel_ext);
  2613. /**
  2614. * when programmed in multirect mode, scalar block will be
  2615. * bypassed. Still we need to update alpha and bitwidth
  2616. * ONLY for RECT0
  2617. */
  2618. if (psde->pipe_hw->ops.setup_scaler &&
  2619. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2620. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2621. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2622. &psde->pipe_cfg, &pstate->pixel_ext,
  2623. &pstate->scaler3_cfg);
  2624. }
  2625. /* update excl rect */
  2626. if (psde->pipe_hw->ops.setup_excl_rect)
  2627. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2628. &pstate->excl_rect,
  2629. pstate->multirect_index);
  2630. /* enable multirect config of corresponding rect */
  2631. if (psde->pipe_hw->ops.update_multirect)
  2632. psde->pipe_hw->ops.update_multirect(
  2633. psde->pipe_hw,
  2634. true,
  2635. pstate->multirect_index,
  2636. pstate->multirect_mode);
  2637. }
  2638. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2639. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2640. {
  2641. uint32_t src_flags = 0;
  2642. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2643. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2644. src_flags |= SDE_SSPP_FLIP_LR;
  2645. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2646. src_flags |= SDE_SSPP_FLIP_UD;
  2647. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2648. src_flags |= SDE_SSPP_ROT_90;
  2649. /* update format */
  2650. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2651. pstate->const_alpha_en, src_flags,
  2652. pstate->multirect_index);
  2653. if (psde->pipe_hw->ops.setup_cdp) {
  2654. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2655. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2656. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2657. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2658. cdp_cfg->ubwc_meta_enable =
  2659. SDE_FORMAT_IS_UBWC(fmt);
  2660. cdp_cfg->tile_amortize_enable =
  2661. SDE_FORMAT_IS_UBWC(fmt) ||
  2662. SDE_FORMAT_IS_TILE(fmt);
  2663. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2664. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2665. pstate->multirect_index);
  2666. }
  2667. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2668. /* update csc */
  2669. if (SDE_FORMAT_IS_YUV(fmt))
  2670. _sde_plane_setup_csc(psde);
  2671. else
  2672. psde->csc_ptr = 0;
  2673. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2674. uint32_t pma_mode = 0;
  2675. if (fmt->alpha_enable)
  2676. pma_mode = (uint32_t) sde_plane_get_property(
  2677. pstate, PLANE_PROP_INVERSE_PMA);
  2678. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2679. pstate->multirect_index, pma_mode);
  2680. }
  2681. if (psde->pipe_hw->ops.setup_dgm_csc)
  2682. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2683. pstate->multirect_index, psde->csc_usr_ptr);
  2684. }
  2685. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2686. {
  2687. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2688. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2689. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2690. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2691. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2692. &psde->sharp_cfg);
  2693. }
  2694. static void _sde_plane_update_properties(struct drm_plane *plane,
  2695. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2696. {
  2697. uint32_t nplanes;
  2698. const struct msm_format *msm_fmt;
  2699. const struct sde_format *fmt;
  2700. struct sde_plane *psde;
  2701. struct drm_plane_state *state;
  2702. struct sde_plane_state *pstate;
  2703. psde = to_sde_plane(plane);
  2704. state = plane->state;
  2705. pstate = to_sde_plane_state(state);
  2706. if (!pstate) {
  2707. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2708. return;
  2709. }
  2710. msm_fmt = msm_framebuffer_format(fb);
  2711. if (!msm_fmt) {
  2712. SDE_ERROR("crtc%d plane%d: null format\n",
  2713. DRMID(crtc), DRMID(plane));
  2714. return;
  2715. }
  2716. fmt = to_sde_format(msm_fmt);
  2717. nplanes = fmt->num_planes;
  2718. /* update secure session flag */
  2719. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2720. _sde_plane_update_secure_session(psde, pstate);
  2721. /* update roi config */
  2722. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2723. _sde_plane_update_roi_config(plane, crtc, fb);
  2724. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2725. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2726. psde->pipe_hw->ops.setup_format)
  2727. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2728. sde_color_process_plane_setup(plane);
  2729. /* update sharpening */
  2730. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2731. psde->pipe_hw->ops.setup_sharpening)
  2732. _sde_plane_update_sharpening(psde);
  2733. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2734. SDE_PLANE_DIRTY_FORMAT))
  2735. _sde_plane_set_qos_lut(plane, crtc, fb);
  2736. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2737. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2738. _sde_plane_set_ot_limit(plane, crtc);
  2739. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2740. _sde_plane_set_ts_prefill(plane, pstate);
  2741. }
  2742. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2743. _sde_plane_set_qos_remap(plane);
  2744. /* clear dirty */
  2745. pstate->dirty = 0x0;
  2746. }
  2747. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2748. struct drm_plane_state *old_state)
  2749. {
  2750. struct sde_plane *psde;
  2751. struct drm_plane_state *state;
  2752. struct sde_plane_state *pstate;
  2753. struct sde_plane_state *old_pstate;
  2754. struct drm_crtc *crtc;
  2755. struct drm_framebuffer *fb;
  2756. int idx;
  2757. int dirty_prop_flag;
  2758. bool is_rt;
  2759. if (!plane) {
  2760. SDE_ERROR("invalid plane\n");
  2761. return -EINVAL;
  2762. } else if (!plane->state) {
  2763. SDE_ERROR("invalid plane state\n");
  2764. return -EINVAL;
  2765. } else if (!old_state) {
  2766. SDE_ERROR("invalid old state\n");
  2767. return -EINVAL;
  2768. }
  2769. psde = to_sde_plane(plane);
  2770. state = plane->state;
  2771. pstate = to_sde_plane_state(state);
  2772. old_pstate = to_sde_plane_state(old_state);
  2773. crtc = state->crtc;
  2774. fb = state->fb;
  2775. if (!crtc || !fb) {
  2776. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2777. !crtc, !fb);
  2778. return -EINVAL;
  2779. }
  2780. SDE_DEBUG(
  2781. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2782. plane->base.id,
  2783. state->fb->width, state->fb->height,
  2784. (char *) &state->fb->format->format,
  2785. state->fb->modifier,
  2786. state->src_w >> 16, state->src_h >> 16,
  2787. state->src_x >> 16, state->src_y >> 16,
  2788. pstate->rotation,
  2789. state->crtc_w, state->crtc_h,
  2790. state->crtc_x, state->crtc_y);
  2791. /* force reprogramming of all the parameters, if the flag is set */
  2792. if (psde->revalidate) {
  2793. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2794. plane->base.id);
  2795. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2796. psde->revalidate = false;
  2797. }
  2798. /* determine what needs to be refreshed */
  2799. mutex_lock(&psde->property_info.property_lock);
  2800. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2801. &pstate->property_state)) >= 0) {
  2802. dirty_prop_flag = plane_prop_array[idx];
  2803. pstate->dirty |= dirty_prop_flag;
  2804. }
  2805. mutex_unlock(&psde->property_info.property_lock);
  2806. /**
  2807. * since plane_atomic_check is invoked before crtc_atomic_check
  2808. * in the commit sequence, all the parameters for updating the
  2809. * plane dirty flag will not be available during
  2810. * plane_atomic_check as some features params are updated
  2811. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2812. * before sspp update.
  2813. */
  2814. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2815. old_state);
  2816. /* re-program the output rects always if partial update roi changed */
  2817. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2818. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2819. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2820. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2821. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2822. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2823. if (is_rt != psde->is_rt_pipe) {
  2824. psde->is_rt_pipe = is_rt;
  2825. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2826. }
  2827. /* early out if nothing dirty */
  2828. if (!pstate->dirty)
  2829. return 0;
  2830. pstate->pending = true;
  2831. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2832. _sde_plane_update_properties(plane, crtc, fb);
  2833. return 0;
  2834. }
  2835. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2836. struct drm_plane_state *old_state)
  2837. {
  2838. struct sde_plane *psde;
  2839. struct drm_plane_state *state;
  2840. struct sde_plane_state *pstate;
  2841. u32 multirect_index = SDE_SSPP_RECT_0;
  2842. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2843. u32 blend_type;
  2844. if (!plane) {
  2845. SDE_ERROR("invalid plane\n");
  2846. return;
  2847. } else if (!plane->state) {
  2848. SDE_ERROR("invalid plane state\n");
  2849. return;
  2850. } else if (!old_state) {
  2851. SDE_ERROR("invalid old state\n");
  2852. return;
  2853. }
  2854. psde = to_sde_plane(plane);
  2855. state = plane->state;
  2856. pstate = to_sde_plane_state(state);
  2857. blend_type = sde_plane_get_property(pstate,
  2858. PLANE_PROP_BLEND_OP);
  2859. /* some of the color features are dependent on plane with skip blend.
  2860. * if skip blend plane is being disabled, we need to disable color properties.
  2861. */
  2862. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2863. skip_blend_plane.valid_plane = false;
  2864. skip_blend_plane.plane = SSPP_NONE;
  2865. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2866. sde_crtc_disable_cp_features(old_state->crtc);
  2867. }
  2868. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2869. pstate->multirect_mode);
  2870. pstate->pending = true;
  2871. if (is_sde_plane_virtual(plane))
  2872. multirect_index = SDE_SSPP_RECT_1;
  2873. /* disable multirect config of corresponding rect */
  2874. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2875. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2876. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2877. }
  2878. static void sde_plane_atomic_update(struct drm_plane *plane,
  2879. struct drm_plane_state *old_state)
  2880. {
  2881. struct sde_plane *psde;
  2882. struct drm_plane_state *state;
  2883. if (!plane) {
  2884. SDE_ERROR("invalid plane\n");
  2885. return;
  2886. } else if (!plane->state) {
  2887. SDE_ERROR("invalid plane state\n");
  2888. return;
  2889. }
  2890. psde = to_sde_plane(plane);
  2891. psde->is_error = false;
  2892. state = plane->state;
  2893. SDE_DEBUG_PLANE(psde, "\n");
  2894. if (!sde_plane_enabled(state)) {
  2895. _sde_plane_atomic_disable(plane, old_state);
  2896. } else {
  2897. int ret;
  2898. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2899. /* atomic_check should have ensured that this doesn't fail */
  2900. WARN_ON(ret < 0);
  2901. }
  2902. }
  2903. void sde_plane_restore(struct drm_plane *plane)
  2904. {
  2905. struct sde_plane *psde;
  2906. if (!plane || !plane->state) {
  2907. SDE_ERROR("invalid plane\n");
  2908. return;
  2909. }
  2910. psde = to_sde_plane(plane);
  2911. /*
  2912. * Revalidate is only true here if idle PC occurred and
  2913. * there is no plane state update in current commit cycle.
  2914. */
  2915. if (!psde->revalidate)
  2916. return;
  2917. SDE_DEBUG_PLANE(psde, "\n");
  2918. /* last plane state is same as current state */
  2919. sde_plane_atomic_update(plane, plane->state);
  2920. }
  2921. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2922. enum sde_sys_cache_type type)
  2923. {
  2924. struct sde_plane_state *pstate;
  2925. if (!plane || !plane->state) {
  2926. SDE_ERROR("invalid plane\n");
  2927. return false;
  2928. }
  2929. pstate = to_sde_plane_state(plane->state);
  2930. /* check if llcc is required for the plane */
  2931. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2932. return true;
  2933. else
  2934. return false;
  2935. }
  2936. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2937. {
  2938. char feature_name[256];
  2939. if (psde->pipe_sblk->maxhdeciexp) {
  2940. msm_property_install_range(&psde->property_info,
  2941. "h_decimate", 0x0, 0,
  2942. psde->pipe_sblk->maxhdeciexp, 0,
  2943. PLANE_PROP_H_DECIMATE);
  2944. }
  2945. if (psde->pipe_sblk->maxvdeciexp) {
  2946. msm_property_install_range(&psde->property_info,
  2947. "v_decimate", 0x0, 0,
  2948. psde->pipe_sblk->maxvdeciexp, 0,
  2949. PLANE_PROP_V_DECIMATE);
  2950. }
  2951. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2952. msm_property_install_range(
  2953. &psde->property_info, "scaler_v2",
  2954. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2955. msm_property_install_blob(&psde->property_info,
  2956. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2957. msm_property_install_blob(&psde->property_info,
  2958. "lut_cir", 0,
  2959. PLANE_PROP_SCALER_LUT_CIR);
  2960. msm_property_install_blob(&psde->property_info,
  2961. "lut_sep", 0,
  2962. PLANE_PROP_SCALER_LUT_SEP);
  2963. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2964. msm_property_install_range(
  2965. &psde->property_info, "scaler_v2",
  2966. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2967. msm_property_install_blob(&psde->property_info,
  2968. "lut_sep", 0,
  2969. PLANE_PROP_SCALER_LUT_SEP);
  2970. } else if (psde->features & SDE_SSPP_SCALER) {
  2971. msm_property_install_range(
  2972. &psde->property_info, "scaler_v1", 0x0,
  2973. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2974. }
  2975. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2976. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2977. msm_property_install_volatile_range(
  2978. &psde->property_info, "csc_v1", 0x0,
  2979. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2980. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2981. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2982. "SDE_SSPP_HUE_V",
  2983. psde->pipe_sblk->hsic_blk.version >> 16);
  2984. msm_property_install_range(&psde->property_info,
  2985. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2986. PLANE_PROP_HUE_ADJUST);
  2987. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2988. "SDE_SSPP_SATURATION_V",
  2989. psde->pipe_sblk->hsic_blk.version >> 16);
  2990. msm_property_install_range(&psde->property_info,
  2991. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2992. PLANE_PROP_SATURATION_ADJUST);
  2993. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2994. "SDE_SSPP_VALUE_V",
  2995. psde->pipe_sblk->hsic_blk.version >> 16);
  2996. msm_property_install_range(&psde->property_info,
  2997. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2998. PLANE_PROP_VALUE_ADJUST);
  2999. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3000. "SDE_SSPP_CONTRAST_V",
  3001. psde->pipe_sblk->hsic_blk.version >> 16);
  3002. msm_property_install_range(&psde->property_info,
  3003. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3004. PLANE_PROP_CONTRAST_ADJUST);
  3005. }
  3006. }
  3007. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3008. struct sde_kms_info *info)
  3009. {
  3010. char feature_name[256];
  3011. bool is_master = !psde->is_virtual;
  3012. if ((is_master &&
  3013. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3014. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3015. msm_property_install_range(&psde->property_info,
  3016. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3017. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3018. }
  3019. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3020. msm_property_install_volatile_range(
  3021. &psde->property_info, "csc_dma_v1", 0x0,
  3022. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3023. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3024. }
  3025. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3026. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3027. "SDE_SSPP_SKIN_COLOR_V",
  3028. psde->pipe_sblk->memcolor_blk.version >> 16);
  3029. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3030. PLANE_PROP_SKIN_COLOR);
  3031. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3032. "SDE_SSPP_SKY_COLOR_V",
  3033. psde->pipe_sblk->memcolor_blk.version >> 16);
  3034. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3035. PLANE_PROP_SKY_COLOR);
  3036. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3037. "SDE_SSPP_FOLIAGE_COLOR_V",
  3038. psde->pipe_sblk->memcolor_blk.version >> 16);
  3039. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3040. PLANE_PROP_FOLIAGE_COLOR);
  3041. }
  3042. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3043. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3044. "SDE_VIG_3D_LUT_GAMUT_V",
  3045. psde->pipe_sblk->gamut_blk.version >> 16);
  3046. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3047. PLANE_PROP_VIG_GAMUT);
  3048. }
  3049. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3050. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3051. "SDE_VIG_1D_LUT_IGC_V",
  3052. psde->pipe_sblk->igc_blk[0].version >> 16);
  3053. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3054. PLANE_PROP_VIG_IGC);
  3055. }
  3056. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3057. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3058. "SDE_DGM_1D_LUT_IGC_V",
  3059. psde->pipe_sblk->igc_blk[0].version >> 16);
  3060. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3061. PLANE_PROP_DMA_IGC);
  3062. }
  3063. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3064. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3065. "SDE_DGM_1D_LUT_GC_V",
  3066. psde->pipe_sblk->gc_blk[0].version >> 16);
  3067. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3068. PLANE_PROP_DMA_GC);
  3069. }
  3070. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3071. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3072. "SDE_SSPP_FP16_IGC_V",
  3073. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3074. msm_property_install_range(&psde->property_info, feature_name,
  3075. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3076. }
  3077. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3078. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3079. "SDE_SSPP_FP16_GC_V",
  3080. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3081. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3082. PLANE_PROP_FP16_GC);
  3083. }
  3084. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3085. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3086. "SDE_SSPP_FP16_CSC_V",
  3087. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3088. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3089. PLANE_PROP_FP16_CSC);
  3090. }
  3091. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3092. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3093. "SDE_SSPP_FP16_UNMULT_V",
  3094. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3095. msm_property_install_range(&psde->property_info, feature_name,
  3096. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3097. }
  3098. }
  3099. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3100. u32 master_plane_id, struct sde_kms_info *info,
  3101. struct sde_mdss_cfg *catalog)
  3102. {
  3103. bool is_master = !psde->is_virtual;
  3104. const struct sde_format_extended *format_list;
  3105. u32 index;
  3106. int pipe_id;
  3107. if (is_master) {
  3108. format_list = psde->pipe_sblk->format_list;
  3109. } else {
  3110. format_list = psde->pipe_sblk->virt_format_list;
  3111. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3112. master_plane_id);
  3113. }
  3114. if (format_list) {
  3115. sde_kms_info_start(info, "pixel_formats");
  3116. while (format_list->fourcc_format) {
  3117. sde_kms_info_append_format(info,
  3118. format_list->fourcc_format,
  3119. format_list->modifier);
  3120. ++format_list;
  3121. }
  3122. sde_kms_info_stop(info);
  3123. }
  3124. if (psde->pipe_hw && catalog->qseed_hw_version)
  3125. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3126. catalog->qseed_hw_version);
  3127. sde_kms_info_add_keyint(info, "max_linewidth",
  3128. psde->pipe_sblk->maxlinewidth);
  3129. sde_kms_info_add_keyint(info, "max_upscale",
  3130. psde->pipe_sblk->maxupscale);
  3131. sde_kms_info_add_keyint(info, "max_downscale",
  3132. psde->pipe_sblk->maxdwnscale);
  3133. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3134. psde->pipe_sblk->maxhdeciexp);
  3135. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3136. psde->pipe_sblk->maxvdeciexp);
  3137. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3138. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3139. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3140. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3141. if (psde->pipe <= SSPP_VIG3 && psde->pipe >= SSPP_VIG0)
  3142. pipe_id = psde->pipe - SSPP_VIG0;
  3143. else if (psde->pipe <= SSPP_RGB3 && psde->pipe >= SSPP_RGB0)
  3144. pipe_id = psde->pipe - SSPP_RGB0;
  3145. else if (psde->pipe <= SSPP_DMA3 && psde->pipe >= SSPP_DMA0)
  3146. pipe_id = psde->pipe - SSPP_DMA0;
  3147. else
  3148. pipe_id = -1;
  3149. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3150. index = (master_plane_id == 0) ? 0 : 1;
  3151. if (catalog->has_demura &&
  3152. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3153. sde_kms_info_add_keyint(info, "demura_block", index);
  3154. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3155. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3156. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3157. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3158. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3159. const struct sde_format_extended *inline_rot_fmt_list;
  3160. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3161. catalog->true_inline_rot_rev);
  3162. sde_kms_info_add_keyint(info,
  3163. "true_inline_dwnscale_rt",
  3164. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3165. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3166. sde_kms_info_add_keyint(info,
  3167. "true_inline_dwnscale_rt_numerator",
  3168. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3169. sde_kms_info_add_keyint(info,
  3170. "true_inline_dwnscale_rt_denominator",
  3171. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3172. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3173. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3174. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3175. psde->pipe_sblk->in_rot_maxheight);
  3176. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3177. if (inline_rot_fmt_list) {
  3178. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3179. while (inline_rot_fmt_list->fourcc_format) {
  3180. sde_kms_info_append_format(info,
  3181. inline_rot_fmt_list->fourcc_format,
  3182. inline_rot_fmt_list->modifier);
  3183. ++inline_rot_fmt_list;
  3184. }
  3185. sde_kms_info_stop(info);
  3186. }
  3187. }
  3188. }
  3189. /* helper to install properties which are common to planes and crtcs */
  3190. static void _sde_plane_install_properties(struct drm_plane *plane,
  3191. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3192. {
  3193. static const struct drm_prop_enum_list e_blend_op[] = {
  3194. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3195. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3196. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3197. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3198. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3199. };
  3200. static const struct drm_prop_enum_list e_src_config[] = {
  3201. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3202. };
  3203. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3204. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3205. {SDE_DRM_FB_SEC, "sec"},
  3206. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3207. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3208. };
  3209. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3210. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3211. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3212. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3213. };
  3214. struct sde_kms_info *info;
  3215. struct sde_plane *psde = to_sde_plane(plane);
  3216. bool is_master;
  3217. int zpos_max = 255;
  3218. int zpos_def = 0;
  3219. if (!plane || !psde) {
  3220. SDE_ERROR("invalid plane\n");
  3221. return;
  3222. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3223. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3224. !psde->pipe_hw, !psde->pipe_sblk);
  3225. return;
  3226. } else if (!catalog) {
  3227. SDE_ERROR("invalid catalog\n");
  3228. return;
  3229. }
  3230. psde->catalog = catalog;
  3231. is_master = !psde->is_virtual;
  3232. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3233. if (!info) {
  3234. SDE_ERROR("failed to allocate info memory\n");
  3235. return;
  3236. }
  3237. if (sde_is_custom_client()) {
  3238. if (catalog->mixer_count &&
  3239. catalog->mixer[0].sblk->maxblendstages) {
  3240. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3241. if (catalog->has_base_layer &&
  3242. (zpos_max > SDE_STAGE_MAX - 1))
  3243. zpos_max = SDE_STAGE_MAX - 1;
  3244. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3245. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3246. }
  3247. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3248. /* reserve zpos == 0 for primary planes */
  3249. zpos_def = drm_plane_index(plane) + 1;
  3250. }
  3251. msm_property_install_range(&psde->property_info, "zpos",
  3252. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3253. msm_property_install_range(&psde->property_info, "alpha",
  3254. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3255. /* linux default file descriptor range on each process */
  3256. msm_property_install_range(&psde->property_info, "input_fence",
  3257. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3258. if (is_master)
  3259. _sde_plane_install_master_only_properties(psde);
  3260. else
  3261. msm_property_install_enum(&psde->property_info,
  3262. "multirect_mode", 0x0, 0, e_multirect_mode,
  3263. ARRAY_SIZE(e_multirect_mode), 0,
  3264. PLANE_PROP_MULTIRECT_MODE);
  3265. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3266. msm_property_install_volatile_range(&psde->property_info,
  3267. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3268. sde_plane_rot_install_properties(plane, catalog);
  3269. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3270. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3271. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3272. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3273. PLANE_PROP_SRC_CONFIG);
  3274. if (psde->pipe_hw->ops.setup_solidfill)
  3275. msm_property_install_range(&psde->property_info, "color_fill",
  3276. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3277. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3278. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3279. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3280. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3281. msm_property_install_blob(&psde->property_info, "capabilities",
  3282. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3283. sde_kms_info_reset(info);
  3284. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3285. catalog);
  3286. _sde_plane_install_colorproc_properties(psde, info);
  3287. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3288. info->data, SDE_KMS_INFO_DATALEN(info),
  3289. PLANE_PROP_INFO);
  3290. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3291. 0x0, 0, e_fb_translation_mode,
  3292. ARRAY_SIZE(e_fb_translation_mode), 0,
  3293. PLANE_PROP_FB_TRANSLATION_MODE);
  3294. kfree(info);
  3295. }
  3296. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3297. void __user *usr_ptr)
  3298. {
  3299. struct sde_drm_csc_v1 csc_v1;
  3300. int i;
  3301. if (!psde) {
  3302. SDE_ERROR("invalid plane\n");
  3303. return;
  3304. }
  3305. psde->csc_usr_ptr = NULL;
  3306. if (!usr_ptr) {
  3307. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3308. return;
  3309. }
  3310. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3311. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3312. return;
  3313. }
  3314. /* populate from user space */
  3315. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3316. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3317. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3318. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3319. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3320. }
  3321. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3322. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3323. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3324. }
  3325. psde->csc_usr_ptr = &psde->csc_cfg;
  3326. }
  3327. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3328. struct sde_plane_state *pstate, void __user *usr)
  3329. {
  3330. struct sde_drm_scaler_v1 scale_v1;
  3331. struct sde_hw_pixel_ext *pe;
  3332. int i;
  3333. if (!psde || !pstate) {
  3334. SDE_ERROR("invalid argument(s)\n");
  3335. return;
  3336. }
  3337. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3338. if (!usr) {
  3339. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3340. return;
  3341. }
  3342. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3343. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3344. return;
  3345. }
  3346. /* force property to be dirty, even if the pointer didn't change */
  3347. msm_property_set_dirty(&psde->property_info,
  3348. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3349. /* populate from user space */
  3350. pe = &pstate->pixel_ext;
  3351. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3352. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3353. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3354. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3355. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3356. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3357. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3358. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3359. }
  3360. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3361. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3362. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3363. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3364. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3365. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3366. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3367. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3368. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3369. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3370. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3371. }
  3372. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3373. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3374. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3375. }
  3376. static void _sde_plane_clear_predownscale_settings(
  3377. struct sde_plane_state *pstate)
  3378. {
  3379. pstate->pre_down.pre_downscale_x_0 = 0;
  3380. pstate->pre_down.pre_downscale_x_1 = 0;
  3381. pstate->pre_down.pre_downscale_y_0 = 0;
  3382. pstate->pre_down.pre_downscale_y_1 = 0;
  3383. }
  3384. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3385. struct sde_plane_state *pstate, void __user *usr)
  3386. {
  3387. struct sde_drm_scaler_v2 scale_v2;
  3388. struct sde_hw_pixel_ext *pe;
  3389. int i;
  3390. struct sde_hw_scaler3_cfg *cfg;
  3391. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3392. if (!psde || !pstate) {
  3393. SDE_ERROR("invalid argument(s)\n");
  3394. return;
  3395. }
  3396. cfg = &pstate->scaler3_cfg;
  3397. pd_cfg = &pstate->pre_down;
  3398. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3399. if (!usr) {
  3400. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3401. cfg->enable = 0;
  3402. _sde_plane_clear_predownscale_settings(pstate);
  3403. goto end;
  3404. }
  3405. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3406. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3407. return;
  3408. }
  3409. /* detach/ignore user data if 'disabled' */
  3410. if (!scale_v2.enable) {
  3411. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3412. cfg->enable = 0;
  3413. _sde_plane_clear_predownscale_settings(pstate);
  3414. goto end;
  3415. }
  3416. /* populate from user space */
  3417. sde_set_scaler_v2(cfg, &scale_v2);
  3418. if (_sde_plane_has_pre_downscale(psde)) {
  3419. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3420. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3421. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3422. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3423. }
  3424. pe = &pstate->pixel_ext;
  3425. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3426. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3427. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3428. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3429. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3430. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3431. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3432. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3433. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3434. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3435. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3436. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3437. }
  3438. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3439. end:
  3440. /* force property to be dirty, even if the pointer didn't change */
  3441. msm_property_set_dirty(&psde->property_info,
  3442. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3443. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3444. cfg->src_width[0], cfg->src_height[0],
  3445. cfg->dst_width, cfg->dst_height);
  3446. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3447. }
  3448. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3449. struct sde_plane_state *pstate, void __user *usr_ptr)
  3450. {
  3451. struct drm_clip_rect excl_rect_v1;
  3452. if (!psde || !pstate) {
  3453. SDE_ERROR("invalid argument(s)\n");
  3454. return;
  3455. }
  3456. if (!usr_ptr) {
  3457. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3458. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3459. return;
  3460. }
  3461. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3462. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3463. return;
  3464. }
  3465. /* populate from user space */
  3466. pstate->excl_rect.x = excl_rect_v1.x1;
  3467. pstate->excl_rect.y = excl_rect_v1.y1;
  3468. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3469. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3470. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3471. pstate->excl_rect.x, pstate->excl_rect.y,
  3472. pstate->excl_rect.w, pstate->excl_rect.h);
  3473. }
  3474. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3475. struct drm_plane_state *state, struct drm_property *property,
  3476. uint64_t val)
  3477. {
  3478. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3479. struct sde_plane_state *pstate;
  3480. int idx, ret = -EINVAL;
  3481. SDE_DEBUG_PLANE(psde, "\n");
  3482. if (!plane) {
  3483. SDE_ERROR("invalid plane\n");
  3484. } else if (!state) {
  3485. SDE_ERROR_PLANE(psde, "invalid state\n");
  3486. } else {
  3487. pstate = to_sde_plane_state(state);
  3488. ret = msm_property_atomic_set(&psde->property_info,
  3489. &pstate->property_state, property, val);
  3490. if (!ret) {
  3491. idx = msm_property_index(&psde->property_info,
  3492. property);
  3493. switch (idx) {
  3494. case PLANE_PROP_INPUT_FENCE:
  3495. _sde_plane_set_input_fence(psde, pstate, val);
  3496. break;
  3497. case PLANE_PROP_CSC_V1:
  3498. case PLANE_PROP_CSC_DMA_V1:
  3499. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3500. break;
  3501. case PLANE_PROP_SCALER_V1:
  3502. _sde_plane_set_scaler_v1(psde, pstate,
  3503. (void *)(uintptr_t)val);
  3504. break;
  3505. case PLANE_PROP_SCALER_V2:
  3506. _sde_plane_set_scaler_v2(psde, pstate,
  3507. (void *)(uintptr_t)val);
  3508. break;
  3509. case PLANE_PROP_EXCL_RECT_V1:
  3510. _sde_plane_set_excl_rect_v1(psde, pstate,
  3511. (void *)(uintptr_t)val);
  3512. break;
  3513. default:
  3514. /* nothing to do */
  3515. break;
  3516. }
  3517. }
  3518. }
  3519. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3520. property->name, property->base.id, val, ret);
  3521. return ret;
  3522. }
  3523. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3524. const struct drm_plane_state *state,
  3525. struct drm_property *property, uint64_t *val)
  3526. {
  3527. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3528. struct sde_plane_state *pstate;
  3529. int ret = -EINVAL;
  3530. if (!plane) {
  3531. SDE_ERROR("invalid plane\n");
  3532. } else if (!state) {
  3533. SDE_ERROR("invalid state\n");
  3534. } else {
  3535. SDE_DEBUG_PLANE(psde, "\n");
  3536. pstate = to_sde_plane_state(state);
  3537. ret = msm_property_atomic_get(&psde->property_info,
  3538. &pstate->property_state, property, val);
  3539. }
  3540. return ret;
  3541. }
  3542. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3543. struct drm_plane_state *plane_state)
  3544. {
  3545. struct sde_plane *psde;
  3546. struct sde_plane_state *pstate;
  3547. struct drm_property *drm_prop;
  3548. enum msm_mdp_plane_property prop_idx;
  3549. if (!plane || !plane_state) {
  3550. SDE_ERROR("invalid params\n");
  3551. return -EINVAL;
  3552. }
  3553. psde = to_sde_plane(plane);
  3554. pstate = to_sde_plane_state(plane_state);
  3555. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3556. uint64_t val = pstate->property_values[prop_idx].value;
  3557. uint64_t def;
  3558. int ret;
  3559. drm_prop = msm_property_index_to_drm_property(
  3560. &psde->property_info, prop_idx);
  3561. if (!drm_prop) {
  3562. /* not all props will be installed, based on caps */
  3563. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3564. prop_idx);
  3565. continue;
  3566. }
  3567. def = msm_property_get_default(&psde->property_info, prop_idx);
  3568. if (val == def)
  3569. continue;
  3570. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3571. drm_prop->name, prop_idx, val, def);
  3572. ret = sde_plane_atomic_set_property(plane, plane_state,
  3573. drm_prop, def);
  3574. if (ret) {
  3575. SDE_ERROR_PLANE(psde,
  3576. "set property failed, idx %d ret %d\n",
  3577. prop_idx, ret);
  3578. continue;
  3579. }
  3580. }
  3581. return 0;
  3582. }
  3583. static void sde_plane_destroy(struct drm_plane *plane)
  3584. {
  3585. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3586. SDE_DEBUG_PLANE(psde, "\n");
  3587. if (psde) {
  3588. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3589. if (psde->blob_info)
  3590. drm_property_blob_put(psde->blob_info);
  3591. msm_property_destroy(&psde->property_info);
  3592. mutex_destroy(&psde->lock);
  3593. /* this will destroy the states as well */
  3594. drm_plane_cleanup(plane);
  3595. if (psde->pipe_hw)
  3596. sde_hw_sspp_destroy(psde->pipe_hw);
  3597. kfree(psde);
  3598. }
  3599. }
  3600. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3601. {
  3602. struct sde_plane_state *pstate;
  3603. if (!state) {
  3604. SDE_ERROR("invalid arg state %d\n", !state);
  3605. return;
  3606. }
  3607. pstate = to_sde_plane_state(state);
  3608. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3609. SDE_DRM_FB_SEC) {
  3610. /* remove ref count for frame buffers */
  3611. if (state->fb) {
  3612. drm_framebuffer_put(state->fb);
  3613. state->fb = NULL;
  3614. }
  3615. }
  3616. }
  3617. static void sde_plane_destroy_state(struct drm_plane *plane,
  3618. struct drm_plane_state *state)
  3619. {
  3620. struct sde_plane *psde;
  3621. struct sde_plane_state *pstate;
  3622. if (!plane || !state) {
  3623. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3624. !plane, !state);
  3625. return;
  3626. }
  3627. psde = to_sde_plane(plane);
  3628. pstate = to_sde_plane_state(state);
  3629. SDE_DEBUG_PLANE(psde, "\n");
  3630. /* remove ref count for frame buffers */
  3631. if (state->fb)
  3632. drm_framebuffer_put(state->fb);
  3633. /* remove ref count for fence */
  3634. if (pstate->input_fence)
  3635. sde_sync_put(pstate->input_fence);
  3636. pstate->input_fence = 0;
  3637. /* destroy value helper */
  3638. msm_property_destroy_state(&psde->property_info, pstate,
  3639. &pstate->property_state);
  3640. }
  3641. static struct drm_plane_state *
  3642. sde_plane_duplicate_state(struct drm_plane *plane)
  3643. {
  3644. struct sde_plane *psde;
  3645. struct sde_plane_state *pstate;
  3646. struct sde_plane_state *old_state;
  3647. struct drm_property *drm_prop;
  3648. uint64_t input_fence_default;
  3649. if (!plane) {
  3650. SDE_ERROR("invalid plane\n");
  3651. return NULL;
  3652. } else if (!plane->state) {
  3653. SDE_ERROR("invalid plane state\n");
  3654. return NULL;
  3655. }
  3656. old_state = to_sde_plane_state(plane->state);
  3657. psde = to_sde_plane(plane);
  3658. if (old_state->cont_splash_populated) {
  3659. plane->state->crtc = NULL;
  3660. old_state->cont_splash_populated = false;
  3661. }
  3662. pstate = msm_property_alloc_state(&psde->property_info);
  3663. if (!pstate) {
  3664. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3665. return NULL;
  3666. }
  3667. SDE_DEBUG_PLANE(psde, "\n");
  3668. /* duplicate value helper */
  3669. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3670. &pstate->property_state, pstate->property_values);
  3671. /* clear out any input fence */
  3672. pstate->input_fence = 0;
  3673. input_fence_default = msm_property_get_default(
  3674. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3675. drm_prop = msm_property_index_to_drm_property(
  3676. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3677. if (msm_property_atomic_set(&psde->property_info,
  3678. &pstate->property_state, drm_prop,
  3679. input_fence_default))
  3680. SDE_DEBUG_PLANE(psde,
  3681. "error clearing duplicated input fence\n");
  3682. pstate->dirty = 0x0;
  3683. pstate->pending = false;
  3684. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3685. /* reset layout offset */
  3686. if (pstate->layout_offset) {
  3687. if (pstate->layout_offset > 0)
  3688. pstate->base.crtc_x += pstate->layout_offset;
  3689. pstate->layout = SDE_LAYOUT_NONE;
  3690. pstate->layout_offset = 0;
  3691. }
  3692. return &pstate->base;
  3693. }
  3694. static void sde_plane_reset(struct drm_plane *plane)
  3695. {
  3696. struct sde_plane *psde;
  3697. struct sde_plane_state *pstate;
  3698. if (!plane) {
  3699. SDE_ERROR("invalid plane\n");
  3700. return;
  3701. }
  3702. psde = to_sde_plane(plane);
  3703. SDE_DEBUG_PLANE(psde, "\n");
  3704. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3705. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3706. return;
  3707. }
  3708. /* remove previous state, if present */
  3709. if (plane->state) {
  3710. sde_plane_destroy_state(plane, plane->state);
  3711. plane->state = 0;
  3712. }
  3713. pstate = msm_property_alloc_state(&psde->property_info);
  3714. if (!pstate) {
  3715. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3716. return;
  3717. }
  3718. /* reset value helper */
  3719. msm_property_reset_state(&psde->property_info, pstate,
  3720. &pstate->property_state,
  3721. pstate->property_values);
  3722. pstate->base.plane = plane;
  3723. plane->state = &pstate->base;
  3724. }
  3725. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3726. {
  3727. u32 ubwc_error = 0;
  3728. struct sde_plane *psde;
  3729. struct sde_plane_state *pstate;
  3730. if (!plane) {
  3731. SDE_ERROR("invalid plane\n");
  3732. return 0;
  3733. }
  3734. psde = to_sde_plane(plane);
  3735. pstate = to_sde_plane_state(plane->state);
  3736. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3737. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3738. pstate->multirect_index);
  3739. return ubwc_error;
  3740. }
  3741. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3742. {
  3743. struct sde_plane *psde;
  3744. struct sde_plane_state *pstate;
  3745. if (!plane) {
  3746. SDE_ERROR("invalid plane\n");
  3747. return;
  3748. }
  3749. psde = to_sde_plane(plane);
  3750. pstate = to_sde_plane_state(plane->state);
  3751. if (psde->pipe_hw->ops.clear_ubwc_error)
  3752. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3753. }
  3754. u32 sde_plane_get_meta_error(struct drm_plane *plane)
  3755. {
  3756. u32 meta_error = 0;
  3757. struct sde_plane *psde;
  3758. struct sde_plane_state *pstate;
  3759. if (!plane) {
  3760. SDE_ERROR("invalid plane\n");
  3761. return 0;
  3762. }
  3763. psde = to_sde_plane(plane);
  3764. pstate = to_sde_plane_state(plane->state);
  3765. if (psde->pipe_hw->ops.get_meta_error)
  3766. meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3767. pstate->multirect_index);
  3768. return meta_error;
  3769. }
  3770. void sde_plane_clear_meta_error(struct drm_plane *plane)
  3771. {
  3772. struct sde_plane *psde;
  3773. struct sde_plane_state *pstate;
  3774. if (!plane) {
  3775. SDE_ERROR("invalid plane\n");
  3776. return;
  3777. }
  3778. psde = to_sde_plane(plane);
  3779. pstate = to_sde_plane_state(plane->state);
  3780. if (psde->pipe_hw->ops.clear_meta_error)
  3781. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3782. }
  3783. #ifdef CONFIG_DEBUG_FS
  3784. static ssize_t _sde_plane_danger_read(struct file *file,
  3785. char __user *buff, size_t count, loff_t *ppos)
  3786. {
  3787. struct sde_kms *kms = file->private_data;
  3788. struct sde_mdss_cfg *cfg = kms->catalog;
  3789. int len = 0;
  3790. char buf[40] = {'\0'};
  3791. if (!cfg)
  3792. return -ENODEV;
  3793. if (*ppos)
  3794. return 0; /* the end */
  3795. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3796. if (len < 0 || len >= sizeof(buf))
  3797. return 0;
  3798. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3799. return -EFAULT;
  3800. *ppos += len; /* increase offset */
  3801. return len;
  3802. }
  3803. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3804. {
  3805. struct drm_plane *plane;
  3806. drm_for_each_plane(plane, kms->dev) {
  3807. if (plane->fb && plane->state) {
  3808. sde_plane_danger_signal_ctrl(plane, enable);
  3809. SDE_DEBUG("plane:%d img:%dx%d ",
  3810. plane->base.id, plane->fb->width,
  3811. plane->fb->height);
  3812. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3813. plane->state->src_x >> 16,
  3814. plane->state->src_y >> 16,
  3815. plane->state->src_w >> 16,
  3816. plane->state->src_h >> 16,
  3817. plane->state->crtc_x, plane->state->crtc_y,
  3818. plane->state->crtc_w, plane->state->crtc_h);
  3819. } else {
  3820. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3821. }
  3822. }
  3823. }
  3824. static ssize_t _sde_plane_danger_write(struct file *file,
  3825. const char __user *user_buf, size_t count, loff_t *ppos)
  3826. {
  3827. struct sde_kms *kms = file->private_data;
  3828. struct sde_mdss_cfg *cfg = kms->catalog;
  3829. int disable_panic;
  3830. char buf[10];
  3831. if (!cfg)
  3832. return -EFAULT;
  3833. if (count >= sizeof(buf))
  3834. return -EFAULT;
  3835. if (copy_from_user(buf, user_buf, count))
  3836. return -EFAULT;
  3837. buf[count] = 0; /* end of string */
  3838. if (kstrtoint(buf, 0, &disable_panic))
  3839. return -EFAULT;
  3840. if (disable_panic) {
  3841. /* Disable panic signal for all active pipes */
  3842. SDE_DEBUG("Disabling danger:\n");
  3843. _sde_plane_set_danger_state(kms, false);
  3844. kms->has_danger_ctrl = false;
  3845. } else {
  3846. /* Enable panic signal for all active pipes */
  3847. SDE_DEBUG("Enabling danger:\n");
  3848. kms->has_danger_ctrl = true;
  3849. _sde_plane_set_danger_state(kms, true);
  3850. }
  3851. return count;
  3852. }
  3853. static const struct file_operations sde_plane_danger_enable = {
  3854. .open = simple_open,
  3855. .read = _sde_plane_danger_read,
  3856. .write = _sde_plane_danger_write,
  3857. };
  3858. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3859. {
  3860. struct sde_plane *psde;
  3861. struct sde_kms *kms;
  3862. struct msm_drm_private *priv;
  3863. const struct sde_sspp_sub_blks *sblk = 0;
  3864. const struct sde_sspp_cfg *cfg = 0;
  3865. if (!plane || !plane->dev) {
  3866. SDE_ERROR("invalid arguments\n");
  3867. return -EINVAL;
  3868. }
  3869. priv = plane->dev->dev_private;
  3870. if (!priv || !priv->kms) {
  3871. SDE_ERROR("invalid KMS reference\n");
  3872. return -EINVAL;
  3873. }
  3874. kms = to_sde_kms(priv->kms);
  3875. psde = to_sde_plane(plane);
  3876. if (psde && psde->pipe_hw)
  3877. cfg = psde->pipe_hw->cap;
  3878. if (cfg)
  3879. sblk = cfg->sblk;
  3880. if (!sblk)
  3881. return 0;
  3882. /* create overall sub-directory for the pipe */
  3883. psde->debugfs_root =
  3884. debugfs_create_dir(psde->pipe_name,
  3885. plane->dev->primary->debugfs_root);
  3886. if (!psde->debugfs_root)
  3887. return -ENOMEM;
  3888. /* don't error check these */
  3889. debugfs_create_x64("features", 0400,
  3890. psde->debugfs_root, &psde->features);
  3891. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3892. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3893. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3894. debugfs_create_bool("default_scaling",
  3895. 0600,
  3896. psde->debugfs_root,
  3897. &psde->debugfs_default_scale);
  3898. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3899. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3900. 0600,
  3901. psde->debugfs_root,
  3902. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3903. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3904. 0600,
  3905. psde->debugfs_root,
  3906. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3907. debugfs_create_u32("in_rot_max_downscale_nrt",
  3908. 0600,
  3909. psde->debugfs_root,
  3910. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3911. debugfs_create_u32("in_rot_max_height",
  3912. 0600,
  3913. psde->debugfs_root,
  3914. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3915. }
  3916. debugfs_create_u32("xin_id",
  3917. 0400,
  3918. psde->debugfs_root,
  3919. (u32 *) &cfg->xin_id);
  3920. debugfs_create_x32("creq_vblank",
  3921. 0600,
  3922. psde->debugfs_root,
  3923. (u32 *) &sblk->creq_vblank);
  3924. debugfs_create_x32("danger_vblank",
  3925. 0600,
  3926. psde->debugfs_root,
  3927. (u32 *) &sblk->danger_vblank);
  3928. debugfs_create_file("disable_danger",
  3929. 0600,
  3930. psde->debugfs_root,
  3931. kms, &sde_plane_danger_enable);
  3932. return 0;
  3933. }
  3934. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3935. {
  3936. struct sde_plane *psde;
  3937. if (!plane)
  3938. return;
  3939. psde = to_sde_plane(plane);
  3940. debugfs_remove_recursive(psde->debugfs_root);
  3941. }
  3942. #else
  3943. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3944. {
  3945. return 0;
  3946. }
  3947. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3948. {
  3949. }
  3950. #endif
  3951. static int sde_plane_late_register(struct drm_plane *plane)
  3952. {
  3953. return _sde_plane_init_debugfs(plane);
  3954. }
  3955. static void sde_plane_early_unregister(struct drm_plane *plane)
  3956. {
  3957. _sde_plane_destroy_debugfs(plane);
  3958. }
  3959. static const struct drm_plane_funcs sde_plane_funcs = {
  3960. .update_plane = drm_atomic_helper_update_plane,
  3961. .disable_plane = drm_atomic_helper_disable_plane,
  3962. .destroy = sde_plane_destroy,
  3963. .atomic_set_property = sde_plane_atomic_set_property,
  3964. .atomic_get_property = sde_plane_atomic_get_property,
  3965. .reset = sde_plane_reset,
  3966. .atomic_duplicate_state = sde_plane_duplicate_state,
  3967. .atomic_destroy_state = sde_plane_destroy_state,
  3968. .late_register = sde_plane_late_register,
  3969. .early_unregister = sde_plane_early_unregister,
  3970. };
  3971. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3972. .prepare_fb = sde_plane_prepare_fb,
  3973. .cleanup_fb = sde_plane_cleanup_fb,
  3974. .atomic_check = sde_plane_atomic_check,
  3975. .atomic_update = sde_plane_atomic_update,
  3976. };
  3977. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3978. {
  3979. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3980. }
  3981. bool is_sde_plane_virtual(struct drm_plane *plane)
  3982. {
  3983. return plane ? to_sde_plane(plane)->is_virtual : false;
  3984. }
  3985. /* initialize plane */
  3986. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3987. uint32_t pipe, bool primary_plane,
  3988. unsigned long possible_crtcs, u32 master_plane_id)
  3989. {
  3990. struct drm_plane *plane = NULL, *master_plane = NULL;
  3991. const struct sde_format_extended *format_list;
  3992. struct sde_plane *psde;
  3993. struct msm_drm_private *priv;
  3994. struct sde_kms *kms;
  3995. enum drm_plane_type type;
  3996. int ret = -EINVAL;
  3997. if (!dev) {
  3998. SDE_ERROR("[%u]device is NULL\n", pipe);
  3999. goto exit;
  4000. }
  4001. priv = dev->dev_private;
  4002. if (!priv) {
  4003. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4004. goto exit;
  4005. }
  4006. if (!priv->kms) {
  4007. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4008. goto exit;
  4009. }
  4010. kms = to_sde_kms(priv->kms);
  4011. if (!kms->catalog) {
  4012. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4013. goto exit;
  4014. }
  4015. /* create and zero local structure */
  4016. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4017. if (!psde) {
  4018. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4019. ret = -ENOMEM;
  4020. goto exit;
  4021. }
  4022. /* cache local stuff for later */
  4023. plane = &psde->base;
  4024. psde->pipe = pipe;
  4025. psde->is_virtual = (master_plane_id != 0);
  4026. INIT_LIST_HEAD(&psde->mplane_list);
  4027. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4028. if (master_plane) {
  4029. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4030. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4031. }
  4032. /* initialize underlying h/w driver */
  4033. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  4034. psde->is_virtual);
  4035. if (IS_ERR(psde->pipe_hw)) {
  4036. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4037. ret = PTR_ERR(psde->pipe_hw);
  4038. goto clean_plane;
  4039. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4040. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4041. goto clean_sspp;
  4042. }
  4043. /* cache features mask for later */
  4044. psde->features = psde->pipe_hw->cap->features_ext;
  4045. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4046. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4047. if (!psde->pipe_sblk) {
  4048. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4049. goto clean_sspp;
  4050. }
  4051. if (psde->is_virtual)
  4052. format_list = psde->pipe_sblk->virt_format_list;
  4053. else
  4054. format_list = psde->pipe_sblk->format_list;
  4055. psde->nformats = sde_populate_formats(format_list,
  4056. psde->formats,
  4057. 0,
  4058. ARRAY_SIZE(psde->formats));
  4059. if (!psde->nformats) {
  4060. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4061. goto clean_sspp;
  4062. }
  4063. if (psde->features & BIT(SDE_SSPP_CURSOR))
  4064. type = DRM_PLANE_TYPE_CURSOR;
  4065. else if (primary_plane)
  4066. type = DRM_PLANE_TYPE_PRIMARY;
  4067. else
  4068. type = DRM_PLANE_TYPE_OVERLAY;
  4069. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4070. psde->formats, psde->nformats,
  4071. NULL, type, NULL);
  4072. if (ret)
  4073. goto clean_sspp;
  4074. /* Populate static array of plane property flags */
  4075. _sde_plane_map_prop_to_dirty_bits();
  4076. /* success! finalize initialization */
  4077. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4078. msm_property_init(&psde->property_info, &plane->base, dev,
  4079. priv->plane_property, psde->property_data,
  4080. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4081. sizeof(struct sde_plane_state));
  4082. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4083. /* save user friendly pipe name for later */
  4084. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4085. mutex_init(&psde->lock);
  4086. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4087. pipe, plane->base.id, master_plane_id);
  4088. return plane;
  4089. clean_sspp:
  4090. if (psde && psde->pipe_hw)
  4091. sde_hw_sspp_destroy(psde->pipe_hw);
  4092. clean_plane:
  4093. kfree(psde);
  4094. exit:
  4095. return ERR_PTR(ret);
  4096. }