wcd938x.c 82 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. #define ADC_MODE_VAL_HIFI 0x01
  29. #define ADC_MODE_VAL_LO_HIF 0x02
  30. #define ADC_MODE_VAL_NORMAL 0x03
  31. #define ADC_MODE_VAL_LP 0x05
  32. #define ADC_MODE_VAL_ULP1 0x09
  33. #define ADC_MODE_VAL_ULP2 0x0B
  34. enum {
  35. WCD9380 = 0,
  36. WCD9385,
  37. WCD9385FX,
  38. };
  39. enum {
  40. CODEC_TX = 0,
  41. CODEC_RX,
  42. };
  43. enum {
  44. WCD_ADC1 = 0,
  45. WCD_ADC2,
  46. WCD_ADC3,
  47. WCD_ADC4,
  48. ALLOW_BUCK_DISABLE,
  49. HPH_COMP_DELAY,
  50. HPH_PA_DELAY,
  51. };
  52. enum {
  53. ADC_MODE_INVALID = 0,
  54. ADC_MODE_HIFI,
  55. ADC_MODE_LO_HIF,
  56. ADC_MODE_NORMAL,
  57. ADC_MODE_LP,
  58. ADC_MODE_ULP1,
  59. ADC_MODE_ULP2,
  60. };
  61. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  62. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  63. static int wcd938x_handle_post_irq(void *data);
  64. static int wcd938x_reset(struct device *dev);
  65. static int wcd938x_reset_low(struct device *dev);
  66. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  87. };
  88. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  89. .name = "wcd938x",
  90. .irqs = wcd938x_irqs,
  91. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  92. .num_regs = 3,
  93. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  94. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  95. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  96. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  97. .use_ack = 1,
  98. .runtime_pm = false,
  99. .handle_post_irq = wcd938x_handle_post_irq,
  100. .irq_drv_data = NULL,
  101. };
  102. static int wcd938x_handle_post_irq(void *data)
  103. {
  104. struct wcd938x_priv *wcd938x = data;
  105. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  109. wcd938x->tx_swr_dev->slave_irq_pending =
  110. ((sts1 || sts2 || sts3) ? true : false);
  111. return IRQ_HANDLED;
  112. }
  113. static int wcd938x_init_reg(struct snd_soc_component *component)
  114. {
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  116. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  117. /* 1 msec delay as per HW requirement */
  118. usleep_range(1000, 1010);
  119. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  120. /* 1 msec delay as per HW requirement */
  121. usleep_range(1000, 1010);
  122. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  123. 0x10, 0x00);
  124. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  125. 0xF0, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  127. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  128. /* 10 msec delay as per HW requirement */
  129. usleep_range(10000, 10010);
  130. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  131. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  132. 0xFF, 0x3A);
  133. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  134. 0x0F, 0x02);
  135. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  136. 0x01, 0x01);
  137. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  138. 0x01, 0x01);
  139. snd_soc_component_update_bits(component,
  140. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  141. 0xF0, 0x00);
  142. snd_soc_component_update_bits(component,
  143. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  144. 0x1F, 0x15);
  145. snd_soc_component_update_bits(component,
  146. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  147. 0x1F, 0x15);
  148. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  149. 0xC0, 0x80);
  150. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  151. 0x02, 0x02);
  152. return 0;
  153. }
  154. static int wcd938x_set_port_params(struct snd_soc_component *component,
  155. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  156. u8 *ch_mask, u32 *ch_rate,
  157. u8 *port_type, u8 path)
  158. {
  159. int i, j;
  160. u8 num_ports;
  161. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  162. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  163. switch (path) {
  164. case CODEC_RX:
  165. map = &wcd938x->rx_port_mapping;
  166. num_ports = wcd938x->num_rx_ports;
  167. break;
  168. case CODEC_TX:
  169. map = &wcd938x->tx_port_mapping;
  170. num_ports = wcd938x->num_tx_ports;
  171. break;
  172. }
  173. for (i = 0; i <= num_ports; i++) {
  174. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  175. if ((*map)[i][j].slave_port_type == slv_prt_type)
  176. goto found;
  177. }
  178. }
  179. found:
  180. if (i > num_ports || j == MAX_CH_PER_PORT) {
  181. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  182. __func__, slv_prt_type);
  183. return -EINVAL;
  184. }
  185. *port_id = i;
  186. *num_ch = (*map)[i][j].num_ch;
  187. *ch_mask = (*map)[i][j].ch_mask;
  188. *ch_rate = (*map)[i][j].ch_rate;
  189. *port_type = (*map)[i][j].master_port_type;
  190. return 0;
  191. }
  192. static int wcd938x_parse_port_mapping(struct device *dev,
  193. char *prop, u8 path)
  194. {
  195. u32 *dt_array, map_size, map_length;
  196. u32 port_num, ch_mask, ch_rate, old_port_num = 0;
  197. u32 slave_port_type, master_port_type;
  198. u32 i, ch_iter = 0;
  199. int ret = 0;
  200. u8 *num_ports;
  201. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  202. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  203. switch (path) {
  204. case CODEC_RX:
  205. map = &wcd938x->rx_port_mapping;
  206. num_ports = &wcd938x->num_rx_ports;
  207. break;
  208. case CODEC_TX:
  209. map = &wcd938x->tx_port_mapping;
  210. num_ports = &wcd938x->num_tx_ports;
  211. break;
  212. }
  213. if (!of_find_property(dev->of_node, prop,
  214. &map_size)) {
  215. dev_err(dev, "missing port mapping prop %s\n", prop);
  216. ret = -EINVAL;
  217. goto err_port_map;
  218. }
  219. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  220. dt_array = kzalloc(map_size, GFP_KERNEL);
  221. if (!dt_array) {
  222. ret = -ENOMEM;
  223. goto err_alloc;
  224. }
  225. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  226. NUM_SWRS_DT_PARAMS * map_length);
  227. if (ret) {
  228. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  229. __func__, prop);
  230. goto err_pdata_fail;
  231. }
  232. for (i = 0; i < map_length; i++) {
  233. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  234. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  235. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  236. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  237. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  238. if (port_num != old_port_num)
  239. ch_iter = 0;
  240. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  241. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  242. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  243. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  244. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  245. old_port_num = port_num;
  246. }
  247. *num_ports = port_num;
  248. kfree(dt_array);
  249. return 0;
  250. err_pdata_fail:
  251. kfree(dt_array);
  252. err_alloc:
  253. err_port_map:
  254. return ret;
  255. }
  256. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  257. u8 slv_port_type, u8 enable)
  258. {
  259. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  260. u8 port_id, num_ch, ch_mask, port_type;
  261. u32 ch_rate;
  262. u8 num_port = 1;
  263. int ret = 0;
  264. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  265. &num_ch, &ch_mask, &ch_rate,
  266. &port_type, CODEC_TX);
  267. if (ret)
  268. return ret;
  269. if (enable)
  270. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  271. num_port, &ch_mask, &ch_rate,
  272. &num_ch, &port_type);
  273. else
  274. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  275. num_port, &ch_mask, &port_type);
  276. return ret;
  277. }
  278. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  279. u8 slv_port_type, u8 enable)
  280. {
  281. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  282. u8 port_id, num_ch, ch_mask, port_type;
  283. u32 ch_rate;
  284. u8 num_port = 1;
  285. int ret = 0;
  286. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  287. &num_ch, &ch_mask, &ch_rate,
  288. &port_type, CODEC_RX);
  289. if (ret)
  290. return ret;
  291. if (enable)
  292. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  293. num_port, &ch_mask, &ch_rate,
  294. &num_ch, &port_type);
  295. else
  296. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  297. num_port, &ch_mask, &port_type);
  298. return ret;
  299. }
  300. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  301. {
  302. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  303. if (wcd938x->rx_clk_cnt == 0) {
  304. snd_soc_component_update_bits(component,
  305. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  306. snd_soc_component_update_bits(component,
  307. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  308. snd_soc_component_update_bits(component,
  309. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  310. snd_soc_component_update_bits(component,
  311. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  312. snd_soc_component_update_bits(component,
  313. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  314. snd_soc_component_update_bits(component,
  315. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  316. }
  317. wcd938x->rx_clk_cnt++;
  318. return 0;
  319. }
  320. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  321. {
  322. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  323. wcd938x->rx_clk_cnt--;
  324. if (wcd938x->rx_clk_cnt == 0) {
  325. snd_soc_component_update_bits(component,
  326. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  327. snd_soc_component_update_bits(component,
  328. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  329. snd_soc_component_update_bits(component,
  330. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  331. snd_soc_component_update_bits(component,
  332. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  333. snd_soc_component_update_bits(component,
  334. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  335. }
  336. return 0;
  337. }
  338. /*
  339. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  340. * @component: handle to snd_soc_component *
  341. *
  342. * return wcd938x_mbhc handle or error code in case of failure
  343. */
  344. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  345. {
  346. struct wcd938x_priv *wcd938x;
  347. if (!component) {
  348. pr_err("%s: Invalid params, NULL component\n", __func__);
  349. return NULL;
  350. }
  351. wcd938x = snd_soc_component_get_drvdata(component);
  352. if (!wcd938x) {
  353. pr_err("%s: wcd938x is NULL\n", __func__);
  354. return NULL;
  355. }
  356. return wcd938x->mbhc;
  357. }
  358. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  359. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  360. struct snd_kcontrol *kcontrol,
  361. int event)
  362. {
  363. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  364. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  365. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  366. w->name, event);
  367. switch (event) {
  368. case SND_SOC_DAPM_PRE_PMU:
  369. wcd938x_rx_clk_enable(component);
  370. snd_soc_component_update_bits(component,
  371. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  372. snd_soc_component_update_bits(component,
  373. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  374. snd_soc_component_update_bits(component,
  375. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  376. break;
  377. case SND_SOC_DAPM_POST_PMU:
  378. snd_soc_component_update_bits(component,
  379. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  380. if (wcd938x->comp1_enable) {
  381. snd_soc_component_update_bits(component,
  382. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  383. /* 5msec compander delay as per HW requirement */
  384. if (!wcd938x->comp2_enable ||
  385. (snd_soc_component_read32(component,
  386. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  387. usleep_range(5000, 5010);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  390. } else {
  391. snd_soc_component_update_bits(component,
  392. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  393. 0x02, 0x00);
  394. snd_soc_component_update_bits(component,
  395. WCD938X_HPH_L_EN, 0x20, 0x20);
  396. }
  397. break;
  398. case SND_SOC_DAPM_POST_PMD:
  399. snd_soc_component_update_bits(component,
  400. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  401. 0x0F, 0x01);
  402. break;
  403. }
  404. return 0;
  405. }
  406. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  407. struct snd_kcontrol *kcontrol,
  408. int event)
  409. {
  410. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  411. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  412. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  413. w->name, event);
  414. switch (event) {
  415. case SND_SOC_DAPM_PRE_PMU:
  416. wcd938x_rx_clk_enable(component);
  417. snd_soc_component_update_bits(component,
  418. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  419. snd_soc_component_update_bits(component,
  420. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  421. snd_soc_component_update_bits(component,
  422. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  423. break;
  424. case SND_SOC_DAPM_POST_PMU:
  425. snd_soc_component_update_bits(component,
  426. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  427. if (wcd938x->comp2_enable) {
  428. snd_soc_component_update_bits(component,
  429. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  430. /* 5msec compander delay as per HW requirement */
  431. if (!wcd938x->comp1_enable ||
  432. (snd_soc_component_read32(component,
  433. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  434. usleep_range(5000, 5010);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  437. } else {
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  440. 0x01, 0x00);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_HPH_R_EN, 0x20, 0x20);
  443. }
  444. break;
  445. case SND_SOC_DAPM_POST_PMD:
  446. snd_soc_component_update_bits(component,
  447. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  448. 0x0F, 0x01);
  449. break;
  450. }
  451. return 0;
  452. }
  453. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  454. struct snd_kcontrol *kcontrol,
  455. int event)
  456. {
  457. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  458. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  459. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  460. w->name, event);
  461. switch (event) {
  462. case SND_SOC_DAPM_PRE_PMU:
  463. wcd938x_rx_clk_enable(component);
  464. snd_soc_component_update_bits(component,
  465. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  466. snd_soc_component_update_bits(component,
  467. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  468. snd_soc_component_update_bits(component,
  469. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  470. /* 5 msec delay as per HW requirement */
  471. usleep_range(5000, 5010);
  472. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  473. 0x04, 0x00);
  474. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  475. WCD_CLSH_EVENT_PRE_DAC,
  476. WCD_CLSH_STATE_EAR,
  477. wcd938x->hph_mode);
  478. break;
  479. case SND_SOC_DAPM_POST_PMD:
  480. break;
  481. };
  482. return 0;
  483. }
  484. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  485. struct snd_kcontrol *kcontrol,
  486. int event)
  487. {
  488. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  489. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  490. int ret = 0;
  491. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  492. w->name, event);
  493. switch (event) {
  494. case SND_SOC_DAPM_PRE_PMU:
  495. wcd938x_rx_clk_enable(component);
  496. snd_soc_component_update_bits(component,
  497. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  498. snd_soc_component_update_bits(component,
  499. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  500. snd_soc_component_update_bits(component,
  501. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  502. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  503. WCD_CLSH_EVENT_PRE_DAC,
  504. WCD_CLSH_STATE_AUX,
  505. wcd938x->hph_mode);
  506. break;
  507. case SND_SOC_DAPM_POST_PMD:
  508. wcd938x_rx_clk_disable(component);
  509. snd_soc_component_update_bits(component,
  510. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  511. break;
  512. };
  513. return ret;
  514. }
  515. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  516. struct snd_kcontrol *kcontrol,
  517. int event)
  518. {
  519. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  520. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  521. int ret = 0;
  522. int hph_mode = wcd938x->hph_mode;
  523. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  524. w->name, event);
  525. switch (event) {
  526. case SND_SOC_DAPM_PRE_PMU:
  527. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  528. wcd938x->rx_swr_dev->dev_num,
  529. true);
  530. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  531. WCD_CLSH_EVENT_PRE_DAC,
  532. WCD_CLSH_STATE_HPHR,
  533. hph_mode);
  534. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  535. 0x10, 0x10);
  536. /* 100 usec delay as per HW requirement */
  537. usleep_range(100, 110);
  538. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  539. break;
  540. case SND_SOC_DAPM_POST_PMU:
  541. /*
  542. * 7ms sleep is required if compander is enabled as per
  543. * HW requirement. If compander is disabled, then
  544. * 20ms delay is required.
  545. */
  546. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  547. if (!wcd938x->comp2_enable)
  548. usleep_range(20000, 20100);
  549. else
  550. usleep_range(7000, 7100);
  551. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  552. }
  553. snd_soc_component_update_bits(component,
  554. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  555. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  556. snd_soc_component_update_bits(component,
  557. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  558. if (wcd938x->update_wcd_event)
  559. wcd938x->update_wcd_event(wcd938x->handle,
  560. WCD_BOLERO_EVT_RX_MUTE,
  561. (WCD_RX2 << 0x10));
  562. break;
  563. case SND_SOC_DAPM_PRE_PMD:
  564. if (wcd938x->update_wcd_event)
  565. wcd938x->update_wcd_event(wcd938x->handle,
  566. WCD_BOLERO_EVT_RX_MUTE,
  567. (WCD_RX2 << 0x10 | 0x1));
  568. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  569. WCD_EVENT_PRE_HPHR_PA_OFF,
  570. &wcd938x->mbhc->wcd_mbhc);
  571. break;
  572. case SND_SOC_DAPM_POST_PMD:
  573. /* 7 msec delay as per HW requirement */
  574. usleep_range(7000, 7010);
  575. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  576. WCD_EVENT_POST_HPHR_PA_OFF,
  577. &wcd938x->mbhc->wcd_mbhc);
  578. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  579. 0x10, 0x00);
  580. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  581. WCD_CLSH_EVENT_POST_PA,
  582. WCD_CLSH_STATE_HPHR,
  583. hph_mode);
  584. break;
  585. };
  586. return ret;
  587. }
  588. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  589. struct snd_kcontrol *kcontrol,
  590. int event)
  591. {
  592. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  593. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  594. int ret = 0;
  595. int hph_mode = wcd938x->hph_mode;
  596. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  597. w->name, event);
  598. switch (event) {
  599. case SND_SOC_DAPM_PRE_PMU:
  600. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  601. wcd938x->rx_swr_dev->dev_num,
  602. true);
  603. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  604. WCD_CLSH_EVENT_PRE_DAC,
  605. WCD_CLSH_STATE_HPHL,
  606. hph_mode);
  607. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  608. 0x20, 0x20);
  609. /* 100 usec delay as per HW requirement */
  610. usleep_range(100, 110);
  611. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  612. break;
  613. case SND_SOC_DAPM_POST_PMU:
  614. /*
  615. * 7ms sleep is required if compander is enabled as per
  616. * HW requirement. If compander is disabled, then
  617. * 20ms delay is required.
  618. */
  619. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  620. if (!wcd938x->comp1_enable)
  621. usleep_range(20000, 20100);
  622. else
  623. usleep_range(7000, 7100);
  624. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  625. }
  626. snd_soc_component_update_bits(component,
  627. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  628. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  629. snd_soc_component_update_bits(component,
  630. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  631. if (wcd938x->update_wcd_event)
  632. wcd938x->update_wcd_event(wcd938x->handle,
  633. WCD_BOLERO_EVT_RX_MUTE,
  634. (WCD_RX1 << 0x10));
  635. break;
  636. case SND_SOC_DAPM_PRE_PMD:
  637. if (wcd938x->update_wcd_event)
  638. wcd938x->update_wcd_event(wcd938x->handle,
  639. WCD_BOLERO_EVT_RX_MUTE,
  640. (WCD_RX1 << 0x10 | 0x1));
  641. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  642. WCD_EVENT_PRE_HPHL_PA_OFF,
  643. &wcd938x->mbhc->wcd_mbhc);
  644. break;
  645. case SND_SOC_DAPM_POST_PMD:
  646. /* 7 msec delay as per HW requirement */
  647. usleep_range(7000, 7010);
  648. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  649. WCD_EVENT_POST_HPHL_PA_OFF,
  650. &wcd938x->mbhc->wcd_mbhc);
  651. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  652. 0x20, 0x00);
  653. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  654. WCD_CLSH_EVENT_POST_PA,
  655. WCD_CLSH_STATE_HPHL,
  656. hph_mode);
  657. break;
  658. };
  659. return ret;
  660. }
  661. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  662. struct snd_kcontrol *kcontrol,
  663. int event)
  664. {
  665. struct snd_soc_component *component =
  666. snd_soc_dapm_to_component(w->dapm);
  667. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  668. int hph_mode = wcd938x->hph_mode;
  669. int ret = 0;
  670. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  671. w->name, event);
  672. switch (event) {
  673. case SND_SOC_DAPM_PRE_PMU:
  674. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  675. wcd938x->rx_swr_dev->dev_num,
  676. true);
  677. break;
  678. case SND_SOC_DAPM_POST_PMU:
  679. /* 1 msec delay as per HW requirement */
  680. usleep_range(1000, 1010);
  681. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  682. snd_soc_component_update_bits(component,
  683. WCD938X_ANA_RX_SUPPLIES,
  684. 0x20, 0x20);
  685. if (wcd938x->update_wcd_event)
  686. wcd938x->update_wcd_event(wcd938x->handle,
  687. WCD_BOLERO_EVT_RX_MUTE,
  688. (WCD_RX3 << 0x10));
  689. break;
  690. case SND_SOC_DAPM_PRE_PMD:
  691. if (wcd938x->update_wcd_event)
  692. wcd938x->update_wcd_event(wcd938x->handle,
  693. WCD_BOLERO_EVT_RX_MUTE,
  694. (WCD_RX3 << 0x10 | 0x1));
  695. break;
  696. case SND_SOC_DAPM_POST_PMD:
  697. /* 1 msec delay as per HW requirement */
  698. usleep_range(1000, 1010);
  699. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  700. WCD_CLSH_EVENT_POST_PA,
  701. WCD_CLSH_STATE_AUX,
  702. hph_mode);
  703. break;
  704. };
  705. return ret;
  706. }
  707. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  708. struct snd_kcontrol *kcontrol,
  709. int event)
  710. {
  711. struct snd_soc_component *component =
  712. snd_soc_dapm_to_component(w->dapm);
  713. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  714. int hph_mode = wcd938x->hph_mode;
  715. int ret = 0;
  716. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  717. w->name, event);
  718. switch (event) {
  719. case SND_SOC_DAPM_PRE_PMU:
  720. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  721. wcd938x->rx_swr_dev->dev_num,
  722. true);
  723. break;
  724. case SND_SOC_DAPM_POST_PMU:
  725. /* 6 msec delay as per HW requirement */
  726. usleep_range(6000, 6010);
  727. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  728. snd_soc_component_update_bits(component,
  729. WCD938X_ANA_RX_SUPPLIES,
  730. 0x02, 0x02);
  731. if (wcd938x->update_wcd_event)
  732. wcd938x->update_wcd_event(wcd938x->handle,
  733. WCD_BOLERO_EVT_RX_MUTE,
  734. (WCD_RX1 << 0x10));
  735. break;
  736. case SND_SOC_DAPM_PRE_PMD:
  737. if (wcd938x->update_wcd_event)
  738. wcd938x->update_wcd_event(wcd938x->handle,
  739. WCD_BOLERO_EVT_RX_MUTE,
  740. (WCD_RX1 << 0x10 | 0x1));
  741. break;
  742. case SND_SOC_DAPM_POST_PMD:
  743. /* 7 msec delay as per HW requirement */
  744. usleep_range(7000, 7010);
  745. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  746. WCD_CLSH_EVENT_POST_PA,
  747. WCD_CLSH_STATE_EAR,
  748. hph_mode);
  749. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  750. 0x04, 0x04);
  751. break;
  752. };
  753. return ret;
  754. }
  755. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  756. struct snd_kcontrol *kcontrol,
  757. int event)
  758. {
  759. struct snd_soc_component *component =
  760. snd_soc_dapm_to_component(w->dapm);
  761. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  762. int mode = wcd938x->hph_mode;
  763. int ret = 0;
  764. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  765. w->name, event);
  766. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  767. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  768. wcd938x_rx_connect_port(component, CLSH,
  769. SND_SOC_DAPM_EVENT_ON(event));
  770. }
  771. if (SND_SOC_DAPM_EVENT_OFF(event))
  772. ret = swr_slvdev_datapath_control(
  773. wcd938x->rx_swr_dev,
  774. wcd938x->rx_swr_dev->dev_num,
  775. false);
  776. return ret;
  777. }
  778. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  779. struct snd_kcontrol *kcontrol,
  780. int event)
  781. {
  782. struct snd_soc_component *component =
  783. snd_soc_dapm_to_component(w->dapm);
  784. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  785. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  786. w->name, event);
  787. switch (event) {
  788. case SND_SOC_DAPM_PRE_PMU:
  789. wcd938x_rx_connect_port(component, HPH_L, true);
  790. if (wcd938x->comp1_enable)
  791. wcd938x_rx_connect_port(component, COMP_L, true);
  792. break;
  793. case SND_SOC_DAPM_POST_PMD:
  794. wcd938x_rx_connect_port(component, HPH_L, false);
  795. if (wcd938x->comp1_enable)
  796. wcd938x_rx_connect_port(component, COMP_L, false);
  797. wcd938x_rx_clk_disable(component);
  798. snd_soc_component_update_bits(component,
  799. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  800. 0x01, 0x00);
  801. break;
  802. };
  803. return 0;
  804. }
  805. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  806. struct snd_kcontrol *kcontrol, int event)
  807. {
  808. struct snd_soc_component *component =
  809. snd_soc_dapm_to_component(w->dapm);
  810. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  811. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  812. w->name, event);
  813. switch (event) {
  814. case SND_SOC_DAPM_PRE_PMU:
  815. wcd938x_rx_connect_port(component, HPH_R, true);
  816. if (wcd938x->comp2_enable)
  817. wcd938x_rx_connect_port(component, COMP_R, true);
  818. break;
  819. case SND_SOC_DAPM_POST_PMD:
  820. wcd938x_rx_connect_port(component, HPH_R, false);
  821. if (wcd938x->comp2_enable)
  822. wcd938x_rx_connect_port(component, COMP_R, false);
  823. wcd938x_rx_clk_disable(component);
  824. snd_soc_component_update_bits(component,
  825. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  826. 0x02, 0x00);
  827. break;
  828. };
  829. return 0;
  830. }
  831. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  832. struct snd_kcontrol *kcontrol,
  833. int event)
  834. {
  835. struct snd_soc_component *component =
  836. snd_soc_dapm_to_component(w->dapm);
  837. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  838. w->name, event);
  839. switch (event) {
  840. case SND_SOC_DAPM_PRE_PMU:
  841. wcd938x_rx_connect_port(component, LO, true);
  842. break;
  843. case SND_SOC_DAPM_POST_PMD:
  844. wcd938x_rx_connect_port(component, LO, false);
  845. /* 6 msec delay as per HW requirement */
  846. usleep_range(6000, 6010);
  847. wcd938x_rx_clk_disable(component);
  848. snd_soc_component_update_bits(component,
  849. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  850. break;
  851. }
  852. return 0;
  853. }
  854. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  855. struct snd_kcontrol *kcontrol,
  856. int event)
  857. {
  858. struct snd_soc_component *component =
  859. snd_soc_dapm_to_component(w->dapm);
  860. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  861. u16 dmic_clk_reg;
  862. s32 *dmic_clk_cnt;
  863. unsigned int dmic;
  864. char *wname;
  865. int ret = 0;
  866. wname = strpbrk(w->name, "012345");
  867. if (!wname) {
  868. dev_err(component->dev, "%s: widget not found\n", __func__);
  869. return -EINVAL;
  870. }
  871. ret = kstrtouint(wname, 10, &dmic);
  872. if (ret < 0) {
  873. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  874. __func__);
  875. return -EINVAL;
  876. }
  877. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  878. w->name, event);
  879. switch (dmic) {
  880. case 0:
  881. case 1:
  882. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  883. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  884. break;
  885. case 2:
  886. case 3:
  887. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  888. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  889. break;
  890. case 4:
  891. case 5:
  892. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  893. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  894. break;
  895. case 6:
  896. case 7:
  897. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  898. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  899. break;
  900. default:
  901. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  902. __func__);
  903. return -EINVAL;
  904. };
  905. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  906. __func__, event, dmic, *dmic_clk_cnt);
  907. switch (event) {
  908. case SND_SOC_DAPM_PRE_PMU:
  909. snd_soc_component_update_bits(component,
  910. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  911. /* enable clock scaling */
  912. snd_soc_component_update_bits(component,
  913. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  914. snd_soc_component_update_bits(component,
  915. dmic_clk_reg, 0x07, 0x02);
  916. snd_soc_component_update_bits(component,
  917. dmic_clk_reg, 0x08, 0x08);
  918. snd_soc_component_update_bits(component,
  919. dmic_clk_reg, 0x70, 0x20);
  920. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  921. break;
  922. case SND_SOC_DAPM_POST_PMD:
  923. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  924. break;
  925. };
  926. return 0;
  927. }
  928. /*
  929. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  930. * @micb_mv: micbias in mv
  931. *
  932. * return register value converted
  933. */
  934. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  935. {
  936. /* min micbias voltage is 1V and maximum is 2.85V */
  937. if (micb_mv < 1000 || micb_mv > 2850) {
  938. pr_err("%s: unsupported micbias voltage\n", __func__);
  939. return -EINVAL;
  940. }
  941. return (micb_mv - 1000) / 50;
  942. }
  943. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  944. /*
  945. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  946. * @component: handle to snd_soc_component *
  947. * @req_volt: micbias voltage to be set
  948. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  949. *
  950. * return 0 if adjustment is success or error code in case of failure
  951. */
  952. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  953. int req_volt, int micb_num)
  954. {
  955. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  956. int cur_vout_ctl, req_vout_ctl;
  957. int micb_reg, micb_val, micb_en;
  958. int ret = 0;
  959. switch (micb_num) {
  960. case MIC_BIAS_1:
  961. micb_reg = WCD938X_ANA_MICB1;
  962. break;
  963. case MIC_BIAS_2:
  964. micb_reg = WCD938X_ANA_MICB2;
  965. break;
  966. case MIC_BIAS_3:
  967. micb_reg = WCD938X_ANA_MICB3;
  968. break;
  969. case MIC_BIAS_4:
  970. micb_reg = WCD938X_ANA_MICB4;
  971. break;
  972. default:
  973. return -EINVAL;
  974. }
  975. mutex_lock(&wcd938x->micb_lock);
  976. /*
  977. * If requested micbias voltage is same as current micbias
  978. * voltage, then just return. Otherwise, adjust voltage as
  979. * per requested value. If micbias is already enabled, then
  980. * to avoid slow micbias ramp-up or down enable pull-up
  981. * momentarily, change the micbias value and then re-enable
  982. * micbias.
  983. */
  984. micb_val = snd_soc_component_read32(component, micb_reg);
  985. micb_en = (micb_val & 0xC0) >> 6;
  986. cur_vout_ctl = micb_val & 0x3F;
  987. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  988. if (req_vout_ctl < 0) {
  989. ret = -EINVAL;
  990. goto exit;
  991. }
  992. if (cur_vout_ctl == req_vout_ctl) {
  993. ret = 0;
  994. goto exit;
  995. }
  996. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  997. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  998. req_volt, micb_en);
  999. if (micb_en == 0x1)
  1000. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1001. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1002. if (micb_en == 0x1) {
  1003. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1004. /*
  1005. * Add 2ms delay as per HW requirement after enabling
  1006. * micbias
  1007. */
  1008. usleep_range(2000, 2100);
  1009. }
  1010. exit:
  1011. mutex_unlock(&wcd938x->micb_lock);
  1012. return ret;
  1013. }
  1014. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1015. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1016. struct snd_kcontrol *kcontrol,
  1017. int event)
  1018. {
  1019. struct snd_soc_component *component =
  1020. snd_soc_dapm_to_component(w->dapm);
  1021. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1022. int ret = 0;
  1023. switch (event) {
  1024. case SND_SOC_DAPM_PRE_PMU:
  1025. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1026. wcd938x->tx_swr_dev->dev_num,
  1027. true);
  1028. break;
  1029. case SND_SOC_DAPM_POST_PMD:
  1030. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1031. wcd938x->tx_swr_dev->dev_num,
  1032. false);
  1033. break;
  1034. };
  1035. return ret;
  1036. }
  1037. static int wcd938x_get_adc_mode(int val)
  1038. {
  1039. int ret = 0;
  1040. switch (val) {
  1041. case ADC_MODE_INVALID:
  1042. ret = ADC_MODE_VAL_NORMAL;
  1043. break;
  1044. case ADC_MODE_HIFI:
  1045. ret = ADC_MODE_VAL_HIFI;
  1046. break;
  1047. case ADC_MODE_LO_HIF:
  1048. ret = ADC_MODE_VAL_LO_HIF;
  1049. break;
  1050. case ADC_MODE_NORMAL:
  1051. ret = ADC_MODE_VAL_NORMAL;
  1052. break;
  1053. case ADC_MODE_LP:
  1054. ret = ADC_MODE_VAL_LP;
  1055. break;
  1056. case ADC_MODE_ULP1:
  1057. ret = ADC_MODE_VAL_ULP1;
  1058. break;
  1059. case ADC_MODE_ULP2:
  1060. ret = ADC_MODE_VAL_ULP2;
  1061. break;
  1062. default:
  1063. ret = -EINVAL;
  1064. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1065. break;
  1066. }
  1067. return ret;
  1068. }
  1069. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1070. struct snd_kcontrol *kcontrol,
  1071. int event){
  1072. int mode;
  1073. struct snd_soc_component *component =
  1074. snd_soc_dapm_to_component(w->dapm);
  1075. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1076. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1077. w->name, event);
  1078. switch (event) {
  1079. case SND_SOC_DAPM_PRE_PMU:
  1080. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1081. if (mode < 0) {
  1082. dev_info(component->dev,
  1083. "%s: invalid mode, setting to normal mode\n",
  1084. __func__);
  1085. mode = ADC_MODE_VAL_NORMAL;
  1086. }
  1087. snd_soc_component_update_bits(component,
  1088. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1089. snd_soc_component_update_bits(component,
  1090. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1091. snd_soc_component_update_bits(component,
  1092. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1093. switch (w->shift) {
  1094. case 0:
  1095. snd_soc_component_update_bits(component,
  1096. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1097. mode);
  1098. break;
  1099. case 1:
  1100. snd_soc_component_update_bits(component,
  1101. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1102. mode << 4);
  1103. break;
  1104. case 2:
  1105. snd_soc_component_update_bits(component,
  1106. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1107. mode);
  1108. break;
  1109. case 3:
  1110. snd_soc_component_update_bits(component,
  1111. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1112. mode << 4);
  1113. break;
  1114. default:
  1115. break;
  1116. }
  1117. set_bit(w->shift, &wcd938x->status_mask);
  1118. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1119. break;
  1120. case SND_SOC_DAPM_POST_PMD:
  1121. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1122. snd_soc_component_update_bits(component,
  1123. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1124. clear_bit(w->shift, &wcd938x->status_mask);
  1125. break;
  1126. };
  1127. return 0;
  1128. }
  1129. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1130. int channel, int mode)
  1131. {
  1132. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1133. int ret = 0;
  1134. switch (channel) {
  1135. case 0:
  1136. reg = WCD938X_ANA_TX_CH2;
  1137. mask = 0x40;
  1138. break;
  1139. case 1:
  1140. reg = WCD938X_ANA_TX_CH2;
  1141. mask = 0x20;
  1142. break;
  1143. case 2:
  1144. reg = WCD938X_ANA_TX_CH4;
  1145. mask = 0x40;
  1146. break;
  1147. case 3:
  1148. reg = WCD938X_ANA_TX_CH4;
  1149. mask = 0x20;
  1150. break;
  1151. default:
  1152. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1153. ret = -EINVAL;
  1154. break;
  1155. }
  1156. if (!mode)
  1157. val = 0x00;
  1158. else
  1159. val = mask;
  1160. if (!ret)
  1161. snd_soc_component_update_bits(component, reg, mask, val);
  1162. return ret;
  1163. }
  1164. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1165. struct snd_kcontrol *kcontrol, int event)
  1166. {
  1167. struct snd_soc_component *component =
  1168. snd_soc_dapm_to_component(w->dapm);
  1169. int ret = 0;
  1170. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1171. w->name, event);
  1172. switch (event) {
  1173. case SND_SOC_DAPM_PRE_PMU:
  1174. snd_soc_component_update_bits(component,
  1175. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1176. snd_soc_component_update_bits(component,
  1177. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1178. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1179. snd_soc_component_update_bits(component,
  1180. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1181. snd_soc_component_update_bits(component,
  1182. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1183. snd_soc_component_update_bits(component,
  1184. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1185. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1186. break;
  1187. case SND_SOC_DAPM_POST_PMD:
  1188. snd_soc_component_update_bits(component,
  1189. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1190. snd_soc_component_update_bits(component,
  1191. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1192. snd_soc_component_update_bits(component,
  1193. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1194. snd_soc_component_update_bits(component,
  1195. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1196. snd_soc_component_update_bits(component,
  1197. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1198. break;
  1199. };
  1200. return ret;
  1201. }
  1202. int wcd938x_micbias_control(struct snd_soc_component *component,
  1203. int micb_num, int req, bool is_dapm)
  1204. {
  1205. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1206. int micb_index = micb_num - 1;
  1207. u16 micb_reg;
  1208. int pre_off_event = 0, post_off_event = 0;
  1209. int post_on_event = 0, post_dapm_off = 0;
  1210. int post_dapm_on = 0;
  1211. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1212. dev_err(component->dev,
  1213. "%s: Invalid micbias index, micb_ind:%d\n",
  1214. __func__, micb_index);
  1215. return -EINVAL;
  1216. }
  1217. switch (micb_num) {
  1218. case MIC_BIAS_1:
  1219. micb_reg = WCD938X_ANA_MICB1;
  1220. break;
  1221. case MIC_BIAS_2:
  1222. micb_reg = WCD938X_ANA_MICB2;
  1223. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1224. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1225. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1226. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1227. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1228. break;
  1229. case MIC_BIAS_3:
  1230. micb_reg = WCD938X_ANA_MICB3;
  1231. break;
  1232. case MIC_BIAS_4:
  1233. micb_reg = WCD938X_ANA_MICB4;
  1234. break;
  1235. default:
  1236. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1237. __func__, micb_num);
  1238. return -EINVAL;
  1239. };
  1240. mutex_lock(&wcd938x->micb_lock);
  1241. switch (req) {
  1242. case MICB_PULLUP_ENABLE:
  1243. wcd938x->pullup_ref[micb_index]++;
  1244. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1245. (wcd938x->micb_ref[micb_index] == 0))
  1246. snd_soc_component_update_bits(component, micb_reg,
  1247. 0xC0, 0x80);
  1248. break;
  1249. case MICB_PULLUP_DISABLE:
  1250. if (wcd938x->pullup_ref[micb_index] > 0)
  1251. wcd938x->pullup_ref[micb_index]--;
  1252. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1253. (wcd938x->micb_ref[micb_index] == 0))
  1254. snd_soc_component_update_bits(component, micb_reg,
  1255. 0xC0, 0x00);
  1256. break;
  1257. case MICB_ENABLE:
  1258. wcd938x->micb_ref[micb_index]++;
  1259. if (wcd938x->micb_ref[micb_index] == 1) {
  1260. snd_soc_component_update_bits(component,
  1261. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1262. snd_soc_component_update_bits(component,
  1263. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1264. snd_soc_component_update_bits(component,
  1265. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1266. snd_soc_component_update_bits(component,
  1267. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1268. snd_soc_component_update_bits(component,
  1269. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1270. snd_soc_component_update_bits(component,
  1271. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1272. snd_soc_component_update_bits(component,
  1273. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1274. snd_soc_component_update_bits(component,
  1275. micb_reg, 0xC0, 0x40);
  1276. if (post_on_event)
  1277. blocking_notifier_call_chain(
  1278. &wcd938x->mbhc->notifier,
  1279. post_on_event,
  1280. &wcd938x->mbhc->wcd_mbhc);
  1281. }
  1282. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1283. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1284. post_dapm_on,
  1285. &wcd938x->mbhc->wcd_mbhc);
  1286. break;
  1287. case MICB_DISABLE:
  1288. if (wcd938x->micb_ref[micb_index] > 0)
  1289. wcd938x->micb_ref[micb_index]--;
  1290. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1291. (wcd938x->pullup_ref[micb_index] > 0))
  1292. snd_soc_component_update_bits(component, micb_reg,
  1293. 0xC0, 0x80);
  1294. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1295. (wcd938x->pullup_ref[micb_index] == 0)) {
  1296. if (pre_off_event && wcd938x->mbhc)
  1297. blocking_notifier_call_chain(
  1298. &wcd938x->mbhc->notifier,
  1299. pre_off_event,
  1300. &wcd938x->mbhc->wcd_mbhc);
  1301. snd_soc_component_update_bits(component, micb_reg,
  1302. 0xC0, 0x00);
  1303. if (post_off_event && wcd938x->mbhc)
  1304. blocking_notifier_call_chain(
  1305. &wcd938x->mbhc->notifier,
  1306. post_off_event,
  1307. &wcd938x->mbhc->wcd_mbhc);
  1308. }
  1309. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1310. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1311. post_dapm_off,
  1312. &wcd938x->mbhc->wcd_mbhc);
  1313. break;
  1314. };
  1315. dev_dbg(component->dev,
  1316. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1317. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1318. wcd938x->pullup_ref[micb_index]);
  1319. mutex_unlock(&wcd938x->micb_lock);
  1320. return 0;
  1321. }
  1322. EXPORT_SYMBOL(wcd938x_micbias_control);
  1323. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1324. {
  1325. int ret = 0;
  1326. uint8_t devnum = 0;
  1327. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1328. if (ret) {
  1329. dev_err(&swr_dev->dev,
  1330. "%s get devnum %d for dev addr %lx failed\n",
  1331. __func__, devnum, swr_dev->addr);
  1332. swr_remove_device(swr_dev);
  1333. return ret;
  1334. }
  1335. swr_dev->dev_num = devnum;
  1336. return 0;
  1337. }
  1338. static int wcd938x_event_notify(struct notifier_block *block,
  1339. unsigned long val,
  1340. void *data)
  1341. {
  1342. u16 event = (val & 0xffff);
  1343. int ret = 0;
  1344. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1345. struct snd_soc_component *component = wcd938x->component;
  1346. struct wcd_mbhc *mbhc;
  1347. switch (event) {
  1348. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1349. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1350. snd_soc_component_update_bits(component,
  1351. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1352. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1353. }
  1354. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1355. snd_soc_component_update_bits(component,
  1356. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1357. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1358. }
  1359. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1360. snd_soc_component_update_bits(component,
  1361. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1362. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1363. }
  1364. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1365. snd_soc_component_update_bits(component,
  1366. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1367. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1368. }
  1369. break;
  1370. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1371. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1372. 0xC0, 0x00);
  1373. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1374. 0x80, 0x00);
  1375. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1376. 0x80, 0x00);
  1377. break;
  1378. case BOLERO_WCD_EVT_SSR_DOWN:
  1379. wcd938x_reset_low(wcd938x->dev);
  1380. break;
  1381. case BOLERO_WCD_EVT_SSR_UP:
  1382. wcd938x_reset(wcd938x->dev);
  1383. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1384. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1385. regcache_mark_dirty(wcd938x->regmap);
  1386. regcache_sync(wcd938x->regmap);
  1387. /* Initialize MBHC module */
  1388. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1389. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1390. if (ret) {
  1391. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1392. __func__);
  1393. } else {
  1394. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1395. }
  1396. break;
  1397. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1398. snd_soc_component_update_bits(component,
  1399. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1400. ((val >> 0x10) << 0x01));
  1401. break;
  1402. default:
  1403. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1404. break;
  1405. }
  1406. return 0;
  1407. }
  1408. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1409. int event)
  1410. {
  1411. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1412. int micb_num;
  1413. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1414. __func__, w->name, event);
  1415. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1416. micb_num = MIC_BIAS_1;
  1417. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1418. micb_num = MIC_BIAS_2;
  1419. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1420. micb_num = MIC_BIAS_3;
  1421. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1422. micb_num = MIC_BIAS_4;
  1423. else
  1424. return -EINVAL;
  1425. switch (event) {
  1426. case SND_SOC_DAPM_PRE_PMU:
  1427. wcd938x_micbias_control(component, micb_num,
  1428. MICB_ENABLE, true);
  1429. break;
  1430. case SND_SOC_DAPM_POST_PMU:
  1431. /* 1 msec delay as per HW requirement */
  1432. usleep_range(1000, 1100);
  1433. break;
  1434. case SND_SOC_DAPM_POST_PMD:
  1435. wcd938x_micbias_control(component, micb_num,
  1436. MICB_DISABLE, true);
  1437. break;
  1438. };
  1439. return 0;
  1440. }
  1441. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1442. struct snd_kcontrol *kcontrol,
  1443. int event)
  1444. {
  1445. return __wcd938x_codec_enable_micbias(w, event);
  1446. }
  1447. static inline int wcd938x_tx_path_get(const char *wname)
  1448. {
  1449. int ret = 0;
  1450. unsigned int path_num;
  1451. char *widget_name = NULL;
  1452. char *w_name = NULL;
  1453. char *path_num_char = NULL;
  1454. char *path_name = NULL;
  1455. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1456. if (!widget_name)
  1457. return -EINVAL;
  1458. w_name = widget_name;
  1459. path_name = strsep(&widget_name, " ");
  1460. if (!path_name) {
  1461. pr_err("%s: Invalid widget name = %s\n",
  1462. __func__, widget_name);
  1463. ret = -EINVAL;
  1464. goto err;
  1465. }
  1466. path_name = widget_name;
  1467. path_num_char = strpbrk(path_name, "0123");
  1468. if (!path_num_char) {
  1469. pr_err("%s: tx path index not found\n",
  1470. __func__);
  1471. ret = -EINVAL;
  1472. goto err;
  1473. }
  1474. ret = kstrtouint(path_num_char, 10, &path_num);
  1475. if (ret < 0)
  1476. pr_err("%s: Invalid tx path = %s\n",
  1477. __func__, w_name);
  1478. err:
  1479. kfree(w_name);
  1480. return ret;
  1481. }
  1482. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1483. struct snd_ctl_elem_value *ucontrol)
  1484. {
  1485. struct snd_soc_dapm_widget *widget =
  1486. snd_soc_dapm_kcontrol_widget(kcontrol);
  1487. struct snd_soc_component *component =
  1488. snd_soc_kcontrol_component(kcontrol);
  1489. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1490. u32 path = 0;
  1491. if (!widget || !widget->name || !wcd938x || !component)
  1492. return -EINVAL;
  1493. path = wcd938x_tx_path_get(widget->name);
  1494. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1495. return 0;
  1496. }
  1497. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1498. struct snd_ctl_elem_value *ucontrol)
  1499. {
  1500. struct snd_soc_dapm_widget *widget =
  1501. snd_soc_dapm_kcontrol_widget(kcontrol);
  1502. struct snd_soc_component *component =
  1503. snd_soc_kcontrol_component(kcontrol);
  1504. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1505. u32 mode_val;
  1506. u32 path = 0;
  1507. if (!widget || !widget->name || !wcd938x || !component)
  1508. return -EINVAL;
  1509. path = wcd938x_tx_path_get(widget->name);
  1510. mode_val = ucontrol->value.enumerated.item[0];
  1511. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1512. wcd938x->tx_mode[path] = mode_val;
  1513. return 0;
  1514. }
  1515. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1516. struct snd_ctl_elem_value *ucontrol)
  1517. {
  1518. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1519. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1520. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1521. return 0;
  1522. }
  1523. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1528. u32 mode_val;
  1529. mode_val = ucontrol->value.enumerated.item[0];
  1530. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1531. if (mode_val == 0) {
  1532. dev_info(component->dev,
  1533. "%s:Invalid HPH Mode, default to class_AB\n",
  1534. __func__);
  1535. mode_val = 3; /* enum will be updated later */
  1536. }
  1537. wcd938x->hph_mode = mode_val;
  1538. return 0;
  1539. }
  1540. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_value *ucontrol)
  1542. {
  1543. struct snd_soc_component *component =
  1544. snd_soc_kcontrol_component(kcontrol);
  1545. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1546. bool hphr;
  1547. struct soc_multi_mixer_control *mc;
  1548. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1549. hphr = mc->shift;
  1550. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1551. wcd938x->comp1_enable;
  1552. return 0;
  1553. }
  1554. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1555. struct snd_ctl_elem_value *ucontrol)
  1556. {
  1557. struct snd_soc_component *component =
  1558. snd_soc_kcontrol_component(kcontrol);
  1559. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1560. int value = ucontrol->value.integer.value[0];
  1561. bool hphr;
  1562. struct soc_multi_mixer_control *mc;
  1563. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1564. hphr = mc->shift;
  1565. if (hphr)
  1566. wcd938x->comp2_enable = value;
  1567. else
  1568. wcd938x->comp1_enable = value;
  1569. return 0;
  1570. }
  1571. static int wcd938x_tx_hdr_get(struct snd_kcontrol *kcontrol,
  1572. struct snd_ctl_elem_value *ucontrol)
  1573. {
  1574. struct snd_soc_component *component =
  1575. snd_soc_kcontrol_component(kcontrol);
  1576. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1577. int hdr = ((struct soc_multi_mixer_control *)
  1578. kcontrol->private_value)->shift;
  1579. ucontrol->value.integer.value[0] = wcd938x->hdr_en[hdr];
  1580. return 0;
  1581. }
  1582. static int wcd938x_tx_hdr_put(struct snd_kcontrol *kcontrol,
  1583. struct snd_ctl_elem_value *ucontrol)
  1584. {
  1585. struct snd_soc_component *component =
  1586. snd_soc_kcontrol_component(kcontrol);
  1587. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1588. int hdr = ((struct soc_multi_mixer_control *)
  1589. kcontrol->private_value)->shift;
  1590. int val = ucontrol->value.integer.value[0];
  1591. u8 mask = 0;
  1592. wcd938x->hdr_en[hdr] = val;
  1593. switch(val) {
  1594. case TX_HDR12:
  1595. mask = (1 << 4);
  1596. val = (val << 4);
  1597. break;
  1598. case TX_HDR34:
  1599. mask = (1 << 3);
  1600. val = (val << 3);
  1601. break;
  1602. default:
  1603. dev_err(component->dev, "%s: unknown HDR input: %d\n",
  1604. __func__, hdr);
  1605. break;
  1606. }
  1607. if (mask)
  1608. snd_soc_component_update_bits(component,
  1609. WCD938X_TX_NEW_AMIC_MUX_CFG, mask, val);
  1610. return 0;
  1611. }
  1612. static const char * const tx_mode_mux_text[] = {
  1613. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1614. "ADC_ULP1", "ADC_ULP2",
  1615. };
  1616. static const struct soc_enum tx_mode_mux_enum =
  1617. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1618. tx_mode_mux_text);
  1619. static const char * const rx_hph_mode_mux_text[] = {
  1620. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1621. "CLS_H_ULP", "CLS_AB_HIFI",
  1622. };
  1623. static const struct soc_enum rx_hph_mode_mux_enum =
  1624. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1625. rx_hph_mode_mux_text);
  1626. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1627. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1628. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1629. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1630. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1631. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1632. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1633. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1634. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1635. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1636. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1637. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1638. wcd938x_get_compander, wcd938x_set_compander),
  1639. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1640. wcd938x_get_compander, wcd938x_set_compander),
  1641. SOC_SINGLE_EXT("TX HDR12", SND_SOC_NOPM, TX_HDR12, 1, 0,
  1642. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1643. SOC_SINGLE_EXT("TX HDR34", SND_SOC_NOPM, TX_HDR34, 1, 0,
  1644. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1645. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1646. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1647. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1648. analog_gain),
  1649. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1650. analog_gain),
  1651. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1652. analog_gain),
  1653. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1654. analog_gain),
  1655. };
  1656. static const struct snd_kcontrol_new adc1_switch[] = {
  1657. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1658. };
  1659. static const struct snd_kcontrol_new adc2_switch[] = {
  1660. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1661. };
  1662. static const struct snd_kcontrol_new adc3_switch[] = {
  1663. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1664. };
  1665. static const struct snd_kcontrol_new adc4_switch[] = {
  1666. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1667. };
  1668. static const struct snd_kcontrol_new dmic1_switch[] = {
  1669. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1670. };
  1671. static const struct snd_kcontrol_new dmic2_switch[] = {
  1672. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1673. };
  1674. static const struct snd_kcontrol_new dmic3_switch[] = {
  1675. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1676. };
  1677. static const struct snd_kcontrol_new dmic4_switch[] = {
  1678. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1679. };
  1680. static const struct snd_kcontrol_new dmic5_switch[] = {
  1681. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1682. };
  1683. static const struct snd_kcontrol_new dmic6_switch[] = {
  1684. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1685. };
  1686. static const struct snd_kcontrol_new dmic7_switch[] = {
  1687. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1688. };
  1689. static const struct snd_kcontrol_new dmic8_switch[] = {
  1690. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1691. };
  1692. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1693. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1694. };
  1695. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1696. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1697. };
  1698. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1699. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1700. };
  1701. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1702. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1703. };
  1704. static const char * const adc2_mux_text[] = {
  1705. "INP2", "INP3"
  1706. };
  1707. static const struct soc_enum adc2_enum =
  1708. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1709. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1710. static const struct snd_kcontrol_new tx_adc2_mux =
  1711. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1712. static const char * const adc3_mux_text[] = {
  1713. "INP4", "INP6"
  1714. };
  1715. static const struct soc_enum adc3_enum =
  1716. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1717. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1718. static const struct snd_kcontrol_new tx_adc3_mux =
  1719. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1720. static const char * const adc4_mux_text[] = {
  1721. "INP5", "INP7"
  1722. };
  1723. static const struct soc_enum adc4_enum =
  1724. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1725. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1726. static const struct snd_kcontrol_new tx_adc4_mux =
  1727. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1728. static const char * const rdac3_mux_text[] = {
  1729. "RX1", "RX3"
  1730. };
  1731. static const struct soc_enum rdac3_enum =
  1732. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1733. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1734. static const struct snd_kcontrol_new rx_rdac3_mux =
  1735. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1736. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1737. /*input widgets*/
  1738. SND_SOC_DAPM_INPUT("AMIC1"),
  1739. SND_SOC_DAPM_INPUT("AMIC2"),
  1740. SND_SOC_DAPM_INPUT("AMIC3"),
  1741. SND_SOC_DAPM_INPUT("AMIC4"),
  1742. SND_SOC_DAPM_INPUT("AMIC5"),
  1743. SND_SOC_DAPM_INPUT("AMIC6"),
  1744. SND_SOC_DAPM_INPUT("AMIC7"),
  1745. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1746. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1747. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1748. /*tx widgets*/
  1749. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1750. wcd938x_codec_enable_adc,
  1751. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1752. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1753. wcd938x_codec_enable_adc,
  1754. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1755. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1756. wcd938x_codec_enable_adc,
  1757. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1758. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1759. wcd938x_codec_enable_adc,
  1760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1761. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1762. wcd938x_codec_enable_dmic,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1764. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1765. wcd938x_codec_enable_dmic,
  1766. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1767. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1768. wcd938x_codec_enable_dmic,
  1769. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1770. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1771. wcd938x_codec_enable_dmic,
  1772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1773. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1774. wcd938x_codec_enable_dmic,
  1775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1776. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1777. wcd938x_codec_enable_dmic,
  1778. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1779. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1780. wcd938x_codec_enable_dmic,
  1781. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1782. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1783. wcd938x_codec_enable_dmic,
  1784. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1785. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1786. NULL, 0, wcd938x_enable_req,
  1787. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1788. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  1789. NULL, 0, wcd938x_enable_req,
  1790. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1791. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  1792. NULL, 0, wcd938x_enable_req,
  1793. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1794. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  1795. NULL, 0, wcd938x_enable_req,
  1796. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1797. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1798. &tx_adc2_mux),
  1799. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1800. &tx_adc3_mux),
  1801. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1802. &tx_adc4_mux),
  1803. /*tx mixers*/
  1804. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1805. adc1_switch, ARRAY_SIZE(adc1_switch),
  1806. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1807. SND_SOC_DAPM_POST_PMD),
  1808. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1809. adc2_switch, ARRAY_SIZE(adc2_switch),
  1810. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1811. SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1813. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1814. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1815. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1816. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1817. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1818. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1819. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1820. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1821. SND_SOC_DAPM_POST_PMD),
  1822. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1823. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1824. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1825. SND_SOC_DAPM_POST_PMD),
  1826. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1827. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1828. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1829. SND_SOC_DAPM_POST_PMD),
  1830. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1831. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1832. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1833. SND_SOC_DAPM_POST_PMD),
  1834. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1835. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1836. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1837. SND_SOC_DAPM_POST_PMD),
  1838. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1839. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1840. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1841. SND_SOC_DAPM_POST_PMD),
  1842. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1843. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1844. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1845. SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1847. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1848. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1849. SND_SOC_DAPM_POST_PMD),
  1850. /* micbias widgets*/
  1851. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1852. wcd938x_codec_enable_micbias,
  1853. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1854. SND_SOC_DAPM_POST_PMD),
  1855. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1856. wcd938x_codec_enable_micbias,
  1857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1858. SND_SOC_DAPM_POST_PMD),
  1859. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1860. wcd938x_codec_enable_micbias,
  1861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1862. SND_SOC_DAPM_POST_PMD),
  1863. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1864. wcd938x_codec_enable_micbias,
  1865. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1866. SND_SOC_DAPM_POST_PMD),
  1867. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1868. wcd938x_enable_clsh,
  1869. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1870. /*rx widgets*/
  1871. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1872. wcd938x_codec_enable_ear_pa,
  1873. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1874. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1875. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1876. wcd938x_codec_enable_aux_pa,
  1877. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1878. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1879. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1880. wcd938x_codec_enable_hphl_pa,
  1881. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1882. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1883. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1884. wcd938x_codec_enable_hphr_pa,
  1885. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1886. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1887. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1888. wcd938x_codec_hphl_dac_event,
  1889. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1890. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1891. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1892. wcd938x_codec_hphr_dac_event,
  1893. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1894. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1895. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1896. wcd938x_codec_ear_dac_event,
  1897. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1898. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1899. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1900. wcd938x_codec_aux_dac_event,
  1901. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1902. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1903. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1904. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1905. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1906. SND_SOC_DAPM_POST_PMD),
  1907. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1908. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1909. SND_SOC_DAPM_POST_PMD),
  1910. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1911. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1912. SND_SOC_DAPM_POST_PMD),
  1913. /* rx mixer widgets*/
  1914. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1915. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1916. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1917. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1918. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1919. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1920. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1921. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1922. /*output widgets tx*/
  1923. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1924. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1925. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1926. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1927. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1928. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1929. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1930. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1931. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1932. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1933. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1934. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1935. /*output widgets rx*/
  1936. SND_SOC_DAPM_OUTPUT("EAR"),
  1937. SND_SOC_DAPM_OUTPUT("AUX"),
  1938. SND_SOC_DAPM_OUTPUT("HPHL"),
  1939. SND_SOC_DAPM_OUTPUT("HPHR"),
  1940. };
  1941. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1942. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1943. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1944. {"ADC1 REQ", NULL, "ADC1"},
  1945. {"ADC1", NULL, "AMIC1"},
  1946. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1947. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1948. {"ADC2 REQ", NULL, "ADC2"},
  1949. {"ADC2", NULL, "ADC2 MUX"},
  1950. {"ADC2 MUX", "INP3", "AMIC3"},
  1951. {"ADC2 MUX", "INP2", "AMIC2"},
  1952. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1953. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1954. {"ADC3 REQ", NULL, "ADC3"},
  1955. {"ADC3", NULL, "ADC3 MUX"},
  1956. {"ADC3 MUX", "INP4", "AMIC4"},
  1957. {"ADC3 MUX", "INP6", "AMIC6"},
  1958. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1959. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1960. {"ADC4 REQ", NULL, "ADC4"},
  1961. {"ADC4", NULL, "ADC4 MUX"},
  1962. {"ADC4 MUX", "INP5", "AMIC5"},
  1963. {"ADC4 MUX", "INP7", "AMIC7"},
  1964. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1965. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1966. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1967. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1968. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1969. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1970. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1971. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1972. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1973. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1974. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1975. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1976. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  1977. {"DMIC7_MIXER", "Switch", "DMIC7"},
  1978. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  1979. {"DMIC8_MIXER", "Switch", "DMIC8"},
  1980. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1981. {"RX1", NULL, "IN1_HPHL"},
  1982. {"RDAC1", NULL, "RX1"},
  1983. {"HPHL_RDAC", "Switch", "RDAC1"},
  1984. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1985. {"HPHL", NULL, "HPHL PGA"},
  1986. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1987. {"RX2", NULL, "IN2_HPHR"},
  1988. {"RDAC2", NULL, "RX2"},
  1989. {"HPHR_RDAC", "Switch", "RDAC2"},
  1990. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1991. {"HPHR", NULL, "HPHR PGA"},
  1992. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1993. {"RX3", NULL, "IN3_AUX"},
  1994. {"RDAC4", NULL, "RX3"},
  1995. {"AUX_RDAC", "Switch", "RDAC4"},
  1996. {"AUX PGA", NULL, "AUX_RDAC"},
  1997. {"AUX", NULL, "AUX PGA"},
  1998. {"RDAC3_MUX", "RX3", "RX3"},
  1999. {"RDAC3_MUX", "RX1", "RX1"},
  2000. {"RDAC3", NULL, "RDAC3_MUX"},
  2001. {"EAR_RDAC", "Switch", "RDAC3"},
  2002. {"EAR PGA", NULL, "EAR_RDAC"},
  2003. {"EAR", NULL, "EAR PGA"},
  2004. };
  2005. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2006. void *file_private_data,
  2007. struct file *file,
  2008. char __user *buf, size_t count,
  2009. loff_t pos)
  2010. {
  2011. struct wcd938x_priv *priv;
  2012. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2013. int len = 0;
  2014. priv = (struct wcd938x_priv *) entry->private_data;
  2015. if (!priv) {
  2016. pr_err("%s: wcd938x priv is null\n", __func__);
  2017. return -EINVAL;
  2018. }
  2019. switch (priv->version) {
  2020. case WCD938X_VERSION_1_0:
  2021. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2022. break;
  2023. default:
  2024. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2025. }
  2026. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2027. }
  2028. static struct snd_info_entry_ops wcd938x_info_ops = {
  2029. .read = wcd938x_version_read,
  2030. };
  2031. /*
  2032. * wcd938x_info_create_codec_entry - creates wcd938x module
  2033. * @codec_root: The parent directory
  2034. * @component: component instance
  2035. *
  2036. * Creates wcd938x module and version entry under the given
  2037. * parent directory.
  2038. *
  2039. * Return: 0 on success or negative error code on failure.
  2040. */
  2041. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2042. struct snd_soc_component *component)
  2043. {
  2044. struct snd_info_entry *version_entry;
  2045. struct wcd938x_priv *priv;
  2046. struct snd_soc_card *card;
  2047. if (!codec_root || !component)
  2048. return -EINVAL;
  2049. priv = snd_soc_component_get_drvdata(component);
  2050. if (priv->entry) {
  2051. dev_dbg(priv->dev,
  2052. "%s:wcd938x module already created\n", __func__);
  2053. return 0;
  2054. }
  2055. card = component->card;
  2056. priv->entry = snd_info_create_subdir(codec_root->module,
  2057. "wcd938x", codec_root);
  2058. if (!priv->entry) {
  2059. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2060. __func__);
  2061. return -ENOMEM;
  2062. }
  2063. version_entry = snd_info_create_card_entry(card->snd_card,
  2064. "version",
  2065. priv->entry);
  2066. if (!version_entry) {
  2067. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2068. __func__);
  2069. return -ENOMEM;
  2070. }
  2071. version_entry->private_data = priv;
  2072. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2073. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2074. version_entry->c.ops = &wcd938x_info_ops;
  2075. if (snd_info_register(version_entry) < 0) {
  2076. snd_info_free_entry(version_entry);
  2077. return -ENOMEM;
  2078. }
  2079. priv->version_entry = version_entry;
  2080. return 0;
  2081. }
  2082. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2083. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2084. {
  2085. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2086. struct snd_soc_dapm_context *dapm =
  2087. snd_soc_component_get_dapm(component);
  2088. int variant;
  2089. int ret = -EINVAL;
  2090. dev_info(component->dev, "%s()\n", __func__);
  2091. wcd938x = snd_soc_component_get_drvdata(component);
  2092. if (!wcd938x)
  2093. return -EINVAL;
  2094. wcd938x->component = component;
  2095. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2096. variant = (snd_soc_component_read32(component,
  2097. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2098. wcd938x->variant = variant;
  2099. wcd938x->fw_data = devm_kzalloc(component->dev,
  2100. sizeof(*(wcd938x->fw_data)),
  2101. GFP_KERNEL);
  2102. if (!wcd938x->fw_data) {
  2103. dev_err(component->dev, "Failed to allocate fw_data\n");
  2104. ret = -ENOMEM;
  2105. goto err;
  2106. }
  2107. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2108. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2109. WCD9XXX_CODEC_HWDEP_NODE, component);
  2110. if (ret < 0) {
  2111. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2112. goto err_hwdep;
  2113. }
  2114. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2115. if (ret) {
  2116. pr_err("%s: mbhc initialization failed\n", __func__);
  2117. goto err_hwdep;
  2118. }
  2119. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2120. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2121. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2122. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2123. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2124. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2125. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2126. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2127. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2128. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2129. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2130. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2131. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2132. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2133. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2134. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2135. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2136. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2137. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2138. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2139. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2140. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2141. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2142. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2143. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2144. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2145. snd_soc_dapm_sync(dapm);
  2146. wcd_cls_h_init(&wcd938x->clsh_info);
  2147. wcd938x_init_reg(component);
  2148. wcd938x->version = WCD938X_VERSION_1_0;
  2149. /* Register event notifier */
  2150. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2151. if (wcd938x->register_notifier) {
  2152. ret = wcd938x->register_notifier(wcd938x->handle,
  2153. &wcd938x->nblock,
  2154. true);
  2155. if (ret) {
  2156. dev_err(component->dev,
  2157. "%s: Failed to register notifier %d\n",
  2158. __func__, ret);
  2159. return ret;
  2160. }
  2161. }
  2162. return ret;
  2163. err_hwdep:
  2164. wcd938x->fw_data = NULL;
  2165. err:
  2166. return ret;
  2167. }
  2168. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2169. {
  2170. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2171. if (!wcd938x) {
  2172. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2173. __func__);
  2174. return;
  2175. }
  2176. if (wcd938x->register_notifier)
  2177. wcd938x->register_notifier(wcd938x->handle,
  2178. &wcd938x->nblock,
  2179. false);
  2180. }
  2181. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2182. .name = WCD938X_DRV_NAME,
  2183. .probe = wcd938x_soc_codec_probe,
  2184. .remove = wcd938x_soc_codec_remove,
  2185. .controls = wcd938x_snd_controls,
  2186. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2187. .dapm_widgets = wcd938x_dapm_widgets,
  2188. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2189. .dapm_routes = wcd938x_audio_map,
  2190. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2191. };
  2192. static int wcd938x_reset(struct device *dev)
  2193. {
  2194. struct wcd938x_priv *wcd938x = NULL;
  2195. int rc = 0;
  2196. int value = 0;
  2197. if (!dev)
  2198. return -ENODEV;
  2199. wcd938x = dev_get_drvdata(dev);
  2200. if (!wcd938x)
  2201. return -EINVAL;
  2202. if (!wcd938x->rst_np) {
  2203. dev_err(dev, "%s: reset gpio device node not specified\n",
  2204. __func__);
  2205. return -EINVAL;
  2206. }
  2207. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2208. if (value > 0)
  2209. return 0;
  2210. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2211. if (rc) {
  2212. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2213. __func__);
  2214. return rc;
  2215. }
  2216. /* 20us sleep required after pulling the reset gpio to LOW */
  2217. usleep_range(20, 30);
  2218. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2219. if (rc) {
  2220. dev_err(dev, "%s: wcd active state request fail!\n",
  2221. __func__);
  2222. return rc;
  2223. }
  2224. /* 20us sleep required after pulling the reset gpio to HIGH */
  2225. usleep_range(20, 30);
  2226. return rc;
  2227. }
  2228. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2229. u32 *val)
  2230. {
  2231. int rc = 0;
  2232. rc = of_property_read_u32(dev->of_node, name, val);
  2233. if (rc)
  2234. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2235. __func__, name, dev->of_node->full_name);
  2236. return rc;
  2237. }
  2238. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2239. struct wcd938x_micbias_setting *mb)
  2240. {
  2241. u32 prop_val = 0;
  2242. int rc = 0;
  2243. /* MB1 */
  2244. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2245. NULL)) {
  2246. rc = wcd938x_read_of_property_u32(dev,
  2247. "qcom,cdc-micbias1-mv",
  2248. &prop_val);
  2249. if (!rc)
  2250. mb->micb1_mv = prop_val;
  2251. } else {
  2252. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2253. __func__);
  2254. }
  2255. /* MB2 */
  2256. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2257. NULL)) {
  2258. rc = wcd938x_read_of_property_u32(dev,
  2259. "qcom,cdc-micbias2-mv",
  2260. &prop_val);
  2261. if (!rc)
  2262. mb->micb2_mv = prop_val;
  2263. } else {
  2264. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2265. __func__);
  2266. }
  2267. /* MB3 */
  2268. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2269. NULL)) {
  2270. rc = wcd938x_read_of_property_u32(dev,
  2271. "qcom,cdc-micbias3-mv",
  2272. &prop_val);
  2273. if (!rc)
  2274. mb->micb3_mv = prop_val;
  2275. } else {
  2276. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2277. __func__);
  2278. }
  2279. }
  2280. static int wcd938x_reset_low(struct device *dev)
  2281. {
  2282. struct wcd938x_priv *wcd938x = NULL;
  2283. int rc = 0;
  2284. if (!dev)
  2285. return -ENODEV;
  2286. wcd938x = dev_get_drvdata(dev);
  2287. if (!wcd938x)
  2288. return -EINVAL;
  2289. if (!wcd938x->rst_np) {
  2290. dev_err(dev, "%s: reset gpio device node not specified\n",
  2291. __func__);
  2292. return -EINVAL;
  2293. }
  2294. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2295. if (rc) {
  2296. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2297. __func__);
  2298. return rc;
  2299. }
  2300. /* 20us sleep required after pulling the reset gpio to LOW */
  2301. usleep_range(20, 30);
  2302. return rc;
  2303. }
  2304. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2305. {
  2306. struct wcd938x_pdata *pdata = NULL;
  2307. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2308. GFP_KERNEL);
  2309. if (!pdata)
  2310. return NULL;
  2311. pdata->rst_np = of_parse_phandle(dev->of_node,
  2312. "qcom,wcd-rst-gpio-node", 0);
  2313. if (!pdata->rst_np) {
  2314. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2315. __func__, "qcom,wcd-rst-gpio-node",
  2316. dev->of_node->full_name);
  2317. return NULL;
  2318. }
  2319. /* Parse power supplies */
  2320. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2321. &pdata->num_supplies);
  2322. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2323. dev_err(dev, "%s: no power supplies defined for codec\n",
  2324. __func__);
  2325. return NULL;
  2326. }
  2327. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2328. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2329. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2330. return pdata;
  2331. }
  2332. static int wcd938x_bind(struct device *dev)
  2333. {
  2334. int ret = 0, i = 0;
  2335. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2336. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2337. /*
  2338. * Add 5msec delay to provide sufficient time for
  2339. * soundwire auto enumeration of slave devices as
  2340. * as per HW requirement.
  2341. */
  2342. usleep_range(5000, 5010);
  2343. ret = component_bind_all(dev, wcd938x);
  2344. if (ret) {
  2345. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2346. __func__, ret);
  2347. return ret;
  2348. }
  2349. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2350. if (!wcd938x->rx_swr_dev) {
  2351. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2352. __func__);
  2353. ret = -ENODEV;
  2354. goto err;
  2355. }
  2356. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2357. if (!wcd938x->tx_swr_dev) {
  2358. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2359. __func__);
  2360. ret = -ENODEV;
  2361. goto err;
  2362. }
  2363. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2364. &wcd938x_regmap_config);
  2365. if (!wcd938x->regmap) {
  2366. dev_err(dev, "%s: Regmap init failed\n",
  2367. __func__);
  2368. goto err;
  2369. }
  2370. /* Set all interupts as edge triggered */
  2371. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2372. regmap_write(wcd938x->regmap,
  2373. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2374. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2375. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2376. wcd938x->irq_info.codec_name = "WCD938X";
  2377. wcd938x->irq_info.regmap = wcd938x->regmap;
  2378. wcd938x->irq_info.dev = dev;
  2379. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2380. if (ret) {
  2381. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2382. __func__, ret);
  2383. goto err;
  2384. }
  2385. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2386. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2387. NULL, 0);
  2388. if (ret) {
  2389. dev_err(dev, "%s: Codec registration failed\n",
  2390. __func__);
  2391. goto err_irq;
  2392. }
  2393. return ret;
  2394. err_irq:
  2395. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2396. err:
  2397. component_unbind_all(dev, wcd938x);
  2398. return ret;
  2399. }
  2400. static void wcd938x_unbind(struct device *dev)
  2401. {
  2402. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2403. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2404. snd_soc_unregister_component(dev);
  2405. component_unbind_all(dev, wcd938x);
  2406. }
  2407. static const struct of_device_id wcd938x_dt_match[] = {
  2408. { .compatible = "qcom,wcd938x-codec" },
  2409. {}
  2410. };
  2411. static const struct component_master_ops wcd938x_comp_ops = {
  2412. .bind = wcd938x_bind,
  2413. .unbind = wcd938x_unbind,
  2414. };
  2415. static int wcd938x_compare_of(struct device *dev, void *data)
  2416. {
  2417. return dev->of_node == data;
  2418. }
  2419. static void wcd938x_release_of(struct device *dev, void *data)
  2420. {
  2421. of_node_put(data);
  2422. }
  2423. static int wcd938x_add_slave_components(struct device *dev,
  2424. struct component_match **matchptr)
  2425. {
  2426. struct device_node *np, *rx_node, *tx_node;
  2427. np = dev->of_node;
  2428. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2429. if (!rx_node) {
  2430. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2431. return -ENODEV;
  2432. }
  2433. of_node_get(rx_node);
  2434. component_match_add_release(dev, matchptr,
  2435. wcd938x_release_of,
  2436. wcd938x_compare_of,
  2437. rx_node);
  2438. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2439. if (!tx_node) {
  2440. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2441. return -ENODEV;
  2442. }
  2443. of_node_get(tx_node);
  2444. component_match_add_release(dev, matchptr,
  2445. wcd938x_release_of,
  2446. wcd938x_compare_of,
  2447. tx_node);
  2448. return 0;
  2449. }
  2450. static int wcd938x_wakeup(void *handle, bool enable)
  2451. {
  2452. struct wcd938x_priv *priv;
  2453. if (!handle) {
  2454. pr_err("%s: NULL handle\n", __func__);
  2455. return -EINVAL;
  2456. }
  2457. priv = (struct wcd938x_priv *)handle;
  2458. if (!priv->tx_swr_dev) {
  2459. pr_err("%s: tx swr dev is NULL\n", __func__);
  2460. return -EINVAL;
  2461. }
  2462. if (enable)
  2463. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2464. else
  2465. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2466. }
  2467. static int wcd938x_probe(struct platform_device *pdev)
  2468. {
  2469. struct component_match *match = NULL;
  2470. struct wcd938x_priv *wcd938x = NULL;
  2471. struct wcd938x_pdata *pdata = NULL;
  2472. struct wcd_ctrl_platform_data *plat_data = NULL;
  2473. struct device *dev = &pdev->dev;
  2474. int ret;
  2475. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2476. GFP_KERNEL);
  2477. if (!wcd938x)
  2478. return -ENOMEM;
  2479. dev_set_drvdata(dev, wcd938x);
  2480. pdata = wcd938x_populate_dt_data(dev);
  2481. if (!pdata) {
  2482. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2483. return -EINVAL;
  2484. }
  2485. dev->platform_data = pdata;
  2486. wcd938x->rst_np = pdata->rst_np;
  2487. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2488. pdata->regulator, pdata->num_supplies);
  2489. if (!wcd938x->supplies) {
  2490. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2491. __func__);
  2492. return ret;
  2493. }
  2494. plat_data = dev_get_platdata(dev->parent);
  2495. if (!plat_data) {
  2496. dev_err(dev, "%s: platform data from parent is NULL\n",
  2497. __func__);
  2498. return -EINVAL;
  2499. }
  2500. wcd938x->handle = (void *)plat_data->handle;
  2501. if (!wcd938x->handle) {
  2502. dev_err(dev, "%s: handle is NULL\n", __func__);
  2503. return -EINVAL;
  2504. }
  2505. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2506. if (!wcd938x->update_wcd_event) {
  2507. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2508. __func__);
  2509. return -EINVAL;
  2510. }
  2511. wcd938x->register_notifier = plat_data->register_notifier;
  2512. if (!wcd938x->register_notifier) {
  2513. dev_err(dev, "%s: register_notifier api is null!\n",
  2514. __func__);
  2515. return -EINVAL;
  2516. }
  2517. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2518. pdata->regulator,
  2519. pdata->num_supplies);
  2520. if (ret) {
  2521. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2522. __func__);
  2523. return ret;
  2524. }
  2525. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2526. CODEC_RX);
  2527. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2528. CODEC_TX);
  2529. if (ret) {
  2530. dev_err(dev, "Failed to read port mapping\n");
  2531. goto err;
  2532. }
  2533. ret = wcd938x_add_slave_components(dev, &match);
  2534. if (ret)
  2535. goto err;
  2536. wcd938x_reset(dev);
  2537. wcd938x->wakeup = wcd938x_wakeup;
  2538. return component_master_add_with_match(dev,
  2539. &wcd938x_comp_ops, match);
  2540. err:
  2541. return ret;
  2542. }
  2543. static int wcd938x_remove(struct platform_device *pdev)
  2544. {
  2545. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2546. dev_set_drvdata(&pdev->dev, NULL);
  2547. return 0;
  2548. }
  2549. #ifdef CONFIG_PM_SLEEP
  2550. static int wcd938x_suspend(struct device *dev)
  2551. {
  2552. return 0;
  2553. }
  2554. static int wcd938x_resume(struct device *dev)
  2555. {
  2556. return 0;
  2557. }
  2558. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2559. SET_SYSTEM_SLEEP_PM_OPS(
  2560. wcd938x_suspend,
  2561. wcd938x_resume
  2562. )
  2563. };
  2564. #endif
  2565. static struct platform_driver wcd938x_codec_driver = {
  2566. .probe = wcd938x_probe,
  2567. .remove = wcd938x_remove,
  2568. .driver = {
  2569. .name = "wcd938x_codec",
  2570. .owner = THIS_MODULE,
  2571. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2572. #ifdef CONFIG_PM_SLEEP
  2573. .pm = &wcd938x_dev_pm_ops,
  2574. #endif
  2575. },
  2576. };
  2577. module_platform_driver(wcd938x_codec_driver);
  2578. MODULE_DESCRIPTION("WCD938X Codec driver");
  2579. MODULE_LICENSE("GPL v2");