dp_tx.c 89 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. /**
  68. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  69. * @vdev: DP Virtual device handle
  70. * @nbuf: Buffer pointer
  71. * @queue: queue ids container for nbuf
  72. *
  73. * TX packet queue has 2 instances, software descriptors id and dma ring id
  74. * Based on tx feature and hardware configuration queue id combination could be
  75. * different.
  76. * For example -
  77. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  78. * With no XPS,lock based resource protection, Descriptor pool ids are different
  79. * for each vdev, dma ring id will be same as single pdev id
  80. *
  81. * Return: None
  82. */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. qdf_atomic_dec(&pdev->num_tx_outstanding);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  168. qdf_atomic_dec(&pdev->num_tx_exception);
  169. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  170. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  171. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  172. else
  173. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  175. "Tx Completion Release desc %d status %d outstanding %d",
  176. tx_desc->id, comp_status,
  177. qdf_atomic_read(&pdev->num_tx_outstanding));
  178. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  179. return;
  180. }
  181. /**
  182. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  183. * @vdev: DP vdev Handle
  184. * @nbuf: skb
  185. *
  186. * Prepares and fills HTT metadata in the frame pre-header for special frames
  187. * that should be transmitted using varying transmit parameters.
  188. * There are 2 VDEV modes that currently needs this special metadata -
  189. * 1) Mesh Mode
  190. * 2) DSRC Mode
  191. *
  192. * Return: HTT metadata size
  193. *
  194. */
  195. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  196. uint32_t *meta_data)
  197. {
  198. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  199. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  200. uint8_t htt_desc_size;
  201. /* Size rounded of multiple of 8 bytes */
  202. uint8_t htt_desc_size_aligned;
  203. uint8_t *hdr = NULL;
  204. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  205. /*
  206. * Metadata - HTT MSDU Extension header
  207. */
  208. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  209. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  210. if (vdev->mesh_vdev) {
  211. /* Fill and add HTT metaheader */
  212. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  213. if (hdr == NULL) {
  214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  215. "Error in filling HTT metadata\n");
  216. return 0;
  217. }
  218. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  219. } else if (vdev->opmode == wlan_op_mode_ocb) {
  220. /* Todo - Add support for DSRC */
  221. }
  222. return htt_desc_size_aligned;
  223. }
  224. /**
  225. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  226. * @tso_seg: TSO segment to process
  227. * @ext_desc: Pointer to MSDU extension descriptor
  228. *
  229. * Return: void
  230. */
  231. #if defined(FEATURE_TSO)
  232. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  233. void *ext_desc)
  234. {
  235. uint8_t num_frag;
  236. uint32_t tso_flags;
  237. /*
  238. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  239. * tcp_flag_mask
  240. *
  241. * Checksum enable flags are set in TCL descriptor and not in Extension
  242. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  243. */
  244. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  245. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  246. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  247. tso_seg->tso_flags.ip_len);
  248. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  249. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  250. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  251. uint32_t lo = 0;
  252. uint32_t hi = 0;
  253. qdf_dmaaddr_to_32s(
  254. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  255. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  256. tso_seg->tso_frags[num_frag].length);
  257. }
  258. return;
  259. }
  260. #else
  261. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  262. void *ext_desc)
  263. {
  264. return;
  265. }
  266. #endif
  267. #if defined(FEATURE_TSO)
  268. /**
  269. * dp_tx_free_tso_seg() - Loop through the tso segments
  270. * allocated and free them
  271. *
  272. * @soc: soc handle
  273. * @free_seg: list of tso segments
  274. * @msdu_info: msdu descriptor
  275. *
  276. * Return - void
  277. */
  278. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  279. struct qdf_tso_seg_elem_t *free_seg,
  280. struct dp_tx_msdu_info_s *msdu_info)
  281. {
  282. struct qdf_tso_seg_elem_t *next_seg;
  283. while (free_seg) {
  284. next_seg = free_seg->next;
  285. dp_tx_tso_desc_free(soc,
  286. msdu_info->tx_queue.desc_pool_id,
  287. free_seg);
  288. free_seg = next_seg;
  289. }
  290. }
  291. /**
  292. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  293. * allocated and free them
  294. *
  295. * @soc: soc handle
  296. * @free_seg: list of tso segments
  297. * @msdu_info: msdu descriptor
  298. * Return - void
  299. */
  300. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  301. struct qdf_tso_num_seg_elem_t *free_seg,
  302. struct dp_tx_msdu_info_s *msdu_info)
  303. {
  304. struct qdf_tso_num_seg_elem_t *next_seg;
  305. while (free_seg) {
  306. next_seg = free_seg->next;
  307. dp_tso_num_seg_free(soc,
  308. msdu_info->tx_queue.desc_pool_id,
  309. free_seg);
  310. free_seg = next_seg;
  311. }
  312. }
  313. /**
  314. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  315. * @vdev: virtual device handle
  316. * @msdu: network buffer
  317. * @msdu_info: meta data associated with the msdu
  318. *
  319. * Return: QDF_STATUS_SUCCESS success
  320. */
  321. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  322. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *tso_seg;
  325. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  326. struct dp_soc *soc = vdev->pdev->soc;
  327. struct qdf_tso_info_t *tso_info;
  328. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  329. tso_info = &msdu_info->u.tso_info;
  330. tso_info->curr_seg = NULL;
  331. tso_info->tso_seg_list = NULL;
  332. tso_info->num_segs = num_seg;
  333. msdu_info->frm_type = dp_tx_frm_tso;
  334. tso_info->tso_num_seg_list = NULL;
  335. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  336. while (num_seg) {
  337. tso_seg = dp_tx_tso_desc_alloc(
  338. soc, msdu_info->tx_queue.desc_pool_id);
  339. if (tso_seg) {
  340. tso_seg->next = tso_info->tso_seg_list;
  341. tso_info->tso_seg_list = tso_seg;
  342. num_seg--;
  343. } else {
  344. struct qdf_tso_seg_elem_t *free_seg =
  345. tso_info->tso_seg_list;
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. }
  350. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  351. tso_num_seg = dp_tso_num_seg_alloc(soc,
  352. msdu_info->tx_queue.desc_pool_id);
  353. if (tso_num_seg) {
  354. tso_num_seg->next = tso_info->tso_num_seg_list;
  355. tso_info->tso_num_seg_list = tso_num_seg;
  356. } else {
  357. /* Bug: free tso_num_seg and tso_seg */
  358. /* Free the already allocated num of segments */
  359. struct qdf_tso_seg_elem_t *free_seg =
  360. tso_info->tso_seg_list;
  361. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  362. __func__);
  363. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  364. return QDF_STATUS_E_NOMEM;
  365. }
  366. msdu_info->num_seg =
  367. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  368. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  369. msdu_info->num_seg);
  370. if (!(msdu_info->num_seg)) {
  371. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  372. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  373. msdu_info);
  374. return QDF_STATUS_E_INVAL;
  375. }
  376. tso_info->curr_seg = tso_info->tso_seg_list;
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. #else
  380. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  381. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. return QDF_STATUS_E_NOMEM;
  384. }
  385. #endif
  386. /**
  387. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  388. * @vdev: DP Vdev handle
  389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  390. * @desc_pool_id: Descriptor Pool ID
  391. *
  392. * Return:
  393. */
  394. static
  395. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  396. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  397. {
  398. uint8_t i;
  399. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  400. struct dp_tx_seg_info_s *seg_info;
  401. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  402. struct dp_soc *soc = vdev->pdev->soc;
  403. /* Allocate an extension descriptor */
  404. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  405. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  406. if (!msdu_ext_desc) {
  407. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  408. return NULL;
  409. }
  410. if (qdf_unlikely(vdev->mesh_vdev)) {
  411. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  412. &msdu_info->meta_data[0],
  413. sizeof(struct htt_tx_msdu_desc_ext2_t));
  414. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  415. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  416. }
  417. switch (msdu_info->frm_type) {
  418. case dp_tx_frm_sg:
  419. case dp_tx_frm_me:
  420. case dp_tx_frm_raw:
  421. seg_info = msdu_info->u.sg_info.curr_seg;
  422. /* Update the buffer pointers in MSDU Extension Descriptor */
  423. for (i = 0; i < seg_info->frag_cnt; i++) {
  424. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  425. seg_info->frags[i].paddr_lo,
  426. seg_info->frags[i].paddr_hi,
  427. seg_info->frags[i].len);
  428. }
  429. break;
  430. case dp_tx_frm_tso:
  431. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  432. &cached_ext_desc[0]);
  433. break;
  434. default:
  435. break;
  436. }
  437. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  438. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  439. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  440. msdu_ext_desc->vaddr);
  441. return msdu_ext_desc;
  442. }
  443. /**
  444. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  445. * @vdev: DP vdev handle
  446. * @nbuf: skb
  447. * @desc_pool_id: Descriptor pool ID
  448. * @meta_data: Metadata to the fw
  449. * @tx_exc_metadata: Handle that holds exception path metadata
  450. * Allocate and prepare Tx descriptor with msdu information.
  451. *
  452. * Return: Pointer to Tx Descriptor on success,
  453. * NULL on failure
  454. */
  455. static
  456. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  457. qdf_nbuf_t nbuf, uint8_t desc_pool_id, uint32_t *meta_data,
  458. struct cdp_tx_exception_metadata *tx_exc_metadata)
  459. {
  460. uint8_t align_pad;
  461. uint8_t is_exception = 0;
  462. uint8_t htt_hdr_size;
  463. struct ether_header *eh;
  464. struct dp_tx_desc_s *tx_desc;
  465. struct dp_pdev *pdev = vdev->pdev;
  466. struct dp_soc *soc = pdev->soc;
  467. /* Allocate software Tx descriptor */
  468. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  469. if (qdf_unlikely(!tx_desc)) {
  470. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  471. return NULL;
  472. }
  473. /* Flow control/Congestion Control counters */
  474. qdf_atomic_inc(&pdev->num_tx_outstanding);
  475. /* Initialize the SW tx descriptor */
  476. tx_desc->nbuf = nbuf;
  477. tx_desc->frm_type = dp_tx_frm_std;
  478. tx_desc->tx_encap_type = (tx_exc_metadata ?
  479. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  480. tx_desc->vdev = vdev;
  481. tx_desc->pdev = pdev;
  482. tx_desc->msdu_ext_desc = NULL;
  483. tx_desc->pkt_offset = 0;
  484. /*
  485. * For special modes (vdev_type == ocb or mesh), data frames should be
  486. * transmitted using varying transmit parameters (tx spec) which include
  487. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  488. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  489. * These frames are sent as exception packets to firmware.
  490. *
  491. * HW requirement is that metadata should always point to a
  492. * 8-byte aligned address. So we add alignment pad to start of buffer.
  493. * HTT Metadata should be ensured to be multiple of 8-bytes,
  494. * to get 8-byte aligned start address along with align_pad added
  495. *
  496. * |-----------------------------|
  497. * | |
  498. * |-----------------------------| <-----Buffer Pointer Address given
  499. * | | ^ in HW descriptor (aligned)
  500. * | HTT Metadata | |
  501. * | | |
  502. * | | | Packet Offset given in descriptor
  503. * | | |
  504. * |-----------------------------| |
  505. * | Alignment Pad | v
  506. * |-----------------------------| <----- Actual buffer start address
  507. * | SKB Data | (Unaligned)
  508. * | |
  509. * | |
  510. * | |
  511. * | |
  512. * | |
  513. * |-----------------------------|
  514. */
  515. if (qdf_unlikely(vdev->mesh_vdev ||
  516. (vdev->opmode == wlan_op_mode_ocb))) {
  517. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  518. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  519. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  520. "qdf_nbuf_push_head failed\n");
  521. goto failure;
  522. }
  523. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  524. meta_data);
  525. if (htt_hdr_size == 0)
  526. goto failure;
  527. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  528. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  529. is_exception = 1;
  530. }
  531. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  532. qdf_nbuf_map(soc->osdev, nbuf,
  533. QDF_DMA_TO_DEVICE))) {
  534. /* Handle failure */
  535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  536. "qdf_nbuf_map failed\n");
  537. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  538. goto failure;
  539. }
  540. if (qdf_unlikely(vdev->nawds_enabled)) {
  541. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  542. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  543. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  544. is_exception = 1;
  545. }
  546. }
  547. #if !TQM_BYPASS_WAR
  548. if (is_exception || tx_exc_metadata)
  549. #endif
  550. {
  551. /* Temporary WAR due to TQM VP issues */
  552. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  553. qdf_atomic_inc(&pdev->num_tx_exception);
  554. }
  555. return tx_desc;
  556. failure:
  557. dp_tx_desc_release(tx_desc, desc_pool_id);
  558. return NULL;
  559. }
  560. /**
  561. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  562. * @vdev: DP vdev handle
  563. * @nbuf: skb
  564. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  565. * @desc_pool_id : Descriptor Pool ID
  566. *
  567. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  568. * information. For frames wth fragments, allocate and prepare
  569. * an MSDU extension descriptor
  570. *
  571. * Return: Pointer to Tx Descriptor on success,
  572. * NULL on failure
  573. */
  574. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  575. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  576. uint8_t desc_pool_id)
  577. {
  578. struct dp_tx_desc_s *tx_desc;
  579. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  580. struct dp_pdev *pdev = vdev->pdev;
  581. struct dp_soc *soc = pdev->soc;
  582. /* Allocate software Tx descriptor */
  583. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  584. if (!tx_desc) {
  585. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  586. return NULL;
  587. }
  588. /* Flow control/Congestion Control counters */
  589. qdf_atomic_inc(&pdev->num_tx_outstanding);
  590. /* Initialize the SW tx descriptor */
  591. tx_desc->nbuf = nbuf;
  592. tx_desc->frm_type = msdu_info->frm_type;
  593. tx_desc->tx_encap_type = vdev->tx_encap_type;
  594. tx_desc->vdev = vdev;
  595. tx_desc->pdev = pdev;
  596. tx_desc->pkt_offset = 0;
  597. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  598. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  599. /* Handle scattered frames - TSO/SG/ME */
  600. /* Allocate and prepare an extension descriptor for scattered frames */
  601. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  602. if (!msdu_ext_desc) {
  603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  604. "%s Tx Extension Descriptor Alloc Fail\n",
  605. __func__);
  606. goto failure;
  607. }
  608. #if TQM_BYPASS_WAR
  609. /* Temporary WAR due to TQM VP issues */
  610. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  611. qdf_atomic_inc(&pdev->num_tx_exception);
  612. #endif
  613. if (qdf_unlikely(vdev->mesh_vdev))
  614. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  615. tx_desc->msdu_ext_desc = msdu_ext_desc;
  616. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  617. return tx_desc;
  618. failure:
  619. dp_tx_desc_release(tx_desc, desc_pool_id);
  620. return NULL;
  621. }
  622. /**
  623. * dp_tx_prepare_raw() - Prepare RAW packet TX
  624. * @vdev: DP vdev handle
  625. * @nbuf: buffer pointer
  626. * @seg_info: Pointer to Segment info Descriptor to be prepared
  627. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  628. * descriptor
  629. *
  630. * Return:
  631. */
  632. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  633. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  634. {
  635. qdf_nbuf_t curr_nbuf = NULL;
  636. uint16_t total_len = 0;
  637. qdf_dma_addr_t paddr;
  638. int32_t i;
  639. int32_t mapped_buf_num = 0;
  640. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  641. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  642. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  643. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  644. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  645. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  646. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  647. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  648. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  649. QDF_DMA_TO_DEVICE)) {
  650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  651. "%s dma map error \n", __func__);
  652. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  653. mapped_buf_num = i;
  654. goto error;
  655. }
  656. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  657. seg_info->frags[i].paddr_lo = paddr;
  658. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  659. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  660. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  661. total_len += qdf_nbuf_len(curr_nbuf);
  662. }
  663. seg_info->frag_cnt = i;
  664. seg_info->total_len = total_len;
  665. seg_info->next = NULL;
  666. sg_info->curr_seg = seg_info;
  667. msdu_info->frm_type = dp_tx_frm_raw;
  668. msdu_info->num_seg = 1;
  669. return nbuf;
  670. error:
  671. i = 0;
  672. while (nbuf) {
  673. curr_nbuf = nbuf;
  674. if (i < mapped_buf_num) {
  675. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  676. i++;
  677. }
  678. nbuf = qdf_nbuf_next(nbuf);
  679. qdf_nbuf_free(curr_nbuf);
  680. }
  681. return NULL;
  682. }
  683. /**
  684. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  685. * @soc: DP Soc Handle
  686. * @vdev: DP vdev handle
  687. * @tx_desc: Tx Descriptor Handle
  688. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  689. * @fw_metadata: Metadata to send to Target Firmware along with frame
  690. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  691. * @tx_exc_metadata: Handle that holds exception path meta data
  692. *
  693. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  694. * from software Tx descriptor
  695. *
  696. * Return:
  697. */
  698. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  699. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  700. uint16_t fw_metadata, uint8_t ring_id,
  701. struct cdp_tx_exception_metadata
  702. *tx_exc_metadata)
  703. {
  704. uint8_t type;
  705. uint16_t length;
  706. void *hal_tx_desc, *hal_tx_desc_cached;
  707. qdf_dma_addr_t dma_addr;
  708. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  709. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  710. tx_exc_metadata->sec_type : vdev->sec_type);
  711. /* Return Buffer Manager ID */
  712. uint8_t bm_id = ring_id;
  713. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  714. hal_tx_desc_cached = (void *) cached_desc;
  715. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  716. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  717. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  718. type = HAL_TX_BUF_TYPE_EXT_DESC;
  719. dma_addr = tx_desc->msdu_ext_desc->paddr;
  720. } else {
  721. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  722. type = HAL_TX_BUF_TYPE_BUFFER;
  723. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  724. }
  725. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  726. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  727. dma_addr , bm_id, tx_desc->id, type);
  728. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  729. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  730. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  731. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  732. vdev->dscp_tid_map_id);
  733. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  734. sec_type_map[sec_type]);
  735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  737. __func__, length, type, (uint64_t)dma_addr,
  738. tx_desc->pkt_offset, tx_desc->id);
  739. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  740. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  741. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  742. vdev->hal_desc_addr_search_flags);
  743. /* verify checksum offload configuration*/
  744. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  745. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  746. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  747. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  748. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  749. }
  750. if (tid != HTT_TX_EXT_TID_INVALID)
  751. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  752. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  753. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  754. /* Sync cached descriptor with HW */
  755. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  756. if (!hal_tx_desc) {
  757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  758. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  759. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  760. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  761. return QDF_STATUS_E_RESOURCES;
  762. }
  763. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  764. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  765. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  766. /*
  767. * If one packet is enqueued in HW, PM usage count needs to be
  768. * incremented by one to prevent future runtime suspend. This
  769. * should be tied with the success of enqueuing. It will be
  770. * decremented after the packet has been sent.
  771. */
  772. hif_pm_runtime_get_noresume(soc->hif_handle);
  773. return QDF_STATUS_SUCCESS;
  774. }
  775. /**
  776. * dp_cce_classify() - Classify the frame based on CCE rules
  777. * @vdev: DP vdev handle
  778. * @nbuf: skb
  779. *
  780. * Classify frames based on CCE rules
  781. * Return: bool( true if classified,
  782. * else false)
  783. */
  784. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  785. {
  786. struct ether_header *eh = NULL;
  787. uint16_t ether_type;
  788. qdf_llc_t *llcHdr;
  789. qdf_nbuf_t nbuf_clone = NULL;
  790. qdf_dot3_qosframe_t *qos_wh = NULL;
  791. /* for mesh packets don't do any classification */
  792. if (qdf_unlikely(vdev->mesh_vdev))
  793. return false;
  794. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  795. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  796. ether_type = eh->ether_type;
  797. llcHdr = (qdf_llc_t *)(nbuf->data +
  798. sizeof(struct ether_header));
  799. } else {
  800. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  801. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  802. if (qdf_unlikely(
  803. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  804. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  805. ether_type = *(uint16_t *)(nbuf->data
  806. + QDF_IEEE80211_4ADDR_HDR_LEN
  807. + sizeof(qdf_llc_t)
  808. - sizeof(ether_type));
  809. llcHdr = (qdf_llc_t *)(nbuf->data +
  810. QDF_IEEE80211_4ADDR_HDR_LEN);
  811. } else {
  812. ether_type = *(uint16_t *)(nbuf->data
  813. + QDF_IEEE80211_3ADDR_HDR_LEN
  814. + sizeof(qdf_llc_t)
  815. - sizeof(ether_type));
  816. llcHdr = (qdf_llc_t *)(nbuf->data +
  817. QDF_IEEE80211_3ADDR_HDR_LEN);
  818. }
  819. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  820. && (ether_type ==
  821. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  822. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  823. return true;
  824. }
  825. }
  826. return false;
  827. }
  828. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  829. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  830. sizeof(*llcHdr));
  831. nbuf_clone = qdf_nbuf_clone(nbuf);
  832. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  833. if (ether_type == htons(ETHERTYPE_8021Q)) {
  834. qdf_nbuf_pull_head(nbuf_clone,
  835. sizeof(qdf_net_vlanhdr_t));
  836. }
  837. } else {
  838. if (ether_type == htons(ETHERTYPE_8021Q)) {
  839. nbuf_clone = qdf_nbuf_clone(nbuf);
  840. qdf_nbuf_pull_head(nbuf_clone,
  841. sizeof(qdf_net_vlanhdr_t));
  842. }
  843. }
  844. if (qdf_unlikely(nbuf_clone))
  845. nbuf = nbuf_clone;
  846. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  847. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  848. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  849. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  850. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  851. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  852. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  853. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  854. if (qdf_unlikely(nbuf_clone != NULL))
  855. qdf_nbuf_free(nbuf_clone);
  856. return true;
  857. }
  858. if (qdf_unlikely(nbuf_clone != NULL))
  859. qdf_nbuf_free(nbuf_clone);
  860. return false;
  861. }
  862. /**
  863. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  864. * @vdev: DP vdev handle
  865. * @nbuf: skb
  866. *
  867. * Extract the DSCP or PCP information from frame and map into TID value.
  868. * Software based TID classification is required when more than 2 DSCP-TID
  869. * mapping tables are needed.
  870. * Hardware supports 2 DSCP-TID mapping tables
  871. *
  872. * Return: void
  873. */
  874. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  875. struct dp_tx_msdu_info_s *msdu_info)
  876. {
  877. uint8_t tos = 0, dscp_tid_override = 0;
  878. uint8_t *hdr_ptr, *L3datap;
  879. uint8_t is_mcast = 0;
  880. struct ether_header *eh = NULL;
  881. qdf_ethervlan_header_t *evh = NULL;
  882. uint16_t ether_type;
  883. qdf_llc_t *llcHdr;
  884. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  885. /* for mesh packets don't do any classification */
  886. if (qdf_unlikely(vdev->mesh_vdev))
  887. return;
  888. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  889. eh = (struct ether_header *) nbuf->data;
  890. hdr_ptr = eh->ether_dhost;
  891. L3datap = hdr_ptr + sizeof(struct ether_header);
  892. } else {
  893. qdf_dot3_qosframe_t *qos_wh =
  894. (qdf_dot3_qosframe_t *) nbuf->data;
  895. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  896. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  897. return;
  898. }
  899. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  900. ether_type = eh->ether_type;
  901. /*
  902. * Check if packet is dot3 or eth2 type.
  903. */
  904. if (IS_LLC_PRESENT(ether_type)) {
  905. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  906. sizeof(*llcHdr));
  907. if (ether_type == htons(ETHERTYPE_8021Q)) {
  908. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  909. sizeof(*llcHdr);
  910. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  911. + sizeof(*llcHdr) +
  912. sizeof(qdf_net_vlanhdr_t));
  913. } else {
  914. L3datap = hdr_ptr + sizeof(struct ether_header) +
  915. sizeof(*llcHdr);
  916. }
  917. } else {
  918. if (ether_type == htons(ETHERTYPE_8021Q)) {
  919. evh = (qdf_ethervlan_header_t *) eh;
  920. ether_type = evh->ether_type;
  921. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  922. }
  923. }
  924. /*
  925. * Find priority from IP TOS DSCP field
  926. */
  927. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  928. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  929. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  930. /* Only for unicast frames */
  931. if (!is_mcast) {
  932. /* send it on VO queue */
  933. msdu_info->tid = DP_VO_TID;
  934. }
  935. } else {
  936. /*
  937. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  938. * from TOS byte.
  939. */
  940. tos = ip->ip_tos;
  941. dscp_tid_override = 1;
  942. }
  943. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  944. /* TODO
  945. * use flowlabel
  946. *igmpmld cases to be handled in phase 2
  947. */
  948. unsigned long ver_pri_flowlabel;
  949. unsigned long pri;
  950. ver_pri_flowlabel = *(unsigned long *) L3datap;
  951. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  952. DP_IPV6_PRIORITY_SHIFT;
  953. tos = pri;
  954. dscp_tid_override = 1;
  955. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  956. msdu_info->tid = DP_VO_TID;
  957. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  958. /* Only for unicast frames */
  959. if (!is_mcast) {
  960. /* send ucast arp on VO queue */
  961. msdu_info->tid = DP_VO_TID;
  962. }
  963. }
  964. /*
  965. * Assign all MCAST packets to BE
  966. */
  967. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  968. if (is_mcast) {
  969. tos = 0;
  970. dscp_tid_override = 1;
  971. }
  972. }
  973. if (dscp_tid_override == 1) {
  974. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  975. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  976. }
  977. return;
  978. }
  979. #ifdef CONVERGED_TDLS_ENABLE
  980. /**
  981. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  982. * @tx_desc: TX descriptor
  983. *
  984. * Return: None
  985. */
  986. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  987. {
  988. if (tx_desc->vdev) {
  989. if (tx_desc->vdev->is_tdls_frame)
  990. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  991. tx_desc->vdev->is_tdls_frame = false;
  992. }
  993. }
  994. /**
  995. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  996. * @tx_desc: TX descriptor
  997. * @vdev: datapath vdev handle
  998. *
  999. * Return: None
  1000. */
  1001. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1002. struct dp_vdev *vdev)
  1003. {
  1004. struct hal_tx_completion_status ts = {0};
  1005. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1006. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1007. if (vdev->tx_non_std_data_callback.func) {
  1008. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1009. vdev->tx_non_std_data_callback.func(
  1010. vdev->tx_non_std_data_callback.ctxt,
  1011. nbuf, ts.status);
  1012. return;
  1013. }
  1014. }
  1015. #endif
  1016. /**
  1017. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1018. * @vdev: DP vdev handle
  1019. * @nbuf: skb
  1020. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1021. * @meta_data: Metadata to the fw
  1022. * @tx_q: Tx queue to be used for this Tx frame
  1023. * @peer_id: peer_id of the peer in case of NAWDS frames
  1024. * @tx_exc_metadata: Handle that holds exception path metadata
  1025. *
  1026. * Return: NULL on success,
  1027. * nbuf when it fails to send
  1028. */
  1029. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1030. uint8_t tid, struct dp_tx_queue *tx_q,
  1031. uint32_t *meta_data, uint16_t peer_id,
  1032. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1033. {
  1034. struct dp_pdev *pdev = vdev->pdev;
  1035. struct dp_soc *soc = pdev->soc;
  1036. struct dp_tx_desc_s *tx_desc;
  1037. QDF_STATUS status;
  1038. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1039. uint16_t htt_tcl_metadata = 0;
  1040. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  1041. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1042. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1043. meta_data, tx_exc_metadata);
  1044. if (!tx_desc) {
  1045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1046. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1047. __func__, vdev, tx_q->desc_pool_id);
  1048. return nbuf;
  1049. }
  1050. if (qdf_unlikely(soc->cce_disable)) {
  1051. if (dp_cce_classify(vdev, nbuf) == true) {
  1052. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1053. tid = DP_VO_TID;
  1054. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1055. }
  1056. }
  1057. dp_tx_update_tdls_flags(tx_desc);
  1058. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1059. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1060. "%s %d : HAL RING Access Failed -- %pK\n",
  1061. __func__, __LINE__, hal_srng);
  1062. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1063. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1064. goto fail_return;
  1065. }
  1066. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1067. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1068. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1069. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1070. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1071. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1072. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1073. peer_id);
  1074. } else
  1075. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1076. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1077. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1078. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1079. if (status != QDF_STATUS_SUCCESS) {
  1080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1081. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1082. __func__, tx_desc, tx_q->ring_id);
  1083. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1084. goto fail_return;
  1085. }
  1086. nbuf = NULL;
  1087. fail_return:
  1088. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1089. hal_srng_access_end(soc->hal_soc, hal_srng);
  1090. hif_pm_runtime_put(soc->hif_handle);
  1091. } else {
  1092. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1093. }
  1094. return nbuf;
  1095. }
  1096. /**
  1097. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1098. * @vdev: DP vdev handle
  1099. * @nbuf: skb
  1100. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1101. *
  1102. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1103. *
  1104. * Return: NULL on success,
  1105. * nbuf when it fails to send
  1106. */
  1107. #if QDF_LOCK_STATS
  1108. static noinline
  1109. #else
  1110. static
  1111. #endif
  1112. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1113. struct dp_tx_msdu_info_s *msdu_info)
  1114. {
  1115. uint8_t i;
  1116. struct dp_pdev *pdev = vdev->pdev;
  1117. struct dp_soc *soc = pdev->soc;
  1118. struct dp_tx_desc_s *tx_desc;
  1119. bool is_cce_classified = false;
  1120. QDF_STATUS status;
  1121. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1122. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1123. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1124. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1125. "%s %d : HAL RING Access Failed -- %pK\n",
  1126. __func__, __LINE__, hal_srng);
  1127. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1128. return nbuf;
  1129. }
  1130. if (qdf_unlikely(soc->cce_disable)) {
  1131. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1132. if (is_cce_classified) {
  1133. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1134. msdu_info->tid = DP_VO_TID;
  1135. }
  1136. }
  1137. if (msdu_info->frm_type == dp_tx_frm_me)
  1138. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1139. i = 0;
  1140. /* Print statement to track i and num_seg */
  1141. /*
  1142. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1143. * descriptors using information in msdu_info
  1144. */
  1145. while (i < msdu_info->num_seg) {
  1146. /*
  1147. * Setup Tx descriptor for an MSDU, and MSDU extension
  1148. * descriptor
  1149. */
  1150. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1151. tx_q->desc_pool_id);
  1152. if (!tx_desc) {
  1153. if (msdu_info->frm_type == dp_tx_frm_me) {
  1154. dp_tx_me_free_buf(pdev,
  1155. (void *)(msdu_info->u.sg_info
  1156. .curr_seg->frags[0].vaddr));
  1157. }
  1158. goto done;
  1159. }
  1160. if (msdu_info->frm_type == dp_tx_frm_me) {
  1161. tx_desc->me_buffer =
  1162. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1163. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1164. }
  1165. if (is_cce_classified)
  1166. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1167. /*
  1168. * Enqueue the Tx MSDU descriptor to HW for transmit
  1169. */
  1170. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1171. vdev->htt_tcl_metadata, tx_q->ring_id, NULL);
  1172. if (status != QDF_STATUS_SUCCESS) {
  1173. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1174. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1175. __func__, tx_desc, tx_q->ring_id);
  1176. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1177. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1178. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1179. goto done;
  1180. }
  1181. /*
  1182. * TODO
  1183. * if tso_info structure can be modified to have curr_seg
  1184. * as first element, following 2 blocks of code (for TSO and SG)
  1185. * can be combined into 1
  1186. */
  1187. /*
  1188. * For frames with multiple segments (TSO, ME), jump to next
  1189. * segment.
  1190. */
  1191. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1192. if (msdu_info->u.tso_info.curr_seg->next) {
  1193. msdu_info->u.tso_info.curr_seg =
  1194. msdu_info->u.tso_info.curr_seg->next;
  1195. /*
  1196. * If this is a jumbo nbuf, then increment the number of
  1197. * nbuf users for each additional segment of the msdu.
  1198. * This will ensure that the skb is freed only after
  1199. * receiving tx completion for all segments of an nbuf
  1200. */
  1201. qdf_nbuf_inc_users(nbuf);
  1202. /* Check with MCL if this is needed */
  1203. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1204. }
  1205. }
  1206. /*
  1207. * For Multicast-Unicast converted packets,
  1208. * each converted frame (for a client) is represented as
  1209. * 1 segment
  1210. */
  1211. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1212. (msdu_info->frm_type == dp_tx_frm_me)) {
  1213. if (msdu_info->u.sg_info.curr_seg->next) {
  1214. msdu_info->u.sg_info.curr_seg =
  1215. msdu_info->u.sg_info.curr_seg->next;
  1216. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1217. }
  1218. }
  1219. i++;
  1220. }
  1221. nbuf = NULL;
  1222. done:
  1223. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1224. hal_srng_access_end(soc->hal_soc, hal_srng);
  1225. hif_pm_runtime_put(soc->hif_handle);
  1226. } else {
  1227. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1228. }
  1229. return nbuf;
  1230. }
  1231. /**
  1232. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1233. * for SG frames
  1234. * @vdev: DP vdev handle
  1235. * @nbuf: skb
  1236. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1237. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1238. *
  1239. * Return: NULL on success,
  1240. * nbuf when it fails to send
  1241. */
  1242. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1243. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1244. {
  1245. uint32_t cur_frag, nr_frags;
  1246. qdf_dma_addr_t paddr;
  1247. struct dp_tx_sg_info_s *sg_info;
  1248. sg_info = &msdu_info->u.sg_info;
  1249. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1250. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1251. QDF_DMA_TO_DEVICE)) {
  1252. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1253. "dma map error\n");
  1254. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1255. qdf_nbuf_free(nbuf);
  1256. return NULL;
  1257. }
  1258. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1259. seg_info->frags[0].paddr_lo = paddr;
  1260. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1261. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1262. seg_info->frags[0].vaddr = (void *) nbuf;
  1263. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1264. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1265. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1267. "frag dma map error\n");
  1268. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1269. qdf_nbuf_free(nbuf);
  1270. return NULL;
  1271. }
  1272. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1273. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1274. seg_info->frags[cur_frag + 1].paddr_hi =
  1275. ((uint64_t) paddr) >> 32;
  1276. seg_info->frags[cur_frag + 1].len =
  1277. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1278. }
  1279. seg_info->frag_cnt = (cur_frag + 1);
  1280. seg_info->total_len = qdf_nbuf_len(nbuf);
  1281. seg_info->next = NULL;
  1282. sg_info->curr_seg = seg_info;
  1283. msdu_info->frm_type = dp_tx_frm_sg;
  1284. msdu_info->num_seg = 1;
  1285. return nbuf;
  1286. }
  1287. #ifdef MESH_MODE_SUPPORT
  1288. /**
  1289. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1290. and prepare msdu_info for mesh frames.
  1291. * @vdev: DP vdev handle
  1292. * @nbuf: skb
  1293. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1294. *
  1295. * Return: NULL on failure,
  1296. * nbuf when extracted successfully
  1297. */
  1298. static
  1299. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1300. struct dp_tx_msdu_info_s *msdu_info)
  1301. {
  1302. struct meta_hdr_s *mhdr;
  1303. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1304. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1305. nbuf = qdf_nbuf_unshare(nbuf);
  1306. if (nbuf == NULL) {
  1307. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1308. "qdf_nbuf_unshare failed\n");
  1309. return nbuf;
  1310. }
  1311. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1312. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1313. meta_data->host_tx_desc_pool = 1;
  1314. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1315. meta_data->power = mhdr->power;
  1316. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1317. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1318. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1319. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1320. meta_data->dyn_bw = 1;
  1321. meta_data->valid_pwr = 1;
  1322. meta_data->valid_mcs_mask = 1;
  1323. meta_data->valid_nss_mask = 1;
  1324. meta_data->valid_preamble_type = 1;
  1325. meta_data->valid_retries = 1;
  1326. meta_data->valid_bw_info = 1;
  1327. }
  1328. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1329. meta_data->encrypt_type = 0;
  1330. meta_data->valid_encrypt_type = 1;
  1331. }
  1332. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1333. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1334. else
  1335. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1336. meta_data->valid_key_flags = 1;
  1337. meta_data->key_flags = (mhdr->keyix & 0x3);
  1338. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1340. "qdf_nbuf_pull_head failed\n");
  1341. qdf_nbuf_free(nbuf);
  1342. return NULL;
  1343. }
  1344. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1345. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1346. __func__, msdu_info->meta_data[0],
  1347. msdu_info->meta_data[1],
  1348. msdu_info->meta_data[2],
  1349. msdu_info->meta_data[3],
  1350. msdu_info->meta_data[4]);
  1351. return nbuf;
  1352. }
  1353. #else
  1354. static
  1355. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1356. struct dp_tx_msdu_info_s *msdu_info)
  1357. {
  1358. return nbuf;
  1359. }
  1360. #endif
  1361. #ifdef DP_FEATURE_NAWDS_TX
  1362. /**
  1363. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1364. * @vdev: dp_vdev handle
  1365. * @nbuf: skb
  1366. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1367. * @tx_q: Tx queue to be used for this Tx frame
  1368. * @meta_data: Meta date for mesh
  1369. * @peer_id: peer_id of the peer in case of NAWDS frames
  1370. *
  1371. * return: NULL on success nbuf on failure
  1372. */
  1373. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1374. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data)
  1375. {
  1376. struct dp_peer *peer = NULL;
  1377. struct dp_soc *soc = vdev->pdev->soc;
  1378. struct dp_ast_entry *ast_entry = NULL;
  1379. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1380. uint16_t peer_id = HTT_INVALID_PEER;
  1381. struct dp_peer *sa_peer = NULL;
  1382. qdf_nbuf_t nbuf_copy;
  1383. qdf_spin_lock_bh(&(soc->ast_lock));
  1384. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1385. if (ast_entry)
  1386. sa_peer = ast_entry->peer;
  1387. qdf_spin_unlock_bh(&(soc->ast_lock));
  1388. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1389. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1390. (peer->nawds_enabled)) {
  1391. if (sa_peer == peer) {
  1392. QDF_TRACE(QDF_MODULE_ID_DP,
  1393. QDF_TRACE_LEVEL_DEBUG,
  1394. " %s: broadcast multicast packet",
  1395. __func__);
  1396. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1397. continue;
  1398. }
  1399. nbuf_copy = qdf_nbuf_copy(nbuf);
  1400. if (!nbuf_copy) {
  1401. QDF_TRACE(QDF_MODULE_ID_DP,
  1402. QDF_TRACE_LEVEL_ERROR,
  1403. "nbuf copy failed");
  1404. }
  1405. peer_id = peer->peer_ids[0];
  1406. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1407. tx_q, meta_data, peer_id, NULL);
  1408. if (nbuf_copy != NULL) {
  1409. qdf_nbuf_free(nbuf_copy);
  1410. continue;
  1411. }
  1412. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1413. 1, qdf_nbuf_len(nbuf));
  1414. }
  1415. }
  1416. if (peer_id == HTT_INVALID_PEER)
  1417. return nbuf;
  1418. return NULL;
  1419. }
  1420. #endif
  1421. /**
  1422. * dp_check_exc_metadata() - Checks if parameters are valid
  1423. * @tx_exc - holds all exception path parameters
  1424. *
  1425. * Returns true when all the parameters are valid else false
  1426. *
  1427. */
  1428. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1429. {
  1430. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1431. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1432. tx_exc->sec_type > cdp_num_sec_types) {
  1433. return false;
  1434. }
  1435. return true;
  1436. }
  1437. /**
  1438. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1439. * @vap_dev: DP vdev handle
  1440. * @nbuf: skb
  1441. * @tx_exc_metadata: Handle that holds exception path meta data
  1442. *
  1443. * Entry point for Core Tx layer (DP_TX) invoked from
  1444. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1445. *
  1446. * Return: NULL on success,
  1447. * nbuf when it fails to send
  1448. */
  1449. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1450. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1451. {
  1452. struct ether_header *eh = NULL;
  1453. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1454. struct dp_tx_queue tx_queue;
  1455. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1456. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1457. "%s , skb %pM",
  1458. __func__, nbuf->data);
  1459. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1460. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1461. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1462. "Invalid parameters in exception path");
  1463. goto fail;
  1464. }
  1465. /* Basic sanity checks for unsupported packets */
  1466. /* MESH mode */
  1467. if (qdf_unlikely(vdev->mesh_vdev)) {
  1468. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1469. "Mesh mode is not supported in exception path");
  1470. goto fail;
  1471. }
  1472. /* TSO or SG */
  1473. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1474. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1476. "TSO and SG are not supported in exception path");
  1477. goto fail;
  1478. }
  1479. /* RAW */
  1480. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1482. "Raw frame is not supported in exception path");
  1483. goto fail;
  1484. }
  1485. /* Mcast enhancement*/
  1486. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1487. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1489. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1490. }
  1491. }
  1492. /*
  1493. * Get HW Queue to use for this frame.
  1494. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1495. * dedicated for data and 1 for command.
  1496. * "queue_id" maps to one hardware ring.
  1497. * With each ring, we also associate a unique Tx descriptor pool
  1498. * to minimize lock contention for these resources.
  1499. */
  1500. dp_tx_get_queue(vdev, nbuf, &tx_queue);
  1501. /* Reset the control block */
  1502. qdf_nbuf_reset_ctxt(nbuf);
  1503. /* Single linear frame */
  1504. /*
  1505. * If nbuf is a simple linear frame, use send_single function to
  1506. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1507. * SRNG. There is no need to setup a MSDU extension descriptor.
  1508. */
  1509. nbuf = dp_tx_send_msdu_single(vdev, nbuf, tx_exc_metadata->tid,
  1510. &tx_queue, NULL, tx_exc_metadata->peer_id, tx_exc_metadata);
  1511. return nbuf;
  1512. fail:
  1513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1514. "pkt send failed");
  1515. return nbuf;
  1516. }
  1517. /**
  1518. * dp_tx_send() - Transmit a frame on a given VAP
  1519. * @vap_dev: DP vdev handle
  1520. * @nbuf: skb
  1521. *
  1522. * Entry point for Core Tx layer (DP_TX) invoked from
  1523. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1524. * cases
  1525. *
  1526. * Return: NULL on success,
  1527. * nbuf when it fails to send
  1528. */
  1529. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1530. {
  1531. struct ether_header *eh = NULL;
  1532. struct dp_tx_msdu_info_s msdu_info;
  1533. struct dp_tx_seg_info_s seg_info;
  1534. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1535. uint16_t peer_id = HTT_INVALID_PEER;
  1536. qdf_nbuf_t nbuf_mesh = NULL;
  1537. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1538. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1539. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1540. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1541. "%s , skb %pM",
  1542. __func__, nbuf->data);
  1543. /*
  1544. * Set Default Host TID value to invalid TID
  1545. * (TID override disabled)
  1546. */
  1547. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1548. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1549. if (qdf_unlikely(vdev->mesh_vdev)) {
  1550. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1551. &msdu_info);
  1552. if (nbuf_mesh == NULL) {
  1553. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1554. "Extracting mesh metadata failed\n");
  1555. return nbuf;
  1556. }
  1557. nbuf = nbuf_mesh;
  1558. }
  1559. /*
  1560. * Get HW Queue to use for this frame.
  1561. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1562. * dedicated for data and 1 for command.
  1563. * "queue_id" maps to one hardware ring.
  1564. * With each ring, we also associate a unique Tx descriptor pool
  1565. * to minimize lock contention for these resources.
  1566. */
  1567. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1568. /*
  1569. * TCL H/W supports 2 DSCP-TID mapping tables.
  1570. * Table 1 - Default DSCP-TID mapping table
  1571. * Table 2 - 1 DSCP-TID override table
  1572. *
  1573. * If we need a different DSCP-TID mapping for this vap,
  1574. * call tid_classify to extract DSCP/ToS from frame and
  1575. * map to a TID and store in msdu_info. This is later used
  1576. * to fill in TCL Input descriptor (per-packet TID override).
  1577. */
  1578. if (vdev->dscp_tid_map_id > 1)
  1579. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1580. /* Reset the control block */
  1581. qdf_nbuf_reset_ctxt(nbuf);
  1582. /*
  1583. * Classify the frame and call corresponding
  1584. * "prepare" function which extracts the segment (TSO)
  1585. * and fragmentation information (for TSO , SG, ME, or Raw)
  1586. * into MSDU_INFO structure which is later used to fill
  1587. * SW and HW descriptors.
  1588. */
  1589. if (qdf_nbuf_is_tso(nbuf)) {
  1590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1591. "%s TSO frame %pK\n", __func__, vdev);
  1592. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1593. qdf_nbuf_len(nbuf));
  1594. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1595. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1596. return nbuf;
  1597. }
  1598. goto send_multiple;
  1599. }
  1600. /* SG */
  1601. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1602. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1604. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1605. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1606. qdf_nbuf_len(nbuf));
  1607. goto send_multiple;
  1608. }
  1609. #ifdef ATH_SUPPORT_IQUE
  1610. /* Mcast to Ucast Conversion*/
  1611. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1612. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1613. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1615. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1616. DP_STATS_INC_PKT(vdev,
  1617. tx_i.mcast_en.mcast_pkt, 1,
  1618. qdf_nbuf_len(nbuf));
  1619. if (dp_tx_prepare_send_me(vdev, nbuf) !=
  1620. QDF_STATUS_SUCCESS) {
  1621. qdf_nbuf_free(nbuf);
  1622. return NULL;
  1623. }
  1624. }
  1625. }
  1626. #endif
  1627. /* RAW */
  1628. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1629. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1630. if (nbuf == NULL)
  1631. return NULL;
  1632. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1633. "%s Raw frame %pK\n", __func__, vdev);
  1634. goto send_multiple;
  1635. }
  1636. /* Single linear frame */
  1637. /*
  1638. * If nbuf is a simple linear frame, use send_single function to
  1639. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1640. * SRNG. There is no need to setup a MSDU extension descriptor.
  1641. */
  1642. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1643. &msdu_info.tx_queue, msdu_info.meta_data, peer_id, NULL);
  1644. return nbuf;
  1645. send_multiple:
  1646. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1647. return nbuf;
  1648. }
  1649. /**
  1650. * dp_tx_reinject_handler() - Tx Reinject Handler
  1651. * @tx_desc: software descriptor head pointer
  1652. * @status : Tx completion status from HTT descriptor
  1653. *
  1654. * This function reinjects frames back to Target.
  1655. * Todo - Host queue needs to be added
  1656. *
  1657. * Return: none
  1658. */
  1659. static
  1660. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1661. {
  1662. struct dp_vdev *vdev;
  1663. struct dp_peer *peer = NULL;
  1664. uint32_t peer_id = HTT_INVALID_PEER;
  1665. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1666. qdf_nbuf_t nbuf_copy = NULL;
  1667. struct dp_tx_msdu_info_s msdu_info;
  1668. struct dp_peer *sa_peer = NULL;
  1669. struct dp_ast_entry *ast_entry = NULL;
  1670. struct dp_soc *soc = NULL;
  1671. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1672. #ifdef WDS_VENDOR_EXTENSION
  1673. int is_mcast = 0, is_ucast = 0;
  1674. int num_peers_3addr = 0;
  1675. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1676. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1677. #endif
  1678. vdev = tx_desc->vdev;
  1679. soc = vdev->pdev->soc;
  1680. qdf_assert(vdev);
  1681. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1682. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1684. "%s Tx reinject path\n", __func__);
  1685. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1686. qdf_nbuf_len(tx_desc->nbuf));
  1687. qdf_spin_lock_bh(&(soc->ast_lock));
  1688. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1689. if (ast_entry)
  1690. sa_peer = ast_entry->peer;
  1691. qdf_spin_unlock_bh(&(soc->ast_lock));
  1692. #ifdef WDS_VENDOR_EXTENSION
  1693. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1694. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1695. } else {
  1696. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1697. }
  1698. is_ucast = !is_mcast;
  1699. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1700. if (peer->bss_peer)
  1701. continue;
  1702. /* Detect wds peers that use 3-addr framing for mcast.
  1703. * if there are any, the bss_peer is used to send the
  1704. * the mcast frame using 3-addr format. all wds enabled
  1705. * peers that use 4-addr framing for mcast frames will
  1706. * be duplicated and sent as 4-addr frames below.
  1707. */
  1708. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1709. num_peers_3addr = 1;
  1710. break;
  1711. }
  1712. }
  1713. #endif
  1714. if (qdf_unlikely(vdev->mesh_vdev)) {
  1715. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1716. } else {
  1717. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1718. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1719. #ifdef WDS_VENDOR_EXTENSION
  1720. /*
  1721. * . if 3-addr STA, then send on BSS Peer
  1722. * . if Peer WDS enabled and accept 4-addr mcast,
  1723. * send mcast on that peer only
  1724. * . if Peer WDS enabled and accept 4-addr ucast,
  1725. * send ucast on that peer only
  1726. */
  1727. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1728. (peer->wds_enabled &&
  1729. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1730. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1731. #else
  1732. ((peer->bss_peer &&
  1733. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1734. peer->nawds_enabled)) {
  1735. #endif
  1736. peer_id = DP_INVALID_PEER;
  1737. if (peer->nawds_enabled) {
  1738. peer_id = peer->peer_ids[0];
  1739. if (sa_peer == peer) {
  1740. QDF_TRACE(
  1741. QDF_MODULE_ID_DP,
  1742. QDF_TRACE_LEVEL_DEBUG,
  1743. " %s: multicast packet",
  1744. __func__);
  1745. DP_STATS_INC(peer,
  1746. tx.nawds_mcast_drop, 1);
  1747. continue;
  1748. }
  1749. }
  1750. nbuf_copy = qdf_nbuf_copy(nbuf);
  1751. if (!nbuf_copy) {
  1752. QDF_TRACE(QDF_MODULE_ID_DP,
  1753. QDF_TRACE_LEVEL_DEBUG,
  1754. FL("nbuf copy failed"));
  1755. break;
  1756. }
  1757. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1758. nbuf_copy,
  1759. msdu_info.tid,
  1760. &msdu_info.tx_queue,
  1761. msdu_info.meta_data,
  1762. peer_id,
  1763. NULL);
  1764. if (nbuf_copy) {
  1765. QDF_TRACE(QDF_MODULE_ID_DP,
  1766. QDF_TRACE_LEVEL_DEBUG,
  1767. FL("pkt send failed"));
  1768. qdf_nbuf_free(nbuf_copy);
  1769. } else {
  1770. if (peer_id != DP_INVALID_PEER)
  1771. DP_STATS_INC_PKT(peer,
  1772. tx.nawds_mcast,
  1773. 1, qdf_nbuf_len(nbuf));
  1774. }
  1775. }
  1776. }
  1777. }
  1778. if (vdev->nawds_enabled) {
  1779. peer_id = DP_INVALID_PEER;
  1780. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1781. 1, qdf_nbuf_len(nbuf));
  1782. nbuf = dp_tx_send_msdu_single(vdev,
  1783. nbuf, msdu_info.tid,
  1784. &msdu_info.tx_queue,
  1785. msdu_info.meta_data, peer_id, NULL);
  1786. if (nbuf) {
  1787. QDF_TRACE(QDF_MODULE_ID_DP,
  1788. QDF_TRACE_LEVEL_DEBUG,
  1789. FL("pkt send failed"));
  1790. qdf_nbuf_free(nbuf);
  1791. }
  1792. } else
  1793. qdf_nbuf_free(nbuf);
  1794. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1795. }
  1796. /**
  1797. * dp_tx_inspect_handler() - Tx Inspect Handler
  1798. * @tx_desc: software descriptor head pointer
  1799. * @status : Tx completion status from HTT descriptor
  1800. *
  1801. * Handles Tx frames sent back to Host for inspection
  1802. * (ProxyARP)
  1803. *
  1804. * Return: none
  1805. */
  1806. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1807. {
  1808. struct dp_soc *soc;
  1809. struct dp_pdev *pdev = tx_desc->pdev;
  1810. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1811. "%s Tx inspect path\n",
  1812. __func__);
  1813. qdf_assert(pdev);
  1814. soc = pdev->soc;
  1815. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1816. qdf_nbuf_len(tx_desc->nbuf));
  1817. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1818. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1819. }
  1820. #ifdef FEATURE_PERPKT_INFO
  1821. QDF_STATUS
  1822. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1823. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1824. {
  1825. struct tx_capture_hdr *ppdu_hdr;
  1826. struct dp_peer *peer = NULL;
  1827. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1828. return QDF_STATUS_E_NOSUPPORT;
  1829. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1830. dp_peer_find_by_id(soc, peer_id);
  1831. if (!peer) {
  1832. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1833. FL("Peer Invalid"));
  1834. return QDF_STATUS_E_INVAL;
  1835. }
  1836. if (pdev->mcopy_mode) {
  1837. if ((pdev->am_copy_id.tx_ppdu_id == ppdu_id) &&
  1838. (pdev->am_copy_id.tx_peer_id == peer_id)) {
  1839. return QDF_STATUS_E_INVAL;
  1840. }
  1841. pdev->am_copy_id.tx_ppdu_id = ppdu_id;
  1842. pdev->am_copy_id.tx_peer_id = peer_id;
  1843. }
  1844. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1845. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1846. FL("No headroom"));
  1847. return QDF_STATUS_E_NOMEM;
  1848. }
  1849. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1850. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1851. IEEE80211_ADDR_LEN);
  1852. ppdu_hdr->ppdu_id = ppdu_id;
  1853. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1854. IEEE80211_ADDR_LEN);
  1855. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1856. netbuf, peer_id,
  1857. WDI_NO_VAL, pdev->pdev_id);
  1858. return QDF_STATUS_SUCCESS;
  1859. }
  1860. #else
  1861. static QDF_STATUS
  1862. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1863. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1864. {
  1865. return QDF_STATUS_E_NOSUPPORT;
  1866. }
  1867. #endif
  1868. /**
  1869. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1870. * @soc: Soc handle
  1871. * @desc: software Tx descriptor to be processed
  1872. *
  1873. * Return: none
  1874. */
  1875. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1876. struct dp_tx_desc_s *desc)
  1877. {
  1878. struct dp_vdev *vdev = desc->vdev;
  1879. qdf_nbuf_t nbuf = desc->nbuf;
  1880. struct hal_tx_completion_status ts = {0};
  1881. if (desc)
  1882. hal_tx_comp_get_status(&desc->comp, &ts);
  1883. /* If it is TDLS mgmt, don't unmap or free the frame */
  1884. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1885. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1886. /* 0 : MSDU buffer, 1 : MLE */
  1887. if (desc->msdu_ext_desc) {
  1888. /* TSO free */
  1889. if (hal_tx_ext_desc_get_tso_enable(
  1890. desc->msdu_ext_desc->vaddr)) {
  1891. /* If remaining number of segment is 0
  1892. * actual TSO may unmap and free */
  1893. if (qdf_nbuf_get_users(nbuf) == 1)
  1894. __qdf_nbuf_unmap_single(soc->osdev,
  1895. nbuf,
  1896. QDF_DMA_TO_DEVICE);
  1897. qdf_nbuf_free(nbuf);
  1898. return;
  1899. }
  1900. }
  1901. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1902. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1903. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1904. if (dp_send_compl_to_stack(soc, desc->pdev, ts.peer_id,
  1905. ts.ppdu_id, nbuf) == QDF_STATUS_SUCCESS)
  1906. return;
  1907. if (!vdev->mesh_vdev) {
  1908. qdf_nbuf_free(nbuf);
  1909. } else {
  1910. vdev->osif_tx_free_ext((nbuf));
  1911. }
  1912. }
  1913. /**
  1914. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1915. * @vdev: pointer to dp dev handler
  1916. * @status : Tx completion status from HTT descriptor
  1917. *
  1918. * Handles MEC notify event sent from fw to Host
  1919. *
  1920. * Return: none
  1921. */
  1922. #ifdef FEATURE_WDS
  1923. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1924. {
  1925. struct dp_soc *soc;
  1926. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1927. struct dp_peer *peer;
  1928. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1929. soc = vdev->pdev->soc;
  1930. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1931. peer = TAILQ_FIRST(&vdev->peer_list);
  1932. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1933. if (!peer) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1935. FL("peer is NULL"));
  1936. return;
  1937. }
  1938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1939. "%s Tx MEC Handler\n",
  1940. __func__);
  1941. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1942. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1943. status[(DP_MAC_ADDR_LEN - 2) + i];
  1944. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1945. !dp_peer_add_ast(soc, peer, mac_addr, dp_ast_type_mec)) {
  1946. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1947. vdev->osif_vdev,
  1948. mac_addr,
  1949. vdev->mac_addr.raw,
  1950. flags);
  1951. }
  1952. }
  1953. #else
  1954. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1955. {
  1956. }
  1957. #endif
  1958. /**
  1959. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1960. * @tx_desc: software descriptor head pointer
  1961. * @status : Tx completion status from HTT descriptor
  1962. *
  1963. * This function will process HTT Tx indication messages from Target
  1964. *
  1965. * Return: none
  1966. */
  1967. static
  1968. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1969. {
  1970. uint8_t tx_status;
  1971. struct dp_pdev *pdev;
  1972. struct dp_vdev *vdev;
  1973. struct dp_soc *soc;
  1974. uint32_t *htt_status_word = (uint32_t *) status;
  1975. qdf_assert(tx_desc->pdev);
  1976. pdev = tx_desc->pdev;
  1977. vdev = tx_desc->vdev;
  1978. soc = pdev->soc;
  1979. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1980. switch (tx_status) {
  1981. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1982. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1983. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1984. {
  1985. dp_tx_comp_free_buf(soc, tx_desc);
  1986. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1987. break;
  1988. }
  1989. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1990. {
  1991. dp_tx_reinject_handler(tx_desc, status);
  1992. break;
  1993. }
  1994. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1995. {
  1996. dp_tx_inspect_handler(tx_desc, status);
  1997. break;
  1998. }
  1999. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2000. {
  2001. dp_tx_mec_handler(vdev, status);
  2002. break;
  2003. }
  2004. default:
  2005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2006. "%s Invalid HTT tx_status %d\n",
  2007. __func__, tx_status);
  2008. break;
  2009. }
  2010. }
  2011. #ifdef MESH_MODE_SUPPORT
  2012. /**
  2013. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2014. * in mesh meta header
  2015. * @tx_desc: software descriptor head pointer
  2016. * @ts: pointer to tx completion stats
  2017. * Return: none
  2018. */
  2019. static
  2020. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2021. struct hal_tx_completion_status *ts)
  2022. {
  2023. struct meta_hdr_s *mhdr;
  2024. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2025. if (!tx_desc->msdu_ext_desc) {
  2026. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2028. "netbuf %pK offset %d\n",
  2029. netbuf, tx_desc->pkt_offset);
  2030. return;
  2031. }
  2032. }
  2033. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2034. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2035. "netbuf %pK offset %d\n", netbuf,
  2036. sizeof(struct meta_hdr_s));
  2037. return;
  2038. }
  2039. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2040. mhdr->rssi = ts->ack_frame_rssi;
  2041. mhdr->channel = tx_desc->pdev->operating_channel;
  2042. }
  2043. #else
  2044. static
  2045. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2046. struct hal_tx_completion_status *ts)
  2047. {
  2048. }
  2049. #endif
  2050. /**
  2051. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2052. * @peer: Handle to DP peer
  2053. * @ts: pointer to HAL Tx completion stats
  2054. * @length: MSDU length
  2055. *
  2056. * Return: None
  2057. */
  2058. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2059. struct hal_tx_completion_status *ts, uint32_t length)
  2060. {
  2061. struct dp_pdev *pdev = peer->vdev->pdev;
  2062. struct dp_soc *soc = pdev->soc;
  2063. uint8_t mcs, pkt_type;
  2064. mcs = ts->mcs;
  2065. pkt_type = ts->pkt_type;
  2066. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2067. return;
  2068. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2069. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2070. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2071. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2072. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2073. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2074. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2075. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2076. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2077. return;
  2078. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2079. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2080. if (!(soc->process_tx_status))
  2081. return;
  2082. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2083. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2084. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2085. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2086. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2087. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2088. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2089. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2090. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2091. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2092. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2093. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2094. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2095. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2096. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2097. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2098. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2099. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2100. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2101. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2102. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2103. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2104. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2105. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2106. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2107. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2108. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2109. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2110. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2111. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2112. &peer->stats, ts->peer_id,
  2113. UPDATE_PEER_STATS);
  2114. }
  2115. }
  2116. /**
  2117. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2118. * @tx_desc: software descriptor head pointer
  2119. * @length: packet length
  2120. *
  2121. * Return: none
  2122. */
  2123. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2124. uint32_t length)
  2125. {
  2126. struct hal_tx_completion_status ts;
  2127. struct dp_soc *soc = NULL;
  2128. struct dp_vdev *vdev = tx_desc->vdev;
  2129. struct dp_peer *peer = NULL;
  2130. struct ether_header *eh =
  2131. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2132. bool isBroadcast;
  2133. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2135. "-------------------- \n"
  2136. "Tx Completion Stats: \n"
  2137. "-------------------- \n"
  2138. "ack_frame_rssi = %d \n"
  2139. "first_msdu = %d \n"
  2140. "last_msdu = %d \n"
  2141. "msdu_part_of_amsdu = %d \n"
  2142. "rate_stats valid = %d \n"
  2143. "bw = %d \n"
  2144. "pkt_type = %d \n"
  2145. "stbc = %d \n"
  2146. "ldpc = %d \n"
  2147. "sgi = %d \n"
  2148. "mcs = %d \n"
  2149. "ofdma = %d \n"
  2150. "tones_in_ru = %d \n"
  2151. "tsf = %d \n"
  2152. "ppdu_id = %d \n"
  2153. "transmit_cnt = %d \n"
  2154. "tid = %d \n"
  2155. "peer_id = %d \n",
  2156. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2157. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2158. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2159. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2160. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2161. ts.peer_id);
  2162. if (!vdev) {
  2163. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2164. "invalid vdev");
  2165. goto out;
  2166. }
  2167. soc = vdev->pdev->soc;
  2168. /* Update SoC level stats */
  2169. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2170. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2171. /* Update per-packet stats */
  2172. if (qdf_unlikely(vdev->mesh_vdev))
  2173. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2174. /* Update peer level stats */
  2175. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2176. if (!peer) {
  2177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2178. "invalid peer");
  2179. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2180. goto out;
  2181. }
  2182. if (qdf_likely(vdev->tx_encap_type == htt_cmn_pkt_type_ethernet)) {
  2183. isBroadcast = (IEEE80211_IS_BROADCAST(eh->ether_dhost)) ? 1 : 0 ;
  2184. if (isBroadcast) {
  2185. DP_STATS_INC_PKT(peer, tx.bcast, 1,
  2186. qdf_nbuf_len(tx_desc->nbuf));
  2187. }
  2188. }
  2189. dp_tx_update_peer_stats(peer, &ts, length);
  2190. out:
  2191. return;
  2192. }
  2193. /**
  2194. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2195. * @soc: core txrx main context
  2196. * @comp_head: software descriptor head pointer
  2197. *
  2198. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2199. * and release the software descriptors after processing is complete
  2200. *
  2201. * Return: none
  2202. */
  2203. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2204. struct dp_tx_desc_s *comp_head)
  2205. {
  2206. struct dp_tx_desc_s *desc;
  2207. struct dp_tx_desc_s *next;
  2208. struct hal_tx_completion_status ts = {0};
  2209. uint32_t length;
  2210. struct dp_peer *peer;
  2211. DP_HIST_INIT();
  2212. desc = comp_head;
  2213. while (desc) {
  2214. hal_tx_comp_get_status(&desc->comp, &ts);
  2215. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2216. length = qdf_nbuf_len(desc->nbuf);
  2217. dp_tx_comp_process_tx_status(desc, length);
  2218. dp_tx_comp_free_buf(soc, desc);
  2219. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2220. next = desc->next;
  2221. dp_tx_desc_release(desc, desc->pool_id);
  2222. desc = next;
  2223. }
  2224. DP_TX_HIST_STATS_PER_PDEV();
  2225. }
  2226. /**
  2227. * dp_tx_comp_handler() - Tx completion handler
  2228. * @soc: core txrx main context
  2229. * @ring_id: completion ring id
  2230. * @quota: No. of packets/descriptors that can be serviced in one loop
  2231. *
  2232. * This function will collect hardware release ring element contents and
  2233. * handle descriptor contents. Based on contents, free packet or handle error
  2234. * conditions
  2235. *
  2236. * Return: none
  2237. */
  2238. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2239. {
  2240. void *tx_comp_hal_desc;
  2241. uint8_t buffer_src;
  2242. uint8_t pool_id;
  2243. uint32_t tx_desc_id;
  2244. struct dp_tx_desc_s *tx_desc = NULL;
  2245. struct dp_tx_desc_s *head_desc = NULL;
  2246. struct dp_tx_desc_s *tail_desc = NULL;
  2247. uint32_t num_processed;
  2248. uint32_t count;
  2249. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2250. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2251. "%s %d : HAL RING Access Failed -- %pK\n",
  2252. __func__, __LINE__, hal_srng);
  2253. return 0;
  2254. }
  2255. num_processed = 0;
  2256. count = 0;
  2257. /* Find head descriptor from completion ring */
  2258. while (qdf_likely(tx_comp_hal_desc =
  2259. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2260. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2261. /* If this buffer was not released by TQM or FW, then it is not
  2262. * Tx completion indication, assert */
  2263. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2264. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2265. QDF_TRACE(QDF_MODULE_ID_DP,
  2266. QDF_TRACE_LEVEL_FATAL,
  2267. "Tx comp release_src != TQM | FW");
  2268. qdf_assert_always(0);
  2269. }
  2270. /* Get descriptor id */
  2271. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2272. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2273. DP_TX_DESC_ID_POOL_OS;
  2274. /* Pool ID is out of limit. Error */
  2275. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2276. soc->wlan_cfg_ctx)) {
  2277. QDF_TRACE(QDF_MODULE_ID_DP,
  2278. QDF_TRACE_LEVEL_FATAL,
  2279. "Tx Comp pool id %d not valid",
  2280. pool_id);
  2281. qdf_assert_always(0);
  2282. }
  2283. /* Find Tx descriptor */
  2284. tx_desc = dp_tx_desc_find(soc, pool_id,
  2285. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2286. DP_TX_DESC_ID_PAGE_OS,
  2287. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2288. DP_TX_DESC_ID_OFFSET_OS);
  2289. /* Pool id is not matching. Error */
  2290. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  2291. QDF_TRACE(QDF_MODULE_ID_DP,
  2292. QDF_TRACE_LEVEL_FATAL,
  2293. "Tx Comp pool id %d not matched %d",
  2294. pool_id, tx_desc->pool_id);
  2295. qdf_assert_always(0);
  2296. }
  2297. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2298. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2299. QDF_TRACE(QDF_MODULE_ID_DP,
  2300. QDF_TRACE_LEVEL_FATAL,
  2301. "Txdesc invalid, flgs = %x,id = %d",
  2302. tx_desc->flags, tx_desc_id);
  2303. qdf_assert_always(0);
  2304. }
  2305. /*
  2306. * If the release source is FW, process the HTT status
  2307. */
  2308. if (qdf_unlikely(buffer_src ==
  2309. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2310. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2311. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2312. htt_tx_status);
  2313. dp_tx_process_htt_completion(tx_desc,
  2314. htt_tx_status);
  2315. } else {
  2316. /* First ring descriptor on the cycle */
  2317. if (!head_desc) {
  2318. head_desc = tx_desc;
  2319. tail_desc = tx_desc;
  2320. }
  2321. tail_desc->next = tx_desc;
  2322. tx_desc->next = NULL;
  2323. tail_desc = tx_desc;
  2324. /* Collect hw completion contents */
  2325. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2326. &tx_desc->comp, 1);
  2327. }
  2328. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2329. /* Decrement PM usage count if the packet has been sent.*/
  2330. hif_pm_runtime_put(soc->hif_handle);
  2331. /*
  2332. * Processed packet count is more than given quota
  2333. * stop to processing
  2334. */
  2335. if ((num_processed >= quota))
  2336. break;
  2337. count++;
  2338. }
  2339. hal_srng_access_end(soc->hal_soc, hal_srng);
  2340. /* Process the reaped descriptors */
  2341. if (head_desc)
  2342. dp_tx_comp_process_desc(soc, head_desc);
  2343. return num_processed;
  2344. }
  2345. #ifdef CONVERGED_TDLS_ENABLE
  2346. /**
  2347. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2348. *
  2349. * @data_vdev - which vdev should transmit the tx data frames
  2350. * @tx_spec - what non-standard handling to apply to the tx data frames
  2351. * @msdu_list - NULL-terminated list of tx MSDUs
  2352. *
  2353. * Return: NULL on success,
  2354. * nbuf when it fails to send
  2355. */
  2356. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2357. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2358. {
  2359. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2360. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2361. vdev->is_tdls_frame = true;
  2362. return dp_tx_send(vdev_handle, msdu_list);
  2363. }
  2364. #endif
  2365. /**
  2366. * dp_tx_vdev_attach() - attach vdev to dp tx
  2367. * @vdev: virtual device instance
  2368. *
  2369. * Return: QDF_STATUS_SUCCESS: success
  2370. * QDF_STATUS_E_RESOURCES: Error return
  2371. */
  2372. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2373. {
  2374. /*
  2375. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2376. */
  2377. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2378. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2379. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2380. vdev->vdev_id);
  2381. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2382. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2383. /*
  2384. * Set HTT Extension Valid bit to 0 by default
  2385. */
  2386. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2387. dp_tx_vdev_update_search_flags(vdev);
  2388. return QDF_STATUS_SUCCESS;
  2389. }
  2390. /**
  2391. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2392. * @vdev: virtual device instance
  2393. *
  2394. * Return: void
  2395. *
  2396. */
  2397. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2398. {
  2399. /*
  2400. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2401. * for TDLS link
  2402. *
  2403. * Enable AddrY (SA based search) only for non-WDS STA and
  2404. * ProxySTA VAP modes.
  2405. *
  2406. * In all other VAP modes, only DA based search should be
  2407. * enabled
  2408. */
  2409. if (vdev->opmode == wlan_op_mode_sta &&
  2410. vdev->tdls_link_connected)
  2411. vdev->hal_desc_addr_search_flags =
  2412. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2413. else if ((vdev->opmode == wlan_op_mode_sta &&
  2414. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2415. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2416. else
  2417. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2418. }
  2419. /**
  2420. * dp_tx_vdev_detach() - detach vdev from dp tx
  2421. * @vdev: virtual device instance
  2422. *
  2423. * Return: QDF_STATUS_SUCCESS: success
  2424. * QDF_STATUS_E_RESOURCES: Error return
  2425. */
  2426. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2427. {
  2428. return QDF_STATUS_SUCCESS;
  2429. }
  2430. /**
  2431. * dp_tx_pdev_attach() - attach pdev to dp tx
  2432. * @pdev: physical device instance
  2433. *
  2434. * Return: QDF_STATUS_SUCCESS: success
  2435. * QDF_STATUS_E_RESOURCES: Error return
  2436. */
  2437. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2438. {
  2439. struct dp_soc *soc = pdev->soc;
  2440. /* Initialize Flow control counters */
  2441. qdf_atomic_init(&pdev->num_tx_exception);
  2442. qdf_atomic_init(&pdev->num_tx_outstanding);
  2443. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2444. /* Initialize descriptors in TCL Ring */
  2445. hal_tx_init_data_ring(soc->hal_soc,
  2446. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2447. }
  2448. return QDF_STATUS_SUCCESS;
  2449. }
  2450. /**
  2451. * dp_tx_pdev_detach() - detach pdev from dp tx
  2452. * @pdev: physical device instance
  2453. *
  2454. * Return: QDF_STATUS_SUCCESS: success
  2455. * QDF_STATUS_E_RESOURCES: Error return
  2456. */
  2457. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2458. {
  2459. dp_tx_me_exit(pdev);
  2460. return QDF_STATUS_SUCCESS;
  2461. }
  2462. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2463. /* Pools will be allocated dynamically */
  2464. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2465. int num_desc)
  2466. {
  2467. uint8_t i;
  2468. for (i = 0; i < num_pool; i++) {
  2469. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2470. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2471. }
  2472. return 0;
  2473. }
  2474. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2475. {
  2476. uint8_t i;
  2477. for (i = 0; i < num_pool; i++)
  2478. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2479. }
  2480. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2481. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2482. int num_desc)
  2483. {
  2484. uint8_t i;
  2485. /* Allocate software Tx descriptor pools */
  2486. for (i = 0; i < num_pool; i++) {
  2487. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2489. "%s Tx Desc Pool alloc %d failed %pK\n",
  2490. __func__, i, soc);
  2491. return ENOMEM;
  2492. }
  2493. }
  2494. return 0;
  2495. }
  2496. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2497. {
  2498. uint8_t i;
  2499. for (i = 0; i < num_pool; i++) {
  2500. if (dp_tx_desc_pool_free(soc, i)) {
  2501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2502. "%s Tx Desc Pool Free failed\n", __func__);
  2503. }
  2504. }
  2505. }
  2506. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2507. /**
  2508. * dp_tx_soc_detach() - detach soc from dp tx
  2509. * @soc: core txrx main context
  2510. *
  2511. * This function will detach dp tx into main device context
  2512. * will free dp tx resource and initialize resources
  2513. *
  2514. * Return: QDF_STATUS_SUCCESS: success
  2515. * QDF_STATUS_E_RESOURCES: Error return
  2516. */
  2517. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2518. {
  2519. uint8_t num_pool;
  2520. uint16_t num_desc;
  2521. uint16_t num_ext_desc;
  2522. uint8_t i;
  2523. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2524. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2525. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2526. dp_tx_flow_control_deinit(soc);
  2527. dp_tx_delete_static_pools(soc, num_pool);
  2528. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2529. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2530. __func__, num_pool, num_desc);
  2531. for (i = 0; i < num_pool; i++) {
  2532. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2533. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2534. "%s Tx Ext Desc Pool Free failed\n",
  2535. __func__);
  2536. return QDF_STATUS_E_RESOURCES;
  2537. }
  2538. }
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2540. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2541. __func__, num_pool, num_ext_desc);
  2542. for (i = 0; i < num_pool; i++) {
  2543. dp_tx_tso_desc_pool_free(soc, i);
  2544. }
  2545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2546. "%s TSO Desc Pool %d Free descs = %d\n",
  2547. __func__, num_pool, num_desc);
  2548. for (i = 0; i < num_pool; i++)
  2549. dp_tx_tso_num_seg_pool_free(soc, i);
  2550. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2551. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2552. __func__, num_pool, num_desc);
  2553. return QDF_STATUS_SUCCESS;
  2554. }
  2555. /**
  2556. * dp_tx_soc_attach() - attach soc to dp tx
  2557. * @soc: core txrx main context
  2558. *
  2559. * This function will attach dp tx into main device context
  2560. * will allocate dp tx resource and initialize resources
  2561. *
  2562. * Return: QDF_STATUS_SUCCESS: success
  2563. * QDF_STATUS_E_RESOURCES: Error return
  2564. */
  2565. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2566. {
  2567. uint8_t i;
  2568. uint8_t num_pool;
  2569. uint32_t num_desc;
  2570. uint32_t num_ext_desc;
  2571. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2572. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2573. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2574. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2575. goto fail;
  2576. dp_tx_flow_control_init(soc);
  2577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2578. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2579. __func__, num_pool, num_desc);
  2580. /* Allocate extension tx descriptor pools */
  2581. for (i = 0; i < num_pool; i++) {
  2582. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2583. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2584. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2585. i, soc);
  2586. goto fail;
  2587. }
  2588. }
  2589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2590. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2591. __func__, num_pool, num_ext_desc);
  2592. for (i = 0; i < num_pool; i++) {
  2593. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2595. "TSO Desc Pool alloc %d failed %pK\n",
  2596. i, soc);
  2597. goto fail;
  2598. }
  2599. }
  2600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2601. "%s TSO Desc Alloc %d, descs = %d\n",
  2602. __func__, num_pool, num_desc);
  2603. for (i = 0; i < num_pool; i++) {
  2604. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2606. "TSO Num of seg Pool alloc %d failed %pK\n",
  2607. i, soc);
  2608. goto fail;
  2609. }
  2610. }
  2611. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2612. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2613. __func__, num_pool, num_desc);
  2614. /* Initialize descriptors in TCL Rings */
  2615. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2616. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2617. hal_tx_init_data_ring(soc->hal_soc,
  2618. soc->tcl_data_ring[i].hal_srng);
  2619. }
  2620. }
  2621. /*
  2622. * todo - Add a runtime config option to enable this.
  2623. */
  2624. /*
  2625. * Due to multiple issues on NPR EMU, enable it selectively
  2626. * only for NPR EMU, should be removed, once NPR platforms
  2627. * are stable.
  2628. */
  2629. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2631. "%s HAL Tx init Success\n", __func__);
  2632. return QDF_STATUS_SUCCESS;
  2633. fail:
  2634. /* Detach will take care of freeing only allocated resources */
  2635. dp_tx_soc_detach(soc);
  2636. return QDF_STATUS_E_RESOURCES;
  2637. }
  2638. /*
  2639. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2640. * pdev: pointer to DP PDEV structure
  2641. * seg_info_head: Pointer to the head of list
  2642. *
  2643. * return: void
  2644. */
  2645. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2646. struct dp_tx_seg_info_s *seg_info_head)
  2647. {
  2648. struct dp_tx_me_buf_t *mc_uc_buf;
  2649. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2650. qdf_nbuf_t nbuf = NULL;
  2651. uint64_t phy_addr;
  2652. while (seg_info_head) {
  2653. nbuf = seg_info_head->nbuf;
  2654. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2655. seg_info_head->frags[0].vaddr;
  2656. phy_addr = seg_info_head->frags[0].paddr_hi;
  2657. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2658. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2659. phy_addr,
  2660. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2661. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2662. qdf_nbuf_free(nbuf);
  2663. seg_info_new = seg_info_head;
  2664. seg_info_head = seg_info_head->next;
  2665. qdf_mem_free(seg_info_new);
  2666. }
  2667. }
  2668. /**
  2669. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2670. * @vdev: DP VDEV handle
  2671. * @nbuf: Multicast nbuf
  2672. * @newmac: Table of the clients to which packets have to be sent
  2673. * @new_mac_cnt: No of clients
  2674. *
  2675. * return: no of converted packets
  2676. */
  2677. uint16_t
  2678. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2679. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2680. {
  2681. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2682. struct dp_pdev *pdev = vdev->pdev;
  2683. struct ether_header *eh;
  2684. uint8_t *data;
  2685. uint16_t len;
  2686. /* reference to frame dst addr */
  2687. uint8_t *dstmac;
  2688. /* copy of original frame src addr */
  2689. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2690. /* local index into newmac */
  2691. uint8_t new_mac_idx = 0;
  2692. struct dp_tx_me_buf_t *mc_uc_buf;
  2693. qdf_nbuf_t nbuf_clone;
  2694. struct dp_tx_msdu_info_s msdu_info;
  2695. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2696. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2697. struct dp_tx_seg_info_s *seg_info_new;
  2698. struct dp_tx_frag_info_s data_frag;
  2699. qdf_dma_addr_t paddr_data;
  2700. qdf_dma_addr_t paddr_mcbuf = 0;
  2701. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2702. QDF_STATUS status;
  2703. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2704. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2705. eh = (struct ether_header *) nbuf;
  2706. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2707. len = qdf_nbuf_len(nbuf);
  2708. data = qdf_nbuf_data(nbuf);
  2709. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2710. QDF_DMA_TO_DEVICE);
  2711. if (status) {
  2712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2713. "Mapping failure Error:%d", status);
  2714. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2715. return 0;
  2716. }
  2717. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2718. /*preparing data fragment*/
  2719. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2720. data_frag.paddr_lo = (uint32_t)paddr_data;
  2721. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2722. data_frag.len = len - DP_MAC_ADDR_LEN;
  2723. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2724. dstmac = newmac[new_mac_idx];
  2725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2726. "added mac addr (%pM)", dstmac);
  2727. /* Check for NULL Mac Address */
  2728. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2729. continue;
  2730. /* frame to self mac. skip */
  2731. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2732. continue;
  2733. /*
  2734. * TODO: optimize to avoid malloc in per-packet path
  2735. * For eg. seg_pool can be made part of vdev structure
  2736. */
  2737. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2738. if (!seg_info_new) {
  2739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2740. "alloc failed");
  2741. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2742. goto fail_seg_alloc;
  2743. }
  2744. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2745. if (mc_uc_buf == NULL)
  2746. goto fail_buf_alloc;
  2747. /*
  2748. * TODO: Check if we need to clone the nbuf
  2749. * Or can we just use the reference for all cases
  2750. */
  2751. if (new_mac_idx < (new_mac_cnt - 1)) {
  2752. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2753. if (nbuf_clone == NULL) {
  2754. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2755. goto fail_clone;
  2756. }
  2757. } else {
  2758. /*
  2759. * Update the ref
  2760. * to account for frame sent without cloning
  2761. */
  2762. qdf_nbuf_ref(nbuf);
  2763. nbuf_clone = nbuf;
  2764. }
  2765. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2766. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2767. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2768. &paddr_mcbuf);
  2769. if (status) {
  2770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2771. "Mapping failure Error:%d", status);
  2772. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2773. goto fail_map;
  2774. }
  2775. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2776. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2777. seg_info_new->frags[0].paddr_hi =
  2778. ((uint64_t) paddr_mcbuf >> 32);
  2779. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2780. seg_info_new->frags[1] = data_frag;
  2781. seg_info_new->nbuf = nbuf_clone;
  2782. seg_info_new->frag_cnt = 2;
  2783. seg_info_new->total_len = len;
  2784. seg_info_new->next = NULL;
  2785. if (seg_info_head == NULL)
  2786. seg_info_head = seg_info_new;
  2787. else
  2788. seg_info_tail->next = seg_info_new;
  2789. seg_info_tail = seg_info_new;
  2790. }
  2791. if (!seg_info_head)
  2792. return 0;
  2793. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2794. msdu_info.num_seg = new_mac_cnt;
  2795. msdu_info.frm_type = dp_tx_frm_me;
  2796. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2797. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2798. while (seg_info_head->next) {
  2799. seg_info_new = seg_info_head;
  2800. seg_info_head = seg_info_head->next;
  2801. qdf_mem_free(seg_info_new);
  2802. }
  2803. qdf_mem_free(seg_info_head);
  2804. return new_mac_cnt;
  2805. fail_map:
  2806. qdf_nbuf_free(nbuf_clone);
  2807. fail_clone:
  2808. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2809. fail_buf_alloc:
  2810. qdf_mem_free(seg_info_new);
  2811. fail_seg_alloc:
  2812. dp_tx_me_mem_free(pdev, seg_info_head);
  2813. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2814. return 0;
  2815. }