8eda31cab3
Add code to replace usage of void pointers from HAL layer and instead use appropriate opaque pointers Change-Id: Id950bd9130a99014305738937aed736cf0144aca CRs-Fixed: 2487250
166 rader
5.8 KiB
C
166 rader
5.8 KiB
C
/*
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* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* hal_setup_link_idle_list - Setup scattered idle list using the
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* buffer list provided
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*
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* @hal_soc: Opaque HAL SOC handle
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* @scatter_bufs_base_paddr: Array of physical base addresses
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* @scatter_bufs_base_vaddr: Array of virtual base addresses
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* @num_scatter_bufs: Number of scatter buffers in the above lists
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* @scatter_buf_size: Size of each scatter buffer
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* @last_buf_end_offset: Offset to the last entry
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* @num_entries: Total entries of all scatter bufs
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*
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*/
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static void
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hal_setup_link_idle_list_generic(struct hal_soc *soc,
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qdf_dma_addr_t scatter_bufs_base_paddr[],
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void *scatter_bufs_base_vaddr[],
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uint32_t num_scatter_bufs,
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uint32_t scatter_buf_size,
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uint32_t last_buf_end_offset,
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uint32_t num_entries)
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{
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int i;
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uint32_t *prev_buf_link_ptr = NULL;
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uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
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uint32_t val;
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/* Link the scatter buffers */
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for (i = 0; i < num_scatter_bufs; i++) {
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if (i > 0) {
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prev_buf_link_ptr[0] =
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scatter_bufs_base_paddr[i] & 0xffffffff;
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prev_buf_link_ptr[1] = HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[i])
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>> 32)) | HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG,
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ADDRESS_MATCH_TAG_VAL);
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}
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prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
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scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
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}
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/* TBD: Register programming partly based on MLD & the rest based on
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* inputs from HW team. Not complete yet.
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*/
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reg_scatter_buf_size = (scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)/64;
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reg_tot_scatter_buf_size = ((scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs)/64;
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
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reg_scatter_buf_size) |
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
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0x1));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
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SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
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reg_tot_scatter_buf_size));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
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/* ADDRESS_MATCH_TAG field in the above register is expected to match
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* with the upper bits of link pointer. The above write sets this field
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* to zero and we are also setting the upper bits of link pointers to
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* zero while setting up the link list of scatter buffers above
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*/
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/* Setup head and tail pointers for the idle list */
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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scatter_bufs_base_paddr[num_scatter_bufs-1] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs-1])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[0]) >>
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32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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TAIL_POINTER_OFFSET, 0));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
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SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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2*num_entries);
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/* Set RING_ID_DISABLE */
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val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
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/*
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* SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
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* check the presence of the bit before toggling it.
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*/
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#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
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val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
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#endif
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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val);
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}
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