wcd937x.c 80 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define NUM_SWRS_DT_PARAMS 5
  30. #define WCD937X_VERSION_1_0 1
  31. #define WCD937X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. enum {
  34. CODEC_TX = 0,
  35. CODEC_RX,
  36. };
  37. enum {
  38. ALLOW_BUCK_DISABLE,
  39. HPH_COMP_DELAY,
  40. HPH_PA_DELAY,
  41. };
  42. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  43. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  44. static int wcd937x_handle_post_irq(void *data);
  45. static int wcd937x_reset(struct device *dev);
  46. static int wcd937x_reset_low(struct device *dev);
  47. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  48. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  49. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  68. };
  69. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  70. .name = "wcd937x",
  71. .irqs = wcd937x_irqs,
  72. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  73. .num_regs = 3,
  74. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  75. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  76. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  77. .use_ack = 1,
  78. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  79. .runtime_pm = false,
  80. .handle_post_irq = wcd937x_handle_post_irq,
  81. .irq_drv_data = NULL,
  82. };
  83. static int wcd937x_handle_post_irq(void *data)
  84. {
  85. struct wcd937x_priv *wcd937x = data;
  86. u32 status1 = 0, status2 = 0, status3 = 0;
  87. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  88. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  90. wcd937x->tx_swr_dev->slave_irq_pending =
  91. ((status1 || status2 || status3) ? true : false);
  92. return IRQ_HANDLED;
  93. }
  94. static int wcd937x_init_reg(struct snd_soc_component *component)
  95. {
  96. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  97. 0x0E, 0x0E);
  98. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  99. 0x80, 0x80);
  100. usleep_range(1000, 1010);
  101. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  102. 0x40, 0x40);
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  105. 0x10, 0x00);
  106. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  107. 0xF0, 0x80);
  108. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  109. 0x80, 0x80);
  110. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  111. 0x40, 0x40);
  112. usleep_range(10000, 10010);
  113. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  114. 0x40, 0x00);
  115. snd_soc_component_update_bits(component, WCD937X_HPH_OCP_CTL,
  116. 0xFF, 0x3A);
  117. snd_soc_component_update_bits(component, WCD937X_RX_OCP_CTL,
  118. 0x0F, 0x02);
  119. return 0;
  120. }
  121. static int wcd937x_set_port_params(struct snd_soc_component *component,
  122. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  123. u8 *ch_mask, u32 *ch_rate,
  124. u8 *port_type, u8 path)
  125. {
  126. int i, j;
  127. u8 num_ports = 0;
  128. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  129. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  130. switch (path) {
  131. case CODEC_RX:
  132. map = &wcd937x->rx_port_mapping;
  133. num_ports = wcd937x->num_rx_ports;
  134. break;
  135. case CODEC_TX:
  136. map = &wcd937x->tx_port_mapping;
  137. num_ports = wcd937x->num_tx_ports;
  138. break;
  139. }
  140. for (i = 0; i <= num_ports; i++) {
  141. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  142. if ((*map)[i][j].slave_port_type == slv_prt_type)
  143. goto found;
  144. }
  145. }
  146. found:
  147. if (i > num_ports || j == MAX_CH_PER_PORT) {
  148. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  149. __func__, slv_prt_type);
  150. return -EINVAL;
  151. }
  152. *port_id = i;
  153. *num_ch = (*map)[i][j].num_ch;
  154. *ch_mask = (*map)[i][j].ch_mask;
  155. *ch_rate = (*map)[i][j].ch_rate;
  156. *port_type = (*map)[i][j].master_port_type;
  157. return 0;
  158. }
  159. static int wcd937x_parse_port_mapping(struct device *dev,
  160. char *prop, u8 path)
  161. {
  162. u32 *dt_array, map_size, map_length;
  163. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  164. u32 slave_port_type, master_port_type;
  165. u32 i, ch_iter = 0;
  166. int ret = 0;
  167. u8 *num_ports = NULL;
  168. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  169. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  170. switch (path) {
  171. case CODEC_RX:
  172. map = &wcd937x->rx_port_mapping;
  173. num_ports = &wcd937x->num_rx_ports;
  174. break;
  175. case CODEC_TX:
  176. map = &wcd937x->tx_port_mapping;
  177. num_ports = &wcd937x->num_tx_ports;
  178. break;
  179. }
  180. if (!of_find_property(dev->of_node, prop,
  181. &map_size)) {
  182. dev_err(dev, "missing port mapping prop %s\n", prop);
  183. ret = -EINVAL;
  184. goto err;
  185. }
  186. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  187. dt_array = kzalloc(map_size, GFP_KERNEL);
  188. if (!dt_array) {
  189. ret = -ENOMEM;
  190. goto err;
  191. }
  192. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  193. NUM_SWRS_DT_PARAMS * map_length);
  194. if (ret) {
  195. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  196. __func__, prop);
  197. ret = -EINVAL;
  198. goto err_pdata_fail;
  199. }
  200. for (i = 0; i < map_length; i++) {
  201. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  202. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  203. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  204. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  205. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  206. if (port_num != old_port_num)
  207. ch_iter = 0;
  208. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  209. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  210. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  211. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  212. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  213. old_port_num = port_num;
  214. }
  215. *num_ports = port_num;
  216. kfree(dt_array);
  217. return 0;
  218. err_pdata_fail:
  219. kfree(dt_array);
  220. err:
  221. return ret;
  222. }
  223. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  224. u8 slv_port_type, u8 enable)
  225. {
  226. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  227. u8 port_id;
  228. u8 num_ch;
  229. u8 ch_mask;
  230. u32 ch_rate;
  231. u8 port_type;
  232. u8 num_port = 1;
  233. int ret = 0;
  234. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  235. &num_ch, &ch_mask, &ch_rate,
  236. &port_type, CODEC_TX);
  237. if (ret)
  238. return ret;
  239. if (enable)
  240. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  241. num_port, &ch_mask, &ch_rate,
  242. &num_ch, &port_type);
  243. else
  244. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  245. num_port, &ch_mask, &port_type);
  246. return ret;
  247. }
  248. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  249. u8 slv_port_type, u8 enable)
  250. {
  251. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  252. u8 port_id;
  253. u8 num_ch;
  254. u8 ch_mask;
  255. u32 ch_rate;
  256. u8 port_type;
  257. u8 num_port = 1;
  258. int ret = 0;
  259. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  260. &num_ch, &ch_mask, &ch_rate,
  261. &port_type, CODEC_RX);
  262. if (ret)
  263. return ret;
  264. if (enable)
  265. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  266. num_port, &ch_mask, &ch_rate,
  267. &num_ch, &port_type);
  268. else
  269. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  270. num_port, &ch_mask, &port_type);
  271. return ret;
  272. }
  273. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  274. {
  275. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  276. if (wcd937x->rx_clk_cnt == 0) {
  277. snd_soc_component_update_bits(component,
  278. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  279. snd_soc_component_update_bits(component,
  280. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  281. snd_soc_component_update_bits(component,
  282. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  283. snd_soc_component_update_bits(component,
  284. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  285. snd_soc_component_update_bits(component,
  286. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  287. snd_soc_component_update_bits(component,
  288. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  289. snd_soc_component_update_bits(component,
  290. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  291. }
  292. wcd937x->rx_clk_cnt++;
  293. return 0;
  294. }
  295. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  296. {
  297. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  298. if (wcd937x->rx_clk_cnt == 0) {
  299. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  300. return 0;
  301. }
  302. wcd937x->rx_clk_cnt--;
  303. if (wcd937x->rx_clk_cnt == 0) {
  304. snd_soc_component_update_bits(component,
  305. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  306. snd_soc_component_update_bits(component,
  307. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  308. 0x02, 0x00);
  309. snd_soc_component_update_bits(component,
  310. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  311. 0x01, 0x00);
  312. }
  313. return 0;
  314. }
  315. /*
  316. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  317. * @component: handle to snd_soc_component *
  318. *
  319. * return wcd937x_mbhc handle or error code in case of failure
  320. */
  321. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  322. {
  323. struct wcd937x_priv *wcd937x;
  324. if (!component) {
  325. pr_err("%s: Invalid params, NULL component\n", __func__);
  326. return NULL;
  327. }
  328. wcd937x = snd_soc_component_get_drvdata(component);
  329. if (!wcd937x) {
  330. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  331. return NULL;
  332. }
  333. return wcd937x->mbhc;
  334. }
  335. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  336. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  337. struct snd_kcontrol *kcontrol,
  338. int event)
  339. {
  340. struct snd_soc_component *component =
  341. snd_soc_dapm_to_component(w->dapm);
  342. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  343. int hph_mode = wcd937x->hph_mode;
  344. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  345. w->name, event);
  346. switch (event) {
  347. case SND_SOC_DAPM_PRE_PMU:
  348. wcd937x_rx_clk_enable(component);
  349. snd_soc_component_update_bits(component,
  350. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  351. 0x01, 0x01);
  352. snd_soc_component_update_bits(component,
  353. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  354. 0x04, 0x04);
  355. snd_soc_component_update_bits(component,
  356. WCD937X_HPH_RDAC_CLK_CTL1,
  357. 0x80, 0x00);
  358. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  359. break;
  360. case SND_SOC_DAPM_POST_PMU:
  361. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  362. snd_soc_component_update_bits(component,
  363. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  364. 0x0F, 0x02);
  365. else if (hph_mode == CLS_H_LOHIFI)
  366. snd_soc_component_update_bits(component,
  367. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  368. 0x0F, 0x06);
  369. if (wcd937x->comp1_enable) {
  370. snd_soc_component_update_bits(component,
  371. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  372. 0x02, 0x02);
  373. snd_soc_component_update_bits(component,
  374. WCD937X_HPH_L_EN, 0x20, 0x00);
  375. if (wcd937x->comp2_enable) {
  376. snd_soc_component_update_bits(component,
  377. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  378. 0x01, 0x01);
  379. snd_soc_component_update_bits(component,
  380. WCD937X_HPH_R_EN, 0x20, 0x00);
  381. }
  382. /*
  383. * 5ms sleep is required after COMP is enabled as per
  384. * HW requirement
  385. */
  386. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  387. usleep_range(5000, 5100);
  388. clear_bit(HPH_COMP_DELAY,
  389. &wcd937x->status_mask);
  390. }
  391. } else {
  392. snd_soc_component_update_bits(component,
  393. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  394. 0x02, 0x00);
  395. snd_soc_component_update_bits(component,
  396. WCD937X_HPH_L_EN, 0x20, 0x20);
  397. }
  398. snd_soc_component_update_bits(component,
  399. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  400. break;
  401. case SND_SOC_DAPM_POST_PMD:
  402. snd_soc_component_update_bits(component,
  403. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  404. 0x0F, 0x01);
  405. break;
  406. }
  407. return 0;
  408. }
  409. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  410. struct snd_kcontrol *kcontrol,
  411. int event)
  412. {
  413. struct snd_soc_component *component =
  414. snd_soc_dapm_to_component(w->dapm);
  415. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  416. int hph_mode = wcd937x->hph_mode;
  417. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  418. w->name, event);
  419. switch (event) {
  420. case SND_SOC_DAPM_PRE_PMU:
  421. wcd937x_rx_clk_enable(component);
  422. snd_soc_component_update_bits(component,
  423. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  424. snd_soc_component_update_bits(component,
  425. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  426. snd_soc_component_update_bits(component,
  427. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  428. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  429. break;
  430. case SND_SOC_DAPM_POST_PMU:
  431. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  432. snd_soc_component_update_bits(component,
  433. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  434. 0x0F, 0x02);
  435. else if (hph_mode == CLS_H_LOHIFI)
  436. snd_soc_component_update_bits(component,
  437. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  438. 0x0F, 0x06);
  439. if (wcd937x->comp2_enable) {
  440. snd_soc_component_update_bits(component,
  441. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  442. 0x01, 0x01);
  443. snd_soc_component_update_bits(component,
  444. WCD937X_HPH_R_EN, 0x20, 0x00);
  445. if (wcd937x->comp1_enable) {
  446. snd_soc_component_update_bits(component,
  447. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x02, 0x02);
  449. snd_soc_component_update_bits(component,
  450. WCD937X_HPH_L_EN, 0x20, 0x00);
  451. }
  452. /*
  453. * 5ms sleep is required after COMP is enabled as per
  454. * HW requirement
  455. */
  456. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  457. usleep_range(5000, 5100);
  458. clear_bit(HPH_COMP_DELAY,
  459. &wcd937x->status_mask);
  460. }
  461. } else {
  462. snd_soc_component_update_bits(component,
  463. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  464. 0x01, 0x00);
  465. snd_soc_component_update_bits(component,
  466. WCD937X_HPH_R_EN, 0x20, 0x20);
  467. }
  468. snd_soc_component_update_bits(component,
  469. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  470. break;
  471. case SND_SOC_DAPM_POST_PMD:
  472. snd_soc_component_update_bits(component,
  473. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  474. 0x0F, 0x01);
  475. break;
  476. }
  477. return 0;
  478. }
  479. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  480. struct snd_kcontrol *kcontrol,
  481. int event)
  482. {
  483. struct snd_soc_component *component =
  484. snd_soc_dapm_to_component(w->dapm);
  485. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  486. int hph_mode = wcd937x->hph_mode;
  487. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  488. w->name, event);
  489. switch (event) {
  490. case SND_SOC_DAPM_PRE_PMU:
  491. wcd937x_rx_clk_enable(component);
  492. snd_soc_component_update_bits(component,
  493. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  494. 0x04, 0x04);
  495. snd_soc_component_update_bits(component,
  496. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  497. 0x01, 0x01);
  498. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  499. snd_soc_component_update_bits(component,
  500. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  501. 0x0F, 0x02);
  502. else if (hph_mode == CLS_H_LOHIFI)
  503. snd_soc_component_update_bits(component,
  504. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  505. 0x0F, 0x06);
  506. snd_soc_component_update_bits(component,
  507. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  508. 0x02, 0x02);
  509. usleep_range(5000, 5010);
  510. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  511. WCD_CLSH_EVENT_PRE_DAC,
  512. WCD_CLSH_STATE_EAR,
  513. hph_mode);
  514. break;
  515. case SND_SOC_DAPM_POST_PMD:
  516. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  517. hph_mode == CLS_H_HIFI)
  518. snd_soc_component_update_bits(component,
  519. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  520. 0x0F, 0x01);
  521. break;
  522. };
  523. return 0;
  524. }
  525. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  526. struct snd_kcontrol *kcontrol,
  527. int event)
  528. {
  529. struct snd_soc_component *component =
  530. snd_soc_dapm_to_component(w->dapm);
  531. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  532. int hph_mode = wcd937x->hph_mode;
  533. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  534. w->name, event);
  535. switch (event) {
  536. case SND_SOC_DAPM_PRE_PMU:
  537. wcd937x_rx_clk_enable(component);
  538. snd_soc_component_update_bits(component,
  539. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  540. 0x04, 0x04);
  541. snd_soc_component_update_bits(component,
  542. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  543. 0x04, 0x04);
  544. snd_soc_component_update_bits(component,
  545. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  546. 0x01, 0x01);
  547. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  548. WCD_CLSH_EVENT_PRE_DAC,
  549. WCD_CLSH_STATE_AUX,
  550. hph_mode);
  551. break;
  552. case SND_SOC_DAPM_POST_PMD:
  553. wcd937x_rx_clk_disable(component);
  554. snd_soc_component_update_bits(component,
  555. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  556. 0x04, 0x00);
  557. break;
  558. };
  559. return 0;
  560. }
  561. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  562. struct snd_kcontrol *kcontrol,
  563. int event)
  564. {
  565. struct snd_soc_component *component =
  566. snd_soc_dapm_to_component(w->dapm);
  567. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  568. int ret = 0;
  569. int hph_mode = wcd937x->hph_mode;
  570. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  571. w->name, event);
  572. switch (event) {
  573. case SND_SOC_DAPM_PRE_PMU:
  574. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  575. wcd937x->rx_swr_dev->dev_num,
  576. true);
  577. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  578. WCD_CLSH_EVENT_PRE_DAC,
  579. WCD_CLSH_STATE_HPHR,
  580. hph_mode);
  581. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  582. 0x10, 0x10);
  583. usleep_range(100, 110);
  584. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  585. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  586. wcd937x->rx_swr_dev->dev_num,
  587. true);
  588. snd_soc_component_update_bits(component,
  589. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  590. break;
  591. case SND_SOC_DAPM_POST_PMU:
  592. /*
  593. * 7ms sleep is required after PA is enabled as per
  594. * HW requirement. If compander is disabled, then
  595. * 20ms delay is required.
  596. */
  597. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  598. if (!wcd937x->comp2_enable)
  599. usleep_range(20000, 20100);
  600. else
  601. usleep_range(7000, 7100);
  602. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  603. }
  604. snd_soc_component_update_bits(component,
  605. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  606. 0x02, 0x02);
  607. snd_soc_component_update_bits(component,
  608. WCD937X_HPH_R_TEST, 0x01, 0x01);
  609. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  610. snd_soc_component_update_bits(component,
  611. WCD937X_ANA_RX_SUPPLIES,
  612. 0x02, 0x02);
  613. if (wcd937x->update_wcd_event)
  614. wcd937x->update_wcd_event(wcd937x->handle,
  615. WCD_BOLERO_EVT_RX_MUTE,
  616. (WCD_RX2 << 0x10));
  617. break;
  618. case SND_SOC_DAPM_PRE_PMD:
  619. snd_soc_component_update_bits(component,
  620. WCD937X_HPH_R_TEST, 0x01, 0x00);
  621. if (wcd937x->update_wcd_event)
  622. wcd937x->update_wcd_event(wcd937x->handle,
  623. WCD_BOLERO_EVT_RX_MUTE,
  624. (WCD_RX2 << 0x10 | 0x1));
  625. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  626. WCD_EVENT_PRE_HPHR_PA_OFF,
  627. &wcd937x->mbhc->wcd_mbhc);
  628. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  629. break;
  630. case SND_SOC_DAPM_POST_PMD:
  631. /*
  632. * 7ms sleep is required after PA is disabled as per
  633. * HW requirement. If compander is disabled, then
  634. * 20ms delay is required.
  635. */
  636. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  637. if (!wcd937x->comp2_enable)
  638. usleep_range(20000, 20100);
  639. else
  640. usleep_range(7000, 7100);
  641. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  642. }
  643. snd_soc_component_update_bits(component,
  644. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  645. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  646. WCD_EVENT_POST_HPHR_PA_OFF,
  647. &wcd937x->mbhc->wcd_mbhc);
  648. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  649. 0x10, 0x00);
  650. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  651. WCD_CLSH_EVENT_POST_PA,
  652. WCD_CLSH_STATE_HPHR,
  653. hph_mode);
  654. break;
  655. };
  656. return ret;
  657. }
  658. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  659. struct snd_kcontrol *kcontrol,
  660. int event)
  661. {
  662. struct snd_soc_component *component =
  663. snd_soc_dapm_to_component(w->dapm);
  664. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  665. int ret = 0;
  666. int hph_mode = wcd937x->hph_mode;
  667. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  668. w->name, event);
  669. switch (event) {
  670. case SND_SOC_DAPM_PRE_PMU:
  671. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  672. wcd937x->rx_swr_dev->dev_num,
  673. true);
  674. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  675. WCD_CLSH_EVENT_PRE_DAC,
  676. WCD_CLSH_STATE_HPHL,
  677. hph_mode);
  678. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  679. 0x20, 0x20);
  680. usleep_range(100, 110);
  681. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  682. snd_soc_component_update_bits(component,
  683. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  684. break;
  685. case SND_SOC_DAPM_POST_PMU:
  686. /*
  687. * 7ms sleep is required after PA is enabled as per
  688. * HW requirement. If compander is disabled, then
  689. * 20ms delay is required.
  690. */
  691. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  692. if (!wcd937x->comp1_enable)
  693. usleep_range(20000, 20100);
  694. else
  695. usleep_range(7000, 7100);
  696. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  697. }
  698. snd_soc_component_update_bits(component,
  699. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  700. 0x02, 0x02);
  701. snd_soc_component_update_bits(component,
  702. WCD937X_HPH_L_TEST, 0x01, 0x01);
  703. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  704. snd_soc_component_update_bits(component,
  705. WCD937X_ANA_RX_SUPPLIES,
  706. 0x02, 0x02);
  707. if (wcd937x->update_wcd_event)
  708. wcd937x->update_wcd_event(wcd937x->handle,
  709. WCD_BOLERO_EVT_RX_MUTE,
  710. (WCD_RX1 << 0x10));
  711. break;
  712. case SND_SOC_DAPM_PRE_PMD:
  713. snd_soc_component_update_bits(component,
  714. WCD937X_HPH_L_TEST, 0x01, 0x00);
  715. if (wcd937x->update_wcd_event)
  716. wcd937x->update_wcd_event(wcd937x->handle,
  717. WCD_BOLERO_EVT_RX_MUTE,
  718. (WCD_RX1 << 0x10 | 0x1));
  719. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  720. WCD_EVENT_PRE_HPHL_PA_OFF,
  721. &wcd937x->mbhc->wcd_mbhc);
  722. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  723. break;
  724. case SND_SOC_DAPM_POST_PMD:
  725. /*
  726. * 7ms sleep is required after PA is disabled as per
  727. * HW requirement. If compander is disabled, then
  728. * 20ms delay is required.
  729. */
  730. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  731. if (!wcd937x->comp1_enable)
  732. usleep_range(20000, 20100);
  733. else
  734. usleep_range(7000, 7100);
  735. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  736. }
  737. snd_soc_component_update_bits(component,
  738. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  739. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  740. WCD_EVENT_POST_HPHL_PA_OFF,
  741. &wcd937x->mbhc->wcd_mbhc);
  742. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  743. 0x20, 0x00);
  744. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  745. WCD_CLSH_EVENT_POST_PA,
  746. WCD_CLSH_STATE_HPHL,
  747. hph_mode);
  748. break;
  749. };
  750. return ret;
  751. }
  752. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  753. struct snd_kcontrol *kcontrol,
  754. int event)
  755. {
  756. struct snd_soc_component *component =
  757. snd_soc_dapm_to_component(w->dapm);
  758. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  759. int hph_mode = wcd937x->hph_mode;
  760. int ret = 0;
  761. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  762. w->name, event);
  763. switch (event) {
  764. case SND_SOC_DAPM_PRE_PMU:
  765. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  766. wcd937x->rx_swr_dev->dev_num,
  767. true);
  768. snd_soc_component_update_bits(component,
  769. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  770. break;
  771. case SND_SOC_DAPM_POST_PMU:
  772. usleep_range(1000, 1010);
  773. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  774. snd_soc_component_update_bits(component,
  775. WCD937X_ANA_RX_SUPPLIES,
  776. 0x02, 0x02);
  777. if (wcd937x->update_wcd_event)
  778. wcd937x->update_wcd_event(wcd937x->handle,
  779. WCD_BOLERO_EVT_RX_MUTE,
  780. (WCD_RX3 << 0x10));
  781. break;
  782. case SND_SOC_DAPM_PRE_PMD:
  783. if (wcd937x->update_wcd_event)
  784. wcd937x->update_wcd_event(wcd937x->handle,
  785. WCD_BOLERO_EVT_RX_MUTE,
  786. (WCD_RX3 << 0x10 | 0x1));
  787. break;
  788. case SND_SOC_DAPM_POST_PMD:
  789. /* Add delay as per hw requirement */
  790. usleep_range(2000, 2010);
  791. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  792. WCD_CLSH_EVENT_POST_PA,
  793. WCD_CLSH_STATE_AUX,
  794. hph_mode);
  795. snd_soc_component_update_bits(component,
  796. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  797. break;
  798. };
  799. return ret;
  800. }
  801. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  802. struct snd_kcontrol *kcontrol,
  803. int event)
  804. {
  805. struct snd_soc_component *component =
  806. snd_soc_dapm_to_component(w->dapm);
  807. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  808. int hph_mode = wcd937x->hph_mode;
  809. int ret = 0;
  810. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  811. w->name, event);
  812. switch (event) {
  813. case SND_SOC_DAPM_PRE_PMU:
  814. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  815. wcd937x->rx_swr_dev->dev_num,
  816. true);
  817. /*
  818. * Enable watchdog interrupt for HPHL or AUX
  819. * depending on mux value
  820. */
  821. wcd937x->ear_rx_path =
  822. snd_soc_component_read32(
  823. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  824. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  825. snd_soc_component_update_bits(component,
  826. WCD937X_DIGITAL_PDM_WD_CTL2,
  827. 0x05, 0x05);
  828. else
  829. snd_soc_component_update_bits(component,
  830. WCD937X_DIGITAL_PDM_WD_CTL0,
  831. 0x17, 0x13);
  832. if (!wcd937x->comp1_enable)
  833. snd_soc_component_update_bits(component,
  834. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  835. break;
  836. case SND_SOC_DAPM_POST_PMU:
  837. usleep_range(6000, 6010);
  838. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  839. snd_soc_component_update_bits(component,
  840. WCD937X_ANA_RX_SUPPLIES,
  841. 0x02, 0x02);
  842. if (wcd937x->update_wcd_event)
  843. wcd937x->update_wcd_event(wcd937x->handle,
  844. WCD_BOLERO_EVT_RX_MUTE,
  845. (WCD_RX1 << 0x10));
  846. break;
  847. case SND_SOC_DAPM_PRE_PMD:
  848. if (wcd937x->update_wcd_event)
  849. wcd937x->update_wcd_event(wcd937x->handle,
  850. WCD_BOLERO_EVT_RX_MUTE,
  851. (WCD_RX1 << 0x10 | 0x1));
  852. break;
  853. case SND_SOC_DAPM_POST_PMD:
  854. if (!wcd937x->comp1_enable)
  855. snd_soc_component_update_bits(component,
  856. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  857. usleep_range(7000, 7010);
  858. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  859. WCD_CLSH_EVENT_POST_PA,
  860. WCD_CLSH_STATE_EAR,
  861. hph_mode);
  862. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  863. snd_soc_component_update_bits(component,
  864. WCD937X_DIGITAL_PDM_WD_CTL2,
  865. 0x05, 0x00);
  866. else
  867. snd_soc_component_update_bits(component,
  868. WCD937X_DIGITAL_PDM_WD_CTL0,
  869. 0x17, 0x00);
  870. break;
  871. };
  872. return ret;
  873. }
  874. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  875. struct snd_kcontrol *kcontrol,
  876. int event)
  877. {
  878. struct snd_soc_component *component =
  879. snd_soc_dapm_to_component(w->dapm);
  880. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  881. int mode = wcd937x->hph_mode;
  882. int ret = 0;
  883. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  884. w->name, event);
  885. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  886. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  887. wcd937x_rx_connect_port(component, CLSH,
  888. SND_SOC_DAPM_EVENT_ON(event));
  889. }
  890. if (SND_SOC_DAPM_EVENT_OFF(event))
  891. ret = swr_slvdev_datapath_control(
  892. wcd937x->rx_swr_dev,
  893. wcd937x->rx_swr_dev->dev_num,
  894. false);
  895. return ret;
  896. }
  897. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  898. struct snd_kcontrol *kcontrol,
  899. int event)
  900. {
  901. struct snd_soc_component *component =
  902. snd_soc_dapm_to_component(w->dapm);
  903. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  904. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  905. w->name, event);
  906. switch (event) {
  907. case SND_SOC_DAPM_PRE_PMU:
  908. wcd937x_rx_connect_port(component, HPH_L, true);
  909. if (wcd937x->comp1_enable)
  910. wcd937x_rx_connect_port(component, COMP_L, true);
  911. break;
  912. case SND_SOC_DAPM_POST_PMD:
  913. wcd937x_rx_connect_port(component, HPH_L, false);
  914. if (wcd937x->comp1_enable)
  915. wcd937x_rx_connect_port(component, COMP_L, false);
  916. wcd937x_rx_clk_disable(component);
  917. snd_soc_component_update_bits(component,
  918. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  919. 0x01, 0x00);
  920. break;
  921. };
  922. return 0;
  923. }
  924. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  925. struct snd_kcontrol *kcontrol, int event)
  926. {
  927. struct snd_soc_component *component =
  928. snd_soc_dapm_to_component(w->dapm);
  929. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  930. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  931. w->name, event);
  932. switch (event) {
  933. case SND_SOC_DAPM_PRE_PMU:
  934. wcd937x_rx_connect_port(component, HPH_R, true);
  935. if (wcd937x->comp2_enable)
  936. wcd937x_rx_connect_port(component, COMP_R, true);
  937. break;
  938. case SND_SOC_DAPM_POST_PMD:
  939. wcd937x_rx_connect_port(component, HPH_R, false);
  940. if (wcd937x->comp2_enable)
  941. wcd937x_rx_connect_port(component, COMP_R, false);
  942. wcd937x_rx_clk_disable(component);
  943. snd_soc_component_update_bits(component,
  944. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  945. 0x02, 0x00);
  946. break;
  947. };
  948. return 0;
  949. }
  950. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  951. struct snd_kcontrol *kcontrol,
  952. int event)
  953. {
  954. struct snd_soc_component *component =
  955. snd_soc_dapm_to_component(w->dapm);
  956. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  957. w->name, event);
  958. switch (event) {
  959. case SND_SOC_DAPM_PRE_PMU:
  960. wcd937x_rx_connect_port(component, LO, true);
  961. break;
  962. case SND_SOC_DAPM_POST_PMD:
  963. wcd937x_rx_connect_port(component, LO, false);
  964. usleep_range(6000, 6010);
  965. wcd937x_rx_clk_disable(component);
  966. snd_soc_component_update_bits(component,
  967. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  968. break;
  969. }
  970. return 0;
  971. }
  972. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  973. struct snd_kcontrol *kcontrol,
  974. int event)
  975. {
  976. struct snd_soc_component *component =
  977. snd_soc_dapm_to_component(w->dapm);
  978. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  979. u16 dmic_clk_reg;
  980. s32 *dmic_clk_cnt;
  981. unsigned int dmic;
  982. char *wname;
  983. int ret = 0;
  984. wname = strpbrk(w->name, "012345");
  985. if (!wname) {
  986. dev_err(component->dev, "%s: widget not found\n", __func__);
  987. return -EINVAL;
  988. }
  989. ret = kstrtouint(wname, 10, &dmic);
  990. if (ret < 0) {
  991. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  992. __func__);
  993. return -EINVAL;
  994. }
  995. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  996. w->name, event);
  997. switch (dmic) {
  998. case 0:
  999. case 1:
  1000. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1001. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1002. break;
  1003. case 2:
  1004. case 3:
  1005. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1006. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1007. break;
  1008. case 4:
  1009. case 5:
  1010. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1011. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1012. break;
  1013. default:
  1014. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1015. __func__);
  1016. return -EINVAL;
  1017. };
  1018. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1019. __func__, event, dmic, *dmic_clk_cnt);
  1020. switch (event) {
  1021. case SND_SOC_DAPM_PRE_PMU:
  1022. snd_soc_component_update_bits(component,
  1023. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1024. snd_soc_component_update_bits(component,
  1025. dmic_clk_reg, 0x07, 0x02);
  1026. snd_soc_component_update_bits(component,
  1027. dmic_clk_reg, 0x08, 0x08);
  1028. snd_soc_component_update_bits(component,
  1029. dmic_clk_reg, 0x70, 0x20);
  1030. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1031. break;
  1032. case SND_SOC_DAPM_POST_PMD:
  1033. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1034. break;
  1035. };
  1036. return 0;
  1037. }
  1038. /*
  1039. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1040. * @micb_mv: micbias in mv
  1041. *
  1042. * return register value converted
  1043. */
  1044. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1045. {
  1046. /* min micbias voltage is 1V and maximum is 2.85V */
  1047. if (micb_mv < 1000 || micb_mv > 2850) {
  1048. pr_err("%s: unsupported micbias voltage\n", __func__);
  1049. return -EINVAL;
  1050. }
  1051. return (micb_mv - 1000) / 50;
  1052. }
  1053. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1054. /*
  1055. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1056. * @component: handle to snd_soc_component *
  1057. * @req_volt: micbias voltage to be set
  1058. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1059. *
  1060. * return 0 if adjustment is success or error code in case of failure
  1061. */
  1062. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1063. int req_volt, int micb_num)
  1064. {
  1065. struct wcd937x_priv *wcd937x =
  1066. snd_soc_component_get_drvdata(component);
  1067. int cur_vout_ctl, req_vout_ctl;
  1068. int micb_reg, micb_val, micb_en;
  1069. int ret = 0;
  1070. switch (micb_num) {
  1071. case MIC_BIAS_1:
  1072. micb_reg = WCD937X_ANA_MICB1;
  1073. break;
  1074. case MIC_BIAS_2:
  1075. micb_reg = WCD937X_ANA_MICB2;
  1076. break;
  1077. case MIC_BIAS_3:
  1078. micb_reg = WCD937X_ANA_MICB3;
  1079. break;
  1080. default:
  1081. return -EINVAL;
  1082. }
  1083. mutex_lock(&wcd937x->micb_lock);
  1084. /*
  1085. * If requested micbias voltage is same as current micbias
  1086. * voltage, then just return. Otherwise, adjust voltage as
  1087. * per requested value. If micbias is already enabled, then
  1088. * to avoid slow micbias ramp-up or down enable pull-up
  1089. * momentarily, change the micbias value and then re-enable
  1090. * micbias.
  1091. */
  1092. micb_val = snd_soc_component_read32(component, micb_reg);
  1093. micb_en = (micb_val & 0xC0) >> 6;
  1094. cur_vout_ctl = micb_val & 0x3F;
  1095. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1096. if (req_vout_ctl < 0) {
  1097. ret = -EINVAL;
  1098. goto exit;
  1099. }
  1100. if (cur_vout_ctl == req_vout_ctl) {
  1101. ret = 0;
  1102. goto exit;
  1103. }
  1104. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1105. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1106. req_volt, micb_en);
  1107. if (micb_en == 0x1)
  1108. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1109. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1110. if (micb_en == 0x1) {
  1111. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1112. /*
  1113. * Add 2ms delay as per HW requirement after enabling
  1114. * micbias
  1115. */
  1116. usleep_range(2000, 2100);
  1117. }
  1118. exit:
  1119. mutex_unlock(&wcd937x->micb_lock);
  1120. return ret;
  1121. }
  1122. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1123. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1124. struct snd_kcontrol *kcontrol,
  1125. int event)
  1126. {
  1127. struct snd_soc_component *component =
  1128. snd_soc_dapm_to_component(w->dapm);
  1129. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1130. int ret = 0;
  1131. switch (event) {
  1132. case SND_SOC_DAPM_PRE_PMU:
  1133. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1134. wcd937x->tx_swr_dev->dev_num,
  1135. true);
  1136. break;
  1137. case SND_SOC_DAPM_POST_PMD:
  1138. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1139. wcd937x->tx_swr_dev->dev_num,
  1140. false);
  1141. break;
  1142. };
  1143. return ret;
  1144. }
  1145. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1146. struct snd_kcontrol *kcontrol,
  1147. int event){
  1148. struct snd_soc_component *component =
  1149. snd_soc_dapm_to_component(w->dapm);
  1150. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1151. w->name, event);
  1152. switch (event) {
  1153. case SND_SOC_DAPM_PRE_PMU:
  1154. snd_soc_component_update_bits(component,
  1155. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1156. snd_soc_component_update_bits(component,
  1157. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1158. snd_soc_component_update_bits(component,
  1159. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1160. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1161. break;
  1162. case SND_SOC_DAPM_POST_PMD:
  1163. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1164. snd_soc_component_update_bits(component,
  1165. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1166. break;
  1167. };
  1168. return 0;
  1169. }
  1170. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1171. struct snd_kcontrol *kcontrol, int event)
  1172. {
  1173. struct snd_soc_component *component =
  1174. snd_soc_dapm_to_component(w->dapm);
  1175. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1176. w->name, event);
  1177. switch (event) {
  1178. case SND_SOC_DAPM_PRE_PMU:
  1179. snd_soc_component_update_bits(component,
  1180. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1181. snd_soc_component_update_bits(component,
  1182. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1183. snd_soc_component_update_bits(component,
  1184. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1185. snd_soc_component_update_bits(component,
  1186. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1187. snd_soc_component_update_bits(component,
  1188. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1189. snd_soc_component_update_bits(component,
  1190. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1191. snd_soc_component_update_bits(component,
  1192. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1193. break;
  1194. case SND_SOC_DAPM_POST_PMD:
  1195. snd_soc_component_update_bits(component,
  1196. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1197. snd_soc_component_update_bits(component,
  1198. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1199. snd_soc_component_update_bits(component,
  1200. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1201. snd_soc_component_update_bits(component,
  1202. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1203. snd_soc_component_update_bits(component,
  1204. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1205. break;
  1206. };
  1207. return 0;
  1208. }
  1209. int wcd937x_micbias_control(struct snd_soc_component *component,
  1210. int micb_num, int req, bool is_dapm)
  1211. {
  1212. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1213. int micb_index = micb_num - 1;
  1214. u16 micb_reg;
  1215. int pre_off_event = 0, post_off_event = 0;
  1216. int post_on_event = 0, post_dapm_off = 0;
  1217. int post_dapm_on = 0;
  1218. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1219. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1220. __func__, micb_index);
  1221. return -EINVAL;
  1222. }
  1223. switch (micb_num) {
  1224. case MIC_BIAS_1:
  1225. micb_reg = WCD937X_ANA_MICB1;
  1226. break;
  1227. case MIC_BIAS_2:
  1228. micb_reg = WCD937X_ANA_MICB2;
  1229. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1230. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1231. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1232. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1233. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1234. break;
  1235. case MIC_BIAS_3:
  1236. micb_reg = WCD937X_ANA_MICB3;
  1237. break;
  1238. default:
  1239. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1240. __func__, micb_num);
  1241. return -EINVAL;
  1242. };
  1243. mutex_lock(&wcd937x->micb_lock);
  1244. switch (req) {
  1245. case MICB_PULLUP_ENABLE:
  1246. wcd937x->pullup_ref[micb_index]++;
  1247. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1248. (wcd937x->micb_ref[micb_index] == 0))
  1249. snd_soc_component_update_bits(component, micb_reg,
  1250. 0xC0, 0x80);
  1251. break;
  1252. case MICB_PULLUP_DISABLE:
  1253. if (wcd937x->pullup_ref[micb_index] > 0)
  1254. wcd937x->pullup_ref[micb_index]--;
  1255. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1256. (wcd937x->micb_ref[micb_index] == 0))
  1257. snd_soc_component_update_bits(component, micb_reg,
  1258. 0xC0, 0x00);
  1259. break;
  1260. case MICB_ENABLE:
  1261. wcd937x->micb_ref[micb_index]++;
  1262. if (wcd937x->micb_ref[micb_index] == 1) {
  1263. snd_soc_component_update_bits(component,
  1264. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1265. snd_soc_component_update_bits(component,
  1266. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1267. snd_soc_component_update_bits(component,
  1268. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1269. snd_soc_component_update_bits(component,
  1270. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1271. snd_soc_component_update_bits(component,
  1272. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1273. snd_soc_component_update_bits(component,
  1274. micb_reg, 0xC0, 0x40);
  1275. if (post_on_event)
  1276. blocking_notifier_call_chain(
  1277. &wcd937x->mbhc->notifier, post_on_event,
  1278. &wcd937x->mbhc->wcd_mbhc);
  1279. }
  1280. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1281. blocking_notifier_call_chain(
  1282. &wcd937x->mbhc->notifier, post_dapm_on,
  1283. &wcd937x->mbhc->wcd_mbhc);
  1284. break;
  1285. case MICB_DISABLE:
  1286. if (wcd937x->micb_ref[micb_index] > 0)
  1287. wcd937x->micb_ref[micb_index]--;
  1288. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1289. (wcd937x->pullup_ref[micb_index] > 0))
  1290. snd_soc_component_update_bits(component, micb_reg,
  1291. 0xC0, 0x80);
  1292. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1293. (wcd937x->pullup_ref[micb_index] == 0)) {
  1294. if (pre_off_event && wcd937x->mbhc)
  1295. blocking_notifier_call_chain(
  1296. &wcd937x->mbhc->notifier, pre_off_event,
  1297. &wcd937x->mbhc->wcd_mbhc);
  1298. snd_soc_component_update_bits(component, micb_reg,
  1299. 0xC0, 0x00);
  1300. if (post_off_event && wcd937x->mbhc)
  1301. blocking_notifier_call_chain(
  1302. &wcd937x->mbhc->notifier,
  1303. post_off_event,
  1304. &wcd937x->mbhc->wcd_mbhc);
  1305. }
  1306. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1307. blocking_notifier_call_chain(
  1308. &wcd937x->mbhc->notifier, post_dapm_off,
  1309. &wcd937x->mbhc->wcd_mbhc);
  1310. break;
  1311. };
  1312. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1313. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1314. wcd937x->pullup_ref[micb_index]);
  1315. mutex_unlock(&wcd937x->micb_lock);
  1316. return 0;
  1317. }
  1318. EXPORT_SYMBOL(wcd937x_micbias_control);
  1319. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1320. {
  1321. int ret = 0;
  1322. uint8_t devnum = 0;
  1323. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1324. if (ret) {
  1325. dev_err(&swr_dev->dev,
  1326. "%s get devnum %d for dev addr %lx failed\n",
  1327. __func__, devnum, swr_dev->addr);
  1328. swr_remove_device(swr_dev);
  1329. return ret;
  1330. }
  1331. swr_dev->dev_num = devnum;
  1332. return 0;
  1333. }
  1334. static int wcd937x_event_notify(struct notifier_block *block,
  1335. unsigned long val,
  1336. void *data)
  1337. {
  1338. u16 event = (val & 0xffff);
  1339. u16 amic = (val >> 0x10);
  1340. u16 mask = 0x40, reg = 0x0;
  1341. int ret = 0;
  1342. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1343. struct snd_soc_component *component = wcd937x->component;
  1344. struct wcd_mbhc *mbhc;
  1345. switch (event) {
  1346. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1347. if (amic == 0x1 || amic == 0x2)
  1348. reg = WCD937X_ANA_TX_CH2;
  1349. else if (amic == 0x3)
  1350. reg = WCD937X_ANA_TX_CH3_HPF;
  1351. else
  1352. return 0;
  1353. if (amic == 0x2)
  1354. mask = 0x20;
  1355. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1356. break;
  1357. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1358. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1359. 0xC0, 0x00);
  1360. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1361. 0x80, 0x00);
  1362. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1363. 0x80, 0x00);
  1364. break;
  1365. case BOLERO_WCD_EVT_SSR_DOWN:
  1366. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1367. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1368. wcd937x_reset_low(wcd937x->dev);
  1369. break;
  1370. case BOLERO_WCD_EVT_SSR_UP:
  1371. wcd937x_reset(wcd937x->dev);
  1372. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1373. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1374. regcache_mark_dirty(wcd937x->regmap);
  1375. regcache_sync(wcd937x->regmap);
  1376. /* Initialize MBHC module */
  1377. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1378. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1379. if (ret) {
  1380. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1381. __func__);
  1382. } else {
  1383. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1384. }
  1385. break;
  1386. default:
  1387. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1388. event);
  1389. break;
  1390. }
  1391. return 0;
  1392. }
  1393. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1394. int event)
  1395. {
  1396. struct snd_soc_component *component =
  1397. snd_soc_dapm_to_component(w->dapm);
  1398. int micb_num;
  1399. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1400. __func__, w->name, event);
  1401. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1402. micb_num = MIC_BIAS_1;
  1403. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1404. micb_num = MIC_BIAS_2;
  1405. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1406. micb_num = MIC_BIAS_3;
  1407. else
  1408. return -EINVAL;
  1409. switch (event) {
  1410. case SND_SOC_DAPM_PRE_PMU:
  1411. wcd937x_micbias_control(component, micb_num,
  1412. MICB_ENABLE, true);
  1413. break;
  1414. case SND_SOC_DAPM_POST_PMU:
  1415. usleep_range(1000, 1100);
  1416. break;
  1417. case SND_SOC_DAPM_POST_PMD:
  1418. wcd937x_micbias_control(component, micb_num,
  1419. MICB_DISABLE, true);
  1420. break;
  1421. };
  1422. return 0;
  1423. }
  1424. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1425. struct snd_kcontrol *kcontrol,
  1426. int event)
  1427. {
  1428. return __wcd937x_codec_enable_micbias(w, event);
  1429. }
  1430. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1431. struct snd_ctl_elem_value *ucontrol)
  1432. {
  1433. struct snd_soc_component *component =
  1434. snd_soc_kcontrol_component(kcontrol);
  1435. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1436. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1437. return 0;
  1438. }
  1439. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1440. struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct snd_soc_component *component =
  1443. snd_soc_kcontrol_component(kcontrol);
  1444. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1445. u32 mode_val;
  1446. mode_val = ucontrol->value.enumerated.item[0];
  1447. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1448. if (mode_val == 0) {
  1449. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1450. __func__);
  1451. mode_val = 3; /* enum will be updated later */
  1452. }
  1453. wcd937x->hph_mode = mode_val;
  1454. return 0;
  1455. }
  1456. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1457. struct snd_ctl_elem_value *ucontrol)
  1458. {
  1459. u8 ear_pa_gain = 0;
  1460. struct snd_soc_component *component =
  1461. snd_soc_kcontrol_component(kcontrol);
  1462. ear_pa_gain = snd_soc_component_read32(component,
  1463. WCD937X_ANA_EAR_COMPANDER_CTL);
  1464. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1465. ucontrol->value.integer.value[0] = ear_pa_gain;
  1466. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1467. ear_pa_gain);
  1468. return 0;
  1469. }
  1470. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1471. struct snd_ctl_elem_value *ucontrol)
  1472. {
  1473. u8 ear_pa_gain = 0;
  1474. struct snd_soc_component *component =
  1475. snd_soc_kcontrol_component(kcontrol);
  1476. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1477. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1478. __func__, ucontrol->value.integer.value[0]);
  1479. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1480. if (!wcd937x->comp1_enable) {
  1481. snd_soc_component_update_bits(component,
  1482. WCD937X_ANA_EAR_COMPANDER_CTL,
  1483. 0x7C, ear_pa_gain);
  1484. }
  1485. return 0;
  1486. }
  1487. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1488. struct snd_ctl_elem_value *ucontrol)
  1489. {
  1490. struct snd_soc_component *component =
  1491. snd_soc_kcontrol_component(kcontrol);
  1492. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1493. bool hphr;
  1494. struct soc_multi_mixer_control *mc;
  1495. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1496. hphr = mc->shift;
  1497. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1498. wcd937x->comp1_enable;
  1499. return 0;
  1500. }
  1501. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1502. struct snd_ctl_elem_value *ucontrol)
  1503. {
  1504. struct snd_soc_component *component =
  1505. snd_soc_kcontrol_component(kcontrol);
  1506. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1507. int value = ucontrol->value.integer.value[0];
  1508. bool hphr;
  1509. struct soc_multi_mixer_control *mc;
  1510. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1511. hphr = mc->shift;
  1512. if (hphr)
  1513. wcd937x->comp2_enable = value;
  1514. else
  1515. wcd937x->comp1_enable = value;
  1516. return 0;
  1517. }
  1518. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1519. struct snd_kcontrol *kcontrol,
  1520. int event)
  1521. {
  1522. struct snd_soc_component *component =
  1523. snd_soc_dapm_to_component(w->dapm);
  1524. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1525. struct wcd937x_pdata *pdata = NULL;
  1526. int ret = 0;
  1527. pdata = dev_get_platdata(wcd937x->dev);
  1528. if (!pdata) {
  1529. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1530. return -EINVAL;
  1531. }
  1532. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1533. w->name, event);
  1534. switch (event) {
  1535. case SND_SOC_DAPM_PRE_PMU:
  1536. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1537. dev_dbg(component->dev,
  1538. "%s: buck already in enabled state\n",
  1539. __func__);
  1540. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1541. return 0;
  1542. }
  1543. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1544. wcd937x->supplies,
  1545. pdata->regulator,
  1546. pdata->num_supplies,
  1547. "cdc-vdd-buck");
  1548. if (ret == -EINVAL) {
  1549. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1550. __func__);
  1551. return ret;
  1552. }
  1553. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1554. /*
  1555. * 200us sleep is required after LDO15 is enabled as per
  1556. * HW requirement
  1557. */
  1558. usleep_range(200, 250);
  1559. break;
  1560. case SND_SOC_DAPM_POST_PMD:
  1561. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1562. break;
  1563. }
  1564. return 0;
  1565. }
  1566. static const char * const rx_hph_mode_mux_text[] = {
  1567. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1568. "CLS_H_ULP", "CLS_AB_HIFI",
  1569. };
  1570. static const char * const wcd937x_ear_pa_gain_text[] = {
  1571. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1572. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1573. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1574. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1575. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1576. };
  1577. static const struct soc_enum rx_hph_mode_mux_enum =
  1578. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1579. rx_hph_mode_mux_text);
  1580. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1581. wcd937x_ear_pa_gain_text);
  1582. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1583. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1584. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1585. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1586. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1587. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1588. wcd937x_get_compander, wcd937x_set_compander),
  1589. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1590. wcd937x_get_compander, wcd937x_set_compander),
  1591. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1592. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1593. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1594. analog_gain),
  1595. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1596. analog_gain),
  1597. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1598. analog_gain),
  1599. };
  1600. static const struct snd_kcontrol_new adc1_switch[] = {
  1601. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1602. };
  1603. static const struct snd_kcontrol_new adc2_switch[] = {
  1604. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1605. };
  1606. static const struct snd_kcontrol_new adc3_switch[] = {
  1607. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1608. };
  1609. static const struct snd_kcontrol_new dmic1_switch[] = {
  1610. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1611. };
  1612. static const struct snd_kcontrol_new dmic2_switch[] = {
  1613. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1614. };
  1615. static const struct snd_kcontrol_new dmic3_switch[] = {
  1616. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1617. };
  1618. static const struct snd_kcontrol_new dmic4_switch[] = {
  1619. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1620. };
  1621. static const struct snd_kcontrol_new dmic5_switch[] = {
  1622. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1623. };
  1624. static const struct snd_kcontrol_new dmic6_switch[] = {
  1625. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1626. };
  1627. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1628. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1629. };
  1630. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1631. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1632. };
  1633. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1634. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1635. };
  1636. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1637. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1638. };
  1639. static const char * const adc2_mux_text[] = {
  1640. "INP2", "INP3"
  1641. };
  1642. static const char * const rdac3_mux_text[] = {
  1643. "RX1", "RX3"
  1644. };
  1645. static const struct soc_enum adc2_enum =
  1646. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1647. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1648. static const struct soc_enum rdac3_enum =
  1649. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1650. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1651. static const struct snd_kcontrol_new tx_adc2_mux =
  1652. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1653. static const struct snd_kcontrol_new rx_rdac3_mux =
  1654. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1655. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1656. /*input widgets*/
  1657. SND_SOC_DAPM_INPUT("AMIC1"),
  1658. SND_SOC_DAPM_INPUT("AMIC2"),
  1659. SND_SOC_DAPM_INPUT("AMIC3"),
  1660. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1661. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1662. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1663. /*tx widgets*/
  1664. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1665. wcd937x_codec_enable_adc,
  1666. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1667. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1668. wcd937x_codec_enable_adc,
  1669. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1670. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1671. NULL, 0, wcd937x_enable_req,
  1672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1673. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1674. NULL, 0, wcd937x_enable_req,
  1675. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1676. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1677. &tx_adc2_mux),
  1678. /*tx mixers*/
  1679. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1680. adc1_switch, ARRAY_SIZE(adc1_switch),
  1681. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1682. SND_SOC_DAPM_POST_PMD),
  1683. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1684. adc2_switch, ARRAY_SIZE(adc2_switch),
  1685. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1686. SND_SOC_DAPM_POST_PMD),
  1687. /* micbias widgets*/
  1688. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1689. wcd937x_codec_enable_micbias,
  1690. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1691. SND_SOC_DAPM_POST_PMD),
  1692. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1693. wcd937x_codec_enable_micbias,
  1694. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1695. SND_SOC_DAPM_POST_PMD),
  1696. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1697. wcd937x_codec_enable_micbias,
  1698. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1699. SND_SOC_DAPM_POST_PMD),
  1700. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1701. wcd937x_codec_enable_vdd_buck,
  1702. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1703. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1704. wcd937x_enable_clsh,
  1705. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1706. /*rx widgets*/
  1707. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1708. wcd937x_codec_enable_ear_pa,
  1709. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1710. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1711. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1712. wcd937x_codec_enable_aux_pa,
  1713. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1714. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1715. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1716. wcd937x_codec_enable_hphl_pa,
  1717. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1718. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1719. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1720. wcd937x_codec_enable_hphr_pa,
  1721. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1722. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1723. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1724. wcd937x_codec_hphl_dac_event,
  1725. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1726. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1727. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1728. wcd937x_codec_hphr_dac_event,
  1729. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1730. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1731. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1732. wcd937x_codec_ear_dac_event,
  1733. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1734. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1735. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1736. wcd937x_codec_aux_dac_event,
  1737. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1738. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1739. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1740. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1741. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1742. SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1744. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1745. SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1747. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1748. SND_SOC_DAPM_POST_PMD),
  1749. /* rx mixer widgets*/
  1750. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1751. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1752. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1753. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1754. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1755. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1756. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1757. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1758. /*output widgets tx*/
  1759. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1760. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1761. /*output widgets rx*/
  1762. SND_SOC_DAPM_OUTPUT("EAR"),
  1763. SND_SOC_DAPM_OUTPUT("AUX"),
  1764. SND_SOC_DAPM_OUTPUT("HPHL"),
  1765. SND_SOC_DAPM_OUTPUT("HPHR"),
  1766. };
  1767. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1768. /*input widgets*/
  1769. SND_SOC_DAPM_INPUT("AMIC4"),
  1770. /*tx widgets*/
  1771. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1772. wcd937x_codec_enable_adc,
  1773. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1774. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1775. NULL, 0, wcd937x_enable_req,
  1776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1777. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1778. wcd937x_codec_enable_dmic,
  1779. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1780. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1781. wcd937x_codec_enable_dmic,
  1782. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1783. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1784. wcd937x_codec_enable_dmic,
  1785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1786. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1787. wcd937x_codec_enable_dmic,
  1788. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1789. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1790. wcd937x_codec_enable_dmic,
  1791. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1792. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1793. wcd937x_codec_enable_dmic,
  1794. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1795. /*tx mixer widgets*/
  1796. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1797. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1798. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1799. SND_SOC_DAPM_POST_PMD),
  1800. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1801. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1802. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1803. SND_SOC_DAPM_POST_PMD),
  1804. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1805. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1806. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1807. SND_SOC_DAPM_POST_PMD),
  1808. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1809. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1810. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1811. SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1813. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1814. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1815. SND_SOC_DAPM_POST_PMD),
  1816. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1817. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1818. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1819. SND_SOC_DAPM_POST_PMD),
  1820. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1821. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1822. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1823. /*output widgets*/
  1824. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1825. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1826. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1827. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1828. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1829. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1830. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1831. };
  1832. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1833. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1834. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1835. {"ADC1 REQ", NULL, "ADC1"},
  1836. {"ADC1", NULL, "AMIC1"},
  1837. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1838. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1839. {"ADC2 REQ", NULL, "ADC2"},
  1840. {"ADC2", NULL, "ADC2 MUX"},
  1841. {"ADC2 MUX", "INP3", "AMIC3"},
  1842. {"ADC2 MUX", "INP2", "AMIC2"},
  1843. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1844. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1845. {"RX1", NULL, "IN1_HPHL"},
  1846. {"RDAC1", NULL, "RX1"},
  1847. {"HPHL_RDAC", "Switch", "RDAC1"},
  1848. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1849. {"HPHL", NULL, "HPHL PGA"},
  1850. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1851. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1852. {"RX2", NULL, "IN2_HPHR"},
  1853. {"RDAC2", NULL, "RX2"},
  1854. {"HPHR_RDAC", "Switch", "RDAC2"},
  1855. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1856. {"HPHR", NULL, "HPHR PGA"},
  1857. {"IN3_AUX", NULL, "VDD_BUCK"},
  1858. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1859. {"RX3", NULL, "IN3_AUX"},
  1860. {"RDAC4", NULL, "RX3"},
  1861. {"AUX_RDAC", "Switch", "RDAC4"},
  1862. {"AUX PGA", NULL, "AUX_RDAC"},
  1863. {"AUX", NULL, "AUX PGA"},
  1864. {"RDAC3_MUX", "RX3", "RX3"},
  1865. {"RDAC3_MUX", "RX1", "RX1"},
  1866. {"RDAC3", NULL, "RDAC3_MUX"},
  1867. {"EAR_RDAC", "Switch", "RDAC3"},
  1868. {"EAR PGA", NULL, "EAR_RDAC"},
  1869. {"EAR", NULL, "EAR PGA"},
  1870. };
  1871. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1872. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1873. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1874. {"ADC3 REQ", NULL, "ADC3"},
  1875. {"ADC3", NULL, "AMIC4"},
  1876. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1877. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1878. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1879. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1880. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1881. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1882. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1883. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1884. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1885. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1886. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1887. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1888. };
  1889. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1890. void *file_private_data,
  1891. struct file *file,
  1892. char __user *buf, size_t count,
  1893. loff_t pos)
  1894. {
  1895. struct wcd937x_priv *priv;
  1896. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1897. int len = 0;
  1898. priv = (struct wcd937x_priv *) entry->private_data;
  1899. if (!priv) {
  1900. pr_err("%s: wcd937x priv is null\n", __func__);
  1901. return -EINVAL;
  1902. }
  1903. switch (priv->version) {
  1904. case WCD937X_VERSION_1_0:
  1905. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1906. break;
  1907. default:
  1908. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1909. }
  1910. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1911. }
  1912. static struct snd_info_entry_ops wcd937x_info_ops = {
  1913. .read = wcd937x_version_read,
  1914. };
  1915. /*
  1916. * wcd937x_info_create_codec_entry - creates wcd937x module
  1917. * @codec_root: The parent directory
  1918. * @component: component instance
  1919. *
  1920. * Creates wcd937x module and version entry under the given
  1921. * parent directory.
  1922. *
  1923. * Return: 0 on success or negative error code on failure.
  1924. */
  1925. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1926. struct snd_soc_component *component)
  1927. {
  1928. struct snd_info_entry *version_entry;
  1929. struct wcd937x_priv *priv;
  1930. struct snd_soc_card *card;
  1931. if (!codec_root || !component)
  1932. return -EINVAL;
  1933. priv = snd_soc_component_get_drvdata(component);
  1934. if (priv->entry) {
  1935. dev_dbg(priv->dev,
  1936. "%s:wcd937x module already created\n", __func__);
  1937. return 0;
  1938. }
  1939. card = component->card;
  1940. priv->entry = snd_info_create_subdir(codec_root->module,
  1941. "wcd937x", codec_root);
  1942. if (!priv->entry) {
  1943. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  1944. __func__);
  1945. return -ENOMEM;
  1946. }
  1947. version_entry = snd_info_create_card_entry(card->snd_card,
  1948. "version",
  1949. priv->entry);
  1950. if (!version_entry) {
  1951. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  1952. __func__);
  1953. return -ENOMEM;
  1954. }
  1955. version_entry->private_data = priv;
  1956. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  1957. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  1958. version_entry->c.ops = &wcd937x_info_ops;
  1959. if (snd_info_register(version_entry) < 0) {
  1960. snd_info_free_entry(version_entry);
  1961. return -ENOMEM;
  1962. }
  1963. priv->version_entry = version_entry;
  1964. return 0;
  1965. }
  1966. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  1967. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  1968. struct wcd937x_pdata *pdata)
  1969. {
  1970. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  1971. int rc = 0;
  1972. if (!pdata) {
  1973. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  1974. return -ENODEV;
  1975. }
  1976. /* set micbias voltage */
  1977. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  1978. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  1979. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  1980. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  1981. rc = -EINVAL;
  1982. goto done;
  1983. }
  1984. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  1985. vout_ctl_1);
  1986. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  1987. vout_ctl_2);
  1988. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  1989. vout_ctl_3);
  1990. done:
  1991. return rc;
  1992. }
  1993. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  1994. {
  1995. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1996. struct snd_soc_dapm_context *dapm =
  1997. snd_soc_component_get_dapm(component);
  1998. int variant;
  1999. int ret = -EINVAL;
  2000. dev_info(component->dev, "%s()\n", __func__);
  2001. wcd937x = snd_soc_component_get_drvdata(component);
  2002. if (!wcd937x)
  2003. return -EINVAL;
  2004. wcd937x->component = component;
  2005. variant = (snd_soc_component_read32(
  2006. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2007. wcd937x->variant = variant;
  2008. wcd937x->fw_data = devm_kzalloc(component->dev,
  2009. sizeof(*(wcd937x->fw_data)),
  2010. GFP_KERNEL);
  2011. if (!wcd937x->fw_data) {
  2012. dev_err(component->dev, "Failed to allocate fw_data\n");
  2013. ret = -ENOMEM;
  2014. goto err;
  2015. }
  2016. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2017. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2018. WCD9XXX_CODEC_HWDEP_NODE, component);
  2019. if (ret < 0) {
  2020. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2021. goto err_hwdep;
  2022. }
  2023. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2024. if (ret) {
  2025. pr_err("%s: mbhc initialization failed\n", __func__);
  2026. goto err_hwdep;
  2027. }
  2028. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2029. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2030. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2031. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2032. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2033. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2034. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2035. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2036. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2037. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2038. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2039. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2040. snd_soc_dapm_sync(dapm);
  2041. wcd_cls_h_init(&wcd937x->clsh_info);
  2042. wcd937x_init_reg(component);
  2043. if (wcd937x->variant == WCD9375_VARIANT) {
  2044. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2045. ARRAY_SIZE(wcd9375_dapm_widgets));
  2046. if (ret < 0) {
  2047. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2048. __func__);
  2049. goto err_hwdep;
  2050. }
  2051. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2052. ARRAY_SIZE(wcd9375_audio_map));
  2053. if (ret < 0) {
  2054. dev_err(component->dev, "%s: Failed to add routes\n",
  2055. __func__);
  2056. goto err_hwdep;
  2057. }
  2058. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2059. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2060. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2061. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2062. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2063. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2064. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2065. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2066. snd_soc_dapm_sync(dapm);
  2067. }
  2068. wcd937x->version = WCD937X_VERSION_1_0;
  2069. /* Register event notifier */
  2070. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2071. if (wcd937x->register_notifier) {
  2072. ret = wcd937x->register_notifier(wcd937x->handle,
  2073. &wcd937x->nblock,
  2074. true);
  2075. if (ret) {
  2076. dev_err(component->dev,
  2077. "%s: Failed to register notifier %d\n",
  2078. __func__, ret);
  2079. return ret;
  2080. }
  2081. }
  2082. return ret;
  2083. err_hwdep:
  2084. wcd937x->fw_data = NULL;
  2085. err:
  2086. return ret;
  2087. }
  2088. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2089. {
  2090. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2091. if (!wcd937x)
  2092. return;
  2093. if (wcd937x->register_notifier)
  2094. wcd937x->register_notifier(wcd937x->handle,
  2095. &wcd937x->nblock,
  2096. false);
  2097. return;
  2098. }
  2099. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2100. .name = DRV_NAME,
  2101. .probe = wcd937x_soc_codec_probe,
  2102. .remove = wcd937x_soc_codec_remove,
  2103. .controls = wcd937x_snd_controls,
  2104. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2105. .dapm_widgets = wcd937x_dapm_widgets,
  2106. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2107. .dapm_routes = wcd937x_audio_map,
  2108. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2109. };
  2110. #ifdef CONFIG_PM_SLEEP
  2111. static int wcd937x_suspend(struct device *dev)
  2112. {
  2113. struct wcd937x_priv *wcd937x = NULL;
  2114. int ret = 0;
  2115. struct wcd937x_pdata *pdata = NULL;
  2116. if (!dev)
  2117. return -ENODEV;
  2118. wcd937x = dev_get_drvdata(dev);
  2119. if (!wcd937x)
  2120. return -EINVAL;
  2121. pdata = dev_get_platdata(wcd937x->dev);
  2122. if (!pdata) {
  2123. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2124. return -EINVAL;
  2125. }
  2126. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2127. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2128. wcd937x->supplies,
  2129. pdata->regulator,
  2130. pdata->num_supplies,
  2131. "cdc-vdd-buck");
  2132. if (ret == -EINVAL) {
  2133. dev_err(dev, "%s: vdd buck is not disabled\n",
  2134. __func__);
  2135. return 0;
  2136. }
  2137. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2138. }
  2139. return 0;
  2140. }
  2141. static int wcd937x_resume(struct device *dev)
  2142. {
  2143. return 0;
  2144. }
  2145. #endif
  2146. static int wcd937x_reset(struct device *dev)
  2147. {
  2148. struct wcd937x_priv *wcd937x = NULL;
  2149. int rc = 0;
  2150. int value = 0;
  2151. if (!dev)
  2152. return -ENODEV;
  2153. wcd937x = dev_get_drvdata(dev);
  2154. if (!wcd937x)
  2155. return -EINVAL;
  2156. if (!wcd937x->rst_np) {
  2157. dev_err(dev, "%s: reset gpio device node not specified\n",
  2158. __func__);
  2159. return -EINVAL;
  2160. }
  2161. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2162. if (value > 0)
  2163. return 0;
  2164. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2165. if (rc) {
  2166. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2167. __func__);
  2168. return rc;
  2169. }
  2170. /* 20ms sleep required after pulling the reset gpio to LOW */
  2171. usleep_range(20, 30);
  2172. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2173. if (rc) {
  2174. dev_err(dev, "%s: wcd active state request fail!\n",
  2175. __func__);
  2176. return rc;
  2177. }
  2178. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2179. usleep_range(20, 30);
  2180. return rc;
  2181. }
  2182. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2183. u32 *val)
  2184. {
  2185. int rc = 0;
  2186. rc = of_property_read_u32(dev->of_node, name, val);
  2187. if (rc)
  2188. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2189. __func__, name, dev->of_node->full_name);
  2190. return rc;
  2191. }
  2192. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2193. struct wcd937x_micbias_setting *mb)
  2194. {
  2195. u32 prop_val = 0;
  2196. int rc = 0;
  2197. /* MB1 */
  2198. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2199. NULL)) {
  2200. rc = wcd937x_read_of_property_u32(dev,
  2201. "qcom,cdc-micbias1-mv",
  2202. &prop_val);
  2203. if (!rc)
  2204. mb->micb1_mv = prop_val;
  2205. } else {
  2206. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2207. __func__);
  2208. }
  2209. /* MB2 */
  2210. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2211. NULL)) {
  2212. rc = wcd937x_read_of_property_u32(dev,
  2213. "qcom,cdc-micbias2-mv",
  2214. &prop_val);
  2215. if (!rc)
  2216. mb->micb2_mv = prop_val;
  2217. } else {
  2218. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2219. __func__);
  2220. }
  2221. /* MB3 */
  2222. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2223. NULL)) {
  2224. rc = wcd937x_read_of_property_u32(dev,
  2225. "qcom,cdc-micbias3-mv",
  2226. &prop_val);
  2227. if (!rc)
  2228. mb->micb3_mv = prop_val;
  2229. } else {
  2230. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2231. __func__);
  2232. }
  2233. }
  2234. static int wcd937x_reset_low(struct device *dev)
  2235. {
  2236. struct wcd937x_priv *wcd937x = NULL;
  2237. int rc = 0;
  2238. if (!dev)
  2239. return -ENODEV;
  2240. wcd937x = dev_get_drvdata(dev);
  2241. if (!wcd937x)
  2242. return -EINVAL;
  2243. if (!wcd937x->rst_np) {
  2244. dev_err(dev, "%s: reset gpio device node not specified\n",
  2245. __func__);
  2246. return -EINVAL;
  2247. }
  2248. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2249. if (rc) {
  2250. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2251. __func__);
  2252. return rc;
  2253. }
  2254. /* 20ms sleep required after pulling the reset gpio to LOW */
  2255. usleep_range(20, 30);
  2256. return rc;
  2257. }
  2258. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2259. {
  2260. struct wcd937x_pdata *pdata = NULL;
  2261. pdata = devm_kzalloc(dev, sizeof(struct wcd937x_pdata),
  2262. GFP_KERNEL);
  2263. if (!pdata)
  2264. return NULL;
  2265. pdata->rst_np = of_parse_phandle(dev->of_node,
  2266. "qcom,wcd-rst-gpio-node", 0);
  2267. if (!pdata->rst_np) {
  2268. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2269. __func__, "qcom,wcd-rst-gpio-node",
  2270. dev->of_node->full_name);
  2271. return NULL;
  2272. }
  2273. /* Parse power supplies */
  2274. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2275. &pdata->num_supplies);
  2276. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2277. dev_err(dev, "%s: no power supplies defined for codec\n",
  2278. __func__);
  2279. return NULL;
  2280. }
  2281. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2282. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2283. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2284. return pdata;
  2285. }
  2286. static int wcd937x_wakeup(void *handle, bool enable)
  2287. {
  2288. struct wcd937x_priv *priv;
  2289. if (!handle) {
  2290. pr_err("%s: NULL handle\n", __func__);
  2291. return -EINVAL;
  2292. }
  2293. priv = (struct wcd937x_priv *)handle;
  2294. if (!priv->tx_swr_dev) {
  2295. pr_err("%s: tx swr dev is NULL\n", __func__);
  2296. return -EINVAL;
  2297. }
  2298. if (enable)
  2299. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2300. else
  2301. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2302. }
  2303. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2304. {
  2305. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2306. __func__, irq);
  2307. return IRQ_HANDLED;
  2308. }
  2309. static int wcd937x_bind(struct device *dev)
  2310. {
  2311. int ret = 0, i = 0;
  2312. struct wcd937x_priv *wcd937x = NULL;
  2313. struct wcd937x_pdata *pdata = NULL;
  2314. struct wcd_ctrl_platform_data *plat_data = NULL;
  2315. wcd937x = devm_kzalloc(dev, sizeof(struct wcd937x_priv), GFP_KERNEL);
  2316. if (!wcd937x)
  2317. return -ENOMEM;
  2318. dev_set_drvdata(dev, wcd937x);
  2319. pdata = wcd937x_populate_dt_data(dev);
  2320. if (!pdata) {
  2321. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2322. return -EINVAL;
  2323. }
  2324. wcd937x->dev = dev;
  2325. wcd937x->dev->platform_data = pdata;
  2326. wcd937x->rst_np = pdata->rst_np;
  2327. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2328. pdata->regulator, pdata->num_supplies);
  2329. if (!wcd937x->supplies) {
  2330. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2331. __func__);
  2332. return ret;
  2333. }
  2334. plat_data = dev_get_platdata(dev->parent);
  2335. if (!plat_data) {
  2336. dev_err(dev, "%s: platform data from parent is NULL\n",
  2337. __func__);
  2338. return -EINVAL;
  2339. }
  2340. wcd937x->handle = (void *)plat_data->handle;
  2341. if (!wcd937x->handle) {
  2342. dev_err(dev, "%s: handle is NULL\n", __func__);
  2343. return -EINVAL;
  2344. }
  2345. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2346. if (!wcd937x->update_wcd_event) {
  2347. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2348. __func__);
  2349. return -EINVAL;
  2350. }
  2351. wcd937x->register_notifier = plat_data->register_notifier;
  2352. if (!wcd937x->register_notifier) {
  2353. dev_err(dev, "%s: register_notifier api is null!\n",
  2354. __func__);
  2355. return -EINVAL;
  2356. }
  2357. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2358. pdata->regulator,
  2359. pdata->num_supplies);
  2360. if (ret) {
  2361. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2362. __func__);
  2363. return ret;
  2364. }
  2365. wcd937x_reset(dev);
  2366. /*
  2367. * Add 5msec delay to provide sufficient time for
  2368. * soundwire auto enumeration of slave devices as
  2369. * as per HW requirement.
  2370. */
  2371. usleep_range(5000, 5010);
  2372. wcd937x->wakeup = wcd937x_wakeup;
  2373. ret = component_bind_all(dev, wcd937x);
  2374. if (ret) {
  2375. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2376. __func__, ret);
  2377. return ret;
  2378. }
  2379. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2380. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2381. if (ret) {
  2382. dev_err(dev, "Failed to read port mapping\n");
  2383. goto err;
  2384. }
  2385. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2386. if (!wcd937x->rx_swr_dev) {
  2387. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2388. __func__);
  2389. ret = -ENODEV;
  2390. goto err;
  2391. }
  2392. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2393. if (!wcd937x->tx_swr_dev) {
  2394. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2395. __func__);
  2396. ret = -ENODEV;
  2397. goto err;
  2398. }
  2399. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2400. &wcd937x_regmap_config);
  2401. if (!wcd937x->regmap) {
  2402. dev_err(dev, "%s: Regmap init failed\n",
  2403. __func__);
  2404. goto err;
  2405. }
  2406. /* Set all interupts as edge triggered */
  2407. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2408. regmap_write(wcd937x->regmap,
  2409. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2410. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2411. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2412. wcd937x->irq_info.codec_name = "WCD937X";
  2413. wcd937x->irq_info.regmap = wcd937x->regmap;
  2414. wcd937x->irq_info.dev = dev;
  2415. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2416. if (ret) {
  2417. dev_err(dev, "%s: IRQ init failed: %d\n",
  2418. __func__, ret);
  2419. goto err;
  2420. }
  2421. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2422. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2423. if (ret < 0) {
  2424. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2425. goto err_irq;
  2426. }
  2427. mutex_init(&wcd937x->micb_lock);
  2428. /* Request for watchdog interrupt */
  2429. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2430. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2431. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2432. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2433. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2434. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2435. /* Enable watchdog interrupt for HPH and AUX */
  2436. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2437. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2438. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2439. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2440. NULL, 0);
  2441. if (ret) {
  2442. dev_err(dev, "%s: Codec registration failed\n",
  2443. __func__);
  2444. goto err_irq;
  2445. }
  2446. return ret;
  2447. err_irq:
  2448. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2449. err:
  2450. component_unbind_all(dev, wcd937x);
  2451. return ret;
  2452. }
  2453. static void wcd937x_unbind(struct device *dev)
  2454. {
  2455. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2456. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2457. snd_soc_unregister_component(dev);
  2458. component_unbind_all(dev, wcd937x);
  2459. mutex_destroy(&wcd937x->micb_lock);
  2460. }
  2461. static const struct of_device_id wcd937x_dt_match[] = {
  2462. { .compatible = "qcom,wcd937x-codec" },
  2463. {}
  2464. };
  2465. static const struct component_master_ops wcd937x_comp_ops = {
  2466. .bind = wcd937x_bind,
  2467. .unbind = wcd937x_unbind,
  2468. };
  2469. static int wcd937x_compare_of(struct device *dev, void *data)
  2470. {
  2471. return dev->of_node == data;
  2472. }
  2473. static void wcd937x_release_of(struct device *dev, void *data)
  2474. {
  2475. of_node_put(data);
  2476. }
  2477. static int wcd937x_add_slave_components(struct device *dev,
  2478. struct component_match **matchptr)
  2479. {
  2480. struct device_node *np, *rx_node, *tx_node;
  2481. np = dev->of_node;
  2482. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2483. if (!rx_node) {
  2484. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2485. return -ENODEV;
  2486. }
  2487. of_node_get(rx_node);
  2488. component_match_add_release(dev, matchptr,
  2489. wcd937x_release_of,
  2490. wcd937x_compare_of,
  2491. rx_node);
  2492. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2493. if (!tx_node) {
  2494. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2495. return -ENODEV;
  2496. }
  2497. of_node_get(tx_node);
  2498. component_match_add_release(dev, matchptr,
  2499. wcd937x_release_of,
  2500. wcd937x_compare_of,
  2501. tx_node);
  2502. return 0;
  2503. }
  2504. static int wcd937x_probe(struct platform_device *pdev)
  2505. {
  2506. struct component_match *match = NULL;
  2507. int ret;
  2508. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2509. if (ret)
  2510. return ret;
  2511. return component_master_add_with_match(&pdev->dev,
  2512. &wcd937x_comp_ops, match);
  2513. }
  2514. static int wcd937x_remove(struct platform_device *pdev)
  2515. {
  2516. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2517. return 0;
  2518. }
  2519. #ifdef CONFIG_PM_SLEEP
  2520. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2521. SET_SYSTEM_SLEEP_PM_OPS(
  2522. wcd937x_suspend,
  2523. wcd937x_resume
  2524. )
  2525. };
  2526. #endif
  2527. static struct platform_driver wcd937x_codec_driver = {
  2528. .probe = wcd937x_probe,
  2529. .remove = wcd937x_remove,
  2530. .driver = {
  2531. .name = "wcd937x_codec",
  2532. .owner = THIS_MODULE,
  2533. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2534. #ifdef CONFIG_PM_SLEEP
  2535. .pm = &wcd937x_dev_pm_ops,
  2536. #endif
  2537. },
  2538. };
  2539. module_platform_driver(wcd937x_codec_driver);
  2540. MODULE_DESCRIPTION("WCD937X Codec driver");
  2541. MODULE_LICENSE("GPL v2");