dp_rings_main.c 143 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_ipa_obj_mgmt_api.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <qdf_net_types.h>
  23. #include <qdf_lro.h>
  24. #include <qdf_module.h>
  25. #include <hal_hw_headers.h>
  26. #include <hal_api.h>
  27. #include <hif.h>
  28. #include <htt.h>
  29. #include <wdi_event.h>
  30. #include <queue.h>
  31. #include "dp_types.h"
  32. #include "dp_rings.h"
  33. #include "dp_internal.h"
  34. #include "dp_tx.h"
  35. #include "dp_tx_desc.h"
  36. #include "dp_rx.h"
  37. #ifdef DP_RATETABLE_SUPPORT
  38. #include "dp_ratetable.h"
  39. #endif
  40. #include <cdp_txrx_handle.h>
  41. #include <wlan_cfg.h>
  42. #include <wlan_utility.h>
  43. #include "cdp_txrx_cmn_struct.h"
  44. #include "cdp_txrx_stats_struct.h"
  45. #include "cdp_txrx_cmn_reg.h"
  46. #include <qdf_util.h>
  47. #include "dp_peer.h"
  48. #include "htt_stats.h"
  49. #include "dp_htt.h"
  50. #include "htt_ppdu_stats.h"
  51. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  52. #include "cfg_ucfg_api.h"
  53. #include <wlan_module_ids.h>
  54. #ifdef WIFI_MONITOR_SUPPORT
  55. #include <dp_mon.h>
  56. #endif
  57. #ifdef WLAN_FEATURE_STATS_EXT
  58. #define INIT_RX_HW_STATS_LOCK(_soc) \
  59. qdf_spinlock_create(&(_soc)->rx_hw_stats_lock)
  60. #define DEINIT_RX_HW_STATS_LOCK(_soc) \
  61. qdf_spinlock_destroy(&(_soc)->rx_hw_stats_lock)
  62. #else
  63. #define INIT_RX_HW_STATS_LOCK(_soc) /* no op */
  64. #define DEINIT_RX_HW_STATS_LOCK(_soc) /* no op */
  65. #endif
  66. #ifdef QCA_DP_ENABLE_TX_COMP_RING4
  67. #define TXCOMP_RING4_NUM 3
  68. #else
  69. #define TXCOMP_RING4_NUM WBM2SW_TXCOMP_RING4_NUM
  70. #endif
  71. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  72. uint8_t index);
  73. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index);
  74. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index);
  75. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  76. uint8_t index);
  77. /* default_dscp_tid_map - Default DSCP-TID mapping
  78. *
  79. * DSCP TID
  80. * 000000 0
  81. * 001000 1
  82. * 010000 2
  83. * 011000 3
  84. * 100000 4
  85. * 101000 5
  86. * 110000 6
  87. * 111000 7
  88. */
  89. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 1, 1, 1, 1, 1, 1, 1, 1,
  92. 2, 2, 2, 2, 2, 2, 2, 2,
  93. 3, 3, 3, 3, 3, 3, 3, 3,
  94. 4, 4, 4, 4, 4, 4, 4, 4,
  95. 5, 5, 5, 5, 5, 5, 5, 5,
  96. 6, 6, 6, 6, 6, 6, 6, 6,
  97. 7, 7, 7, 7, 7, 7, 7, 7,
  98. };
  99. /* default_pcp_tid_map - Default PCP-TID mapping
  100. *
  101. * PCP TID
  102. * 000 0
  103. * 001 1
  104. * 010 2
  105. * 011 3
  106. * 100 4
  107. * 101 5
  108. * 110 6
  109. * 111 7
  110. */
  111. static uint8_t default_pcp_tid_map[PCP_TID_MAP_MAX] = {
  112. 0, 1, 2, 3, 4, 5, 6, 7,
  113. };
  114. uint8_t
  115. dp_cpu_ring_map[DP_NSS_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS_MAX] = {
  116. {0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2},
  117. {0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1},
  118. {0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0},
  119. {0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2},
  120. {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3},
  121. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  122. {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
  123. #endif
  124. };
  125. qdf_export_symbol(dp_cpu_ring_map);
  126. /**
  127. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  128. * @soc: DP soc handle
  129. * @ring_type: ring type
  130. * @ring_num: ring_num
  131. *
  132. * Return: 0 if the ring is not offloaded, non-0 if it is offloaded
  133. */
  134. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc,
  135. enum hal_ring_type ring_type,
  136. int ring_num)
  137. {
  138. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  139. uint8_t status = 0;
  140. switch (ring_type) {
  141. case WBM2SW_RELEASE:
  142. case REO_DST:
  143. case RXDMA_BUF:
  144. case REO_EXCEPTION:
  145. status = ((nss_config) & (1 << ring_num));
  146. break;
  147. default:
  148. break;
  149. }
  150. return status;
  151. }
  152. /* MCL specific functions */
  153. #if defined(DP_CON_MON)
  154. #ifdef DP_CON_MON_MSI_ENABLED
  155. /**
  156. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  157. * @soc: pointer to dp_soc handle
  158. * @intr_ctx_num: interrupt context number for which mon mask is needed
  159. *
  160. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  161. * This function is returning 0, since in interrupt mode(softirq based RX),
  162. * we donot want to process monitor mode rings in a softirq.
  163. *
  164. * So, in case packet log is enabled for SAP/STA/P2P modes,
  165. * regular interrupt processing will not process monitor mode rings. It would be
  166. * done in a separate timer context.
  167. *
  168. * Return: 0
  169. */
  170. static inline uint32_t
  171. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  172. {
  173. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  174. }
  175. #else
  176. /**
  177. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  178. * @soc: pointer to dp_soc handle
  179. * @intr_ctx_num: interrupt context number for which mon mask is needed
  180. *
  181. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  182. * This function is returning 0, since in interrupt mode(softirq based RX),
  183. * we donot want to process monitor mode rings in a softirq.
  184. *
  185. * So, in case packet log is enabled for SAP/STA/P2P modes,
  186. * regular interrupt processing will not process monitor mode rings. It would be
  187. * done in a separate timer context.
  188. *
  189. * Return: 0
  190. */
  191. static inline uint32_t
  192. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  193. {
  194. return 0;
  195. }
  196. #endif
  197. #else
  198. /**
  199. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  200. * @soc: pointer to dp_soc handle
  201. * @intr_ctx_num: interrupt context number for which mon mask is needed
  202. *
  203. * Return: mon mask value
  204. */
  205. static inline
  206. uint32_t dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc,
  207. int intr_ctx_num)
  208. {
  209. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  210. }
  211. void dp_soc_reset_mon_intr_mask(struct dp_soc *soc)
  212. {
  213. int i;
  214. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  215. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  216. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  217. }
  218. }
  219. qdf_export_symbol(dp_soc_reset_mon_intr_mask);
  220. void dp_service_lmac_rings(void *arg)
  221. {
  222. struct dp_soc *soc = (struct dp_soc *)arg;
  223. int ring = 0, i;
  224. struct dp_pdev *pdev = NULL;
  225. union dp_rx_desc_list_elem_t *desc_list = NULL;
  226. union dp_rx_desc_list_elem_t *tail = NULL;
  227. /* Process LMAC interrupts */
  228. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  229. int mac_for_pdev = ring;
  230. struct dp_srng *rx_refill_buf_ring;
  231. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  232. if (!pdev)
  233. continue;
  234. rx_refill_buf_ring = &soc->rx_refill_buf_ring[mac_for_pdev];
  235. dp_monitor_process(soc, NULL, mac_for_pdev,
  236. QCA_NAPI_BUDGET);
  237. for (i = 0;
  238. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  239. dp_rxdma_err_process(&soc->intr_ctx[i], soc,
  240. mac_for_pdev,
  241. QCA_NAPI_BUDGET);
  242. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF,
  243. mac_for_pdev))
  244. dp_rx_buffers_replenish(soc, mac_for_pdev,
  245. rx_refill_buf_ring,
  246. &soc->rx_desc_buf[mac_for_pdev],
  247. 0, &desc_list, &tail, false);
  248. }
  249. qdf_timer_mod(&soc->lmac_reap_timer, DP_INTR_POLL_TIMER_MS);
  250. }
  251. #endif
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, uint8_t *grp_mask)
  264. {
  265. int ext_group_num;
  266. uint8_t mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. /**
  275. * dp_is_msi_group_number_invalid() - check msi_group_number valid or not
  276. * @soc: dp_soc
  277. * @msi_group_number: MSI group number.
  278. * @msi_data_count: MSI data count.
  279. *
  280. * Return: true if msi_group_number is invalid.
  281. */
  282. static bool dp_is_msi_group_number_invalid(struct dp_soc *soc,
  283. int msi_group_number,
  284. int msi_data_count)
  285. {
  286. if (soc && soc->osdev && soc->osdev->dev &&
  287. pld_is_one_msi(soc->osdev->dev))
  288. return false;
  289. return msi_group_number > msi_data_count;
  290. }
  291. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  292. /**
  293. * dp_is_reo_ring_num_in_nf_grp1() - Check if the current reo ring is part of
  294. * rx_near_full_grp1 mask
  295. * @soc: Datapath SoC Handle
  296. * @ring_num: REO ring number
  297. *
  298. * Return: 1 if the ring_num belongs to reo_nf_grp1,
  299. * 0, otherwise.
  300. */
  301. static inline int
  302. dp_is_reo_ring_num_in_nf_grp1(struct dp_soc *soc, int ring_num)
  303. {
  304. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_1 & (1 << ring_num));
  305. }
  306. /**
  307. * dp_is_reo_ring_num_in_nf_grp2() - Check if the current reo ring is part of
  308. * rx_near_full_grp2 mask
  309. * @soc: Datapath SoC Handle
  310. * @ring_num: REO ring number
  311. *
  312. * Return: 1 if the ring_num belongs to reo_nf_grp2,
  313. * 0, otherwise.
  314. */
  315. static inline int
  316. dp_is_reo_ring_num_in_nf_grp2(struct dp_soc *soc, int ring_num)
  317. {
  318. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_2 & (1 << ring_num));
  319. }
  320. /**
  321. * dp_srng_get_near_full_irq_mask() - Get near-full irq mask for a particular
  322. * ring type and number
  323. * @soc: Datapath SoC handle
  324. * @ring_type: SRNG type
  325. * @ring_num: ring num
  326. *
  327. * Return: near-full irq mask pointer
  328. */
  329. static inline
  330. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  331. enum hal_ring_type ring_type,
  332. int ring_num)
  333. {
  334. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  335. uint8_t wbm2_sw_rx_rel_ring_id;
  336. uint8_t *nf_irq_mask = NULL;
  337. switch (ring_type) {
  338. case WBM2SW_RELEASE:
  339. wbm2_sw_rx_rel_ring_id =
  340. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  341. if (ring_num != wbm2_sw_rx_rel_ring_id) {
  342. nf_irq_mask = &soc->wlan_cfg_ctx->
  343. int_tx_ring_near_full_irq_mask[0];
  344. }
  345. break;
  346. case REO_DST:
  347. if (dp_is_reo_ring_num_in_nf_grp1(soc, ring_num))
  348. nf_irq_mask =
  349. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_1_mask[0];
  350. else if (dp_is_reo_ring_num_in_nf_grp2(soc, ring_num))
  351. nf_irq_mask =
  352. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_2_mask[0];
  353. else
  354. qdf_assert(0);
  355. break;
  356. default:
  357. break;
  358. }
  359. return nf_irq_mask;
  360. }
  361. /**
  362. * dp_srng_set_msi2_ring_params() - Set the msi2 addr/data in the ring params
  363. * @soc: Datapath SoC handle
  364. * @ring_params: srng params handle
  365. * @msi2_addr: MSI2 addr to be set for the SRNG
  366. * @msi2_data: MSI2 data to be set for the SRNG
  367. *
  368. * Return: None
  369. */
  370. static inline
  371. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  372. struct hal_srng_params *ring_params,
  373. qdf_dma_addr_t msi2_addr,
  374. uint32_t msi2_data)
  375. {
  376. ring_params->msi2_addr = msi2_addr;
  377. ring_params->msi2_data = msi2_data;
  378. }
  379. /**
  380. * dp_srng_msi2_setup() - Setup MSI2 details for near full IRQ of an SRNG
  381. * @soc: Datapath SoC handle
  382. * @ring_params: ring_params for SRNG
  383. * @ring_type: SENG type
  384. * @ring_num: ring number for the SRNG
  385. * @nf_msi_grp_num: near full msi group number
  386. *
  387. * Return: None
  388. */
  389. static inline void
  390. dp_srng_msi2_setup(struct dp_soc *soc,
  391. struct hal_srng_params *ring_params,
  392. int ring_type, int ring_num, int nf_msi_grp_num)
  393. {
  394. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  395. int msi_data_count, ret;
  396. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  397. &msi_data_count, &msi_data_start,
  398. &msi_irq_start);
  399. if (ret)
  400. return;
  401. if (nf_msi_grp_num < 0) {
  402. dp_init_info("%pK: ring near full IRQ not part of an ext_group; ring_type: %d,ring_num %d",
  403. soc, ring_type, ring_num);
  404. ring_params->msi2_addr = 0;
  405. ring_params->msi2_data = 0;
  406. return;
  407. }
  408. if (dp_is_msi_group_number_invalid(soc, nf_msi_grp_num,
  409. msi_data_count)) {
  410. dp_init_warn("%pK: 2 msi_groups will share an msi for near full IRQ; msi_group_num %d",
  411. soc, nf_msi_grp_num);
  412. QDF_ASSERT(0);
  413. }
  414. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  415. ring_params->nf_irq_support = 1;
  416. ring_params->msi2_addr = addr_low;
  417. ring_params->msi2_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  418. ring_params->msi2_data = (nf_msi_grp_num % msi_data_count)
  419. + msi_data_start;
  420. ring_params->flags |= HAL_SRNG_MSI_INTR;
  421. }
  422. /* Percentage of ring entries considered as nearly full */
  423. #define DP_NF_HIGH_THRESH_PERCENTAGE 75
  424. /* Percentage of ring entries considered as critically full */
  425. #define DP_NF_CRIT_THRESH_PERCENTAGE 90
  426. /* Percentage of ring entries considered as safe threshold */
  427. #define DP_NF_SAFE_THRESH_PERCENTAGE 50
  428. /**
  429. * dp_srng_configure_nf_interrupt_thresholds() - Configure the thresholds for
  430. * near full irq
  431. * @soc: Datapath SoC handle
  432. * @ring_params: ring params for SRNG
  433. * @ring_type: ring type
  434. */
  435. static inline void
  436. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  437. struct hal_srng_params *ring_params,
  438. int ring_type)
  439. {
  440. if (ring_params->nf_irq_support) {
  441. ring_params->high_thresh = (ring_params->num_entries *
  442. DP_NF_HIGH_THRESH_PERCENTAGE) / 100;
  443. ring_params->crit_thresh = (ring_params->num_entries *
  444. DP_NF_CRIT_THRESH_PERCENTAGE) / 100;
  445. ring_params->safe_thresh = (ring_params->num_entries *
  446. DP_NF_SAFE_THRESH_PERCENTAGE) /100;
  447. }
  448. }
  449. /**
  450. * dp_srng_set_nf_thresholds() - Set the near full thresholds to srng data
  451. * structure from the ring params
  452. * @soc: Datapath SoC handle
  453. * @srng: SRNG handle
  454. * @ring_params: ring params for a SRNG
  455. *
  456. * Return: None
  457. */
  458. static inline void
  459. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  460. struct hal_srng_params *ring_params)
  461. {
  462. srng->crit_thresh = ring_params->crit_thresh;
  463. srng->safe_thresh = ring_params->safe_thresh;
  464. }
  465. #else
  466. static inline
  467. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  468. enum hal_ring_type ring_type,
  469. int ring_num)
  470. {
  471. return NULL;
  472. }
  473. static inline
  474. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  475. struct hal_srng_params *ring_params,
  476. qdf_dma_addr_t msi2_addr,
  477. uint32_t msi2_data)
  478. {
  479. }
  480. static inline void
  481. dp_srng_msi2_setup(struct dp_soc *soc,
  482. struct hal_srng_params *ring_params,
  483. int ring_type, int ring_num, int nf_msi_grp_num)
  484. {
  485. }
  486. static inline void
  487. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  488. struct hal_srng_params *ring_params,
  489. int ring_type)
  490. {
  491. }
  492. static inline void
  493. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  494. struct hal_srng_params *ring_params)
  495. {
  496. }
  497. #endif
  498. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  499. enum hal_ring_type ring_type,
  500. int ring_num,
  501. int *reg_msi_grp_num,
  502. bool nf_irq_support,
  503. int *nf_msi_grp_num)
  504. {
  505. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  506. uint8_t *grp_mask, *nf_irq_mask = NULL;
  507. bool nf_irq_enabled = false;
  508. uint8_t wbm2_sw_rx_rel_ring_id;
  509. switch (ring_type) {
  510. case WBM2SW_RELEASE:
  511. wbm2_sw_rx_rel_ring_id =
  512. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  513. if (ring_num == wbm2_sw_rx_rel_ring_id) {
  514. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  515. grp_mask = &cfg_ctx->int_rx_wbm_rel_ring_mask[0];
  516. ring_num = 0;
  517. } else if (ring_num == WBM2_SW_PPE_REL_RING_ID) {
  518. grp_mask = &cfg_ctx->int_ppeds_wbm_release_ring_mask[0];
  519. ring_num = 0;
  520. } else { /* dp_tx_comp_handler - soc->tx_comp_ring */
  521. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  522. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc,
  523. ring_type,
  524. ring_num);
  525. if (nf_irq_mask)
  526. nf_irq_enabled = true;
  527. /*
  528. * Using ring 4 as 4th tx completion ring since ring 3
  529. * is Rx error ring
  530. */
  531. if (ring_num == WBM2SW_TXCOMP_RING4_NUM)
  532. ring_num = TXCOMP_RING4_NUM;
  533. }
  534. break;
  535. case REO_EXCEPTION:
  536. /* dp_rx_err_process - &soc->reo_exception_ring */
  537. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  538. break;
  539. case REO_DST:
  540. /* dp_rx_process - soc->reo_dest_ring */
  541. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  542. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc, ring_type,
  543. ring_num);
  544. if (nf_irq_mask)
  545. nf_irq_enabled = true;
  546. break;
  547. case REO_STATUS:
  548. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  549. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  550. break;
  551. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  552. case RXDMA_MONITOR_STATUS:
  553. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  554. case RXDMA_MONITOR_DST:
  555. /* dp_mon_process */
  556. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  557. break;
  558. case TX_MONITOR_DST:
  559. /* dp_tx_mon_process */
  560. grp_mask = &soc->wlan_cfg_ctx->int_tx_mon_ring_mask[0];
  561. break;
  562. case RXDMA_DST:
  563. /* dp_rxdma_err_process */
  564. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  565. break;
  566. case RXDMA_BUF:
  567. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  568. break;
  569. case RXDMA_MONITOR_BUF:
  570. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  571. break;
  572. case TX_MONITOR_BUF:
  573. grp_mask = &soc->wlan_cfg_ctx->int_host2txmon_ring_mask[0];
  574. break;
  575. case REO2PPE:
  576. grp_mask = &soc->wlan_cfg_ctx->int_reo2ppe_ring_mask[0];
  577. break;
  578. case PPE2TCL:
  579. grp_mask = &soc->wlan_cfg_ctx->int_ppe2tcl_ring_mask[0];
  580. break;
  581. case TCL_DATA:
  582. /* CMD_CREDIT_RING is used as command in 8074 and credit in 9000 */
  583. case TCL_CMD_CREDIT:
  584. case REO_CMD:
  585. case SW2WBM_RELEASE:
  586. case WBM_IDLE_LINK:
  587. /* normally empty SW_TO_HW rings */
  588. return -QDF_STATUS_E_NOENT;
  589. break;
  590. case TCL_STATUS:
  591. case REO_REINJECT:
  592. /* misc unused rings */
  593. return -QDF_STATUS_E_NOENT;
  594. break;
  595. case CE_SRC:
  596. case CE_DST:
  597. case CE_DST_STATUS:
  598. /* CE_rings - currently handled by hif */
  599. default:
  600. return -QDF_STATUS_E_NOENT;
  601. break;
  602. }
  603. *reg_msi_grp_num = dp_srng_find_ring_in_mask(ring_num, grp_mask);
  604. if (nf_irq_support && nf_irq_enabled) {
  605. *nf_msi_grp_num = dp_srng_find_ring_in_mask(ring_num,
  606. nf_irq_mask);
  607. }
  608. return QDF_STATUS_SUCCESS;
  609. }
  610. /**
  611. * dp_get_num_msi_available()- API to get number of MSIs available
  612. * @soc: DP soc Handle
  613. * @interrupt_mode: Mode of interrupts
  614. *
  615. * Return: Number of MSIs available or 0 in case of integrated
  616. */
  617. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  618. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  619. {
  620. return 0;
  621. }
  622. #else
  623. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  624. {
  625. int msi_data_count;
  626. int msi_data_start;
  627. int msi_irq_start;
  628. int ret;
  629. if (interrupt_mode == DP_INTR_INTEGRATED) {
  630. return 0;
  631. } else if (interrupt_mode == DP_INTR_MSI || interrupt_mode ==
  632. DP_INTR_POLL) {
  633. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  634. &msi_data_count,
  635. &msi_data_start,
  636. &msi_irq_start);
  637. if (ret) {
  638. qdf_err("Unable to get DP MSI assignment %d",
  639. interrupt_mode);
  640. return -EINVAL;
  641. }
  642. return msi_data_count;
  643. }
  644. qdf_err("Interrupt mode invalid %d", interrupt_mode);
  645. return -EINVAL;
  646. }
  647. #endif
  648. #if defined(IPA_OFFLOAD) && defined(IPA_WDI3_VLAN_SUPPORT)
  649. static void
  650. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  651. int ring_num)
  652. {
  653. if (wlan_ipa_is_vlan_enabled()) {
  654. if ((ring_type == REO_DST) &&
  655. (ring_num == IPA_ALT_REO_DEST_RING_IDX)) {
  656. ring_params->msi_addr = 0;
  657. ring_params->msi_data = 0;
  658. ring_params->flags &= ~HAL_SRNG_MSI_INTR;
  659. }
  660. }
  661. }
  662. #else
  663. static inline void
  664. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  665. int ring_num)
  666. {
  667. }
  668. #endif
  669. static void dp_srng_msi_setup(struct dp_soc *soc, struct dp_srng *srng,
  670. struct hal_srng_params *ring_params,
  671. int ring_type, int ring_num)
  672. {
  673. int reg_msi_grp_num;
  674. /*
  675. * nf_msi_grp_num needs to be initialized with negative value,
  676. * to avoid configuring near-full msi for WBM2SW3 ring
  677. */
  678. int nf_msi_grp_num = -1;
  679. int msi_data_count;
  680. int ret;
  681. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  682. bool nf_irq_support;
  683. int vector;
  684. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  685. &msi_data_count, &msi_data_start,
  686. &msi_irq_start);
  687. if (ret)
  688. return;
  689. nf_irq_support = hal_srng_is_near_full_irq_supported(soc->hal_soc,
  690. ring_type,
  691. ring_num);
  692. ret = dp_srng_calculate_msi_group(soc, ring_type, ring_num,
  693. &reg_msi_grp_num,
  694. nf_irq_support,
  695. &nf_msi_grp_num);
  696. if (ret < 0) {
  697. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  698. soc, ring_type, ring_num);
  699. ring_params->msi_addr = 0;
  700. ring_params->msi_data = 0;
  701. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  702. return;
  703. }
  704. if (reg_msi_grp_num < 0) {
  705. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  706. soc, ring_type, ring_num);
  707. ring_params->msi_addr = 0;
  708. ring_params->msi_data = 0;
  709. goto configure_msi2;
  710. }
  711. if (dp_is_msi_group_number_invalid(soc, reg_msi_grp_num,
  712. msi_data_count)) {
  713. dp_init_warn("%pK: 2 msi_groups will share an msi; msi_group_num %d",
  714. soc, reg_msi_grp_num);
  715. QDF_ASSERT(0);
  716. }
  717. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  718. ring_params->msi_addr = addr_low;
  719. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  720. ring_params->msi_data = (reg_msi_grp_num % msi_data_count)
  721. + msi_data_start;
  722. ring_params->flags |= HAL_SRNG_MSI_INTR;
  723. dp_ipa_vlan_srng_msi_setup(ring_params, ring_type, ring_num);
  724. dp_debug("ring type %u ring_num %u msi->data %u msi_addr %llx",
  725. ring_type, ring_num, ring_params->msi_data,
  726. (uint64_t)ring_params->msi_addr);
  727. vector = msi_irq_start + (reg_msi_grp_num % msi_data_count);
  728. if (soc->arch_ops.dp_register_ppeds_interrupts)
  729. if (soc->arch_ops.dp_register_ppeds_interrupts(soc, srng,
  730. vector,
  731. ring_type,
  732. ring_num))
  733. return;
  734. configure_msi2:
  735. if (!nf_irq_support) {
  736. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  737. return;
  738. }
  739. dp_srng_msi2_setup(soc, ring_params, ring_type, ring_num,
  740. nf_msi_grp_num);
  741. }
  742. /**
  743. * dp_srng_configure_pointer_update_thresholds() - Retrieve pointer
  744. * update threshold value from wlan_cfg_ctx
  745. * @soc: device handle
  746. * @ring_params: per ring specific parameters
  747. * @ring_type: Ring type
  748. * @ring_num: Ring number for a given ring type
  749. * @num_entries: number of entries to fill
  750. *
  751. * Fill the ring params with the pointer update threshold
  752. * configuration parameters available in wlan_cfg_ctx
  753. *
  754. * Return: None
  755. */
  756. static void
  757. dp_srng_configure_pointer_update_thresholds(
  758. struct dp_soc *soc,
  759. struct hal_srng_params *ring_params,
  760. int ring_type, int ring_num,
  761. int num_entries)
  762. {
  763. if (ring_type == REO_DST) {
  764. ring_params->pointer_timer_threshold =
  765. wlan_cfg_get_pointer_timer_threshold_rx(
  766. soc->wlan_cfg_ctx);
  767. ring_params->pointer_num_threshold =
  768. wlan_cfg_get_pointer_num_threshold_rx(
  769. soc->wlan_cfg_ctx);
  770. }
  771. }
  772. #ifdef WLAN_DP_PER_RING_TYPE_CONFIG
  773. /**
  774. * dp_srng_configure_interrupt_thresholds() - Retrieve interrupt
  775. * threshold values from the wlan_srng_cfg table for each ring type
  776. * @soc: device handle
  777. * @ring_params: per ring specific parameters
  778. * @ring_type: Ring type
  779. * @ring_num: Ring number for a given ring type
  780. * @num_entries: number of entries to fill
  781. *
  782. * Fill the ring params with the interrupt threshold
  783. * configuration parameters available in the per ring type wlan_srng_cfg
  784. * table.
  785. *
  786. * Return: None
  787. */
  788. static void
  789. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  790. struct hal_srng_params *ring_params,
  791. int ring_type, int ring_num,
  792. int num_entries)
  793. {
  794. uint8_t wbm2_sw_rx_rel_ring_id;
  795. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  796. if (ring_type == REO_DST) {
  797. ring_params->intr_timer_thres_us =
  798. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  799. ring_params->intr_batch_cntr_thres_entries =
  800. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  801. } else if (ring_type == WBM2SW_RELEASE &&
  802. (ring_num == wbm2_sw_rx_rel_ring_id)) {
  803. ring_params->intr_timer_thres_us =
  804. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  805. ring_params->intr_batch_cntr_thres_entries =
  806. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  807. } else {
  808. ring_params->intr_timer_thres_us =
  809. soc->wlan_srng_cfg[ring_type].timer_threshold;
  810. ring_params->intr_batch_cntr_thres_entries =
  811. soc->wlan_srng_cfg[ring_type].batch_count_threshold;
  812. }
  813. ring_params->low_threshold =
  814. soc->wlan_srng_cfg[ring_type].low_threshold;
  815. if (ring_params->low_threshold)
  816. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  817. dp_srng_configure_nf_interrupt_thresholds(soc, ring_params, ring_type);
  818. }
  819. #else
  820. static void
  821. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  822. struct hal_srng_params *ring_params,
  823. int ring_type, int ring_num,
  824. int num_entries)
  825. {
  826. uint8_t wbm2_sw_rx_rel_ring_id;
  827. bool rx_refill_lt_disable;
  828. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  829. if (ring_type == REO_DST || ring_type == REO2PPE) {
  830. ring_params->intr_timer_thres_us =
  831. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  832. ring_params->intr_batch_cntr_thres_entries =
  833. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  834. } else if (ring_type == WBM2SW_RELEASE &&
  835. (ring_num < wbm2_sw_rx_rel_ring_id ||
  836. ring_num == WBM2SW_TXCOMP_RING4_NUM ||
  837. ring_num == WBM2_SW_PPE_REL_RING_ID)) {
  838. ring_params->intr_timer_thres_us =
  839. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  840. ring_params->intr_batch_cntr_thres_entries =
  841. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  842. } else if (ring_type == RXDMA_BUF) {
  843. rx_refill_lt_disable =
  844. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable
  845. (soc->wlan_cfg_ctx);
  846. ring_params->intr_timer_thres_us =
  847. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  848. if (!rx_refill_lt_disable) {
  849. ring_params->low_threshold = num_entries >> 3;
  850. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  851. ring_params->intr_batch_cntr_thres_entries = 0;
  852. }
  853. } else {
  854. ring_params->intr_timer_thres_us =
  855. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  856. ring_params->intr_batch_cntr_thres_entries =
  857. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  858. }
  859. /* These rings donot require interrupt to host. Make them zero */
  860. switch (ring_type) {
  861. case REO_REINJECT:
  862. case REO_CMD:
  863. case TCL_DATA:
  864. case TCL_CMD_CREDIT:
  865. case TCL_STATUS:
  866. case WBM_IDLE_LINK:
  867. case SW2WBM_RELEASE:
  868. case SW2RXDMA_NEW:
  869. ring_params->intr_timer_thres_us = 0;
  870. ring_params->intr_batch_cntr_thres_entries = 0;
  871. break;
  872. case PPE2TCL:
  873. ring_params->intr_timer_thres_us =
  874. wlan_cfg_get_int_timer_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  875. ring_params->intr_batch_cntr_thres_entries =
  876. wlan_cfg_get_int_batch_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  877. break;
  878. }
  879. /* Enable low threshold interrupts for rx buffer rings (regular and
  880. * monitor buffer rings.
  881. * TODO: See if this is required for any other ring
  882. */
  883. if ((ring_type == RXDMA_MONITOR_BUF) ||
  884. (ring_type == RXDMA_MONITOR_STATUS ||
  885. (ring_type == TX_MONITOR_BUF))) {
  886. /* TODO: Setting low threshold to 1/8th of ring size
  887. * see if this needs to be configurable
  888. */
  889. ring_params->low_threshold = num_entries >> 3;
  890. ring_params->intr_timer_thres_us =
  891. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  892. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  893. ring_params->intr_batch_cntr_thres_entries = 0;
  894. }
  895. /* During initialisation monitor rings are only filled with
  896. * MON_BUF_MIN_ENTRIES entries. So low threshold needs to be set to
  897. * a value less than that. Low threshold value is reconfigured again
  898. * to 1/8th of the ring size when monitor vap is created.
  899. */
  900. if (ring_type == RXDMA_MONITOR_BUF)
  901. ring_params->low_threshold = MON_BUF_MIN_ENTRIES >> 1;
  902. /* In case of PCI chipsets, we dont have PPDU end interrupts,
  903. * so MONITOR STATUS ring is reaped by receiving MSI from srng.
  904. * Keep batch threshold as 8 so that interrupt is received for
  905. * every 4 packets in MONITOR_STATUS ring
  906. */
  907. if ((ring_type == RXDMA_MONITOR_STATUS) &&
  908. (soc->intr_mode == DP_INTR_MSI))
  909. ring_params->intr_batch_cntr_thres_entries = 4;
  910. }
  911. #endif
  912. #ifdef DISABLE_MON_RING_MSI_CFG
  913. /**
  914. * dp_skip_msi_cfg() - Check if msi cfg has to be skipped for ring_type
  915. * @soc: DP SoC context
  916. * @ring_type: sring type
  917. *
  918. * Return: True if msi cfg should be skipped for srng type else false
  919. */
  920. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  921. {
  922. if (ring_type == RXDMA_MONITOR_STATUS)
  923. return true;
  924. return false;
  925. }
  926. #else
  927. #ifdef DP_CON_MON_MSI_ENABLED
  928. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  929. {
  930. if (soc->cdp_soc.ol_ops->get_con_mode &&
  931. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) {
  932. if (ring_type == REO_DST || ring_type == RXDMA_DST)
  933. return true;
  934. } else if (ring_type == RXDMA_MONITOR_STATUS) {
  935. return true;
  936. }
  937. return false;
  938. }
  939. #else
  940. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  941. {
  942. return false;
  943. }
  944. #endif /* DP_CON_MON_MSI_ENABLED */
  945. #endif /* DISABLE_MON_RING_MSI_CFG */
  946. QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng,
  947. int ring_type, int ring_num, int mac_id,
  948. uint32_t idx)
  949. {
  950. bool idle_check;
  951. hal_soc_handle_t hal_soc = soc->hal_soc;
  952. struct hal_srng_params ring_params;
  953. if (srng->hal_srng) {
  954. dp_init_err("%pK: Ring type: %d, num:%d is already initialized",
  955. soc, ring_type, ring_num);
  956. return QDF_STATUS_SUCCESS;
  957. }
  958. /* memset the srng ring to zero */
  959. qdf_mem_zero(srng->base_vaddr_unaligned, srng->alloc_size);
  960. qdf_mem_zero(&ring_params, sizeof(struct hal_srng_params));
  961. ring_params.ring_base_paddr = srng->base_paddr_aligned;
  962. ring_params.ring_base_vaddr = srng->base_vaddr_aligned;
  963. ring_params.num_entries = srng->num_entries;
  964. dp_info("Ring type: %d, num:%d vaddr %pK paddr %pK entries %u",
  965. ring_type, ring_num,
  966. (void *)ring_params.ring_base_vaddr,
  967. (void *)ring_params.ring_base_paddr,
  968. ring_params.num_entries);
  969. if (soc->intr_mode == DP_INTR_MSI && !dp_skip_msi_cfg(soc, ring_type)) {
  970. dp_srng_msi_setup(soc, srng, &ring_params, ring_type, ring_num);
  971. dp_verbose_debug("Using MSI for ring_type: %d, ring_num %d",
  972. ring_type, ring_num);
  973. } else {
  974. ring_params.msi_data = 0;
  975. ring_params.msi_addr = 0;
  976. dp_srng_set_msi2_ring_params(soc, &ring_params, 0, 0);
  977. dp_verbose_debug("Skipping MSI for ring_type: %d, ring_num %d",
  978. ring_type, ring_num);
  979. }
  980. dp_srng_configure_interrupt_thresholds(soc, &ring_params,
  981. ring_type, ring_num,
  982. srng->num_entries);
  983. dp_srng_set_nf_thresholds(soc, srng, &ring_params);
  984. dp_srng_configure_pointer_update_thresholds(soc, &ring_params,
  985. ring_type, ring_num,
  986. srng->num_entries);
  987. if (srng->cached)
  988. ring_params.flags |= HAL_SRNG_CACHED_DESC;
  989. idle_check = dp_check_umac_reset_in_progress(soc);
  990. srng->hal_srng = hal_srng_setup_idx(hal_soc, ring_type, ring_num,
  991. mac_id, &ring_params, idle_check,
  992. idx);
  993. if (!srng->hal_srng) {
  994. dp_srng_free(soc, srng);
  995. return QDF_STATUS_E_FAILURE;
  996. }
  997. return QDF_STATUS_SUCCESS;
  998. }
  999. qdf_export_symbol(dp_srng_init_idx);
  1000. static int dp_process_rxdma_dst_ring(struct dp_soc *soc,
  1001. struct dp_intr *int_ctx,
  1002. int mac_for_pdev,
  1003. int total_budget)
  1004. {
  1005. uint32_t target_type;
  1006. target_type = hal_get_target_type(soc->hal_soc);
  1007. if (target_type == TARGET_TYPE_QCN9160)
  1008. return dp_monitor_process(soc, int_ctx,
  1009. mac_for_pdev, total_budget);
  1010. else
  1011. return dp_rxdma_err_process(int_ctx, soc, mac_for_pdev,
  1012. total_budget);
  1013. }
  1014. /**
  1015. * dp_process_lmac_rings() - Process LMAC rings
  1016. * @int_ctx: interrupt context
  1017. * @total_budget: budget of work which can be done
  1018. *
  1019. * Return: work done
  1020. */
  1021. static int dp_process_lmac_rings(struct dp_intr *int_ctx, int total_budget)
  1022. {
  1023. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1024. struct dp_soc *soc = int_ctx->soc;
  1025. uint32_t remaining_quota = total_budget;
  1026. struct dp_pdev *pdev = NULL;
  1027. uint32_t work_done = 0;
  1028. int budget = total_budget;
  1029. int ring = 0;
  1030. bool rx_refill_lt_disable;
  1031. rx_refill_lt_disable =
  1032. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable(soc->wlan_cfg_ctx);
  1033. /* Process LMAC interrupts */
  1034. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  1035. int mac_for_pdev = ring;
  1036. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  1037. if (!pdev)
  1038. continue;
  1039. if (int_ctx->rx_mon_ring_mask & (1 << mac_for_pdev)) {
  1040. work_done = dp_monitor_process(soc, int_ctx,
  1041. mac_for_pdev,
  1042. remaining_quota);
  1043. if (work_done)
  1044. intr_stats->num_rx_mon_ring_masks++;
  1045. budget -= work_done;
  1046. if (budget <= 0)
  1047. goto budget_done;
  1048. remaining_quota = budget;
  1049. }
  1050. if (int_ctx->tx_mon_ring_mask & (1 << mac_for_pdev)) {
  1051. work_done = dp_tx_mon_process(soc, int_ctx,
  1052. mac_for_pdev,
  1053. remaining_quota);
  1054. if (work_done)
  1055. intr_stats->num_tx_mon_ring_masks++;
  1056. budget -= work_done;
  1057. if (budget <= 0)
  1058. goto budget_done;
  1059. remaining_quota = budget;
  1060. }
  1061. if (int_ctx->rxdma2host_ring_mask &
  1062. (1 << mac_for_pdev)) {
  1063. work_done = dp_process_rxdma_dst_ring(soc, int_ctx,
  1064. mac_for_pdev,
  1065. remaining_quota);
  1066. if (work_done)
  1067. intr_stats->num_rxdma2host_ring_masks++;
  1068. budget -= work_done;
  1069. if (budget <= 0)
  1070. goto budget_done;
  1071. remaining_quota = budget;
  1072. }
  1073. if (int_ctx->host2rxdma_ring_mask & (1 << mac_for_pdev)) {
  1074. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1075. union dp_rx_desc_list_elem_t *tail = NULL;
  1076. struct dp_srng *rx_refill_buf_ring;
  1077. struct rx_desc_pool *rx_desc_pool;
  1078. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  1079. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  1080. rx_refill_buf_ring =
  1081. &soc->rx_refill_buf_ring[mac_for_pdev];
  1082. else
  1083. rx_refill_buf_ring =
  1084. &soc->rx_refill_buf_ring[pdev->lmac_id];
  1085. intr_stats->num_host2rxdma_ring_masks++;
  1086. if (!rx_refill_lt_disable)
  1087. dp_rx_buffers_lt_replenish_simple(soc,
  1088. mac_for_pdev,
  1089. rx_refill_buf_ring,
  1090. rx_desc_pool,
  1091. 0,
  1092. &desc_list,
  1093. &tail);
  1094. }
  1095. }
  1096. if (int_ctx->host2rxdma_mon_ring_mask)
  1097. dp_rx_mon_buf_refill(int_ctx);
  1098. if (int_ctx->host2txmon_ring_mask)
  1099. dp_tx_mon_buf_refill(int_ctx);
  1100. budget_done:
  1101. return total_budget - budget;
  1102. }
  1103. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1104. /**
  1105. * dp_service_near_full_srngs() - Bottom half handler to process the near
  1106. * full IRQ on a SRNG
  1107. * @dp_ctx: Datapath SoC handle
  1108. * @dp_budget: Number of SRNGs which can be processed in a single attempt
  1109. * without rescheduling
  1110. * @cpu: cpu id
  1111. *
  1112. * Return: remaining budget/quota for the soc device
  1113. */
  1114. static
  1115. uint32_t dp_service_near_full_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1116. {
  1117. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1118. struct dp_soc *soc = int_ctx->soc;
  1119. /*
  1120. * dp_service_near_full_srngs arch ops should be initialized always
  1121. * if the NEAR FULL IRQ feature is enabled.
  1122. */
  1123. return soc->arch_ops.dp_service_near_full_srngs(soc, int_ctx,
  1124. dp_budget);
  1125. }
  1126. #endif
  1127. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1128. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1129. {
  1130. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1131. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1132. struct dp_soc *soc = int_ctx->soc;
  1133. int ring = 0;
  1134. int index;
  1135. uint32_t work_done = 0;
  1136. int budget = dp_budget;
  1137. uint8_t tx_mask = int_ctx->tx_ring_mask;
  1138. uint8_t rx_mask = int_ctx->rx_ring_mask;
  1139. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  1140. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  1141. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1142. uint32_t remaining_quota = dp_budget;
  1143. qdf_atomic_set_bit(cpu, &soc->service_rings_running);
  1144. dp_verbose_debug("tx %x rx %x rx_err %x rx_wbm_rel %x reo_status %x rx_mon_ring %x host2rxdma %x rxdma2host %x\n",
  1145. tx_mask, rx_mask, rx_err_mask, rx_wbm_rel_mask,
  1146. reo_status_mask,
  1147. int_ctx->rx_mon_ring_mask,
  1148. int_ctx->host2rxdma_ring_mask,
  1149. int_ctx->rxdma2host_ring_mask);
  1150. /* Process Tx completion interrupts first to return back buffers */
  1151. for (index = 0; index < soc->num_tx_comp_rings; index++) {
  1152. if (!(1 << wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) & tx_mask))
  1153. continue;
  1154. work_done = dp_tx_comp_handler(int_ctx,
  1155. soc,
  1156. soc->tx_comp_ring[index].hal_srng,
  1157. index, remaining_quota);
  1158. if (work_done) {
  1159. intr_stats->num_tx_ring_masks[index]++;
  1160. dp_verbose_debug("tx mask 0x%x index %d, budget %d, work_done %d",
  1161. tx_mask, index, budget,
  1162. work_done);
  1163. }
  1164. budget -= work_done;
  1165. if (budget <= 0)
  1166. goto budget_done;
  1167. remaining_quota = budget;
  1168. }
  1169. /* Process REO Exception ring interrupt */
  1170. if (rx_err_mask) {
  1171. work_done = dp_rx_err_process(int_ctx, soc,
  1172. soc->reo_exception_ring.hal_srng,
  1173. remaining_quota);
  1174. if (work_done) {
  1175. intr_stats->num_rx_err_ring_masks++;
  1176. dp_verbose_debug("REO Exception Ring: work_done %d budget %d",
  1177. work_done, budget);
  1178. }
  1179. budget -= work_done;
  1180. if (budget <= 0) {
  1181. goto budget_done;
  1182. }
  1183. remaining_quota = budget;
  1184. }
  1185. /* Process Rx WBM release ring interrupt */
  1186. if (rx_wbm_rel_mask) {
  1187. work_done = dp_rx_wbm_err_process(int_ctx, soc,
  1188. soc->rx_rel_ring.hal_srng,
  1189. remaining_quota);
  1190. if (work_done) {
  1191. intr_stats->num_rx_wbm_rel_ring_masks++;
  1192. dp_verbose_debug("WBM Release Ring: work_done %d budget %d",
  1193. work_done, budget);
  1194. }
  1195. budget -= work_done;
  1196. if (budget <= 0) {
  1197. goto budget_done;
  1198. }
  1199. remaining_quota = budget;
  1200. }
  1201. /* Process Rx interrupts */
  1202. if (rx_mask) {
  1203. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1204. if (!(rx_mask & (1 << ring)))
  1205. continue;
  1206. work_done = soc->arch_ops.dp_rx_process(int_ctx,
  1207. soc->reo_dest_ring[ring].hal_srng,
  1208. ring,
  1209. remaining_quota);
  1210. if (work_done) {
  1211. intr_stats->num_rx_ring_masks[ring]++;
  1212. dp_verbose_debug("rx mask 0x%x ring %d, work_done %d budget %d",
  1213. rx_mask, ring,
  1214. work_done, budget);
  1215. budget -= work_done;
  1216. if (budget <= 0)
  1217. goto budget_done;
  1218. remaining_quota = budget;
  1219. }
  1220. }
  1221. }
  1222. if (reo_status_mask) {
  1223. if (dp_reo_status_ring_handler(int_ctx, soc))
  1224. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1225. }
  1226. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1227. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1228. if (work_done) {
  1229. budget -= work_done;
  1230. if (budget <= 0)
  1231. goto budget_done;
  1232. remaining_quota = budget;
  1233. }
  1234. }
  1235. qdf_lro_flush(int_ctx->lro_ctx);
  1236. intr_stats->num_masks++;
  1237. budget_done:
  1238. qdf_atomic_clear_bit(cpu, &soc->service_rings_running);
  1239. if (soc->notify_fw_callback)
  1240. soc->notify_fw_callback(soc);
  1241. return dp_budget - budget;
  1242. }
  1243. #else /* QCA_HOST_MODE_WIFI_DISABLED */
  1244. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1245. {
  1246. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1247. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1248. struct dp_soc *soc = int_ctx->soc;
  1249. uint32_t remaining_quota = dp_budget;
  1250. uint32_t work_done = 0;
  1251. int budget = dp_budget;
  1252. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1253. if (reo_status_mask) {
  1254. if (dp_reo_status_ring_handler(int_ctx, soc))
  1255. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1256. }
  1257. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1258. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1259. if (work_done) {
  1260. budget -= work_done;
  1261. if (budget <= 0)
  1262. goto budget_done;
  1263. remaining_quota = budget;
  1264. }
  1265. }
  1266. qdf_lro_flush(int_ctx->lro_ctx);
  1267. intr_stats->num_masks++;
  1268. budget_done:
  1269. return dp_budget - budget;
  1270. }
  1271. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1272. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  1273. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1274. struct dp_intr *intr_ctx)
  1275. {
  1276. if (intr_ctx->rx_mon_ring_mask)
  1277. return true;
  1278. return false;
  1279. }
  1280. #else
  1281. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1282. struct dp_intr *intr_ctx)
  1283. {
  1284. return false;
  1285. }
  1286. #endif
  1287. QDF_STATUS dp_soc_attach_poll(struct cdp_soc_t *txrx_soc)
  1288. {
  1289. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1290. int i;
  1291. int lmac_id = 0;
  1292. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1293. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1294. soc->intr_mode = DP_INTR_POLL;
  1295. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1296. soc->intr_ctx[i].dp_intr_id = i;
  1297. soc->intr_ctx[i].tx_ring_mask =
  1298. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1299. soc->intr_ctx[i].rx_ring_mask =
  1300. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1301. soc->intr_ctx[i].rx_mon_ring_mask =
  1302. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1303. soc->intr_ctx[i].rx_err_ring_mask =
  1304. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1305. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  1306. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1307. soc->intr_ctx[i].reo_status_ring_mask =
  1308. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1309. soc->intr_ctx[i].rxdma2host_ring_mask =
  1310. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1311. soc->intr_ctx[i].soc = soc;
  1312. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1313. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1314. hif_event_history_init(soc->hif_handle, i);
  1315. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1316. lmac_id++;
  1317. }
  1318. }
  1319. qdf_timer_init(soc->osdev, &soc->int_timer,
  1320. dp_interrupt_timer, (void *)soc,
  1321. QDF_TIMER_TYPE_WAKE_APPS);
  1322. return QDF_STATUS_SUCCESS;
  1323. }
  1324. void dp_soc_set_interrupt_mode(struct dp_soc *soc)
  1325. {
  1326. uint32_t msi_base_data, msi_vector_start;
  1327. int msi_vector_count, ret;
  1328. soc->intr_mode = DP_INTR_INTEGRATED;
  1329. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  1330. (dp_is_monitor_mode_using_poll(soc) &&
  1331. soc->cdp_soc.ol_ops->get_con_mode &&
  1332. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)) {
  1333. soc->intr_mode = DP_INTR_POLL;
  1334. } else {
  1335. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1336. &msi_vector_count,
  1337. &msi_base_data,
  1338. &msi_vector_start);
  1339. if (ret)
  1340. return;
  1341. soc->intr_mode = DP_INTR_MSI;
  1342. }
  1343. }
  1344. #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS
  1345. /**
  1346. * dp_soc_interrupt_map_calculate_wifi3_pci_legacy() -
  1347. * Calculate interrupt map for legacy interrupts
  1348. * @soc: DP soc handle
  1349. * @intr_ctx_num: Interrupt context number
  1350. * @irq_id_map: IRQ map
  1351. * @num_irq_r: Number of interrupts assigned for this context
  1352. *
  1353. * Return: void
  1354. */
  1355. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1356. int intr_ctx_num,
  1357. int *irq_id_map,
  1358. int *num_irq_r)
  1359. {
  1360. int j;
  1361. int num_irq = 0;
  1362. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1363. soc->wlan_cfg_ctx, intr_ctx_num);
  1364. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1365. soc->wlan_cfg_ctx, intr_ctx_num);
  1366. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1367. soc->wlan_cfg_ctx, intr_ctx_num);
  1368. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1369. soc->wlan_cfg_ctx, intr_ctx_num);
  1370. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1371. soc->wlan_cfg_ctx, intr_ctx_num);
  1372. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1373. soc->wlan_cfg_ctx, intr_ctx_num);
  1374. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1375. soc->wlan_cfg_ctx, intr_ctx_num);
  1376. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1377. soc->wlan_cfg_ctx, intr_ctx_num);
  1378. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1379. soc->wlan_cfg_ctx, intr_ctx_num);
  1380. soc->intr_mode = DP_INTR_LEGACY_VIRTUAL_IRQ;
  1381. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1382. if (tx_mask & (1 << j))
  1383. irq_id_map[num_irq++] = (wbm2sw0_release - j);
  1384. if (rx_mask & (1 << j))
  1385. irq_id_map[num_irq++] = (reo2sw1_intr - j);
  1386. if (rx_mon_mask & (1 << j))
  1387. irq_id_map[num_irq++] = (rxmon2sw_p0_dest0 - j);
  1388. if (rx_err_ring_mask & (1 << j))
  1389. irq_id_map[num_irq++] = (reo2sw0_intr - j);
  1390. if (rx_wbm_rel_ring_mask & (1 << j))
  1391. irq_id_map[num_irq++] = (wbm2sw5_release - j);
  1392. if (reo_status_ring_mask & (1 << j))
  1393. irq_id_map[num_irq++] = (reo_status - j);
  1394. if (rxdma2host_ring_mask & (1 << j))
  1395. irq_id_map[num_irq++] = (rxdma2sw_dst_ring0 - j);
  1396. if (host2rxdma_ring_mask & (1 << j))
  1397. irq_id_map[num_irq++] = (sw2rxdma_0 - j);
  1398. if (host2rxdma_mon_ring_mask & (1 << j))
  1399. irq_id_map[num_irq++] = (sw2rxmon_src_ring - j);
  1400. }
  1401. *num_irq_r = num_irq;
  1402. }
  1403. #else
  1404. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1405. int intr_ctx_num,
  1406. int *irq_id_map,
  1407. int *num_irq_r)
  1408. {
  1409. }
  1410. #endif
  1411. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  1412. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  1413. {
  1414. int j;
  1415. int num_irq = 0;
  1416. int tx_mask =
  1417. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1418. int rx_mask =
  1419. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1420. int rx_mon_mask =
  1421. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1422. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1423. soc->wlan_cfg_ctx, intr_ctx_num);
  1424. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1425. soc->wlan_cfg_ctx, intr_ctx_num);
  1426. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1427. soc->wlan_cfg_ctx, intr_ctx_num);
  1428. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1429. soc->wlan_cfg_ctx, intr_ctx_num);
  1430. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1431. soc->wlan_cfg_ctx, intr_ctx_num);
  1432. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1433. soc->wlan_cfg_ctx, intr_ctx_num);
  1434. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1435. soc->wlan_cfg_ctx, intr_ctx_num);
  1436. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1437. soc->wlan_cfg_ctx, intr_ctx_num);
  1438. soc->intr_mode = DP_INTR_INTEGRATED;
  1439. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1440. if (tx_mask & (1 << j)) {
  1441. irq_id_map[num_irq++] =
  1442. (wbm2host_tx_completions_ring1 - j);
  1443. }
  1444. if (rx_mask & (1 << j)) {
  1445. irq_id_map[num_irq++] =
  1446. (reo2host_destination_ring1 - j);
  1447. }
  1448. if (rxdma2host_ring_mask & (1 << j)) {
  1449. irq_id_map[num_irq++] =
  1450. rxdma2host_destination_ring_mac1 - j;
  1451. }
  1452. if (host2rxdma_ring_mask & (1 << j)) {
  1453. irq_id_map[num_irq++] =
  1454. host2rxdma_host_buf_ring_mac1 - j;
  1455. }
  1456. if (host2rxdma_mon_ring_mask & (1 << j)) {
  1457. irq_id_map[num_irq++] =
  1458. host2rxdma_monitor_ring1 - j;
  1459. }
  1460. if (rx_mon_mask & (1 << j)) {
  1461. irq_id_map[num_irq++] =
  1462. ppdu_end_interrupts_mac1 - j;
  1463. irq_id_map[num_irq++] =
  1464. rxdma2host_monitor_status_ring_mac1 - j;
  1465. irq_id_map[num_irq++] =
  1466. rxdma2host_monitor_destination_mac1 - j;
  1467. }
  1468. if (rx_wbm_rel_ring_mask & (1 << j))
  1469. irq_id_map[num_irq++] = wbm2host_rx_release;
  1470. if (rx_err_ring_mask & (1 << j))
  1471. irq_id_map[num_irq++] = reo2host_exception;
  1472. if (reo_status_ring_mask & (1 << j))
  1473. irq_id_map[num_irq++] = reo2host_status;
  1474. if (host2txmon_ring_mask & (1 << j))
  1475. irq_id_map[num_irq++] = host2tx_monitor_ring1;
  1476. if (txmon2host_mon_ring_mask & (1 << j)) {
  1477. irq_id_map[num_irq++] =
  1478. (txmon2host_monitor_destination_mac1 - j);
  1479. }
  1480. }
  1481. *num_irq_r = num_irq;
  1482. }
  1483. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  1484. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  1485. int msi_vector_count, int msi_vector_start)
  1486. {
  1487. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1488. soc->wlan_cfg_ctx, intr_ctx_num);
  1489. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1490. soc->wlan_cfg_ctx, intr_ctx_num);
  1491. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1492. soc->wlan_cfg_ctx, intr_ctx_num);
  1493. int tx_mon_mask = wlan_cfg_get_tx_mon_ring_mask(
  1494. soc->wlan_cfg_ctx, intr_ctx_num);
  1495. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1496. soc->wlan_cfg_ctx, intr_ctx_num);
  1497. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1498. soc->wlan_cfg_ctx, intr_ctx_num);
  1499. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1500. soc->wlan_cfg_ctx, intr_ctx_num);
  1501. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1502. soc->wlan_cfg_ctx, intr_ctx_num);
  1503. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1504. soc->wlan_cfg_ctx, intr_ctx_num);
  1505. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1506. soc->wlan_cfg_ctx, intr_ctx_num);
  1507. int rx_near_full_grp_1_mask =
  1508. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1509. intr_ctx_num);
  1510. int rx_near_full_grp_2_mask =
  1511. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1512. intr_ctx_num);
  1513. int tx_ring_near_full_mask =
  1514. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1515. intr_ctx_num);
  1516. int host2txmon_ring_mask =
  1517. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx,
  1518. intr_ctx_num);
  1519. unsigned int vector =
  1520. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  1521. int num_irq = 0;
  1522. soc->intr_mode = DP_INTR_MSI;
  1523. if (tx_mask | rx_mask | rx_mon_mask | tx_mon_mask | rx_err_ring_mask |
  1524. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask |
  1525. host2rxdma_ring_mask | host2rxdma_mon_ring_mask |
  1526. rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1527. tx_ring_near_full_mask | host2txmon_ring_mask)
  1528. irq_id_map[num_irq++] =
  1529. pld_get_msi_irq(soc->osdev->dev, vector);
  1530. *num_irq_r = num_irq;
  1531. }
  1532. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  1533. int *irq_id_map, int *num_irq)
  1534. {
  1535. int msi_vector_count, ret;
  1536. uint32_t msi_base_data, msi_vector_start;
  1537. if (pld_get_enable_intx(soc->osdev->dev)) {
  1538. return dp_soc_interrupt_map_calculate_wifi3_pci_legacy(soc,
  1539. intr_ctx_num, irq_id_map, num_irq);
  1540. }
  1541. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1542. &msi_vector_count,
  1543. &msi_base_data,
  1544. &msi_vector_start);
  1545. if (ret)
  1546. return dp_soc_interrupt_map_calculate_integrated(soc,
  1547. intr_ctx_num, irq_id_map, num_irq);
  1548. else
  1549. dp_soc_interrupt_map_calculate_msi(soc,
  1550. intr_ctx_num, irq_id_map, num_irq,
  1551. msi_vector_count, msi_vector_start);
  1552. }
  1553. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1554. /**
  1555. * dp_soc_near_full_interrupt_attach() - Register handler for DP near fill irq
  1556. * @soc: DP soc handle
  1557. * @num_irq: IRQ number
  1558. * @irq_id_map: IRQ map
  1559. * @intr_id: interrupt context ID
  1560. *
  1561. * Return: 0 for success. nonzero for failure.
  1562. */
  1563. static inline int
  1564. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1565. int irq_id_map[], int intr_id)
  1566. {
  1567. return hif_register_ext_group(soc->hif_handle,
  1568. num_irq, irq_id_map,
  1569. dp_service_near_full_srngs,
  1570. &soc->intr_ctx[intr_id], "dp_nf_intr",
  1571. HIF_EXEC_NAPI_TYPE,
  1572. QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  1573. }
  1574. #else
  1575. static inline int
  1576. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1577. int *irq_id_map, int intr_id)
  1578. {
  1579. return 0;
  1580. }
  1581. #endif
  1582. #ifdef DP_CON_MON_MSI_SKIP_SET
  1583. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1584. {
  1585. return !!(soc->cdp_soc.ol_ops->get_con_mode() !=
  1586. QDF_GLOBAL_MONITOR_MODE);
  1587. }
  1588. #else
  1589. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1590. {
  1591. return false;
  1592. }
  1593. #endif
  1594. void dp_soc_interrupt_detach(struct cdp_soc_t *txrx_soc)
  1595. {
  1596. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1597. int i;
  1598. if (soc->intr_mode == DP_INTR_POLL) {
  1599. qdf_timer_free(&soc->int_timer);
  1600. } else {
  1601. hif_deconfigure_ext_group_interrupts(soc->hif_handle);
  1602. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1603. hif_deregister_exec_group(soc->hif_handle, "dp_nf_intr");
  1604. }
  1605. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1606. soc->intr_ctx[i].tx_ring_mask = 0;
  1607. soc->intr_ctx[i].rx_ring_mask = 0;
  1608. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1609. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1610. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1611. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1612. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1613. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  1614. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  1615. soc->intr_ctx[i].rx_near_full_grp_1_mask = 0;
  1616. soc->intr_ctx[i].rx_near_full_grp_2_mask = 0;
  1617. soc->intr_ctx[i].tx_ring_near_full_mask = 0;
  1618. soc->intr_ctx[i].tx_mon_ring_mask = 0;
  1619. soc->intr_ctx[i].host2txmon_ring_mask = 0;
  1620. soc->intr_ctx[i].umac_reset_intr_mask = 0;
  1621. hif_event_history_deinit(soc->hif_handle, i);
  1622. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1623. }
  1624. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1625. sizeof(soc->mon_intr_id_lmac_map),
  1626. DP_MON_INVALID_LMAC_ID);
  1627. }
  1628. QDF_STATUS dp_soc_interrupt_attach(struct cdp_soc_t *txrx_soc)
  1629. {
  1630. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1631. int i = 0;
  1632. int num_irq = 0;
  1633. int rx_err_ring_intr_ctxt_id = HIF_MAX_GROUP;
  1634. int lmac_id = 0;
  1635. int napi_scale;
  1636. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1637. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1638. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1639. int ret = 0;
  1640. /* Map of IRQ ids registered with one interrupt context */
  1641. int irq_id_map[HIF_MAX_GRP_IRQ];
  1642. int tx_mask =
  1643. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1644. int rx_mask =
  1645. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1646. int rx_mon_mask =
  1647. dp_soc_get_mon_mask_for_interrupt_mode(soc, i);
  1648. int tx_mon_ring_mask =
  1649. wlan_cfg_get_tx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1650. int rx_err_ring_mask =
  1651. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1652. int rx_wbm_rel_ring_mask =
  1653. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1654. int reo_status_ring_mask =
  1655. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1656. int rxdma2host_ring_mask =
  1657. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1658. int host2rxdma_ring_mask =
  1659. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  1660. int host2rxdma_mon_ring_mask =
  1661. wlan_cfg_get_host2rxdma_mon_ring_mask(
  1662. soc->wlan_cfg_ctx, i);
  1663. int rx_near_full_grp_1_mask =
  1664. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1665. i);
  1666. int rx_near_full_grp_2_mask =
  1667. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1668. i);
  1669. int tx_ring_near_full_mask =
  1670. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1671. i);
  1672. int host2txmon_ring_mask =
  1673. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx, i);
  1674. int umac_reset_intr_mask =
  1675. wlan_cfg_get_umac_reset_intr_mask(soc->wlan_cfg_ctx, i);
  1676. if (dp_skip_rx_mon_ring_mask_set(soc))
  1677. rx_mon_mask = 0;
  1678. soc->intr_ctx[i].dp_intr_id = i;
  1679. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1680. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1681. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1682. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1683. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1684. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  1685. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1686. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1687. soc->intr_ctx[i].host2rxdma_mon_ring_mask =
  1688. host2rxdma_mon_ring_mask;
  1689. soc->intr_ctx[i].rx_near_full_grp_1_mask =
  1690. rx_near_full_grp_1_mask;
  1691. soc->intr_ctx[i].rx_near_full_grp_2_mask =
  1692. rx_near_full_grp_2_mask;
  1693. soc->intr_ctx[i].tx_ring_near_full_mask =
  1694. tx_ring_near_full_mask;
  1695. soc->intr_ctx[i].tx_mon_ring_mask = tx_mon_ring_mask;
  1696. soc->intr_ctx[i].host2txmon_ring_mask = host2txmon_ring_mask;
  1697. soc->intr_ctx[i].umac_reset_intr_mask = umac_reset_intr_mask;
  1698. soc->intr_ctx[i].soc = soc;
  1699. num_irq = 0;
  1700. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1701. &num_irq);
  1702. if (rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1703. tx_ring_near_full_mask) {
  1704. dp_soc_near_full_interrupt_attach(soc, num_irq,
  1705. irq_id_map, i);
  1706. } else {
  1707. napi_scale = wlan_cfg_get_napi_scale_factor(
  1708. soc->wlan_cfg_ctx);
  1709. if (!napi_scale)
  1710. napi_scale = QCA_NAPI_DEF_SCALE_BIN_SHIFT;
  1711. ret = hif_register_ext_group(soc->hif_handle,
  1712. num_irq, irq_id_map, dp_service_srngs,
  1713. &soc->intr_ctx[i], "dp_intr",
  1714. HIF_EXEC_NAPI_TYPE, napi_scale);
  1715. }
  1716. dp_debug(" int ctx %u num_irq %u irq_id_map %u %u",
  1717. i, num_irq, irq_id_map[0], irq_id_map[1]);
  1718. if (ret) {
  1719. dp_init_err("%pK: failed, ret = %d", soc, ret);
  1720. dp_soc_interrupt_detach(txrx_soc);
  1721. return QDF_STATUS_E_FAILURE;
  1722. }
  1723. hif_event_history_init(soc->hif_handle, i);
  1724. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1725. if (rx_err_ring_mask)
  1726. rx_err_ring_intr_ctxt_id = i;
  1727. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1728. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1729. lmac_id++;
  1730. }
  1731. }
  1732. hif_configure_ext_group_interrupts(soc->hif_handle);
  1733. if (rx_err_ring_intr_ctxt_id != HIF_MAX_GROUP)
  1734. hif_config_irq_clear_cpu_affinity(soc->hif_handle,
  1735. rx_err_ring_intr_ctxt_id, 0);
  1736. return QDF_STATUS_SUCCESS;
  1737. }
  1738. #define AVG_MAX_MPDUS_PER_TID 128
  1739. #define AVG_TIDS_PER_CLIENT 2
  1740. #define AVG_FLOWS_PER_TID 2
  1741. #define AVG_MSDUS_PER_FLOW 128
  1742. #define AVG_MSDUS_PER_MPDU 4
  1743. void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id)
  1744. {
  1745. struct qdf_mem_multi_page_t *pages;
  1746. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1747. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1748. } else {
  1749. pages = &soc->link_desc_pages;
  1750. }
  1751. if (!pages) {
  1752. dp_err("can not get link desc pages");
  1753. QDF_ASSERT(0);
  1754. return;
  1755. }
  1756. if (pages->dma_pages) {
  1757. wlan_minidump_remove((void *)
  1758. pages->dma_pages->page_v_addr_start,
  1759. pages->num_pages * pages->page_size,
  1760. soc->ctrl_psoc,
  1761. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1762. "hw_link_desc_bank");
  1763. dp_desc_multi_pages_mem_free(soc, DP_HW_LINK_DESC_TYPE,
  1764. pages, 0, false);
  1765. }
  1766. }
  1767. qdf_export_symbol(dp_hw_link_desc_pool_banks_free);
  1768. QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, uint32_t mac_id)
  1769. {
  1770. hal_soc_handle_t hal_soc = soc->hal_soc;
  1771. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1772. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1773. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1774. uint32_t num_mpdus_per_link_desc = hal_num_mpdus_per_link_desc(hal_soc);
  1775. uint32_t num_msdus_per_link_desc = hal_num_msdus_per_link_desc(hal_soc);
  1776. uint32_t num_mpdu_links_per_queue_desc =
  1777. hal_num_mpdu_links_per_queue_desc(hal_soc);
  1778. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1779. uint32_t *total_link_descs, total_mem_size;
  1780. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1781. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1782. uint32_t num_entries;
  1783. struct qdf_mem_multi_page_t *pages;
  1784. struct dp_srng *dp_srng;
  1785. uint8_t minidump_str[MINIDUMP_STR_SIZE];
  1786. /* Only Tx queue descriptors are allocated from common link descriptor
  1787. * pool Rx queue descriptors are not included in this because (REO queue
  1788. * extension descriptors) they are expected to be allocated contiguously
  1789. * with REO queue descriptors
  1790. */
  1791. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1792. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1793. /* dp_monitor_get_link_desc_pages returns NULL only
  1794. * if monitor SOC is NULL
  1795. */
  1796. if (!pages) {
  1797. dp_err("can not get link desc pages");
  1798. QDF_ASSERT(0);
  1799. return QDF_STATUS_E_FAULT;
  1800. }
  1801. dp_srng = &soc->rxdma_mon_desc_ring[mac_id];
  1802. num_entries = dp_srng->alloc_size /
  1803. hal_srng_get_entrysize(soc->hal_soc,
  1804. RXDMA_MONITOR_DESC);
  1805. total_link_descs = dp_monitor_get_total_link_descs(soc, mac_id);
  1806. qdf_str_lcopy(minidump_str, "mon_link_desc_bank",
  1807. MINIDUMP_STR_SIZE);
  1808. } else {
  1809. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1810. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1811. num_mpdu_queue_descs = num_mpdu_link_descs /
  1812. num_mpdu_links_per_queue_desc;
  1813. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1814. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1815. num_msdus_per_link_desc;
  1816. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1817. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1818. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1819. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1820. pages = &soc->link_desc_pages;
  1821. total_link_descs = &soc->total_link_descs;
  1822. qdf_str_lcopy(minidump_str, "link_desc_bank",
  1823. MINIDUMP_STR_SIZE);
  1824. }
  1825. /* If link descriptor banks are allocated, return from here */
  1826. if (pages->num_pages)
  1827. return QDF_STATUS_SUCCESS;
  1828. /* Round up to power of 2 */
  1829. *total_link_descs = 1;
  1830. while (*total_link_descs < num_entries)
  1831. *total_link_descs <<= 1;
  1832. dp_init_info("%pK: total_link_descs: %u, link_desc_size: %d",
  1833. soc, *total_link_descs, link_desc_size);
  1834. total_mem_size = *total_link_descs * link_desc_size;
  1835. total_mem_size += link_desc_align;
  1836. dp_init_info("%pK: total_mem_size: %d",
  1837. soc, total_mem_size);
  1838. dp_set_max_page_size(pages, max_alloc_size);
  1839. dp_desc_multi_pages_mem_alloc(soc, DP_HW_LINK_DESC_TYPE,
  1840. pages,
  1841. link_desc_size,
  1842. *total_link_descs,
  1843. 0, false);
  1844. if (!pages->num_pages) {
  1845. dp_err("Multi page alloc fail for hw link desc pool");
  1846. return QDF_STATUS_E_FAULT;
  1847. }
  1848. wlan_minidump_log(pages->dma_pages->page_v_addr_start,
  1849. pages->num_pages * pages->page_size,
  1850. soc->ctrl_psoc,
  1851. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1852. "hw_link_desc_bank");
  1853. return QDF_STATUS_SUCCESS;
  1854. }
  1855. void dp_hw_link_desc_ring_free(struct dp_soc *soc)
  1856. {
  1857. uint32_t i;
  1858. uint32_t size = soc->wbm_idle_scatter_buf_size;
  1859. void *vaddr = soc->wbm_idle_link_ring.base_vaddr_unaligned;
  1860. qdf_dma_addr_t paddr;
  1861. if (soc->wbm_idle_scatter_buf_base_vaddr[0]) {
  1862. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1863. vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1864. paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1865. if (vaddr) {
  1866. qdf_mem_free_consistent(soc->osdev,
  1867. soc->osdev->dev,
  1868. size,
  1869. vaddr,
  1870. paddr,
  1871. 0);
  1872. vaddr = NULL;
  1873. }
  1874. }
  1875. } else {
  1876. wlan_minidump_remove(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1877. soc->wbm_idle_link_ring.alloc_size,
  1878. soc->ctrl_psoc,
  1879. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1880. "wbm_idle_link_ring");
  1881. dp_srng_free(soc, &soc->wbm_idle_link_ring);
  1882. }
  1883. }
  1884. QDF_STATUS dp_hw_link_desc_ring_alloc(struct dp_soc *soc)
  1885. {
  1886. uint32_t entry_size, i;
  1887. uint32_t total_mem_size;
  1888. qdf_dma_addr_t *baseaddr = NULL;
  1889. struct dp_srng *dp_srng;
  1890. uint32_t ring_type;
  1891. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1892. uint32_t tlds;
  1893. ring_type = WBM_IDLE_LINK;
  1894. dp_srng = &soc->wbm_idle_link_ring;
  1895. tlds = soc->total_link_descs;
  1896. entry_size = hal_srng_get_entrysize(soc->hal_soc, ring_type);
  1897. total_mem_size = entry_size * tlds;
  1898. if (total_mem_size <= max_alloc_size) {
  1899. if (dp_srng_alloc(soc, dp_srng, ring_type, tlds, 0)) {
  1900. dp_init_err("%pK: Link desc idle ring setup failed",
  1901. soc);
  1902. goto fail;
  1903. }
  1904. wlan_minidump_log(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1905. soc->wbm_idle_link_ring.alloc_size,
  1906. soc->ctrl_psoc,
  1907. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1908. "wbm_idle_link_ring");
  1909. } else {
  1910. uint32_t num_scatter_bufs;
  1911. uint32_t buf_size = 0;
  1912. soc->wbm_idle_scatter_buf_size =
  1913. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1914. hal_idle_scatter_buf_num_entries(
  1915. soc->hal_soc,
  1916. soc->wbm_idle_scatter_buf_size);
  1917. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1918. soc->hal_soc, total_mem_size,
  1919. soc->wbm_idle_scatter_buf_size);
  1920. if (num_scatter_bufs > MAX_IDLE_SCATTER_BUFS) {
  1921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1922. FL("scatter bufs size out of bounds"));
  1923. goto fail;
  1924. }
  1925. for (i = 0; i < num_scatter_bufs; i++) {
  1926. baseaddr = &soc->wbm_idle_scatter_buf_base_paddr[i];
  1927. buf_size = soc->wbm_idle_scatter_buf_size;
  1928. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1929. qdf_mem_alloc_consistent(soc->osdev,
  1930. soc->osdev->dev,
  1931. buf_size,
  1932. baseaddr);
  1933. if (!soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP,
  1935. QDF_TRACE_LEVEL_ERROR,
  1936. FL("Scatter lst memory alloc fail"));
  1937. goto fail;
  1938. }
  1939. }
  1940. soc->num_scatter_bufs = num_scatter_bufs;
  1941. }
  1942. return QDF_STATUS_SUCCESS;
  1943. fail:
  1944. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1945. void *vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1946. qdf_dma_addr_t paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1947. if (vaddr) {
  1948. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1949. soc->wbm_idle_scatter_buf_size,
  1950. vaddr,
  1951. paddr, 0);
  1952. vaddr = NULL;
  1953. }
  1954. }
  1955. return QDF_STATUS_E_NOMEM;
  1956. }
  1957. qdf_export_symbol(dp_hw_link_desc_pool_banks_alloc);
  1958. QDF_STATUS dp_hw_link_desc_ring_init(struct dp_soc *soc)
  1959. {
  1960. struct dp_srng *dp_srng = &soc->wbm_idle_link_ring;
  1961. if (dp_srng->base_vaddr_unaligned) {
  1962. if (dp_srng_init(soc, dp_srng, WBM_IDLE_LINK, 0, 0))
  1963. return QDF_STATUS_E_FAILURE;
  1964. }
  1965. return QDF_STATUS_SUCCESS;
  1966. }
  1967. void dp_hw_link_desc_ring_deinit(struct dp_soc *soc)
  1968. {
  1969. dp_srng_deinit(soc, &soc->wbm_idle_link_ring, WBM_IDLE_LINK, 0);
  1970. }
  1971. void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id)
  1972. {
  1973. uint32_t cookie = 0;
  1974. uint32_t page_idx = 0;
  1975. struct qdf_mem_multi_page_t *pages;
  1976. struct qdf_mem_dma_page_t *dma_pages;
  1977. uint32_t offset = 0;
  1978. uint32_t count = 0;
  1979. uint32_t desc_id = 0;
  1980. void *desc_srng;
  1981. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1982. uint32_t *total_link_descs_addr;
  1983. uint32_t total_link_descs;
  1984. uint32_t scatter_buf_num;
  1985. uint32_t num_entries_per_buf = 0;
  1986. uint32_t rem_entries;
  1987. uint32_t num_descs_per_page;
  1988. uint32_t num_scatter_bufs = 0;
  1989. uint8_t *scatter_buf_ptr;
  1990. void *desc;
  1991. num_scatter_bufs = soc->num_scatter_bufs;
  1992. if (mac_id == WLAN_INVALID_PDEV_ID) {
  1993. pages = &soc->link_desc_pages;
  1994. total_link_descs = soc->total_link_descs;
  1995. desc_srng = soc->wbm_idle_link_ring.hal_srng;
  1996. } else {
  1997. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1998. /* dp_monitor_get_link_desc_pages returns NULL only
  1999. * if monitor SOC is NULL
  2000. */
  2001. if (!pages) {
  2002. dp_err("can not get link desc pages");
  2003. QDF_ASSERT(0);
  2004. return;
  2005. }
  2006. total_link_descs_addr =
  2007. dp_monitor_get_total_link_descs(soc, mac_id);
  2008. total_link_descs = *total_link_descs_addr;
  2009. desc_srng = soc->rxdma_mon_desc_ring[mac_id].hal_srng;
  2010. }
  2011. dma_pages = pages->dma_pages;
  2012. do {
  2013. qdf_mem_zero(dma_pages[page_idx].page_v_addr_start,
  2014. pages->page_size);
  2015. page_idx++;
  2016. } while (page_idx < pages->num_pages);
  2017. if (desc_srng) {
  2018. hal_srng_access_start_unlocked(soc->hal_soc, desc_srng);
  2019. page_idx = 0;
  2020. count = 0;
  2021. offset = 0;
  2022. pages = &soc->link_desc_pages;
  2023. while ((desc = hal_srng_src_get_next(soc->hal_soc,
  2024. desc_srng)) &&
  2025. (count < total_link_descs)) {
  2026. page_idx = count / pages->num_element_per_page;
  2027. if (desc_id == pages->num_element_per_page)
  2028. desc_id = 0;
  2029. offset = count % pages->num_element_per_page;
  2030. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2031. soc->link_desc_id_start);
  2032. hal_set_link_desc_addr(soc->hal_soc, desc, cookie,
  2033. dma_pages[page_idx].page_p_addr
  2034. + (offset * link_desc_size),
  2035. soc->idle_link_bm_id);
  2036. count++;
  2037. desc_id++;
  2038. }
  2039. hal_srng_access_end_unlocked(soc->hal_soc, desc_srng);
  2040. } else {
  2041. /* Populate idle list scatter buffers with link descriptor
  2042. * pointers
  2043. */
  2044. scatter_buf_num = 0;
  2045. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  2046. soc->hal_soc,
  2047. soc->wbm_idle_scatter_buf_size);
  2048. scatter_buf_ptr = (uint8_t *)(
  2049. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  2050. rem_entries = num_entries_per_buf;
  2051. pages = &soc->link_desc_pages;
  2052. page_idx = 0; count = 0;
  2053. offset = 0;
  2054. num_descs_per_page = pages->num_element_per_page;
  2055. while (count < total_link_descs) {
  2056. page_idx = count / num_descs_per_page;
  2057. offset = count % num_descs_per_page;
  2058. if (desc_id == pages->num_element_per_page)
  2059. desc_id = 0;
  2060. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2061. soc->link_desc_id_start);
  2062. hal_set_link_desc_addr(soc->hal_soc,
  2063. (void *)scatter_buf_ptr,
  2064. cookie,
  2065. dma_pages[page_idx].page_p_addr +
  2066. (offset * link_desc_size),
  2067. soc->idle_link_bm_id);
  2068. rem_entries--;
  2069. if (rem_entries) {
  2070. scatter_buf_ptr += link_desc_size;
  2071. } else {
  2072. rem_entries = num_entries_per_buf;
  2073. scatter_buf_num++;
  2074. if (scatter_buf_num >= num_scatter_bufs)
  2075. break;
  2076. scatter_buf_ptr = (uint8_t *)
  2077. (soc->wbm_idle_scatter_buf_base_vaddr[
  2078. scatter_buf_num]);
  2079. }
  2080. count++;
  2081. desc_id++;
  2082. }
  2083. /* Setup link descriptor idle list in HW */
  2084. hal_setup_link_idle_list(soc->hal_soc,
  2085. soc->wbm_idle_scatter_buf_base_paddr,
  2086. soc->wbm_idle_scatter_buf_base_vaddr,
  2087. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  2088. (uint32_t)(scatter_buf_ptr -
  2089. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  2090. scatter_buf_num-1])), total_link_descs);
  2091. }
  2092. }
  2093. qdf_export_symbol(dp_link_desc_ring_replenish);
  2094. #ifdef IPA_OFFLOAD
  2095. #define USE_1_IPA_RX_REO_RING 1
  2096. #define USE_2_IPA_RX_REO_RINGS 2
  2097. #define REO_DST_RING_SIZE_QCA6290 1023
  2098. #ifndef CONFIG_WIFI_EMULATION_WIFI_3_0
  2099. #define REO_DST_RING_SIZE_QCA8074 1023
  2100. #define REO_DST_RING_SIZE_QCN9000 2048
  2101. #else
  2102. #define REO_DST_RING_SIZE_QCA8074 8
  2103. #define REO_DST_RING_SIZE_QCN9000 8
  2104. #endif /* CONFIG_WIFI_EMULATION_WIFI_3_0 */
  2105. #ifdef IPA_WDI3_TX_TWO_PIPES
  2106. #ifdef DP_MEMORY_OPT
  2107. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2108. {
  2109. return dp_init_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2110. }
  2111. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2112. {
  2113. dp_deinit_tx_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2114. }
  2115. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2116. {
  2117. return dp_alloc_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2118. }
  2119. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2120. {
  2121. dp_free_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2122. }
  2123. #else /* !DP_MEMORY_OPT */
  2124. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2125. {
  2126. return 0;
  2127. }
  2128. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2129. {
  2130. }
  2131. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2132. {
  2133. return 0
  2134. }
  2135. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2136. {
  2137. }
  2138. #endif /* DP_MEMORY_OPT */
  2139. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2140. {
  2141. hal_tx_init_data_ring(soc->hal_soc,
  2142. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng);
  2143. }
  2144. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2145. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2146. {
  2147. return 0;
  2148. }
  2149. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2150. {
  2151. }
  2152. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2153. {
  2154. return 0;
  2155. }
  2156. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2157. {
  2158. }
  2159. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2160. {
  2161. }
  2162. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2163. #else
  2164. #define REO_DST_RING_SIZE_QCA6290 1024
  2165. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2166. {
  2167. return 0;
  2168. }
  2169. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2170. {
  2171. }
  2172. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2173. {
  2174. return 0;
  2175. }
  2176. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2177. {
  2178. }
  2179. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2180. {
  2181. }
  2182. #endif /* IPA_OFFLOAD */
  2183. /**
  2184. * dp_soc_reset_cpu_ring_map() - Reset cpu ring map
  2185. * @soc: Datapath soc handler
  2186. *
  2187. * This api resets the default cpu ring map
  2188. */
  2189. void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  2190. {
  2191. uint8_t i;
  2192. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2193. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  2194. switch (nss_config) {
  2195. case dp_nss_cfg_first_radio:
  2196. /*
  2197. * Setting Tx ring map for one nss offloaded radio
  2198. */
  2199. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  2200. break;
  2201. case dp_nss_cfg_second_radio:
  2202. /*
  2203. * Setting Tx ring for two nss offloaded radios
  2204. */
  2205. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  2206. break;
  2207. case dp_nss_cfg_dbdc:
  2208. /*
  2209. * Setting Tx ring map for 2 nss offloaded radios
  2210. */
  2211. soc->tx_ring_map[i] =
  2212. dp_cpu_ring_map[DP_NSS_DBDC_OFFLOADED_MAP][i];
  2213. break;
  2214. case dp_nss_cfg_dbtc:
  2215. /*
  2216. * Setting Tx ring map for 3 nss offloaded radios
  2217. */
  2218. soc->tx_ring_map[i] =
  2219. dp_cpu_ring_map[DP_NSS_DBTC_OFFLOADED_MAP][i];
  2220. break;
  2221. default:
  2222. dp_err("tx_ring_map failed due to invalid nss cfg");
  2223. break;
  2224. }
  2225. }
  2226. }
  2227. /**
  2228. * dp_soc_disable_unused_mac_intr_mask() - reset interrupt mask for
  2229. * unused WMAC hw rings
  2230. * @soc: DP Soc handle
  2231. * @mac_num: wmac num
  2232. *
  2233. * Return: Return void
  2234. */
  2235. static void dp_soc_disable_unused_mac_intr_mask(struct dp_soc *soc,
  2236. int mac_num)
  2237. {
  2238. uint8_t *grp_mask = NULL;
  2239. int group_number;
  2240. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2241. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2242. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2243. group_number, 0x0);
  2244. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  2245. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2246. wlan_cfg_set_rx_mon_ring_mask(soc->wlan_cfg_ctx,
  2247. group_number, 0x0);
  2248. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  2249. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2250. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx,
  2251. group_number, 0x0);
  2252. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  2253. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2254. wlan_cfg_set_host2rxdma_mon_ring_mask(soc->wlan_cfg_ctx,
  2255. group_number, 0x0);
  2256. }
  2257. #ifdef IPA_OFFLOAD
  2258. #ifdef IPA_WDI3_VLAN_SUPPORT
  2259. /**
  2260. * dp_soc_reset_ipa_vlan_intr_mask() - reset interrupt mask for IPA offloaded
  2261. * ring for vlan tagged traffic
  2262. * @soc: DP Soc handle
  2263. *
  2264. * Return: Return void
  2265. */
  2266. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2267. {
  2268. uint8_t *grp_mask = NULL;
  2269. int group_number, mask;
  2270. if (!wlan_ipa_is_vlan_enabled())
  2271. return;
  2272. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2273. group_number = dp_srng_find_ring_in_mask(IPA_ALT_REO_DEST_RING_IDX, grp_mask);
  2274. if (group_number < 0) {
  2275. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2276. soc, REO_DST, IPA_ALT_REO_DEST_RING_IDX);
  2277. return;
  2278. }
  2279. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2280. /* reset the interrupt mask for offloaded ring */
  2281. mask &= (~(1 << IPA_ALT_REO_DEST_RING_IDX));
  2282. /*
  2283. * set the interrupt mask to zero for rx offloaded radio.
  2284. */
  2285. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2286. }
  2287. #else
  2288. inline
  2289. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2290. { }
  2291. #endif /* IPA_WDI3_VLAN_SUPPORT */
  2292. #else
  2293. inline
  2294. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2295. { }
  2296. #endif /* IPA_OFFLOAD */
  2297. /**
  2298. * dp_soc_reset_intr_mask() - reset interrupt mask
  2299. * @soc: DP Soc handle
  2300. *
  2301. * Return: Return void
  2302. */
  2303. void dp_soc_reset_intr_mask(struct dp_soc *soc)
  2304. {
  2305. uint8_t j;
  2306. uint8_t *grp_mask = NULL;
  2307. int group_number, mask, num_ring;
  2308. /* number of tx ring */
  2309. num_ring = soc->num_tcl_data_rings;
  2310. /*
  2311. * group mask for tx completion ring.
  2312. */
  2313. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  2314. /* loop and reset the mask for only offloaded ring */
  2315. for (j = 0; j < WLAN_CFG_NUM_TCL_DATA_RINGS; j++) {
  2316. /*
  2317. * Group number corresponding to tx offloaded ring.
  2318. */
  2319. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2320. if (group_number < 0) {
  2321. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2322. soc, WBM2SW_RELEASE, j);
  2323. continue;
  2324. }
  2325. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2326. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j) &&
  2327. (!mask)) {
  2328. continue;
  2329. }
  2330. /* reset the tx mask for offloaded ring */
  2331. mask &= (~(1 << j));
  2332. /*
  2333. * reset the interrupt mask for offloaded ring.
  2334. */
  2335. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2336. }
  2337. /* number of rx rings */
  2338. num_ring = soc->num_reo_dest_rings;
  2339. /*
  2340. * group mask for reo destination ring.
  2341. */
  2342. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2343. /* loop and reset the mask for only offloaded ring */
  2344. for (j = 0; j < WLAN_CFG_NUM_REO_DEST_RING; j++) {
  2345. /*
  2346. * Group number corresponding to rx offloaded ring.
  2347. */
  2348. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2349. if (group_number < 0) {
  2350. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2351. soc, REO_DST, j);
  2352. continue;
  2353. }
  2354. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2355. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j) &&
  2356. (!mask)) {
  2357. continue;
  2358. }
  2359. /* reset the interrupt mask for offloaded ring */
  2360. mask &= (~(1 << j));
  2361. /*
  2362. * set the interrupt mask to zero for rx offloaded radio.
  2363. */
  2364. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2365. }
  2366. /*
  2367. * group mask for Rx buffer refill ring
  2368. */
  2369. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2370. /* loop and reset the mask for only offloaded ring */
  2371. for (j = 0; j < MAX_PDEV_CNT; j++) {
  2372. int lmac_id = wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  2373. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  2374. continue;
  2375. }
  2376. /*
  2377. * Group number corresponding to rx offloaded ring.
  2378. */
  2379. group_number = dp_srng_find_ring_in_mask(lmac_id, grp_mask);
  2380. if (group_number < 0) {
  2381. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2382. soc, REO_DST, lmac_id);
  2383. continue;
  2384. }
  2385. /* set the interrupt mask for offloaded ring */
  2386. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2387. group_number);
  2388. mask &= (~(1 << lmac_id));
  2389. /*
  2390. * set the interrupt mask to zero for rx offloaded radio.
  2391. */
  2392. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2393. group_number, mask);
  2394. }
  2395. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  2396. for (j = 0; j < num_ring; j++) {
  2397. if (!dp_soc_ring_if_nss_offloaded(soc, REO_EXCEPTION, j)) {
  2398. continue;
  2399. }
  2400. /*
  2401. * Group number corresponding to rx err ring.
  2402. */
  2403. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2404. if (group_number < 0) {
  2405. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2406. soc, REO_EXCEPTION, j);
  2407. continue;
  2408. }
  2409. wlan_cfg_set_rx_err_ring_mask(soc->wlan_cfg_ctx,
  2410. group_number, 0);
  2411. }
  2412. }
  2413. #ifdef IPA_OFFLOAD
  2414. bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0,
  2415. uint32_t *remap1, uint32_t *remap2)
  2416. {
  2417. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX] = {
  2418. REO_REMAP_SW1, REO_REMAP_SW2, REO_REMAP_SW3,
  2419. REO_REMAP_SW5, REO_REMAP_SW6, REO_REMAP_SW7};
  2420. switch (soc->arch_id) {
  2421. case CDP_ARCH_TYPE_BE:
  2422. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2423. soc->num_reo_dest_rings -
  2424. USE_2_IPA_RX_REO_RINGS, remap1,
  2425. remap2);
  2426. break;
  2427. case CDP_ARCH_TYPE_LI:
  2428. if (wlan_ipa_is_vlan_enabled()) {
  2429. hal_compute_reo_remap_ix2_ix3(
  2430. soc->hal_soc, ring,
  2431. soc->num_reo_dest_rings -
  2432. USE_2_IPA_RX_REO_RINGS, remap1,
  2433. remap2);
  2434. } else {
  2435. hal_compute_reo_remap_ix2_ix3(
  2436. soc->hal_soc, ring,
  2437. soc->num_reo_dest_rings -
  2438. USE_1_IPA_RX_REO_RING, remap1,
  2439. remap2);
  2440. }
  2441. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2442. break;
  2443. default:
  2444. dp_err("unknown arch_id 0x%x", soc->arch_id);
  2445. QDF_BUG(0);
  2446. }
  2447. dp_debug("remap1 %x remap2 %x", *remap1, *remap2);
  2448. return true;
  2449. }
  2450. #ifdef IPA_WDI3_TX_TWO_PIPES
  2451. static bool dp_ipa_is_alt_tx_ring(int index)
  2452. {
  2453. return index == IPA_TX_ALT_RING_IDX;
  2454. }
  2455. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2456. {
  2457. return index == IPA_TX_ALT_COMP_RING_IDX;
  2458. }
  2459. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2460. static bool dp_ipa_is_alt_tx_ring(int index)
  2461. {
  2462. return false;
  2463. }
  2464. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2465. {
  2466. return false;
  2467. }
  2468. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2469. /**
  2470. * dp_ipa_get_tx_ring_size() - Get Tx ring size for IPA
  2471. *
  2472. * @tx_ring_num: Tx ring number
  2473. * @tx_ipa_ring_sz: Return param only updated for IPA.
  2474. * @soc_cfg_ctx: dp soc cfg context
  2475. *
  2476. * Return: None
  2477. */
  2478. static void dp_ipa_get_tx_ring_size(int tx_ring_num, int *tx_ipa_ring_sz,
  2479. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2480. {
  2481. if (!soc_cfg_ctx->ipa_enabled)
  2482. return;
  2483. if (tx_ring_num == IPA_TCL_DATA_RING_IDX)
  2484. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_ring_size(soc_cfg_ctx);
  2485. else if (dp_ipa_is_alt_tx_ring(tx_ring_num))
  2486. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_alt_ring_size(soc_cfg_ctx);
  2487. }
  2488. /**
  2489. * dp_ipa_get_tx_comp_ring_size() - Get Tx comp ring size for IPA
  2490. *
  2491. * @tx_comp_ring_num: Tx comp ring number
  2492. * @tx_comp_ipa_ring_sz: Return param only updated for IPA.
  2493. * @soc_cfg_ctx: dp soc cfg context
  2494. *
  2495. * Return: None
  2496. */
  2497. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2498. int *tx_comp_ipa_ring_sz,
  2499. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2500. {
  2501. if (!soc_cfg_ctx->ipa_enabled)
  2502. return;
  2503. if (tx_comp_ring_num == IPA_TCL_DATA_RING_IDX)
  2504. *tx_comp_ipa_ring_sz =
  2505. wlan_cfg_ipa_tx_comp_ring_size(soc_cfg_ctx);
  2506. else if (dp_ipa_is_alt_tx_comp_ring(tx_comp_ring_num))
  2507. *tx_comp_ipa_ring_sz =
  2508. wlan_cfg_ipa_tx_alt_comp_ring_size(soc_cfg_ctx);
  2509. }
  2510. #else
  2511. static uint8_t dp_reo_ring_selection(uint32_t value, uint32_t *ring)
  2512. {
  2513. uint8_t num = 0;
  2514. switch (value) {
  2515. /* should we have all the different possible ring configs */
  2516. case 0xFF:
  2517. num = 8;
  2518. ring[0] = REO_REMAP_SW1;
  2519. ring[1] = REO_REMAP_SW2;
  2520. ring[2] = REO_REMAP_SW3;
  2521. ring[3] = REO_REMAP_SW4;
  2522. ring[4] = REO_REMAP_SW5;
  2523. ring[5] = REO_REMAP_SW6;
  2524. ring[6] = REO_REMAP_SW7;
  2525. ring[7] = REO_REMAP_SW8;
  2526. break;
  2527. case 0x3F:
  2528. num = 6;
  2529. ring[0] = REO_REMAP_SW1;
  2530. ring[1] = REO_REMAP_SW2;
  2531. ring[2] = REO_REMAP_SW3;
  2532. ring[3] = REO_REMAP_SW4;
  2533. ring[4] = REO_REMAP_SW5;
  2534. ring[5] = REO_REMAP_SW6;
  2535. break;
  2536. case 0xF:
  2537. num = 4;
  2538. ring[0] = REO_REMAP_SW1;
  2539. ring[1] = REO_REMAP_SW2;
  2540. ring[2] = REO_REMAP_SW3;
  2541. ring[3] = REO_REMAP_SW4;
  2542. break;
  2543. case 0xE:
  2544. num = 3;
  2545. ring[0] = REO_REMAP_SW2;
  2546. ring[1] = REO_REMAP_SW3;
  2547. ring[2] = REO_REMAP_SW4;
  2548. break;
  2549. case 0xD:
  2550. num = 3;
  2551. ring[0] = REO_REMAP_SW1;
  2552. ring[1] = REO_REMAP_SW3;
  2553. ring[2] = REO_REMAP_SW4;
  2554. break;
  2555. case 0xC:
  2556. num = 2;
  2557. ring[0] = REO_REMAP_SW3;
  2558. ring[1] = REO_REMAP_SW4;
  2559. break;
  2560. case 0xB:
  2561. num = 3;
  2562. ring[0] = REO_REMAP_SW1;
  2563. ring[1] = REO_REMAP_SW2;
  2564. ring[2] = REO_REMAP_SW4;
  2565. break;
  2566. case 0xA:
  2567. num = 2;
  2568. ring[0] = REO_REMAP_SW2;
  2569. ring[1] = REO_REMAP_SW4;
  2570. break;
  2571. case 0x9:
  2572. num = 2;
  2573. ring[0] = REO_REMAP_SW1;
  2574. ring[1] = REO_REMAP_SW4;
  2575. break;
  2576. case 0x8:
  2577. num = 1;
  2578. ring[0] = REO_REMAP_SW4;
  2579. break;
  2580. case 0x7:
  2581. num = 3;
  2582. ring[0] = REO_REMAP_SW1;
  2583. ring[1] = REO_REMAP_SW2;
  2584. ring[2] = REO_REMAP_SW3;
  2585. break;
  2586. case 0x6:
  2587. num = 2;
  2588. ring[0] = REO_REMAP_SW2;
  2589. ring[1] = REO_REMAP_SW3;
  2590. break;
  2591. case 0x5:
  2592. num = 2;
  2593. ring[0] = REO_REMAP_SW1;
  2594. ring[1] = REO_REMAP_SW3;
  2595. break;
  2596. case 0x4:
  2597. num = 1;
  2598. ring[0] = REO_REMAP_SW3;
  2599. break;
  2600. case 0x3:
  2601. num = 2;
  2602. ring[0] = REO_REMAP_SW1;
  2603. ring[1] = REO_REMAP_SW2;
  2604. break;
  2605. case 0x2:
  2606. num = 1;
  2607. ring[0] = REO_REMAP_SW2;
  2608. break;
  2609. case 0x1:
  2610. num = 1;
  2611. ring[0] = REO_REMAP_SW1;
  2612. break;
  2613. default:
  2614. dp_err("unknown reo ring map 0x%x", value);
  2615. QDF_BUG(0);
  2616. }
  2617. return num;
  2618. }
  2619. bool dp_reo_remap_config(struct dp_soc *soc,
  2620. uint32_t *remap0,
  2621. uint32_t *remap1,
  2622. uint32_t *remap2)
  2623. {
  2624. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2625. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2626. uint8_t num;
  2627. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX];
  2628. uint32_t value;
  2629. switch (offload_radio) {
  2630. case dp_nss_cfg_default:
  2631. value = reo_config & WLAN_CFG_NUM_REO_RINGS_MAP_MAX;
  2632. num = dp_reo_ring_selection(value, ring);
  2633. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2634. num, remap1, remap2);
  2635. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2636. break;
  2637. case dp_nss_cfg_first_radio:
  2638. value = reo_config & 0xE;
  2639. num = dp_reo_ring_selection(value, ring);
  2640. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2641. num, remap1, remap2);
  2642. break;
  2643. case dp_nss_cfg_second_radio:
  2644. value = reo_config & 0xD;
  2645. num = dp_reo_ring_selection(value, ring);
  2646. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2647. num, remap1, remap2);
  2648. break;
  2649. case dp_nss_cfg_dbdc:
  2650. case dp_nss_cfg_dbtc:
  2651. /* return false if both or all are offloaded to NSS */
  2652. return false;
  2653. }
  2654. dp_debug("remap1 %x remap2 %x offload_radio %u",
  2655. *remap1, *remap2, offload_radio);
  2656. return true;
  2657. }
  2658. static void dp_ipa_get_tx_ring_size(int ring_num, int *tx_ipa_ring_sz,
  2659. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2660. {
  2661. }
  2662. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2663. int *tx_comp_ipa_ring_sz,
  2664. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2665. {
  2666. }
  2667. #endif /* IPA_OFFLOAD */
  2668. /**
  2669. * dp_reo_frag_dst_set() - configure reo register to set the
  2670. * fragment destination ring
  2671. * @soc: Datapath soc
  2672. * @frag_dst_ring: output parameter to set fragment destination ring
  2673. *
  2674. * Based on offload_radio below fragment destination rings is selected
  2675. * 0 - TCL
  2676. * 1 - SW1
  2677. * 2 - SW2
  2678. * 3 - SW3
  2679. * 4 - SW4
  2680. * 5 - Release
  2681. * 6 - FW
  2682. * 7 - alternate select
  2683. *
  2684. * Return: void
  2685. */
  2686. void dp_reo_frag_dst_set(struct dp_soc *soc, uint8_t *frag_dst_ring)
  2687. {
  2688. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2689. switch (offload_radio) {
  2690. case dp_nss_cfg_default:
  2691. *frag_dst_ring = REO_REMAP_TCL;
  2692. break;
  2693. case dp_nss_cfg_first_radio:
  2694. /*
  2695. * This configuration is valid for single band radio which
  2696. * is also NSS offload.
  2697. */
  2698. case dp_nss_cfg_dbdc:
  2699. case dp_nss_cfg_dbtc:
  2700. *frag_dst_ring = HAL_SRNG_REO_ALTERNATE_SELECT;
  2701. break;
  2702. default:
  2703. dp_init_err("%pK: dp_reo_frag_dst_set invalid offload radio config", soc);
  2704. break;
  2705. }
  2706. }
  2707. #ifdef WLAN_FEATURE_STATS_EXT
  2708. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2709. {
  2710. qdf_event_create(&soc->rx_hw_stats_event);
  2711. }
  2712. #else
  2713. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2714. {
  2715. }
  2716. #endif
  2717. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index)
  2718. {
  2719. int tcl_ring_num, wbm_ring_num;
  2720. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2721. index,
  2722. &tcl_ring_num,
  2723. &wbm_ring_num);
  2724. if (tcl_ring_num == -1) {
  2725. dp_err("incorrect tcl ring num for index %u", index);
  2726. return;
  2727. }
  2728. wlan_minidump_remove(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2729. soc->tcl_data_ring[index].alloc_size,
  2730. soc->ctrl_psoc,
  2731. WLAN_MD_DP_SRNG_TCL_DATA,
  2732. "tcl_data_ring");
  2733. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2734. dp_srng_deinit(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2735. tcl_ring_num);
  2736. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2737. return;
  2738. wlan_minidump_remove(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2739. soc->tx_comp_ring[index].alloc_size,
  2740. soc->ctrl_psoc,
  2741. WLAN_MD_DP_SRNG_TX_COMP,
  2742. "tcl_comp_ring");
  2743. dp_srng_deinit(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2744. wbm_ring_num);
  2745. }
  2746. /**
  2747. * dp_init_tx_ring_pair_by_index() - The function inits tcl data/wbm completion
  2748. * ring pair
  2749. * @soc: DP soc pointer
  2750. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2751. *
  2752. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2753. */
  2754. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  2755. uint8_t index)
  2756. {
  2757. int tcl_ring_num, wbm_ring_num;
  2758. uint8_t bm_id;
  2759. if (index >= MAX_TCL_DATA_RINGS) {
  2760. dp_err("unexpected index!");
  2761. QDF_BUG(0);
  2762. goto fail1;
  2763. }
  2764. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2765. index,
  2766. &tcl_ring_num,
  2767. &wbm_ring_num);
  2768. if (tcl_ring_num == -1) {
  2769. dp_err("incorrect tcl ring num for index %u", index);
  2770. goto fail1;
  2771. }
  2772. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2773. if (dp_srng_init(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2774. tcl_ring_num, 0)) {
  2775. dp_err("dp_srng_init failed for tcl_data_ring");
  2776. goto fail1;
  2777. }
  2778. wlan_minidump_log(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2779. soc->tcl_data_ring[index].alloc_size,
  2780. soc->ctrl_psoc,
  2781. WLAN_MD_DP_SRNG_TCL_DATA,
  2782. "tcl_data_ring");
  2783. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2784. goto set_rbm;
  2785. if (dp_srng_init(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2786. wbm_ring_num, 0)) {
  2787. dp_err("dp_srng_init failed for tx_comp_ring");
  2788. goto fail1;
  2789. }
  2790. wlan_minidump_log(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2791. soc->tx_comp_ring[index].alloc_size,
  2792. soc->ctrl_psoc,
  2793. WLAN_MD_DP_SRNG_TX_COMP,
  2794. "tcl_comp_ring");
  2795. set_rbm:
  2796. bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_ring_num);
  2797. soc->arch_ops.tx_implicit_rbm_set(soc, tcl_ring_num, bm_id);
  2798. return QDF_STATUS_SUCCESS;
  2799. fail1:
  2800. return QDF_STATUS_E_FAILURE;
  2801. }
  2802. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index)
  2803. {
  2804. dp_debug("index %u", index);
  2805. dp_srng_free(soc, &soc->tcl_data_ring[index]);
  2806. dp_srng_free(soc, &soc->tx_comp_ring[index]);
  2807. }
  2808. /**
  2809. * dp_alloc_tx_ring_pair_by_index() - The function allocs tcl data/wbm2sw
  2810. * ring pair for the given "index"
  2811. * @soc: DP soc pointer
  2812. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2813. *
  2814. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2815. */
  2816. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  2817. uint8_t index)
  2818. {
  2819. int tx_ring_size;
  2820. int tx_comp_ring_size;
  2821. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  2822. int cached = 0;
  2823. if (index >= MAX_TCL_DATA_RINGS) {
  2824. dp_err("unexpected index!");
  2825. QDF_BUG(0);
  2826. goto fail1;
  2827. }
  2828. dp_debug("index %u", index);
  2829. tx_ring_size = wlan_cfg_tx_ring_size(soc_cfg_ctx);
  2830. dp_ipa_get_tx_ring_size(index, &tx_ring_size, soc_cfg_ctx);
  2831. if (dp_srng_alloc(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2832. tx_ring_size, cached)) {
  2833. dp_err("dp_srng_alloc failed for tcl_data_ring");
  2834. goto fail1;
  2835. }
  2836. tx_comp_ring_size = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  2837. dp_ipa_get_tx_comp_ring_size(index, &tx_comp_ring_size, soc_cfg_ctx);
  2838. /* Enable cached TCL desc if NSS offload is disabled */
  2839. if (!wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  2840. cached = WLAN_CFG_DST_RING_CACHED_DESC;
  2841. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) ==
  2842. INVALID_WBM_RING_NUM)
  2843. return QDF_STATUS_SUCCESS;
  2844. if (dp_srng_alloc(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2845. tx_comp_ring_size, cached)) {
  2846. dp_err("dp_srng_alloc failed for tx_comp_ring");
  2847. goto fail1;
  2848. }
  2849. return QDF_STATUS_SUCCESS;
  2850. fail1:
  2851. return QDF_STATUS_E_FAILURE;
  2852. }
  2853. /**
  2854. * dp_dscp_tid_map_setup() - Initialize the dscp-tid maps
  2855. * @pdev: DP_PDEV handle
  2856. *
  2857. * Return: void
  2858. */
  2859. void
  2860. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  2861. {
  2862. uint8_t map_id;
  2863. struct dp_soc *soc = pdev->soc;
  2864. if (!soc)
  2865. return;
  2866. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  2867. qdf_mem_copy(pdev->dscp_tid_map[map_id],
  2868. default_dscp_tid_map,
  2869. sizeof(default_dscp_tid_map));
  2870. }
  2871. for (map_id = 0; map_id < soc->num_hw_dscp_tid_map; map_id++) {
  2872. hal_tx_set_dscp_tid_map(soc->hal_soc,
  2873. default_dscp_tid_map,
  2874. map_id);
  2875. }
  2876. }
  2877. /**
  2878. * dp_pcp_tid_map_setup() - Initialize the pcp-tid maps
  2879. * @pdev: DP_PDEV handle
  2880. *
  2881. * Return: void
  2882. */
  2883. void
  2884. dp_pcp_tid_map_setup(struct dp_pdev *pdev)
  2885. {
  2886. struct dp_soc *soc = pdev->soc;
  2887. if (!soc)
  2888. return;
  2889. qdf_mem_copy(soc->pcp_tid_map, default_pcp_tid_map,
  2890. sizeof(default_pcp_tid_map));
  2891. hal_tx_set_pcp_tid_map_default(soc->hal_soc, default_pcp_tid_map);
  2892. }
  2893. #ifndef DP_UMAC_HW_RESET_SUPPORT
  2894. static inline
  2895. #endif
  2896. void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2897. {
  2898. struct reo_desc_list_node *desc;
  2899. struct dp_rx_tid *rx_tid;
  2900. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2901. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2902. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2903. rx_tid = &desc->rx_tid;
  2904. qdf_mem_unmap_nbytes_single(soc->osdev,
  2905. rx_tid->hw_qdesc_paddr,
  2906. QDF_DMA_BIDIRECTIONAL,
  2907. rx_tid->hw_qdesc_alloc_size);
  2908. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2909. qdf_mem_free(desc);
  2910. }
  2911. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2912. qdf_list_destroy(&soc->reo_desc_freelist);
  2913. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2914. }
  2915. #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY
  2916. /**
  2917. * dp_reo_desc_deferred_freelist_create() - Initialize the resources used
  2918. * for deferred reo desc list
  2919. * @soc: Datapath soc handle
  2920. *
  2921. * Return: void
  2922. */
  2923. static void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2924. {
  2925. qdf_spinlock_create(&soc->reo_desc_deferred_freelist_lock);
  2926. qdf_list_create(&soc->reo_desc_deferred_freelist,
  2927. REO_DESC_DEFERRED_FREELIST_SIZE);
  2928. soc->reo_desc_deferred_freelist_init = true;
  2929. }
  2930. /**
  2931. * dp_reo_desc_deferred_freelist_destroy() - loop the deferred free list &
  2932. * free the leftover REO QDESCs
  2933. * @soc: Datapath soc handle
  2934. *
  2935. * Return: void
  2936. */
  2937. static void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2938. {
  2939. struct reo_desc_deferred_freelist_node *desc;
  2940. qdf_spin_lock_bh(&soc->reo_desc_deferred_freelist_lock);
  2941. soc->reo_desc_deferred_freelist_init = false;
  2942. while (qdf_list_remove_front(&soc->reo_desc_deferred_freelist,
  2943. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2944. qdf_mem_unmap_nbytes_single(soc->osdev,
  2945. desc->hw_qdesc_paddr,
  2946. QDF_DMA_BIDIRECTIONAL,
  2947. desc->hw_qdesc_alloc_size);
  2948. qdf_mem_free(desc->hw_qdesc_vaddr_unaligned);
  2949. qdf_mem_free(desc);
  2950. }
  2951. qdf_spin_unlock_bh(&soc->reo_desc_deferred_freelist_lock);
  2952. qdf_list_destroy(&soc->reo_desc_deferred_freelist);
  2953. qdf_spinlock_destroy(&soc->reo_desc_deferred_freelist_lock);
  2954. }
  2955. #else
  2956. static inline void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2957. {
  2958. }
  2959. static inline void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2960. {
  2961. }
  2962. #endif /* !WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */
  2963. /**
  2964. * dp_soc_reset_txrx_ring_map() - reset tx ring map
  2965. * @soc: DP SOC handle
  2966. *
  2967. */
  2968. static void dp_soc_reset_txrx_ring_map(struct dp_soc *soc)
  2969. {
  2970. uint32_t i;
  2971. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++)
  2972. soc->tx_ring_map[i] = 0;
  2973. }
  2974. /**
  2975. * dp_soc_deinit() - Deinitialize txrx SOC
  2976. * @txrx_soc: Opaque DP SOC handle
  2977. *
  2978. * Return: None
  2979. */
  2980. void dp_soc_deinit(void *txrx_soc)
  2981. {
  2982. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2983. struct htt_soc *htt_soc = soc->htt_handle;
  2984. dp_monitor_soc_deinit(soc);
  2985. /* free peer tables & AST tables allocated during peer_map_attach */
  2986. if (soc->peer_map_attach_success) {
  2987. dp_peer_find_detach(soc);
  2988. soc->arch_ops.txrx_peer_map_detach(soc);
  2989. soc->peer_map_attach_success = FALSE;
  2990. }
  2991. qdf_flush_work(&soc->htt_stats.work);
  2992. qdf_disable_work(&soc->htt_stats.work);
  2993. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2994. dp_soc_reset_txrx_ring_map(soc);
  2995. dp_reo_desc_freelist_destroy(soc);
  2996. dp_reo_desc_deferred_freelist_destroy(soc);
  2997. DEINIT_RX_HW_STATS_LOCK(soc);
  2998. qdf_spinlock_destroy(&soc->ast_lock);
  2999. dp_peer_mec_spinlock_destroy(soc);
  3000. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  3001. qdf_nbuf_queue_free(&soc->invalid_buf_queue);
  3002. qdf_spinlock_destroy(&soc->rx.defrag.defrag_lock);
  3003. qdf_spinlock_destroy(&soc->vdev_map_lock);
  3004. dp_reo_cmdlist_destroy(soc);
  3005. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  3006. dp_soc_tx_desc_sw_pools_deinit(soc);
  3007. dp_soc_srng_deinit(soc);
  3008. dp_hw_link_desc_ring_deinit(soc);
  3009. dp_soc_print_inactive_objects(soc);
  3010. qdf_spinlock_destroy(&soc->inactive_peer_list_lock);
  3011. qdf_spinlock_destroy(&soc->inactive_vdev_list_lock);
  3012. htt_soc_htc_dealloc(soc->htt_handle);
  3013. htt_soc_detach(htt_soc);
  3014. /* Free wbm sg list and reset flags in down path */
  3015. dp_rx_wbm_sg_list_deinit(soc);
  3016. wlan_minidump_remove(soc, sizeof(*soc), soc->ctrl_psoc,
  3017. WLAN_MD_DP_SOC, "dp_soc");
  3018. }
  3019. #ifdef QCA_HOST2FW_RXBUF_RING
  3020. void
  3021. dp_htt_setup_rxdma_err_dst_ring(struct dp_soc *soc, int mac_id,
  3022. int lmac_id)
  3023. {
  3024. if (soc->rxdma_err_dst_ring[lmac_id].hal_srng)
  3025. htt_srng_setup(soc->htt_handle, mac_id,
  3026. soc->rxdma_err_dst_ring[lmac_id].hal_srng,
  3027. RXDMA_DST);
  3028. }
  3029. #endif
  3030. void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev,
  3031. enum cdp_host_reo_dest_ring *reo_dest,
  3032. bool *hash_based)
  3033. {
  3034. struct dp_soc *soc;
  3035. struct dp_pdev *pdev;
  3036. pdev = vdev->pdev;
  3037. soc = pdev->soc;
  3038. /*
  3039. * hash based steering is disabled for Radios which are offloaded
  3040. * to NSS
  3041. */
  3042. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  3043. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  3044. /*
  3045. * Below line of code will ensure the proper reo_dest ring is chosen
  3046. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  3047. */
  3048. *reo_dest = pdev->reo_dest;
  3049. }
  3050. #ifdef IPA_OFFLOAD
  3051. /**
  3052. * dp_is_vdev_subtype_p2p() - Check if the subtype for vdev is P2P
  3053. * @vdev: Virtual device
  3054. *
  3055. * Return: true if the vdev is of subtype P2P
  3056. * false if the vdev is of any other subtype
  3057. */
  3058. static inline bool dp_is_vdev_subtype_p2p(struct dp_vdev *vdev)
  3059. {
  3060. if (vdev->subtype == wlan_op_subtype_p2p_device ||
  3061. vdev->subtype == wlan_op_subtype_p2p_cli ||
  3062. vdev->subtype == wlan_op_subtype_p2p_go)
  3063. return true;
  3064. return false;
  3065. }
  3066. /**
  3067. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3068. * @vdev: Datapath VDEV handle
  3069. * @setup_info:
  3070. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3071. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3072. * @lmac_peer_id_msb:
  3073. *
  3074. * If IPA is enabled in ini, for SAP mode, disable hash based
  3075. * steering, use default reo_dst ring for RX. Use config values for other modes.
  3076. *
  3077. * Return: None
  3078. */
  3079. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3080. struct cdp_peer_setup_info *setup_info,
  3081. enum cdp_host_reo_dest_ring *reo_dest,
  3082. bool *hash_based,
  3083. uint8_t *lmac_peer_id_msb)
  3084. {
  3085. struct dp_soc *soc;
  3086. struct dp_pdev *pdev;
  3087. pdev = vdev->pdev;
  3088. soc = pdev->soc;
  3089. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  3090. /* For P2P-GO interfaces we do not need to change the REO
  3091. * configuration even if IPA config is enabled
  3092. */
  3093. if (dp_is_vdev_subtype_p2p(vdev))
  3094. return;
  3095. /*
  3096. * If IPA is enabled, disable hash-based flow steering and set
  3097. * reo_dest_ring_4 as the REO ring to receive packets on.
  3098. * IPA is configured to reap reo_dest_ring_4.
  3099. *
  3100. * Note - REO DST indexes are from 0 - 3, while cdp_host_reo_dest_ring
  3101. * value enum value is from 1 - 4.
  3102. * Hence, *reo_dest = IPA_REO_DEST_RING_IDX + 1
  3103. */
  3104. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  3105. if (dp_ipa_is_mdm_platform()) {
  3106. *reo_dest = IPA_REO_DEST_RING_IDX + 1;
  3107. if (vdev->opmode == wlan_op_mode_ap)
  3108. *hash_based = 0;
  3109. } else {
  3110. dp_debug("opt_dp: default HOST reo ring is set");
  3111. }
  3112. }
  3113. }
  3114. #else
  3115. /**
  3116. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3117. * @vdev: Datapath VDEV handle
  3118. * @setup_info:
  3119. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3120. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3121. * @lmac_peer_id_msb:
  3122. *
  3123. * Use system config values for hash based steering.
  3124. * Return: None
  3125. */
  3126. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3127. struct cdp_peer_setup_info *setup_info,
  3128. enum cdp_host_reo_dest_ring *reo_dest,
  3129. bool *hash_based,
  3130. uint8_t *lmac_peer_id_msb)
  3131. {
  3132. struct dp_soc *soc = vdev->pdev->soc;
  3133. soc->arch_ops.peer_get_reo_hash(vdev, setup_info, reo_dest, hash_based,
  3134. lmac_peer_id_msb);
  3135. }
  3136. #endif /* IPA_OFFLOAD */
  3137. /**
  3138. * dp_peer_setup_wifi3() - initialize the peer
  3139. * @soc_hdl: soc handle object
  3140. * @vdev_id: vdev_id of vdev object
  3141. * @peer_mac: Peer's mac address
  3142. * @setup_info: peer setup info for MLO
  3143. *
  3144. * Return: QDF_STATUS
  3145. */
  3146. QDF_STATUS
  3147. dp_peer_setup_wifi3(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3148. uint8_t *peer_mac,
  3149. struct cdp_peer_setup_info *setup_info)
  3150. {
  3151. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3152. struct dp_pdev *pdev;
  3153. bool hash_based = 0;
  3154. enum cdp_host_reo_dest_ring reo_dest;
  3155. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3156. struct dp_vdev *vdev = NULL;
  3157. struct dp_peer *peer =
  3158. dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id,
  3159. DP_MOD_ID_CDP);
  3160. struct dp_peer *mld_peer = NULL;
  3161. enum wlan_op_mode vdev_opmode;
  3162. uint8_t lmac_peer_id_msb = 0;
  3163. if (!peer)
  3164. return QDF_STATUS_E_FAILURE;
  3165. vdev = peer->vdev;
  3166. if (!vdev) {
  3167. status = QDF_STATUS_E_FAILURE;
  3168. goto fail;
  3169. }
  3170. /* save vdev related member in case vdev freed */
  3171. vdev_opmode = vdev->opmode;
  3172. pdev = vdev->pdev;
  3173. dp_peer_setup_get_reo_hash(vdev, setup_info,
  3174. &reo_dest, &hash_based,
  3175. &lmac_peer_id_msb);
  3176. dp_cfg_event_record_peer_setup_evt(soc, DP_CFG_EVENT_PEER_SETUP,
  3177. peer, vdev, vdev->vdev_id,
  3178. setup_info);
  3179. dp_info("pdev: %d vdev :%d opmode:%u peer %pK (" QDF_MAC_ADDR_FMT ") "
  3180. "hash-based-steering:%d default-reo_dest:%u",
  3181. pdev->pdev_id, vdev->vdev_id,
  3182. vdev->opmode, peer,
  3183. QDF_MAC_ADDR_REF(peer->mac_addr.raw), hash_based, reo_dest);
  3184. /*
  3185. * There are corner cases where the AD1 = AD2 = "VAPs address"
  3186. * i.e both the devices have same MAC address. In these
  3187. * cases we want such pkts to be processed in NULL Q handler
  3188. * which is REO2TCL ring. for this reason we should
  3189. * not setup reo_queues and default route for bss_peer.
  3190. */
  3191. if (!IS_MLO_DP_MLD_PEER(peer))
  3192. dp_monitor_peer_tx_init(pdev, peer);
  3193. if (!setup_info)
  3194. if (dp_peer_legacy_setup(soc, peer) !=
  3195. QDF_STATUS_SUCCESS) {
  3196. status = QDF_STATUS_E_RESOURCES;
  3197. goto fail;
  3198. }
  3199. if (peer->bss_peer && vdev->opmode == wlan_op_mode_ap) {
  3200. status = QDF_STATUS_E_FAILURE;
  3201. goto fail;
  3202. }
  3203. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  3204. /* TODO: Check the destination ring number to be passed to FW */
  3205. soc->cdp_soc.ol_ops->peer_set_default_routing(
  3206. soc->ctrl_psoc,
  3207. peer->vdev->pdev->pdev_id,
  3208. peer->mac_addr.raw,
  3209. peer->vdev->vdev_id, hash_based, reo_dest,
  3210. lmac_peer_id_msb);
  3211. }
  3212. qdf_atomic_set(&peer->is_default_route_set, 1);
  3213. status = dp_peer_mlo_setup(soc, peer, vdev->vdev_id, setup_info);
  3214. if (QDF_IS_STATUS_ERROR(status)) {
  3215. dp_peer_err("peer mlo setup failed");
  3216. qdf_assert_always(0);
  3217. }
  3218. if (vdev_opmode != wlan_op_mode_monitor) {
  3219. /* In case of MLD peer, switch peer to mld peer and
  3220. * do peer_rx_init.
  3221. */
  3222. if (hal_reo_shared_qaddr_is_enable(soc->hal_soc) &&
  3223. IS_MLO_DP_LINK_PEER(peer)) {
  3224. if (setup_info && setup_info->is_first_link) {
  3225. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  3226. if (mld_peer)
  3227. dp_peer_rx_init(pdev, mld_peer);
  3228. else
  3229. dp_peer_err("MLD peer null. Primary link peer:%pK", peer);
  3230. }
  3231. } else {
  3232. dp_peer_rx_init(pdev, peer);
  3233. }
  3234. }
  3235. if (!IS_MLO_DP_MLD_PEER(peer))
  3236. dp_peer_ppdu_delayed_ba_init(peer);
  3237. fail:
  3238. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3239. return status;
  3240. }
  3241. /**
  3242. * dp_set_ba_aging_timeout() - set ba aging timeout per AC
  3243. * @txrx_soc: cdp soc handle
  3244. * @ac: Access category
  3245. * @value: timeout value in millisec
  3246. *
  3247. * Return: void
  3248. */
  3249. void dp_set_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3250. uint8_t ac, uint32_t value)
  3251. {
  3252. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3253. hal_set_ba_aging_timeout(soc->hal_soc, ac, value);
  3254. }
  3255. /**
  3256. * dp_get_ba_aging_timeout() - get ba aging timeout per AC
  3257. * @txrx_soc: cdp soc handle
  3258. * @ac: access category
  3259. * @value: timeout value in millisec
  3260. *
  3261. * Return: void
  3262. */
  3263. void dp_get_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3264. uint8_t ac, uint32_t *value)
  3265. {
  3266. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3267. hal_get_ba_aging_timeout(soc->hal_soc, ac, value);
  3268. }
  3269. /**
  3270. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  3271. * @txrx_soc: cdp soc handle
  3272. * @pdev_id: id of physical device object
  3273. * @val: reo destination ring index (1 - 4)
  3274. *
  3275. * Return: QDF_STATUS
  3276. */
  3277. QDF_STATUS
  3278. dp_set_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id,
  3279. enum cdp_host_reo_dest_ring val)
  3280. {
  3281. struct dp_pdev *pdev =
  3282. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3283. pdev_id);
  3284. if (pdev) {
  3285. pdev->reo_dest = val;
  3286. return QDF_STATUS_SUCCESS;
  3287. }
  3288. return QDF_STATUS_E_FAILURE;
  3289. }
  3290. /**
  3291. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  3292. * @txrx_soc: cdp soc handle
  3293. * @pdev_id: id of physical device object
  3294. *
  3295. * Return: reo destination ring index
  3296. */
  3297. enum cdp_host_reo_dest_ring
  3298. dp_get_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id)
  3299. {
  3300. struct dp_pdev *pdev =
  3301. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3302. pdev_id);
  3303. if (pdev)
  3304. return pdev->reo_dest;
  3305. else
  3306. return cdp_host_reo_dest_ring_unknown;
  3307. }
  3308. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3309. union hal_reo_status *reo_status)
  3310. {
  3311. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3312. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3313. if (!dp_check_pdev_exists(soc, pdev)) {
  3314. dp_err_rl("pdev doesn't exist");
  3315. return;
  3316. }
  3317. if (!qdf_atomic_read(&soc->cmn_init_done))
  3318. return;
  3319. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3320. DP_PRINT_STATS("REO stats failure %d",
  3321. queue_status->header.status);
  3322. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3323. return;
  3324. }
  3325. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3326. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3327. }
  3328. /**
  3329. * dp_dump_wbm_idle_hptp() - dump wbm idle ring, hw hp tp info.
  3330. * @soc: dp soc.
  3331. * @pdev: dp pdev.
  3332. *
  3333. * Return: None.
  3334. */
  3335. void
  3336. dp_dump_wbm_idle_hptp(struct dp_soc *soc, struct dp_pdev *pdev)
  3337. {
  3338. uint32_t hw_head;
  3339. uint32_t hw_tail;
  3340. struct dp_srng *srng;
  3341. if (!soc) {
  3342. dp_err("soc is NULL");
  3343. return;
  3344. }
  3345. if (!pdev) {
  3346. dp_err("pdev is NULL");
  3347. return;
  3348. }
  3349. srng = &pdev->soc->wbm_idle_link_ring;
  3350. if (!srng) {
  3351. dp_err("wbm_idle_link_ring srng is NULL");
  3352. return;
  3353. }
  3354. hal_get_hw_hptp(soc->hal_soc, srng->hal_srng, &hw_head,
  3355. &hw_tail, WBM_IDLE_LINK);
  3356. dp_debug("WBM_IDLE_LINK: HW hp: %d, HW tp: %d",
  3357. hw_head, hw_tail);
  3358. }
  3359. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3360. static void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3361. uint32_t rx_limit)
  3362. {
  3363. soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit = tx_limit;
  3364. soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit = rx_limit;
  3365. }
  3366. #else
  3367. static inline
  3368. void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3369. uint32_t rx_limit)
  3370. {
  3371. }
  3372. #endif /* WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT */
  3373. /**
  3374. * dp_display_srng_info() - Dump the srng HP TP info
  3375. * @soc_hdl: CDP Soc handle
  3376. *
  3377. * This function dumps the SW hp/tp values for the important rings.
  3378. * HW hp/tp values are not being dumped, since it can lead to
  3379. * READ NOC error when UMAC is in low power state. MCC does not have
  3380. * device force wake working yet.
  3381. *
  3382. * Return: none
  3383. */
  3384. void dp_display_srng_info(struct cdp_soc_t *soc_hdl)
  3385. {
  3386. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3387. hal_soc_handle_t hal_soc = soc->hal_soc;
  3388. uint32_t hp, tp, i;
  3389. dp_info("SRNG HP-TP data:");
  3390. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3391. hal_get_sw_hptp(hal_soc, soc->tcl_data_ring[i].hal_srng,
  3392. &tp, &hp);
  3393. dp_info("TCL DATA ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3394. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, i) ==
  3395. INVALID_WBM_RING_NUM)
  3396. continue;
  3397. hal_get_sw_hptp(hal_soc, soc->tx_comp_ring[i].hal_srng,
  3398. &tp, &hp);
  3399. dp_info("TX comp ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3400. }
  3401. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  3402. hal_get_sw_hptp(hal_soc, soc->reo_dest_ring[i].hal_srng,
  3403. &tp, &hp);
  3404. dp_info("REO DST ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3405. }
  3406. hal_get_sw_hptp(hal_soc, soc->reo_exception_ring.hal_srng, &tp, &hp);
  3407. dp_info("REO exception ring: hp=0x%x, tp=0x%x", hp, tp);
  3408. hal_get_sw_hptp(hal_soc, soc->rx_rel_ring.hal_srng, &tp, &hp);
  3409. dp_info("WBM RX release ring: hp=0x%x, tp=0x%x", hp, tp);
  3410. hal_get_sw_hptp(hal_soc, soc->wbm_desc_rel_ring.hal_srng, &tp, &hp);
  3411. dp_info("WBM desc release ring: hp=0x%x, tp=0x%x", hp, tp);
  3412. }
  3413. /**
  3414. * dp_set_pdev_pcp_tid_map_wifi3() - update pcp tid map in pdev
  3415. * @psoc: dp soc handle
  3416. * @pdev_id: id of DP_PDEV handle
  3417. * @pcp: pcp value
  3418. * @tid: tid value passed by the user
  3419. *
  3420. * Return: QDF_STATUS_SUCCESS on success
  3421. */
  3422. QDF_STATUS dp_set_pdev_pcp_tid_map_wifi3(ol_txrx_soc_handle psoc,
  3423. uint8_t pdev_id,
  3424. uint8_t pcp, uint8_t tid)
  3425. {
  3426. struct dp_soc *soc = (struct dp_soc *)psoc;
  3427. soc->pcp_tid_map[pcp] = tid;
  3428. hal_tx_update_pcp_tid_map(soc->hal_soc, pcp, tid);
  3429. return QDF_STATUS_SUCCESS;
  3430. }
  3431. /**
  3432. * dp_set_vdev_pcp_tid_map_wifi3() - update pcp tid map in vdev
  3433. * @soc_hdl: DP soc handle
  3434. * @vdev_id: id of DP_VDEV handle
  3435. * @pcp: pcp value
  3436. * @tid: tid value passed by the user
  3437. *
  3438. * Return: QDF_STATUS_SUCCESS on success
  3439. */
  3440. QDF_STATUS dp_set_vdev_pcp_tid_map_wifi3(struct cdp_soc_t *soc_hdl,
  3441. uint8_t vdev_id,
  3442. uint8_t pcp, uint8_t tid)
  3443. {
  3444. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3445. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3446. DP_MOD_ID_CDP);
  3447. if (!vdev)
  3448. return QDF_STATUS_E_FAILURE;
  3449. vdev->pcp_tid_map[pcp] = tid;
  3450. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3451. return QDF_STATUS_SUCCESS;
  3452. }
  3453. #if defined(FEATURE_RUNTIME_PM) || defined(DP_POWER_SAVE)
  3454. void dp_drain_txrx(struct cdp_soc_t *soc_handle)
  3455. {
  3456. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  3457. uint32_t cur_tx_limit, cur_rx_limit;
  3458. uint32_t budget = 0xffff;
  3459. uint32_t val;
  3460. int i;
  3461. int cpu = dp_srng_get_cpu();
  3462. cur_tx_limit = soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit;
  3463. cur_rx_limit = soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit;
  3464. /* Temporarily increase soft irq limits when going to drain
  3465. * the UMAC/LMAC SRNGs and restore them after polling.
  3466. * Though the budget is on higher side, the TX/RX reaping loops
  3467. * will not execute longer as both TX and RX would be suspended
  3468. * by the time this API is called.
  3469. */
  3470. dp_update_soft_irq_limits(soc, budget, budget);
  3471. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  3472. dp_service_srngs(&soc->intr_ctx[i], budget, cpu);
  3473. dp_update_soft_irq_limits(soc, cur_tx_limit, cur_rx_limit);
  3474. /* Do a dummy read at offset 0; this will ensure all
  3475. * pendings writes(HP/TP) are flushed before read returns.
  3476. */
  3477. val = HAL_REG_READ((struct hal_soc *)soc->hal_soc, 0);
  3478. dp_debug("Register value at offset 0: %u\n", val);
  3479. }
  3480. #endif
  3481. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  3482. /**
  3483. * dp_flush_ring_hptp() - Update ring shadow
  3484. * register HP/TP address when runtime
  3485. * resume
  3486. * @soc: DP soc context
  3487. * @hal_srng: srng
  3488. *
  3489. * Return: None
  3490. */
  3491. void dp_flush_ring_hptp(struct dp_soc *soc, hal_ring_handle_t hal_srng)
  3492. {
  3493. if (hal_srng && hal_srng_get_clear_event(hal_srng,
  3494. HAL_SRNG_FLUSH_EVENT)) {
  3495. /* Acquire the lock */
  3496. hal_srng_access_start(soc->hal_soc, hal_srng);
  3497. hal_srng_access_end(soc->hal_soc, hal_srng);
  3498. hal_srng_set_flush_last_ts(hal_srng);
  3499. dp_debug("flushed");
  3500. }
  3501. }
  3502. #endif
  3503. #ifdef FEATURE_RUNTIME_PM
  3504. /**
  3505. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  3506. * @soc_hdl: Datapath soc handle
  3507. * @pdev_id: id of data path pdev handle
  3508. *
  3509. * DP is ready to runtime suspend if there are no pending TX packets.
  3510. *
  3511. * Return: QDF_STATUS
  3512. */
  3513. QDF_STATUS dp_runtime_suspend(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  3514. {
  3515. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3516. struct dp_pdev *pdev;
  3517. uint8_t i;
  3518. int32_t tx_pending;
  3519. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3520. if (!pdev) {
  3521. dp_err("pdev is NULL");
  3522. return QDF_STATUS_E_INVAL;
  3523. }
  3524. /* Abort if there are any pending TX packets */
  3525. tx_pending = dp_get_tx_pending(dp_pdev_to_cdp_pdev(pdev));
  3526. if (tx_pending) {
  3527. dp_info_rl("%pK: Abort suspend due to pending TX packets %d",
  3528. soc, tx_pending);
  3529. dp_find_missing_tx_comp(soc);
  3530. /* perform a force flush if tx is pending */
  3531. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3532. hal_srng_set_event(soc->tcl_data_ring[i].hal_srng,
  3533. HAL_SRNG_FLUSH_EVENT);
  3534. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3535. }
  3536. qdf_atomic_set(&soc->tx_pending_rtpm, 0);
  3537. return QDF_STATUS_E_AGAIN;
  3538. }
  3539. if (dp_runtime_get_refcount(soc)) {
  3540. dp_init_info("refcount: %d", dp_runtime_get_refcount(soc));
  3541. return QDF_STATUS_E_AGAIN;
  3542. }
  3543. if (soc->intr_mode == DP_INTR_POLL)
  3544. qdf_timer_stop(&soc->int_timer);
  3545. dp_rx_fst_update_pm_suspend_status(soc, true);
  3546. return QDF_STATUS_SUCCESS;
  3547. }
  3548. #define DP_FLUSH_WAIT_CNT 10
  3549. #define DP_RUNTIME_SUSPEND_WAIT_MS 10
  3550. /**
  3551. * dp_runtime_resume() - ensure DP is ready to runtime resume
  3552. * @soc_hdl: Datapath soc handle
  3553. * @pdev_id: id of data path pdev handle
  3554. *
  3555. * Resume DP for runtime PM.
  3556. *
  3557. * Return: QDF_STATUS
  3558. */
  3559. QDF_STATUS dp_runtime_resume(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  3560. {
  3561. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3562. int i, suspend_wait = 0;
  3563. if (soc->intr_mode == DP_INTR_POLL)
  3564. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  3565. /*
  3566. * Wait until dp runtime refcount becomes zero or time out, then flush
  3567. * pending tx for runtime suspend.
  3568. */
  3569. while (dp_runtime_get_refcount(soc) &&
  3570. suspend_wait < DP_FLUSH_WAIT_CNT) {
  3571. qdf_sleep(DP_RUNTIME_SUSPEND_WAIT_MS);
  3572. suspend_wait++;
  3573. }
  3574. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3575. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3576. }
  3577. qdf_atomic_set(&soc->tx_pending_rtpm, 0);
  3578. dp_flush_ring_hptp(soc, soc->reo_cmd_ring.hal_srng);
  3579. dp_rx_fst_update_pm_suspend_status(soc, false);
  3580. return QDF_STATUS_SUCCESS;
  3581. }
  3582. #endif /* FEATURE_RUNTIME_PM */
  3583. #ifdef WLAN_FEATURE_STATS_EXT
  3584. /* rx hw stats event wait timeout in ms */
  3585. #define DP_REO_STATUS_STATS_TIMEOUT 100
  3586. /**
  3587. * dp_rx_hw_stats_cb() - request rx hw stats response callback
  3588. * @soc: soc handle
  3589. * @cb_ctxt: callback context
  3590. * @reo_status: reo command response status
  3591. *
  3592. * Return: None
  3593. */
  3594. static void dp_rx_hw_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3595. union hal_reo_status *reo_status)
  3596. {
  3597. struct dp_req_rx_hw_stats_t *rx_hw_stats = cb_ctxt;
  3598. struct hal_reo_queue_status *queue_status = &reo_status->queue_status;
  3599. bool is_query_timeout;
  3600. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3601. is_query_timeout = rx_hw_stats->is_query_timeout;
  3602. /* free the cb_ctxt if all pending tid stats query is received */
  3603. if (qdf_atomic_dec_and_test(&rx_hw_stats->pending_tid_stats_cnt)) {
  3604. if (!is_query_timeout) {
  3605. qdf_event_set(&soc->rx_hw_stats_event);
  3606. soc->is_last_stats_ctx_init = false;
  3607. }
  3608. qdf_mem_free(rx_hw_stats);
  3609. }
  3610. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3611. dp_info("REO stats failure %d",
  3612. queue_status->header.status);
  3613. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3614. return;
  3615. }
  3616. if (!is_query_timeout) {
  3617. soc->ext_stats.rx_mpdu_received +=
  3618. queue_status->mpdu_frms_cnt;
  3619. soc->ext_stats.rx_mpdu_missed +=
  3620. queue_status->hole_cnt;
  3621. }
  3622. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3623. }
  3624. /**
  3625. * dp_request_rx_hw_stats() - request rx hardware stats
  3626. * @soc_hdl: soc handle
  3627. * @vdev_id: vdev id
  3628. *
  3629. * Return: None
  3630. */
  3631. QDF_STATUS
  3632. dp_request_rx_hw_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
  3633. {
  3634. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3635. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3636. DP_MOD_ID_CDP);
  3637. struct dp_peer *peer = NULL;
  3638. QDF_STATUS status;
  3639. struct dp_req_rx_hw_stats_t *rx_hw_stats;
  3640. int rx_stats_sent_cnt = 0;
  3641. uint32_t last_rx_mpdu_received;
  3642. uint32_t last_rx_mpdu_missed;
  3643. if (!vdev) {
  3644. dp_err("vdev is null for vdev_id: %u", vdev_id);
  3645. status = QDF_STATUS_E_INVAL;
  3646. goto out;
  3647. }
  3648. peer = dp_vdev_bss_peer_ref_n_get(soc, vdev, DP_MOD_ID_CDP);
  3649. if (!peer) {
  3650. dp_err("Peer is NULL");
  3651. status = QDF_STATUS_E_INVAL;
  3652. goto out;
  3653. }
  3654. rx_hw_stats = qdf_mem_malloc(sizeof(*rx_hw_stats));
  3655. if (!rx_hw_stats) {
  3656. dp_err("malloc failed for hw stats structure");
  3657. status = QDF_STATUS_E_INVAL;
  3658. goto out;
  3659. }
  3660. qdf_event_reset(&soc->rx_hw_stats_event);
  3661. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3662. /* save the last soc cumulative stats and reset it to 0 */
  3663. last_rx_mpdu_received = soc->ext_stats.rx_mpdu_received;
  3664. last_rx_mpdu_missed = soc->ext_stats.rx_mpdu_missed;
  3665. soc->ext_stats.rx_mpdu_received = 0;
  3666. soc->ext_stats.rx_mpdu_missed = 0;
  3667. dp_debug("HW stats query start");
  3668. rx_stats_sent_cnt =
  3669. dp_peer_rxtid_stats(peer, dp_rx_hw_stats_cb, rx_hw_stats);
  3670. if (!rx_stats_sent_cnt) {
  3671. dp_err("no tid stats sent successfully");
  3672. qdf_mem_free(rx_hw_stats);
  3673. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3674. status = QDF_STATUS_E_INVAL;
  3675. goto out;
  3676. }
  3677. qdf_atomic_set(&rx_hw_stats->pending_tid_stats_cnt,
  3678. rx_stats_sent_cnt);
  3679. rx_hw_stats->is_query_timeout = false;
  3680. soc->is_last_stats_ctx_init = true;
  3681. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3682. status = qdf_wait_single_event(&soc->rx_hw_stats_event,
  3683. DP_REO_STATUS_STATS_TIMEOUT);
  3684. dp_debug("HW stats query end with %d", rx_stats_sent_cnt);
  3685. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3686. if (status != QDF_STATUS_SUCCESS) {
  3687. dp_info("partial rx hw stats event collected with %d",
  3688. qdf_atomic_read(
  3689. &rx_hw_stats->pending_tid_stats_cnt));
  3690. if (soc->is_last_stats_ctx_init)
  3691. rx_hw_stats->is_query_timeout = true;
  3692. /*
  3693. * If query timeout happened, use the last saved stats
  3694. * for this time query.
  3695. */
  3696. soc->ext_stats.rx_mpdu_received = last_rx_mpdu_received;
  3697. soc->ext_stats.rx_mpdu_missed = last_rx_mpdu_missed;
  3698. DP_STATS_INC(soc, rx.rx_hw_stats_timeout, 1);
  3699. }
  3700. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3701. out:
  3702. if (peer)
  3703. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3704. if (vdev)
  3705. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3706. DP_STATS_INC(soc, rx.rx_hw_stats_requested, 1);
  3707. return status;
  3708. }
  3709. /**
  3710. * dp_reset_rx_hw_ext_stats() - Reset rx hardware ext stats
  3711. * @soc_hdl: soc handle
  3712. *
  3713. * Return: None
  3714. */
  3715. void dp_reset_rx_hw_ext_stats(struct cdp_soc_t *soc_hdl)
  3716. {
  3717. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3718. soc->ext_stats.rx_mpdu_received = 0;
  3719. soc->ext_stats.rx_mpdu_missed = 0;
  3720. }
  3721. #endif /* WLAN_FEATURE_STATS_EXT */
  3722. uint32_t dp_get_tx_rings_grp_bitmap(struct cdp_soc_t *soc_hdl)
  3723. {
  3724. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3725. return soc->wlan_cfg_ctx->tx_rings_grp_bitmap;
  3726. }
  3727. void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  3728. {
  3729. uint32_t i;
  3730. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  3731. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_DEFAULT_MAP][i];
  3732. }
  3733. }
  3734. qdf_export_symbol(dp_soc_set_txrx_ring_map);
  3735. static void dp_soc_cfg_dump(struct dp_soc *soc, uint32_t target_type)
  3736. {
  3737. dp_init_info("DP soc Dump for Target = %d", target_type);
  3738. dp_init_info("ast_override_support = %d, da_war_enabled = %d,",
  3739. soc->ast_override_support, soc->da_war_enabled);
  3740. wlan_cfg_dp_soc_ctx_dump(soc->wlan_cfg_ctx);
  3741. }
  3742. /**
  3743. * dp_soc_cfg_init() - initialize target specific configuration
  3744. * during dp_soc_init
  3745. * @soc: dp soc handle
  3746. */
  3747. static void dp_soc_cfg_init(struct dp_soc *soc)
  3748. {
  3749. uint32_t target_type;
  3750. target_type = hal_get_target_type(soc->hal_soc);
  3751. switch (target_type) {
  3752. case TARGET_TYPE_QCA6290:
  3753. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3754. REO_DST_RING_SIZE_QCA6290);
  3755. soc->ast_override_support = 1;
  3756. soc->da_war_enabled = false;
  3757. break;
  3758. case TARGET_TYPE_QCA6390:
  3759. case TARGET_TYPE_QCA6490:
  3760. case TARGET_TYPE_QCA6750:
  3761. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3762. REO_DST_RING_SIZE_QCA6290);
  3763. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3764. soc->ast_override_support = 1;
  3765. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3766. soc->cdp_soc.ol_ops->get_con_mode() ==
  3767. QDF_GLOBAL_MONITOR_MODE) {
  3768. int int_ctx;
  3769. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS; int_ctx++) {
  3770. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3771. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3772. }
  3773. }
  3774. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3775. break;
  3776. case TARGET_TYPE_KIWI:
  3777. case TARGET_TYPE_MANGO:
  3778. case TARGET_TYPE_PEACH:
  3779. soc->ast_override_support = 1;
  3780. soc->per_tid_basize_max_tid = 8;
  3781. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3782. soc->cdp_soc.ol_ops->get_con_mode() ==
  3783. QDF_GLOBAL_MONITOR_MODE) {
  3784. int int_ctx;
  3785. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS;
  3786. int_ctx++) {
  3787. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3788. if (dp_is_monitor_mode_using_poll(soc))
  3789. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3790. }
  3791. }
  3792. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3793. soc->wlan_cfg_ctx->num_rxdma_dst_rings_per_pdev = 1;
  3794. break;
  3795. case TARGET_TYPE_QCA8074:
  3796. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3797. soc->da_war_enabled = true;
  3798. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3799. break;
  3800. case TARGET_TYPE_QCA8074V2:
  3801. case TARGET_TYPE_QCA6018:
  3802. case TARGET_TYPE_QCA9574:
  3803. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3804. soc->ast_override_support = 1;
  3805. soc->per_tid_basize_max_tid = 8;
  3806. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3807. soc->da_war_enabled = false;
  3808. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3809. break;
  3810. case TARGET_TYPE_QCN9000:
  3811. soc->ast_override_support = 1;
  3812. soc->da_war_enabled = false;
  3813. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3814. soc->per_tid_basize_max_tid = 8;
  3815. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3816. soc->lmac_polled_mode = 0;
  3817. soc->wbm_release_desc_rx_sg_support = 1;
  3818. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3819. break;
  3820. case TARGET_TYPE_QCA5018:
  3821. case TARGET_TYPE_QCN6122:
  3822. case TARGET_TYPE_QCN9160:
  3823. soc->ast_override_support = 1;
  3824. soc->da_war_enabled = false;
  3825. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3826. soc->per_tid_basize_max_tid = 8;
  3827. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS_11AX;
  3828. soc->disable_mac1_intr = 1;
  3829. soc->disable_mac2_intr = 1;
  3830. soc->wbm_release_desc_rx_sg_support = 1;
  3831. break;
  3832. case TARGET_TYPE_QCN9224:
  3833. soc->ast_override_support = 1;
  3834. soc->da_war_enabled = false;
  3835. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3836. soc->per_tid_basize_max_tid = 8;
  3837. soc->wbm_release_desc_rx_sg_support = 1;
  3838. soc->rxdma2sw_rings_not_supported = 1;
  3839. soc->wbm_sg_last_msdu_war = 1;
  3840. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3841. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3842. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3843. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3844. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3845. CFG_DP_HOST_AST_DB_ENABLE);
  3846. soc->features.wds_ext_ast_override_enable = true;
  3847. break;
  3848. case TARGET_TYPE_QCA5332:
  3849. soc->ast_override_support = 1;
  3850. soc->da_war_enabled = false;
  3851. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3852. soc->per_tid_basize_max_tid = 8;
  3853. soc->wbm_release_desc_rx_sg_support = 1;
  3854. soc->rxdma2sw_rings_not_supported = 1;
  3855. soc->wbm_sg_last_msdu_war = 1;
  3856. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3857. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3858. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS_5332;
  3859. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3860. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3861. CFG_DP_HOST_AST_DB_ENABLE);
  3862. soc->features.wds_ext_ast_override_enable = true;
  3863. break;
  3864. default:
  3865. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  3866. qdf_assert_always(0);
  3867. break;
  3868. }
  3869. dp_soc_cfg_dump(soc, target_type);
  3870. }
  3871. /**
  3872. * dp_soc_init() - Initialize txrx SOC
  3873. * @soc: Opaque DP SOC handle
  3874. * @htc_handle: Opaque HTC handle
  3875. * @hif_handle: Opaque HIF handle
  3876. *
  3877. * Return: DP SOC handle on success, NULL on failure
  3878. */
  3879. void *dp_soc_init(struct dp_soc *soc, HTC_HANDLE htc_handle,
  3880. struct hif_opaque_softc *hif_handle)
  3881. {
  3882. struct htt_soc *htt_soc = (struct htt_soc *)soc->htt_handle;
  3883. bool is_monitor_mode = false;
  3884. uint8_t i;
  3885. int num_dp_msi;
  3886. htt_soc = htt_soc_attach(soc, htc_handle);
  3887. if (!htt_soc)
  3888. goto fail1;
  3889. soc->htt_handle = htt_soc;
  3890. if (htt_soc_htc_prealloc(htt_soc) != QDF_STATUS_SUCCESS)
  3891. goto fail2;
  3892. htt_set_htc_handle(htt_soc, htc_handle);
  3893. dp_soc_cfg_init(soc);
  3894. dp_monitor_soc_cfg_init(soc);
  3895. /* Reset/Initialize wbm sg list and flags */
  3896. dp_rx_wbm_sg_list_reset(soc);
  3897. /* Note: Any SRNG ring initialization should happen only after
  3898. * Interrupt mode is set and followed by filling up the
  3899. * interrupt mask. IT SHOULD ALWAYS BE IN THIS ORDER.
  3900. */
  3901. dp_soc_set_interrupt_mode(soc);
  3902. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3903. soc->cdp_soc.ol_ops->get_con_mode() ==
  3904. QDF_GLOBAL_MONITOR_MODE) {
  3905. is_monitor_mode = true;
  3906. soc->curr_rx_pkt_tlv_size = soc->rx_mon_pkt_tlv_size;
  3907. } else {
  3908. soc->curr_rx_pkt_tlv_size = soc->rx_pkt_tlv_size;
  3909. }
  3910. num_dp_msi = dp_get_num_msi_available(soc, soc->intr_mode);
  3911. if (num_dp_msi < 0) {
  3912. dp_init_err("%pK: dp_interrupt assignment failed", soc);
  3913. goto fail3;
  3914. }
  3915. wlan_cfg_fill_interrupt_mask(soc->wlan_cfg_ctx, num_dp_msi,
  3916. soc->intr_mode, is_monitor_mode);
  3917. /* initialize WBM_IDLE_LINK ring */
  3918. if (dp_hw_link_desc_ring_init(soc)) {
  3919. dp_init_err("%pK: dp_hw_link_desc_ring_init failed", soc);
  3920. goto fail3;
  3921. }
  3922. dp_link_desc_ring_replenish(soc, WLAN_INVALID_PDEV_ID);
  3923. if (dp_soc_srng_init(soc)) {
  3924. dp_init_err("%pK: dp_soc_srng_init failed", soc);
  3925. goto fail4;
  3926. }
  3927. if (htt_soc_initialize(soc->htt_handle, soc->ctrl_psoc,
  3928. htt_get_htc_handle(htt_soc),
  3929. soc->hal_soc, soc->osdev) == NULL)
  3930. goto fail5;
  3931. /* Initialize descriptors in TCL Rings */
  3932. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3933. hal_tx_init_data_ring(soc->hal_soc,
  3934. soc->tcl_data_ring[i].hal_srng);
  3935. }
  3936. if (dp_soc_tx_desc_sw_pools_init(soc)) {
  3937. dp_init_err("%pK: dp_tx_soc_attach failed", soc);
  3938. goto fail6;
  3939. }
  3940. if (soc->arch_ops.txrx_soc_ppeds_start) {
  3941. if (soc->arch_ops.txrx_soc_ppeds_start(soc)) {
  3942. dp_init_err("%pK: ppeds start failed", soc);
  3943. goto fail7;
  3944. }
  3945. }
  3946. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx,
  3947. cfg_get(soc->ctrl_psoc, CFG_DP_RX_HASH));
  3948. soc->cce_disable = false;
  3949. soc->max_ast_ageout_count = MAX_AST_AGEOUT_COUNT;
  3950. soc->sta_mode_search_policy = DP_TX_ADDR_SEARCH_ADDR_POLICY;
  3951. qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map));
  3952. qdf_spinlock_create(&soc->vdev_map_lock);
  3953. qdf_atomic_init(&soc->num_tx_outstanding);
  3954. qdf_atomic_init(&soc->num_tx_exception);
  3955. soc->num_tx_allowed =
  3956. wlan_cfg_get_dp_soc_tx_device_limit(soc->wlan_cfg_ctx);
  3957. soc->num_tx_spl_allowed =
  3958. wlan_cfg_get_dp_soc_tx_spl_device_limit(soc->wlan_cfg_ctx);
  3959. soc->num_reg_tx_allowed = soc->num_tx_allowed - soc->num_tx_spl_allowed;
  3960. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3961. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3962. CDP_CFG_MAX_PEER_ID);
  3963. if (ret != -EINVAL)
  3964. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  3965. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3966. CDP_CFG_CCE_DISABLE);
  3967. if (ret == 1)
  3968. soc->cce_disable = true;
  3969. }
  3970. /*
  3971. * Skip registering hw ring interrupts for WMAC2 on IPQ6018
  3972. * and IPQ5018 WMAC2 is not there in these platforms.
  3973. */
  3974. if (hal_get_target_type(soc->hal_soc) == TARGET_TYPE_QCA6018 ||
  3975. soc->disable_mac2_intr)
  3976. dp_soc_disable_unused_mac_intr_mask(soc, 0x2);
  3977. /*
  3978. * Skip registering hw ring interrupts for WMAC1 on IPQ5018
  3979. * WMAC1 is not there in this platform.
  3980. */
  3981. if (soc->disable_mac1_intr)
  3982. dp_soc_disable_unused_mac_intr_mask(soc, 0x1);
  3983. /* setup the global rx defrag waitlist */
  3984. TAILQ_INIT(&soc->rx.defrag.waitlist);
  3985. soc->rx.defrag.timeout_ms =
  3986. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  3987. soc->rx.defrag.next_flush_ms = 0;
  3988. soc->rx.flags.defrag_timeout_check =
  3989. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  3990. qdf_spinlock_create(&soc->rx.defrag.defrag_lock);
  3991. dp_monitor_soc_init(soc);
  3992. qdf_atomic_set(&soc->cmn_init_done, 1);
  3993. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  3994. qdf_spinlock_create(&soc->ast_lock);
  3995. dp_peer_mec_spinlock_create(soc);
  3996. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  3997. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  3998. INIT_RX_HW_STATS_LOCK(soc);
  3999. qdf_nbuf_queue_init(&soc->invalid_buf_queue);
  4000. /* fill the tx/rx cpu ring map*/
  4001. dp_soc_set_txrx_ring_map(soc);
  4002. TAILQ_INIT(&soc->inactive_peer_list);
  4003. qdf_spinlock_create(&soc->inactive_peer_list_lock);
  4004. TAILQ_INIT(&soc->inactive_vdev_list);
  4005. qdf_spinlock_create(&soc->inactive_vdev_list_lock);
  4006. qdf_spinlock_create(&soc->htt_stats.lock);
  4007. /* initialize work queue for stats processing */
  4008. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4009. dp_reo_desc_deferred_freelist_create(soc);
  4010. dp_info("Mem stats: DMA = %u HEAP = %u SKB = %u",
  4011. qdf_dma_mem_stats_read(),
  4012. qdf_heap_mem_stats_read(),
  4013. qdf_skb_total_mem_stats_read());
  4014. soc->vdev_stats_id_map = 0;
  4015. return soc;
  4016. fail7:
  4017. dp_soc_tx_desc_sw_pools_deinit(soc);
  4018. fail6:
  4019. htt_soc_htc_dealloc(soc->htt_handle);
  4020. fail5:
  4021. dp_soc_srng_deinit(soc);
  4022. fail4:
  4023. dp_hw_link_desc_ring_deinit(soc);
  4024. fail3:
  4025. htt_htc_pkt_pool_free(htt_soc);
  4026. fail2:
  4027. htt_soc_detach(htt_soc);
  4028. fail1:
  4029. return NULL;
  4030. }
  4031. #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
  4032. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  4033. {
  4034. QDF_STATUS status;
  4035. if (soc->init_tcl_cmd_cred_ring) {
  4036. status = dp_srng_init(soc, &soc->tcl_cmd_credit_ring,
  4037. TCL_CMD_CREDIT, 0, 0);
  4038. if (QDF_IS_STATUS_ERROR(status))
  4039. return status;
  4040. wlan_minidump_log(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  4041. soc->tcl_cmd_credit_ring.alloc_size,
  4042. soc->ctrl_psoc,
  4043. WLAN_MD_DP_SRNG_TCL_CMD,
  4044. "wbm_desc_rel_ring");
  4045. }
  4046. return QDF_STATUS_SUCCESS;
  4047. }
  4048. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4049. {
  4050. if (soc->init_tcl_cmd_cred_ring) {
  4051. wlan_minidump_remove(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  4052. soc->tcl_cmd_credit_ring.alloc_size,
  4053. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_CMD,
  4054. "wbm_desc_rel_ring");
  4055. dp_srng_deinit(soc, &soc->tcl_cmd_credit_ring,
  4056. TCL_CMD_CREDIT, 0);
  4057. }
  4058. }
  4059. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4060. {
  4061. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4062. uint32_t entries;
  4063. QDF_STATUS status;
  4064. entries = wlan_cfg_get_dp_soc_tcl_cmd_credit_ring_size(soc_cfg_ctx);
  4065. if (soc->init_tcl_cmd_cred_ring) {
  4066. status = dp_srng_alloc(soc, &soc->tcl_cmd_credit_ring,
  4067. TCL_CMD_CREDIT, entries, 0);
  4068. if (QDF_IS_STATUS_ERROR(status))
  4069. return status;
  4070. }
  4071. return QDF_STATUS_SUCCESS;
  4072. }
  4073. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4074. {
  4075. if (soc->init_tcl_cmd_cred_ring)
  4076. dp_srng_free(soc, &soc->tcl_cmd_credit_ring);
  4077. }
  4078. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4079. {
  4080. if (soc->init_tcl_cmd_cred_ring)
  4081. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  4082. soc->tcl_cmd_credit_ring.hal_srng);
  4083. }
  4084. #else
  4085. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  4086. {
  4087. return QDF_STATUS_SUCCESS;
  4088. }
  4089. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4090. {
  4091. }
  4092. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4093. {
  4094. return QDF_STATUS_SUCCESS;
  4095. }
  4096. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4097. {
  4098. }
  4099. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4100. {
  4101. }
  4102. #endif
  4103. #ifndef WLAN_DP_DISABLE_TCL_STATUS_SRNG
  4104. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4105. {
  4106. QDF_STATUS status;
  4107. status = dp_srng_init(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0);
  4108. if (QDF_IS_STATUS_ERROR(status))
  4109. return status;
  4110. wlan_minidump_log(soc->tcl_status_ring.base_vaddr_unaligned,
  4111. soc->tcl_status_ring.alloc_size,
  4112. soc->ctrl_psoc,
  4113. WLAN_MD_DP_SRNG_TCL_STATUS,
  4114. "wbm_desc_rel_ring");
  4115. return QDF_STATUS_SUCCESS;
  4116. }
  4117. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4118. {
  4119. wlan_minidump_remove(soc->tcl_status_ring.base_vaddr_unaligned,
  4120. soc->tcl_status_ring.alloc_size,
  4121. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_STATUS,
  4122. "wbm_desc_rel_ring");
  4123. dp_srng_deinit(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  4124. }
  4125. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4126. {
  4127. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4128. uint32_t entries;
  4129. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4130. entries = wlan_cfg_get_dp_soc_tcl_status_ring_size(soc_cfg_ctx);
  4131. status = dp_srng_alloc(soc, &soc->tcl_status_ring,
  4132. TCL_STATUS, entries, 0);
  4133. return status;
  4134. }
  4135. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4136. {
  4137. dp_srng_free(soc, &soc->tcl_status_ring);
  4138. }
  4139. #else
  4140. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4141. {
  4142. return QDF_STATUS_SUCCESS;
  4143. }
  4144. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4145. {
  4146. }
  4147. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4148. {
  4149. return QDF_STATUS_SUCCESS;
  4150. }
  4151. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4152. {
  4153. }
  4154. #endif
  4155. /**
  4156. * dp_soc_srng_deinit() - de-initialize soc srng rings
  4157. * @soc: Datapath soc handle
  4158. *
  4159. */
  4160. void dp_soc_srng_deinit(struct dp_soc *soc)
  4161. {
  4162. uint32_t i;
  4163. if (soc->arch_ops.txrx_soc_srng_deinit)
  4164. soc->arch_ops.txrx_soc_srng_deinit(soc);
  4165. /* Free the ring memories */
  4166. /* Common rings */
  4167. wlan_minidump_remove(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4168. soc->wbm_desc_rel_ring.alloc_size,
  4169. soc->ctrl_psoc, WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4170. "wbm_desc_rel_ring");
  4171. dp_srng_deinit(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  4172. /* Tx data rings */
  4173. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4174. dp_deinit_tx_pair_by_index(soc, i);
  4175. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4176. dp_deinit_tx_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4177. dp_ipa_deinit_alt_tx_ring(soc);
  4178. }
  4179. /* TCL command and status rings */
  4180. dp_soc_tcl_cmd_cred_srng_deinit(soc);
  4181. dp_soc_tcl_status_srng_deinit(soc);
  4182. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4183. /* TODO: Get number of rings and ring sizes
  4184. * from wlan_cfg
  4185. */
  4186. wlan_minidump_remove(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4187. soc->reo_dest_ring[i].alloc_size,
  4188. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_DEST,
  4189. "reo_dest_ring");
  4190. dp_srng_deinit(soc, &soc->reo_dest_ring[i], REO_DST, i);
  4191. }
  4192. /* REO reinjection ring */
  4193. wlan_minidump_remove(soc->reo_reinject_ring.base_vaddr_unaligned,
  4194. soc->reo_reinject_ring.alloc_size,
  4195. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_REINJECT,
  4196. "reo_reinject_ring");
  4197. dp_srng_deinit(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  4198. /* Rx release ring */
  4199. wlan_minidump_remove(soc->rx_rel_ring.base_vaddr_unaligned,
  4200. soc->rx_rel_ring.alloc_size,
  4201. soc->ctrl_psoc, WLAN_MD_DP_SRNG_RX_REL,
  4202. "reo_release_ring");
  4203. dp_srng_deinit(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  4204. /* Rx exception ring */
  4205. /* TODO: Better to store ring_type and ring_num in
  4206. * dp_srng during setup
  4207. */
  4208. wlan_minidump_remove(soc->reo_exception_ring.base_vaddr_unaligned,
  4209. soc->reo_exception_ring.alloc_size,
  4210. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4211. "reo_exception_ring");
  4212. dp_srng_deinit(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  4213. /* REO command and status rings */
  4214. wlan_minidump_remove(soc->reo_cmd_ring.base_vaddr_unaligned,
  4215. soc->reo_cmd_ring.alloc_size,
  4216. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_CMD,
  4217. "reo_cmd_ring");
  4218. dp_srng_deinit(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  4219. wlan_minidump_remove(soc->reo_status_ring.base_vaddr_unaligned,
  4220. soc->reo_status_ring.alloc_size,
  4221. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_STATUS,
  4222. "reo_status_ring");
  4223. dp_srng_deinit(soc, &soc->reo_status_ring, REO_STATUS, 0);
  4224. }
  4225. /**
  4226. * dp_soc_srng_init() - Initialize soc level srng rings
  4227. * @soc: Datapath soc handle
  4228. *
  4229. * Return: QDF_STATUS_SUCCESS on success
  4230. * QDF_STATUS_E_FAILURE on failure
  4231. */
  4232. QDF_STATUS dp_soc_srng_init(struct dp_soc *soc)
  4233. {
  4234. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4235. uint8_t i;
  4236. uint8_t wbm2_sw_rx_rel_ring_id;
  4237. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4238. dp_enable_verbose_debug(soc);
  4239. /* WBM descriptor release ring */
  4240. if (dp_srng_init(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0)) {
  4241. dp_init_err("%pK: dp_srng_init failed for wbm_desc_rel_ring", soc);
  4242. goto fail1;
  4243. }
  4244. wlan_minidump_log(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4245. soc->wbm_desc_rel_ring.alloc_size,
  4246. soc->ctrl_psoc,
  4247. WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4248. "wbm_desc_rel_ring");
  4249. /* TCL command and status rings */
  4250. if (dp_soc_tcl_cmd_cred_srng_init(soc)) {
  4251. dp_init_err("%pK: dp_srng_init failed for tcl_cmd_ring", soc);
  4252. goto fail1;
  4253. }
  4254. if (dp_soc_tcl_status_srng_init(soc)) {
  4255. dp_init_err("%pK: dp_srng_init failed for tcl_status_ring", soc);
  4256. goto fail1;
  4257. }
  4258. /* REO reinjection ring */
  4259. if (dp_srng_init(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0)) {
  4260. dp_init_err("%pK: dp_srng_init failed for reo_reinject_ring", soc);
  4261. goto fail1;
  4262. }
  4263. wlan_minidump_log(soc->reo_reinject_ring.base_vaddr_unaligned,
  4264. soc->reo_reinject_ring.alloc_size,
  4265. soc->ctrl_psoc,
  4266. WLAN_MD_DP_SRNG_REO_REINJECT,
  4267. "reo_reinject_ring");
  4268. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc_cfg_ctx);
  4269. /* Rx release ring */
  4270. if (dp_srng_init(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4271. wbm2_sw_rx_rel_ring_id, 0)) {
  4272. dp_init_err("%pK: dp_srng_init failed for rx_rel_ring", soc);
  4273. goto fail1;
  4274. }
  4275. wlan_minidump_log(soc->rx_rel_ring.base_vaddr_unaligned,
  4276. soc->rx_rel_ring.alloc_size,
  4277. soc->ctrl_psoc,
  4278. WLAN_MD_DP_SRNG_RX_REL,
  4279. "reo_release_ring");
  4280. /* Rx exception ring */
  4281. if (dp_srng_init(soc, &soc->reo_exception_ring,
  4282. REO_EXCEPTION, 0, MAX_REO_DEST_RINGS)) {
  4283. dp_init_err("%pK: dp_srng_init failed - reo_exception", soc);
  4284. goto fail1;
  4285. }
  4286. wlan_minidump_log(soc->reo_exception_ring.base_vaddr_unaligned,
  4287. soc->reo_exception_ring.alloc_size,
  4288. soc->ctrl_psoc,
  4289. WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4290. "reo_exception_ring");
  4291. /* REO command and status rings */
  4292. if (dp_srng_init(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0)) {
  4293. dp_init_err("%pK: dp_srng_init failed for reo_cmd_ring", soc);
  4294. goto fail1;
  4295. }
  4296. wlan_minidump_log(soc->reo_cmd_ring.base_vaddr_unaligned,
  4297. soc->reo_cmd_ring.alloc_size,
  4298. soc->ctrl_psoc,
  4299. WLAN_MD_DP_SRNG_REO_CMD,
  4300. "reo_cmd_ring");
  4301. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  4302. TAILQ_INIT(&soc->rx.reo_cmd_list);
  4303. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  4304. if (dp_srng_init(soc, &soc->reo_status_ring, REO_STATUS, 0, 0)) {
  4305. dp_init_err("%pK: dp_srng_init failed for reo_status_ring", soc);
  4306. goto fail1;
  4307. }
  4308. wlan_minidump_log(soc->reo_status_ring.base_vaddr_unaligned,
  4309. soc->reo_status_ring.alloc_size,
  4310. soc->ctrl_psoc,
  4311. WLAN_MD_DP_SRNG_REO_STATUS,
  4312. "reo_status_ring");
  4313. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4314. if (dp_init_tx_ring_pair_by_index(soc, i))
  4315. goto fail1;
  4316. }
  4317. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4318. if (dp_init_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4319. goto fail1;
  4320. if (dp_ipa_init_alt_tx_ring(soc))
  4321. goto fail1;
  4322. }
  4323. dp_create_ext_stats_event(soc);
  4324. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4325. /* Initialize REO destination ring */
  4326. if (dp_srng_init(soc, &soc->reo_dest_ring[i], REO_DST, i, 0)) {
  4327. dp_init_err("%pK: dp_srng_init failed for reo_dest_ringn", soc);
  4328. goto fail1;
  4329. }
  4330. wlan_minidump_log(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4331. soc->reo_dest_ring[i].alloc_size,
  4332. soc->ctrl_psoc,
  4333. WLAN_MD_DP_SRNG_REO_DEST,
  4334. "reo_dest_ring");
  4335. }
  4336. if (soc->arch_ops.txrx_soc_srng_init) {
  4337. if (soc->arch_ops.txrx_soc_srng_init(soc)) {
  4338. dp_init_err("%pK: dp_srng_init failed for arch rings",
  4339. soc);
  4340. goto fail1;
  4341. }
  4342. }
  4343. return QDF_STATUS_SUCCESS;
  4344. fail1:
  4345. /*
  4346. * Cleanup will be done as part of soc_detach, which will
  4347. * be called on pdev attach failure
  4348. */
  4349. dp_soc_srng_deinit(soc);
  4350. return QDF_STATUS_E_FAILURE;
  4351. }
  4352. /**
  4353. * dp_soc_srng_free() - free soc level srng rings
  4354. * @soc: Datapath soc handle
  4355. *
  4356. */
  4357. void dp_soc_srng_free(struct dp_soc *soc)
  4358. {
  4359. uint32_t i;
  4360. if (soc->arch_ops.txrx_soc_srng_free)
  4361. soc->arch_ops.txrx_soc_srng_free(soc);
  4362. dp_srng_free(soc, &soc->wbm_desc_rel_ring);
  4363. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4364. dp_free_tx_ring_pair_by_index(soc, i);
  4365. /* Free IPA rings for TCL_TX and TCL_COMPL ring */
  4366. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4367. dp_free_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4368. dp_ipa_free_alt_tx_ring(soc);
  4369. }
  4370. dp_soc_tcl_cmd_cred_srng_free(soc);
  4371. dp_soc_tcl_status_srng_free(soc);
  4372. for (i = 0; i < soc->num_reo_dest_rings; i++)
  4373. dp_srng_free(soc, &soc->reo_dest_ring[i]);
  4374. dp_srng_free(soc, &soc->reo_reinject_ring);
  4375. dp_srng_free(soc, &soc->rx_rel_ring);
  4376. dp_srng_free(soc, &soc->reo_exception_ring);
  4377. dp_srng_free(soc, &soc->reo_cmd_ring);
  4378. dp_srng_free(soc, &soc->reo_status_ring);
  4379. }
  4380. /**
  4381. * dp_soc_srng_alloc() - Allocate memory for soc level srng rings
  4382. * @soc: Datapath soc handle
  4383. *
  4384. * Return: QDF_STATUS_SUCCESS on success
  4385. * QDF_STATUS_E_NOMEM on failure
  4386. */
  4387. QDF_STATUS dp_soc_srng_alloc(struct dp_soc *soc)
  4388. {
  4389. uint32_t entries;
  4390. uint32_t i;
  4391. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4392. uint32_t cached = WLAN_CFG_DST_RING_CACHED_DESC;
  4393. uint32_t reo_dst_ring_size;
  4394. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4395. /* sw2wbm link descriptor release ring */
  4396. entries = wlan_cfg_get_dp_soc_wbm_release_ring_size(soc_cfg_ctx);
  4397. if (dp_srng_alloc(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE,
  4398. entries, 0)) {
  4399. dp_init_err("%pK: dp_srng_alloc failed for wbm_desc_rel_ring", soc);
  4400. goto fail1;
  4401. }
  4402. /* TCL command and status rings */
  4403. if (dp_soc_tcl_cmd_cred_srng_alloc(soc)) {
  4404. dp_init_err("%pK: dp_srng_alloc failed for tcl_cmd_ring", soc);
  4405. goto fail1;
  4406. }
  4407. if (dp_soc_tcl_status_srng_alloc(soc)) {
  4408. dp_init_err("%pK: dp_srng_alloc failed for tcl_status_ring", soc);
  4409. goto fail1;
  4410. }
  4411. /* REO reinjection ring */
  4412. entries = wlan_cfg_get_dp_soc_reo_reinject_ring_size(soc_cfg_ctx);
  4413. if (dp_srng_alloc(soc, &soc->reo_reinject_ring, REO_REINJECT,
  4414. entries, 0)) {
  4415. dp_init_err("%pK: dp_srng_alloc failed for reo_reinject_ring", soc);
  4416. goto fail1;
  4417. }
  4418. /* Rx release ring */
  4419. entries = wlan_cfg_get_dp_soc_rx_release_ring_size(soc_cfg_ctx);
  4420. if (dp_srng_alloc(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4421. entries, 0)) {
  4422. dp_init_err("%pK: dp_srng_alloc failed for rx_rel_ring", soc);
  4423. goto fail1;
  4424. }
  4425. /* Rx exception ring */
  4426. entries = wlan_cfg_get_dp_soc_reo_exception_ring_size(soc_cfg_ctx);
  4427. if (dp_srng_alloc(soc, &soc->reo_exception_ring, REO_EXCEPTION,
  4428. entries, 0)) {
  4429. dp_init_err("%pK: dp_srng_alloc failed - reo_exception", soc);
  4430. goto fail1;
  4431. }
  4432. /* REO command and status rings */
  4433. entries = wlan_cfg_get_dp_soc_reo_cmd_ring_size(soc_cfg_ctx);
  4434. if (dp_srng_alloc(soc, &soc->reo_cmd_ring, REO_CMD, entries, 0)) {
  4435. dp_init_err("%pK: dp_srng_alloc failed for reo_cmd_ring", soc);
  4436. goto fail1;
  4437. }
  4438. entries = wlan_cfg_get_dp_soc_reo_status_ring_size(soc_cfg_ctx);
  4439. if (dp_srng_alloc(soc, &soc->reo_status_ring, REO_STATUS,
  4440. entries, 0)) {
  4441. dp_init_err("%pK: dp_srng_alloc failed for reo_status_ring", soc);
  4442. goto fail1;
  4443. }
  4444. reo_dst_ring_size = wlan_cfg_get_reo_dst_ring_size(soc_cfg_ctx);
  4445. /* Disable cached desc if NSS offload is enabled */
  4446. if (wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  4447. cached = 0;
  4448. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4449. if (dp_alloc_tx_ring_pair_by_index(soc, i))
  4450. goto fail1;
  4451. }
  4452. /* IPA rings for TCL_TX and TX_COMP will be allocated here */
  4453. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4454. if (dp_alloc_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4455. goto fail1;
  4456. if (dp_ipa_alloc_alt_tx_ring(soc))
  4457. goto fail1;
  4458. }
  4459. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4460. /* Setup REO destination ring */
  4461. if (dp_srng_alloc(soc, &soc->reo_dest_ring[i], REO_DST,
  4462. reo_dst_ring_size, cached)) {
  4463. dp_init_err("%pK: dp_srng_alloc failed for reo_dest_ring", soc);
  4464. goto fail1;
  4465. }
  4466. }
  4467. if (soc->arch_ops.txrx_soc_srng_alloc) {
  4468. if (soc->arch_ops.txrx_soc_srng_alloc(soc)) {
  4469. dp_init_err("%pK: dp_srng_alloc failed for arch rings",
  4470. soc);
  4471. goto fail1;
  4472. }
  4473. }
  4474. return QDF_STATUS_SUCCESS;
  4475. fail1:
  4476. dp_soc_srng_free(soc);
  4477. return QDF_STATUS_E_NOMEM;
  4478. }
  4479. /**
  4480. * dp_soc_cfg_attach() - set target specific configuration in
  4481. * dp soc cfg.
  4482. * @soc: dp soc handle
  4483. */
  4484. void dp_soc_cfg_attach(struct dp_soc *soc)
  4485. {
  4486. int target_type;
  4487. int nss_cfg = 0;
  4488. target_type = hal_get_target_type(soc->hal_soc);
  4489. switch (target_type) {
  4490. case TARGET_TYPE_QCA6290:
  4491. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4492. REO_DST_RING_SIZE_QCA6290);
  4493. break;
  4494. case TARGET_TYPE_QCA6390:
  4495. case TARGET_TYPE_QCA6490:
  4496. case TARGET_TYPE_QCA6750:
  4497. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4498. REO_DST_RING_SIZE_QCA6290);
  4499. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4500. break;
  4501. case TARGET_TYPE_KIWI:
  4502. case TARGET_TYPE_MANGO:
  4503. case TARGET_TYPE_PEACH:
  4504. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4505. break;
  4506. case TARGET_TYPE_QCA8074:
  4507. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4508. break;
  4509. case TARGET_TYPE_QCA8074V2:
  4510. case TARGET_TYPE_QCA6018:
  4511. case TARGET_TYPE_QCA9574:
  4512. case TARGET_TYPE_QCN6122:
  4513. case TARGET_TYPE_QCA5018:
  4514. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4515. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4516. break;
  4517. case TARGET_TYPE_QCN9160:
  4518. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4519. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4520. break;
  4521. case TARGET_TYPE_QCN9000:
  4522. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4523. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4524. break;
  4525. case TARGET_TYPE_QCN9224:
  4526. case TARGET_TYPE_QCA5332:
  4527. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4528. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4529. break;
  4530. default:
  4531. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  4532. qdf_assert_always(0);
  4533. break;
  4534. }
  4535. if (soc->cdp_soc.ol_ops->get_soc_nss_cfg)
  4536. nss_cfg = soc->cdp_soc.ol_ops->get_soc_nss_cfg(soc->ctrl_psoc);
  4537. wlan_cfg_set_dp_soc_nss_cfg(soc->wlan_cfg_ctx, nss_cfg);
  4538. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  4539. wlan_cfg_set_num_tx_desc_pool(soc->wlan_cfg_ctx, 0);
  4540. wlan_cfg_set_num_tx_ext_desc_pool(soc->wlan_cfg_ctx, 0);
  4541. wlan_cfg_set_num_tx_desc(soc->wlan_cfg_ctx, 0);
  4542. wlan_cfg_set_num_tx_ext_desc(soc->wlan_cfg_ctx, 0);
  4543. soc->init_tcl_cmd_cred_ring = false;
  4544. soc->num_tcl_data_rings =
  4545. wlan_cfg_num_nss_tcl_data_rings(soc->wlan_cfg_ctx);
  4546. soc->num_reo_dest_rings =
  4547. wlan_cfg_num_nss_reo_dest_rings(soc->wlan_cfg_ctx);
  4548. } else {
  4549. soc->init_tcl_cmd_cred_ring = true;
  4550. soc->num_tx_comp_rings =
  4551. wlan_cfg_num_tx_comp_rings(soc->wlan_cfg_ctx);
  4552. soc->num_tcl_data_rings =
  4553. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  4554. soc->num_reo_dest_rings =
  4555. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  4556. }
  4557. }
  4558. void dp_pdev_set_default_reo(struct dp_pdev *pdev)
  4559. {
  4560. struct dp_soc *soc = pdev->soc;
  4561. switch (pdev->pdev_id) {
  4562. case 0:
  4563. pdev->reo_dest =
  4564. wlan_cfg_radio0_default_reo_get(soc->wlan_cfg_ctx);
  4565. break;
  4566. case 1:
  4567. pdev->reo_dest =
  4568. wlan_cfg_radio1_default_reo_get(soc->wlan_cfg_ctx);
  4569. break;
  4570. case 2:
  4571. pdev->reo_dest =
  4572. wlan_cfg_radio2_default_reo_get(soc->wlan_cfg_ctx);
  4573. break;
  4574. default:
  4575. dp_init_err("%pK: Invalid pdev_id %d for reo selection",
  4576. soc, pdev->pdev_id);
  4577. break;
  4578. }
  4579. }