dp_main.c 155 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_MONITOR_BUF:
  316. case RXDMA_BUF:
  317. /* TODO: support low_thresh interrupt */
  318. return -QDF_STATUS_E_NOENT;
  319. break;
  320. case TCL_DATA:
  321. case TCL_CMD:
  322. case REO_CMD:
  323. case SW2WBM_RELEASE:
  324. case WBM_IDLE_LINK:
  325. /* normally empty SW_TO_HW rings */
  326. return -QDF_STATUS_E_NOENT;
  327. break;
  328. case TCL_STATUS:
  329. case REO_REINJECT:
  330. case RXDMA_DST:
  331. /* misc unused rings */
  332. return -QDF_STATUS_E_NOENT;
  333. break;
  334. case CE_SRC:
  335. case CE_DST:
  336. case CE_DST_STATUS:
  337. /* CE_rings - currently handled by hif */
  338. default:
  339. return -QDF_STATUS_E_NOENT;
  340. break;
  341. }
  342. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  343. }
  344. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  345. *ring_params, int ring_type, int ring_num)
  346. {
  347. int msi_group_number;
  348. int msi_data_count;
  349. int ret;
  350. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  351. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  352. &msi_data_count, &msi_data_start,
  353. &msi_irq_start);
  354. if (ret)
  355. return;
  356. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  357. ring_num);
  358. if (msi_group_number < 0) {
  359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  360. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  361. ring_type, ring_num);
  362. ring_params->msi_addr = 0;
  363. ring_params->msi_data = 0;
  364. return;
  365. }
  366. if (msi_group_number > msi_data_count) {
  367. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  368. FL("2 msi_groups will share an msi; msi_group_num %d"),
  369. msi_group_number);
  370. QDF_ASSERT(0);
  371. }
  372. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  373. ring_params->msi_addr = addr_low;
  374. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  375. ring_params->msi_data = (msi_group_number % msi_data_count)
  376. + msi_data_start;
  377. ring_params->flags |= HAL_SRNG_MSI_INTR;
  378. }
  379. /**
  380. * dp_print_ast_stats() - Dump AST table contents
  381. * @soc: Datapath soc handle
  382. *
  383. * return void
  384. */
  385. #ifdef FEATURE_WDS
  386. static void dp_print_ast_stats(struct dp_soc *soc)
  387. {
  388. uint8_t i;
  389. uint8_t num_entries = 0;
  390. struct dp_vdev *vdev;
  391. struct dp_pdev *pdev;
  392. struct dp_peer *peer;
  393. struct dp_ast_entry *ase, *tmp_ase;
  394. DP_PRINT_STATS("AST Stats:");
  395. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  396. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  397. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  398. DP_PRINT_STATS("AST Table:");
  399. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  400. pdev = soc->pdev_list[i];
  401. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  402. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  403. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  404. DP_PRINT_STATS("%6d mac_addr = %pM"
  405. " peer_mac_addr = %pM"
  406. " type = %d"
  407. " next_hop = %d"
  408. " is_active = %d"
  409. " is_bss = %d",
  410. ++num_entries,
  411. ase->mac_addr.raw,
  412. ase->peer->mac_addr.raw,
  413. ase->type,
  414. ase->next_hop,
  415. ase->is_active,
  416. ase->is_bss);
  417. }
  418. }
  419. }
  420. }
  421. }
  422. #else
  423. static void dp_print_ast_stats(struct dp_soc *soc)
  424. {
  425. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  426. return;
  427. }
  428. #endif
  429. /*
  430. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  431. */
  432. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  433. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  434. {
  435. void *hal_soc = soc->hal_soc;
  436. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  437. /* TODO: See if we should get align size from hal */
  438. uint32_t ring_base_align = 8;
  439. struct hal_srng_params ring_params;
  440. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  441. /* TODO: Currently hal layer takes care of endianness related settings.
  442. * See if these settings need to passed from DP layer
  443. */
  444. ring_params.flags = 0;
  445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  446. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  447. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  448. srng->hal_srng = NULL;
  449. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  450. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  451. soc->osdev, soc->osdev->dev, srng->alloc_size,
  452. &(srng->base_paddr_unaligned));
  453. if (!srng->base_vaddr_unaligned) {
  454. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  455. FL("alloc failed - ring_type: %d, ring_num %d"),
  456. ring_type, ring_num);
  457. return QDF_STATUS_E_NOMEM;
  458. }
  459. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  460. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  461. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  462. ((unsigned long)(ring_params.ring_base_vaddr) -
  463. (unsigned long)srng->base_vaddr_unaligned);
  464. ring_params.num_entries = num_entries;
  465. if (soc->intr_mode == DP_INTR_MSI) {
  466. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  468. FL("Using MSI for ring_type: %d, ring_num %d"),
  469. ring_type, ring_num);
  470. } else {
  471. ring_params.msi_data = 0;
  472. ring_params.msi_addr = 0;
  473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  474. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  475. ring_type, ring_num);
  476. }
  477. /*
  478. * Setup interrupt timer and batch counter thresholds for
  479. * interrupt mitigation based on ring type
  480. */
  481. if (ring_type == REO_DST) {
  482. ring_params.intr_timer_thres_us =
  483. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  484. ring_params.intr_batch_cntr_thres_entries =
  485. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  486. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  487. ring_params.intr_timer_thres_us =
  488. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  489. ring_params.intr_batch_cntr_thres_entries =
  490. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  491. } else {
  492. ring_params.intr_timer_thres_us =
  493. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  494. ring_params.intr_batch_cntr_thres_entries =
  495. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  496. }
  497. /* Enable low threshold interrupts for rx buffer rings (regular and
  498. * monitor buffer rings.
  499. * TODO: See if this is required for any other ring
  500. */
  501. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  502. /* TODO: Setting low threshold to 1/8th of ring size
  503. * see if this needs to be configurable
  504. */
  505. ring_params.low_threshold = num_entries >> 3;
  506. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  507. ring_params.intr_timer_thres_us = 0x1000;
  508. }
  509. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  510. mac_id, &ring_params);
  511. return 0;
  512. }
  513. /**
  514. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  515. * Any buffers allocated and attached to ring entries are expected to be freed
  516. * before calling this function.
  517. */
  518. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  519. int ring_type, int ring_num)
  520. {
  521. if (!srng->hal_srng) {
  522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  523. FL("Ring type: %d, num:%d not setup"),
  524. ring_type, ring_num);
  525. return;
  526. }
  527. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  528. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  529. srng->alloc_size,
  530. srng->base_vaddr_unaligned,
  531. srng->base_paddr_unaligned, 0);
  532. srng->hal_srng = NULL;
  533. }
  534. #ifdef IPA_OFFLOAD
  535. /**
  536. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  537. * @soc: data path instance
  538. * @pdev: core txrx pdev context
  539. *
  540. * Free allocated TX buffers with WBM SRNG
  541. *
  542. * Return: none
  543. */
  544. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  545. {
  546. int idx;
  547. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  548. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  549. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  550. }
  551. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  552. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  553. }
  554. /**
  555. * dp_rx_ipa_uc_detach - free autonomy RX resources
  556. * @soc: data path instance
  557. * @pdev: core txrx pdev context
  558. *
  559. * This function will detach DP RX into main device context
  560. * will free DP Rx resources.
  561. *
  562. * Return: none
  563. */
  564. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  565. {
  566. }
  567. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. /* TX resource detach */
  570. dp_tx_ipa_uc_detach(soc, pdev);
  571. /* RX resource detach */
  572. dp_rx_ipa_uc_detach(soc, pdev);
  573. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  574. return QDF_STATUS_SUCCESS; /* success */
  575. }
  576. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  577. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  578. /**
  579. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  580. * @soc: data path instance
  581. * @pdev: Physical device handle
  582. *
  583. * Allocate TX buffer from non-cacheable memory
  584. * Attache allocated TX buffers with WBM SRNG
  585. *
  586. * Return: int
  587. */
  588. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  589. {
  590. uint32_t tx_buffer_count;
  591. uint32_t ring_base_align = 8;
  592. void *buffer_vaddr_unaligned;
  593. void *buffer_vaddr;
  594. qdf_dma_addr_t buffer_paddr_unaligned;
  595. qdf_dma_addr_t buffer_paddr;
  596. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  597. uint32_t paddr_lo;
  598. uint32_t paddr_hi;
  599. void *ring_entry;
  600. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  601. int retval = QDF_STATUS_SUCCESS;
  602. /*
  603. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  604. * unsigned int uc_tx_buf_sz =
  605. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  606. */
  607. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  608. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  610. "requested %d buffers to be posted to wbm ring",
  611. ring_size);
  612. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  613. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  614. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  615. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  616. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  617. return -ENOMEM;
  618. }
  619. hal_srng_access_start(soc->hal_soc, wbm_srng);
  620. /* Allocate TX buffers as many as possible */
  621. for (tx_buffer_count = 0;
  622. tx_buffer_count < ring_size; tx_buffer_count++) {
  623. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  624. if (!ring_entry) {
  625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  626. "Failed to get WBM ring entry\n");
  627. goto fail;
  628. }
  629. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  630. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  631. if (!buffer_vaddr_unaligned) {
  632. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  633. "IPA WDI TX buffer alloc fail %d allocated\n",
  634. tx_buffer_count);
  635. break;
  636. }
  637. buffer_vaddr = buffer_vaddr_unaligned +
  638. ((unsigned long)buffer_vaddr_unaligned %
  639. ring_base_align);
  640. buffer_paddr = buffer_paddr_unaligned +
  641. ((unsigned long)(buffer_vaddr) -
  642. (unsigned long)buffer_vaddr_unaligned);
  643. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  644. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  645. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  646. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  647. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  648. buffer_vaddr;
  649. }
  650. hal_srng_access_end(soc->hal_soc, wbm_srng);
  651. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  652. return retval;
  653. fail:
  654. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  655. return retval;
  656. }
  657. /**
  658. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  659. * @soc: data path instance
  660. * @pdev: core txrx pdev context
  661. *
  662. * This function will attach a DP RX instance into the main
  663. * device (SOC) context.
  664. *
  665. * Return: QDF_STATUS_SUCCESS: success
  666. * QDF_STATUS_E_RESOURCES: Error return
  667. */
  668. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  669. {
  670. return QDF_STATUS_SUCCESS;
  671. }
  672. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  673. {
  674. int error;
  675. /* TX resource attach */
  676. error = dp_tx_ipa_uc_attach(soc, pdev);
  677. if (error) {
  678. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  679. "DP IPA UC TX attach fail code %d\n", error);
  680. return error;
  681. }
  682. /* RX resource attach */
  683. error = dp_rx_ipa_uc_attach(soc, pdev);
  684. if (error) {
  685. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  686. "DP IPA UC RX attach fail code %d\n", error);
  687. dp_tx_ipa_uc_detach(soc, pdev);
  688. return error;
  689. }
  690. return QDF_STATUS_SUCCESS; /* success */
  691. }
  692. #else
  693. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  694. {
  695. return QDF_STATUS_SUCCESS;
  696. }
  697. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  698. {
  699. return QDF_STATUS_SUCCESS;
  700. }
  701. #endif
  702. /* TODO: Need this interface from HIF */
  703. void *hif_get_hal_handle(void *hif_handle);
  704. /*
  705. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  706. * @dp_ctx: DP SOC handle
  707. * @budget: Number of frames/descriptors that can be processed in one shot
  708. *
  709. * Return: remaining budget/quota for the soc device
  710. */
  711. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  712. {
  713. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  714. struct dp_soc *soc = int_ctx->soc;
  715. int ring = 0;
  716. uint32_t work_done = 0;
  717. int budget = dp_budget;
  718. uint8_t tx_mask = int_ctx->tx_ring_mask;
  719. uint8_t rx_mask = int_ctx->rx_ring_mask;
  720. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  721. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  722. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  723. uint32_t remaining_quota = dp_budget;
  724. /* Process Tx completion interrupts first to return back buffers */
  725. while (tx_mask) {
  726. if (tx_mask & 0x1) {
  727. work_done = dp_tx_comp_handler(soc,
  728. soc->tx_comp_ring[ring].hal_srng,
  729. remaining_quota);
  730. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  731. "tx mask 0x%x ring %d, budget %d, work_done %d",
  732. tx_mask, ring, budget, work_done);
  733. budget -= work_done;
  734. if (budget <= 0)
  735. goto budget_done;
  736. remaining_quota = budget;
  737. }
  738. tx_mask = tx_mask >> 1;
  739. ring++;
  740. }
  741. /* Process REO Exception ring interrupt */
  742. if (rx_err_mask) {
  743. work_done = dp_rx_err_process(soc,
  744. soc->reo_exception_ring.hal_srng,
  745. remaining_quota);
  746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  747. "REO Exception Ring: work_done %d budget %d",
  748. work_done, budget);
  749. budget -= work_done;
  750. if (budget <= 0) {
  751. goto budget_done;
  752. }
  753. remaining_quota = budget;
  754. }
  755. /* Process Rx WBM release ring interrupt */
  756. if (rx_wbm_rel_mask) {
  757. work_done = dp_rx_wbm_err_process(soc,
  758. soc->rx_rel_ring.hal_srng, remaining_quota);
  759. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  760. "WBM Release Ring: work_done %d budget %d",
  761. work_done, budget);
  762. budget -= work_done;
  763. if (budget <= 0) {
  764. goto budget_done;
  765. }
  766. remaining_quota = budget;
  767. }
  768. /* Process Rx interrupts */
  769. if (rx_mask) {
  770. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  771. if (rx_mask & (1 << ring)) {
  772. work_done = dp_rx_process(int_ctx,
  773. soc->reo_dest_ring[ring].hal_srng,
  774. remaining_quota);
  775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  776. "rx mask 0x%x ring %d, work_done %d budget %d",
  777. rx_mask, ring, work_done, budget);
  778. budget -= work_done;
  779. if (budget <= 0)
  780. goto budget_done;
  781. remaining_quota = budget;
  782. }
  783. }
  784. }
  785. if (reo_status_mask)
  786. dp_reo_status_ring_handler(soc);
  787. /* Process LMAC interrupts */
  788. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  789. if (soc->pdev_list[ring] == NULL)
  790. continue;
  791. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  792. work_done = dp_mon_process(soc, ring, remaining_quota);
  793. budget -= work_done;
  794. remaining_quota = budget;
  795. }
  796. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  797. work_done = dp_rxdma_err_process(soc, ring,
  798. remaining_quota);
  799. budget -= work_done;
  800. }
  801. }
  802. qdf_lro_flush(int_ctx->lro_ctx);
  803. budget_done:
  804. return dp_budget - budget;
  805. }
  806. #ifdef DP_INTR_POLL_BASED
  807. /* dp_interrupt_timer()- timer poll for interrupts
  808. *
  809. * @arg: SoC Handle
  810. *
  811. * Return:
  812. *
  813. */
  814. static void dp_interrupt_timer(void *arg)
  815. {
  816. struct dp_soc *soc = (struct dp_soc *) arg;
  817. int i;
  818. if (qdf_atomic_read(&soc->cmn_init_done)) {
  819. for (i = 0;
  820. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  821. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  822. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  823. }
  824. }
  825. /*
  826. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  827. * @txrx_soc: DP SOC handle
  828. *
  829. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  830. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  831. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  832. *
  833. * Return: 0 for success. nonzero for failure.
  834. */
  835. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  836. {
  837. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  838. int i;
  839. soc->intr_mode = DP_INTR_POLL;
  840. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  841. soc->intr_ctx[i].dp_intr_id = i;
  842. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  843. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  844. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  845. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  846. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  847. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  848. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  849. soc->intr_ctx[i].soc = soc;
  850. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  851. }
  852. qdf_timer_init(soc->osdev, &soc->int_timer,
  853. dp_interrupt_timer, (void *)soc,
  854. QDF_TIMER_TYPE_WAKE_APPS);
  855. return QDF_STATUS_SUCCESS;
  856. }
  857. #ifdef CONFIG_MCL
  858. extern int con_mode_monitor;
  859. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  860. /*
  861. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  862. * @txrx_soc: DP SOC handle
  863. *
  864. * Call the appropriate attach function based on the mode of operation.
  865. * This is a WAR for enabling monitor mode.
  866. *
  867. * Return: 0 for success. nonzero for failure.
  868. */
  869. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  870. {
  871. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  872. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  873. FL("Attach interrupts in Poll mode"));
  874. return dp_soc_interrupt_attach_poll(txrx_soc);
  875. } else {
  876. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  877. FL("Attach interrupts in MSI mode"));
  878. return dp_soc_interrupt_attach(txrx_soc);
  879. }
  880. }
  881. #else
  882. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  883. {
  884. return dp_soc_interrupt_attach_poll(txrx_soc);
  885. }
  886. #endif
  887. #endif
  888. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  889. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  890. {
  891. int j;
  892. int num_irq = 0;
  893. int tx_mask =
  894. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  895. int rx_mask =
  896. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  897. int rx_mon_mask =
  898. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  899. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  900. soc->wlan_cfg_ctx, intr_ctx_num);
  901. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  902. soc->wlan_cfg_ctx, intr_ctx_num);
  903. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  904. soc->wlan_cfg_ctx, intr_ctx_num);
  905. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  906. if (tx_mask & (1 << j)) {
  907. irq_id_map[num_irq++] =
  908. (wbm2host_tx_completions_ring1 - j);
  909. }
  910. if (rx_mask & (1 << j)) {
  911. irq_id_map[num_irq++] =
  912. (reo2host_destination_ring1 - j);
  913. }
  914. if (rx_mon_mask & (1 << j)) {
  915. irq_id_map[num_irq++] =
  916. (ppdu_end_interrupts_mac1 - j);
  917. }
  918. if (rx_wbm_rel_ring_mask & (1 << j))
  919. irq_id_map[num_irq++] = wbm2host_rx_release;
  920. if (rx_err_ring_mask & (1 << j))
  921. irq_id_map[num_irq++] = reo2host_exception;
  922. if (reo_status_ring_mask & (1 << j))
  923. irq_id_map[num_irq++] = reo2host_status;
  924. }
  925. *num_irq_r = num_irq;
  926. }
  927. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  928. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  929. int msi_vector_count, int msi_vector_start)
  930. {
  931. int tx_mask = wlan_cfg_get_tx_ring_mask(
  932. soc->wlan_cfg_ctx, intr_ctx_num);
  933. int rx_mask = wlan_cfg_get_rx_ring_mask(
  934. soc->wlan_cfg_ctx, intr_ctx_num);
  935. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  936. soc->wlan_cfg_ctx, intr_ctx_num);
  937. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  938. soc->wlan_cfg_ctx, intr_ctx_num);
  939. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  940. soc->wlan_cfg_ctx, intr_ctx_num);
  941. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  942. soc->wlan_cfg_ctx, intr_ctx_num);
  943. unsigned int vector =
  944. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  945. int num_irq = 0;
  946. soc->intr_mode = DP_INTR_MSI;
  947. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  948. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  949. irq_id_map[num_irq++] =
  950. pld_get_msi_irq(soc->osdev->dev, vector);
  951. *num_irq_r = num_irq;
  952. }
  953. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  954. int *irq_id_map, int *num_irq)
  955. {
  956. int msi_vector_count, ret;
  957. uint32_t msi_base_data, msi_vector_start;
  958. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  959. &msi_vector_count,
  960. &msi_base_data,
  961. &msi_vector_start);
  962. if (ret)
  963. return dp_soc_interrupt_map_calculate_integrated(soc,
  964. intr_ctx_num, irq_id_map, num_irq);
  965. else
  966. dp_soc_interrupt_map_calculate_msi(soc,
  967. intr_ctx_num, irq_id_map, num_irq,
  968. msi_vector_count, msi_vector_start);
  969. }
  970. /*
  971. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  972. * @txrx_soc: DP SOC handle
  973. *
  974. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  975. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  976. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  977. *
  978. * Return: 0 for success. nonzero for failure.
  979. */
  980. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  981. {
  982. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  983. int i = 0;
  984. int num_irq = 0;
  985. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  986. int ret = 0;
  987. /* Map of IRQ ids registered with one interrupt context */
  988. int irq_id_map[HIF_MAX_GRP_IRQ];
  989. int tx_mask =
  990. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  991. int rx_mask =
  992. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  993. int rx_mon_mask =
  994. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  995. int rx_err_ring_mask =
  996. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  997. int rx_wbm_rel_ring_mask =
  998. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  999. int reo_status_ring_mask =
  1000. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1001. int rxdma2host_ring_mask =
  1002. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1003. soc->intr_ctx[i].dp_intr_id = i;
  1004. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1005. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1006. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1007. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1008. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1009. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1010. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1011. soc->intr_ctx[i].soc = soc;
  1012. num_irq = 0;
  1013. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1014. &num_irq);
  1015. ret = hif_register_ext_group(soc->hif_handle,
  1016. num_irq, irq_id_map, dp_service_srngs,
  1017. &soc->intr_ctx[i], "dp_intr",
  1018. HIF_EXEC_NAPI_TYPE, 2);
  1019. if (ret) {
  1020. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1021. FL("failed, ret = %d"), ret);
  1022. return QDF_STATUS_E_FAILURE;
  1023. }
  1024. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1025. }
  1026. hif_configure_ext_group_interrupts(soc->hif_handle);
  1027. return QDF_STATUS_SUCCESS;
  1028. }
  1029. /*
  1030. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1031. * @txrx_soc: DP SOC handle
  1032. *
  1033. * Return: void
  1034. */
  1035. static void dp_soc_interrupt_detach(void *txrx_soc)
  1036. {
  1037. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1038. int i;
  1039. if (soc->intr_mode == DP_INTR_POLL) {
  1040. qdf_timer_stop(&soc->int_timer);
  1041. qdf_timer_free(&soc->int_timer);
  1042. } else {
  1043. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1044. }
  1045. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1046. soc->intr_ctx[i].tx_ring_mask = 0;
  1047. soc->intr_ctx[i].rx_ring_mask = 0;
  1048. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1049. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1050. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1051. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1052. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1053. }
  1054. }
  1055. #define AVG_MAX_MPDUS_PER_TID 128
  1056. #define AVG_TIDS_PER_CLIENT 2
  1057. #define AVG_FLOWS_PER_TID 2
  1058. #define AVG_MSDUS_PER_FLOW 128
  1059. #define AVG_MSDUS_PER_MPDU 4
  1060. /*
  1061. * Allocate and setup link descriptor pool that will be used by HW for
  1062. * various link and queue descriptors and managed by WBM
  1063. */
  1064. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1065. {
  1066. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1067. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1068. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1069. uint32_t num_mpdus_per_link_desc =
  1070. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1071. uint32_t num_msdus_per_link_desc =
  1072. hal_num_msdus_per_link_desc(soc->hal_soc);
  1073. uint32_t num_mpdu_links_per_queue_desc =
  1074. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1075. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1076. uint32_t total_link_descs, total_mem_size;
  1077. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1078. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1079. uint32_t num_link_desc_banks;
  1080. uint32_t last_bank_size = 0;
  1081. uint32_t entry_size, num_entries;
  1082. int i;
  1083. uint32_t desc_id = 0;
  1084. /* Only Tx queue descriptors are allocated from common link descriptor
  1085. * pool Rx queue descriptors are not included in this because (REO queue
  1086. * extension descriptors) they are expected to be allocated contiguously
  1087. * with REO queue descriptors
  1088. */
  1089. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1090. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1091. num_mpdu_queue_descs = num_mpdu_link_descs /
  1092. num_mpdu_links_per_queue_desc;
  1093. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1094. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1095. num_msdus_per_link_desc;
  1096. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1097. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1098. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1099. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1100. /* Round up to power of 2 */
  1101. total_link_descs = 1;
  1102. while (total_link_descs < num_entries)
  1103. total_link_descs <<= 1;
  1104. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1105. FL("total_link_descs: %u, link_desc_size: %d"),
  1106. total_link_descs, link_desc_size);
  1107. total_mem_size = total_link_descs * link_desc_size;
  1108. total_mem_size += link_desc_align;
  1109. if (total_mem_size <= max_alloc_size) {
  1110. num_link_desc_banks = 0;
  1111. last_bank_size = total_mem_size;
  1112. } else {
  1113. num_link_desc_banks = (total_mem_size) /
  1114. (max_alloc_size - link_desc_align);
  1115. last_bank_size = total_mem_size %
  1116. (max_alloc_size - link_desc_align);
  1117. }
  1118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1119. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1120. total_mem_size, num_link_desc_banks);
  1121. for (i = 0; i < num_link_desc_banks; i++) {
  1122. soc->link_desc_banks[i].base_vaddr_unaligned =
  1123. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1124. max_alloc_size,
  1125. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1126. soc->link_desc_banks[i].size = max_alloc_size;
  1127. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1128. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1129. ((unsigned long)(
  1130. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1131. link_desc_align));
  1132. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1133. soc->link_desc_banks[i].base_paddr_unaligned) +
  1134. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1135. (unsigned long)(
  1136. soc->link_desc_banks[i].base_vaddr_unaligned));
  1137. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1138. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1139. FL("Link descriptor memory alloc failed"));
  1140. goto fail;
  1141. }
  1142. }
  1143. if (last_bank_size) {
  1144. /* Allocate last bank in case total memory required is not exact
  1145. * multiple of max_alloc_size
  1146. */
  1147. soc->link_desc_banks[i].base_vaddr_unaligned =
  1148. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1149. last_bank_size,
  1150. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1151. soc->link_desc_banks[i].size = last_bank_size;
  1152. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1153. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1154. ((unsigned long)(
  1155. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1156. link_desc_align));
  1157. soc->link_desc_banks[i].base_paddr =
  1158. (unsigned long)(
  1159. soc->link_desc_banks[i].base_paddr_unaligned) +
  1160. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1161. (unsigned long)(
  1162. soc->link_desc_banks[i].base_vaddr_unaligned));
  1163. }
  1164. /* Allocate and setup link descriptor idle list for HW internal use */
  1165. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1166. total_mem_size = entry_size * total_link_descs;
  1167. if (total_mem_size <= max_alloc_size) {
  1168. void *desc;
  1169. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1170. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1171. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1172. FL("Link desc idle ring setup failed"));
  1173. goto fail;
  1174. }
  1175. hal_srng_access_start_unlocked(soc->hal_soc,
  1176. soc->wbm_idle_link_ring.hal_srng);
  1177. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1178. soc->link_desc_banks[i].base_paddr; i++) {
  1179. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1180. ((unsigned long)(
  1181. soc->link_desc_banks[i].base_vaddr) -
  1182. (unsigned long)(
  1183. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1184. / link_desc_size;
  1185. unsigned long paddr = (unsigned long)(
  1186. soc->link_desc_banks[i].base_paddr);
  1187. while (num_entries && (desc = hal_srng_src_get_next(
  1188. soc->hal_soc,
  1189. soc->wbm_idle_link_ring.hal_srng))) {
  1190. hal_set_link_desc_addr(desc,
  1191. LINK_DESC_COOKIE(desc_id, i), paddr);
  1192. num_entries--;
  1193. desc_id++;
  1194. paddr += link_desc_size;
  1195. }
  1196. }
  1197. hal_srng_access_end_unlocked(soc->hal_soc,
  1198. soc->wbm_idle_link_ring.hal_srng);
  1199. } else {
  1200. uint32_t num_scatter_bufs;
  1201. uint32_t num_entries_per_buf;
  1202. uint32_t rem_entries;
  1203. uint8_t *scatter_buf_ptr;
  1204. uint16_t scatter_buf_num;
  1205. soc->wbm_idle_scatter_buf_size =
  1206. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1207. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1208. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1209. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1210. soc->hal_soc, total_mem_size,
  1211. soc->wbm_idle_scatter_buf_size);
  1212. for (i = 0; i < num_scatter_bufs; i++) {
  1213. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1214. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1215. soc->wbm_idle_scatter_buf_size,
  1216. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1217. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1218. QDF_TRACE(QDF_MODULE_ID_DP,
  1219. QDF_TRACE_LEVEL_ERROR,
  1220. FL("Scatter list memory alloc failed"));
  1221. goto fail;
  1222. }
  1223. }
  1224. /* Populate idle list scatter buffers with link descriptor
  1225. * pointers
  1226. */
  1227. scatter_buf_num = 0;
  1228. scatter_buf_ptr = (uint8_t *)(
  1229. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1230. rem_entries = num_entries_per_buf;
  1231. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1232. soc->link_desc_banks[i].base_paddr; i++) {
  1233. uint32_t num_link_descs =
  1234. (soc->link_desc_banks[i].size -
  1235. ((unsigned long)(
  1236. soc->link_desc_banks[i].base_vaddr) -
  1237. (unsigned long)(
  1238. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1239. / link_desc_size;
  1240. unsigned long paddr = (unsigned long)(
  1241. soc->link_desc_banks[i].base_paddr);
  1242. while (num_link_descs) {
  1243. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1244. LINK_DESC_COOKIE(desc_id, i), paddr);
  1245. num_link_descs--;
  1246. desc_id++;
  1247. paddr += link_desc_size;
  1248. rem_entries--;
  1249. if (rem_entries) {
  1250. scatter_buf_ptr += entry_size;
  1251. } else {
  1252. rem_entries = num_entries_per_buf;
  1253. scatter_buf_num++;
  1254. if (scatter_buf_num >= num_scatter_bufs)
  1255. break;
  1256. scatter_buf_ptr = (uint8_t *)(
  1257. soc->wbm_idle_scatter_buf_base_vaddr[
  1258. scatter_buf_num]);
  1259. }
  1260. }
  1261. }
  1262. /* Setup link descriptor idle list in HW */
  1263. hal_setup_link_idle_list(soc->hal_soc,
  1264. soc->wbm_idle_scatter_buf_base_paddr,
  1265. soc->wbm_idle_scatter_buf_base_vaddr,
  1266. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1267. (uint32_t)(scatter_buf_ptr -
  1268. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1269. scatter_buf_num-1])), total_link_descs);
  1270. }
  1271. return 0;
  1272. fail:
  1273. if (soc->wbm_idle_link_ring.hal_srng) {
  1274. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1275. WBM_IDLE_LINK, 0);
  1276. }
  1277. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1278. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1279. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1280. soc->wbm_idle_scatter_buf_size,
  1281. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1282. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1283. }
  1284. }
  1285. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1286. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1287. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1288. soc->link_desc_banks[i].size,
  1289. soc->link_desc_banks[i].base_vaddr_unaligned,
  1290. soc->link_desc_banks[i].base_paddr_unaligned,
  1291. 0);
  1292. }
  1293. }
  1294. return QDF_STATUS_E_FAILURE;
  1295. }
  1296. /*
  1297. * Free link descriptor pool that was setup HW
  1298. */
  1299. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1300. {
  1301. int i;
  1302. if (soc->wbm_idle_link_ring.hal_srng) {
  1303. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1304. WBM_IDLE_LINK, 0);
  1305. }
  1306. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1307. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1308. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1309. soc->wbm_idle_scatter_buf_size,
  1310. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1311. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1312. }
  1313. }
  1314. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1315. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1316. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1317. soc->link_desc_banks[i].size,
  1318. soc->link_desc_banks[i].base_vaddr_unaligned,
  1319. soc->link_desc_banks[i].base_paddr_unaligned,
  1320. 0);
  1321. }
  1322. }
  1323. }
  1324. /* TODO: Following should be configurable */
  1325. #define WBM_RELEASE_RING_SIZE 64
  1326. #define TCL_CMD_RING_SIZE 32
  1327. #define TCL_STATUS_RING_SIZE 32
  1328. #if defined(QCA_WIFI_QCA6290)
  1329. #define REO_DST_RING_SIZE 1024
  1330. #else
  1331. #define REO_DST_RING_SIZE 2048
  1332. #endif
  1333. #define REO_REINJECT_RING_SIZE 32
  1334. #define RX_RELEASE_RING_SIZE 1024
  1335. #define REO_EXCEPTION_RING_SIZE 128
  1336. #define REO_CMD_RING_SIZE 32
  1337. #define REO_STATUS_RING_SIZE 32
  1338. #define RXDMA_BUF_RING_SIZE 1024
  1339. #define RXDMA_REFILL_RING_SIZE 2048
  1340. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1341. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1342. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1343. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1344. #define RXDMA_ERR_DST_RING_SIZE 1024
  1345. /*
  1346. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1347. * @soc: Datapath SOC handle
  1348. *
  1349. * This is a timer function used to age out stale WDS nodes from
  1350. * AST table
  1351. */
  1352. #ifdef FEATURE_WDS
  1353. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1354. {
  1355. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1356. struct dp_pdev *pdev;
  1357. struct dp_vdev *vdev;
  1358. struct dp_peer *peer;
  1359. struct dp_ast_entry *ase, *temp_ase;
  1360. int i;
  1361. qdf_spin_lock_bh(&soc->ast_lock);
  1362. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1363. pdev = soc->pdev_list[i];
  1364. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1365. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1366. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1367. /*
  1368. * Do not expire static ast entries
  1369. */
  1370. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1371. continue;
  1372. if (ase->is_active) {
  1373. ase->is_active = FALSE;
  1374. continue;
  1375. }
  1376. DP_STATS_INC(soc, ast.aged_out, 1);
  1377. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1378. pdev->osif_pdev,
  1379. ase->mac_addr.raw);
  1380. dp_peer_del_ast(soc, ase);
  1381. }
  1382. }
  1383. }
  1384. }
  1385. qdf_spin_unlock_bh(&soc->ast_lock);
  1386. if (qdf_atomic_read(&soc->cmn_init_done))
  1387. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1388. }
  1389. /*
  1390. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1391. * @soc: Datapath SOC handle
  1392. *
  1393. * Return: None
  1394. */
  1395. static void dp_soc_wds_attach(struct dp_soc *soc)
  1396. {
  1397. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1398. dp_wds_aging_timer_fn, (void *)soc,
  1399. QDF_TIMER_TYPE_WAKE_APPS);
  1400. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1401. }
  1402. /*
  1403. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1404. * @txrx_soc: DP SOC handle
  1405. *
  1406. * Return: None
  1407. */
  1408. static void dp_soc_wds_detach(struct dp_soc *soc)
  1409. {
  1410. qdf_timer_stop(&soc->wds_aging_timer);
  1411. qdf_timer_free(&soc->wds_aging_timer);
  1412. }
  1413. #else
  1414. static void dp_soc_wds_attach(struct dp_soc *soc)
  1415. {
  1416. }
  1417. static void dp_soc_wds_detach(struct dp_soc *soc)
  1418. {
  1419. }
  1420. #endif
  1421. /*
  1422. * dp_soc_reset_ring_map() - Reset cpu ring map
  1423. * @soc: Datapath soc handler
  1424. *
  1425. * This api resets the default cpu ring map
  1426. */
  1427. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1428. {
  1429. uint8_t i;
  1430. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1431. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1432. if (nss_config == 1) {
  1433. /*
  1434. * Setting Tx ring map for one nss offloaded radio
  1435. */
  1436. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1437. } else if (nss_config == 2) {
  1438. /*
  1439. * Setting Tx ring for two nss offloaded radios
  1440. */
  1441. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1442. } else {
  1443. /*
  1444. * Setting Tx ring map for all nss offloaded radios
  1445. */
  1446. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1447. }
  1448. }
  1449. }
  1450. #ifdef IPA_OFFLOAD
  1451. /**
  1452. * dp_reo_remap_config() - configure reo remap register value based
  1453. * nss configuration.
  1454. * based on offload_radio value below remap configuration
  1455. * get applied.
  1456. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1457. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1458. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1459. * 3 - both Radios handled by NSS (remap not required)
  1460. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1461. *
  1462. * @remap1: output parameter indicates reo remap 1 register value
  1463. * @remap2: output parameter indicates reo remap 2 register value
  1464. * Return: bool type, true if remap is configured else false.
  1465. */
  1466. static bool dp_reo_remap_config(struct dp_soc *soc,
  1467. uint32_t *remap1,
  1468. uint32_t *remap2)
  1469. {
  1470. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1471. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1472. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1473. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1474. return true;
  1475. }
  1476. #else
  1477. static bool dp_reo_remap_config(struct dp_soc *soc,
  1478. uint32_t *remap1,
  1479. uint32_t *remap2)
  1480. {
  1481. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1482. switch (offload_radio) {
  1483. case 0:
  1484. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1485. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1486. (0x3 << 18) | (0x4 << 21)) << 8;
  1487. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1488. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1489. (0x3 << 18) | (0x4 << 21)) << 8;
  1490. break;
  1491. case 1:
  1492. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1493. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1494. (0x2 << 18) | (0x3 << 21)) << 8;
  1495. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1496. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1497. (0x4 << 18) | (0x2 << 21)) << 8;
  1498. break;
  1499. case 2:
  1500. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1501. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1502. (0x1 << 18) | (0x3 << 21)) << 8;
  1503. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1504. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1505. (0x4 << 18) | (0x1 << 21)) << 8;
  1506. break;
  1507. case 3:
  1508. /* return false if both radios are offloaded to NSS */
  1509. return false;
  1510. }
  1511. return true;
  1512. }
  1513. #endif
  1514. /*
  1515. * dp_soc_cmn_setup() - Common SoC level initializion
  1516. * @soc: Datapath SOC handle
  1517. *
  1518. * This is an internal function used to setup common SOC data structures,
  1519. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1520. */
  1521. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1522. {
  1523. int i;
  1524. struct hal_reo_params reo_params;
  1525. int tx_ring_size;
  1526. int tx_comp_ring_size;
  1527. if (qdf_atomic_read(&soc->cmn_init_done))
  1528. return 0;
  1529. if (dp_peer_find_attach(soc))
  1530. goto fail0;
  1531. if (dp_hw_link_desc_pool_setup(soc))
  1532. goto fail1;
  1533. /* Setup SRNG rings */
  1534. /* Common rings */
  1535. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1536. WBM_RELEASE_RING_SIZE)) {
  1537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1538. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1539. goto fail1;
  1540. }
  1541. soc->num_tcl_data_rings = 0;
  1542. /* Tx data rings */
  1543. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1544. soc->num_tcl_data_rings =
  1545. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1546. tx_comp_ring_size =
  1547. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1548. tx_ring_size =
  1549. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1550. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1551. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1552. TCL_DATA, i, 0, tx_ring_size)) {
  1553. QDF_TRACE(QDF_MODULE_ID_DP,
  1554. QDF_TRACE_LEVEL_ERROR,
  1555. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1556. goto fail1;
  1557. }
  1558. /*
  1559. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1560. * count
  1561. */
  1562. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1563. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1564. QDF_TRACE(QDF_MODULE_ID_DP,
  1565. QDF_TRACE_LEVEL_ERROR,
  1566. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1567. goto fail1;
  1568. }
  1569. }
  1570. } else {
  1571. /* This will be incremented during per pdev ring setup */
  1572. soc->num_tcl_data_rings = 0;
  1573. }
  1574. if (dp_tx_soc_attach(soc)) {
  1575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1576. FL("dp_tx_soc_attach failed"));
  1577. goto fail1;
  1578. }
  1579. /* TCL command and status rings */
  1580. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1581. TCL_CMD_RING_SIZE)) {
  1582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1583. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1584. goto fail1;
  1585. }
  1586. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1587. TCL_STATUS_RING_SIZE)) {
  1588. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1589. FL("dp_srng_setup failed for tcl_status_ring"));
  1590. goto fail1;
  1591. }
  1592. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1593. * descriptors
  1594. */
  1595. /* Rx data rings */
  1596. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1597. soc->num_reo_dest_rings =
  1598. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1599. QDF_TRACE(QDF_MODULE_ID_DP,
  1600. QDF_TRACE_LEVEL_ERROR,
  1601. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1602. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1603. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1604. i, 0, REO_DST_RING_SIZE)) {
  1605. QDF_TRACE(QDF_MODULE_ID_DP,
  1606. QDF_TRACE_LEVEL_ERROR,
  1607. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1608. goto fail1;
  1609. }
  1610. }
  1611. } else {
  1612. /* This will be incremented during per pdev ring setup */
  1613. soc->num_reo_dest_rings = 0;
  1614. }
  1615. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1616. /* REO reinjection ring */
  1617. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1618. REO_REINJECT_RING_SIZE)) {
  1619. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1620. FL("dp_srng_setup failed for reo_reinject_ring"));
  1621. goto fail1;
  1622. }
  1623. /* Rx release ring */
  1624. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1625. RX_RELEASE_RING_SIZE)) {
  1626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1627. FL("dp_srng_setup failed for rx_rel_ring"));
  1628. goto fail1;
  1629. }
  1630. /* Rx exception ring */
  1631. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1632. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1634. FL("dp_srng_setup failed for reo_exception_ring"));
  1635. goto fail1;
  1636. }
  1637. /* REO command and status rings */
  1638. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1639. REO_CMD_RING_SIZE)) {
  1640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1641. FL("dp_srng_setup failed for reo_cmd_ring"));
  1642. goto fail1;
  1643. }
  1644. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1645. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1646. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1647. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1648. REO_STATUS_RING_SIZE)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1650. FL("dp_srng_setup failed for reo_status_ring"));
  1651. goto fail1;
  1652. }
  1653. qdf_spinlock_create(&soc->ast_lock);
  1654. dp_soc_wds_attach(soc);
  1655. /* Reset the cpu ring map if radio is NSS offloaded */
  1656. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1657. dp_soc_reset_cpu_ring_map(soc);
  1658. }
  1659. /* Setup HW REO */
  1660. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1661. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1662. /*
  1663. * Reo ring remap is not required if both radios
  1664. * are offloaded to NSS
  1665. */
  1666. if (!dp_reo_remap_config(soc,
  1667. &reo_params.remap1,
  1668. &reo_params.remap2))
  1669. goto out;
  1670. reo_params.rx_hash_enabled = true;
  1671. }
  1672. out:
  1673. hal_reo_setup(soc->hal_soc, &reo_params);
  1674. qdf_atomic_set(&soc->cmn_init_done, 1);
  1675. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1676. return 0;
  1677. fail1:
  1678. /*
  1679. * Cleanup will be done as part of soc_detach, which will
  1680. * be called on pdev attach failure
  1681. */
  1682. fail0:
  1683. return QDF_STATUS_E_FAILURE;
  1684. }
  1685. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1686. static void dp_lro_hash_setup(struct dp_soc *soc)
  1687. {
  1688. struct cdp_lro_hash_config lro_hash;
  1689. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1690. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1691. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1692. FL("LRO disabled RX hash disabled"));
  1693. return;
  1694. }
  1695. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1696. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1697. lro_hash.lro_enable = 1;
  1698. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1699. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1700. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1701. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1702. }
  1703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1704. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1705. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1706. LRO_IPV4_SEED_ARR_SZ));
  1707. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1708. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1709. LRO_IPV6_SEED_ARR_SZ));
  1710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1711. "lro_hash: lro_enable: 0x%x"
  1712. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1713. lro_hash.lro_enable, lro_hash.tcp_flag,
  1714. lro_hash.tcp_flag_mask);
  1715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1716. FL("lro_hash: toeplitz_hash_ipv4:"));
  1717. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1718. QDF_TRACE_LEVEL_ERROR,
  1719. (void *)lro_hash.toeplitz_hash_ipv4,
  1720. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1721. LRO_IPV4_SEED_ARR_SZ));
  1722. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1723. FL("lro_hash: toeplitz_hash_ipv6:"));
  1724. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1725. QDF_TRACE_LEVEL_ERROR,
  1726. (void *)lro_hash.toeplitz_hash_ipv6,
  1727. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1728. LRO_IPV6_SEED_ARR_SZ));
  1729. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1730. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1731. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1732. (soc->osif_soc, &lro_hash);
  1733. }
  1734. /*
  1735. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1736. * @soc: data path SoC handle
  1737. * @pdev: Physical device handle
  1738. *
  1739. * Return: 0 - success, > 0 - failure
  1740. */
  1741. #ifdef QCA_HOST2FW_RXBUF_RING
  1742. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1743. struct dp_pdev *pdev)
  1744. {
  1745. int max_mac_rings =
  1746. wlan_cfg_get_num_mac_rings
  1747. (pdev->wlan_cfg_ctx);
  1748. int i;
  1749. for (i = 0; i < max_mac_rings; i++) {
  1750. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1751. "%s: pdev_id %d mac_id %d\n",
  1752. __func__, pdev->pdev_id, i);
  1753. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1754. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1755. QDF_TRACE(QDF_MODULE_ID_DP,
  1756. QDF_TRACE_LEVEL_ERROR,
  1757. FL("failed rx mac ring setup"));
  1758. return QDF_STATUS_E_FAILURE;
  1759. }
  1760. }
  1761. return QDF_STATUS_SUCCESS;
  1762. }
  1763. #else
  1764. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1765. struct dp_pdev *pdev)
  1766. {
  1767. return QDF_STATUS_SUCCESS;
  1768. }
  1769. #endif
  1770. /**
  1771. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1772. * @pdev - DP_PDEV handle
  1773. *
  1774. * Return: void
  1775. */
  1776. static inline void
  1777. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1778. {
  1779. uint8_t map_id;
  1780. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1781. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1782. sizeof(default_dscp_tid_map));
  1783. }
  1784. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1785. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1786. pdev->dscp_tid_map[map_id],
  1787. map_id);
  1788. }
  1789. }
  1790. /*
  1791. * dp_reset_intr_mask() - reset interrupt mask
  1792. * @dp_soc - DP Soc handle
  1793. * @dp_pdev - DP pdev handle
  1794. *
  1795. * Return: Return void
  1796. */
  1797. static inline
  1798. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1799. {
  1800. /*
  1801. * We will set the interrupt mask to zero for NSS offloaded radio
  1802. */
  1803. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1804. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1805. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1806. }
  1807. /*
  1808. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1809. * @soc: data path SoC handle
  1810. *
  1811. * Return: none
  1812. */
  1813. #ifdef IPA_OFFLOAD
  1814. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1815. struct dp_pdev *pdev)
  1816. {
  1817. void *hal_srng;
  1818. struct hal_srng_params srng_params;
  1819. qdf_dma_addr_t hp_addr, tp_addr;
  1820. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1821. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1822. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1823. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1824. srng_params.ring_base_paddr;
  1825. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1826. srng_params.ring_base_vaddr;
  1827. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1828. srng_params.num_entries * srng_params.entry_size;
  1829. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1830. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1831. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1832. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1833. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1834. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1835. srng_params.ring_base_paddr;
  1836. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1837. srng_params.ring_base_vaddr;
  1838. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1839. srng_params.num_entries * srng_params.entry_size;
  1840. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1841. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1842. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1843. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1844. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1845. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1846. srng_params.ring_base_paddr;
  1847. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1848. srng_params.ring_base_vaddr;
  1849. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1850. srng_params.num_entries * srng_params.entry_size;
  1851. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1852. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1853. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1854. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1855. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1856. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1857. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1858. __func__);
  1859. return -EFAULT;
  1860. }
  1861. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1862. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1863. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1864. srng_params.ring_base_paddr;
  1865. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1866. srng_params.ring_base_vaddr;
  1867. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1868. srng_params.num_entries * srng_params.entry_size;
  1869. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1870. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1871. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1872. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1873. "_entries:%d, hp_addr:%pK\n",
  1874. __func__,
  1875. (void *)srng_params.ring_base_paddr,
  1876. (void *)srng_params.ring_base_vaddr,
  1877. srng_params.num_entries,
  1878. (void *)hp_addr);
  1879. return 0;
  1880. }
  1881. #else
  1882. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1883. struct dp_pdev *pdev)
  1884. {
  1885. return 0;
  1886. }
  1887. #endif
  1888. /*
  1889. * dp_pdev_attach_wifi3() - attach txrx pdev
  1890. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1891. * @txrx_soc: Datapath SOC handle
  1892. * @htc_handle: HTC handle for host-target interface
  1893. * @qdf_osdev: QDF OS device
  1894. * @pdev_id: PDEV ID
  1895. *
  1896. * Return: DP PDEV handle on success, NULL on failure
  1897. */
  1898. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1899. struct cdp_cfg *ctrl_pdev,
  1900. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1901. {
  1902. int tx_ring_size;
  1903. int tx_comp_ring_size;
  1904. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1905. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1906. if (!pdev) {
  1907. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1908. FL("DP PDEV memory allocation failed"));
  1909. goto fail0;
  1910. }
  1911. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1912. if (!pdev->wlan_cfg_ctx) {
  1913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1914. FL("pdev cfg_attach failed"));
  1915. qdf_mem_free(pdev);
  1916. goto fail0;
  1917. }
  1918. /*
  1919. * set nss pdev config based on soc config
  1920. */
  1921. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1922. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1923. pdev->soc = soc;
  1924. pdev->osif_pdev = ctrl_pdev;
  1925. pdev->pdev_id = pdev_id;
  1926. soc->pdev_list[pdev_id] = pdev;
  1927. soc->pdev_count++;
  1928. TAILQ_INIT(&pdev->vdev_list);
  1929. pdev->vdev_count = 0;
  1930. qdf_spinlock_create(&pdev->tx_mutex);
  1931. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1932. TAILQ_INIT(&pdev->neighbour_peers_list);
  1933. if (dp_soc_cmn_setup(soc)) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1935. FL("dp_soc_cmn_setup failed"));
  1936. goto fail1;
  1937. }
  1938. /* Setup per PDEV TCL rings if configured */
  1939. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1940. tx_ring_size =
  1941. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1942. tx_comp_ring_size =
  1943. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1944. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1945. pdev_id, pdev_id, tx_ring_size)) {
  1946. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1947. FL("dp_srng_setup failed for tcl_data_ring"));
  1948. goto fail1;
  1949. }
  1950. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1951. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1952. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1953. FL("dp_srng_setup failed for tx_comp_ring"));
  1954. goto fail1;
  1955. }
  1956. soc->num_tcl_data_rings++;
  1957. }
  1958. /* Tx specific init */
  1959. if (dp_tx_pdev_attach(pdev)) {
  1960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1961. FL("dp_tx_pdev_attach failed"));
  1962. goto fail1;
  1963. }
  1964. /* Setup per PDEV REO rings if configured */
  1965. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1966. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1967. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1968. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1969. FL("dp_srng_setup failed for reo_dest_ringn"));
  1970. goto fail1;
  1971. }
  1972. soc->num_reo_dest_rings++;
  1973. }
  1974. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1975. RXDMA_REFILL_RING_SIZE)) {
  1976. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1977. FL("dp_srng_setup failed rx refill ring"));
  1978. goto fail1;
  1979. }
  1980. if (dp_rxdma_ring_setup(soc, pdev)) {
  1981. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1982. FL("RXDMA ring config failed"));
  1983. goto fail1;
  1984. }
  1985. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1986. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1987. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1988. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1989. goto fail1;
  1990. }
  1991. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1992. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1993. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1994. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1995. goto fail1;
  1996. }
  1997. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1998. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1999. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2001. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2002. goto fail1;
  2003. }
  2004. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2005. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2006. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2007. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2008. goto fail1;
  2009. }
  2010. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2011. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2013. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2014. goto fail1;
  2015. }
  2016. if (dp_ipa_ring_resource_setup(soc, pdev))
  2017. goto fail1;
  2018. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2019. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2020. "%s: dp_ipa_uc_attach failed\n", __func__);
  2021. goto fail1;
  2022. }
  2023. /* Rx specific init */
  2024. if (dp_rx_pdev_attach(pdev)) {
  2025. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2026. FL("dp_rx_pdev_attach failed "));
  2027. goto fail0;
  2028. }
  2029. DP_STATS_INIT(pdev);
  2030. #ifndef CONFIG_WIN
  2031. /* MCL */
  2032. dp_local_peer_id_pool_init(pdev);
  2033. #endif
  2034. dp_dscp_tid_map_setup(pdev);
  2035. /* Rx monitor mode specific init */
  2036. if (dp_rx_pdev_mon_attach(pdev)) {
  2037. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2038. "dp_rx_pdev_attach failed\n");
  2039. goto fail1;
  2040. }
  2041. if (dp_wdi_event_attach(pdev)) {
  2042. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2043. "dp_wdi_evet_attach failed\n");
  2044. goto fail1;
  2045. }
  2046. /* set the reo destination during initialization */
  2047. pdev->reo_dest = pdev->pdev_id + 1;
  2048. /*
  2049. * reset the interrupt mask for offloaded radio
  2050. */
  2051. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2052. dp_soc_reset_intr_mask(soc, pdev);
  2053. }
  2054. return (struct cdp_pdev *)pdev;
  2055. fail1:
  2056. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2057. fail0:
  2058. return NULL;
  2059. }
  2060. /*
  2061. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2062. * @soc: data path SoC handle
  2063. * @pdev: Physical device handle
  2064. *
  2065. * Return: void
  2066. */
  2067. #ifdef QCA_HOST2FW_RXBUF_RING
  2068. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2069. struct dp_pdev *pdev)
  2070. {
  2071. int max_mac_rings =
  2072. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2073. int i;
  2074. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2075. max_mac_rings : MAX_RX_MAC_RINGS;
  2076. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2077. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2078. RXDMA_BUF, 1);
  2079. }
  2080. #else
  2081. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2082. struct dp_pdev *pdev)
  2083. {
  2084. }
  2085. #endif
  2086. /*
  2087. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2088. * @pdev: device object
  2089. *
  2090. * Return: void
  2091. */
  2092. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2093. {
  2094. struct dp_neighbour_peer *peer = NULL;
  2095. struct dp_neighbour_peer *temp_peer = NULL;
  2096. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2097. neighbour_peer_list_elem, temp_peer) {
  2098. /* delete this peer from the list */
  2099. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2100. peer, neighbour_peer_list_elem);
  2101. qdf_mem_free(peer);
  2102. }
  2103. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2104. }
  2105. /*
  2106. * dp_pdev_detach_wifi3() - detach txrx pdev
  2107. * @txrx_pdev: Datapath PDEV handle
  2108. * @force: Force detach
  2109. *
  2110. */
  2111. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2112. {
  2113. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2114. struct dp_soc *soc = pdev->soc;
  2115. dp_wdi_event_detach(pdev);
  2116. dp_tx_pdev_detach(pdev);
  2117. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2118. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2119. TCL_DATA, pdev->pdev_id);
  2120. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2121. WBM2SW_RELEASE, pdev->pdev_id);
  2122. }
  2123. dp_rx_pdev_detach(pdev);
  2124. dp_rx_pdev_mon_detach(pdev);
  2125. dp_neighbour_peers_detach(pdev);
  2126. qdf_spinlock_destroy(&pdev->tx_mutex);
  2127. dp_ipa_uc_detach(soc, pdev);
  2128. /* Cleanup per PDEV REO rings if configured */
  2129. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2130. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2131. REO_DST, pdev->pdev_id);
  2132. }
  2133. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2134. dp_rxdma_ring_cleanup(soc, pdev);
  2135. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2136. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2137. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2138. RXDMA_MONITOR_STATUS, 0);
  2139. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2140. RXDMA_MONITOR_DESC, 0);
  2141. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2142. soc->pdev_list[pdev->pdev_id] = NULL;
  2143. soc->pdev_count--;
  2144. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2145. qdf_mem_free(pdev);
  2146. }
  2147. /*
  2148. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2149. * @soc: DP SOC handle
  2150. */
  2151. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2152. {
  2153. struct reo_desc_list_node *desc;
  2154. struct dp_rx_tid *rx_tid;
  2155. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2156. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2157. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2158. rx_tid = &desc->rx_tid;
  2159. qdf_mem_unmap_nbytes_single(soc->osdev,
  2160. rx_tid->hw_qdesc_paddr,
  2161. QDF_DMA_BIDIRECTIONAL,
  2162. rx_tid->hw_qdesc_alloc_size);
  2163. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2164. qdf_mem_free(desc);
  2165. }
  2166. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2167. qdf_list_destroy(&soc->reo_desc_freelist);
  2168. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2169. }
  2170. /*
  2171. * dp_soc_detach_wifi3() - Detach txrx SOC
  2172. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2173. */
  2174. static void dp_soc_detach_wifi3(void *txrx_soc)
  2175. {
  2176. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2177. int i;
  2178. qdf_atomic_set(&soc->cmn_init_done, 0);
  2179. qdf_flush_work(0, &soc->htt_stats.work);
  2180. qdf_disable_work(0, &soc->htt_stats.work);
  2181. /* Free pending htt stats messages */
  2182. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2183. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2184. if (soc->pdev_list[i])
  2185. dp_pdev_detach_wifi3(
  2186. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2187. }
  2188. dp_peer_find_detach(soc);
  2189. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2190. * SW descriptors
  2191. */
  2192. /* Free the ring memories */
  2193. /* Common rings */
  2194. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2195. dp_tx_soc_detach(soc);
  2196. /* Tx data rings */
  2197. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2198. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2199. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2200. TCL_DATA, i);
  2201. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2202. WBM2SW_RELEASE, i);
  2203. }
  2204. }
  2205. /* TCL command and status rings */
  2206. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2207. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2208. /* Rx data rings */
  2209. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2210. soc->num_reo_dest_rings =
  2211. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2212. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2213. /* TODO: Get number of rings and ring sizes
  2214. * from wlan_cfg
  2215. */
  2216. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2217. REO_DST, i);
  2218. }
  2219. }
  2220. /* REO reinjection ring */
  2221. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2222. /* Rx release ring */
  2223. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2224. /* Rx exception ring */
  2225. /* TODO: Better to store ring_type and ring_num in
  2226. * dp_srng during setup
  2227. */
  2228. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2229. /* REO command and status rings */
  2230. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2231. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2232. dp_hw_link_desc_pool_cleanup(soc);
  2233. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2234. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2235. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2236. htt_soc_detach(soc->htt_handle);
  2237. dp_reo_cmdlist_destroy(soc);
  2238. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2239. dp_reo_desc_freelist_destroy(soc);
  2240. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2241. dp_soc_wds_detach(soc);
  2242. qdf_spinlock_destroy(&soc->ast_lock);
  2243. qdf_mem_free(soc);
  2244. }
  2245. /*
  2246. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2247. * @soc: data path SoC handle
  2248. * @pdev: physical device handle
  2249. *
  2250. * Return: void
  2251. */
  2252. #ifdef IPA_OFFLOAD
  2253. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2254. struct dp_pdev *pdev)
  2255. {
  2256. htt_srng_setup(soc->htt_handle, 0,
  2257. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2258. }
  2259. #else
  2260. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2261. struct dp_pdev *pdev)
  2262. {
  2263. }
  2264. #endif
  2265. /*
  2266. * dp_rxdma_ring_config() - configure the RX DMA rings
  2267. *
  2268. * This function is used to configure the MAC rings.
  2269. * On MCL host provides buffers in Host2FW ring
  2270. * FW refills (copies) buffers to the ring and updates
  2271. * ring_idx in register
  2272. *
  2273. * @soc: data path SoC handle
  2274. *
  2275. * Return: void
  2276. */
  2277. #ifdef QCA_HOST2FW_RXBUF_RING
  2278. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2279. {
  2280. int i;
  2281. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2282. struct dp_pdev *pdev = soc->pdev_list[i];
  2283. if (pdev) {
  2284. int mac_id = 0;
  2285. int j;
  2286. bool dbs_enable = 0;
  2287. int max_mac_rings =
  2288. wlan_cfg_get_num_mac_rings
  2289. (pdev->wlan_cfg_ctx);
  2290. htt_srng_setup(soc->htt_handle, 0,
  2291. pdev->rx_refill_buf_ring.hal_srng,
  2292. RXDMA_BUF);
  2293. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2294. if (soc->cdp_soc.ol_ops->
  2295. is_hw_dbs_2x2_capable) {
  2296. dbs_enable = soc->cdp_soc.ol_ops->
  2297. is_hw_dbs_2x2_capable(soc->psoc);
  2298. }
  2299. if (dbs_enable) {
  2300. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2301. QDF_TRACE_LEVEL_ERROR,
  2302. FL("DBS enabled max_mac_rings %d\n"),
  2303. max_mac_rings);
  2304. } else {
  2305. max_mac_rings = 1;
  2306. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2307. QDF_TRACE_LEVEL_ERROR,
  2308. FL("DBS disabled, max_mac_rings %d\n"),
  2309. max_mac_rings);
  2310. }
  2311. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2312. FL("pdev_id %d max_mac_rings %d\n"),
  2313. pdev->pdev_id, max_mac_rings);
  2314. for (j = 0; j < max_mac_rings; j++) {
  2315. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2316. QDF_TRACE_LEVEL_ERROR,
  2317. FL("mac_id %d\n"), mac_id);
  2318. htt_srng_setup(soc->htt_handle, mac_id,
  2319. pdev->rx_mac_buf_ring[j]
  2320. .hal_srng,
  2321. RXDMA_BUF);
  2322. mac_id++;
  2323. }
  2324. /* Configure monitor mode rings */
  2325. htt_srng_setup(soc->htt_handle, i,
  2326. pdev->rxdma_mon_buf_ring.hal_srng,
  2327. RXDMA_MONITOR_BUF);
  2328. htt_srng_setup(soc->htt_handle, i,
  2329. pdev->rxdma_mon_dst_ring.hal_srng,
  2330. RXDMA_MONITOR_DST);
  2331. htt_srng_setup(soc->htt_handle, i,
  2332. pdev->rxdma_mon_status_ring.hal_srng,
  2333. RXDMA_MONITOR_STATUS);
  2334. htt_srng_setup(soc->htt_handle, i,
  2335. pdev->rxdma_mon_desc_ring.hal_srng,
  2336. RXDMA_MONITOR_DESC);
  2337. htt_srng_setup(soc->htt_handle, i,
  2338. pdev->rxdma_err_dst_ring.hal_srng,
  2339. RXDMA_DST);
  2340. }
  2341. }
  2342. }
  2343. #else
  2344. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2345. {
  2346. int i;
  2347. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2348. struct dp_pdev *pdev = soc->pdev_list[i];
  2349. if (pdev) {
  2350. htt_srng_setup(soc->htt_handle, i,
  2351. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2352. htt_srng_setup(soc->htt_handle, i,
  2353. pdev->rxdma_mon_buf_ring.hal_srng,
  2354. RXDMA_MONITOR_BUF);
  2355. htt_srng_setup(soc->htt_handle, i,
  2356. pdev->rxdma_mon_dst_ring.hal_srng,
  2357. RXDMA_MONITOR_DST);
  2358. htt_srng_setup(soc->htt_handle, i,
  2359. pdev->rxdma_mon_status_ring.hal_srng,
  2360. RXDMA_MONITOR_STATUS);
  2361. htt_srng_setup(soc->htt_handle, i,
  2362. pdev->rxdma_mon_desc_ring.hal_srng,
  2363. RXDMA_MONITOR_DESC);
  2364. htt_srng_setup(soc->htt_handle, i,
  2365. pdev->rxdma_err_dst_ring.hal_srng,
  2366. RXDMA_DST);
  2367. }
  2368. }
  2369. }
  2370. #endif
  2371. /*
  2372. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2373. * @txrx_soc: Datapath SOC handle
  2374. */
  2375. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2376. {
  2377. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2378. htt_soc_attach_target(soc->htt_handle);
  2379. dp_rxdma_ring_config(soc);
  2380. DP_STATS_INIT(soc);
  2381. /* initialize work queue for stats processing */
  2382. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2383. return 0;
  2384. }
  2385. /*
  2386. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2387. * @txrx_soc: Datapath SOC handle
  2388. */
  2389. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2390. {
  2391. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2392. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2393. }
  2394. /*
  2395. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2396. * @txrx_soc: Datapath SOC handle
  2397. * @nss_cfg: nss config
  2398. */
  2399. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2400. {
  2401. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2402. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2403. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2404. FL("nss-wifi<0> nss config is enabled"));
  2405. }
  2406. /*
  2407. * dp_vdev_attach_wifi3() - attach txrx vdev
  2408. * @txrx_pdev: Datapath PDEV handle
  2409. * @vdev_mac_addr: MAC address of the virtual interface
  2410. * @vdev_id: VDEV Id
  2411. * @wlan_op_mode: VDEV operating mode
  2412. *
  2413. * Return: DP VDEV handle on success, NULL on failure
  2414. */
  2415. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2416. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2417. {
  2418. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2419. struct dp_soc *soc = pdev->soc;
  2420. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2421. int tx_ring_size;
  2422. if (!vdev) {
  2423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2424. FL("DP VDEV memory allocation failed"));
  2425. goto fail0;
  2426. }
  2427. vdev->pdev = pdev;
  2428. vdev->vdev_id = vdev_id;
  2429. vdev->opmode = op_mode;
  2430. vdev->osdev = soc->osdev;
  2431. vdev->osif_rx = NULL;
  2432. vdev->osif_rsim_rx_decap = NULL;
  2433. vdev->osif_get_key = NULL;
  2434. vdev->osif_rx_mon = NULL;
  2435. vdev->osif_tx_free_ext = NULL;
  2436. vdev->osif_vdev = NULL;
  2437. vdev->delete.pending = 0;
  2438. vdev->safemode = 0;
  2439. vdev->drop_unenc = 1;
  2440. #ifdef notyet
  2441. vdev->filters_num = 0;
  2442. #endif
  2443. qdf_mem_copy(
  2444. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2445. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2446. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2447. vdev->dscp_tid_map_id = 0;
  2448. vdev->mcast_enhancement_en = 0;
  2449. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2450. /* TODO: Initialize default HTT meta data that will be used in
  2451. * TCL descriptors for packets transmitted from this VDEV
  2452. */
  2453. TAILQ_INIT(&vdev->peer_list);
  2454. /* add this vdev into the pdev's list */
  2455. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2456. pdev->vdev_count++;
  2457. dp_tx_vdev_attach(vdev);
  2458. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2459. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2460. goto fail1;
  2461. if ((soc->intr_mode == DP_INTR_POLL) &&
  2462. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2463. if (pdev->vdev_count == 1)
  2464. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2465. }
  2466. dp_lro_hash_setup(soc);
  2467. /* LRO */
  2468. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2469. wlan_op_mode_sta == vdev->opmode)
  2470. vdev->lro_enable = true;
  2471. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2472. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2474. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2475. DP_STATS_INIT(vdev);
  2476. return (struct cdp_vdev *)vdev;
  2477. fail1:
  2478. dp_tx_vdev_detach(vdev);
  2479. qdf_mem_free(vdev);
  2480. fail0:
  2481. return NULL;
  2482. }
  2483. /**
  2484. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2485. * @vdev: Datapath VDEV handle
  2486. * @osif_vdev: OSIF vdev handle
  2487. * @txrx_ops: Tx and Rx operations
  2488. *
  2489. * Return: DP VDEV handle on success, NULL on failure
  2490. */
  2491. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2492. void *osif_vdev,
  2493. struct ol_txrx_ops *txrx_ops)
  2494. {
  2495. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2496. vdev->osif_vdev = osif_vdev;
  2497. vdev->osif_rx = txrx_ops->rx.rx;
  2498. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2499. vdev->osif_get_key = txrx_ops->get_key;
  2500. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2501. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2502. #ifdef notyet
  2503. #if ATH_SUPPORT_WAPI
  2504. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2505. #endif
  2506. #endif
  2507. #ifdef UMAC_SUPPORT_PROXY_ARP
  2508. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2509. #endif
  2510. vdev->me_convert = txrx_ops->me_convert;
  2511. /* TODO: Enable the following once Tx code is integrated */
  2512. txrx_ops->tx.tx = dp_tx_send;
  2513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2514. "DP Vdev Register success");
  2515. }
  2516. /*
  2517. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2518. * @txrx_vdev: Datapath VDEV handle
  2519. * @callback: Callback OL_IF on completion of detach
  2520. * @cb_context: Callback context
  2521. *
  2522. */
  2523. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2524. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2525. {
  2526. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2527. struct dp_pdev *pdev = vdev->pdev;
  2528. struct dp_soc *soc = pdev->soc;
  2529. /* preconditions */
  2530. qdf_assert(vdev);
  2531. /* remove the vdev from its parent pdev's list */
  2532. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2533. /*
  2534. * Use peer_ref_mutex while accessing peer_list, in case
  2535. * a peer is in the process of being removed from the list.
  2536. */
  2537. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2538. /* check that the vdev has no peers allocated */
  2539. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2540. /* debug print - will be removed later */
  2541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2542. FL("not deleting vdev object %pK (%pM)"
  2543. "until deletion finishes for all its peers"),
  2544. vdev, vdev->mac_addr.raw);
  2545. /* indicate that the vdev needs to be deleted */
  2546. vdev->delete.pending = 1;
  2547. vdev->delete.callback = callback;
  2548. vdev->delete.context = cb_context;
  2549. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2550. return;
  2551. }
  2552. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2553. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2554. vdev->vdev_id);
  2555. dp_tx_vdev_detach(vdev);
  2556. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2557. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2558. qdf_mem_free(vdev);
  2559. if (callback)
  2560. callback(cb_context);
  2561. }
  2562. /*
  2563. * dp_peer_create_wifi3() - attach txrx peer
  2564. * @txrx_vdev: Datapath VDEV handle
  2565. * @peer_mac_addr: Peer MAC address
  2566. *
  2567. * Return: DP peeer handle on success, NULL on failure
  2568. */
  2569. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2570. uint8_t *peer_mac_addr)
  2571. {
  2572. struct dp_peer *peer;
  2573. int i;
  2574. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2575. struct dp_pdev *pdev;
  2576. struct dp_soc *soc;
  2577. /* preconditions */
  2578. qdf_assert(vdev);
  2579. qdf_assert(peer_mac_addr);
  2580. pdev = vdev->pdev;
  2581. soc = pdev->soc;
  2582. #ifdef notyet
  2583. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2584. soc->mempool_ol_ath_peer);
  2585. #else
  2586. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2587. #endif
  2588. if (!peer)
  2589. return NULL; /* failure */
  2590. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2591. TAILQ_INIT(&peer->ast_entry_list);
  2592. /* store provided params */
  2593. peer->vdev = vdev;
  2594. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2595. qdf_spinlock_create(&peer->peer_info_lock);
  2596. qdf_mem_copy(
  2597. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2598. /* TODO: See of rx_opt_proc is really required */
  2599. peer->rx_opt_proc = soc->rx_opt_proc;
  2600. /* initialize the peer_id */
  2601. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2602. peer->peer_ids[i] = HTT_INVALID_PEER;
  2603. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2604. qdf_atomic_init(&peer->ref_cnt);
  2605. /* keep one reference for attach */
  2606. qdf_atomic_inc(&peer->ref_cnt);
  2607. /* add this peer into the vdev's list */
  2608. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2609. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2610. /* TODO: See if hash based search is required */
  2611. dp_peer_find_hash_add(soc, peer);
  2612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2613. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2614. vdev, peer, peer->mac_addr.raw,
  2615. qdf_atomic_read(&peer->ref_cnt));
  2616. /*
  2617. * For every peer MAp message search and set if bss_peer
  2618. */
  2619. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2621. "vdev bss_peer!!!!");
  2622. peer->bss_peer = 1;
  2623. vdev->vap_bss_peer = peer;
  2624. }
  2625. #ifndef CONFIG_WIN
  2626. dp_local_peer_id_alloc(pdev, peer);
  2627. #endif
  2628. DP_STATS_INIT(peer);
  2629. return (void *)peer;
  2630. }
  2631. /*
  2632. * dp_peer_setup_wifi3() - initialize the peer
  2633. * @vdev_hdl: virtual device object
  2634. * @peer: Peer object
  2635. *
  2636. * Return: void
  2637. */
  2638. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2639. {
  2640. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2641. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2642. struct dp_pdev *pdev;
  2643. struct dp_soc *soc;
  2644. bool hash_based = 0;
  2645. enum cdp_host_reo_dest_ring reo_dest;
  2646. /* preconditions */
  2647. qdf_assert(vdev);
  2648. qdf_assert(peer);
  2649. pdev = vdev->pdev;
  2650. soc = pdev->soc;
  2651. dp_peer_rx_init(pdev, peer);
  2652. peer->last_assoc_rcvd = 0;
  2653. peer->last_disassoc_rcvd = 0;
  2654. peer->last_deauth_rcvd = 0;
  2655. /*
  2656. * hash based steering is disabled for Radios which are offloaded
  2657. * to NSS
  2658. */
  2659. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2660. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2662. FL("hash based steering for pdev: %d is %d\n"),
  2663. pdev->pdev_id, hash_based);
  2664. if (!hash_based)
  2665. reo_dest = pdev->reo_dest;
  2666. else
  2667. reo_dest = 1;
  2668. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2669. /* TODO: Check the destination ring number to be passed to FW */
  2670. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2671. pdev->osif_pdev, peer->mac_addr.raw,
  2672. peer->vdev->vdev_id, hash_based, reo_dest);
  2673. }
  2674. return;
  2675. }
  2676. /*
  2677. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2678. * @vdev_handle: virtual device object
  2679. * @htt_pkt_type: type of pkt
  2680. *
  2681. * Return: void
  2682. */
  2683. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2684. enum htt_cmn_pkt_type val)
  2685. {
  2686. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2687. vdev->tx_encap_type = val;
  2688. }
  2689. /*
  2690. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2691. * @vdev_handle: virtual device object
  2692. * @htt_pkt_type: type of pkt
  2693. *
  2694. * Return: void
  2695. */
  2696. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2697. enum htt_cmn_pkt_type val)
  2698. {
  2699. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2700. vdev->rx_decap_type = val;
  2701. }
  2702. /*
  2703. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2704. * @pdev_handle: physical device object
  2705. * @val: reo destination ring index (1 - 4)
  2706. *
  2707. * Return: void
  2708. */
  2709. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2710. enum cdp_host_reo_dest_ring val)
  2711. {
  2712. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2713. if (pdev)
  2714. pdev->reo_dest = val;
  2715. }
  2716. /*
  2717. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2718. * @pdev_handle: physical device object
  2719. *
  2720. * Return: reo destination ring index
  2721. */
  2722. static enum cdp_host_reo_dest_ring
  2723. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2724. {
  2725. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2726. if (pdev)
  2727. return pdev->reo_dest;
  2728. else
  2729. return cdp_host_reo_dest_ring_unknown;
  2730. }
  2731. #ifdef QCA_SUPPORT_SON
  2732. static void dp_son_peer_authorize(struct dp_peer *peer)
  2733. {
  2734. struct dp_soc *soc;
  2735. soc = peer->vdev->pdev->soc;
  2736. peer->peer_bs_inact_flag = 0;
  2737. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2738. return;
  2739. }
  2740. #else
  2741. static void dp_son_peer_authorize(struct dp_peer *peer)
  2742. {
  2743. return;
  2744. }
  2745. #endif
  2746. /*
  2747. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2748. * @pdev_handle: device object
  2749. * @val: value to be set
  2750. *
  2751. * Return: void
  2752. */
  2753. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2754. uint32_t val)
  2755. {
  2756. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2757. /* Enable/Disable smart mesh filtering. This flag will be checked
  2758. * during rx processing to check if packets are from NAC clients.
  2759. */
  2760. pdev->filter_neighbour_peers = val;
  2761. return 0;
  2762. }
  2763. /*
  2764. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2765. * address for smart mesh filtering
  2766. * @pdev_handle: device object
  2767. * @cmd: Add/Del command
  2768. * @macaddr: nac client mac address
  2769. *
  2770. * Return: void
  2771. */
  2772. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2773. uint32_t cmd, uint8_t *macaddr)
  2774. {
  2775. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2776. struct dp_neighbour_peer *peer = NULL;
  2777. if (!macaddr)
  2778. goto fail0;
  2779. /* Store address of NAC (neighbour peer) which will be checked
  2780. * against TA of received packets.
  2781. */
  2782. if (cmd == DP_NAC_PARAM_ADD) {
  2783. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2784. sizeof(*peer));
  2785. if (!peer) {
  2786. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2787. FL("DP neighbour peer node memory allocation failed"));
  2788. goto fail0;
  2789. }
  2790. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2791. macaddr, DP_MAC_ADDR_LEN);
  2792. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2793. /* add this neighbour peer into the list */
  2794. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2795. neighbour_peer_list_elem);
  2796. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2797. return 1;
  2798. } else if (cmd == DP_NAC_PARAM_DEL) {
  2799. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2800. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2801. neighbour_peer_list_elem) {
  2802. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2803. macaddr, DP_MAC_ADDR_LEN)) {
  2804. /* delete this peer from the list */
  2805. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2806. peer, neighbour_peer_list_elem);
  2807. qdf_mem_free(peer);
  2808. break;
  2809. }
  2810. }
  2811. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2812. return 1;
  2813. }
  2814. fail0:
  2815. return 0;
  2816. }
  2817. /*
  2818. * dp_get_sec_type() - Get the security type
  2819. * @peer: Datapath peer handle
  2820. * @sec_idx: Security id (mcast, ucast)
  2821. *
  2822. * return sec_type: Security type
  2823. */
  2824. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2825. {
  2826. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2827. return dpeer->security[sec_idx].sec_type;
  2828. }
  2829. /*
  2830. * dp_peer_authorize() - authorize txrx peer
  2831. * @peer_handle: Datapath peer handle
  2832. * @authorize
  2833. *
  2834. */
  2835. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2836. {
  2837. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2838. struct dp_soc *soc;
  2839. if (peer != NULL) {
  2840. soc = peer->vdev->pdev->soc;
  2841. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2842. dp_son_peer_authorize(peer);
  2843. peer->authorize = authorize ? 1 : 0;
  2844. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2845. }
  2846. }
  2847. /*
  2848. * dp_peer_unref_delete() - unref and delete peer
  2849. * @peer_handle: Datapath peer handle
  2850. *
  2851. */
  2852. void dp_peer_unref_delete(void *peer_handle)
  2853. {
  2854. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2855. struct dp_vdev *vdev = peer->vdev;
  2856. struct dp_pdev *pdev = vdev->pdev;
  2857. struct dp_soc *soc = pdev->soc;
  2858. struct dp_peer *tmppeer;
  2859. int found = 0;
  2860. uint16_t peer_id;
  2861. /*
  2862. * Hold the lock all the way from checking if the peer ref count
  2863. * is zero until the peer references are removed from the hash
  2864. * table and vdev list (if the peer ref count is zero).
  2865. * This protects against a new HL tx operation starting to use the
  2866. * peer object just after this function concludes it's done being used.
  2867. * Furthermore, the lock needs to be held while checking whether the
  2868. * vdev's list of peers is empty, to make sure that list is not modified
  2869. * concurrently with the empty check.
  2870. */
  2871. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2872. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2873. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2874. peer, qdf_atomic_read(&peer->ref_cnt));
  2875. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2876. peer_id = peer->peer_ids[0];
  2877. /*
  2878. * Make sure that the reference to the peer in
  2879. * peer object map is removed
  2880. */
  2881. if (peer_id != HTT_INVALID_PEER)
  2882. soc->peer_id_to_obj_map[peer_id] = NULL;
  2883. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2884. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2885. /* remove the reference to the peer from the hash table */
  2886. dp_peer_find_hash_remove(soc, peer);
  2887. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2888. if (tmppeer == peer) {
  2889. found = 1;
  2890. break;
  2891. }
  2892. }
  2893. if (found) {
  2894. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2895. peer_list_elem);
  2896. } else {
  2897. /*Ignoring the remove operation as peer not found*/
  2898. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2899. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2900. peer, vdev, &peer->vdev->peer_list);
  2901. }
  2902. /* cleanup the peer data */
  2903. dp_peer_cleanup(vdev, peer);
  2904. /* check whether the parent vdev has no peers left */
  2905. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2906. /*
  2907. * Now that there are no references to the peer, we can
  2908. * release the peer reference lock.
  2909. */
  2910. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2911. /*
  2912. * Check if the parent vdev was waiting for its peers
  2913. * to be deleted, in order for it to be deleted too.
  2914. */
  2915. if (vdev->delete.pending) {
  2916. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2917. vdev->delete.callback;
  2918. void *vdev_delete_context =
  2919. vdev->delete.context;
  2920. QDF_TRACE(QDF_MODULE_ID_DP,
  2921. QDF_TRACE_LEVEL_INFO_HIGH,
  2922. FL("deleting vdev object %pK (%pM)"
  2923. " - its last peer is done"),
  2924. vdev, vdev->mac_addr.raw);
  2925. /* all peers are gone, go ahead and delete it */
  2926. qdf_mem_free(vdev);
  2927. if (vdev_delete_cb)
  2928. vdev_delete_cb(vdev_delete_context);
  2929. }
  2930. } else {
  2931. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2932. }
  2933. #ifdef notyet
  2934. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2935. #else
  2936. qdf_mem_free(peer);
  2937. #endif
  2938. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2939. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2940. vdev->vdev_id, peer->mac_addr.raw);
  2941. }
  2942. } else {
  2943. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2944. }
  2945. }
  2946. /*
  2947. * dp_peer_detach_wifi3() – Detach txrx peer
  2948. * @peer_handle: Datapath peer handle
  2949. *
  2950. */
  2951. static void dp_peer_delete_wifi3(void *peer_handle)
  2952. {
  2953. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2954. /* redirect the peer's rx delivery function to point to a
  2955. * discard func
  2956. */
  2957. peer->rx_opt_proc = dp_rx_discard;
  2958. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2959. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2960. #ifndef CONFIG_WIN
  2961. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2962. #endif
  2963. qdf_spinlock_destroy(&peer->peer_info_lock);
  2964. /*
  2965. * Remove the reference added during peer_attach.
  2966. * The peer will still be left allocated until the
  2967. * PEER_UNMAP message arrives to remove the other
  2968. * reference, added by the PEER_MAP message.
  2969. */
  2970. dp_peer_unref_delete(peer_handle);
  2971. }
  2972. /*
  2973. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2974. * @peer_handle: Datapath peer handle
  2975. *
  2976. */
  2977. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2978. {
  2979. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2980. return vdev->mac_addr.raw;
  2981. }
  2982. /*
  2983. * dp_vdev_set_wds() - Enable per packet stats
  2984. * @vdev_handle: DP VDEV handle
  2985. * @val: value
  2986. *
  2987. * Return: none
  2988. */
  2989. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2990. {
  2991. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2992. vdev->wds_enabled = val;
  2993. return 0;
  2994. }
  2995. /*
  2996. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2997. * @peer_handle: Datapath peer handle
  2998. *
  2999. */
  3000. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3001. uint8_t vdev_id)
  3002. {
  3003. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3004. struct dp_vdev *vdev = NULL;
  3005. if (qdf_unlikely(!pdev))
  3006. return NULL;
  3007. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3008. if (vdev->vdev_id == vdev_id)
  3009. break;
  3010. }
  3011. return (struct cdp_vdev *)vdev;
  3012. }
  3013. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3014. {
  3015. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3016. return vdev->opmode;
  3017. }
  3018. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3019. {
  3020. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3021. struct dp_pdev *pdev = vdev->pdev;
  3022. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3023. }
  3024. /**
  3025. * dp_reset_monitor_mode() - Disable monitor mode
  3026. * @pdev_handle: Datapath PDEV handle
  3027. *
  3028. * Return: 0 on success, not 0 on failure
  3029. */
  3030. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3031. {
  3032. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3033. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3034. struct dp_soc *soc;
  3035. uint8_t pdev_id;
  3036. pdev_id = pdev->pdev_id;
  3037. soc = pdev->soc;
  3038. pdev->monitor_vdev = NULL;
  3039. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3040. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3041. pdev->rxdma_mon_buf_ring.hal_srng,
  3042. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3043. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3044. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3045. RX_BUFFER_SIZE, &htt_tlv_filter);
  3046. return 0;
  3047. }
  3048. /**
  3049. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3050. * @vdev_handle: Datapath VDEV handle
  3051. * @smart_monitor: Flag to denote if its smart monitor mode
  3052. *
  3053. * Return: 0 on success, not 0 on failure
  3054. */
  3055. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3056. uint8_t smart_monitor)
  3057. {
  3058. /* Many monitor VAPs can exists in a system but only one can be up at
  3059. * anytime
  3060. */
  3061. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3062. struct dp_pdev *pdev;
  3063. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3064. struct dp_soc *soc;
  3065. uint8_t pdev_id;
  3066. qdf_assert(vdev);
  3067. pdev = vdev->pdev;
  3068. pdev_id = pdev->pdev_id;
  3069. soc = pdev->soc;
  3070. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3071. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3072. pdev, pdev_id, soc, vdev);
  3073. /*Check if current pdev's monitor_vdev exists */
  3074. if (pdev->monitor_vdev) {
  3075. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3076. "vdev=%pK\n", vdev);
  3077. qdf_assert(vdev);
  3078. }
  3079. pdev->monitor_vdev = vdev;
  3080. /* If smart monitor mode, do not configure monitor ring */
  3081. if (smart_monitor)
  3082. return QDF_STATUS_SUCCESS;
  3083. htt_tlv_filter.mpdu_start = 1;
  3084. htt_tlv_filter.msdu_start = 1;
  3085. htt_tlv_filter.packet = 1;
  3086. htt_tlv_filter.msdu_end = 1;
  3087. htt_tlv_filter.mpdu_end = 1;
  3088. htt_tlv_filter.packet_header = 1;
  3089. htt_tlv_filter.attention = 1;
  3090. htt_tlv_filter.ppdu_start = 0;
  3091. htt_tlv_filter.ppdu_end = 0;
  3092. htt_tlv_filter.ppdu_end_user_stats = 0;
  3093. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3094. htt_tlv_filter.ppdu_end_status_done = 0;
  3095. htt_tlv_filter.header_per_msdu = 1;
  3096. htt_tlv_filter.enable_fp = 1;
  3097. htt_tlv_filter.enable_md = 0;
  3098. htt_tlv_filter.enable_mo = 1;
  3099. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3100. pdev->rxdma_mon_buf_ring.hal_srng,
  3101. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3102. htt_tlv_filter.mpdu_start = 1;
  3103. htt_tlv_filter.msdu_start = 1;
  3104. htt_tlv_filter.packet = 0;
  3105. htt_tlv_filter.msdu_end = 1;
  3106. htt_tlv_filter.mpdu_end = 1;
  3107. htt_tlv_filter.packet_header = 1;
  3108. htt_tlv_filter.attention = 1;
  3109. htt_tlv_filter.ppdu_start = 1;
  3110. htt_tlv_filter.ppdu_end = 1;
  3111. htt_tlv_filter.ppdu_end_user_stats = 1;
  3112. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3113. htt_tlv_filter.ppdu_end_status_done = 1;
  3114. htt_tlv_filter.header_per_msdu = 0;
  3115. htt_tlv_filter.enable_fp = 1;
  3116. htt_tlv_filter.enable_md = 0;
  3117. htt_tlv_filter.enable_mo = 1;
  3118. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3119. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3120. RX_BUFFER_SIZE, &htt_tlv_filter);
  3121. return QDF_STATUS_SUCCESS;
  3122. }
  3123. #ifdef MESH_MODE_SUPPORT
  3124. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3125. {
  3126. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3128. FL("val %d"), val);
  3129. vdev->mesh_vdev = val;
  3130. }
  3131. /*
  3132. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3133. * @vdev_hdl: virtual device object
  3134. * @val: value to be set
  3135. *
  3136. * Return: void
  3137. */
  3138. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3139. {
  3140. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3142. FL("val %d"), val);
  3143. vdev->mesh_rx_filter = val;
  3144. }
  3145. #endif
  3146. /**
  3147. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3148. * @vdev: DP VDEV handle
  3149. *
  3150. * return: void
  3151. */
  3152. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3153. {
  3154. struct dp_peer *peer = NULL;
  3155. struct dp_soc *soc = vdev->pdev->soc;
  3156. int i;
  3157. uint8_t pream_type;
  3158. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3159. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3160. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3161. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3162. for (i = 0; i < MAX_MCS; i++) {
  3163. DP_STATS_AGGR(vdev, peer,
  3164. tx.pkt_type[pream_type].mcs_count[i]);
  3165. DP_STATS_AGGR(vdev, peer,
  3166. rx.pkt_type[pream_type].mcs_count[i]);
  3167. }
  3168. }
  3169. for (i = 0; i < MAX_BW; i++) {
  3170. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3171. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3172. }
  3173. for (i = 0; i < SS_COUNT; i++)
  3174. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3175. for (i = 0; i < WME_AC_MAX; i++) {
  3176. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3177. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3178. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3179. }
  3180. for (i = 0; i < MAX_GI; i++) {
  3181. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3182. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3183. }
  3184. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3185. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3186. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3187. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3188. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3189. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3190. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3191. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3192. DP_STATS_AGGR(vdev, peer, tx.retries);
  3193. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3194. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3195. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3196. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3197. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3198. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3199. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3200. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3201. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3202. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3203. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3204. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3205. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3206. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3207. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3208. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3209. peer->stats.rx.multicast.num;
  3210. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3211. peer->stats.rx.multicast.bytes;
  3212. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3213. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3214. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3215. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3216. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3217. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3218. vdev->stats.tx.last_ack_rssi =
  3219. peer->stats.tx.last_ack_rssi;
  3220. }
  3221. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3222. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3223. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3224. }
  3225. /**
  3226. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3227. * @pdev: DP PDEV handle
  3228. *
  3229. * return: void
  3230. */
  3231. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3232. {
  3233. struct dp_vdev *vdev = NULL;
  3234. uint8_t i;
  3235. uint8_t pream_type;
  3236. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3237. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3238. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3239. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3240. dp_aggregate_vdev_stats(vdev);
  3241. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3242. for (i = 0; i < MAX_MCS; i++) {
  3243. DP_STATS_AGGR(pdev, vdev,
  3244. tx.pkt_type[pream_type].mcs_count[i]);
  3245. DP_STATS_AGGR(pdev, vdev,
  3246. rx.pkt_type[pream_type].mcs_count[i]);
  3247. }
  3248. }
  3249. for (i = 0; i < MAX_BW; i++) {
  3250. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3251. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3252. }
  3253. for (i = 0; i < SS_COUNT; i++)
  3254. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3255. for (i = 0; i < WME_AC_MAX; i++) {
  3256. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3257. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3258. DP_STATS_AGGR(pdev, vdev,
  3259. tx.excess_retries_ac[i]);
  3260. }
  3261. for (i = 0; i < MAX_GI; i++) {
  3262. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3263. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3264. }
  3265. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3266. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3267. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3268. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3269. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3270. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3271. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3272. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3273. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3274. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3275. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3276. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3277. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3278. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3279. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3280. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3281. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3282. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3283. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3284. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3285. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3286. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3287. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3288. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3289. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3290. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3291. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3292. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3293. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3294. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3295. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3296. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3297. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3298. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3299. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3300. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3301. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3302. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3303. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3304. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3305. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3306. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3307. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3308. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3309. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3310. DP_STATS_AGGR(pdev, vdev,
  3311. tx_i.mcast_en.dropped_map_error);
  3312. DP_STATS_AGGR(pdev, vdev,
  3313. tx_i.mcast_en.dropped_self_mac);
  3314. DP_STATS_AGGR(pdev, vdev,
  3315. tx_i.mcast_en.dropped_send_fail);
  3316. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3317. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3318. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3319. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3320. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3321. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3322. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3323. pdev->stats.tx_i.dropped.dma_error +
  3324. pdev->stats.tx_i.dropped.ring_full +
  3325. pdev->stats.tx_i.dropped.enqueue_fail +
  3326. pdev->stats.tx_i.dropped.desc_na +
  3327. pdev->stats.tx_i.dropped.res_full;
  3328. pdev->stats.tx.last_ack_rssi =
  3329. vdev->stats.tx.last_ack_rssi;
  3330. pdev->stats.tx_i.tso.num_seg =
  3331. vdev->stats.tx_i.tso.num_seg;
  3332. }
  3333. }
  3334. /**
  3335. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3336. * @pdev: DP_PDEV Handle
  3337. *
  3338. * Return:void
  3339. */
  3340. static inline void
  3341. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3342. {
  3343. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3344. DP_PRINT_STATS("Received From Stack:");
  3345. DP_PRINT_STATS(" Packets = %d",
  3346. pdev->stats.tx_i.rcvd.num);
  3347. DP_PRINT_STATS(" Bytes = %d",
  3348. pdev->stats.tx_i.rcvd.bytes);
  3349. DP_PRINT_STATS("Processed:");
  3350. DP_PRINT_STATS(" Packets = %d",
  3351. pdev->stats.tx_i.processed.num);
  3352. DP_PRINT_STATS(" Bytes = %d",
  3353. pdev->stats.tx_i.processed.bytes);
  3354. DP_PRINT_STATS("Completions:");
  3355. DP_PRINT_STATS(" Packets = %d",
  3356. pdev->stats.tx.comp_pkt.num);
  3357. DP_PRINT_STATS(" Bytes = %d",
  3358. pdev->stats.tx.comp_pkt.bytes);
  3359. DP_PRINT_STATS("Dropped:");
  3360. DP_PRINT_STATS(" Total = %d",
  3361. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3362. DP_PRINT_STATS(" Dma_map_error = %d",
  3363. pdev->stats.tx_i.dropped.dma_error);
  3364. DP_PRINT_STATS(" Ring Full = %d",
  3365. pdev->stats.tx_i.dropped.ring_full);
  3366. DP_PRINT_STATS(" Descriptor Not available = %d",
  3367. pdev->stats.tx_i.dropped.desc_na);
  3368. DP_PRINT_STATS(" HW enqueue failed= %d",
  3369. pdev->stats.tx_i.dropped.enqueue_fail);
  3370. DP_PRINT_STATS(" Resources Full = %d",
  3371. pdev->stats.tx_i.dropped.res_full);
  3372. DP_PRINT_STATS(" FW removed = %d",
  3373. pdev->stats.tx.dropped.fw_rem);
  3374. DP_PRINT_STATS(" FW removed transmitted = %d",
  3375. pdev->stats.tx.dropped.fw_rem_tx);
  3376. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3377. pdev->stats.tx.dropped.fw_rem_notx);
  3378. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3379. pdev->stats.tx.dropped.age_out);
  3380. DP_PRINT_STATS("Scatter Gather:");
  3381. DP_PRINT_STATS(" Packets = %d",
  3382. pdev->stats.tx_i.sg.sg_pkt.num);
  3383. DP_PRINT_STATS(" Bytes = %d",
  3384. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3385. DP_PRINT_STATS(" Dropped By Host = %d",
  3386. pdev->stats.tx_i.sg.dropped_host);
  3387. DP_PRINT_STATS(" Dropped By Target = %d",
  3388. pdev->stats.tx_i.sg.dropped_target);
  3389. DP_PRINT_STATS("TSO:");
  3390. DP_PRINT_STATS(" Number of Segments = %d",
  3391. pdev->stats.tx_i.tso.num_seg);
  3392. DP_PRINT_STATS(" Packets = %d",
  3393. pdev->stats.tx_i.tso.tso_pkt.num);
  3394. DP_PRINT_STATS(" Bytes = %d",
  3395. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3396. DP_PRINT_STATS(" Dropped By Host = %d",
  3397. pdev->stats.tx_i.tso.dropped_host);
  3398. DP_PRINT_STATS("Mcast Enhancement:");
  3399. DP_PRINT_STATS(" Packets = %d",
  3400. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3401. DP_PRINT_STATS(" Bytes = %d",
  3402. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3403. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3404. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3405. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3406. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3407. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3408. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3409. DP_PRINT_STATS(" Unicast sent = %d",
  3410. pdev->stats.tx_i.mcast_en.ucast);
  3411. DP_PRINT_STATS("Raw:");
  3412. DP_PRINT_STATS(" Packets = %d",
  3413. pdev->stats.tx_i.raw.raw_pkt.num);
  3414. DP_PRINT_STATS(" Bytes = %d",
  3415. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3416. DP_PRINT_STATS(" DMA map error = %d",
  3417. pdev->stats.tx_i.raw.dma_map_error);
  3418. DP_PRINT_STATS("Reinjected:");
  3419. DP_PRINT_STATS(" Packets = %d",
  3420. pdev->stats.tx_i.reinject_pkts.num);
  3421. DP_PRINT_STATS("Bytes = %d\n",
  3422. pdev->stats.tx_i.reinject_pkts.bytes);
  3423. DP_PRINT_STATS("Inspected:");
  3424. DP_PRINT_STATS(" Packets = %d",
  3425. pdev->stats.tx_i.inspect_pkts.num);
  3426. DP_PRINT_STATS(" Bytes = %d",
  3427. pdev->stats.tx_i.inspect_pkts.bytes);
  3428. }
  3429. /**
  3430. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3431. * @pdev: DP_PDEV Handle
  3432. *
  3433. * Return: void
  3434. */
  3435. static inline void
  3436. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3437. {
  3438. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3439. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3440. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3441. pdev->stats.rx.rcvd_reo[0].num,
  3442. pdev->stats.rx.rcvd_reo[1].num,
  3443. pdev->stats.rx.rcvd_reo[2].num,
  3444. pdev->stats.rx.rcvd_reo[3].num);
  3445. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3446. pdev->stats.rx.rcvd_reo[0].bytes,
  3447. pdev->stats.rx.rcvd_reo[1].bytes,
  3448. pdev->stats.rx.rcvd_reo[2].bytes,
  3449. pdev->stats.rx.rcvd_reo[3].bytes);
  3450. DP_PRINT_STATS("Replenished:");
  3451. DP_PRINT_STATS(" Packets = %d",
  3452. pdev->stats.replenish.pkts.num);
  3453. DP_PRINT_STATS(" Bytes = %d",
  3454. pdev->stats.replenish.pkts.bytes);
  3455. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3456. pdev->stats.buf_freelist);
  3457. DP_PRINT_STATS("Dropped:");
  3458. DP_PRINT_STATS(" msdu_not_done = %d",
  3459. pdev->stats.dropped.msdu_not_done);
  3460. DP_PRINT_STATS("Sent To Stack:");
  3461. DP_PRINT_STATS(" Packets = %d",
  3462. pdev->stats.rx.to_stack.num);
  3463. DP_PRINT_STATS(" Bytes = %d",
  3464. pdev->stats.rx.to_stack.bytes);
  3465. DP_PRINT_STATS("Multicast/Broadcast:");
  3466. DP_PRINT_STATS(" Packets = %d",
  3467. pdev->stats.rx.multicast.num);
  3468. DP_PRINT_STATS(" Bytes = %d",
  3469. pdev->stats.rx.multicast.bytes);
  3470. DP_PRINT_STATS("Errors:");
  3471. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3472. pdev->stats.replenish.rxdma_err);
  3473. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3474. pdev->stats.err.desc_alloc_fail);
  3475. }
  3476. /**
  3477. * dp_print_soc_tx_stats(): Print SOC level stats
  3478. * @soc DP_SOC Handle
  3479. *
  3480. * Return: void
  3481. */
  3482. static inline void
  3483. dp_print_soc_tx_stats(struct dp_soc *soc)
  3484. {
  3485. DP_PRINT_STATS("SOC Tx Stats:\n");
  3486. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3487. soc->stats.tx.desc_in_use);
  3488. DP_PRINT_STATS("Invalid peer:");
  3489. DP_PRINT_STATS(" Packets = %d",
  3490. soc->stats.tx.tx_invalid_peer.num);
  3491. DP_PRINT_STATS(" Bytes = %d",
  3492. soc->stats.tx.tx_invalid_peer.bytes);
  3493. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3494. soc->stats.tx.tcl_ring_full[0],
  3495. soc->stats.tx.tcl_ring_full[1],
  3496. soc->stats.tx.tcl_ring_full[2]);
  3497. }
  3498. /**
  3499. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3500. * @soc: DP_SOC Handle
  3501. *
  3502. * Return:void
  3503. */
  3504. static inline void
  3505. dp_print_soc_rx_stats(struct dp_soc *soc)
  3506. {
  3507. uint32_t i;
  3508. char reo_error[DP_REO_ERR_LENGTH];
  3509. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3510. uint8_t index = 0;
  3511. DP_PRINT_STATS("SOC Rx Stats:\n");
  3512. DP_PRINT_STATS("Errors:\n");
  3513. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3514. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3515. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3516. DP_PRINT_STATS("Invalid RBM = %d",
  3517. soc->stats.rx.err.invalid_rbm);
  3518. DP_PRINT_STATS("Invalid Vdev = %d",
  3519. soc->stats.rx.err.invalid_vdev);
  3520. DP_PRINT_STATS("Invalid Pdev = %d",
  3521. soc->stats.rx.err.invalid_pdev);
  3522. DP_PRINT_STATS("Invalid Peer = %d",
  3523. soc->stats.rx.err.rx_invalid_peer.num);
  3524. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3525. soc->stats.rx.err.hal_ring_access_fail);
  3526. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3527. index += qdf_snprint(&rxdma_error[index],
  3528. DP_RXDMA_ERR_LENGTH - index,
  3529. " %d", soc->stats.rx.err.rxdma_error[i]);
  3530. }
  3531. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3532. rxdma_error);
  3533. index = 0;
  3534. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3535. index += qdf_snprint(&reo_error[index],
  3536. DP_REO_ERR_LENGTH - index,
  3537. " %d", soc->stats.rx.err.reo_error[i]);
  3538. }
  3539. DP_PRINT_STATS("REO Error(0-14):%s",
  3540. reo_error);
  3541. }
  3542. /**
  3543. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3544. * @soc: DP_SOC handle
  3545. * @srng: DP_SRNG handle
  3546. * @ring_name: SRNG name
  3547. *
  3548. * Return: void
  3549. */
  3550. static inline void
  3551. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3552. char *ring_name)
  3553. {
  3554. uint32_t tailp;
  3555. uint32_t headp;
  3556. if (srng->hal_srng != NULL) {
  3557. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3558. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3559. ring_name, headp, tailp);
  3560. }
  3561. }
  3562. /**
  3563. * dp_print_ring_stats(): Print tail and head pointer
  3564. * @pdev: DP_PDEV handle
  3565. *
  3566. * Return:void
  3567. */
  3568. static inline void
  3569. dp_print_ring_stats(struct dp_pdev *pdev)
  3570. {
  3571. uint32_t i;
  3572. char ring_name[STR_MAXLEN + 1];
  3573. dp_print_ring_stat_from_hal(pdev->soc,
  3574. &pdev->soc->reo_exception_ring,
  3575. "Reo Exception Ring");
  3576. dp_print_ring_stat_from_hal(pdev->soc,
  3577. &pdev->soc->reo_reinject_ring,
  3578. "Reo Inject Ring");
  3579. dp_print_ring_stat_from_hal(pdev->soc,
  3580. &pdev->soc->reo_cmd_ring,
  3581. "Reo Command Ring");
  3582. dp_print_ring_stat_from_hal(pdev->soc,
  3583. &pdev->soc->reo_status_ring,
  3584. "Reo Status Ring");
  3585. dp_print_ring_stat_from_hal(pdev->soc,
  3586. &pdev->soc->rx_rel_ring,
  3587. "Rx Release ring");
  3588. dp_print_ring_stat_from_hal(pdev->soc,
  3589. &pdev->soc->tcl_cmd_ring,
  3590. "Tcl command Ring");
  3591. dp_print_ring_stat_from_hal(pdev->soc,
  3592. &pdev->soc->tcl_status_ring,
  3593. "Tcl Status Ring");
  3594. dp_print_ring_stat_from_hal(pdev->soc,
  3595. &pdev->soc->wbm_desc_rel_ring,
  3596. "Wbm Desc Rel Ring");
  3597. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3598. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3599. dp_print_ring_stat_from_hal(pdev->soc,
  3600. &pdev->soc->reo_dest_ring[i],
  3601. ring_name);
  3602. }
  3603. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3604. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3605. dp_print_ring_stat_from_hal(pdev->soc,
  3606. &pdev->soc->tcl_data_ring[i],
  3607. ring_name);
  3608. }
  3609. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3610. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3611. dp_print_ring_stat_from_hal(pdev->soc,
  3612. &pdev->soc->tx_comp_ring[i],
  3613. ring_name);
  3614. }
  3615. dp_print_ring_stat_from_hal(pdev->soc,
  3616. &pdev->rx_refill_buf_ring,
  3617. "Rx Refill Buf Ring");
  3618. #ifdef IPA_OFFLOAD
  3619. dp_print_ring_stat_from_hal(pdev->soc,
  3620. &pdev->ipa_rx_refill_buf_ring,
  3621. "IPA Rx Refill Buf Ring");
  3622. #endif
  3623. dp_print_ring_stat_from_hal(pdev->soc,
  3624. &pdev->rxdma_mon_buf_ring,
  3625. "Rxdma Mon Buf Ring");
  3626. dp_print_ring_stat_from_hal(pdev->soc,
  3627. &pdev->rxdma_mon_dst_ring,
  3628. "Rxdma Mon Dst Ring");
  3629. dp_print_ring_stat_from_hal(pdev->soc,
  3630. &pdev->rxdma_mon_status_ring,
  3631. "Rxdma Mon Status Ring");
  3632. dp_print_ring_stat_from_hal(pdev->soc,
  3633. &pdev->rxdma_mon_desc_ring,
  3634. "Rxdma mon desc Ring");
  3635. dp_print_ring_stat_from_hal(pdev->soc,
  3636. &pdev->rxdma_err_dst_ring,
  3637. "Rxdma err dst ring");
  3638. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3639. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3640. dp_print_ring_stat_from_hal(pdev->soc,
  3641. &pdev->rx_mac_buf_ring[i],
  3642. ring_name);
  3643. }
  3644. }
  3645. /**
  3646. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3647. * @vdev: DP_VDEV handle
  3648. *
  3649. * Return:void
  3650. */
  3651. static inline void
  3652. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3653. {
  3654. struct dp_peer *peer = NULL;
  3655. DP_STATS_CLR(vdev->pdev);
  3656. DP_STATS_CLR(vdev->pdev->soc);
  3657. DP_STATS_CLR(vdev);
  3658. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3659. if (!peer)
  3660. return;
  3661. DP_STATS_CLR(peer);
  3662. }
  3663. }
  3664. /**
  3665. * dp_print_rx_rates(): Print Rx rate stats
  3666. * @vdev: DP_VDEV handle
  3667. *
  3668. * Return:void
  3669. */
  3670. static inline void
  3671. dp_print_rx_rates(struct dp_vdev *vdev)
  3672. {
  3673. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3674. uint8_t i, mcs, pkt_type;
  3675. uint8_t index = 0;
  3676. char nss[DP_NSS_LENGTH];
  3677. DP_PRINT_STATS("Rx Rate Info:\n");
  3678. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3679. index = 0;
  3680. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3681. if (!dp_rate_string[pkt_type][mcs].valid)
  3682. continue;
  3683. DP_PRINT_STATS(" %s = %d",
  3684. dp_rate_string[pkt_type][mcs].mcs_type,
  3685. pdev->stats.rx.pkt_type[pkt_type].
  3686. mcs_count[mcs]);
  3687. }
  3688. DP_PRINT_STATS("\n");
  3689. }
  3690. index = 0;
  3691. for (i = 0; i < SS_COUNT; i++) {
  3692. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3693. " %d", pdev->stats.rx.nss[i]);
  3694. }
  3695. DP_PRINT_STATS("NSS(0-7) = %s",
  3696. nss);
  3697. DP_PRINT_STATS("SGI ="
  3698. " 0.8us %d,"
  3699. " 0.4us %d,"
  3700. " 1.6us %d,"
  3701. " 3.2us %d,",
  3702. pdev->stats.rx.sgi_count[0],
  3703. pdev->stats.rx.sgi_count[1],
  3704. pdev->stats.rx.sgi_count[2],
  3705. pdev->stats.rx.sgi_count[3]);
  3706. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3707. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3708. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3709. DP_PRINT_STATS("Reception Type ="
  3710. " SU: %d,"
  3711. " MU_MIMO:%d,"
  3712. " MU_OFDMA:%d,"
  3713. " MU_OFDMA_MIMO:%d\n",
  3714. pdev->stats.rx.reception_type[0],
  3715. pdev->stats.rx.reception_type[1],
  3716. pdev->stats.rx.reception_type[2],
  3717. pdev->stats.rx.reception_type[3]);
  3718. DP_PRINT_STATS("Aggregation:\n");
  3719. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3720. pdev->stats.rx.ampdu_cnt);
  3721. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3722. pdev->stats.rx.non_ampdu_cnt);
  3723. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3724. pdev->stats.rx.amsdu_cnt);
  3725. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3726. pdev->stats.rx.non_amsdu_cnt);
  3727. }
  3728. /**
  3729. * dp_print_tx_rates(): Print tx rates
  3730. * @vdev: DP_VDEV handle
  3731. *
  3732. * Return:void
  3733. */
  3734. static inline void
  3735. dp_print_tx_rates(struct dp_vdev *vdev)
  3736. {
  3737. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3738. uint8_t mcs, pkt_type;
  3739. uint32_t index;
  3740. DP_PRINT_STATS("Tx Rate Info:\n");
  3741. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3742. index = 0;
  3743. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3744. if (!dp_rate_string[pkt_type][mcs].valid)
  3745. continue;
  3746. DP_PRINT_STATS(" %s = %d",
  3747. dp_rate_string[pkt_type][mcs].mcs_type,
  3748. pdev->stats.tx.pkt_type[pkt_type].
  3749. mcs_count[mcs]);
  3750. }
  3751. DP_PRINT_STATS("\n");
  3752. }
  3753. DP_PRINT_STATS("SGI ="
  3754. " 0.8us %d"
  3755. " 0.4us %d"
  3756. " 1.6us %d"
  3757. " 3.2us %d",
  3758. pdev->stats.tx.sgi_count[0],
  3759. pdev->stats.tx.sgi_count[1],
  3760. pdev->stats.tx.sgi_count[2],
  3761. pdev->stats.tx.sgi_count[3]);
  3762. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3763. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3764. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3765. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3766. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3767. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3768. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3769. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3770. DP_PRINT_STATS("Aggregation:\n");
  3771. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3772. pdev->stats.tx.amsdu_cnt);
  3773. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3774. pdev->stats.tx.non_amsdu_cnt);
  3775. }
  3776. /**
  3777. * dp_print_peer_stats():print peer stats
  3778. * @peer: DP_PEER handle
  3779. *
  3780. * return void
  3781. */
  3782. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3783. {
  3784. uint8_t i, mcs, pkt_type;
  3785. uint32_t index;
  3786. char nss[DP_NSS_LENGTH];
  3787. DP_PRINT_STATS("Node Tx Stats:\n");
  3788. DP_PRINT_STATS("Total Packet Completions = %d",
  3789. peer->stats.tx.comp_pkt.num);
  3790. DP_PRINT_STATS("Total Bytes Completions = %d",
  3791. peer->stats.tx.comp_pkt.bytes);
  3792. DP_PRINT_STATS("Success Packets = %d",
  3793. peer->stats.tx.tx_success.num);
  3794. DP_PRINT_STATS("Success Bytes = %d",
  3795. peer->stats.tx.tx_success.bytes);
  3796. DP_PRINT_STATS("Packets Failed = %d",
  3797. peer->stats.tx.tx_failed);
  3798. DP_PRINT_STATS("Packets In OFDMA = %d",
  3799. peer->stats.tx.ofdma);
  3800. DP_PRINT_STATS("Packets In STBC = %d",
  3801. peer->stats.tx.stbc);
  3802. DP_PRINT_STATS("Packets In LDPC = %d",
  3803. peer->stats.tx.ldpc);
  3804. DP_PRINT_STATS("Packet Retries = %d",
  3805. peer->stats.tx.retries);
  3806. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3807. peer->stats.tx.amsdu_cnt);
  3808. DP_PRINT_STATS("Last Packet RSSI = %d",
  3809. peer->stats.tx.last_ack_rssi);
  3810. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3811. peer->stats.tx.dropped.fw_rem);
  3812. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3813. peer->stats.tx.dropped.fw_rem_tx);
  3814. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3815. peer->stats.tx.dropped.fw_rem_notx);
  3816. DP_PRINT_STATS("Dropped : Age Out = %d",
  3817. peer->stats.tx.dropped.age_out);
  3818. DP_PRINT_STATS("Rate Info:");
  3819. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3820. index = 0;
  3821. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3822. if (!dp_rate_string[pkt_type][mcs].valid)
  3823. continue;
  3824. DP_PRINT_STATS(" %s = %d",
  3825. dp_rate_string[pkt_type][mcs].mcs_type,
  3826. peer->stats.tx.pkt_type[pkt_type].
  3827. mcs_count[mcs]);
  3828. }
  3829. DP_PRINT_STATS("\n");
  3830. }
  3831. DP_PRINT_STATS("SGI = "
  3832. " 0.8us %d"
  3833. " 0.4us %d"
  3834. " 1.6us %d"
  3835. " 3.2us %d",
  3836. peer->stats.tx.sgi_count[0],
  3837. peer->stats.tx.sgi_count[1],
  3838. peer->stats.tx.sgi_count[2],
  3839. peer->stats.tx.sgi_count[3]);
  3840. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3841. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3842. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3843. DP_PRINT_STATS("Aggregation:");
  3844. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3845. peer->stats.tx.amsdu_cnt);
  3846. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3847. peer->stats.tx.non_amsdu_cnt);
  3848. DP_PRINT_STATS("Node Rx Stats:");
  3849. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3850. peer->stats.rx.to_stack.num);
  3851. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3852. peer->stats.rx.to_stack.bytes);
  3853. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3854. DP_PRINT_STATS("Packets Received = %d",
  3855. peer->stats.rx.rcvd_reo[i].num);
  3856. DP_PRINT_STATS("Bytes Received = %d",
  3857. peer->stats.rx.rcvd_reo[i].bytes);
  3858. }
  3859. DP_PRINT_STATS("Multicast Packets Received = %d",
  3860. peer->stats.rx.multicast.num);
  3861. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3862. peer->stats.rx.multicast.bytes);
  3863. DP_PRINT_STATS("WDS Packets Received = %d",
  3864. peer->stats.rx.wds.num);
  3865. DP_PRINT_STATS("WDS Bytes Received = %d",
  3866. peer->stats.rx.wds.bytes);
  3867. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3868. peer->stats.rx.intra_bss.pkts.num);
  3869. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3870. peer->stats.rx.intra_bss.pkts.bytes);
  3871. DP_PRINT_STATS("Raw Packets Received = %d",
  3872. peer->stats.rx.raw.num);
  3873. DP_PRINT_STATS("Raw Bytes Received = %d",
  3874. peer->stats.rx.raw.bytes);
  3875. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3876. peer->stats.rx.err.mic_err);
  3877. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3878. peer->stats.rx.err.decrypt_err);
  3879. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3880. peer->stats.rx.non_ampdu_cnt);
  3881. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3882. peer->stats.rx.ampdu_cnt);
  3883. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3884. peer->stats.rx.non_amsdu_cnt);
  3885. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3886. peer->stats.rx.amsdu_cnt);
  3887. DP_PRINT_STATS("SGI ="
  3888. " 0.8us %d"
  3889. " 0.4us %d"
  3890. " 1.6us %d"
  3891. " 3.2us %d",
  3892. peer->stats.rx.sgi_count[0],
  3893. peer->stats.rx.sgi_count[1],
  3894. peer->stats.rx.sgi_count[2],
  3895. peer->stats.rx.sgi_count[3]);
  3896. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3897. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3898. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3899. DP_PRINT_STATS("Reception Type ="
  3900. " SU %d,"
  3901. " MU_MIMO %d,"
  3902. " MU_OFDMA %d,"
  3903. " MU_OFDMA_MIMO %d",
  3904. peer->stats.rx.reception_type[0],
  3905. peer->stats.rx.reception_type[1],
  3906. peer->stats.rx.reception_type[2],
  3907. peer->stats.rx.reception_type[3]);
  3908. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3909. index = 0;
  3910. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3911. if (!dp_rate_string[pkt_type][mcs].valid)
  3912. continue;
  3913. DP_PRINT_STATS(" %s = %d",
  3914. dp_rate_string[pkt_type][mcs].mcs_type,
  3915. peer->stats.rx.pkt_type[pkt_type].
  3916. mcs_count[mcs]);
  3917. }
  3918. DP_PRINT_STATS("\n");
  3919. }
  3920. index = 0;
  3921. for (i = 0; i < SS_COUNT; i++) {
  3922. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3923. " %d", peer->stats.rx.nss[i]);
  3924. }
  3925. DP_PRINT_STATS("NSS(0-7) = %s",
  3926. nss);
  3927. DP_PRINT_STATS("Aggregation:");
  3928. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3929. peer->stats.rx.ampdu_cnt);
  3930. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3931. peer->stats.rx.non_ampdu_cnt);
  3932. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3933. peer->stats.rx.amsdu_cnt);
  3934. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3935. peer->stats.rx.non_amsdu_cnt);
  3936. }
  3937. /**
  3938. * dp_print_host_stats()- Function to print the stats aggregated at host
  3939. * @vdev_handle: DP_VDEV handle
  3940. * @type: host stats type
  3941. *
  3942. * Available Stat types
  3943. * TXRX_CLEAR_STATS : Clear the stats
  3944. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3945. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3946. * TXRX_TX_HOST_STATS: Print Tx Stats
  3947. * TXRX_RX_HOST_STATS: Print Rx Stats
  3948. * TXRX_AST_STATS: Print AST Stats
  3949. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3950. *
  3951. * Return: 0 on success, print error message in case of failure
  3952. */
  3953. static int
  3954. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3955. {
  3956. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3957. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3958. dp_aggregate_pdev_stats(pdev);
  3959. switch (type) {
  3960. case TXRX_CLEAR_STATS:
  3961. dp_txrx_host_stats_clr(vdev);
  3962. break;
  3963. case TXRX_RX_RATE_STATS:
  3964. dp_print_rx_rates(vdev);
  3965. break;
  3966. case TXRX_TX_RATE_STATS:
  3967. dp_print_tx_rates(vdev);
  3968. break;
  3969. case TXRX_TX_HOST_STATS:
  3970. dp_print_pdev_tx_stats(pdev);
  3971. dp_print_soc_tx_stats(pdev->soc);
  3972. break;
  3973. case TXRX_RX_HOST_STATS:
  3974. dp_print_pdev_rx_stats(pdev);
  3975. dp_print_soc_rx_stats(pdev->soc);
  3976. break;
  3977. case TXRX_AST_STATS:
  3978. dp_print_ast_stats(pdev->soc);
  3979. break;
  3980. case TXRX_SRNG_PTR_STATS:
  3981. dp_print_ring_stats(pdev);
  3982. break;
  3983. default:
  3984. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3985. break;
  3986. }
  3987. return 0;
  3988. }
  3989. /*
  3990. * dp_get_host_peer_stats()- function to print peer stats
  3991. * @pdev_handle: DP_PDEV handle
  3992. * @mac_addr: mac address of the peer
  3993. *
  3994. * Return: void
  3995. */
  3996. static void
  3997. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3998. {
  3999. struct dp_peer *peer;
  4000. uint8_t local_id;
  4001. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4002. &local_id);
  4003. if (!peer) {
  4004. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4005. "%s: Invalid peer\n", __func__);
  4006. return;
  4007. }
  4008. dp_print_peer_stats(peer);
  4009. dp_peer_rxtid_stats(peer);
  4010. return;
  4011. }
  4012. /*
  4013. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4014. * @pdev: DP_PDEV handle
  4015. *
  4016. * Return: void
  4017. */
  4018. static void
  4019. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4020. {
  4021. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4022. htt_tlv_filter.mpdu_start = 0;
  4023. htt_tlv_filter.msdu_start = 0;
  4024. htt_tlv_filter.packet = 0;
  4025. htt_tlv_filter.msdu_end = 0;
  4026. htt_tlv_filter.mpdu_end = 0;
  4027. htt_tlv_filter.packet_header = 1;
  4028. htt_tlv_filter.attention = 1;
  4029. htt_tlv_filter.ppdu_start = 1;
  4030. htt_tlv_filter.ppdu_end = 1;
  4031. htt_tlv_filter.ppdu_end_user_stats = 1;
  4032. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4033. htt_tlv_filter.ppdu_end_status_done = 1;
  4034. htt_tlv_filter.enable_fp = 1;
  4035. htt_tlv_filter.enable_md = 0;
  4036. htt_tlv_filter.enable_mo = 0;
  4037. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4038. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4039. RX_BUFFER_SIZE, &htt_tlv_filter);
  4040. }
  4041. /*
  4042. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4043. * @pdev_handle: DP_PDEV handle
  4044. *
  4045. * Return: void
  4046. */
  4047. static void
  4048. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4049. {
  4050. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4051. pdev->enhanced_stats_en = 1;
  4052. dp_ppdu_ring_cfg(pdev);
  4053. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4054. }
  4055. /*
  4056. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4057. * @pdev_handle: DP_PDEV handle
  4058. *
  4059. * Return: void
  4060. */
  4061. static void
  4062. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4063. {
  4064. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4065. pdev->enhanced_stats_en = 0;
  4066. }
  4067. /*
  4068. * dp_get_fw_peer_stats()- function to print peer stats
  4069. * @pdev_handle: DP_PDEV handle
  4070. * @mac_addr: mac address of the peer
  4071. * @cap: Type of htt stats requested
  4072. *
  4073. * Currently Supporting only MAC ID based requests Only
  4074. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4075. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4076. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4077. *
  4078. * Return: void
  4079. */
  4080. static void
  4081. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4082. uint32_t cap)
  4083. {
  4084. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4085. uint32_t config_param0 = 0;
  4086. uint32_t config_param1 = 0;
  4087. uint32_t config_param2 = 0;
  4088. uint32_t config_param3 = 0;
  4089. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4090. config_param0 |= (1 << (cap + 1));
  4091. config_param1 = 0x8f;
  4092. config_param2 |= (mac_addr[0] & 0x000000ff);
  4093. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4094. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4095. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4096. config_param3 |= (mac_addr[4] & 0x000000ff);
  4097. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4098. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4099. config_param0, config_param1, config_param2,
  4100. config_param3);
  4101. }
  4102. /*
  4103. * dp_set_vdev_param: function to set parameters in vdev
  4104. * @param: parameter type to be set
  4105. * @val: value of parameter to be set
  4106. *
  4107. * return: void
  4108. */
  4109. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4110. enum cdp_vdev_param_type param, uint32_t val)
  4111. {
  4112. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4113. switch (param) {
  4114. case CDP_ENABLE_WDS:
  4115. vdev->wds_enabled = val;
  4116. break;
  4117. case CDP_ENABLE_NAWDS:
  4118. vdev->nawds_enabled = val;
  4119. break;
  4120. case CDP_ENABLE_MCAST_EN:
  4121. vdev->mcast_enhancement_en = val;
  4122. break;
  4123. case CDP_ENABLE_PROXYSTA:
  4124. vdev->proxysta_vdev = val;
  4125. break;
  4126. case CDP_UPDATE_TDLS_FLAGS:
  4127. vdev->tdls_link_connected = val;
  4128. break;
  4129. case CDP_CFG_WDS_AGING_TIMER:
  4130. if (val == 0)
  4131. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4132. else if (val != vdev->wds_aging_timer_val)
  4133. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4134. vdev->wds_aging_timer_val = val;
  4135. break;
  4136. case CDP_ENABLE_AP_BRIDGE:
  4137. if (wlan_op_mode_sta != vdev->opmode)
  4138. vdev->ap_bridge_enabled = val;
  4139. else
  4140. vdev->ap_bridge_enabled = false;
  4141. break;
  4142. default:
  4143. break;
  4144. }
  4145. dp_tx_vdev_update_search_flags(vdev);
  4146. }
  4147. /**
  4148. * dp_peer_set_nawds: set nawds bit in peer
  4149. * @peer_handle: pointer to peer
  4150. * @value: enable/disable nawds
  4151. *
  4152. * return: void
  4153. */
  4154. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4155. {
  4156. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4157. peer->nawds_enabled = value;
  4158. }
  4159. /*
  4160. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4161. * @vdev_handle: DP_VDEV handle
  4162. * @map_id:ID of map that needs to be updated
  4163. *
  4164. * Return: void
  4165. */
  4166. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4167. uint8_t map_id)
  4168. {
  4169. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4170. vdev->dscp_tid_map_id = map_id;
  4171. return;
  4172. }
  4173. /**
  4174. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4175. * @pdev: DP_PDEV handle
  4176. * @map_id: ID of map that needs to be updated
  4177. * @tos: index value in map
  4178. * @tid: tid value passed by the user
  4179. *
  4180. * Return: void
  4181. */
  4182. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4183. uint8_t map_id, uint8_t tos, uint8_t tid)
  4184. {
  4185. uint8_t dscp;
  4186. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4187. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4188. pdev->dscp_tid_map[map_id][dscp] = tid;
  4189. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4190. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4191. map_id, dscp);
  4192. return;
  4193. }
  4194. /**
  4195. * dp_fw_stats_process(): Process TxRX FW stats request
  4196. * @vdev_handle: DP VDEV handle
  4197. * @val: value passed by user
  4198. *
  4199. * return: int
  4200. */
  4201. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4202. {
  4203. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4204. struct dp_pdev *pdev = NULL;
  4205. if (!vdev) {
  4206. DP_TRACE(NONE, "VDEV not found");
  4207. return 1;
  4208. }
  4209. pdev = vdev->pdev;
  4210. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4211. }
  4212. /*
  4213. * dp_txrx_stats() - function to map to firmware and host stats
  4214. * @vdev: virtual handle
  4215. * @stats: type of statistics requested
  4216. *
  4217. * Return: integer
  4218. */
  4219. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4220. {
  4221. int host_stats;
  4222. int fw_stats;
  4223. if (stats >= CDP_TXRX_MAX_STATS)
  4224. return 0;
  4225. /*
  4226. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4227. * has to be updated if new FW HTT stats added
  4228. */
  4229. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4230. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4231. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4232. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4234. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4235. stats, fw_stats, host_stats);
  4236. if (fw_stats != TXRX_FW_STATS_INVALID)
  4237. return dp_fw_stats_process(vdev, fw_stats);
  4238. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4239. (host_stats <= TXRX_HOST_STATS_MAX))
  4240. return dp_print_host_stats(vdev, host_stats);
  4241. else
  4242. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4243. "Wrong Input for TxRx Stats");
  4244. return 0;
  4245. }
  4246. /*
  4247. * dp_print_napi_stats(): NAPI stats
  4248. * @soc - soc handle
  4249. */
  4250. static void dp_print_napi_stats(struct dp_soc *soc)
  4251. {
  4252. hif_print_napi_stats(soc->hif_handle);
  4253. }
  4254. /*
  4255. * dp_print_per_ring_stats(): Packet count per ring
  4256. * @soc - soc handle
  4257. */
  4258. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4259. {
  4260. uint8_t core, ring;
  4261. uint64_t total_packets;
  4262. DP_TRACE(FATAL, "Reo packets per ring:");
  4263. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4264. total_packets = 0;
  4265. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4266. for (core = 0; core < NR_CPUS; core++) {
  4267. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4268. core, soc->stats.rx.ring_packets[core][ring]);
  4269. total_packets += soc->stats.rx.ring_packets[core][ring];
  4270. }
  4271. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4272. ring, total_packets);
  4273. }
  4274. }
  4275. /*
  4276. * dp_txrx_path_stats() - Function to display dump stats
  4277. * @soc - soc handle
  4278. *
  4279. * return: none
  4280. */
  4281. static void dp_txrx_path_stats(struct dp_soc *soc)
  4282. {
  4283. uint8_t error_code;
  4284. uint8_t loop_pdev;
  4285. struct dp_pdev *pdev;
  4286. uint8_t i;
  4287. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4288. pdev = soc->pdev_list[loop_pdev];
  4289. dp_aggregate_pdev_stats(pdev);
  4290. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4291. "Tx path Statistics:");
  4292. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4293. pdev->stats.tx_i.rcvd.num,
  4294. pdev->stats.tx_i.rcvd.bytes);
  4295. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4296. pdev->stats.tx_i.processed.num,
  4297. pdev->stats.tx_i.processed.bytes);
  4298. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4299. pdev->stats.tx.tx_success.num,
  4300. pdev->stats.tx.tx_success.bytes);
  4301. DP_TRACE(FATAL, "Dropped in host:");
  4302. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4303. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4304. DP_TRACE(FATAL, "Descriptor not available: %u",
  4305. pdev->stats.tx_i.dropped.desc_na);
  4306. DP_TRACE(FATAL, "Ring full: %u",
  4307. pdev->stats.tx_i.dropped.ring_full);
  4308. DP_TRACE(FATAL, "Enqueue fail: %u",
  4309. pdev->stats.tx_i.dropped.enqueue_fail);
  4310. DP_TRACE(FATAL, "DMA Error: %u",
  4311. pdev->stats.tx_i.dropped.dma_error);
  4312. DP_TRACE(FATAL, "Dropped in hardware:");
  4313. DP_TRACE(FATAL, "total packets dropped: %u",
  4314. pdev->stats.tx.tx_failed);
  4315. DP_TRACE(FATAL, "mpdu age out: %u",
  4316. pdev->stats.tx.dropped.age_out);
  4317. DP_TRACE(FATAL, "firmware removed: %u",
  4318. pdev->stats.tx.dropped.fw_rem);
  4319. DP_TRACE(FATAL, "firmware removed tx: %u",
  4320. pdev->stats.tx.dropped.fw_rem_tx);
  4321. DP_TRACE(FATAL, "firmware removed notx %u",
  4322. pdev->stats.tx.dropped.fw_rem_notx);
  4323. DP_TRACE(FATAL, "peer_invalid: %u",
  4324. pdev->soc->stats.tx.tx_invalid_peer.num);
  4325. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4326. DP_TRACE(FATAL, "Single Packet: %u",
  4327. pdev->stats.tx_comp_histogram.pkts_1);
  4328. DP_TRACE(FATAL, "2-20 Packets: %u",
  4329. pdev->stats.tx_comp_histogram.pkts_2_20);
  4330. DP_TRACE(FATAL, "21-40 Packets: %u",
  4331. pdev->stats.tx_comp_histogram.pkts_21_40);
  4332. DP_TRACE(FATAL, "41-60 Packets: %u",
  4333. pdev->stats.tx_comp_histogram.pkts_41_60);
  4334. DP_TRACE(FATAL, "61-80 Packets: %u",
  4335. pdev->stats.tx_comp_histogram.pkts_61_80);
  4336. DP_TRACE(FATAL, "81-100 Packets: %u",
  4337. pdev->stats.tx_comp_histogram.pkts_81_100);
  4338. DP_TRACE(FATAL, "101-200 Packets: %u",
  4339. pdev->stats.tx_comp_histogram.pkts_101_200);
  4340. DP_TRACE(FATAL, " 201+ Packets: %u",
  4341. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4342. DP_TRACE(FATAL, "Rx path statistics");
  4343. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4344. pdev->stats.rx.to_stack.num,
  4345. pdev->stats.rx.to_stack.bytes);
  4346. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4347. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4348. i, pdev->stats.rx.rcvd_reo[i].num,
  4349. pdev->stats.rx.rcvd_reo[i].bytes);
  4350. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4351. pdev->stats.rx.intra_bss.pkts.num,
  4352. pdev->stats.rx.intra_bss.pkts.bytes);
  4353. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4354. pdev->stats.rx.intra_bss.fail.num,
  4355. pdev->stats.rx.intra_bss.fail.bytes);
  4356. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4357. pdev->stats.rx.raw.num,
  4358. pdev->stats.rx.raw.bytes);
  4359. DP_TRACE(FATAL, "dropped: error %u msdus",
  4360. pdev->stats.rx.err.mic_err);
  4361. DP_TRACE(FATAL, "peer invalid %u",
  4362. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4363. DP_TRACE(FATAL, "Reo Statistics");
  4364. DP_TRACE(FATAL, "rbm error: %u msdus",
  4365. pdev->soc->stats.rx.err.invalid_rbm);
  4366. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4367. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4368. DP_TRACE(FATAL, "Reo errors");
  4369. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4370. error_code++) {
  4371. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4372. error_code,
  4373. pdev->soc->stats.rx.err.reo_error[error_code]);
  4374. }
  4375. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4376. error_code++) {
  4377. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4378. error_code,
  4379. pdev->soc->stats.rx.err
  4380. .rxdma_error[error_code]);
  4381. }
  4382. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4383. DP_TRACE(FATAL, "Single Packet: %u",
  4384. pdev->stats.rx_ind_histogram.pkts_1);
  4385. DP_TRACE(FATAL, "2-20 Packets: %u",
  4386. pdev->stats.rx_ind_histogram.pkts_2_20);
  4387. DP_TRACE(FATAL, "21-40 Packets: %u",
  4388. pdev->stats.rx_ind_histogram.pkts_21_40);
  4389. DP_TRACE(FATAL, "41-60 Packets: %u",
  4390. pdev->stats.rx_ind_histogram.pkts_41_60);
  4391. DP_TRACE(FATAL, "61-80 Packets: %u",
  4392. pdev->stats.rx_ind_histogram.pkts_61_80);
  4393. DP_TRACE(FATAL, "81-100 Packets: %u",
  4394. pdev->stats.rx_ind_histogram.pkts_81_100);
  4395. DP_TRACE(FATAL, "101-200 Packets: %u",
  4396. pdev->stats.rx_ind_histogram.pkts_101_200);
  4397. DP_TRACE(FATAL, " 201+ Packets: %u",
  4398. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4399. }
  4400. }
  4401. /*
  4402. * dp_txrx_dump_stats() - Dump statistics
  4403. * @value - Statistics option
  4404. */
  4405. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4406. {
  4407. struct dp_soc *soc =
  4408. (struct dp_soc *)psoc;
  4409. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4410. if (!soc) {
  4411. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4412. "%s: soc is NULL", __func__);
  4413. return QDF_STATUS_E_INVAL;
  4414. }
  4415. switch (value) {
  4416. case CDP_TXRX_PATH_STATS:
  4417. dp_txrx_path_stats(soc);
  4418. break;
  4419. case CDP_RX_RING_STATS:
  4420. dp_print_per_ring_stats(soc);
  4421. break;
  4422. case CDP_TXRX_TSO_STATS:
  4423. /* TODO: NOT IMPLEMENTED */
  4424. break;
  4425. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4426. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4427. break;
  4428. case CDP_DP_NAPI_STATS:
  4429. dp_print_napi_stats(soc);
  4430. break;
  4431. case CDP_TXRX_DESC_STATS:
  4432. /* TODO: NOT IMPLEMENTED */
  4433. break;
  4434. default:
  4435. status = QDF_STATUS_E_INVAL;
  4436. break;
  4437. }
  4438. return status;
  4439. }
  4440. static struct cdp_wds_ops dp_ops_wds = {
  4441. .vdev_set_wds = dp_vdev_set_wds,
  4442. };
  4443. /*
  4444. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4445. * @soc - datapath soc handle
  4446. * @peer - datapath peer handle
  4447. *
  4448. * Delete the AST entries belonging to a peer
  4449. */
  4450. #ifdef FEATURE_WDS
  4451. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4452. struct dp_peer *peer)
  4453. {
  4454. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4455. qdf_spin_lock_bh(&soc->ast_lock);
  4456. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4457. if (ast_entry->next_hop) {
  4458. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4459. peer->vdev->pdev->osif_pdev,
  4460. ast_entry->mac_addr.raw);
  4461. }
  4462. dp_peer_del_ast(soc, ast_entry);
  4463. }
  4464. qdf_spin_unlock_bh(&soc->ast_lock);
  4465. }
  4466. #else
  4467. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4468. struct dp_peer *peer)
  4469. {
  4470. }
  4471. #endif
  4472. #ifdef CONFIG_WIN
  4473. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4474. {
  4475. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4476. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4477. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4478. dp_peer_delete_ast_entries(soc, peer);
  4479. }
  4480. #endif
  4481. static struct cdp_cmn_ops dp_ops_cmn = {
  4482. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4483. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4484. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4485. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4486. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4487. .txrx_peer_create = dp_peer_create_wifi3,
  4488. .txrx_peer_setup = dp_peer_setup_wifi3,
  4489. #ifdef CONFIG_WIN
  4490. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4491. #else
  4492. .txrx_peer_teardown = NULL,
  4493. #endif
  4494. .txrx_peer_delete = dp_peer_delete_wifi3,
  4495. .txrx_vdev_register = dp_vdev_register_wifi3,
  4496. .txrx_soc_detach = dp_soc_detach_wifi3,
  4497. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4498. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4499. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4500. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4501. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4502. .delba_process = dp_delba_process_wifi3,
  4503. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4504. .flush_cache_rx_queue = NULL,
  4505. /* TODO: get API's for dscp-tid need to be added*/
  4506. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4507. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4508. .txrx_stats = dp_txrx_stats,
  4509. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4510. .display_stats = dp_txrx_dump_stats,
  4511. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4512. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4513. #ifdef DP_INTR_POLL_BASED
  4514. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4515. #else
  4516. .txrx_intr_attach = dp_soc_interrupt_attach,
  4517. #endif
  4518. .txrx_intr_detach = dp_soc_interrupt_detach,
  4519. .set_pn_check = dp_set_pn_check_wifi3,
  4520. /* TODO: Add other functions */
  4521. };
  4522. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4523. .txrx_peer_authorize = dp_peer_authorize,
  4524. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4525. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4526. #ifdef MESH_MODE_SUPPORT
  4527. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4528. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4529. #endif
  4530. .txrx_set_vdev_param = dp_set_vdev_param,
  4531. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4532. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4533. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4534. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4535. .txrx_update_filter_neighbour_peers =
  4536. dp_update_filter_neighbour_peers,
  4537. .txrx_get_sec_type = dp_get_sec_type,
  4538. /* TODO: Add other functions */
  4539. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4540. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4541. };
  4542. static struct cdp_me_ops dp_ops_me = {
  4543. #ifdef ATH_SUPPORT_IQUE
  4544. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4545. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4546. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4547. #endif
  4548. };
  4549. static struct cdp_mon_ops dp_ops_mon = {
  4550. .txrx_monitor_set_filter_ucast_data = NULL,
  4551. .txrx_monitor_set_filter_mcast_data = NULL,
  4552. .txrx_monitor_set_filter_non_data = NULL,
  4553. .txrx_monitor_get_filter_ucast_data = NULL,
  4554. .txrx_monitor_get_filter_mcast_data = NULL,
  4555. .txrx_monitor_get_filter_non_data = NULL,
  4556. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4557. };
  4558. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4559. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4560. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4561. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4562. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4563. /* TODO */
  4564. };
  4565. static struct cdp_raw_ops dp_ops_raw = {
  4566. /* TODO */
  4567. };
  4568. #ifdef CONFIG_WIN
  4569. static struct cdp_pflow_ops dp_ops_pflow = {
  4570. /* TODO */
  4571. };
  4572. #endif /* CONFIG_WIN */
  4573. #ifdef FEATURE_RUNTIME_PM
  4574. /**
  4575. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4576. * @opaque_pdev: DP pdev context
  4577. *
  4578. * DP is ready to runtime suspend if there are no pending TX packets.
  4579. *
  4580. * Return: QDF_STATUS
  4581. */
  4582. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4583. {
  4584. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4585. struct dp_soc *soc = pdev->soc;
  4586. /* Call DP TX flow control API to check if there is any
  4587. pending packets */
  4588. if (soc->intr_mode == DP_INTR_POLL)
  4589. qdf_timer_stop(&soc->int_timer);
  4590. return QDF_STATUS_SUCCESS;
  4591. }
  4592. /**
  4593. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4594. * @opaque_pdev: DP pdev context
  4595. *
  4596. * Resume DP for runtime PM.
  4597. *
  4598. * Return: QDF_STATUS
  4599. */
  4600. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4601. {
  4602. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4603. struct dp_soc *soc = pdev->soc;
  4604. void *hal_srng;
  4605. int i;
  4606. if (soc->intr_mode == DP_INTR_POLL)
  4607. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4608. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4609. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4610. if (hal_srng) {
  4611. /* We actually only need to acquire the lock */
  4612. hal_srng_access_start(soc->hal_soc, hal_srng);
  4613. /* Update SRC ring head pointer for HW to send
  4614. all pending packets */
  4615. hal_srng_access_end(soc->hal_soc, hal_srng);
  4616. }
  4617. }
  4618. return QDF_STATUS_SUCCESS;
  4619. }
  4620. #endif /* FEATURE_RUNTIME_PM */
  4621. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4622. {
  4623. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4624. struct dp_soc *soc = pdev->soc;
  4625. if (soc->intr_mode == DP_INTR_POLL)
  4626. qdf_timer_stop(&soc->int_timer);
  4627. return QDF_STATUS_SUCCESS;
  4628. }
  4629. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4630. {
  4631. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4632. struct dp_soc *soc = pdev->soc;
  4633. if (soc->intr_mode == DP_INTR_POLL)
  4634. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4635. return QDF_STATUS_SUCCESS;
  4636. }
  4637. #ifndef CONFIG_WIN
  4638. static struct cdp_misc_ops dp_ops_misc = {
  4639. .get_opmode = dp_get_opmode,
  4640. #ifdef FEATURE_RUNTIME_PM
  4641. .runtime_suspend = dp_runtime_suspend,
  4642. .runtime_resume = dp_runtime_resume,
  4643. #endif /* FEATURE_RUNTIME_PM */
  4644. };
  4645. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4646. /* WIFI 3.0 DP implement as required. */
  4647. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4648. .register_pause_cb = dp_txrx_register_pause_cb,
  4649. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4650. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4651. };
  4652. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4653. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4654. };
  4655. #ifdef IPA_OFFLOAD
  4656. static struct cdp_ipa_ops dp_ops_ipa = {
  4657. .ipa_get_resource = dp_ipa_get_resource,
  4658. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4659. .ipa_op_response = dp_ipa_op_response,
  4660. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4661. .ipa_get_stat = dp_ipa_get_stat,
  4662. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4663. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4664. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4665. .ipa_setup = dp_ipa_setup,
  4666. .ipa_cleanup = dp_ipa_cleanup,
  4667. .ipa_setup_iface = dp_ipa_setup_iface,
  4668. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4669. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4670. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4671. .ipa_set_perf_level = dp_ipa_set_perf_level
  4672. };
  4673. #endif
  4674. static struct cdp_bus_ops dp_ops_bus = {
  4675. .bus_suspend = dp_bus_suspend,
  4676. .bus_resume = dp_bus_resume
  4677. };
  4678. static struct cdp_ocb_ops dp_ops_ocb = {
  4679. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4680. };
  4681. static struct cdp_throttle_ops dp_ops_throttle = {
  4682. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4683. };
  4684. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4685. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4686. };
  4687. static struct cdp_cfg_ops dp_ops_cfg = {
  4688. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4689. };
  4690. static struct cdp_peer_ops dp_ops_peer = {
  4691. .register_peer = dp_register_peer,
  4692. .clear_peer = dp_clear_peer,
  4693. .find_peer_by_addr = dp_find_peer_by_addr,
  4694. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4695. .local_peer_id = dp_local_peer_id,
  4696. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4697. .peer_state_update = dp_peer_state_update,
  4698. .get_vdevid = dp_get_vdevid,
  4699. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4700. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4701. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4702. .get_peer_state = dp_get_peer_state,
  4703. .last_assoc_received = dp_get_last_assoc_received,
  4704. .last_disassoc_received = dp_get_last_disassoc_received,
  4705. .last_deauth_received = dp_get_last_deauth_received,
  4706. };
  4707. #endif
  4708. static struct cdp_ops dp_txrx_ops = {
  4709. .cmn_drv_ops = &dp_ops_cmn,
  4710. .ctrl_ops = &dp_ops_ctrl,
  4711. .me_ops = &dp_ops_me,
  4712. .mon_ops = &dp_ops_mon,
  4713. .host_stats_ops = &dp_ops_host_stats,
  4714. .wds_ops = &dp_ops_wds,
  4715. .raw_ops = &dp_ops_raw,
  4716. #ifdef CONFIG_WIN
  4717. .pflow_ops = &dp_ops_pflow,
  4718. #endif /* CONFIG_WIN */
  4719. #ifndef CONFIG_WIN
  4720. .misc_ops = &dp_ops_misc,
  4721. .cfg_ops = &dp_ops_cfg,
  4722. .flowctl_ops = &dp_ops_flowctl,
  4723. .l_flowctl_ops = &dp_ops_l_flowctl,
  4724. #ifdef IPA_OFFLOAD
  4725. .ipa_ops = &dp_ops_ipa,
  4726. #endif
  4727. .bus_ops = &dp_ops_bus,
  4728. .ocb_ops = &dp_ops_ocb,
  4729. .peer_ops = &dp_ops_peer,
  4730. .throttle_ops = &dp_ops_throttle,
  4731. .mob_stats_ops = &dp_ops_mob_stats,
  4732. #endif
  4733. };
  4734. /*
  4735. * dp_soc_set_txrx_ring_map()
  4736. * @dp_soc: DP handler for soc
  4737. *
  4738. * Return: Void
  4739. */
  4740. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4741. {
  4742. uint32_t i;
  4743. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4744. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4745. }
  4746. }
  4747. /*
  4748. * dp_soc_attach_wifi3() - Attach txrx SOC
  4749. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4750. * @htc_handle: Opaque HTC handle
  4751. * @hif_handle: Opaque HIF handle
  4752. * @qdf_osdev: QDF device
  4753. *
  4754. * Return: DP SOC handle on success, NULL on failure
  4755. */
  4756. /*
  4757. * Local prototype added to temporarily address warning caused by
  4758. * -Wmissing-prototypes. A more correct solution, namely to expose
  4759. * a prototype in an appropriate header file, will come later.
  4760. */
  4761. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4762. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4763. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4764. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4765. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4766. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4767. {
  4768. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4769. if (!soc) {
  4770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4771. FL("DP SOC memory allocation failed"));
  4772. goto fail0;
  4773. }
  4774. soc->cdp_soc.ops = &dp_txrx_ops;
  4775. soc->cdp_soc.ol_ops = ol_ops;
  4776. soc->osif_soc = osif_soc;
  4777. soc->osdev = qdf_osdev;
  4778. soc->hif_handle = hif_handle;
  4779. soc->psoc = psoc;
  4780. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4781. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4782. soc->hal_soc, qdf_osdev);
  4783. if (!soc->htt_handle) {
  4784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4785. FL("HTT attach failed"));
  4786. goto fail1;
  4787. }
  4788. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4789. if (!soc->wlan_cfg_ctx) {
  4790. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4791. FL("wlan_cfg_soc_attach failed"));
  4792. goto fail2;
  4793. }
  4794. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4795. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4796. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4797. CDP_CFG_MAX_PEER_ID);
  4798. if (ret != -EINVAL) {
  4799. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4800. }
  4801. }
  4802. qdf_spinlock_create(&soc->peer_ref_mutex);
  4803. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4804. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4805. /* fill the tx/rx cpu ring map*/
  4806. dp_soc_set_txrx_ring_map(soc);
  4807. qdf_spinlock_create(&soc->htt_stats.lock);
  4808. /* initialize work queue for stats processing */
  4809. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4810. return (void *)soc;
  4811. fail2:
  4812. htt_soc_detach(soc->htt_handle);
  4813. fail1:
  4814. qdf_mem_free(soc);
  4815. fail0:
  4816. return NULL;
  4817. }
  4818. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4819. /*
  4820. * dp_set_pktlog_wifi3() - attach txrx vdev
  4821. * @pdev: Datapath PDEV handle
  4822. * @event: which event's notifications are being subscribed to
  4823. * @enable: WDI event subscribe or not. (True or False)
  4824. *
  4825. * Return: Success, NULL on failure
  4826. */
  4827. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4828. bool enable)
  4829. {
  4830. struct dp_soc *soc = pdev->soc;
  4831. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4832. if (enable) {
  4833. switch (event) {
  4834. case WDI_EVENT_RX_DESC:
  4835. if (pdev->monitor_vdev) {
  4836. /* Nothing needs to be done if monitor mode is
  4837. * enabled
  4838. */
  4839. return 0;
  4840. }
  4841. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4842. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4843. htt_tlv_filter.mpdu_start = 1;
  4844. htt_tlv_filter.msdu_start = 1;
  4845. htt_tlv_filter.msdu_end = 1;
  4846. htt_tlv_filter.mpdu_end = 1;
  4847. htt_tlv_filter.packet_header = 1;
  4848. htt_tlv_filter.attention = 1;
  4849. htt_tlv_filter.ppdu_start = 1;
  4850. htt_tlv_filter.ppdu_end = 1;
  4851. htt_tlv_filter.ppdu_end_user_stats = 1;
  4852. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4853. htt_tlv_filter.ppdu_end_status_done = 1;
  4854. htt_tlv_filter.enable_fp = 1;
  4855. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4856. pdev->pdev_id,
  4857. pdev->rxdma_mon_status_ring.hal_srng,
  4858. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4859. &htt_tlv_filter);
  4860. }
  4861. break;
  4862. case WDI_EVENT_LITE_RX:
  4863. if (pdev->monitor_vdev) {
  4864. /* Nothing needs to be done if monitor mode is
  4865. * enabled
  4866. */
  4867. return 0;
  4868. }
  4869. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4870. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4871. htt_tlv_filter.ppdu_start = 1;
  4872. htt_tlv_filter.ppdu_end = 1;
  4873. htt_tlv_filter.ppdu_end_user_stats = 1;
  4874. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4875. htt_tlv_filter.ppdu_end_status_done = 1;
  4876. htt_tlv_filter.enable_fp = 1;
  4877. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4878. pdev->pdev_id,
  4879. pdev->rxdma_mon_status_ring.hal_srng,
  4880. RXDMA_MONITOR_STATUS,
  4881. RX_BUFFER_SIZE_PKTLOG_LITE,
  4882. &htt_tlv_filter);
  4883. }
  4884. break;
  4885. case WDI_EVENT_LITE_T2H:
  4886. if (pdev->monitor_vdev) {
  4887. /* Nothing needs to be done if monitor mode is
  4888. * enabled
  4889. */
  4890. return 0;
  4891. }
  4892. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4893. * passing value 0xffff. Once these macros will define in htt
  4894. * header file will use proper macros
  4895. */
  4896. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4897. break;
  4898. default:
  4899. /* Nothing needs to be done for other pktlog types */
  4900. break;
  4901. }
  4902. } else {
  4903. switch (event) {
  4904. case WDI_EVENT_RX_DESC:
  4905. case WDI_EVENT_LITE_RX:
  4906. if (pdev->monitor_vdev) {
  4907. /* Nothing needs to be done if monitor mode is
  4908. * enabled
  4909. */
  4910. return 0;
  4911. }
  4912. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4913. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4914. /* htt_tlv_filter is initialized to 0 */
  4915. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4916. pdev->pdev_id,
  4917. pdev->rxdma_mon_status_ring.hal_srng,
  4918. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4919. &htt_tlv_filter);
  4920. }
  4921. break;
  4922. case WDI_EVENT_LITE_T2H:
  4923. if (pdev->monitor_vdev) {
  4924. /* Nothing needs to be done if monitor mode is
  4925. * enabled
  4926. */
  4927. return 0;
  4928. }
  4929. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4930. * passing value 0. Once these macros will define in htt
  4931. * header file will use proper macros
  4932. */
  4933. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4934. break;
  4935. default:
  4936. /* Nothing needs to be done for other pktlog types */
  4937. break;
  4938. }
  4939. }
  4940. return 0;
  4941. }
  4942. #endif