dp_ctrl.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/completion.h>
  7. #include <linux/delay.h>
  8. #include <drm/drm_fixed.h>
  9. #include "dp_ctrl.h"
  10. #include "dp_debug.h"
  11. #define DP_MST_DEBUG(fmt, ...) DP_DEBUG(fmt, ##__VA_ARGS__)
  12. #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
  13. #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
  14. #define DP_CTRL_INTR_MST_DP0_VCPF_SENT BIT(0)
  15. #define DP_CTRL_INTR_MST_DP1_VCPF_SENT BIT(3)
  16. /* dp state ctrl */
  17. #define ST_TRAIN_PATTERN_1 BIT(0)
  18. #define ST_TRAIN_PATTERN_2 BIT(1)
  19. #define ST_TRAIN_PATTERN_3 BIT(2)
  20. #define ST_TRAIN_PATTERN_4 BIT(3)
  21. #define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(4)
  22. #define ST_PRBS7 BIT(5)
  23. #define ST_CUSTOM_80_BIT_PATTERN BIT(6)
  24. #define ST_SEND_VIDEO BIT(7)
  25. #define ST_PUSH_IDLE BIT(8)
  26. #define MST_DP0_PUSH_VCPF BIT(12)
  27. #define MST_DP0_FORCE_VCPF BIT(13)
  28. #define MST_DP1_PUSH_VCPF BIT(14)
  29. #define MST_DP1_FORCE_VCPF BIT(15)
  30. #define MR_LINK_TRAINING1 0x8
  31. #define MR_LINK_SYMBOL_ERM 0x80
  32. #define MR_LINK_PRBS7 0x100
  33. #define MR_LINK_CUSTOM80 0x200
  34. #define MR_LINK_TRAINING4 0x40
  35. #define DP_MAX_LANES 4
  36. struct dp_mst_ch_slot_info {
  37. u32 start_slot;
  38. u32 tot_slots;
  39. };
  40. struct dp_mst_channel_info {
  41. struct dp_mst_ch_slot_info slot_info[DP_STREAM_MAX];
  42. };
  43. struct dp_ctrl_private {
  44. struct dp_ctrl dp_ctrl;
  45. struct device *dev;
  46. struct dp_aux *aux;
  47. struct dp_panel *panel;
  48. struct dp_link *link;
  49. struct dp_power *power;
  50. struct dp_parser *parser;
  51. struct dp_catalog_ctrl *catalog;
  52. struct completion idle_comp;
  53. struct completion video_comp;
  54. bool orientation;
  55. bool power_on;
  56. bool mst_mode;
  57. bool fec_mode;
  58. bool dsc_mode;
  59. bool sim_mode;
  60. atomic_t aborted;
  61. u8 initial_lane_count;
  62. u8 initial_bw_code;
  63. u32 vic;
  64. u32 stream_count;
  65. u32 training_2_pattern;
  66. struct dp_mst_channel_info mst_ch_info;
  67. };
  68. enum notification_status {
  69. NOTIFY_UNKNOWN,
  70. NOTIFY_CONNECT,
  71. NOTIFY_DISCONNECT,
  72. NOTIFY_CONNECT_IRQ_HPD,
  73. NOTIFY_DISCONNECT_IRQ_HPD,
  74. };
  75. static void dp_ctrl_idle_patterns_sent(struct dp_ctrl_private *ctrl)
  76. {
  77. DP_DEBUG("idle_patterns_sent\n");
  78. complete(&ctrl->idle_comp);
  79. }
  80. static void dp_ctrl_video_ready(struct dp_ctrl_private *ctrl)
  81. {
  82. DP_DEBUG("dp_video_ready\n");
  83. complete(&ctrl->video_comp);
  84. }
  85. static void dp_ctrl_abort(struct dp_ctrl *dp_ctrl, bool abort)
  86. {
  87. struct dp_ctrl_private *ctrl;
  88. if (!dp_ctrl) {
  89. DP_ERR("Invalid input data\n");
  90. return;
  91. }
  92. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  93. atomic_set(&ctrl->aborted, abort);
  94. }
  95. static void dp_ctrl_state_ctrl(struct dp_ctrl_private *ctrl, u32 state)
  96. {
  97. ctrl->catalog->state_ctrl(ctrl->catalog, state);
  98. }
  99. static void dp_ctrl_push_idle(struct dp_ctrl_private *ctrl,
  100. enum dp_stream_id strm)
  101. {
  102. int const idle_pattern_completion_timeout_ms = HZ / 10;
  103. u32 state = 0x0;
  104. if (!ctrl->power_on)
  105. return;
  106. if (!ctrl->mst_mode) {
  107. state = ST_PUSH_IDLE;
  108. goto trigger_idle;
  109. }
  110. if (strm >= DP_STREAM_MAX) {
  111. DP_ERR("mst push idle, invalid stream:%d\n", strm);
  112. return;
  113. }
  114. state |= (strm == DP_STREAM_0) ? MST_DP0_PUSH_VCPF : MST_DP1_PUSH_VCPF;
  115. trigger_idle:
  116. reinit_completion(&ctrl->idle_comp);
  117. dp_ctrl_state_ctrl(ctrl, state);
  118. if (!wait_for_completion_timeout(&ctrl->idle_comp,
  119. idle_pattern_completion_timeout_ms))
  120. DP_WARN("time out\n");
  121. else
  122. DP_DEBUG("mainlink off done\n");
  123. }
  124. /**
  125. * dp_ctrl_configure_source_link_params() - configures DP TX source params
  126. * @ctrl: Display Port Driver data
  127. * @enable: enable or disable DP transmitter
  128. *
  129. * Configures the DP transmitter source params including details such as lane
  130. * configuration, output format and sink/panel timing information.
  131. */
  132. static void dp_ctrl_configure_source_link_params(struct dp_ctrl_private *ctrl,
  133. bool enable)
  134. {
  135. if (enable) {
  136. ctrl->catalog->lane_mapping(ctrl->catalog, ctrl->orientation,
  137. ctrl->parser->l_map);
  138. ctrl->catalog->lane_pnswap(ctrl->catalog,
  139. ctrl->parser->l_pnswap);
  140. ctrl->catalog->mst_config(ctrl->catalog, ctrl->mst_mode);
  141. ctrl->catalog->config_ctrl(ctrl->catalog,
  142. ctrl->link->link_params.lane_count);
  143. ctrl->catalog->mainlink_levels(ctrl->catalog,
  144. ctrl->link->link_params.lane_count);
  145. ctrl->catalog->mainlink_ctrl(ctrl->catalog, true);
  146. } else {
  147. ctrl->catalog->mainlink_ctrl(ctrl->catalog, false);
  148. }
  149. }
  150. static void dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
  151. {
  152. if (!wait_for_completion_timeout(&ctrl->video_comp, HZ / 2))
  153. DP_WARN("SEND_VIDEO time out\n");
  154. }
  155. static int dp_ctrl_update_sink_vx_px(struct dp_ctrl_private *ctrl)
  156. {
  157. int i, ret;
  158. u8 buf[DP_MAX_LANES];
  159. u8 v_level = ctrl->link->phy_params.v_level;
  160. u8 p_level = ctrl->link->phy_params.p_level;
  161. u8 size = min_t(u8, sizeof(buf), ctrl->link->link_params.lane_count);
  162. u32 max_level_reached = 0;
  163. if (v_level == DP_LINK_VOLTAGE_MAX) {
  164. DP_DEBUG("max voltage swing level reached %d\n", v_level);
  165. max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
  166. }
  167. if (p_level == DP_LINK_PRE_EMPHASIS_MAX) {
  168. DP_DEBUG("max pre-emphasis level reached %d\n", p_level);
  169. max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  170. }
  171. p_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
  172. for (i = 0; i < size; i++)
  173. buf[i] = v_level | p_level | max_level_reached;
  174. DP_DEBUG("lanes: %d, swing: 0x%x, pre-emp: 0x%x\n",
  175. size, v_level, p_level);
  176. ret = drm_dp_dpcd_write(ctrl->aux->drm_aux,
  177. DP_TRAINING_LANE0_SET, buf, size);
  178. return ret <= 0 ? -EINVAL : 0;
  179. }
  180. static void dp_ctrl_update_hw_vx_px(struct dp_ctrl_private *ctrl)
  181. {
  182. struct dp_link *link = ctrl->link;
  183. bool high = false;
  184. if (ctrl->link->link_params.bw_code == DP_LINK_BW_5_4 ||
  185. ctrl->link->link_params.bw_code == DP_LINK_BW_8_1)
  186. high = true;
  187. ctrl->catalog->update_vx_px(ctrl->catalog,
  188. link->phy_params.v_level, link->phy_params.p_level, high);
  189. }
  190. static int dp_ctrl_update_sink_pattern(struct dp_ctrl_private *ctrl, u8 pattern)
  191. {
  192. u8 buf = pattern;
  193. int ret;
  194. DP_DEBUG("sink: pattern=%x\n", pattern);
  195. if (pattern && pattern != DP_TRAINING_PATTERN_4)
  196. buf |= DP_LINK_SCRAMBLING_DISABLE;
  197. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  198. DP_TRAINING_PATTERN_SET, buf);
  199. return ret <= 0 ? -EINVAL : 0;
  200. }
  201. static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
  202. u8 *link_status)
  203. {
  204. int ret = 0, len;
  205. u32 const offset = DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS;
  206. u32 link_status_read_max_retries = 100;
  207. while (--link_status_read_max_retries) {
  208. len = drm_dp_dpcd_read_link_status(ctrl->aux->drm_aux,
  209. link_status);
  210. if (len != DP_LINK_STATUS_SIZE) {
  211. DP_ERR("DP link status read failed, err: %d\n", len);
  212. ret = len;
  213. break;
  214. }
  215. if (!(link_status[offset] & DP_LINK_STATUS_UPDATED))
  216. break;
  217. }
  218. return ret;
  219. }
  220. static int dp_ctrl_lane_count_down_shift(struct dp_ctrl_private *ctrl)
  221. {
  222. int ret = -EAGAIN;
  223. u8 lanes = ctrl->link->link_params.lane_count;
  224. if (ctrl->panel->link_info.revision != 0x14)
  225. return -EINVAL;
  226. switch (lanes) {
  227. case 4:
  228. ctrl->link->link_params.lane_count = 2;
  229. break;
  230. case 2:
  231. ctrl->link->link_params.lane_count = 1;
  232. break;
  233. default:
  234. if (lanes != ctrl->initial_lane_count)
  235. ret = -EINVAL;
  236. break;
  237. }
  238. DP_DEBUG("new lane count=%d\n", ctrl->link->link_params.lane_count);
  239. return ret;
  240. }
  241. static bool dp_ctrl_is_link_rate_rbr(struct dp_ctrl_private *ctrl)
  242. {
  243. return ctrl->link->link_params.bw_code == DP_LINK_BW_1_62;
  244. }
  245. static u8 dp_ctrl_get_active_lanes(struct dp_ctrl_private *ctrl,
  246. u8 *link_status)
  247. {
  248. u8 lane, count = 0;
  249. for (lane = 0; lane < ctrl->link->link_params.lane_count; lane++) {
  250. if (link_status[lane / 2] & (1 << (lane * 4)))
  251. count++;
  252. else
  253. break;
  254. }
  255. return count;
  256. }
  257. static int dp_ctrl_link_training_1(struct dp_ctrl_private *ctrl)
  258. {
  259. int tries, old_v_level, ret = -EINVAL;
  260. u8 link_status[DP_LINK_STATUS_SIZE];
  261. u8 pattern = 0;
  262. int const maximum_retries = 5;
  263. ctrl->aux->state &= ~DP_STATE_TRAIN_1_FAILED;
  264. ctrl->aux->state &= ~DP_STATE_TRAIN_1_SUCCEEDED;
  265. ctrl->aux->state |= DP_STATE_TRAIN_1_STARTED;
  266. if (ctrl->sim_mode) {
  267. DP_DEBUG("simulation enabled, skip clock recovery\n");
  268. ret = 0;
  269. goto skip_training;
  270. }
  271. dp_ctrl_state_ctrl(ctrl, 0);
  272. /* Make sure to clear the current pattern before starting a new one */
  273. wmb();
  274. tries = 0;
  275. old_v_level = ctrl->link->phy_params.v_level;
  276. while (!atomic_read(&ctrl->aborted)) {
  277. /* update hardware with current swing/pre-emp values */
  278. dp_ctrl_update_hw_vx_px(ctrl);
  279. if (!pattern) {
  280. pattern = DP_TRAINING_PATTERN_1;
  281. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  282. /* update sink with current settings */
  283. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  284. if (ret)
  285. break;
  286. }
  287. ret = dp_ctrl_update_sink_vx_px(ctrl);
  288. if (ret)
  289. break;
  290. drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
  291. ret = dp_ctrl_read_link_status(ctrl, link_status);
  292. if (ret)
  293. break;
  294. if (!drm_dp_clock_recovery_ok(link_status,
  295. ctrl->link->link_params.lane_count))
  296. ret = -EINVAL;
  297. else
  298. break;
  299. if (ctrl->link->phy_params.v_level == DP_LINK_VOLTAGE_MAX) {
  300. pr_err_ratelimited("max v_level reached\n");
  301. break;
  302. }
  303. if (old_v_level == ctrl->link->phy_params.v_level) {
  304. if (++tries >= maximum_retries) {
  305. DP_ERR("max tries reached\n");
  306. ret = -ETIMEDOUT;
  307. break;
  308. }
  309. } else {
  310. tries = 0;
  311. old_v_level = ctrl->link->phy_params.v_level;
  312. }
  313. DP_DEBUG("clock recovery not done, adjusting vx px\n");
  314. ctrl->link->adjust_levels(ctrl->link, link_status);
  315. }
  316. if (ret && dp_ctrl_is_link_rate_rbr(ctrl)) {
  317. u8 active_lanes = dp_ctrl_get_active_lanes(ctrl, link_status);
  318. if (active_lanes) {
  319. ctrl->link->link_params.lane_count = active_lanes;
  320. ctrl->link->link_params.bw_code = ctrl->initial_bw_code;
  321. /* retry with new settings */
  322. ret = -EAGAIN;
  323. }
  324. }
  325. skip_training:
  326. ctrl->aux->state &= ~DP_STATE_TRAIN_1_STARTED;
  327. if (ret)
  328. ctrl->aux->state |= DP_STATE_TRAIN_1_FAILED;
  329. else
  330. ctrl->aux->state |= DP_STATE_TRAIN_1_SUCCEEDED;
  331. return ret;
  332. }
  333. static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
  334. {
  335. int ret = 0;
  336. if (!ctrl)
  337. return -EINVAL;
  338. switch (ctrl->link->link_params.bw_code) {
  339. case DP_LINK_BW_8_1:
  340. ctrl->link->link_params.bw_code = DP_LINK_BW_5_4;
  341. break;
  342. case DP_LINK_BW_5_4:
  343. ctrl->link->link_params.bw_code = DP_LINK_BW_2_7;
  344. break;
  345. case DP_LINK_BW_2_7:
  346. case DP_LINK_BW_1_62:
  347. default:
  348. ctrl->link->link_params.bw_code = DP_LINK_BW_1_62;
  349. break;
  350. }
  351. DP_DEBUG("new bw code=0x%x\n", ctrl->link->link_params.bw_code);
  352. return ret;
  353. }
  354. static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
  355. {
  356. dp_ctrl_update_sink_pattern(ctrl, 0);
  357. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  358. }
  359. static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl)
  360. {
  361. int tries = 0, ret = -EINVAL;
  362. u8 dpcd_pattern, pattern = 0;
  363. int const maximum_retries = 5;
  364. u8 link_status[DP_LINK_STATUS_SIZE];
  365. ctrl->aux->state &= ~DP_STATE_TRAIN_2_FAILED;
  366. ctrl->aux->state &= ~DP_STATE_TRAIN_2_SUCCEEDED;
  367. ctrl->aux->state |= DP_STATE_TRAIN_2_STARTED;
  368. if (ctrl->sim_mode) {
  369. DP_DEBUG("simulation enabled, skip channel equalization\n");
  370. ret = 0;
  371. goto skip_training;
  372. }
  373. dp_ctrl_state_ctrl(ctrl, 0);
  374. /* Make sure to clear the current pattern before starting a new one */
  375. wmb();
  376. dpcd_pattern = ctrl->training_2_pattern;
  377. while (!atomic_read(&ctrl->aborted)) {
  378. /* update hardware with current swing/pre-emp values */
  379. dp_ctrl_update_hw_vx_px(ctrl);
  380. if (!pattern) {
  381. pattern = dpcd_pattern;
  382. /* program hw to send pattern */
  383. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  384. /* update sink with current pattern */
  385. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  386. if (ret)
  387. break;
  388. }
  389. ret = dp_ctrl_update_sink_vx_px(ctrl);
  390. if (ret)
  391. break;
  392. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  393. ret = dp_ctrl_read_link_status(ctrl, link_status);
  394. if (ret)
  395. break;
  396. /* check if CR bits still remain set */
  397. if (!drm_dp_clock_recovery_ok(link_status,
  398. ctrl->link->link_params.lane_count)) {
  399. ret = -EINVAL;
  400. break;
  401. }
  402. if (!drm_dp_channel_eq_ok(link_status,
  403. ctrl->link->link_params.lane_count))
  404. ret = -EINVAL;
  405. else
  406. break;
  407. if (tries >= maximum_retries) {
  408. ret = dp_ctrl_lane_count_down_shift(ctrl);
  409. break;
  410. }
  411. tries++;
  412. ctrl->link->adjust_levels(ctrl->link, link_status);
  413. }
  414. skip_training:
  415. ctrl->aux->state &= ~DP_STATE_TRAIN_2_STARTED;
  416. if (ret)
  417. ctrl->aux->state |= DP_STATE_TRAIN_2_FAILED;
  418. else
  419. ctrl->aux->state |= DP_STATE_TRAIN_2_SUCCEEDED;
  420. return ret;
  421. }
  422. static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl)
  423. {
  424. int ret = 0;
  425. u8 const encoding = 0x1, downspread = 0x00;
  426. struct drm_dp_link link_info = {0};
  427. ctrl->link->phy_params.p_level = 0;
  428. ctrl->link->phy_params.v_level = 0;
  429. link_info.num_lanes = ctrl->link->link_params.lane_count;
  430. link_info.rate = drm_dp_bw_code_to_link_rate(
  431. ctrl->link->link_params.bw_code);
  432. link_info.capabilities = ctrl->panel->link_info.capabilities;
  433. ret = drm_dp_link_configure(ctrl->aux->drm_aux, &link_info);
  434. if (ret)
  435. goto end;
  436. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  437. DP_DOWNSPREAD_CTRL, downspread);
  438. if (ret <= 0) {
  439. ret = -EINVAL;
  440. goto end;
  441. }
  442. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  443. DP_MAIN_LINK_CHANNEL_CODING_SET, encoding);
  444. if (ret <= 0) {
  445. ret = -EINVAL;
  446. goto end;
  447. }
  448. ret = dp_ctrl_link_training_1(ctrl);
  449. if (ret) {
  450. DP_ERR("link training #1 failed\n");
  451. goto end;
  452. }
  453. /* print success info as this is a result of user initiated action */
  454. DP_INFO("link training #1 successful\n");
  455. ret = dp_ctrl_link_training_2(ctrl);
  456. if (ret) {
  457. DP_ERR("link training #2 failed\n");
  458. goto end;
  459. }
  460. /* print success info as this is a result of user initiated action */
  461. DP_INFO("link training #2 successful\n");
  462. end:
  463. dp_ctrl_state_ctrl(ctrl, 0);
  464. /* Make sure to clear the current pattern before starting a new one */
  465. wmb();
  466. dp_ctrl_clear_training_pattern(ctrl);
  467. return ret;
  468. }
  469. static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl)
  470. {
  471. int ret = 0;
  472. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
  473. goto end;
  474. /*
  475. * As part of previous calls, DP controller state might have
  476. * transitioned to PUSH_IDLE. In order to start transmitting a link
  477. * training pattern, we have to first to a DP software reset.
  478. */
  479. ctrl->catalog->reset(ctrl->catalog);
  480. if (ctrl->fec_mode)
  481. drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_FEC_CONFIGURATION,
  482. 0x01);
  483. ret = dp_ctrl_link_train(ctrl);
  484. end:
  485. return ret;
  486. }
  487. static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
  488. char *name, enum dp_pm_type clk_type, u32 rate)
  489. {
  490. u32 num = ctrl->parser->mp[clk_type].num_clk;
  491. struct dss_clk *cfg = ctrl->parser->mp[clk_type].clk_config;
  492. while (num && strcmp(cfg->clk_name, name)) {
  493. num--;
  494. cfg++;
  495. }
  496. DP_DEBUG("setting rate=%d on clk=%s\n", rate, name);
  497. if (num)
  498. cfg->rate = rate;
  499. else
  500. DP_ERR("%s clock could not be set with rate %d\n", name, rate);
  501. }
  502. static int dp_ctrl_enable_link_clock(struct dp_ctrl_private *ctrl)
  503. {
  504. int ret = 0;
  505. u32 rate = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
  506. enum dp_pm_type type = DP_LINK_PM;
  507. DP_DEBUG("rate=%d\n", rate);
  508. dp_ctrl_set_clock_rate(ctrl, "link_clk", type, rate);
  509. ret = ctrl->power->clk_enable(ctrl->power, type, true);
  510. if (ret) {
  511. DP_ERR("Unabled to start link clocks\n");
  512. ret = -EINVAL;
  513. }
  514. return ret;
  515. }
  516. static void dp_ctrl_disable_link_clock(struct dp_ctrl_private *ctrl)
  517. {
  518. ctrl->power->clk_enable(ctrl->power, DP_LINK_PM, false);
  519. }
  520. static void dp_ctrl_select_training_pattern(struct dp_ctrl_private *ctrl,
  521. bool downgrade)
  522. {
  523. u32 pattern;
  524. if (drm_dp_tps4_supported(ctrl->panel->dpcd))
  525. pattern = DP_TRAINING_PATTERN_4;
  526. else if (drm_dp_tps3_supported(ctrl->panel->dpcd))
  527. pattern = DP_TRAINING_PATTERN_3;
  528. else
  529. pattern = DP_TRAINING_PATTERN_2;
  530. if (!downgrade)
  531. goto end;
  532. switch (pattern) {
  533. case DP_TRAINING_PATTERN_4:
  534. pattern = DP_TRAINING_PATTERN_3;
  535. break;
  536. case DP_TRAINING_PATTERN_3:
  537. pattern = DP_TRAINING_PATTERN_2;
  538. break;
  539. default:
  540. break;
  541. }
  542. end:
  543. ctrl->training_2_pattern = pattern;
  544. }
  545. static int dp_ctrl_link_setup(struct dp_ctrl_private *ctrl, bool shallow)
  546. {
  547. int rc = -EINVAL;
  548. bool downgrade = false;
  549. u32 link_train_max_retries = 100;
  550. struct dp_catalog_ctrl *catalog;
  551. struct dp_link_params *link_params;
  552. catalog = ctrl->catalog;
  553. link_params = &ctrl->link->link_params;
  554. catalog->phy_lane_cfg(catalog, ctrl->orientation,
  555. link_params->lane_count);
  556. while (1) {
  557. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  558. link_params->bw_code, link_params->lane_count);
  559. rc = dp_ctrl_enable_link_clock(ctrl);
  560. if (rc)
  561. break;
  562. ctrl->catalog->late_phy_init(ctrl->catalog,
  563. ctrl->link->link_params.lane_count,
  564. ctrl->orientation);
  565. dp_ctrl_configure_source_link_params(ctrl, true);
  566. if (!(--link_train_max_retries % 10)) {
  567. struct dp_link_params *link = &ctrl->link->link_params;
  568. link->lane_count = ctrl->initial_lane_count;
  569. link->bw_code = ctrl->initial_bw_code;
  570. downgrade = true;
  571. }
  572. dp_ctrl_select_training_pattern(ctrl, downgrade);
  573. rc = dp_ctrl_setup_main_link(ctrl);
  574. if (!rc)
  575. break;
  576. /*
  577. * Shallow means link training failure is not important.
  578. * If it fails, we still keep the link clocks on.
  579. * In this mode, the system expects DP to be up
  580. * even though the cable is removed. Disconnect interrupt
  581. * will eventually trigger and shutdown DP.
  582. */
  583. if (shallow) {
  584. rc = 0;
  585. break;
  586. }
  587. if (!link_train_max_retries || atomic_read(&ctrl->aborted)) {
  588. dp_ctrl_disable_link_clock(ctrl);
  589. break;
  590. }
  591. if (rc != -EAGAIN)
  592. dp_ctrl_link_rate_down_shift(ctrl);
  593. dp_ctrl_configure_source_link_params(ctrl, false);
  594. dp_ctrl_disable_link_clock(ctrl);
  595. /* hw recommended delays before retrying link training */
  596. msleep(20);
  597. }
  598. return rc;
  599. }
  600. static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl,
  601. struct dp_panel *dp_panel)
  602. {
  603. int ret = 0;
  604. u32 pclk;
  605. enum dp_pm_type clk_type;
  606. char clk_name[32] = "";
  607. ret = ctrl->power->set_pixel_clk_parent(ctrl->power,
  608. dp_panel->stream_id);
  609. if (ret)
  610. return ret;
  611. if (dp_panel->stream_id == DP_STREAM_0) {
  612. clk_type = DP_STREAM0_PM;
  613. strlcpy(clk_name, "strm0_pixel_clk", 32);
  614. } else if (dp_panel->stream_id == DP_STREAM_1) {
  615. clk_type = DP_STREAM1_PM;
  616. strlcpy(clk_name, "strm1_pixel_clk", 32);
  617. } else {
  618. DP_ERR("Invalid stream:%d for clk enable\n",
  619. dp_panel->stream_id);
  620. return -EINVAL;
  621. }
  622. pclk = dp_panel->pinfo.widebus_en ?
  623. (dp_panel->pinfo.pixel_clk_khz >> 1) :
  624. (dp_panel->pinfo.pixel_clk_khz);
  625. dp_ctrl_set_clock_rate(ctrl, clk_name, clk_type, pclk);
  626. ret = ctrl->power->clk_enable(ctrl->power, clk_type, true);
  627. if (ret) {
  628. DP_ERR("Unabled to start stream:%d clocks\n",
  629. dp_panel->stream_id);
  630. ret = -EINVAL;
  631. }
  632. return ret;
  633. }
  634. static int dp_ctrl_disable_stream_clocks(struct dp_ctrl_private *ctrl,
  635. struct dp_panel *dp_panel)
  636. {
  637. int ret = 0;
  638. if (dp_panel->stream_id == DP_STREAM_0) {
  639. return ctrl->power->clk_enable(ctrl->power,
  640. DP_STREAM0_PM, false);
  641. } else if (dp_panel->stream_id == DP_STREAM_1) {
  642. return ctrl->power->clk_enable(ctrl->power,
  643. DP_STREAM1_PM, false);
  644. } else {
  645. DP_ERR("Invalid stream:%d for clk disable\n",
  646. dp_panel->stream_id);
  647. ret = -EINVAL;
  648. }
  649. return ret;
  650. }
  651. static int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
  652. {
  653. struct dp_ctrl_private *ctrl;
  654. struct dp_catalog_ctrl *catalog;
  655. if (!dp_ctrl) {
  656. DP_ERR("Invalid input data\n");
  657. return -EINVAL;
  658. }
  659. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  660. ctrl->orientation = flip;
  661. catalog = ctrl->catalog;
  662. if (reset) {
  663. catalog->usb_reset(ctrl->catalog, flip);
  664. catalog->phy_reset(ctrl->catalog);
  665. }
  666. catalog->enable_irq(ctrl->catalog, true);
  667. atomic_set(&ctrl->aborted, 0);
  668. return 0;
  669. }
  670. /**
  671. * dp_ctrl_host_deinit() - Uninitialize DP controller
  672. * @ctrl: Display Port Driver data
  673. *
  674. * Perform required steps to uninitialize DP controller
  675. * and its resources.
  676. */
  677. static void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
  678. {
  679. struct dp_ctrl_private *ctrl;
  680. if (!dp_ctrl) {
  681. DP_ERR("Invalid input data\n");
  682. return;
  683. }
  684. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  685. ctrl->catalog->enable_irq(ctrl->catalog, false);
  686. DP_DEBUG("Host deinitialized successfully\n");
  687. }
  688. static void dp_ctrl_send_video(struct dp_ctrl_private *ctrl)
  689. {
  690. reinit_completion(&ctrl->video_comp);
  691. ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO);
  692. }
  693. static int dp_ctrl_link_maintenance(struct dp_ctrl *dp_ctrl)
  694. {
  695. int ret = 0;
  696. struct dp_ctrl_private *ctrl;
  697. if (!dp_ctrl) {
  698. DP_ERR("Invalid input data\n");
  699. return -EINVAL;
  700. }
  701. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  702. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_COMPLETED;
  703. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_FAILED;
  704. if (!ctrl->power_on) {
  705. DP_ERR("ctrl off\n");
  706. ret = -EINVAL;
  707. goto end;
  708. }
  709. if (atomic_read(&ctrl->aborted))
  710. goto end;
  711. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_STARTED;
  712. ret = dp_ctrl_setup_main_link(ctrl);
  713. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_STARTED;
  714. if (ret) {
  715. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_FAILED;
  716. goto end;
  717. }
  718. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_COMPLETED;
  719. if (ctrl->stream_count) {
  720. dp_ctrl_send_video(ctrl);
  721. dp_ctrl_wait4video_ready(ctrl);
  722. }
  723. end:
  724. return ret;
  725. }
  726. static void dp_ctrl_process_phy_test_request(struct dp_ctrl *dp_ctrl)
  727. {
  728. int ret = 0;
  729. struct dp_ctrl_private *ctrl;
  730. if (!dp_ctrl) {
  731. DP_ERR("Invalid input data\n");
  732. return;
  733. }
  734. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  735. if (!ctrl->link->phy_params.phy_test_pattern_sel) {
  736. DP_DEBUG("no test pattern selected by sink\n");
  737. return;
  738. }
  739. DP_DEBUG("start\n");
  740. /*
  741. * The global reset will need DP link ralated clocks to be
  742. * running. Add the global reset just before disabling the
  743. * link clocks and core clocks.
  744. */
  745. ctrl->catalog->reset(ctrl->catalog);
  746. ctrl->dp_ctrl.stream_pre_off(&ctrl->dp_ctrl, ctrl->panel);
  747. ctrl->dp_ctrl.stream_off(&ctrl->dp_ctrl, ctrl->panel);
  748. ctrl->dp_ctrl.off(&ctrl->dp_ctrl);
  749. ctrl->aux->init(ctrl->aux, ctrl->parser->aux_cfg);
  750. ret = ctrl->dp_ctrl.on(&ctrl->dp_ctrl, ctrl->mst_mode,
  751. ctrl->fec_mode, ctrl->dsc_mode, false);
  752. if (ret)
  753. DP_ERR("failed to enable DP controller\n");
  754. ctrl->dp_ctrl.stream_on(&ctrl->dp_ctrl, ctrl->panel);
  755. DP_DEBUG("end\n");
  756. }
  757. static void dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
  758. {
  759. bool success = false;
  760. u32 pattern_sent = 0x0;
  761. u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
  762. dp_ctrl_update_hw_vx_px(ctrl);
  763. ctrl->catalog->send_phy_pattern(ctrl->catalog, pattern_requested);
  764. dp_ctrl_update_sink_vx_px(ctrl);
  765. ctrl->link->send_test_response(ctrl->link);
  766. pattern_sent = ctrl->catalog->read_phy_pattern(ctrl->catalog);
  767. DP_DEBUG("pattern_request: %s. pattern_sent: 0x%x\n",
  768. dp_link_get_phy_test_pattern(pattern_requested),
  769. pattern_sent);
  770. switch (pattern_sent) {
  771. case MR_LINK_TRAINING1:
  772. if (pattern_requested ==
  773. DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING)
  774. success = true;
  775. break;
  776. case MR_LINK_SYMBOL_ERM:
  777. if ((pattern_requested ==
  778. DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT)
  779. || (pattern_requested ==
  780. DP_TEST_PHY_PATTERN_CP2520_PATTERN_1))
  781. success = true;
  782. break;
  783. case MR_LINK_PRBS7:
  784. if (pattern_requested == DP_TEST_PHY_PATTERN_PRBS7)
  785. success = true;
  786. break;
  787. case MR_LINK_CUSTOM80:
  788. if (pattern_requested ==
  789. DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN)
  790. success = true;
  791. break;
  792. case MR_LINK_TRAINING4:
  793. if (pattern_requested ==
  794. DP_TEST_PHY_PATTERN_CP2520_PATTERN_3)
  795. success = true;
  796. break;
  797. default:
  798. success = false;
  799. break;
  800. }
  801. DP_DEBUG("%s: %s\n", success ? "success" : "failed",
  802. dp_link_get_phy_test_pattern(pattern_requested));
  803. }
  804. static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl,
  805. struct dp_panel *panel, u32 *p_x_int, u32 *p_y_frac_enum)
  806. {
  807. u64 min_slot_cnt, max_slot_cnt;
  808. u64 raw_target_sc, target_sc_fixp;
  809. u64 ts_denom, ts_enum, ts_int;
  810. u64 pclk = panel->pinfo.pixel_clk_khz;
  811. u64 lclk = panel->link_info.rate;
  812. u64 lanes = panel->link_info.num_lanes;
  813. u64 bpp = panel->pinfo.bpp;
  814. u64 pbn = panel->pbn;
  815. u64 numerator, denominator, temp, temp1, temp2;
  816. u32 x_int = 0, y_frac_enum = 0;
  817. u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp;
  818. if (panel->pinfo.comp_info.comp_ratio > 1)
  819. bpp = DSC_BPP(panel->pinfo.comp_info.dsc_info.config);
  820. /* min_slot_cnt */
  821. numerator = pclk * bpp * 64 * 1000;
  822. denominator = lclk * lanes * 8 * 1000;
  823. min_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  824. /* max_slot_cnt */
  825. numerator = pbn * 54 * 1000;
  826. denominator = lclk * lanes;
  827. max_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  828. /* raw_target_sc */
  829. numerator = max_slot_cnt + min_slot_cnt;
  830. denominator = drm_fixp_from_fraction(2, 1);
  831. raw_target_sc = drm_fixp_div(numerator, denominator);
  832. DP_DEBUG("raw_target_sc before overhead:0x%llx\n", raw_target_sc);
  833. DP_DEBUG("dsc_overhead_fp:0x%llx\n", panel->pinfo.dsc_overhead_fp);
  834. /* apply fec and dsc overhead factor */
  835. if (panel->pinfo.dsc_overhead_fp)
  836. raw_target_sc = drm_fixp_mul(raw_target_sc,
  837. panel->pinfo.dsc_overhead_fp);
  838. if (panel->fec_overhead_fp)
  839. raw_target_sc = drm_fixp_mul(raw_target_sc,
  840. panel->fec_overhead_fp);
  841. DP_DEBUG("raw_target_sc after overhead:0x%llx\n", raw_target_sc);
  842. /* target_sc */
  843. temp = drm_fixp_from_fraction(256 * lanes, 1);
  844. numerator = drm_fixp_mul(raw_target_sc, temp);
  845. denominator = drm_fixp_from_fraction(256 * lanes, 1);
  846. target_sc_fixp = drm_fixp_div(numerator, denominator);
  847. ts_enum = 256 * lanes;
  848. ts_denom = drm_fixp_from_fraction(256 * lanes, 1);
  849. ts_int = drm_fixp2int(target_sc_fixp);
  850. temp = drm_fixp2int_ceil(raw_target_sc);
  851. if (temp != ts_int) {
  852. temp = drm_fixp_from_fraction(ts_int, 1);
  853. temp1 = raw_target_sc - temp;
  854. temp2 = drm_fixp_mul(temp1, ts_denom);
  855. ts_enum = drm_fixp2int(temp2);
  856. }
  857. /* target_strm_sym */
  858. ts_int_fixp = drm_fixp_from_fraction(ts_int, 1);
  859. ts_frac_fixp = drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom));
  860. temp = ts_int_fixp + ts_frac_fixp;
  861. temp1 = drm_fixp_from_fraction(lanes, 1);
  862. target_strm_sym = drm_fixp_mul(temp, temp1);
  863. /* x_int */
  864. x_int = drm_fixp2int(target_strm_sym);
  865. /* y_enum_frac */
  866. temp = drm_fixp_from_fraction(x_int, 1);
  867. temp1 = target_strm_sym - temp;
  868. temp2 = drm_fixp_from_fraction(256, 1);
  869. y_frac_enum_fixp = drm_fixp_mul(temp1, temp2);
  870. temp1 = drm_fixp2int(y_frac_enum_fixp);
  871. temp2 = drm_fixp2int_ceil(y_frac_enum_fixp);
  872. y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1);
  873. panel->mst_target_sc = raw_target_sc;
  874. *p_x_int = x_int;
  875. *p_y_frac_enum = y_frac_enum;
  876. DP_DEBUG("x_int: %d, y_frac_enum: %d\n", x_int, y_frac_enum);
  877. }
  878. static int dp_ctrl_mst_send_act(struct dp_ctrl_private *ctrl)
  879. {
  880. bool act_complete;
  881. if (!ctrl->mst_mode)
  882. return 0;
  883. ctrl->catalog->trigger_act(ctrl->catalog);
  884. msleep(20); /* needs 1 frame time */
  885. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  886. if (!act_complete)
  887. DP_ERR("mst act trigger complete failed\n");
  888. else
  889. DP_MST_DEBUG("mst ACT trigger complete SUCCESS\n");
  890. return 0;
  891. }
  892. static void dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl,
  893. struct dp_panel *panel)
  894. {
  895. u32 x_int, y_frac_enum, lanes, bw_code;
  896. int i;
  897. if (!ctrl->mst_mode)
  898. return;
  899. DP_MST_DEBUG("mst stream channel allocation\n");
  900. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  901. ctrl->catalog->channel_alloc(ctrl->catalog,
  902. i,
  903. ctrl->mst_ch_info.slot_info[i].start_slot,
  904. ctrl->mst_ch_info.slot_info[i].tot_slots);
  905. }
  906. lanes = ctrl->link->link_params.lane_count;
  907. bw_code = ctrl->link->link_params.bw_code;
  908. dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum);
  909. ctrl->catalog->update_rg(ctrl->catalog, panel->stream_id,
  910. x_int, y_frac_enum);
  911. DP_MST_DEBUG("mst stream:%d, start_slot:%d, tot_slots:%d\n",
  912. panel->stream_id,
  913. panel->channel_start_slot, panel->channel_total_slots);
  914. DP_MST_DEBUG("mst lane_cnt:%d, bw:%d, x_int:%d, y_frac:%d\n",
  915. lanes, bw_code, x_int, y_frac_enum);
  916. }
  917. static void dp_ctrl_fec_dsc_setup(struct dp_ctrl_private *ctrl)
  918. {
  919. u8 fec_sts = 0;
  920. int rlen;
  921. u32 dsc_enable;
  922. if (!ctrl->fec_mode)
  923. return;
  924. ctrl->catalog->fec_config(ctrl->catalog, ctrl->fec_mode);
  925. /* wait for controller to start fec sequence */
  926. usleep_range(900, 1000);
  927. drm_dp_dpcd_readb(ctrl->aux->drm_aux, DP_FEC_STATUS, &fec_sts);
  928. DP_DEBUG("sink fec status:%d\n", fec_sts);
  929. dsc_enable = ctrl->dsc_mode ? 1 : 0;
  930. rlen = drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_DSC_ENABLE,
  931. dsc_enable);
  932. if (rlen < 1)
  933. DP_WARN("failed to enable sink dsc\n");
  934. }
  935. static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  936. {
  937. int rc = 0;
  938. bool link_ready = false;
  939. struct dp_ctrl_private *ctrl;
  940. if (!dp_ctrl || !panel)
  941. return -EINVAL;
  942. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  943. if (!ctrl->power_on) {
  944. DP_DEBUG("controller powered off\n");
  945. return -EPERM;
  946. }
  947. rc = dp_ctrl_enable_stream_clocks(ctrl, panel);
  948. if (rc) {
  949. DP_ERR("failure on stream clock enable\n");
  950. return rc;
  951. }
  952. rc = panel->hw_cfg(panel, true);
  953. if (rc)
  954. return rc;
  955. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  956. dp_ctrl_send_phy_test_pattern(ctrl);
  957. return 0;
  958. }
  959. dp_ctrl_mst_stream_setup(ctrl, panel);
  960. dp_ctrl_send_video(ctrl);
  961. dp_ctrl_mst_send_act(ctrl);
  962. dp_ctrl_wait4video_ready(ctrl);
  963. ctrl->stream_count++;
  964. link_ready = ctrl->catalog->mainlink_ready(ctrl->catalog);
  965. DP_DEBUG("mainlink %s\n", link_ready ? "READY" : "NOT READY");
  966. /* wait for link training completion before fec config as per spec */
  967. dp_ctrl_fec_dsc_setup(ctrl);
  968. return rc;
  969. }
  970. static void dp_ctrl_mst_stream_pre_off(struct dp_ctrl *dp_ctrl,
  971. struct dp_panel *panel)
  972. {
  973. struct dp_ctrl_private *ctrl;
  974. bool act_complete;
  975. int i;
  976. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  977. if (!ctrl->mst_mode)
  978. return;
  979. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  980. ctrl->catalog->channel_alloc(ctrl->catalog,
  981. i,
  982. ctrl->mst_ch_info.slot_info[i].start_slot,
  983. ctrl->mst_ch_info.slot_info[i].tot_slots);
  984. }
  985. ctrl->catalog->trigger_act(ctrl->catalog);
  986. msleep(20); /* needs 1 frame time */
  987. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  988. if (!act_complete)
  989. DP_ERR("mst stream_off act trigger complete failed\n");
  990. else
  991. DP_MST_DEBUG("mst stream_off ACT trigger complete SUCCESS\n");
  992. }
  993. static void dp_ctrl_stream_pre_off(struct dp_ctrl *dp_ctrl,
  994. struct dp_panel *panel)
  995. {
  996. struct dp_ctrl_private *ctrl;
  997. if (!dp_ctrl || !panel) {
  998. DP_ERR("invalid input\n");
  999. return;
  1000. }
  1001. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1002. dp_ctrl_push_idle(ctrl, panel->stream_id);
  1003. dp_ctrl_mst_stream_pre_off(dp_ctrl, panel);
  1004. }
  1005. static void dp_ctrl_stream_off(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  1006. {
  1007. struct dp_ctrl_private *ctrl;
  1008. if (!dp_ctrl || !panel)
  1009. return;
  1010. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1011. if (!ctrl->power_on)
  1012. return;
  1013. panel->hw_cfg(panel, false);
  1014. dp_ctrl_disable_stream_clocks(ctrl, panel);
  1015. ctrl->stream_count--;
  1016. }
  1017. static int dp_ctrl_on(struct dp_ctrl *dp_ctrl, bool mst_mode,
  1018. bool fec_mode, bool dsc_mode, bool shallow)
  1019. {
  1020. int rc = 0;
  1021. struct dp_ctrl_private *ctrl;
  1022. u32 rate = 0;
  1023. if (!dp_ctrl) {
  1024. rc = -EINVAL;
  1025. goto end;
  1026. }
  1027. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1028. if (ctrl->power_on)
  1029. goto end;
  1030. if (atomic_read(&ctrl->aborted)) {
  1031. rc = -EPERM;
  1032. goto end;
  1033. }
  1034. ctrl->mst_mode = mst_mode;
  1035. if (fec_mode) {
  1036. ctrl->fec_mode = fec_mode;
  1037. ctrl->dsc_mode = dsc_mode;
  1038. }
  1039. rate = ctrl->panel->link_info.rate;
  1040. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  1041. DP_DEBUG("using phy test link parameters\n");
  1042. } else {
  1043. ctrl->link->link_params.bw_code =
  1044. drm_dp_link_rate_to_bw_code(rate);
  1045. ctrl->link->link_params.lane_count =
  1046. ctrl->panel->link_info.num_lanes;
  1047. }
  1048. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  1049. ctrl->link->link_params.bw_code,
  1050. ctrl->link->link_params.lane_count);
  1051. /* backup initial lane count and bw code */
  1052. ctrl->initial_lane_count = ctrl->link->link_params.lane_count;
  1053. ctrl->initial_bw_code = ctrl->link->link_params.bw_code;
  1054. rc = dp_ctrl_link_setup(ctrl, shallow);
  1055. if (!rc)
  1056. ctrl->power_on = true;
  1057. end:
  1058. return rc;
  1059. }
  1060. static void dp_ctrl_off(struct dp_ctrl *dp_ctrl)
  1061. {
  1062. struct dp_ctrl_private *ctrl;
  1063. if (!dp_ctrl)
  1064. return;
  1065. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1066. if (!ctrl->power_on)
  1067. return;
  1068. ctrl->catalog->fec_config(ctrl->catalog, false);
  1069. dp_ctrl_configure_source_link_params(ctrl, false);
  1070. ctrl->catalog->reset(ctrl->catalog);
  1071. /* Make sure DP is disabled before clk disable */
  1072. wmb();
  1073. dp_ctrl_disable_link_clock(ctrl);
  1074. ctrl->mst_mode = false;
  1075. ctrl->fec_mode = false;
  1076. ctrl->dsc_mode = false;
  1077. ctrl->power_on = false;
  1078. memset(&ctrl->mst_ch_info, 0, sizeof(ctrl->mst_ch_info));
  1079. DP_DEBUG("DP off done\n");
  1080. }
  1081. static void dp_ctrl_set_mst_channel_info(struct dp_ctrl *dp_ctrl,
  1082. enum dp_stream_id strm,
  1083. u32 start_slot, u32 tot_slots)
  1084. {
  1085. struct dp_ctrl_private *ctrl;
  1086. if (!dp_ctrl || strm >= DP_STREAM_MAX) {
  1087. DP_ERR("invalid input\n");
  1088. return;
  1089. }
  1090. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1091. ctrl->mst_ch_info.slot_info[strm].start_slot = start_slot;
  1092. ctrl->mst_ch_info.slot_info[strm].tot_slots = tot_slots;
  1093. }
  1094. static void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
  1095. {
  1096. struct dp_ctrl_private *ctrl;
  1097. if (!dp_ctrl)
  1098. return;
  1099. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1100. ctrl->catalog->get_interrupt(ctrl->catalog);
  1101. if (ctrl->catalog->isr & DP_CTRL_INTR_READY_FOR_VIDEO)
  1102. dp_ctrl_video_ready(ctrl);
  1103. if (ctrl->catalog->isr & DP_CTRL_INTR_IDLE_PATTERN_SENT)
  1104. dp_ctrl_idle_patterns_sent(ctrl);
  1105. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP0_VCPF_SENT)
  1106. dp_ctrl_idle_patterns_sent(ctrl);
  1107. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP1_VCPF_SENT)
  1108. dp_ctrl_idle_patterns_sent(ctrl);
  1109. }
  1110. void dp_ctrl_set_sim_mode(struct dp_ctrl *dp_ctrl, bool en)
  1111. {
  1112. struct dp_ctrl_private *ctrl;
  1113. if (!dp_ctrl)
  1114. return;
  1115. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1116. ctrl->sim_mode = en;
  1117. DP_INFO("sim_mode=%d\n", ctrl->sim_mode);
  1118. }
  1119. struct dp_ctrl *dp_ctrl_get(struct dp_ctrl_in *in)
  1120. {
  1121. int rc = 0;
  1122. struct dp_ctrl_private *ctrl;
  1123. struct dp_ctrl *dp_ctrl;
  1124. if (!in->dev || !in->panel || !in->aux ||
  1125. !in->link || !in->catalog) {
  1126. DP_ERR("invalid input\n");
  1127. rc = -EINVAL;
  1128. goto error;
  1129. }
  1130. ctrl = devm_kzalloc(in->dev, sizeof(*ctrl), GFP_KERNEL);
  1131. if (!ctrl) {
  1132. rc = -ENOMEM;
  1133. goto error;
  1134. }
  1135. init_completion(&ctrl->idle_comp);
  1136. init_completion(&ctrl->video_comp);
  1137. /* in parameters */
  1138. ctrl->parser = in->parser;
  1139. ctrl->panel = in->panel;
  1140. ctrl->power = in->power;
  1141. ctrl->aux = in->aux;
  1142. ctrl->link = in->link;
  1143. ctrl->catalog = in->catalog;
  1144. ctrl->dev = in->dev;
  1145. ctrl->mst_mode = false;
  1146. ctrl->fec_mode = false;
  1147. dp_ctrl = &ctrl->dp_ctrl;
  1148. /* out parameters */
  1149. dp_ctrl->init = dp_ctrl_host_init;
  1150. dp_ctrl->deinit = dp_ctrl_host_deinit;
  1151. dp_ctrl->on = dp_ctrl_on;
  1152. dp_ctrl->off = dp_ctrl_off;
  1153. dp_ctrl->abort = dp_ctrl_abort;
  1154. dp_ctrl->isr = dp_ctrl_isr;
  1155. dp_ctrl->link_maintenance = dp_ctrl_link_maintenance;
  1156. dp_ctrl->process_phy_test_request = dp_ctrl_process_phy_test_request;
  1157. dp_ctrl->stream_on = dp_ctrl_stream_on;
  1158. dp_ctrl->stream_off = dp_ctrl_stream_off;
  1159. dp_ctrl->stream_pre_off = dp_ctrl_stream_pre_off;
  1160. dp_ctrl->set_mst_channel_info = dp_ctrl_set_mst_channel_info;
  1161. dp_ctrl->set_sim_mode = dp_ctrl_set_sim_mode;
  1162. return dp_ctrl;
  1163. error:
  1164. return ERR_PTR(rc);
  1165. }
  1166. void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
  1167. {
  1168. struct dp_ctrl_private *ctrl;
  1169. if (!dp_ctrl)
  1170. return;
  1171. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1172. devm_kfree(ctrl->dev, ctrl);
  1173. }