cam_mem_mgr.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  13. #include <linux/mem-buf.h>
  14. #include <soc/qcom/secure_buffer.h>
  15. #endif
  16. #include "cam_compat.h"
  17. #include "cam_req_mgr_util.h"
  18. #include "cam_mem_mgr.h"
  19. #include "cam_smmu_api.h"
  20. #include "cam_debug_util.h"
  21. #include "cam_trace.h"
  22. #include "cam_common_util.h"
  23. #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
  24. static struct cam_mem_table tbl;
  25. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  26. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  27. static void cam_mem_mgr_put_dma_heaps(void);
  28. static int cam_mem_mgr_get_dma_heaps(void);
  29. #endif
  30. static void cam_mem_mgr_print_tbl(void)
  31. {
  32. int i;
  33. uint64_t ms, tmp, hrs, min, sec;
  34. struct timespec64 *ts = NULL;
  35. struct timespec64 current_ts;
  36. ktime_get_real_ts64(&(current_ts));
  37. tmp = current_ts.tv_sec;
  38. ms = (current_ts.tv_nsec) / 1000000;
  39. sec = do_div(tmp, 60);
  40. min = do_div(tmp, 60);
  41. hrs = do_div(tmp, 24);
  42. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  43. hrs, min, sec, ms);
  44. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  45. if (tbl.bufq[i].active) {
  46. ts = &tbl.bufq[i].timestamp;
  47. tmp = ts->tv_sec;
  48. ms = (ts->tv_nsec) / 1000000;
  49. sec = do_div(tmp, 60);
  50. min = do_div(tmp, 60);
  51. hrs = do_div(tmp, 24);
  52. CAM_INFO(CAM_MEM,
  53. "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu",
  54. hrs, min, sec, ms, i, tbl.bufq[i].fd, tbl.bufq[i].i_ino,
  55. tbl.bufq[i].len);
  56. }
  57. }
  58. }
  59. static int cam_mem_util_get_dma_dir(uint32_t flags)
  60. {
  61. int rc = -EINVAL;
  62. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  63. rc = DMA_TO_DEVICE;
  64. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  65. rc = DMA_FROM_DEVICE;
  66. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  67. rc = DMA_BIDIRECTIONAL;
  68. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  69. rc = DMA_BIDIRECTIONAL;
  70. return rc;
  71. }
  72. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  73. uintptr_t *vaddr,
  74. size_t *len)
  75. {
  76. int rc = 0;
  77. void *addr;
  78. /*
  79. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  80. * need to be called in pair to avoid stability issue.
  81. */
  82. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  83. if (rc) {
  84. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  85. return rc;
  86. }
  87. addr = dma_buf_vmap(dmabuf);
  88. if (!addr) {
  89. CAM_ERR(CAM_MEM, "kernel map fail");
  90. *vaddr = 0;
  91. *len = 0;
  92. rc = -ENOSPC;
  93. goto fail;
  94. }
  95. *vaddr = (uint64_t)addr;
  96. *len = dmabuf->size;
  97. return 0;
  98. fail:
  99. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  100. return rc;
  101. }
  102. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  103. uint64_t vaddr)
  104. {
  105. int rc = 0;
  106. if (!dmabuf || !vaddr) {
  107. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  108. return -EINVAL;
  109. }
  110. dma_buf_vunmap(dmabuf, (void *)vaddr);
  111. /*
  112. * dma_buf_begin_cpu_access() and
  113. * dma_buf_end_cpu_access() need to be called in pair
  114. * to avoid stability issue.
  115. */
  116. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  117. if (rc) {
  118. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  119. dmabuf);
  120. return rc;
  121. }
  122. return rc;
  123. }
  124. static int cam_mem_mgr_create_debug_fs(void)
  125. {
  126. int rc = 0;
  127. struct dentry *dbgfileptr = NULL;
  128. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  129. if (!dbgfileptr) {
  130. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  131. rc = -ENOENT;
  132. goto end;
  133. }
  134. /* Store parent inode for cleanup in caller */
  135. tbl.dentry = dbgfileptr;
  136. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  137. tbl.dentry, &tbl.alloc_profile_enable);
  138. if (IS_ERR(dbgfileptr)) {
  139. if (PTR_ERR(dbgfileptr) == -ENODEV)
  140. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  141. else
  142. rc = PTR_ERR(dbgfileptr);
  143. }
  144. end:
  145. return rc;
  146. }
  147. int cam_mem_mgr_init(void)
  148. {
  149. int i;
  150. int bitmap_size;
  151. int rc = 0;
  152. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  153. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  154. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  155. return -EINVAL;
  156. }
  157. tbl.need_shared_buffer_padding = cam_smmu_need_shared_buffer_padding();
  158. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  159. rc = cam_mem_mgr_get_dma_heaps();
  160. if (rc) {
  161. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  162. return rc;
  163. }
  164. #endif
  165. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  166. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  167. if (!tbl.bitmap) {
  168. rc = -ENOMEM;
  169. goto put_heaps;
  170. }
  171. tbl.bits = bitmap_size * BITS_PER_BYTE;
  172. bitmap_zero(tbl.bitmap, tbl.bits);
  173. /* We need to reserve slot 0 because 0 is invalid */
  174. set_bit(0, tbl.bitmap);
  175. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  176. tbl.bufq[i].fd = -1;
  177. tbl.bufq[i].buf_handle = -1;
  178. }
  179. mutex_init(&tbl.m_lock);
  180. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  181. cam_mem_mgr_create_debug_fs();
  182. return 0;
  183. put_heaps:
  184. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  185. cam_mem_mgr_put_dma_heaps();
  186. #endif
  187. return rc;
  188. }
  189. static int32_t cam_mem_get_slot(void)
  190. {
  191. int32_t idx;
  192. mutex_lock(&tbl.m_lock);
  193. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  194. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  195. mutex_unlock(&tbl.m_lock);
  196. return -ENOMEM;
  197. }
  198. set_bit(idx, tbl.bitmap);
  199. tbl.bufq[idx].active = true;
  200. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  201. mutex_init(&tbl.bufq[idx].q_lock);
  202. mutex_unlock(&tbl.m_lock);
  203. return idx;
  204. }
  205. static void cam_mem_put_slot(int32_t idx)
  206. {
  207. mutex_lock(&tbl.m_lock);
  208. mutex_lock(&tbl.bufq[idx].q_lock);
  209. tbl.bufq[idx].active = false;
  210. tbl.bufq[idx].is_internal = false;
  211. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  212. mutex_unlock(&tbl.bufq[idx].q_lock);
  213. mutex_destroy(&tbl.bufq[idx].q_lock);
  214. clear_bit(idx, tbl.bitmap);
  215. mutex_unlock(&tbl.m_lock);
  216. }
  217. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  218. dma_addr_t *iova_ptr, size_t *len_ptr, uint32_t *flags)
  219. {
  220. int rc = 0, idx;
  221. *len_ptr = 0;
  222. if (!atomic_read(&cam_mem_mgr_state)) {
  223. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  224. return -EINVAL;
  225. }
  226. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  227. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  228. return -ENOENT;
  229. if (!tbl.bufq[idx].active) {
  230. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  231. idx);
  232. return -EAGAIN;
  233. }
  234. mutex_lock(&tbl.bufq[idx].q_lock);
  235. if (buf_handle != tbl.bufq[idx].buf_handle) {
  236. rc = -EINVAL;
  237. goto handle_mismatch;
  238. }
  239. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  240. rc = cam_smmu_get_stage2_iova(mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].dma_buf,
  241. iova_ptr, len_ptr);
  242. else
  243. rc = cam_smmu_get_iova(mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].dma_buf,
  244. iova_ptr, len_ptr);
  245. if (rc) {
  246. CAM_ERR(CAM_MEM,
  247. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d i_ino:%lu",
  248. buf_handle, mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino);
  249. goto handle_mismatch;
  250. }
  251. if (flags)
  252. *flags = tbl.bufq[idx].flags;
  253. CAM_DBG(CAM_MEM,
  254. "handle:0x%x fd:%d i_ino:%lu iova_ptr:0x%llx len_ptr:%llu",
  255. mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino, iova_ptr, *len_ptr);
  256. handle_mismatch:
  257. mutex_unlock(&tbl.bufq[idx].q_lock);
  258. return rc;
  259. }
  260. EXPORT_SYMBOL(cam_mem_get_io_buf);
  261. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  262. {
  263. int idx;
  264. if (!atomic_read(&cam_mem_mgr_state)) {
  265. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  266. return -EINVAL;
  267. }
  268. if (!buf_handle || !vaddr_ptr || !len)
  269. return -EINVAL;
  270. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  271. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  272. return -EINVAL;
  273. if (!tbl.bufq[idx].active) {
  274. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  275. idx);
  276. return -EPERM;
  277. }
  278. if (buf_handle != tbl.bufq[idx].buf_handle)
  279. return -EINVAL;
  280. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  281. return -EINVAL;
  282. if (tbl.bufq[idx].kmdvaddr) {
  283. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  284. *len = tbl.bufq[idx].len;
  285. } else {
  286. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  287. buf_handle);
  288. return -EINVAL;
  289. }
  290. return 0;
  291. }
  292. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  293. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  294. {
  295. int rc = 0, idx;
  296. uint32_t cache_dir;
  297. unsigned long dmabuf_flag = 0;
  298. if (!atomic_read(&cam_mem_mgr_state)) {
  299. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  300. return -EINVAL;
  301. }
  302. if (!cmd)
  303. return -EINVAL;
  304. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  305. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  306. return -EINVAL;
  307. mutex_lock(&tbl.bufq[idx].q_lock);
  308. if (!tbl.bufq[idx].active) {
  309. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  310. idx);
  311. rc = -EINVAL;
  312. goto end;
  313. }
  314. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  315. rc = -EINVAL;
  316. goto end;
  317. }
  318. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  319. if (rc) {
  320. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  321. goto end;
  322. }
  323. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  324. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  325. cache_dir = DMA_BIDIRECTIONAL;
  326. #else
  327. if (dmabuf_flag & ION_FLAG_CACHED) {
  328. switch (cmd->mem_cache_ops) {
  329. case CAM_MEM_CLEAN_CACHE:
  330. cache_dir = DMA_TO_DEVICE;
  331. break;
  332. case CAM_MEM_INV_CACHE:
  333. cache_dir = DMA_FROM_DEVICE;
  334. break;
  335. case CAM_MEM_CLEAN_INV_CACHE:
  336. cache_dir = DMA_BIDIRECTIONAL;
  337. break;
  338. default:
  339. CAM_ERR(CAM_MEM,
  340. "invalid cache ops :%d", cmd->mem_cache_ops);
  341. rc = -EINVAL;
  342. goto end;
  343. }
  344. } else {
  345. CAM_DBG(CAM_MEM, "BUF is not cached");
  346. goto end;
  347. }
  348. #endif
  349. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  350. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  351. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  352. if (rc) {
  353. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  354. goto end;
  355. }
  356. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  357. cache_dir);
  358. if (rc) {
  359. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  360. goto end;
  361. }
  362. end:
  363. mutex_unlock(&tbl.bufq[idx].q_lock);
  364. return rc;
  365. }
  366. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  367. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  368. #define CAM_MAX_VMIDS 4
  369. static void cam_mem_mgr_put_dma_heaps(void)
  370. {
  371. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  372. }
  373. static int cam_mem_mgr_get_dma_heaps(void)
  374. {
  375. int rc = 0;
  376. tbl.system_heap = NULL;
  377. tbl.system_uncached_heap = NULL;
  378. tbl.camera_heap = NULL;
  379. tbl.camera_uncached_heap = NULL;
  380. tbl.secure_display_heap = NULL;
  381. tbl.system_heap = dma_heap_find("qcom,system");
  382. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  383. rc = PTR_ERR(tbl.system_heap);
  384. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  385. tbl.system_heap = NULL;
  386. goto put_heaps;
  387. }
  388. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  389. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  390. if (tbl.force_cache_allocs) {
  391. /* optional, we anyway do not use uncached */
  392. CAM_DBG(CAM_MEM,
  393. "qcom system-uncached heap not found, err=%d",
  394. PTR_ERR(tbl.system_uncached_heap));
  395. tbl.system_uncached_heap = NULL;
  396. } else {
  397. /* fatal, must need uncached heaps */
  398. rc = PTR_ERR(tbl.system_uncached_heap);
  399. CAM_ERR(CAM_MEM,
  400. "qcom system-uncached heap not found, rc=%d",
  401. rc);
  402. tbl.system_uncached_heap = NULL;
  403. goto put_heaps;
  404. }
  405. }
  406. tbl.secure_display_heap = dma_heap_find("qcom,display");
  407. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  408. rc = PTR_ERR(tbl.secure_display_heap);
  409. CAM_ERR(CAM_MEM, "qcom,display heap not found, rc=%d",
  410. rc);
  411. tbl.secure_display_heap = NULL;
  412. goto put_heaps;
  413. }
  414. tbl.camera_heap = dma_heap_find("qcom,camera");
  415. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  416. /* optional heap, not a fatal error */
  417. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  418. PTR_ERR(tbl.camera_heap));
  419. tbl.camera_heap = NULL;
  420. }
  421. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  422. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  423. /* optional heap, not a fatal error */
  424. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  425. PTR_ERR(tbl.camera_uncached_heap));
  426. tbl.camera_uncached_heap = NULL;
  427. }
  428. CAM_INFO(CAM_MEM,
  429. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  430. tbl.system_heap, tbl.system_uncached_heap,
  431. tbl.camera_heap, tbl.camera_uncached_heap,
  432. tbl.secure_display_heap);
  433. return 0;
  434. put_heaps:
  435. cam_mem_mgr_put_dma_heaps();
  436. return rc;
  437. }
  438. static int cam_mem_util_get_dma_buf(size_t len,
  439. unsigned int cam_flags,
  440. struct dma_buf **buf,
  441. unsigned long *i_ino)
  442. {
  443. int rc = 0;
  444. struct dma_heap *heap;
  445. struct dma_heap *try_heap = NULL;
  446. struct timespec64 ts1, ts2;
  447. long microsec = 0;
  448. bool use_cached_heap = false;
  449. struct mem_buf_lend_kernel_arg arg;
  450. int vmids[CAM_MAX_VMIDS];
  451. int perms[CAM_MAX_VMIDS];
  452. int num_vmids = 0;
  453. if (!buf) {
  454. CAM_ERR(CAM_MEM, "Invalid params");
  455. return -EINVAL;
  456. }
  457. if (tbl.alloc_profile_enable)
  458. CAM_GET_TIMESTAMP(ts1);
  459. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  460. (tbl.force_cache_allocs &&
  461. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  462. CAM_DBG(CAM_MEM,
  463. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  464. cam_flags, tbl.force_cache_allocs);
  465. use_cached_heap = true;
  466. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  467. use_cached_heap = true;
  468. CAM_DBG(CAM_MEM,
  469. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  470. cam_flags, tbl.force_cache_allocs);
  471. } else {
  472. use_cached_heap = false;
  473. CAM_ERR(CAM_MEM,
  474. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  475. cam_flags, tbl.force_cache_allocs);
  476. /*
  477. * Need a better handling based on whether dma-buf-heaps support
  478. * uncached heaps or not. For now, assume not supported.
  479. */
  480. return -EINVAL;
  481. }
  482. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  483. heap = tbl.secure_display_heap;
  484. vmids[num_vmids] = VMID_CP_CAMERA;
  485. perms[num_vmids] = PERM_READ | PERM_WRITE;
  486. num_vmids++;
  487. if (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT) {
  488. CAM_DBG(CAM_MEM, "Secure mode CDSP flags");
  489. vmids[num_vmids] = VMID_CP_CDSP;
  490. perms[num_vmids] = PERM_READ | PERM_WRITE;
  491. num_vmids++;
  492. }
  493. } else if (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL) {
  494. heap = tbl.secure_display_heap;
  495. vmids[num_vmids] = VMID_CP_NON_PIXEL;
  496. perms[num_vmids] = PERM_READ | PERM_WRITE;
  497. num_vmids++;
  498. } else if (use_cached_heap) {
  499. try_heap = tbl.camera_heap;
  500. heap = tbl.system_heap;
  501. } else {
  502. try_heap = tbl.camera_uncached_heap;
  503. heap = tbl.system_uncached_heap;
  504. }
  505. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  506. *buf = NULL;
  507. if (!try_heap && !heap) {
  508. CAM_ERR(CAM_MEM,
  509. "No heap available for allocation, cant allocate");
  510. return -EINVAL;
  511. }
  512. if (try_heap) {
  513. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  514. if (IS_ERR(*buf)) {
  515. CAM_WARN(CAM_MEM,
  516. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  517. try_heap, len, PTR_ERR(*buf));
  518. *buf = NULL;
  519. }
  520. }
  521. if (*buf == NULL) {
  522. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  523. if (IS_ERR(*buf)) {
  524. rc = PTR_ERR(*buf);
  525. CAM_ERR(CAM_MEM,
  526. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  527. heap, len, rc);
  528. *buf = NULL;
  529. return rc;
  530. }
  531. }
  532. *i_ino = file_inode((*buf)->file)->i_ino;
  533. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) ||
  534. (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL)) {
  535. if (num_vmids >= CAM_MAX_VMIDS) {
  536. CAM_ERR(CAM_MEM, "Insufficient array size for vmids %d", num_vmids);
  537. rc = -EINVAL;
  538. goto end;
  539. }
  540. arg.nr_acl_entries = num_vmids;
  541. arg.vmids = vmids;
  542. arg.perms = perms;
  543. rc = mem_buf_lend(*buf, &arg);
  544. if (rc) {
  545. CAM_ERR(CAM_MEM,
  546. "Failed in buf lend rc=%d, buf=%pK, vmids [0]=0x%x, [1]=0x%x, [2]=0x%x",
  547. rc, *buf, vmids[0], vmids[1], vmids[2]);
  548. goto end;
  549. }
  550. }
  551. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK, i_ino=%lu", len, *buf, *i_ino);
  552. if (tbl.alloc_profile_enable) {
  553. CAM_GET_TIMESTAMP(ts2);
  554. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  555. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  556. len, microsec);
  557. }
  558. return rc;
  559. end:
  560. dma_buf_put(*buf);
  561. return rc;
  562. }
  563. #else
  564. static int cam_mem_util_get_dma_buf(size_t len,
  565. unsigned int cam_flags,
  566. struct dma_buf **buf,
  567. unsigned long *i_ino)
  568. {
  569. int rc = 0;
  570. unsigned int heap_id;
  571. int32_t ion_flag = 0;
  572. struct timespec64 ts1, ts2;
  573. long microsec = 0;
  574. if (!buf) {
  575. CAM_ERR(CAM_MEM, "Invalid params");
  576. return -EINVAL;
  577. }
  578. if (tbl.alloc_profile_enable)
  579. CAM_GET_TIMESTAMP(ts1);
  580. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  581. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  582. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  583. ion_flag |=
  584. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  585. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  586. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  587. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  588. } else {
  589. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  590. ION_HEAP(ION_CAMERA_HEAP_ID);
  591. }
  592. if (cam_flags & CAM_MEM_FLAG_CACHE)
  593. ion_flag |= ION_FLAG_CACHED;
  594. else
  595. ion_flag &= ~ION_FLAG_CACHED;
  596. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  597. ion_flag |= ION_FLAG_CACHED;
  598. *buf = ion_alloc(len, heap_id, ion_flag);
  599. if (IS_ERR_OR_NULL(*buf))
  600. return -ENOMEM;
  601. *i_ino = file_inode((*buf)->file)->i_ino;
  602. if (tbl.alloc_profile_enable) {
  603. CAM_GET_TIMESTAMP(ts2);
  604. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  605. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  606. len, microsec);
  607. }
  608. return rc;
  609. }
  610. #endif
  611. static int cam_mem_util_buffer_alloc(size_t len, uint32_t flags,
  612. struct dma_buf **dmabuf,
  613. int *fd,
  614. unsigned long *i_ino)
  615. {
  616. int rc;
  617. struct dma_buf *temp_dmabuf = NULL;
  618. rc = cam_mem_util_get_dma_buf(len, flags, dmabuf, i_ino);
  619. if (rc) {
  620. CAM_ERR(CAM_MEM,
  621. "Error allocating dma buf : len=%llu, flags=0x%x",
  622. len, flags);
  623. return rc;
  624. }
  625. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  626. if (*fd < 0) {
  627. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  628. rc = -EINVAL;
  629. goto put_buf;
  630. }
  631. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d, i_ino=%lu",
  632. len, *dmabuf, *fd, *i_ino);
  633. /*
  634. * increment the ref count so that ref count becomes 2 here
  635. * when we close fd, refcount becomes 1 and when we do
  636. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  637. */
  638. temp_dmabuf = dma_buf_get(*fd);
  639. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  640. rc = PTR_ERR(temp_dmabuf);
  641. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d, i_ino=%lu, rc=%d", *fd, *i_ino, rc);
  642. goto put_buf;
  643. }
  644. return rc;
  645. put_buf:
  646. dma_buf_put(*dmabuf);
  647. return rc;
  648. }
  649. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  650. {
  651. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  652. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  653. CAM_MEM_MMU_MAX_HANDLE);
  654. return -EINVAL;
  655. }
  656. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  657. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  658. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  659. return -EINVAL;
  660. }
  661. if ((cmd->flags & CAM_MEM_FLAG_EVA_NOPIXEL) &&
  662. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE ||
  663. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS)){
  664. CAM_ERR(CAM_MEM,
  665. "Kernel mapping and secure mode not allowed in no pixel mode");
  666. return -EINVAL;
  667. }
  668. return 0;
  669. }
  670. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  671. {
  672. if (!cmd->flags) {
  673. CAM_ERR(CAM_MEM, "Invalid flags");
  674. return -EINVAL;
  675. }
  676. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  677. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  678. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  679. return -EINVAL;
  680. }
  681. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  682. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  683. CAM_ERR(CAM_MEM,
  684. "Kernel mapping in secure mode not allowed, flags=0x%x",
  685. cmd->flags);
  686. return -EINVAL;
  687. }
  688. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  689. CAM_ERR(CAM_MEM,
  690. "Shared memory buffers are not allowed to be mapped");
  691. return -EINVAL;
  692. }
  693. return 0;
  694. }
  695. static int cam_mem_util_map_hw_va(uint32_t flags,
  696. int32_t *mmu_hdls,
  697. int32_t num_hdls,
  698. int fd,
  699. struct dma_buf *dmabuf,
  700. dma_addr_t *hw_vaddr,
  701. size_t *len,
  702. enum cam_smmu_region_id region,
  703. bool is_internal)
  704. {
  705. int i;
  706. int rc = -1;
  707. int dir = cam_mem_util_get_dma_dir(flags);
  708. bool dis_delayed_unmap = false;
  709. if (dir < 0) {
  710. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  711. return dir;
  712. }
  713. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  714. dis_delayed_unmap = true;
  715. CAM_DBG(CAM_MEM,
  716. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  717. fd, flags, dir, num_hdls);
  718. for (i = 0; i < num_hdls; i++) {
  719. /* If 36-bit enabled, check for ICP cmd buffers and map them within the shared region */
  720. if (cam_smmu_is_expanded_memory() &&
  721. cam_smmu_supports_shared_region(mmu_hdls[i]) &&
  722. (flags & CAM_MEM_FLAG_CMD_BUF_TYPE))
  723. region = CAM_SMMU_REGION_SHARED;
  724. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  725. rc = cam_smmu_map_stage2_iova(mmu_hdls[i], fd, dmabuf, dir, hw_vaddr, len);
  726. else
  727. rc = cam_smmu_map_user_iova(mmu_hdls[i], fd, dmabuf, dis_delayed_unmap, dir,
  728. hw_vaddr, len, region, is_internal);
  729. if (rc) {
  730. CAM_ERR(CAM_MEM,
  731. "Failed %s map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  732. (flags & CAM_MEM_FLAG_PROTECTED_MODE) ? "" : "secured",
  733. i, fd, dir, mmu_hdls[i], rc);
  734. goto multi_map_fail;
  735. }
  736. }
  737. return rc;
  738. multi_map_fail:
  739. for (--i; i>= 0; i--) {
  740. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  741. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd, dmabuf);
  742. else
  743. cam_smmu_unmap_user_iova(mmu_hdls[i], fd, dmabuf, CAM_SMMU_REGION_IO);
  744. }
  745. return rc;
  746. }
  747. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  748. {
  749. int rc;
  750. int32_t idx;
  751. struct dma_buf *dmabuf = NULL;
  752. int fd = -1;
  753. dma_addr_t hw_vaddr = 0;
  754. size_t len;
  755. uintptr_t kvaddr = 0;
  756. size_t klen;
  757. unsigned long i_ino = 0;
  758. if (!atomic_read(&cam_mem_mgr_state)) {
  759. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  760. return -EINVAL;
  761. }
  762. if (!cmd) {
  763. CAM_ERR(CAM_MEM, " Invalid argument");
  764. return -EINVAL;
  765. }
  766. len = cmd->len;
  767. if (tbl.need_shared_buffer_padding &&
  768. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)) {
  769. len += CAM_MEM_SHARED_BUFFER_PAD_4K;
  770. CAM_DBG(CAM_MEM, "Pad 4k size, actual %llu, allocating %zu",
  771. cmd->len, len);
  772. }
  773. rc = cam_mem_util_check_alloc_flags(cmd);
  774. if (rc) {
  775. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  776. cmd->flags, rc);
  777. return rc;
  778. }
  779. rc = cam_mem_util_buffer_alloc(len, cmd->flags, &dmabuf, &fd, &i_ino);
  780. if (rc) {
  781. CAM_ERR(CAM_MEM,
  782. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  783. len, cmd->align, cmd->flags, cmd->num_hdl);
  784. cam_mem_mgr_print_tbl();
  785. return rc;
  786. }
  787. if (!dmabuf) {
  788. CAM_ERR(CAM_MEM,
  789. "Ion Alloc return NULL dmabuf! fd=%d, i_ino=%lu, len=%d", fd, i_ino, len);
  790. cam_mem_mgr_print_tbl();
  791. return rc;
  792. }
  793. idx = cam_mem_get_slot();
  794. if (idx < 0) {
  795. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  796. rc = -ENOMEM;
  797. goto slot_fail;
  798. }
  799. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  800. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  801. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  802. enum cam_smmu_region_id region;
  803. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  804. region = CAM_SMMU_REGION_IO;
  805. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  806. region = CAM_SMMU_REGION_SHARED;
  807. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  808. region = CAM_SMMU_REGION_IO;
  809. rc = cam_mem_util_map_hw_va(cmd->flags,
  810. cmd->mmu_hdls,
  811. cmd->num_hdl,
  812. fd,
  813. dmabuf,
  814. &hw_vaddr,
  815. &len,
  816. region,
  817. true);
  818. if (rc) {
  819. CAM_ERR(CAM_MEM,
  820. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  821. len, cmd->flags,
  822. fd, region, cmd->num_hdl, rc);
  823. if (rc == -EALREADY) {
  824. if ((size_t)dmabuf->size != len)
  825. rc = -EBADR;
  826. cam_mem_mgr_print_tbl();
  827. }
  828. goto map_hw_fail;
  829. }
  830. }
  831. mutex_lock(&tbl.bufq[idx].q_lock);
  832. tbl.bufq[idx].fd = fd;
  833. tbl.bufq[idx].i_ino = i_ino;
  834. tbl.bufq[idx].dma_buf = NULL;
  835. tbl.bufq[idx].flags = cmd->flags;
  836. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  837. tbl.bufq[idx].is_internal = true;
  838. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  839. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  840. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  841. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  842. if (rc) {
  843. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  844. dmabuf, rc);
  845. goto map_kernel_fail;
  846. }
  847. }
  848. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  849. tbl.dbg_buf_idx = idx;
  850. tbl.bufq[idx].kmdvaddr = kvaddr;
  851. tbl.bufq[idx].vaddr = hw_vaddr;
  852. tbl.bufq[idx].dma_buf = dmabuf;
  853. tbl.bufq[idx].len = len;
  854. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  855. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  856. sizeof(int32_t) * cmd->num_hdl);
  857. tbl.bufq[idx].is_imported = false;
  858. mutex_unlock(&tbl.bufq[idx].q_lock);
  859. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  860. cmd->out.fd = tbl.bufq[idx].fd;
  861. cmd->out.vaddr = 0;
  862. CAM_DBG(CAM_MEM,
  863. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu, i_ino=%lu",
  864. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  865. tbl.bufq[idx].len, tbl.bufq[idx].i_ino);
  866. return rc;
  867. map_kernel_fail:
  868. mutex_unlock(&tbl.bufq[idx].q_lock);
  869. map_hw_fail:
  870. cam_mem_put_slot(idx);
  871. slot_fail:
  872. dma_buf_put(dmabuf);
  873. return rc;
  874. }
  875. static bool cam_mem_util_is_map_internal(int32_t fd, unsigned i_ino)
  876. {
  877. uint32_t i;
  878. bool is_internal = false;
  879. mutex_lock(&tbl.m_lock);
  880. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  881. if ((tbl.bufq[i].fd == fd) && (tbl.bufq[i].i_ino == i_ino)) {
  882. is_internal = tbl.bufq[i].is_internal;
  883. break;
  884. }
  885. }
  886. mutex_unlock(&tbl.m_lock);
  887. return is_internal;
  888. }
  889. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  890. {
  891. int32_t idx;
  892. int rc;
  893. struct dma_buf *dmabuf;
  894. dma_addr_t hw_vaddr = 0;
  895. size_t len = 0;
  896. bool is_internal = false;
  897. unsigned long i_ino;
  898. if (!atomic_read(&cam_mem_mgr_state)) {
  899. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  900. return -EINVAL;
  901. }
  902. if (!cmd || (cmd->fd < 0)) {
  903. CAM_ERR(CAM_MEM, "Invalid argument");
  904. return -EINVAL;
  905. }
  906. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  907. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  908. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  909. return -EINVAL;
  910. }
  911. rc = cam_mem_util_check_map_flags(cmd);
  912. if (rc) {
  913. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  914. return rc;
  915. }
  916. dmabuf = dma_buf_get(cmd->fd);
  917. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  918. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  919. return -EINVAL;
  920. }
  921. i_ino = file_inode(dmabuf->file)->i_ino;
  922. is_internal = cam_mem_util_is_map_internal(cmd->fd, i_ino);
  923. idx = cam_mem_get_slot();
  924. if (idx < 0) {
  925. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  926. idx, cmd->fd);
  927. rc = -ENOMEM;
  928. goto slot_fail;
  929. }
  930. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  931. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  932. rc = cam_mem_util_map_hw_va(cmd->flags,
  933. cmd->mmu_hdls,
  934. cmd->num_hdl,
  935. cmd->fd,
  936. dmabuf,
  937. &hw_vaddr,
  938. &len,
  939. CAM_SMMU_REGION_IO,
  940. is_internal);
  941. if (rc) {
  942. CAM_ERR(CAM_MEM,
  943. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  944. cmd->flags, cmd->fd, len,
  945. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  946. if (rc == -EALREADY) {
  947. if ((size_t)dmabuf->size != len) {
  948. rc = -EBADR;
  949. cam_mem_mgr_print_tbl();
  950. }
  951. }
  952. goto map_fail;
  953. }
  954. }
  955. mutex_lock(&tbl.bufq[idx].q_lock);
  956. tbl.bufq[idx].fd = cmd->fd;
  957. tbl.bufq[idx].i_ino = i_ino;
  958. tbl.bufq[idx].dma_buf = NULL;
  959. tbl.bufq[idx].flags = cmd->flags;
  960. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  961. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  962. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  963. tbl.bufq[idx].kmdvaddr = 0;
  964. if (cmd->num_hdl > 0)
  965. tbl.bufq[idx].vaddr = hw_vaddr;
  966. else
  967. tbl.bufq[idx].vaddr = 0;
  968. tbl.bufq[idx].dma_buf = dmabuf;
  969. tbl.bufq[idx].len = len;
  970. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  971. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  972. sizeof(int32_t) * cmd->num_hdl);
  973. tbl.bufq[idx].is_imported = true;
  974. tbl.bufq[idx].is_internal = is_internal;
  975. mutex_unlock(&tbl.bufq[idx].q_lock);
  976. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  977. cmd->out.vaddr = 0;
  978. cmd->out.size = (uint32_t)len;
  979. CAM_DBG(CAM_MEM,
  980. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu, i_ino=%lu",
  981. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  982. tbl.bufq[idx].len, tbl.bufq[idx].i_ino);
  983. return rc;
  984. map_fail:
  985. cam_mem_put_slot(idx);
  986. slot_fail:
  987. dma_buf_put(dmabuf);
  988. return rc;
  989. }
  990. static int cam_mem_util_unmap_hw_va(int32_t idx,
  991. enum cam_smmu_region_id region,
  992. enum cam_smmu_mapping_client client)
  993. {
  994. int i;
  995. uint32_t flags;
  996. int32_t *mmu_hdls;
  997. int num_hdls;
  998. int fd;
  999. struct dma_buf *dma_buf;
  1000. unsigned long i_ino;
  1001. int rc = 0;
  1002. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1003. CAM_ERR(CAM_MEM, "Incorrect index");
  1004. return -EINVAL;
  1005. }
  1006. flags = tbl.bufq[idx].flags;
  1007. mmu_hdls = tbl.bufq[idx].hdls;
  1008. num_hdls = tbl.bufq[idx].num_hdl;
  1009. fd = tbl.bufq[idx].fd;
  1010. dma_buf = tbl.bufq[idx].dma_buf;
  1011. i_ino = tbl.bufq[idx].i_ino;
  1012. CAM_DBG(CAM_MEM,
  1013. "unmap_hw_va : idx=%d, fd=%x, i_ino=%lu flags=0x%x, num_hdls=%d, client=%d",
  1014. idx, fd, i_ino, flags, num_hdls, client);
  1015. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  1016. for (i = 0; i < num_hdls; i++) {
  1017. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd, dma_buf);
  1018. if (rc < 0) {
  1019. CAM_ERR(CAM_MEM,
  1020. "Failed in secure unmap, i=%d, fd=%d, i_ino=%lu, mmu_hdl=%d, rc=%d",
  1021. i, fd, i_ino, mmu_hdls[i], rc);
  1022. goto unmap_end;
  1023. }
  1024. }
  1025. } else {
  1026. for (i = 0; i < num_hdls; i++) {
  1027. if (client == CAM_SMMU_MAPPING_USER) {
  1028. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  1029. fd, dma_buf, region);
  1030. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  1031. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  1032. tbl.bufq[idx].dma_buf, region);
  1033. } else {
  1034. CAM_ERR(CAM_MEM,
  1035. "invalid caller for unmapping : %d",
  1036. client);
  1037. rc = -EINVAL;
  1038. }
  1039. if (rc < 0) {
  1040. CAM_ERR(CAM_MEM,
  1041. "Failed in unmap, i=%d, fd=%d, i_ino=%lu, mmu_hdl=%d, region=%d, rc=%d",
  1042. i, fd, i_ino, mmu_hdls[i], region, rc);
  1043. goto unmap_end;
  1044. }
  1045. }
  1046. }
  1047. return rc;
  1048. unmap_end:
  1049. CAM_ERR(CAM_MEM, "unmapping failed");
  1050. return rc;
  1051. }
  1052. static void cam_mem_mgr_unmap_active_buf(int idx)
  1053. {
  1054. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1055. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1056. region = CAM_SMMU_REGION_SHARED;
  1057. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1058. region = CAM_SMMU_REGION_IO;
  1059. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1060. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1061. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1062. tbl.bufq[idx].kmdvaddr);
  1063. }
  1064. static int cam_mem_mgr_cleanup_table(void)
  1065. {
  1066. int i;
  1067. mutex_lock(&tbl.m_lock);
  1068. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1069. if (!tbl.bufq[i].active) {
  1070. CAM_DBG(CAM_MEM,
  1071. "Buffer inactive at idx=%d, continuing", i);
  1072. continue;
  1073. } else {
  1074. CAM_DBG(CAM_MEM,
  1075. "Active buffer at idx=%d, possible leak needs unmapping",
  1076. i);
  1077. cam_mem_mgr_unmap_active_buf(i);
  1078. }
  1079. mutex_lock(&tbl.bufq[i].q_lock);
  1080. if (tbl.bufq[i].dma_buf) {
  1081. dma_buf_put(tbl.bufq[i].dma_buf);
  1082. tbl.bufq[i].dma_buf = NULL;
  1083. }
  1084. tbl.bufq[i].fd = -1;
  1085. tbl.bufq[i].i_ino = 0;
  1086. tbl.bufq[i].flags = 0;
  1087. tbl.bufq[i].buf_handle = -1;
  1088. tbl.bufq[i].vaddr = 0;
  1089. tbl.bufq[i].len = 0;
  1090. memset(tbl.bufq[i].hdls, 0,
  1091. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1092. tbl.bufq[i].num_hdl = 0;
  1093. tbl.bufq[i].dma_buf = NULL;
  1094. tbl.bufq[i].active = false;
  1095. tbl.bufq[i].is_internal = false;
  1096. mutex_unlock(&tbl.bufq[i].q_lock);
  1097. mutex_destroy(&tbl.bufq[i].q_lock);
  1098. }
  1099. bitmap_zero(tbl.bitmap, tbl.bits);
  1100. /* We need to reserve slot 0 because 0 is invalid */
  1101. set_bit(0, tbl.bitmap);
  1102. mutex_unlock(&tbl.m_lock);
  1103. return 0;
  1104. }
  1105. void cam_mem_mgr_deinit(void)
  1106. {
  1107. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1108. cam_mem_mgr_cleanup_table();
  1109. debugfs_remove_recursive(tbl.dentry);
  1110. mutex_lock(&tbl.m_lock);
  1111. bitmap_zero(tbl.bitmap, tbl.bits);
  1112. kfree(tbl.bitmap);
  1113. tbl.bitmap = NULL;
  1114. tbl.dbg_buf_idx = -1;
  1115. mutex_unlock(&tbl.m_lock);
  1116. mutex_destroy(&tbl.m_lock);
  1117. }
  1118. static int cam_mem_util_unmap(int32_t idx,
  1119. enum cam_smmu_mapping_client client)
  1120. {
  1121. int rc = 0;
  1122. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1123. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1124. CAM_ERR(CAM_MEM, "Incorrect index");
  1125. return -EINVAL;
  1126. }
  1127. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1128. mutex_lock(&tbl.m_lock);
  1129. if ((!tbl.bufq[idx].active) &&
  1130. (tbl.bufq[idx].vaddr) == 0) {
  1131. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1132. idx);
  1133. mutex_unlock(&tbl.m_lock);
  1134. return 0;
  1135. }
  1136. /* Deactivate the buffer queue to prevent multiple unmap */
  1137. mutex_lock(&tbl.bufq[idx].q_lock);
  1138. tbl.bufq[idx].active = false;
  1139. tbl.bufq[idx].vaddr = 0;
  1140. mutex_unlock(&tbl.bufq[idx].q_lock);
  1141. mutex_unlock(&tbl.m_lock);
  1142. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1143. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1144. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1145. tbl.bufq[idx].kmdvaddr);
  1146. if (rc)
  1147. CAM_ERR(CAM_MEM,
  1148. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1149. tbl.bufq[idx].dma_buf,
  1150. (void *) tbl.bufq[idx].kmdvaddr);
  1151. }
  1152. }
  1153. /* SHARED flag gets precedence, all other flags after it */
  1154. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1155. region = CAM_SMMU_REGION_SHARED;
  1156. } else {
  1157. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1158. region = CAM_SMMU_REGION_IO;
  1159. }
  1160. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1161. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1162. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1163. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1164. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1165. tbl.bufq[idx].dma_buf);
  1166. /*
  1167. * Workaround as smmu driver doing put_buf without get_buf for kernel mappings
  1168. * Setting NULL here so that we dont call dma_buf_pt again below
  1169. */
  1170. if (client == CAM_SMMU_MAPPING_KERNEL)
  1171. tbl.bufq[idx].dma_buf = NULL;
  1172. }
  1173. mutex_lock(&tbl.m_lock);
  1174. mutex_lock(&tbl.bufq[idx].q_lock);
  1175. tbl.bufq[idx].flags = 0;
  1176. tbl.bufq[idx].buf_handle = -1;
  1177. memset(tbl.bufq[idx].hdls, 0,
  1178. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1179. CAM_DBG(CAM_MEM,
  1180. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK, i_ino %lu",
  1181. idx, tbl.bufq[idx].fd, tbl.bufq[idx].is_imported, tbl.bufq[idx].dma_buf,
  1182. tbl.bufq[idx].i_ino);
  1183. if (tbl.bufq[idx].dma_buf)
  1184. dma_buf_put(tbl.bufq[idx].dma_buf);
  1185. tbl.bufq[idx].fd = -1;
  1186. tbl.bufq[idx].i_ino = 0;
  1187. tbl.bufq[idx].dma_buf = NULL;
  1188. tbl.bufq[idx].is_imported = false;
  1189. tbl.bufq[idx].is_internal = false;
  1190. tbl.bufq[idx].len = 0;
  1191. tbl.bufq[idx].num_hdl = 0;
  1192. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1193. mutex_unlock(&tbl.bufq[idx].q_lock);
  1194. mutex_destroy(&tbl.bufq[idx].q_lock);
  1195. clear_bit(idx, tbl.bitmap);
  1196. mutex_unlock(&tbl.m_lock);
  1197. return rc;
  1198. }
  1199. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1200. {
  1201. int idx;
  1202. int rc;
  1203. if (!atomic_read(&cam_mem_mgr_state)) {
  1204. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1205. return -EINVAL;
  1206. }
  1207. if (!cmd) {
  1208. CAM_ERR(CAM_MEM, "Invalid argument");
  1209. return -EINVAL;
  1210. }
  1211. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1212. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1213. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1214. idx);
  1215. return -EINVAL;
  1216. }
  1217. if (!tbl.bufq[idx].active) {
  1218. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1219. return -EINVAL;
  1220. }
  1221. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1222. CAM_ERR(CAM_MEM,
  1223. "Released buf handle %d not matching within table %d, idx=%d",
  1224. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1225. return -EINVAL;
  1226. }
  1227. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1228. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1229. return rc;
  1230. }
  1231. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1232. struct cam_mem_mgr_memory_desc *out)
  1233. {
  1234. struct dma_buf *buf = NULL;
  1235. int ion_fd = -1;
  1236. int rc = 0;
  1237. uintptr_t kvaddr;
  1238. dma_addr_t iova = 0;
  1239. size_t request_len = 0;
  1240. uint32_t mem_handle;
  1241. int32_t idx;
  1242. int32_t smmu_hdl = 0;
  1243. int32_t num_hdl = 0;
  1244. unsigned long i_ino = 0;
  1245. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1246. if (!atomic_read(&cam_mem_mgr_state)) {
  1247. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1248. return -EINVAL;
  1249. }
  1250. if (!inp || !out) {
  1251. CAM_ERR(CAM_MEM, "Invalid params");
  1252. return -EINVAL;
  1253. }
  1254. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1255. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1256. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1257. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1258. return -EINVAL;
  1259. }
  1260. rc = cam_mem_util_get_dma_buf(inp->size, inp->flags, &buf, &i_ino);
  1261. if (rc) {
  1262. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1263. goto ion_fail;
  1264. } else if (!buf) {
  1265. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1266. goto ion_fail;
  1267. } else {
  1268. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1269. }
  1270. /*
  1271. * we are mapping kva always here,
  1272. * update flags so that we do unmap properly
  1273. */
  1274. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1275. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1276. if (rc) {
  1277. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1278. goto map_fail;
  1279. }
  1280. if (!inp->smmu_hdl) {
  1281. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1282. rc = -EINVAL;
  1283. goto smmu_fail;
  1284. }
  1285. /* SHARED flag gets precedence, all other flags after it */
  1286. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1287. region = CAM_SMMU_REGION_SHARED;
  1288. } else {
  1289. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1290. region = CAM_SMMU_REGION_IO;
  1291. }
  1292. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1293. buf,
  1294. CAM_SMMU_MAP_RW,
  1295. &iova,
  1296. &request_len,
  1297. region);
  1298. if (rc < 0) {
  1299. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1300. goto smmu_fail;
  1301. }
  1302. smmu_hdl = inp->smmu_hdl;
  1303. num_hdl = 1;
  1304. idx = cam_mem_get_slot();
  1305. if (idx < 0) {
  1306. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1307. rc = -ENOMEM;
  1308. goto slot_fail;
  1309. }
  1310. mutex_lock(&tbl.bufq[idx].q_lock);
  1311. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1312. tbl.bufq[idx].dma_buf = buf;
  1313. tbl.bufq[idx].fd = -1;
  1314. tbl.bufq[idx].i_ino = i_ino;
  1315. tbl.bufq[idx].flags = inp->flags;
  1316. tbl.bufq[idx].buf_handle = mem_handle;
  1317. tbl.bufq[idx].kmdvaddr = kvaddr;
  1318. tbl.bufq[idx].vaddr = iova;
  1319. tbl.bufq[idx].len = inp->size;
  1320. tbl.bufq[idx].num_hdl = num_hdl;
  1321. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1322. sizeof(int32_t));
  1323. tbl.bufq[idx].is_imported = false;
  1324. mutex_unlock(&tbl.bufq[idx].q_lock);
  1325. out->kva = kvaddr;
  1326. out->iova = (uint32_t)iova;
  1327. out->smmu_hdl = smmu_hdl;
  1328. out->mem_handle = mem_handle;
  1329. out->len = inp->size;
  1330. out->region = region;
  1331. CAM_DBG(CAM_MEM, "idx=%d, dmabuf=%pK, i_ino=%lu, flags=0x%x, mem_handle=0x%x",
  1332. idx, buf, i_ino, inp->flags, mem_handle);
  1333. return rc;
  1334. slot_fail:
  1335. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1336. buf, region);
  1337. smmu_fail:
  1338. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1339. map_fail:
  1340. dma_buf_put(buf);
  1341. ion_fail:
  1342. return rc;
  1343. }
  1344. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1345. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1346. {
  1347. int32_t idx;
  1348. int rc;
  1349. if (!atomic_read(&cam_mem_mgr_state)) {
  1350. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1351. return -EINVAL;
  1352. }
  1353. if (!inp) {
  1354. CAM_ERR(CAM_MEM, "Invalid argument");
  1355. return -EINVAL;
  1356. }
  1357. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1358. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1359. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1360. return -EINVAL;
  1361. }
  1362. if (!tbl.bufq[idx].active) {
  1363. if (tbl.bufq[idx].vaddr == 0) {
  1364. CAM_ERR(CAM_MEM, "buffer is released already");
  1365. return 0;
  1366. }
  1367. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1368. return -EINVAL;
  1369. }
  1370. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1371. CAM_ERR(CAM_MEM,
  1372. "Released buf handle not matching within table");
  1373. return -EINVAL;
  1374. }
  1375. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1376. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1377. return rc;
  1378. }
  1379. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1380. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1381. enum cam_smmu_region_id region,
  1382. struct cam_mem_mgr_memory_desc *out)
  1383. {
  1384. struct dma_buf *buf = NULL;
  1385. int rc = 0;
  1386. int ion_fd = -1;
  1387. dma_addr_t iova = 0;
  1388. size_t request_len = 0;
  1389. uint32_t mem_handle;
  1390. int32_t idx;
  1391. int32_t smmu_hdl = 0;
  1392. int32_t num_hdl = 0;
  1393. uintptr_t kvaddr = 0;
  1394. unsigned long i_ino = 0;
  1395. if (!atomic_read(&cam_mem_mgr_state)) {
  1396. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1397. return -EINVAL;
  1398. }
  1399. if (!inp || !out) {
  1400. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1401. return -EINVAL;
  1402. }
  1403. if (!inp->smmu_hdl) {
  1404. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1405. return -EINVAL;
  1406. }
  1407. if ((region != CAM_SMMU_REGION_SECHEAP) &&
  1408. (region != CAM_SMMU_REGION_FWUNCACHED)) {
  1409. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1410. return -EINVAL;
  1411. }
  1412. rc = cam_mem_util_get_dma_buf(inp->size, 0, &buf, &i_ino);
  1413. if (rc) {
  1414. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1415. goto ion_fail;
  1416. } else if (!buf) {
  1417. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1418. goto ion_fail;
  1419. } else {
  1420. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1421. }
  1422. if (inp->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1423. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1424. if (rc) {
  1425. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1426. goto kmap_fail;
  1427. }
  1428. }
  1429. rc = cam_smmu_reserve_buf_region(region,
  1430. inp->smmu_hdl, buf, &iova, &request_len);
  1431. if (rc) {
  1432. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1433. goto smmu_fail;
  1434. }
  1435. smmu_hdl = inp->smmu_hdl;
  1436. num_hdl = 1;
  1437. idx = cam_mem_get_slot();
  1438. if (idx < 0) {
  1439. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1440. rc = -ENOMEM;
  1441. goto slot_fail;
  1442. }
  1443. mutex_lock(&tbl.bufq[idx].q_lock);
  1444. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1445. tbl.bufq[idx].fd = -1;
  1446. tbl.bufq[idx].i_ino = i_ino;
  1447. tbl.bufq[idx].dma_buf = buf;
  1448. tbl.bufq[idx].flags = inp->flags;
  1449. tbl.bufq[idx].buf_handle = mem_handle;
  1450. tbl.bufq[idx].kmdvaddr = kvaddr;
  1451. tbl.bufq[idx].vaddr = iova;
  1452. tbl.bufq[idx].len = request_len;
  1453. tbl.bufq[idx].num_hdl = num_hdl;
  1454. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1455. sizeof(int32_t));
  1456. tbl.bufq[idx].is_imported = false;
  1457. mutex_unlock(&tbl.bufq[idx].q_lock);
  1458. out->kva = kvaddr;
  1459. out->iova = (uint32_t)iova;
  1460. out->smmu_hdl = smmu_hdl;
  1461. out->mem_handle = mem_handle;
  1462. out->len = request_len;
  1463. out->region = region;
  1464. return rc;
  1465. slot_fail:
  1466. cam_smmu_release_buf_region(region, smmu_hdl);
  1467. smmu_fail:
  1468. if (region == CAM_SMMU_REGION_FWUNCACHED)
  1469. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1470. kmap_fail:
  1471. dma_buf_put(buf);
  1472. ion_fail:
  1473. return rc;
  1474. }
  1475. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1476. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1477. {
  1478. int32_t idx;
  1479. int rc;
  1480. int32_t smmu_hdl;
  1481. if (!atomic_read(&cam_mem_mgr_state)) {
  1482. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1483. return -EINVAL;
  1484. }
  1485. if (!inp) {
  1486. CAM_ERR(CAM_MEM, "Invalid argument");
  1487. return -EINVAL;
  1488. }
  1489. if ((inp->region != CAM_SMMU_REGION_SECHEAP) &&
  1490. (inp->region != CAM_SMMU_REGION_FWUNCACHED)) {
  1491. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1492. return -EINVAL;
  1493. }
  1494. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1495. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1496. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1497. return -EINVAL;
  1498. }
  1499. if (!tbl.bufq[idx].active) {
  1500. if (tbl.bufq[idx].vaddr == 0) {
  1501. CAM_ERR(CAM_MEM, "buffer is released already");
  1502. return 0;
  1503. }
  1504. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1505. return -EINVAL;
  1506. }
  1507. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1508. CAM_ERR(CAM_MEM,
  1509. "Released buf handle not matching within table");
  1510. return -EINVAL;
  1511. }
  1512. if (tbl.bufq[idx].num_hdl != 1) {
  1513. CAM_ERR(CAM_MEM,
  1514. "Sec heap region should have only one smmu hdl");
  1515. return -ENODEV;
  1516. }
  1517. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1518. sizeof(int32_t));
  1519. if (inp->smmu_hdl != smmu_hdl) {
  1520. CAM_ERR(CAM_MEM,
  1521. "Passed SMMU handle doesn't match with internal hdl");
  1522. return -ENODEV;
  1523. }
  1524. rc = cam_smmu_release_buf_region(inp->region, inp->smmu_hdl);
  1525. if (rc) {
  1526. CAM_ERR(CAM_MEM,
  1527. "Sec heap region release failed");
  1528. return -ENODEV;
  1529. }
  1530. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1531. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1532. if (rc)
  1533. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1534. return rc;
  1535. }
  1536. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);
  1537. #ifndef CONFIG_CAM_PRESIL
  1538. struct dma_buf * cam_mem_mgr_get_dma_buf(int fd)
  1539. {
  1540. return NULL;
  1541. }
  1542. int cam_mem_mgr_send_all_buffers_to_presil(int32_t iommu_hdl)
  1543. {
  1544. return 0;
  1545. }
  1546. int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
  1547. {
  1548. return 0;
  1549. }
  1550. int cam_mem_mgr_retrieve_buffer_from_presil(int32_t buf_handle,
  1551. uint32_t buf_size,
  1552. uint32_t offset,
  1553. int32_t iommu_hdl)
  1554. {
  1555. return 0;
  1556. }
  1557. #endif