ubwcp_main.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/dma-buf.h>
  8. #include <linux/slab.h>
  9. #include <linux/cdev.h>
  10. #include <linux/hashtable.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/types.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/of.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/genalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/numa.h>
  21. #include <linux/memory_hotplug.h>
  22. #include <asm/page.h>
  23. #include <linux/delay.h>
  24. #include <linux/ubwcp_dma_heap.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/clk.h>
  27. #include <linux/iommu.h>
  28. #include <linux/set_memory.h>
  29. #include <linux/range.h>
  30. MODULE_IMPORT_NS(DMA_BUF);
  31. #include "include/kernel/ubwcp.h"
  32. #include "ubwcp_hw.h"
  33. #include "include/uapi/ubwcp_ioctl.h"
  34. #define CREATE_TRACE_POINTS
  35. #include "ubwcp_trace.h"
  36. #define UBWCP_NUM_DEVICES 1
  37. #define UBWCP_DEVICE_NAME "ubwcp"
  38. #define UBWCP_BUFFER_DESC_OFFSET 64
  39. #define UBWCP_BUFFER_DESC_COUNT 256
  40. #define CACHE_ADDR(x) ((x) >> 6)
  41. #define PAGE_ADDR(x) ((x) >> 12)
  42. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  43. #define DBG_BUF_ATTR(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  44. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  45. } while (0)
  46. #define DBG(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  47. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  48. } while (0)
  49. #define ERR(fmt, args...) pr_err("ubwcp: %d: %s(): ~~~ERROR~~~: " fmt "\n", __LINE__, __func__, ##args)
  50. #define ERR_RATE_LIMIT(fmt, args...) pr_err_ratelimited("ubwcp: %s(): ~~~ERROR~~~: " fmt "\n",\
  51. __func__, ##args)
  52. #define FENTRY() DBG("")
  53. #define META_DATA_PITCH_ALIGN 64
  54. #define META_DATA_HEIGHT_ALIGN 16
  55. #define META_DATA_SIZE_ALIGN 4096
  56. #define PIXEL_DATA_SIZE_ALIGN 4096
  57. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  58. enum ula_remove_mem_status {
  59. ULA_REMOVE_MEM_SUCCESS = 0,
  60. ULA_REMOVE_MEM_ABORTED = 1
  61. };
  62. struct ubwcp_desc {
  63. int idx;
  64. void *ptr;
  65. };
  66. /* TBD: confirm size of width/height */
  67. struct ubwcp_dimension {
  68. u16 width;
  69. u16 height;
  70. };
  71. struct ubwcp_plane_info {
  72. u16 pixel_bytes;
  73. u16 per_pixel;
  74. struct ubwcp_dimension tilesize_p; /* pixels */
  75. struct ubwcp_dimension macrotilesize_p; /* pixels */
  76. };
  77. struct ubwcp_image_format_info {
  78. u16 planes;
  79. struct ubwcp_plane_info p_info[2];
  80. };
  81. enum ubwcp_std_image_format {
  82. RGBA = 0,
  83. NV12 = 1,
  84. NV124R = 2,
  85. P010 = 3,
  86. TP10 = 4,
  87. P016 = 5,
  88. INFO_FORMAT_LIST_SIZE,
  89. STD_IMAGE_FORMAT_INVALID = 0xFF
  90. };
  91. enum ubwcp_state {
  92. UBWCP_STATE_READY = 0,
  93. UBWCP_STATE_INVALID = -1,
  94. UBWCP_STATE_FAULT = -2,
  95. };
  96. struct ubwcp_driver {
  97. /* cdev related */
  98. dev_t devt;
  99. struct class *dev_class; //sysfs dev class
  100. struct device *dev_sys; //sysfs dev
  101. struct cdev cdev; //char dev
  102. /* debugfs */
  103. struct dentry *debugfs_root;
  104. bool read_err_irq_en;
  105. bool write_err_irq_en;
  106. bool decode_err_irq_en;
  107. bool encode_err_irq_en;
  108. /* ubwcp devices */
  109. struct device *dev; //ubwcp device
  110. struct device *dev_desc_cb; //smmu dev for descriptors
  111. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  112. void __iomem *base; //ubwcp base address
  113. struct regulator *vdd;
  114. struct clk **clocks;
  115. int num_clocks;
  116. /* interrupts */
  117. int irq_range_ck_rd;
  118. int irq_range_ck_wr;
  119. int irq_encode;
  120. int irq_decode;
  121. /* ula address pool */
  122. u64 ula_pool_base;
  123. u64 ula_pool_size;
  124. struct gen_pool *ula_pool;
  125. configure_mmap mmap_config_fptr;
  126. /* HW version */
  127. u32 hw_ver_major;
  128. u32 hw_ver_minor;
  129. /* keep track of all potential buffers.
  130. * hash table index'ed using dma_buf ptr.
  131. * 2**13 = 8192 hash values
  132. */
  133. DECLARE_HASHTABLE(buf_table, 13);
  134. /* buffer descriptor */
  135. void *buffer_desc_base; /* CPU address */
  136. dma_addr_t buffer_desc_dma_handle; /* dma address */
  137. size_t buffer_desc_size;
  138. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  139. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  140. /* driver state */
  141. enum ubwcp_state state;
  142. atomic_t num_non_lin_buffers;
  143. bool mem_online;
  144. struct mutex desc_lock; /* allocate/free descriptors */
  145. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  146. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  147. struct mutex ula_lock; /* allocate/free ula */
  148. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  149. struct mutex hw_range_ck_lock; /* range ck */
  150. struct list_head err_handler_list; /* error handler list */
  151. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  152. struct dev_pagemap pgmap;
  153. };
  154. struct ubwcp_buf {
  155. struct hlist_node hnode;
  156. struct ubwcp_driver *ubwcp;
  157. struct ubwcp_buffer_attrs buf_attr;
  158. bool perm;
  159. struct ubwcp_desc *desc;
  160. bool buf_attr_set;
  161. enum dma_data_direction lock_dir;
  162. int lock_count;
  163. /* dma_buf info */
  164. struct dma_buf *dma_buf;
  165. struct dma_buf_attachment *attachment;
  166. struct sg_table *sgt;
  167. /* ula info */
  168. phys_addr_t ula_pa;
  169. size_t ula_size;
  170. /* meta metadata */
  171. struct ubwcp_hw_meta_metadata mmdata;
  172. struct mutex lock;
  173. };
  174. static struct ubwcp_driver *me;
  175. static u32 ubwcp_debug_trace_enable;
  176. static struct ubwcp_driver *ubwcp_get_driver(void)
  177. {
  178. if (!me)
  179. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  180. return me;
  181. }
  182. static void image_format_init(struct ubwcp_driver *ubwcp)
  183. { /* planes, bytes/p, Tp , MTp */
  184. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  185. {1, {{4, 1, {16, 4}, {64, 16}}}};
  186. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  187. {2, {{1, 1, {32, 8}, {128, 32}},
  188. {2, 1, {16, 8}, { 64, 32}}}};
  189. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  190. {2, {{1, 1, {64, 4}, {256, 16}},
  191. {2, 1, {32, 4}, {128, 16}}}};
  192. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  193. {2, {{2, 1, {32, 4}, {128, 16}},
  194. {4, 1, {16, 4}, { 64, 16}}}};
  195. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  196. {2, {{4, 3, {48, 4}, {192, 16}},
  197. {8, 3, {24, 4}, { 96, 16}}}};
  198. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  199. {2, {{2, 1, {32, 4}, {128, 16}},
  200. {4, 1, {16, 4}, { 64, 16}}}};
  201. }
  202. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  203. {
  204. int idx;
  205. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  206. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  207. desc_list[idx].idx = -1;
  208. desc_list[idx].ptr = NULL;
  209. }
  210. }
  211. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  212. {
  213. const char *cname;
  214. struct property *prop;
  215. int i;
  216. ubwcp->num_clocks =
  217. of_property_count_strings(dev->of_node, "clock-names");
  218. if (ubwcp->num_clocks < 1) {
  219. ubwcp->num_clocks = 0;
  220. return 0;
  221. }
  222. ubwcp->clocks = devm_kzalloc(dev,
  223. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  224. if (!ubwcp->clocks)
  225. return -ENOMEM;
  226. i = 0;
  227. of_property_for_each_string(dev->of_node, "clock-names",
  228. prop, cname) {
  229. struct clk *c = devm_clk_get(dev, cname);
  230. if (IS_ERR(c)) {
  231. ERR("Couldn't get clock: %s\n", cname);
  232. return PTR_ERR(c);
  233. }
  234. ubwcp->clocks[i] = c;
  235. ++i;
  236. }
  237. return 0;
  238. }
  239. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  240. {
  241. int i, ret = 0;
  242. for (i = 0; i < ubwcp->num_clocks; ++i) {
  243. ret = clk_prepare_enable(ubwcp->clocks[i]);
  244. if (ret) {
  245. ERR("Couldn't enable clock #%d\n", i);
  246. while (i--)
  247. clk_disable_unprepare(ubwcp->clocks[i]);
  248. break;
  249. }
  250. }
  251. return ret;
  252. }
  253. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  254. {
  255. int i;
  256. for (i = ubwcp->num_clocks; i; --i)
  257. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  258. }
  259. /* UBWCP Power control */
  260. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  261. {
  262. int ret = 0;
  263. if (enable)
  264. ret = regulator_enable(ubwcp->vdd);
  265. else
  266. ret = regulator_disable(ubwcp->vdd);
  267. if (ret) {
  268. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  269. return ret;
  270. }
  271. if (enable) {
  272. ret = ubwcp_enable_clocks(ubwcp);
  273. if (ret) {
  274. ERR("enable clocks failed: %d", ret);
  275. regulator_disable(ubwcp->vdd);
  276. return ret;
  277. }
  278. } else {
  279. ubwcp_disable_clocks(ubwcp);
  280. }
  281. return ret;
  282. }
  283. /* get ubwcp_buf corresponding to the given dma_buf */
  284. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  285. {
  286. struct ubwcp_buf *buf = NULL;
  287. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  288. unsigned long flags;
  289. if (!dmabuf || !ubwcp)
  290. return NULL;
  291. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  292. /* look up ubwcp_buf corresponding to this dma_buf */
  293. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  294. if (buf->dma_buf == dmabuf)
  295. break;
  296. }
  297. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  298. return buf;
  299. }
  300. /* return ubwcp hardware version */
  301. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  302. {
  303. struct ubwcp_driver *ubwcp;
  304. FENTRY();
  305. if (!ver) {
  306. ERR("invalid version ptr");
  307. return -EINVAL;
  308. }
  309. ubwcp = ubwcp_get_driver();
  310. if (!ubwcp)
  311. return -1;
  312. if (ubwcp->state != UBWCP_STATE_FAULT)
  313. return -EPERM;
  314. ver->major = ubwcp->hw_ver_major;
  315. ver->minor = ubwcp->hw_ver_minor;
  316. return 0;
  317. }
  318. EXPORT_SYMBOL(ubwcp_get_hw_version);
  319. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  320. {
  321. int ret = 0;
  322. int nid;
  323. void *ptr;
  324. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  325. DBG("calling memremap_pages()...");
  326. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  327. ubwcp->pgmap.nr_range = 1;
  328. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  329. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  330. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  331. ptr = memremap_pages(&ubwcp->pgmap, nid);
  332. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  333. if (IS_ERR(ptr)) {
  334. ret = IS_ERR(ptr);
  335. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  336. ubwcp->ula_pool_base,
  337. ubwcp->ula_pool_size,
  338. ret);
  339. } else {
  340. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  341. ubwcp->ula_pool_base,
  342. ubwcp->ula_pool_size,
  343. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  344. }
  345. return ret;
  346. }
  347. static int ula_map_uncached(u64 base, u64 size)
  348. {
  349. int ret;
  350. trace_ubwcp_set_direct_map_range_uncached_start(size);
  351. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  352. trace_ubwcp_set_direct_map_range_uncached_end(size);
  353. if (ret)
  354. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  355. base, size >> PAGE_SHIFT, ret);
  356. return ret;
  357. }
  358. static void ula_unmap(struct ubwcp_driver *ubwcp)
  359. {
  360. DBG("Calling memunmap_pages() for ULA PA pool");
  361. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  362. memunmap_pages(&ubwcp->pgmap);
  363. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  364. }
  365. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  366. {
  367. DBG("Partial sync offset:0x%lx size:0x%lx", addr, size);
  368. trace_ubwcp_dma_sync_single_for_cpu_start(size);
  369. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  370. trace_ubwcp_dma_sync_single_for_cpu_end(size);
  371. }
  372. /** Remove ula memory in chunks
  373. * Abort if new buffer addition is detected
  374. * If remove succeeds or aborted, return success
  375. * status value indicates if mem was removed or aborted (not removed)
  376. * Otherwise return failure
  377. */
  378. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  379. {
  380. int ret = 0;
  381. unsigned long sync_remain = ubwcp->ula_pool_size;
  382. unsigned long sync_offset = 0;
  383. unsigned long sync_size = 0;
  384. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  385. if (ret)
  386. return ret;
  387. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  388. while (sync_remain > 0) {
  389. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  390. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  391. ula_unmap(ubwcp);
  392. if (ula_add_mem(ubwcp)) {
  393. ERR("remove mem: failed to add back during abort");
  394. return -1;
  395. }
  396. *status = ULA_REMOVE_MEM_ABORTED;
  397. return 0;
  398. }
  399. if (UBWCP_SYNC_GRANULE > sync_remain) {
  400. sync_size = sync_remain;
  401. sync_remain = 0;
  402. } else {
  403. sync_size = UBWCP_SYNC_GRANULE;
  404. sync_remain -= UBWCP_SYNC_GRANULE;
  405. }
  406. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  407. sync_offset += sync_size;
  408. }
  409. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  410. ula_unmap(ubwcp);
  411. *status = ULA_REMOVE_MEM_SUCCESS;
  412. return 0;
  413. }
  414. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  415. {
  416. atomic_inc(&ubwcp->num_non_lin_buffers);
  417. mutex_lock(&ubwcp->mem_hotplug_lock);
  418. if (!ubwcp->mem_online) {
  419. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  420. ERR("Bad state: num_non_lin_buffers should not be 0");
  421. goto err;
  422. }
  423. if (ubwcp_power(ubwcp, true))
  424. goto err;
  425. if (ula_add_mem(ubwcp))
  426. goto err_add_memory;
  427. ubwcp->mem_online = true;
  428. }
  429. mutex_unlock(&ubwcp->mem_hotplug_lock);
  430. return 0;
  431. err_add_memory:
  432. ubwcp_power(ubwcp, false);
  433. err:
  434. atomic_dec(&ubwcp->num_non_lin_buffers);
  435. mutex_unlock(&ubwcp->mem_hotplug_lock);
  436. ubwcp->state = UBWCP_STATE_FAULT;
  437. return -1;
  438. }
  439. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  440. {
  441. int ret;
  442. enum ula_remove_mem_status remove_status;
  443. atomic_dec(&ubwcp->num_non_lin_buffers);
  444. mutex_lock(&ubwcp->mem_hotplug_lock);
  445. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  446. DBG("last buffer: ~~~~~~~~~~~");
  447. if (!ubwcp->mem_online) {
  448. ERR("Bad state: mem_online should not be false");
  449. goto err;
  450. }
  451. ret = ula_remove_mem(ubwcp, &remove_status);
  452. if (ret)
  453. goto err;
  454. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  455. ubwcp->mem_online = false;
  456. if (ubwcp_power(ubwcp, false))
  457. goto err;
  458. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  459. DBG("ula memory offline aborted");
  460. } else {
  461. ERR("unexpected ula remove status: %d", remove_status);
  462. goto err;
  463. }
  464. }
  465. mutex_unlock(&ubwcp->mem_hotplug_lock);
  466. return 0;
  467. err:
  468. atomic_inc(&ubwcp->num_non_lin_buffers);
  469. mutex_unlock(&ubwcp->mem_hotplug_lock);
  470. ubwcp->state = UBWCP_STATE_FAULT;
  471. return -1;
  472. }
  473. /**
  474. *
  475. * Initialize ubwcp buffer for the given dma_buf. This
  476. * initializes ubwcp internal data structures and possibly hw to
  477. * use ubwcp for this buffer.
  478. *
  479. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  480. *
  481. * @return int : 0 on success, otherwise error code
  482. */
  483. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  484. {
  485. struct ubwcp_buf *buf;
  486. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  487. unsigned long flags;
  488. FENTRY();
  489. trace_ubwcp_init_buffer_start(dmabuf);
  490. if (!ubwcp) {
  491. trace_ubwcp_init_buffer_end(dmabuf);
  492. return -1;
  493. }
  494. if (ubwcp->state != UBWCP_STATE_READY) {
  495. ERR("driver in invalid state: %d", ubwcp->state);
  496. trace_ubwcp_init_buffer_end(dmabuf);
  497. return -EPERM;
  498. }
  499. if (!dmabuf) {
  500. ERR("NULL dmabuf input ptr");
  501. trace_ubwcp_init_buffer_end(dmabuf);
  502. return -EINVAL;
  503. }
  504. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  505. ERR("dma_buf already initialized for ubwcp");
  506. trace_ubwcp_init_buffer_end(dmabuf);
  507. return -EEXIST;
  508. }
  509. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  510. if (!buf) {
  511. ERR("failed to alloc for new ubwcp_buf");
  512. trace_ubwcp_init_buffer_end(dmabuf);
  513. return -ENOMEM;
  514. }
  515. mutex_init(&buf->lock);
  516. buf->dma_buf = dmabuf;
  517. buf->ubwcp = ubwcp;
  518. buf->buf_attr.image_format = UBWCP_LINEAR;
  519. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  520. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  521. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  522. trace_ubwcp_init_buffer_end(dmabuf);
  523. return 0;
  524. }
  525. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  526. {
  527. DBG_BUF_ATTR("");
  528. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  529. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  530. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  531. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  532. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  533. DBG_BUF_ATTR("width: %d", attr->width);
  534. DBG_BUF_ATTR("height: %d", attr->height);
  535. DBG_BUF_ATTR("stride: %d", attr->stride);
  536. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  537. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  538. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  539. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  540. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  541. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  542. DBG_BUF_ATTR("");
  543. }
  544. static enum ubwcp_std_image_format to_std_format(u16 ioctl_image_format)
  545. {
  546. switch (ioctl_image_format) {
  547. case UBWCP_RGBA8888:
  548. return RGBA;
  549. case UBWCP_NV12:
  550. case UBWCP_NV12_Y:
  551. case UBWCP_NV12_UV:
  552. return NV12;
  553. case UBWCP_NV124R:
  554. case UBWCP_NV124R_Y:
  555. case UBWCP_NV124R_UV:
  556. return NV124R;
  557. case UBWCP_TP10:
  558. case UBWCP_TP10_Y:
  559. case UBWCP_TP10_UV:
  560. return TP10;
  561. case UBWCP_P010:
  562. case UBWCP_P010_Y:
  563. case UBWCP_P010_UV:
  564. return P010;
  565. case UBWCP_P016:
  566. case UBWCP_P016_Y:
  567. case UBWCP_P016_UV:
  568. return P016;
  569. default:
  570. WARN(1, "Fix this!!!");
  571. return STD_IMAGE_FORMAT_INVALID;
  572. }
  573. }
  574. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  575. {
  576. switch (format) {
  577. case TP10:
  578. *align = 64;
  579. return 0;
  580. case NV12:
  581. *align = 128;
  582. return 0;
  583. case RGBA:
  584. case NV124R:
  585. case P010:
  586. case P016:
  587. *align = 256;
  588. return 0;
  589. default:
  590. return -1;
  591. }
  592. }
  593. /* returns stride of compressed image */
  594. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  595. enum ubwcp_std_image_format format, u32 width)
  596. {
  597. struct ubwcp_plane_info p_info;
  598. u16 macro_tile_width_p;
  599. u16 pixel_bytes;
  600. u16 per_pixel;
  601. p_info = ubwcp->format_info[format].p_info[0];
  602. macro_tile_width_p = p_info.macrotilesize_p.width;
  603. pixel_bytes = p_info.pixel_bytes;
  604. per_pixel = p_info.per_pixel;
  605. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  606. }
  607. static void
  608. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  609. enum ubwcp_std_image_format format,
  610. u32 width_p, u32 height_p,
  611. u32 *width_b, u32 *height_b)
  612. {
  613. u16 pixel_bytes;
  614. u16 per_pixel;
  615. struct ubwcp_image_format_info f_info;
  616. struct ubwcp_plane_info p_info;
  617. f_info = ubwcp->format_info[format];
  618. p_info = f_info.p_info[0];
  619. pixel_bytes = p_info.pixel_bytes;
  620. per_pixel = p_info.per_pixel;
  621. *width_b = (width_p*pixel_bytes)/per_pixel;
  622. *height_b = (height_p*pixel_bytes)/per_pixel;
  623. }
  624. /* check if linear stride conforms to hw limitations
  625. * always returns false for linear image
  626. */
  627. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  628. u16 ioctl_img_fmt, u32 width, u32 lin_stride)
  629. {
  630. u32 compressed_stride;
  631. u32 width_b;
  632. u32 height_b;
  633. enum ubwcp_std_image_format format = to_std_format(ioctl_img_fmt);
  634. if (format == STD_IMAGE_FORMAT_INVALID)
  635. return false;
  636. ubwcp_pixel_to_bytes(ubwcp, format, width, 0, &width_b, &height_b);
  637. if ((lin_stride < width_b) || (lin_stride > 64*1024)) {
  638. ERR("Invalid stride: %u width: %u width_b: %u", lin_stride, width, width_b);
  639. return false;
  640. }
  641. if (format == TP10) {
  642. if(!IS_ALIGNED(lin_stride, 64)) {
  643. ERR("stride must be aligned to 64: %d", lin_stride);
  644. return false;
  645. }
  646. } else {
  647. compressed_stride = get_compressed_stride(ubwcp, format, width);
  648. if (lin_stride != compressed_stride) {
  649. ERR("linear stride: %d must be same as compressed stride: %d",
  650. lin_stride, compressed_stride);
  651. return false;
  652. }
  653. }
  654. return true;
  655. }
  656. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  657. {
  658. switch (ioctl_image_format) {
  659. case UBWCP_LINEAR:
  660. case UBWCP_RGBA8888:
  661. case UBWCP_NV12:
  662. case UBWCP_NV12_Y:
  663. case UBWCP_NV12_UV:
  664. case UBWCP_NV124R:
  665. case UBWCP_NV124R_Y:
  666. case UBWCP_NV124R_UV:
  667. case UBWCP_TP10:
  668. case UBWCP_TP10_Y:
  669. case UBWCP_TP10_UV:
  670. case UBWCP_P010:
  671. case UBWCP_P010_Y:
  672. case UBWCP_P010_UV:
  673. case UBWCP_P016:
  674. case UBWCP_P016_Y:
  675. case UBWCP_P016_UV:
  676. return true;
  677. default:
  678. return false;
  679. }
  680. }
  681. /* validate buffer attributes */
  682. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  683. {
  684. if (!ioctl_format_is_valid(attr->image_format)) {
  685. ERR("invalid image format: %d", attr->image_format);
  686. goto err;
  687. }
  688. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  689. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  690. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  691. goto err;
  692. }
  693. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  694. ERR("compression_type is not valid: %d",
  695. attr->compression_type);
  696. goto err;
  697. }
  698. if (attr->lossy_params != 0) {
  699. ERR("lossy_params is not valid: %d", attr->lossy_params);
  700. goto err;
  701. }
  702. //TBD: some upper limit for width?
  703. if (attr->width > 10*1024) {
  704. ERR("width is invalid (above upper limit): %d", attr->width);
  705. goto err;
  706. }
  707. //TBD: some upper limit for height?
  708. if (attr->height > 10*1024) {
  709. ERR("height is invalid (above upper limit): %d", attr->height);
  710. goto err;
  711. }
  712. if (attr->image_format != UBWCP_LINEAR)
  713. if(!stride_is_valid(ubwcp, attr->image_format, attr->width, attr->stride)) {
  714. ERR("stride is invalid: %d", attr->stride);
  715. goto err;
  716. }
  717. if ((attr->scanlines < attr->height) ||
  718. (attr->scanlines > attr->height + 32*1024)) {
  719. ERR("scanlines is not valid - height: %d scanlines: %d",
  720. attr->height, attr->scanlines);
  721. goto err;
  722. }
  723. if (attr->planar_padding > 4096) {
  724. ERR("planar_padding is not valid. (<= 4096): %d",
  725. attr->planar_padding);
  726. goto err;
  727. }
  728. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  729. ERR("subsample is not valid: %d", attr->subsample);
  730. goto err;
  731. }
  732. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  733. ERR("sub_system_target other that CPU is not supported: %d",
  734. attr->sub_system_target);
  735. goto err;
  736. }
  737. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  738. ERR("sub_system_target is not set to CPU: %d",
  739. attr->sub_system_target);
  740. goto err;
  741. }
  742. if (attr->y_offset != 0) {
  743. ERR("y_offset is not valid: %d", attr->y_offset);
  744. goto err;
  745. }
  746. if (attr->batch_size != 1) {
  747. ERR("batch_size is not valid: %d", attr->batch_size);
  748. goto err;
  749. }
  750. dump_attributes(attr);
  751. return true;
  752. err:
  753. dump_attributes(attr);
  754. return false;
  755. }
  756. /* calculate and return metadata buffer size for a given plane
  757. * and buffer attributes
  758. * NOTE: in this function, we will only pass in NV12 format.
  759. * NOT NV12_Y or NV12_UV etc.
  760. * the Y or UV information is in the "plane"
  761. * "format" here purely means "encoding format" and no information
  762. * if some plane data is missing.
  763. */
  764. static size_t metadata_buf_sz(struct ubwcp_driver *ubwcp,
  765. enum ubwcp_std_image_format format,
  766. u32 width, u32 height, u8 plane)
  767. {
  768. size_t size;
  769. u64 pitch;
  770. u64 lines;
  771. u64 tile_width;
  772. u32 tile_height;
  773. struct ubwcp_image_format_info f_info;
  774. struct ubwcp_plane_info p_info;
  775. f_info = ubwcp->format_info[format];
  776. DBG_BUF_ATTR("");
  777. DBG_BUF_ATTR("");
  778. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  779. if (plane >= f_info.planes) {
  780. ERR("Format does not have requested plane info: format: %d, plane: %d",
  781. format, plane);
  782. WARN(1, "Fix this!!!!!");
  783. return 0;
  784. }
  785. p_info = f_info.p_info[plane];
  786. /* UV plane */
  787. if (plane == 1) {
  788. width = width/2;
  789. height = height/2;
  790. }
  791. tile_width = p_info.tilesize_p.width;
  792. tile_height = p_info.tilesize_p.height;
  793. /* pitch: # of tiles in a row
  794. * lines: # of tile rows
  795. */
  796. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  797. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  798. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  799. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  800. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  801. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  802. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  803. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  804. size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  805. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  806. return size;
  807. }
  808. /* calculate and return size of pixel data buffer for a given plane
  809. * and buffer attributes
  810. */
  811. static size_t pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  812. u16 format, u32 width,
  813. u32 height, u8 plane)
  814. {
  815. size_t size;
  816. u64 pitch;
  817. u64 lines;
  818. u16 pixel_bytes;
  819. u16 per_pixel;
  820. u64 macro_tile_width_p;
  821. u64 macro_tile_height_p;
  822. struct ubwcp_image_format_info f_info;
  823. struct ubwcp_plane_info p_info;
  824. f_info = ubwcp->format_info[format];
  825. DBG_BUF_ATTR("");
  826. DBG_BUF_ATTR("");
  827. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  828. if (plane >= f_info.planes) {
  829. ERR("Format does not have requested plane info: format: %d, plane: %d",
  830. format, plane);
  831. WARN(1, "Fix this!!!!!");
  832. return 0;
  833. }
  834. p_info = f_info.p_info[plane];
  835. pixel_bytes = p_info.pixel_bytes;
  836. per_pixel = p_info.per_pixel;
  837. /* UV plane */
  838. if (plane == 1) {
  839. width = width/2;
  840. height = height/2;
  841. }
  842. macro_tile_width_p = p_info.macrotilesize_p.width;
  843. macro_tile_height_p = p_info.macrotilesize_p.height;
  844. /* align pixel width and height macro tile width and height */
  845. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  846. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  847. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  848. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  849. macro_tile_height_p);
  850. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  851. DBG_BUF_ATTR("pitch : %d", pitch);
  852. DBG_BUF_ATTR("lines : %d", lines);
  853. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  854. size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  855. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  856. return size;
  857. }
  858. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  859. u8 plane)
  860. {
  861. struct ubwcp_image_format_info f_info;
  862. struct ubwcp_plane_info p_info;
  863. f_info = ubwcp->format_info[format];
  864. p_info = f_info.p_info[plane];
  865. return p_info.tilesize_p.height;
  866. }
  867. /*
  868. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  869. */
  870. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  871. u32 stride_b, u32 scanlines, u8 plane,
  872. bool add_tile_pad)
  873. {
  874. size_t size;
  875. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  876. /* UV plane */
  877. if (plane == 1)
  878. scanlines = scanlines/2;
  879. if (add_tile_pad) {
  880. int tile_height = get_tile_height(ubwcp, format, plane);
  881. /* Align plane size to plane tile height */
  882. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  883. }
  884. size = stride_b*scanlines;
  885. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  886. plane, stride_b, scanlines, size, size);
  887. return size;
  888. }
  889. static int missing_plane_from_format(u16 ioctl_image_format)
  890. {
  891. int missing_plane;
  892. switch (ioctl_image_format) {
  893. case UBWCP_NV12_Y:
  894. missing_plane = 2;
  895. break;
  896. case UBWCP_NV12_UV:
  897. missing_plane = 1;
  898. break;
  899. case UBWCP_NV124R_Y:
  900. missing_plane = 2;
  901. break;
  902. case UBWCP_NV124R_UV:
  903. missing_plane = 1;
  904. break;
  905. case UBWCP_TP10_Y:
  906. missing_plane = 2;
  907. break;
  908. case UBWCP_TP10_UV:
  909. missing_plane = 1;
  910. break;
  911. case UBWCP_P010_Y:
  912. missing_plane = 2;
  913. break;
  914. case UBWCP_P010_UV:
  915. missing_plane = 1;
  916. break;
  917. case UBWCP_P016_Y:
  918. missing_plane = 2;
  919. break;
  920. case UBWCP_P016_UV:
  921. missing_plane = 1;
  922. break;
  923. default:
  924. missing_plane = 0;
  925. }
  926. return missing_plane;
  927. }
  928. static int planes_in_format(enum ubwcp_std_image_format format)
  929. {
  930. if (format == RGBA)
  931. return 1;
  932. else
  933. return 2;
  934. }
  935. static unsigned int ubwcp_get_hw_image_format_value(u16 ioctl_image_format)
  936. {
  937. enum ubwcp_std_image_format format;
  938. format = to_std_format(ioctl_image_format);
  939. switch (format) {
  940. case RGBA:
  941. return HW_BUFFER_FORMAT_RGBA;
  942. case NV12:
  943. return HW_BUFFER_FORMAT_NV12;
  944. case NV124R:
  945. return HW_BUFFER_FORMAT_NV124R;
  946. case P010:
  947. return HW_BUFFER_FORMAT_P010;
  948. case TP10:
  949. return HW_BUFFER_FORMAT_TP10;
  950. case P016:
  951. return HW_BUFFER_FORMAT_P016;
  952. default:
  953. WARN(1, "Fix this!!!!!");
  954. return 0;
  955. }
  956. }
  957. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  958. struct ubwcp_buffer_attrs *attr,
  959. size_t ula_y_plane_size,
  960. size_t uv_start_offset)
  961. {
  962. int ret = 0;
  963. size_t ula_y_plane_size_align;
  964. size_t y_tile_align_bytes;
  965. int y_tile_height;
  966. int planes;
  967. /* Only validate UV align if there is both a Y and UV plane */
  968. planes = planes_in_format(to_std_format(attr->image_format));
  969. if (planes != 2)
  970. return 0;
  971. /* Check it is cache line size aligned */
  972. if ((uv_start_offset % 64) != 0) {
  973. ret = -EINVAL;
  974. ERR("uv_start_offset %zu not cache line aligned",
  975. uv_start_offset);
  976. goto err;
  977. }
  978. /*
  979. * Check that UV plane does not overlap with any of the Y plane’s tiles
  980. */
  981. y_tile_height = get_tile_height(ubwcp, to_std_format(attr->image_format), 0);
  982. y_tile_align_bytes = y_tile_height * attr->stride;
  983. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  984. y_tile_align_bytes) * y_tile_align_bytes;
  985. if (uv_start_offset < ula_y_plane_size_align) {
  986. ret = -EINVAL;
  987. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  988. uv_start_offset, ula_y_plane_size_align,
  989. ula_y_plane_size);
  990. goto err;
  991. }
  992. return 0;
  993. err:
  994. return ret;
  995. }
  996. /* calculate ULA buffer parms */
  997. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  998. struct ubwcp_buffer_attrs *attr,
  999. size_t *ula_size,
  1000. size_t *ula_y_plane_size,
  1001. size_t *uv_start_offset)
  1002. {
  1003. size_t size;
  1004. enum ubwcp_std_image_format format;
  1005. int planes;
  1006. int missing_plane;
  1007. u32 stride;
  1008. u32 scanlines;
  1009. u32 planar_padding;
  1010. stride = attr->stride;
  1011. scanlines = attr->scanlines;
  1012. planar_padding = attr->planar_padding;
  1013. /* convert ioctl image format to standard image format */
  1014. format = to_std_format(attr->image_format);
  1015. /* Number of "expected" planes in "the standard defined" image format */
  1016. planes = planes_in_format(format);
  1017. /* any plane missing?
  1018. * valid missing_plane values:
  1019. * 0 == no plane missing
  1020. * 1 == 1st plane missing
  1021. * 2 == 2nd plane missing
  1022. */
  1023. missing_plane = missing_plane_from_format(attr->image_format);
  1024. DBG_BUF_ATTR("ula params -->");
  1025. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1026. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1027. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1028. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1029. if (planes == 1) {
  1030. /* uv_start beyond ULA range */
  1031. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1032. *uv_start_offset = size;
  1033. *ula_y_plane_size = size;
  1034. } else {
  1035. if (!missing_plane) {
  1036. /* size for both planes and padding */
  1037. /* Don't pad out Y plane as client would not expect this padding */
  1038. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1039. *ula_y_plane_size = size;
  1040. size += planar_padding;
  1041. *uv_start_offset = size;
  1042. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1043. } else {
  1044. if (missing_plane == 2) {
  1045. /* Y-only image, set uv_start beyond ULA range */
  1046. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1047. *uv_start_offset = size;
  1048. *ula_y_plane_size = size;
  1049. } else {
  1050. /* first plane data is not there */
  1051. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1052. *uv_start_offset = 0; /* uv data is at the beginning */
  1053. *ula_y_plane_size = 0;
  1054. }
  1055. }
  1056. }
  1057. *ula_size = UBWCP_ALIGN(size, 4096);
  1058. DBG_BUF_ATTR("ULA_Size: %zu (0x%x) (before 4K align: %zu)", *ula_size, *ula_size, size);
  1059. return 0;
  1060. }
  1061. /* calculate UBWCP buffer parms */
  1062. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1063. struct ubwcp_buffer_attrs *attr,
  1064. size_t *md_p0, size_t *pd_p0,
  1065. size_t *md_p1, size_t *pd_p1,
  1066. size_t *stride_tp10_b)
  1067. {
  1068. int planes;
  1069. int missing_plane;
  1070. enum ubwcp_std_image_format format;
  1071. size_t stride_tp10_p;
  1072. FENTRY();
  1073. /* convert ioctl image format to standard image format */
  1074. format = to_std_format(attr->image_format);
  1075. missing_plane = missing_plane_from_format(attr->image_format);
  1076. planes = planes_in_format(format);
  1077. DBG_BUF_ATTR("ubwcp params -->");
  1078. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1079. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1080. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1081. *md_p0 = 0;
  1082. *pd_p0 = 0;
  1083. *md_p1 = 0;
  1084. *pd_p1 = 0;
  1085. *stride_tp10_b = 0;
  1086. if (!missing_plane) {
  1087. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1088. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1089. if (planes == 2) {
  1090. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1091. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1092. }
  1093. } else {
  1094. if (missing_plane == 1) {
  1095. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1096. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1097. } else {
  1098. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1099. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1100. }
  1101. }
  1102. if (format == TP10) {
  1103. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1104. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1105. }
  1106. return 0;
  1107. }
  1108. /* reserve ULA address space of the given size */
  1109. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1110. {
  1111. phys_addr_t pa;
  1112. mutex_lock(&ubwcp->ula_lock);
  1113. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1114. DBG("addr: %p, size: %zx", pa, size);
  1115. mutex_unlock(&ubwcp->ula_lock);
  1116. return pa;
  1117. }
  1118. /* free ULA address space of the given address and size */
  1119. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1120. {
  1121. mutex_lock(&ubwcp->ula_lock);
  1122. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1123. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1124. goto err;
  1125. }
  1126. DBG("addr: %p, size: %zx", pa, size);
  1127. gen_pool_free(ubwcp->ula_pool, pa, size);
  1128. mutex_unlock(&ubwcp->ula_lock);
  1129. return;
  1130. err:
  1131. mutex_unlock(&ubwcp->ula_lock);
  1132. }
  1133. /* free up or expand current_pa and return the new pa */
  1134. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1135. phys_addr_t pa,
  1136. size_t size,
  1137. size_t new_size)
  1138. {
  1139. if (size == new_size)
  1140. return pa;
  1141. if (pa)
  1142. ubwcp_ula_free(ubwcp, pa, size);
  1143. return ubwcp_ula_alloc(ubwcp, new_size);
  1144. }
  1145. /* unmap dma buf */
  1146. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1147. {
  1148. FENTRY();
  1149. if (buf->dma_buf && buf->attachment) {
  1150. DBG("Calling dma_buf_unmap_attachment()");
  1151. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1152. buf->sgt = NULL;
  1153. dma_buf_detach(buf->dma_buf, buf->attachment);
  1154. buf->attachment = NULL;
  1155. }
  1156. }
  1157. static bool verify_dma_buf_size(struct ubwcp_buf *buf, size_t min_size)
  1158. {
  1159. size_t dma_len;
  1160. dma_len = sg_dma_len(buf->sgt->sgl);
  1161. if (dma_len < min_size) {
  1162. ERR("dma len: %zu is less than min ubwcp buffer size: %zu", dma_len, min_size);
  1163. return false;
  1164. } else
  1165. return true;
  1166. }
  1167. /* dma map ubwcp buffer */
  1168. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1169. struct device *dev,
  1170. dma_addr_t *iova)
  1171. {
  1172. int ret = 0;
  1173. struct dma_buf *dma_buf = buf->dma_buf;
  1174. struct dma_buf_attachment *attachment;
  1175. struct sg_table *sgt;
  1176. /* Map buffer to SMMU and get IOVA */
  1177. attachment = dma_buf_attach(dma_buf, dev);
  1178. if (IS_ERR(attachment)) {
  1179. ret = PTR_ERR(attachment);
  1180. ERR("dma_buf_attach() failed: %d", ret);
  1181. goto err;
  1182. }
  1183. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1184. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1185. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1186. if (IS_ERR_OR_NULL(sgt)) {
  1187. ret = PTR_ERR(sgt);
  1188. ERR("dma_buf_map_attachment() failed: %d", ret);
  1189. goto err_detach;
  1190. }
  1191. if (sgt->nents != 1) {
  1192. ERR("nents = %d", sgt->nents);
  1193. goto err_unmap;
  1194. }
  1195. *iova = sg_dma_address(sgt->sgl);
  1196. buf->attachment = attachment;
  1197. buf->sgt = sgt;
  1198. return ret;
  1199. err_unmap:
  1200. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1201. err_detach:
  1202. dma_buf_detach(dma_buf, attachment);
  1203. err:
  1204. if (!ret)
  1205. ret = -1;
  1206. return ret;
  1207. }
  1208. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1209. {
  1210. struct ubwcp_hw_meta_metadata *mmdata;
  1211. struct ubwcp_driver *ubwcp;
  1212. ubwcp = buf->ubwcp;
  1213. mmdata = &buf->mmdata;
  1214. ubwcp_dma_unmap(buf);
  1215. /* reset ula params */
  1216. if (buf->ula_size) {
  1217. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1218. buf->ula_size = 0;
  1219. buf->ula_pa = 0;
  1220. }
  1221. /* reset ubwcp params */
  1222. memset(mmdata, 0, sizeof(*mmdata));
  1223. buf->buf_attr_set = false;
  1224. buf->buf_attr.image_format = UBWCP_LINEAR;
  1225. }
  1226. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1227. {
  1228. DBG_BUF_ATTR("");
  1229. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1230. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1231. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1232. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1233. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1234. mmdata->stride, mmdata->stride << 6);
  1235. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1236. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1237. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1238. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1239. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1240. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1241. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1242. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1243. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1244. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1245. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1246. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1247. DBG_BUF_ATTR("");
  1248. }
  1249. /* set buffer attributes:
  1250. * Failure:
  1251. * This call may fail for multiple reasons and it will leave the buffer in an undefined state.
  1252. * In some situations it may leave the buffer in linear mapped state, and in other situations it
  1253. * may leave the buffer in previously set attributes state.
  1254. */
  1255. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1256. {
  1257. int ret = 0;
  1258. size_t ula_size = 0;
  1259. size_t uv_start_offset = 0;
  1260. size_t ula_y_plane_size = 0;
  1261. phys_addr_t ula_pa = 0x0;
  1262. struct ubwcp_buf *buf;
  1263. struct ubwcp_driver *ubwcp;
  1264. size_t metadata_p0;
  1265. size_t pixeldata_p0;
  1266. size_t metadata_p1;
  1267. size_t pixeldata_p1;
  1268. size_t iova_min_size;
  1269. size_t stride_tp10_b;
  1270. dma_addr_t iova_base;
  1271. struct ubwcp_hw_meta_metadata *mmdata;
  1272. u64 uv_start;
  1273. u32 stride_b;
  1274. u32 width_b;
  1275. u32 height_b;
  1276. enum ubwcp_std_image_format std_image_format;
  1277. bool is_non_lin_buf;
  1278. FENTRY();
  1279. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1280. if (!dmabuf) {
  1281. ERR("NULL dmabuf input ptr");
  1282. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1283. return -EINVAL;
  1284. }
  1285. if (!attr) {
  1286. ERR("NULL attr ptr");
  1287. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1288. return -EINVAL;
  1289. }
  1290. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1291. if (!buf) {
  1292. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1293. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1294. return -EINVAL;
  1295. }
  1296. ubwcp = buf->ubwcp;
  1297. if (ubwcp->state != UBWCP_STATE_READY)
  1298. return -EPERM;
  1299. mutex_lock(&buf->lock);
  1300. if (buf->lock_count) {
  1301. ERR("Cannot set attr when buffer is locked");
  1302. ret = -EBUSY;
  1303. goto unlock;
  1304. }
  1305. mmdata = &buf->mmdata;
  1306. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1307. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1308. ERR("Invalid buf attrs");
  1309. goto unlock;
  1310. }
  1311. /* note: this also checks if buf is mmap'ed */
  1312. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1313. if (ret) {
  1314. ERR("dma_buf_mmap_config(0,0) failed: %d", ret);
  1315. goto unlock;
  1316. }
  1317. if (attr->image_format == UBWCP_LINEAR) {
  1318. DBG_BUF_ATTR("Linear format requested");
  1319. if (buf->buf_attr_set)
  1320. reset_buf_attrs(buf);
  1321. if (is_non_lin_buf) {
  1322. /*
  1323. * Changing buffer from ubwc to linear so decrement
  1324. * number of ubwc buffers
  1325. */
  1326. ret = dec_num_non_lin_buffers(ubwcp);
  1327. }
  1328. mutex_unlock(&buf->lock);
  1329. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1330. return ret;
  1331. }
  1332. std_image_format = to_std_format(attr->image_format);
  1333. if (std_image_format == STD_IMAGE_FORMAT_INVALID) {
  1334. ERR("Unable to map ioctl image format to std image format");
  1335. goto unlock;
  1336. }
  1337. /* Calculate uncompressed-buffer size. */
  1338. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1339. if (ret) {
  1340. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1341. goto unlock;
  1342. }
  1343. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1344. if (ret) {
  1345. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1346. goto unlock;
  1347. }
  1348. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr, &metadata_p0, &pixeldata_p0, &metadata_p1,
  1349. &pixeldata_p1, &stride_tp10_b);
  1350. if (ret) {
  1351. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1352. goto unlock;
  1353. }
  1354. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1355. DBG_BUF_ATTR("");
  1356. DBG_BUF_ATTR("");
  1357. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1358. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1359. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1360. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1361. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1362. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1363. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1364. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1365. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1366. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1367. DBG_BUF_ATTR("");
  1368. /* assign ULA PA with uncompressed-size range */
  1369. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1370. if (!ula_pa) {
  1371. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1372. goto err;
  1373. }
  1374. buf->ula_size = ula_size;
  1375. buf->ula_pa = ula_pa;
  1376. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1377. DBG_BUF_ATTR("");
  1378. /* dma map only the first time attribute is set */
  1379. if (!buf->buf_attr_set) {
  1380. /* linear -> ubwcp. map ubwcp buffer */
  1381. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, &iova_base);
  1382. if (ret) {
  1383. ERR("ubwcp_dma_map() failed: %d", ret);
  1384. goto err;
  1385. }
  1386. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1387. iova_base, iova_min_size, iova_base + iova_min_size);
  1388. }
  1389. if(!verify_dma_buf_size(buf, iova_min_size))
  1390. goto err;
  1391. uv_start = ula_pa + uv_start_offset;
  1392. if (!IS_ALIGNED(uv_start, 64)) {
  1393. ERR("ERROR: uv_start is NOT aligned to cache line");
  1394. goto err;
  1395. }
  1396. /* Convert height and width to bytes for writing to mmdata */
  1397. if (std_image_format != TP10) {
  1398. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1399. attr->height, &width_b, &height_b);
  1400. } else {
  1401. /* for tp10 image compression, we need to program p010 width/height */
  1402. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1403. attr->height, &width_b, &height_b);
  1404. }
  1405. stride_b = attr->stride;
  1406. /* create the mmdata descriptor */
  1407. memset(mmdata, 0, sizeof(*mmdata));
  1408. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1409. mmdata->format = ubwcp_get_hw_image_format_value(attr->image_format);
  1410. if (std_image_format != TP10) {
  1411. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1412. } else {
  1413. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1414. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1415. }
  1416. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1417. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1418. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1419. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1420. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1421. * For other versions, width in bytes & height in pixels.
  1422. */
  1423. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1424. mmdata->width_height = width_b << 16 | height_b;
  1425. else
  1426. mmdata->width_height = width_b << 16 | attr->height;
  1427. print_mmdata_desc(mmdata);
  1428. if (!is_non_lin_buf) {
  1429. /*
  1430. * Changing buffer from linear to ubwc so increment
  1431. * number of ubwc buffers
  1432. */
  1433. ret = inc_num_non_lin_buffers(ubwcp);
  1434. }
  1435. if (ret) {
  1436. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1437. goto err;
  1438. }
  1439. /* inform ULA-PA to dma-heap */
  1440. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1441. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa, buf->ula_size);
  1442. if (ret) {
  1443. ERR("dma_buf_mmap_config() failed: %d", ret);
  1444. if (!is_non_lin_buf)
  1445. dec_num_non_lin_buffers(ubwcp);
  1446. goto err;
  1447. }
  1448. buf->buf_attr = *attr;
  1449. buf->buf_attr_set = true;
  1450. mutex_unlock(&buf->lock);
  1451. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1452. return 0;
  1453. err:
  1454. reset_buf_attrs(buf);
  1455. if (is_non_lin_buf) {
  1456. /*
  1457. * Changing buffer from ubwc to linear so decrement
  1458. * number of ubwc buffers
  1459. */
  1460. dec_num_non_lin_buffers(ubwcp);
  1461. }
  1462. unlock:
  1463. mutex_unlock(&buf->lock);
  1464. if (!ret)
  1465. ret = -1;
  1466. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1467. return ret;
  1468. }
  1469. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1470. /* Set buffer attributes ioctl */
  1471. static int ubwcp_set_buf_attrs_ioctl(struct ubwcp_ioctl_buffer_attrs *attr_ioctl)
  1472. {
  1473. int ret;
  1474. struct dma_buf *dmabuf;
  1475. dmabuf = dma_buf_get(attr_ioctl->fd);
  1476. if (IS_ERR(dmabuf)) {
  1477. ERR("dmabuf ptr not found for dma_buf_fd = %d", dma_buf_fd);
  1478. return PTR_ERR(dmabuf);
  1479. }
  1480. ret = ubwcp_set_buf_attrs(dmabuf, &attr_ioctl->attr);
  1481. dma_buf_put(dmabuf);
  1482. return ret;
  1483. }
  1484. /* Free up the buffer descriptor */
  1485. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1486. {
  1487. int idx = desc->idx;
  1488. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1489. mutex_lock(&ubwcp->desc_lock);
  1490. desc_list[idx].idx = -1;
  1491. desc_list[idx].ptr = NULL;
  1492. DBG("freed descriptor_id: %d", idx);
  1493. mutex_unlock(&ubwcp->desc_lock);
  1494. }
  1495. /* Allocate next available buffer descriptor. */
  1496. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1497. {
  1498. int idx;
  1499. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1500. mutex_lock(&ubwcp->desc_lock);
  1501. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1502. if (desc_list[idx].idx == -1) {
  1503. desc_list[idx].idx = idx;
  1504. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1505. idx*UBWCP_BUFFER_DESC_OFFSET;
  1506. DBG("allocated descriptor_id: %d", idx);
  1507. mutex_unlock(&ubwcp->desc_lock);
  1508. return &desc_list[idx];
  1509. }
  1510. }
  1511. mutex_unlock(&ubwcp->desc_lock);
  1512. return NULL;
  1513. }
  1514. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1515. {
  1516. int ret = 0;
  1517. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1518. trace_ubwcp_hw_flush_start(0);
  1519. ret = ubwcp_hw_flush(ubwcp->base);
  1520. trace_ubwcp_hw_flush_end(0);
  1521. if (ret)
  1522. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1523. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1524. return ret;
  1525. }
  1526. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1527. {
  1528. int ret;
  1529. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1530. mutex_lock(&ubwcp->hw_range_ck_lock);
  1531. trace_ubwcp_hw_flush_start(0);
  1532. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1533. trace_ubwcp_hw_flush_end(0);
  1534. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1535. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1536. return ret;
  1537. }
  1538. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1539. {
  1540. mutex_lock(&ubwcp->hw_range_ck_lock);
  1541. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1542. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1543. }
  1544. /**
  1545. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1546. * CPU access to the compressed buffer. It will perform
  1547. * necessary address translation configuration and cache maintenance ops
  1548. * so that CPU can safely access ubwcp buffer, if this call is
  1549. * successful.
  1550. * Allocate descriptor if not already,
  1551. * perform CMO and then enable range check
  1552. *
  1553. * @param dmabuf : ptr to the dma buf
  1554. * @param direction : direction of access
  1555. *
  1556. * @return int : 0 on success, otherwise error code
  1557. */
  1558. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1559. {
  1560. int ret = 0;
  1561. struct ubwcp_buf *buf;
  1562. struct ubwcp_driver *ubwcp;
  1563. FENTRY();
  1564. trace_ubwcp_lock_start(dmabuf);
  1565. if (!dmabuf) {
  1566. ERR("NULL dmabuf input ptr");
  1567. trace_ubwcp_lock_end(dmabuf);
  1568. return -EINVAL;
  1569. }
  1570. if (!valid_dma_direction(dir)) {
  1571. ERR("invalid direction: %d", dir);
  1572. trace_ubwcp_lock_end(dmabuf);
  1573. return -EINVAL;
  1574. }
  1575. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1576. if (!buf) {
  1577. ERR("ubwcp_buf ptr not found");
  1578. trace_ubwcp_lock_end(dmabuf);
  1579. return -1;
  1580. }
  1581. ubwcp = buf->ubwcp;
  1582. if (ubwcp->state != UBWCP_STATE_READY) {
  1583. ERR("driver in invalid state: %d", ubwcp->state);
  1584. trace_ubwcp_lock_end(dmabuf);
  1585. return -EPERM;
  1586. }
  1587. mutex_lock(&buf->lock);
  1588. if (!buf->buf_attr_set) {
  1589. ERR("lock() called on buffer, but attr not set");
  1590. goto err;
  1591. }
  1592. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1593. ERR("lock() called on linear buffer");
  1594. goto err;
  1595. }
  1596. if (!buf->lock_count) {
  1597. DBG("first lock on buffer");
  1598. /* buf->desc could already be allocated because of perm range xlation */
  1599. if (!buf->desc) {
  1600. /* allocate a buffer descriptor */
  1601. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1602. if (!buf->desc) {
  1603. ERR("ubwcp_allocate_buf_desc() failed");
  1604. goto err;
  1605. }
  1606. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1607. /* Flushing of updated mmdata:
  1608. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1609. * *as long as* it has not cached that itself during previous
  1610. * access to the same descriptor.
  1611. *
  1612. * During unlock of previous use of this descriptor,
  1613. * we do hw flush, which will get rid of this mmdata from
  1614. * ubwcp cache.
  1615. *
  1616. * In addition, we also do a hw flush after enable_range_ck().
  1617. * That will also get rid of any speculative fetch of mmdata
  1618. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1619. * will cache mmdata only for active descriptor. But if ubwcp
  1620. * is speculatively fetching mmdata for all descriptors
  1621. * (irrespetive of enabled or not), the flush during lock
  1622. * will be necessary to make sure ubwcp sees updated mmdata
  1623. * that we just updated
  1624. */
  1625. /* program ULA range for this buffer */
  1626. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1627. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1628. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1629. buf->ula_size);
  1630. }
  1631. /* enable range check */
  1632. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1633. range_check_enable(ubwcp, buf->desc->idx);
  1634. /* Flush/invalidate UBWCP caches */
  1635. /* Why: cpu could have done a speculative fetch before
  1636. * enable_range_ck() and ubwcp in process of returning "default" data
  1637. * we don't want that stashing of default data pending.
  1638. * we force completion of that and then we also cpu invalidate which
  1639. * will get rid of that line.
  1640. */
  1641. ret = ubwcp_flush(ubwcp);
  1642. if (ret) {
  1643. ubwcp->state = UBWCP_STATE_FAULT;
  1644. ERR("ubwcp_flush() failed: %d, driver state set to FAULT", ret);
  1645. goto err_flush_failed;
  1646. }
  1647. /* Flush/invalidate ULA PA from CPU caches
  1648. * TBD: if (dir == READ or BIDIRECTION) //NOT for write
  1649. * -- Confirm with Chris if this can be skipped for write
  1650. */
  1651. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size);
  1652. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1653. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size);
  1654. buf->lock_dir = dir;
  1655. } else {
  1656. DBG("buf already locked");
  1657. /* TBD: what if new buffer direction is not same as previous?
  1658. * must update the dir.
  1659. */
  1660. }
  1661. buf->lock_count++;
  1662. DBG("new lock_count: %d", buf->lock_count);
  1663. mutex_unlock(&buf->lock);
  1664. trace_ubwcp_lock_end(dmabuf);
  1665. return ret;
  1666. err_flush_failed:
  1667. range_check_disable(ubwcp, buf->desc->idx);
  1668. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1669. buf->desc = NULL;
  1670. err:
  1671. mutex_unlock(&buf->lock);
  1672. if (!ret)
  1673. ret = -1;
  1674. trace_ubwcp_lock_end(dmabuf);
  1675. return ret;
  1676. }
  1677. /* This can be called as a result of external unlock() call or
  1678. * internally if free() is called without unlock().
  1679. */
  1680. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1681. {
  1682. int ret = 0;
  1683. struct ubwcp_driver *ubwcp;
  1684. DBG("current lock_count: %d", buf->lock_count);
  1685. if (free_buffer) {
  1686. buf->lock_count = 0;
  1687. DBG("Forced lock_count: %d", buf->lock_count);
  1688. } else {
  1689. buf->lock_count--;
  1690. DBG("new lock_count: %d", buf->lock_count);
  1691. if (buf->lock_count) {
  1692. DBG("more than 1 lock on buffer. waiting until last unlock");
  1693. return 0;
  1694. }
  1695. }
  1696. ubwcp = buf->ubwcp;
  1697. /* Flush/invalidate ULA PA from CPU caches */
  1698. //TBD: if (dir == WRITE or BIDIRECTION)
  1699. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size);
  1700. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1701. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size);
  1702. /* disable range check */
  1703. DBG("disabling range check");
  1704. ret = range_check_disable(ubwcp, buf->desc->idx);
  1705. if (ret) {
  1706. ubwcp->state = UBWCP_STATE_FAULT;
  1707. ERR("disable_range_check_with_flush() failed: %d, driver state set to FAULT", ret);
  1708. }
  1709. /* release descriptor if perm range xlation is not set */
  1710. if (!buf->perm) {
  1711. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1712. buf->desc = NULL;
  1713. }
  1714. return ret;
  1715. }
  1716. /**
  1717. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1718. * safely allow for device access to the compressed buffer including any
  1719. * necessary cache maintenance ops. It may also free up certain ubwcp
  1720. * resources that could result in error when accessed by CPU in
  1721. * unlocked state.
  1722. *
  1723. * @param dmabuf : ptr to the dma buf
  1724. * @param direction : direction of access
  1725. *
  1726. * @return int : 0 on success, otherwise error code
  1727. */
  1728. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1729. {
  1730. struct ubwcp_buf *buf;
  1731. int ret;
  1732. FENTRY();
  1733. trace_ubwcp_unlock_start(dmabuf);
  1734. if (!dmabuf) {
  1735. ERR("NULL dmabuf input ptr");
  1736. trace_ubwcp_unlock_end(dmabuf);
  1737. return -EINVAL;
  1738. }
  1739. if (!valid_dma_direction(dir)) {
  1740. ERR("invalid direction: %d", dir);
  1741. trace_ubwcp_unlock_end(dmabuf);
  1742. return -EINVAL;
  1743. }
  1744. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1745. if (!buf) {
  1746. ERR("ubwcp_buf not found");
  1747. trace_ubwcp_unlock_end(dmabuf);
  1748. return -1;
  1749. }
  1750. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1751. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1752. trace_ubwcp_unlock_end(dmabuf);
  1753. return -EPERM;
  1754. }
  1755. mutex_lock(&buf->lock);
  1756. if (!buf->lock_count) {
  1757. ERR("unlock() called on buffer which not in locked state");
  1758. trace_ubwcp_unlock_end(dmabuf);
  1759. mutex_unlock(&buf->lock);
  1760. return -1;
  1761. }
  1762. ret = unlock_internal(buf, dir, false);
  1763. mutex_unlock(&buf->lock);
  1764. trace_ubwcp_unlock_end(dmabuf);
  1765. return ret;
  1766. }
  1767. /* Return buffer attributes for the given buffer */
  1768. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1769. {
  1770. int ret = 0;
  1771. struct ubwcp_buf *buf;
  1772. FENTRY();
  1773. if (!dmabuf) {
  1774. ERR("NULL dmabuf input ptr");
  1775. return -EINVAL;
  1776. }
  1777. if (!attr) {
  1778. ERR("NULL attr ptr");
  1779. return -EINVAL;
  1780. }
  1781. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1782. if (!buf) {
  1783. ERR("ubwcp_buf ptr not found");
  1784. return -1;
  1785. }
  1786. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1787. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1788. return -EPERM;
  1789. }
  1790. mutex_lock(&buf->lock);
  1791. if (!buf->buf_attr_set) {
  1792. ERR("buffer attributes not set");
  1793. mutex_unlock(&buf->lock);
  1794. return -1;
  1795. }
  1796. *attr = buf->buf_attr;
  1797. mutex_unlock(&buf->lock);
  1798. return ret;
  1799. }
  1800. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1801. /* Set permanent range translation.
  1802. * enable: Descriptor will be reserved for this buffer until disabled,
  1803. * making lock/unlock quicker.
  1804. * disable: Descriptor will not be reserved for this buffer. Instead,
  1805. * descriptor will be allocated and released for each lock/unlock.
  1806. * If currently allocated but not being used, descriptor will be
  1807. * released.
  1808. */
  1809. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1810. {
  1811. int ret = 0;
  1812. struct ubwcp_buf *buf;
  1813. FENTRY();
  1814. if (!dmabuf) {
  1815. ERR("NULL dmabuf input ptr");
  1816. return -EINVAL;
  1817. }
  1818. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1819. if (!buf) {
  1820. ERR("ubwcp_buf not found");
  1821. return -1;
  1822. }
  1823. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1824. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1825. return -EPERM;
  1826. }
  1827. /* not implemented */
  1828. if (1) {
  1829. ERR("API not implemented yet");
  1830. return -1;
  1831. }
  1832. /* TBD: make sure we acquire buf lock while setting this so there is
  1833. * no race condition with attr_set/lock/unlock
  1834. */
  1835. buf->perm = enable;
  1836. /* if "disable" and we have allocated a desc and it is not being
  1837. * used currently, release it
  1838. */
  1839. if (!enable && buf->desc && !buf->lock_count) {
  1840. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1841. buf->desc = NULL;
  1842. /* Flush/invalidate UBWCP caches */
  1843. //TBD: need to do anything?
  1844. }
  1845. return ret;
  1846. }
  1847. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1848. /**
  1849. * Free up ubwcp resources for this buffer.
  1850. *
  1851. * @param dmabuf : ptr to the dma buf
  1852. *
  1853. * @return int : 0 on success, otherwise error code
  1854. */
  1855. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1856. {
  1857. int ret = 0;
  1858. struct ubwcp_buf *buf;
  1859. struct ubwcp_driver *ubwcp;
  1860. unsigned long flags;
  1861. bool is_non_lin_buf;
  1862. FENTRY();
  1863. trace_ubwcp_free_buffer_start(dmabuf);
  1864. if (!dmabuf) {
  1865. ERR("NULL dmabuf input ptr");
  1866. trace_ubwcp_free_buffer_end(dmabuf);
  1867. return -EINVAL;
  1868. }
  1869. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1870. if (!buf) {
  1871. ERR("ubwcp_buf ptr not found");
  1872. trace_ubwcp_free_buffer_end(dmabuf);
  1873. return -1;
  1874. }
  1875. ubwcp = buf->ubwcp;
  1876. if (ubwcp->state != UBWCP_STATE_READY) {
  1877. ERR("driver in invalid state: %d", ubwcp->state);
  1878. trace_ubwcp_free_buffer_end(dmabuf);
  1879. return -EPERM;
  1880. }
  1881. mutex_lock(&buf->lock);
  1882. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1883. if (buf->lock_count) {
  1884. DBG("free before unlock (lock_count: %d). unlock()'ing first", buf->lock_count);
  1885. ret = unlock_internal(buf, buf->lock_dir, true);
  1886. if (ret)
  1887. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1888. }
  1889. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1890. if (buf->desc) {
  1891. if (!buf->perm) {
  1892. ubwcp->state = UBWCP_STATE_FAULT;
  1893. WARN_ON(true);
  1894. }
  1895. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1896. buf->desc = NULL;
  1897. }
  1898. if (buf->buf_attr_set)
  1899. reset_buf_attrs(buf);
  1900. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1901. hash_del(&buf->hnode);
  1902. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1903. mutex_unlock(&buf->lock);
  1904. kfree(buf);
  1905. if (is_non_lin_buf)
  1906. dec_num_non_lin_buffers(ubwcp);
  1907. trace_ubwcp_free_buffer_end(dmabuf);
  1908. return ret;
  1909. }
  1910. /* file open: TBD: increment ref count? */
  1911. static int ubwcp_open(struct inode *i, struct file *f)
  1912. {
  1913. return 0;
  1914. }
  1915. /* file open: TBD: decrement ref count? */
  1916. static int ubwcp_close(struct inode *i, struct file *f)
  1917. {
  1918. return 0;
  1919. }
  1920. /* handle IOCTLs */
  1921. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  1922. {
  1923. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  1924. struct ubwcp_ioctl_hw_version hw_ver;
  1925. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  1926. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  1927. enum ubwcp_std_image_format format;
  1928. struct ubwcp_driver *ubwcp;
  1929. ubwcp = ubwcp_get_driver();
  1930. if (!ubwcp)
  1931. return -EINVAL;
  1932. if (ubwcp->state != UBWCP_STATE_READY) {
  1933. ERR("driver in invalid state: %d", ubwcp->state);
  1934. return -EPERM;
  1935. }
  1936. switch (ioctl_num) {
  1937. case UBWCP_IOCTL_SET_BUF_ATTR:
  1938. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  1939. sizeof(buf_attr_ioctl))) {
  1940. ERR("ERROR: copy_from_user() failed");
  1941. return -EFAULT;
  1942. }
  1943. DBG("IOCTL : SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  1944. if (buf_attr_ioctl.attr.unused1 || buf_attr_ioctl.attr.unused2
  1945. || buf_attr_ioctl.attr.unused3 || buf_attr_ioctl.attr.unused4
  1946. || buf_attr_ioctl.attr.unused5 || buf_attr_ioctl.attr.unused6
  1947. || buf_attr_ioctl.attr.unused7 || buf_attr_ioctl.attr.unused8
  1948. || buf_attr_ioctl.attr.unused9) {
  1949. ERR("ERROR: buf attr unused values must be set to 0");
  1950. return -EINVAL;
  1951. }
  1952. return ubwcp_set_buf_attrs_ioctl(&buf_attr_ioctl);
  1953. case UBWCP_IOCTL_GET_HW_VER:
  1954. DBG("IOCTL : GET_HW_VER");
  1955. if (ubwcp_get_hw_version(&hw_ver))
  1956. return -EINVAL;
  1957. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  1958. ERR("ERROR: copy_to_user() failed");
  1959. return -EFAULT;
  1960. }
  1961. break;
  1962. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  1963. DBG("IOCTL : GET_STRIDE_ALIGN");
  1964. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  1965. sizeof(stride_align_ioctl))) {
  1966. ERR("ERROR: copy_from_user() failed");
  1967. return -EFAULT;
  1968. }
  1969. format = to_std_format(stride_align_ioctl.image_format);
  1970. if (format == STD_IMAGE_FORMAT_INVALID)
  1971. return -EINVAL;
  1972. if (stride_align_ioctl.unused != 0)
  1973. return -EINVAL;
  1974. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  1975. ERR("ERROR: copy_to_user() failed");
  1976. return -EFAULT;
  1977. }
  1978. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  1979. sizeof(stride_align_ioctl))) {
  1980. ERR("ERROR: copy_to_user() failed");
  1981. return -EFAULT;
  1982. }
  1983. break;
  1984. case UBWCP_IOCTL_VALIDATE_STRIDE:
  1985. DBG("IOCTL : VALIDATE_STRIDE");
  1986. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  1987. sizeof(validate_stride_ioctl))) {
  1988. ERR("ERROR: copy_from_user() failed");
  1989. return -EFAULT;
  1990. }
  1991. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  1992. ERR("ERROR: unused values must be set to 0");
  1993. return -EINVAL;
  1994. }
  1995. format = to_std_format(validate_stride_ioctl.image_format);
  1996. if (format == STD_IMAGE_FORMAT_INVALID) {
  1997. ERR("ERROR: invalid format: %d", validate_stride_ioctl.image_format);
  1998. return -EINVAL;
  1999. }
  2000. validate_stride_ioctl.valid = stride_is_valid(ubwcp,
  2001. validate_stride_ioctl.image_format,
  2002. validate_stride_ioctl.width,
  2003. validate_stride_ioctl.stride);
  2004. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2005. sizeof(validate_stride_ioctl))) {
  2006. ERR("ERROR: copy_to_user() failed");
  2007. return -EFAULT;
  2008. }
  2009. break;
  2010. default:
  2011. ERR("Invalid ioctl_num = %d", ioctl_num);
  2012. return -EINVAL;
  2013. }
  2014. return 0;
  2015. }
  2016. static const struct file_operations ubwcp_fops = {
  2017. .owner = THIS_MODULE,
  2018. .open = ubwcp_open,
  2019. .release = ubwcp_close,
  2020. .unlocked_ioctl = ubwcp_ioctl,
  2021. };
  2022. static int read_err_r_op(void *data, u64 *value)
  2023. {
  2024. struct ubwcp_driver *ubwcp = data;
  2025. *value = ubwcp->read_err_irq_en;
  2026. return 0;
  2027. }
  2028. static int read_err_w_op(void *data, u64 value)
  2029. {
  2030. struct ubwcp_driver *ubwcp = data;
  2031. if (ubwcp->state != UBWCP_STATE_READY)
  2032. return -EPERM;
  2033. if (ubwcp_power(ubwcp, true))
  2034. goto err;
  2035. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2036. ubwcp->read_err_irq_en = value;
  2037. if (ubwcp_power(ubwcp, false))
  2038. goto err;
  2039. return 0;
  2040. err:
  2041. ubwcp->state = UBWCP_STATE_FAULT;
  2042. return -1;
  2043. }
  2044. static int write_err_r_op(void *data, u64 *value)
  2045. {
  2046. struct ubwcp_driver *ubwcp = data;
  2047. if (ubwcp->state != UBWCP_STATE_READY)
  2048. return -EPERM;
  2049. *value = ubwcp->write_err_irq_en;
  2050. return 0;
  2051. }
  2052. static int write_err_w_op(void *data, u64 value)
  2053. {
  2054. struct ubwcp_driver *ubwcp = data;
  2055. if (ubwcp->state != UBWCP_STATE_READY)
  2056. return -EPERM;
  2057. if (ubwcp_power(ubwcp, true))
  2058. goto err;
  2059. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2060. ubwcp->write_err_irq_en = value;
  2061. if (ubwcp_power(ubwcp, false))
  2062. goto err;
  2063. return 0;
  2064. err:
  2065. ubwcp->state = UBWCP_STATE_FAULT;
  2066. return -1;
  2067. }
  2068. static int decode_err_r_op(void *data, u64 *value)
  2069. {
  2070. struct ubwcp_driver *ubwcp = data;
  2071. if (ubwcp->state != UBWCP_STATE_READY)
  2072. return -EPERM;
  2073. *value = ubwcp->decode_err_irq_en;
  2074. return 0;
  2075. }
  2076. static int decode_err_w_op(void *data, u64 value)
  2077. {
  2078. struct ubwcp_driver *ubwcp = data;
  2079. if (ubwcp->state != UBWCP_STATE_READY)
  2080. return -EPERM;
  2081. if (ubwcp_power(ubwcp, true))
  2082. goto err;
  2083. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2084. ubwcp->decode_err_irq_en = value;
  2085. if (ubwcp_power(ubwcp, false))
  2086. goto err;
  2087. return 0;
  2088. err:
  2089. ubwcp->state = UBWCP_STATE_FAULT;
  2090. return -1;
  2091. }
  2092. static int encode_err_r_op(void *data, u64 *value)
  2093. {
  2094. struct ubwcp_driver *ubwcp = data;
  2095. if (ubwcp->state != UBWCP_STATE_READY)
  2096. return -EPERM;
  2097. *value = ubwcp->encode_err_irq_en;
  2098. return 0;
  2099. }
  2100. static int encode_err_w_op(void *data, u64 value)
  2101. {
  2102. struct ubwcp_driver *ubwcp = data;
  2103. if (ubwcp->state != UBWCP_STATE_READY)
  2104. return -EPERM;
  2105. if (ubwcp_power(ubwcp, true))
  2106. goto err;
  2107. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2108. ubwcp->encode_err_irq_en = value;
  2109. if (ubwcp_power(ubwcp, false))
  2110. goto err;
  2111. return 0;
  2112. err:
  2113. ubwcp->state = UBWCP_STATE_FAULT;
  2114. return -1;
  2115. }
  2116. static int reg_rw_trace_w_op(void *data, u64 value)
  2117. {
  2118. struct ubwcp_driver *ubwcp = data;
  2119. if (ubwcp->state != UBWCP_STATE_READY)
  2120. return -EPERM;
  2121. ubwcp_hw_trace_set(value);
  2122. return 0;
  2123. }
  2124. static int reg_rw_trace_r_op(void *data, u64 *value)
  2125. {
  2126. struct ubwcp_driver *ubwcp = data;
  2127. bool trace_status;
  2128. if (ubwcp->state != UBWCP_STATE_READY)
  2129. return -EPERM;
  2130. ubwcp_hw_trace_get(&trace_status);
  2131. *value = trace_status;
  2132. return 0;
  2133. }
  2134. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2135. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2136. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2137. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2138. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2139. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2140. {
  2141. struct dentry *debugfs_root;
  2142. struct dentry *dfile;
  2143. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2144. if (IS_ERR_OR_NULL(debugfs_root)) {
  2145. ERR("Failed to create debugfs for ubwcp\n");
  2146. return;
  2147. }
  2148. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2149. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2150. if (IS_ERR_OR_NULL(dfile)) {
  2151. ERR("failed to create reg_rw_trace_en debugfs file");
  2152. goto err;
  2153. }
  2154. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2155. if (IS_ERR_OR_NULL(dfile)) {
  2156. ERR("failed to create read_err_irq debugfs file");
  2157. goto err;
  2158. }
  2159. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2160. if (IS_ERR_OR_NULL(dfile)) {
  2161. ERR("failed to create write_err_irq debugfs file");
  2162. goto err;
  2163. }
  2164. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2165. &decode_err_fops);
  2166. if (IS_ERR_OR_NULL(dfile)) {
  2167. ERR("failed to create decode_err_irq debugfs file");
  2168. goto err;
  2169. }
  2170. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2171. &encode_err_fops);
  2172. if (IS_ERR_OR_NULL(dfile)) {
  2173. ERR("failed to create encode_err_irq debugfs file");
  2174. goto err;
  2175. }
  2176. ubwcp->debugfs_root = debugfs_root;
  2177. return;
  2178. err:
  2179. debugfs_remove_recursive(ubwcp->debugfs_root);
  2180. ubwcp->debugfs_root = NULL;
  2181. }
  2182. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2183. {
  2184. debugfs_remove_recursive(ubwcp->debugfs_root);
  2185. }
  2186. /* ubwcp char device initialization */
  2187. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2188. {
  2189. int ret;
  2190. dev_t devt;
  2191. struct class *dev_class;
  2192. struct device *dev_sys;
  2193. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2194. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2195. if (ret) {
  2196. ERR("alloc_chrdev_region() failed: %d", ret);
  2197. return ret;
  2198. }
  2199. /* create device class (/sys/class/ubwcp_class) */
  2200. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2201. if (IS_ERR(dev_class)) {
  2202. ret = PTR_ERR(dev_class);
  2203. ERR("class_create() failed, ret: %d", ret);
  2204. goto err;
  2205. }
  2206. /* Create device and register with sysfs
  2207. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2208. */
  2209. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2210. UBWCP_DEVICE_NAME);
  2211. if (IS_ERR(dev_sys)) {
  2212. ret = PTR_ERR(dev_sys);
  2213. ERR("device_create() failed, ret: %d", ret);
  2214. goto err_device_create;
  2215. }
  2216. /* register file operations and get cdev */
  2217. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2218. /* associate cdev and device major/minor with file system
  2219. * can do file ops on /dev/ubwcp after this
  2220. */
  2221. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2222. if (ret) {
  2223. ERR("cdev_add() failed, ret: %d", ret);
  2224. goto err_cdev_add;
  2225. }
  2226. ubwcp->devt = devt;
  2227. ubwcp->dev_class = dev_class;
  2228. ubwcp->dev_sys = dev_sys;
  2229. return 0;
  2230. err_cdev_add:
  2231. device_destroy(dev_class, devt);
  2232. err_device_create:
  2233. class_destroy(dev_class);
  2234. err:
  2235. unregister_chrdev_region(devt, UBWCP_NUM_DEVICES);
  2236. return ret;
  2237. }
  2238. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2239. {
  2240. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2241. class_destroy(ubwcp->dev_class);
  2242. cdev_del(&ubwcp->cdev);
  2243. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2244. }
  2245. struct handler_node {
  2246. struct list_head list;
  2247. u32 client_id;
  2248. ubwcp_error_handler_t handler;
  2249. void *data;
  2250. };
  2251. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2252. void *data)
  2253. {
  2254. struct handler_node *node;
  2255. unsigned long flags;
  2256. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2257. if (!ubwcp)
  2258. return -EINVAL;
  2259. if (client_id != -1)
  2260. return -EINVAL;
  2261. if (!handler)
  2262. return -EINVAL;
  2263. if (ubwcp->state != UBWCP_STATE_READY)
  2264. return -EPERM;
  2265. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2266. if (!node)
  2267. return -ENOMEM;
  2268. node->client_id = client_id;
  2269. node->handler = handler;
  2270. node->data = data;
  2271. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2272. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2273. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2274. return 0;
  2275. }
  2276. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2277. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2278. {
  2279. struct handler_node *node;
  2280. unsigned long flags;
  2281. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2282. if (!ubwcp)
  2283. return;
  2284. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2285. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2286. node->handler(err, node->data);
  2287. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2288. }
  2289. int ubwcp_unregister_error_handler(u32 client_id)
  2290. {
  2291. int ret = -EINVAL;
  2292. struct handler_node *node;
  2293. unsigned long flags;
  2294. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2295. if (!ubwcp)
  2296. return -EINVAL;
  2297. if (ubwcp->state != UBWCP_STATE_INVALID)
  2298. return -EPERM;
  2299. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2300. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2301. if (node->client_id == client_id) {
  2302. list_del(&node->list);
  2303. kfree(node);
  2304. ret = 0;
  2305. break;
  2306. }
  2307. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2308. return ret;
  2309. }
  2310. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2311. /* get ubwcp_buf corresponding to the ULA PA*/
  2312. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2313. {
  2314. struct ubwcp_buf *buf = NULL;
  2315. struct dma_buf *ret_buf = NULL;
  2316. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2317. unsigned long flags;
  2318. u32 i;
  2319. if (!ubwcp)
  2320. return NULL;
  2321. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2322. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2323. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2324. ret_buf = buf->dma_buf;
  2325. break;
  2326. }
  2327. }
  2328. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2329. return ret_buf;
  2330. }
  2331. /* get ubwcp_buf corresponding to the IOVA*/
  2332. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2333. {
  2334. struct ubwcp_buf *buf = NULL;
  2335. struct dma_buf *ret_buf = NULL;
  2336. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2337. unsigned long flags;
  2338. u32 i;
  2339. if (!ubwcp)
  2340. return NULL;
  2341. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2342. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2343. unsigned long iova_base;
  2344. unsigned int iova_size;
  2345. if (!buf->sgt)
  2346. continue;
  2347. iova_base = sg_dma_address(buf->sgt->sgl);
  2348. iova_size = sg_dma_len(buf->sgt->sgl);
  2349. if (iova_base <= addr && addr < iova_base + iova_size) {
  2350. ret_buf = buf->dma_buf;
  2351. break;
  2352. }
  2353. }
  2354. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2355. return ret_buf;
  2356. }
  2357. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2358. unsigned long iova, int flags, void *data)
  2359. {
  2360. int ret = 0;
  2361. struct ubwcp_err_info err;
  2362. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2363. struct device *cb_dev = (struct device *)data;
  2364. if (!ubwcp) {
  2365. ret = -EINVAL;
  2366. goto err;
  2367. }
  2368. err.err_code = UBWCP_SMMU_FAULT;
  2369. if (cb_dev == ubwcp->dev_desc_cb)
  2370. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2371. else if (cb_dev == ubwcp->dev_buf_cb)
  2372. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2373. else
  2374. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2375. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2376. err.smmu_err.iova = iova;
  2377. err.smmu_err.iommu_fault_flags = flags;
  2378. ERR_RATE_LIMIT("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2379. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2380. err.smmu_err.iommu_fault_flags);
  2381. ubwcp_notify_error_handlers(&err);
  2382. err:
  2383. return ret;
  2384. }
  2385. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2386. {
  2387. struct ubwcp_driver *ubwcp;
  2388. void __iomem *base;
  2389. phys_addr_t addr;
  2390. struct ubwcp_err_info err;
  2391. ubwcp = (struct ubwcp_driver *) ptr;
  2392. base = ubwcp->base;
  2393. if (irq == ubwcp->irq_range_ck_rd) {
  2394. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2395. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2396. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2397. err.translation_err.ula_pa = addr;
  2398. err.translation_err.read = true;
  2399. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2400. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2401. ubwcp_notify_error_handlers(&err);
  2402. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2403. } else if (irq == ubwcp->irq_range_ck_wr) {
  2404. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2405. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2406. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2407. err.translation_err.ula_pa = addr;
  2408. err.translation_err.read = false;
  2409. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2410. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2411. ubwcp_notify_error_handlers(&err);
  2412. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2413. } else if (irq == ubwcp->irq_encode) {
  2414. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2415. err.err_code = UBWCP_ENCODE_ERROR;
  2416. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2417. err.enc_err.ula_pa = addr;
  2418. ERR_RATE_LIMIT("ubwcp_err: err code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2419. err.err_code, err.enc_err.dmabuf, addr);
  2420. ubwcp_notify_error_handlers(&err);
  2421. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2422. } else if (irq == ubwcp->irq_decode) {
  2423. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2424. err.err_code = UBWCP_DECODE_ERROR;
  2425. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2426. err.dec_err.ula_pa = addr;
  2427. ERR_RATE_LIMIT("ubwcp_err: err code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2428. err.err_code, err.enc_err.dmabuf, addr);
  2429. ubwcp_notify_error_handlers(&err);
  2430. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2431. } else {
  2432. ERR("unknown irq: %d", irq);
  2433. return IRQ_NONE;
  2434. }
  2435. return IRQ_HANDLED;
  2436. }
  2437. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2438. {
  2439. int ret = 0;
  2440. struct device *dev = &pdev->dev;
  2441. FENTRY();
  2442. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2443. if (ubwcp->irq_range_ck_rd < 0)
  2444. return ubwcp->irq_range_ck_rd;
  2445. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2446. if (ubwcp->irq_range_ck_wr < 0)
  2447. return ubwcp->irq_range_ck_wr;
  2448. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2449. if (ubwcp->irq_encode < 0)
  2450. return ubwcp->irq_encode;
  2451. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2452. if (ubwcp->irq_decode < 0)
  2453. return ubwcp->irq_decode;
  2454. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2455. ubwcp->irq_range_ck_wr,
  2456. ubwcp->irq_encode,
  2457. ubwcp->irq_decode);
  2458. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2459. if (ret) {
  2460. ERR("request_irq() failed. irq: %d ret: %d",
  2461. ubwcp->irq_range_ck_rd, ret);
  2462. return ret;
  2463. }
  2464. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2465. if (ret) {
  2466. ERR("request_irq() failed. irq: %d ret: %d",
  2467. ubwcp->irq_range_ck_wr, ret);
  2468. return ret;
  2469. }
  2470. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2471. if (ret) {
  2472. ERR("request_irq() failed. irq: %d ret: %d",
  2473. ubwcp->irq_encode, ret);
  2474. return ret;
  2475. }
  2476. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2477. if (ret) {
  2478. ERR("request_irq() failed. irq: %d ret: %d",
  2479. ubwcp->irq_decode, ret);
  2480. return ret;
  2481. }
  2482. return ret;
  2483. }
  2484. /* ubwcp device probe */
  2485. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2486. {
  2487. int ret = 0;
  2488. struct ubwcp_driver *ubwcp;
  2489. struct device *ubwcp_dev = &pdev->dev;
  2490. FENTRY();
  2491. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2492. if (!ubwcp) {
  2493. ERR("devm_kzalloc() failed");
  2494. return -ENOMEM;
  2495. }
  2496. ubwcp->dev = &pdev->dev;
  2497. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2498. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2499. if (IS_ERR(ubwcp->base)) {
  2500. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2501. return PTR_ERR(ubwcp->base);
  2502. }
  2503. DBG("ubwcp->base: %p", ubwcp->base);
  2504. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2505. if (ret) {
  2506. ERR("failed reading ula_range (base): %d", ret);
  2507. return ret;
  2508. }
  2509. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2510. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2511. if (ret) {
  2512. ERR("failed reading ula_range (size): %d", ret);
  2513. return ret;
  2514. }
  2515. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2516. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2517. /* driver initial state */
  2518. ubwcp->state = UBWCP_STATE_INVALID;
  2519. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2520. ubwcp->mem_online = false;
  2521. mutex_init(&ubwcp->desc_lock);
  2522. spin_lock_init(&ubwcp->buf_table_lock);
  2523. mutex_init(&ubwcp->mem_hotplug_lock);
  2524. mutex_init(&ubwcp->ula_lock);
  2525. mutex_init(&ubwcp->ubwcp_flush_lock);
  2526. mutex_init(&ubwcp->hw_range_ck_lock);
  2527. spin_lock_init(&ubwcp->err_handler_list_lock);
  2528. /* Regulator */
  2529. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2530. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2531. ret = PTR_ERR(ubwcp->vdd);
  2532. ERR("devm_regulator_get() failed: %d", ret);
  2533. return ret;
  2534. }
  2535. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2536. if (ret) {
  2537. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2538. return ret;
  2539. }
  2540. if (ubwcp_power(ubwcp, true))
  2541. return -1;
  2542. if (ubwcp_cdev_init(ubwcp))
  2543. return -1;
  2544. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2545. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2546. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2547. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2548. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2549. if (ubwcp_interrupt_register(pdev, ubwcp))
  2550. return -1;
  2551. ubwcp_debugfs_init(ubwcp);
  2552. /* create ULA pool */
  2553. ubwcp->ula_pool = gen_pool_create(12, -1);
  2554. if (!ubwcp->ula_pool) {
  2555. ERR("failed gen_pool_create()");
  2556. ret = -1;
  2557. goto err_pool_create;
  2558. }
  2559. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2560. if (ret) {
  2561. ERR("failed gen_pool_add(): %d", ret);
  2562. ret = -1;
  2563. goto err_pool_add;
  2564. }
  2565. /* register the default config mmap function. */
  2566. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2567. hash_init(ubwcp->buf_table);
  2568. ubwcp_buf_desc_list_init(ubwcp);
  2569. image_format_init(ubwcp);
  2570. /* one time hw init */
  2571. ubwcp_hw_one_time_init(ubwcp->base);
  2572. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2573. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2574. if (ubwcp->hw_ver_major == 0) {
  2575. ERR("Failed to read HW version");
  2576. ret = -1;
  2577. goto err_pool_add;
  2578. }
  2579. /* set pdev->dev->driver_data = ubwcp */
  2580. platform_set_drvdata(pdev, ubwcp);
  2581. /* enable interrupts */
  2582. if (ubwcp->read_err_irq_en)
  2583. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2584. if (ubwcp->write_err_irq_en)
  2585. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2586. if (ubwcp->decode_err_irq_en)
  2587. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2588. if (ubwcp->encode_err_irq_en)
  2589. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2590. /* Turn OFF until buffers are allocated */
  2591. if (ubwcp_power(ubwcp, false)) {
  2592. ret = -1;
  2593. goto err_power_off;
  2594. }
  2595. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2596. if (ret) {
  2597. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2598. goto err_power_off;
  2599. } else {
  2600. DBG("msm_ubwcp_set_ops(): success"); }
  2601. me = ubwcp;
  2602. return ret;
  2603. err_power_off:
  2604. if (!ubwcp_power(ubwcp, true)) {
  2605. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2606. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2607. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2608. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2609. ubwcp_power(ubwcp, false);
  2610. }
  2611. err_pool_add:
  2612. gen_pool_destroy(ubwcp->ula_pool);
  2613. err_pool_create:
  2614. ubwcp_debugfs_deinit(ubwcp);
  2615. ubwcp_cdev_deinit(ubwcp);
  2616. return ret;
  2617. }
  2618. /* buffer context bank device probe */
  2619. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2620. {
  2621. struct ubwcp_driver *ubwcp;
  2622. struct iommu_domain *domain = NULL;
  2623. FENTRY();
  2624. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2625. if (!ubwcp) {
  2626. ERR("failed to get ubwcp ptr");
  2627. return -EINVAL;
  2628. }
  2629. ubwcp->dev_buf_cb = &pdev->dev;
  2630. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2631. if (domain)
  2632. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2633. if (ubwcp->dev_desc_cb)
  2634. ubwcp->state = UBWCP_STATE_READY;
  2635. return 0;
  2636. }
  2637. /* descriptor context bank device probe */
  2638. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2639. {
  2640. int ret = 0;
  2641. struct ubwcp_driver *ubwcp;
  2642. struct iommu_domain *domain = NULL;
  2643. FENTRY();
  2644. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2645. if (!ubwcp) {
  2646. ERR("failed to get ubwcp ptr");
  2647. return -EINVAL;
  2648. }
  2649. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2650. UBWCP_BUFFER_DESC_COUNT;
  2651. ubwcp->dev_desc_cb = &pdev->dev;
  2652. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2653. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2654. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2655. * Thus we don't need to flush after updates to buffer descriptors.
  2656. */
  2657. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2658. ubwcp->buffer_desc_size,
  2659. &ubwcp->buffer_desc_dma_handle,
  2660. GFP_KERNEL);
  2661. if (!ubwcp->buffer_desc_base) {
  2662. ERR("failed to allocate desc buffer");
  2663. return -ENOMEM;
  2664. }
  2665. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2666. ubwcp->buffer_desc_size);
  2667. ret = ubwcp_power(ubwcp, true);
  2668. if (ret) {
  2669. ERR("failed to power on");
  2670. goto err;
  2671. }
  2672. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2673. UBWCP_BUFFER_DESC_OFFSET);
  2674. ret = ubwcp_power(ubwcp, false);
  2675. if (ret) {
  2676. ERR("failed to power off");
  2677. goto err;
  2678. }
  2679. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2680. if (domain)
  2681. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2682. if (ubwcp->dev_buf_cb)
  2683. ubwcp->state = UBWCP_STATE_READY;
  2684. return ret;
  2685. err:
  2686. dma_free_coherent(ubwcp->dev_desc_cb,
  2687. ubwcp->buffer_desc_size,
  2688. ubwcp->buffer_desc_base,
  2689. ubwcp->buffer_desc_dma_handle);
  2690. ubwcp->buffer_desc_base = NULL;
  2691. ubwcp->buffer_desc_dma_handle = 0;
  2692. ubwcp->dev_desc_cb = NULL;
  2693. return -1;
  2694. }
  2695. /* buffer context bank device remove */
  2696. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2697. {
  2698. struct ubwcp_driver *ubwcp;
  2699. FENTRY();
  2700. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2701. if (!ubwcp) {
  2702. ERR("failed to get ubwcp ptr");
  2703. return -EINVAL;
  2704. }
  2705. ubwcp->state = UBWCP_STATE_INVALID;
  2706. ubwcp->dev_buf_cb = NULL;
  2707. return 0;
  2708. }
  2709. /* descriptor context bank device remove */
  2710. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2711. {
  2712. struct ubwcp_driver *ubwcp;
  2713. FENTRY();
  2714. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2715. if (!ubwcp) {
  2716. ERR("failed to get ubwcp ptr");
  2717. return -EINVAL;
  2718. }
  2719. if (!ubwcp->dev_desc_cb) {
  2720. ERR("ubwcp->dev_desc_cb == NULL");
  2721. return -1;
  2722. }
  2723. if (!ubwcp_power(ubwcp, true)) {
  2724. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2725. ubwcp_power(ubwcp, false);
  2726. }
  2727. ubwcp->state = UBWCP_STATE_INVALID;
  2728. dma_free_coherent(ubwcp->dev_desc_cb,
  2729. ubwcp->buffer_desc_size,
  2730. ubwcp->buffer_desc_base,
  2731. ubwcp->buffer_desc_dma_handle);
  2732. ubwcp->buffer_desc_base = NULL;
  2733. ubwcp->buffer_desc_dma_handle = 0;
  2734. return 0;
  2735. }
  2736. /* ubwcp device remove */
  2737. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2738. {
  2739. size_t avail;
  2740. size_t psize;
  2741. struct ubwcp_driver *ubwcp;
  2742. FENTRY();
  2743. /* get pdev->dev->driver_data = ubwcp */
  2744. ubwcp = platform_get_drvdata(pdev);
  2745. if (!ubwcp) {
  2746. ERR("ubwcp == NULL");
  2747. return -1;
  2748. }
  2749. if (!ubwcp_power(ubwcp, true)) {
  2750. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2751. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2752. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2753. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2754. ubwcp_power(ubwcp, false);
  2755. }
  2756. ubwcp->state = UBWCP_STATE_INVALID;
  2757. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics. */
  2758. avail = gen_pool_avail(ubwcp->ula_pool);
  2759. psize = gen_pool_size(ubwcp->ula_pool);
  2760. if (psize != avail) {
  2761. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2762. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2763. WARN(1, "Fix this!");
  2764. } else {
  2765. gen_pool_destroy(ubwcp->ula_pool);
  2766. }
  2767. ubwcp_debugfs_deinit(ubwcp);
  2768. ubwcp_cdev_deinit(ubwcp);
  2769. return 0;
  2770. }
  2771. /* top level ubwcp device probe function */
  2772. static int ubwcp_probe(struct platform_device *pdev)
  2773. {
  2774. const char *compatible = "";
  2775. FENTRY();
  2776. trace_ubwcp_probe(pdev);
  2777. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2778. return qcom_ubwcp_probe(pdev);
  2779. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2780. return ubwcp_probe_cb_desc(pdev);
  2781. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2782. return ubwcp_probe_cb_buf(pdev);
  2783. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2784. ERR("unknown device: %s", compatible);
  2785. WARN_ON(1);
  2786. return -EINVAL;
  2787. }
  2788. /* top level ubwcp device remove function */
  2789. static int ubwcp_remove(struct platform_device *pdev)
  2790. {
  2791. const char *compatible = "";
  2792. FENTRY();
  2793. trace_ubwcp_remove(pdev);
  2794. /* TBD: what if buffers are still allocated? locked? etc.
  2795. * also should turn off power?
  2796. */
  2797. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2798. return qcom_ubwcp_remove(pdev);
  2799. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2800. return ubwcp_remove_cb_desc(pdev);
  2801. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2802. return ubwcp_remove_cb_buf(pdev);
  2803. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2804. ERR("unknown device: %s", compatible);
  2805. WARN_ON(1);
  2806. return -EINVAL;
  2807. }
  2808. static const struct of_device_id ubwcp_dt_match[] = {
  2809. {.compatible = "qcom,ubwcp"},
  2810. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2811. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2812. {}
  2813. };
  2814. struct platform_driver ubwcp_platform_driver = {
  2815. .probe = ubwcp_probe,
  2816. .remove = ubwcp_remove,
  2817. .driver = {
  2818. .name = "qcom,ubwcp",
  2819. .of_match_table = ubwcp_dt_match,
  2820. },
  2821. };
  2822. int ubwcp_init(void)
  2823. {
  2824. int ret = 0;
  2825. DBG("+++++++++++");
  2826. ret = platform_driver_register(&ubwcp_platform_driver);
  2827. if (ret)
  2828. ERR("platform_driver_register() failed: %d", ret);
  2829. return ret;
  2830. }
  2831. void ubwcp_exit(void)
  2832. {
  2833. platform_driver_unregister(&ubwcp_platform_driver);
  2834. DBG("-----------");
  2835. }
  2836. module_init(ubwcp_init);
  2837. module_exit(ubwcp_exit);
  2838. MODULE_LICENSE("GPL");