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pll
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dsi_pll_28nm.h

dsi_pll_28nm.h 1.8 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef __MDSS_DSI_PLL_28NM_H
    7. 

  7. #define __MDSS_DSI_PLL_28NM_H
    8. 

  8. 

  9. #define DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG          (0x0020)
    10. 

  10. #define DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2       (0x0064)
    11. 

  11. #define DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG         (0x0068)
    12. 

  12. #define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1         (0x0070)
    13. 

  13. 

  14. #define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG	(0x0004)
    15. 

  15. #define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG	(0x0028)
    16. 

  16. #define DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG		(0x0010)
    17. 

  17. 

  18. struct ssc_params {
    19. 

  19. 	s32 kdiv;
    20. 

  20. 	s64 triang_inc_7_0;
    21. 

  21. 	s64 triang_inc_9_8;
    22. 

  22. 	s64 triang_steps;
    23. 

  23. 	s64 dc_offset;
    24. 

  24. 	s64 freq_seed_7_0;
    25. 

  25. 	s64 freq_seed_15_8;
    26. 

  26. };
    27. 

  27. 

  28. struct mdss_dsi_vco_calc {
    29. 

  29. 	s64 sdm_cfg0;
    30. 

  30. 	s64 sdm_cfg1;
    31. 

  31. 	s64 sdm_cfg2;
    32. 

  32. 	s64 sdm_cfg3;
    33. 

  33. 	s64 cal_cfg10;
    34. 

  34. 	s64 cal_cfg11;
    35. 

  35. 	s64 refclk_cfg;
    36. 

  36. 	s64 gen_vco_clk;
    37. 

  37. 	u32 lpfr_lut_res;
    38. 

  38. 	struct ssc_params ssc;
    39. 

  39. };
    40. 

  40. 

  41. unsigned long vco_28nm_recalc_rate(struct clk_hw *hw,
    42. 

  42. 				unsigned long parent_rate);
    43. 

  43. int vco_28nm_set_rate(struct clk_hw *hw, unsigned long rate,
    44. 

  44. 				unsigned long parent_rate);
    45. 

  45. long vco_28nm_round_rate(struct clk_hw *hw, unsigned long rate,
    46. 

  46. 				unsigned long *parent_rate);
    47. 

  47. int vco_28nm_prepare(struct clk_hw *hw);
    48. 

  48. void vco_28nm_unprepare(struct clk_hw *hw);
    49. 

  49. 

  50. int analog_postdiv_reg_write(void *context,
    51. 

  51. 				unsigned int reg, unsigned int div);
    52. 

  52. int analog_postdiv_reg_read(void *context,
    53. 

  53. 				unsigned int reg, unsigned int *div);
    54. 

  54. int byteclk_mux_write_sel(void *context,
    55. 

  55. 				unsigned int reg, unsigned int val);
    56. 

  56. int byteclk_mux_read_sel(void *context,
    57. 

  57. 				unsigned int reg, unsigned int *val);
    58. 

  58. int pixel_clk_set_div(void *context,
    59. 

  59. 				unsigned int reg, unsigned int div);
    60. 

  60. int pixel_clk_get_div(void *context,
    61. 

  61. 				unsigned int reg, unsigned int *div);
    62. 

  62. 

  63. int dsi_pll_lock_status(struct mdss_pll_resources *rsc);
    64. 

  64. #endif /* __MDSS_DSI_PLL_28NM_H */
    65.