sde_kms.c 86 KB

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  1. /*
  2. * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/dma-buf.h>
  24. #include <linux/memblock.h>
  25. #include <linux/bootmem.h>
  26. #include "msm_drv.h"
  27. #include "msm_mmu.h"
  28. #include "msm_gem.h"
  29. #include "dsi_display.h"
  30. #include "dsi_drm.h"
  31. #include "sde_wb.h"
  32. #include "dp_display.h"
  33. #include "dp_drm.h"
  34. #include "sde_kms.h"
  35. #include "sde_core_irq.h"
  36. #include "sde_formats.h"
  37. #include "sde_hw_vbif.h"
  38. #include "sde_vbif.h"
  39. #include "sde_encoder.h"
  40. #include "sde_plane.h"
  41. #include "sde_crtc.h"
  42. #include "sde_reg_dma.h"
  43. #include <soc/qcom/scm.h>
  44. #include "soc/qcom/secure_buffer.h"
  45. #include "soc/qcom/qtee_shmbridge.h"
  46. #define CREATE_TRACE_POINTS
  47. #include "sde_trace.h"
  48. /* defines for secure channel call */
  49. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  50. #define MDP_DEVICE_ID 0x1A
  51. static const char * const iommu_ports[] = {
  52. "mdp_0",
  53. };
  54. /**
  55. * Controls size of event log buffer. Specified as a power of 2.
  56. */
  57. #define SDE_EVTLOG_SIZE 1024
  58. /*
  59. * To enable overall DRM driver logging
  60. * # echo 0x2 > /sys/module/drm/parameters/debug
  61. *
  62. * To enable DRM driver h/w logging
  63. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  64. *
  65. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  66. */
  67. #define SDE_DEBUGFS_DIR "msm_sde"
  68. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  69. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  70. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  71. /**
  72. * sdecustom - enable certain driver customizations for sde clients
  73. * Enabling this modifies the standard DRM behavior slightly and assumes
  74. * that the clients have specific knowledge about the modifications that
  75. * are involved, so don't enable this unless you know what you're doing.
  76. *
  77. * Parts of the driver that are affected by this setting may be located by
  78. * searching for invocations of the 'sde_is_custom_client()' function.
  79. *
  80. * This is disabled by default.
  81. */
  82. static bool sdecustom = true;
  83. module_param(sdecustom, bool, 0400);
  84. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  85. static int sde_kms_hw_init(struct msm_kms *kms);
  86. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  87. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  88. static int _sde_kms_register_events(struct msm_kms *kms,
  89. struct drm_mode_object *obj, u32 event, bool en);
  90. bool sde_is_custom_client(void)
  91. {
  92. return sdecustom;
  93. }
  94. #ifdef CONFIG_DEBUG_FS
  95. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  96. {
  97. struct msm_drm_private *priv;
  98. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  99. return NULL;
  100. priv = sde_kms->dev->dev_private;
  101. return priv->debug_root;
  102. }
  103. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  104. {
  105. void *p;
  106. int rc;
  107. void *debugfs_root;
  108. p = sde_hw_util_get_log_mask_ptr();
  109. if (!sde_kms || !p)
  110. return -EINVAL;
  111. debugfs_root = sde_debugfs_get_root(sde_kms);
  112. if (!debugfs_root)
  113. return -EINVAL;
  114. /* allow debugfs_root to be NULL */
  115. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  116. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  117. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  118. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  119. if (rc) {
  120. SDE_ERROR("failed to init perf %d\n", rc);
  121. return rc;
  122. }
  123. if (sde_kms->catalog->qdss_count)
  124. debugfs_create_u32("qdss", 0600, debugfs_root,
  125. (u32 *)&sde_kms->qdss_enabled);
  126. return 0;
  127. }
  128. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  129. {
  130. /* don't need to NULL check debugfs_root */
  131. if (sde_kms) {
  132. sde_debugfs_vbif_destroy(sde_kms);
  133. sde_debugfs_core_irq_destroy(sde_kms);
  134. }
  135. }
  136. #else
  137. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  138. {
  139. return 0;
  140. }
  141. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  142. {
  143. }
  144. #endif
  145. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  146. {
  147. int ret = 0;
  148. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  149. ret = sde_crtc_vblank(crtc, true);
  150. SDE_ATRACE_END("sde_kms_enable_vblank");
  151. return ret;
  152. }
  153. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  154. {
  155. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  156. sde_crtc_vblank(crtc, false);
  157. SDE_ATRACE_END("sde_kms_disable_vblank");
  158. }
  159. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  160. struct drm_crtc *crtc)
  161. {
  162. struct drm_encoder *encoder;
  163. struct drm_device *dev;
  164. int ret;
  165. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  166. SDE_ERROR("invalid params\n");
  167. return;
  168. }
  169. if (!crtc->state->enable) {
  170. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  171. return;
  172. }
  173. if (!crtc->state->active) {
  174. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  175. return;
  176. }
  177. dev = crtc->dev;
  178. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  179. if (encoder->crtc != crtc)
  180. continue;
  181. /*
  182. * Video Mode - Wait for VSYNC
  183. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  184. * complete
  185. */
  186. SDE_EVT32_VERBOSE(DRMID(crtc));
  187. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  188. if (ret && ret != -EWOULDBLOCK) {
  189. SDE_ERROR(
  190. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  191. crtc->base.id, encoder->base.id, ret);
  192. break;
  193. }
  194. }
  195. }
  196. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  197. struct drm_crtc *crtc, bool enable)
  198. {
  199. struct drm_device *dev;
  200. struct msm_drm_private *priv;
  201. struct sde_mdss_cfg *sde_cfg;
  202. struct drm_plane *plane;
  203. int i, ret;
  204. dev = sde_kms->dev;
  205. priv = dev->dev_private;
  206. sde_cfg = sde_kms->catalog;
  207. ret = sde_vbif_halt_xin_mask(sde_kms,
  208. sde_cfg->sui_block_xin_mask, enable);
  209. if (ret) {
  210. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  211. return ret;
  212. }
  213. if (enable) {
  214. for (i = 0; i < priv->num_planes; i++) {
  215. plane = priv->planes[i];
  216. sde_plane_secure_ctrl_xin_client(plane, crtc);
  217. }
  218. }
  219. return 0;
  220. }
  221. /**
  222. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  223. * @sde_kms: Pointer to sde_kms struct
  224. * @vimd: switch the stage 2 translation to this VMID
  225. */
  226. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  227. {
  228. struct scm_desc desc = {0};
  229. uint32_t num_sids;
  230. uint32_t *sec_sid;
  231. uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;
  232. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  233. int ret = 0, i;
  234. struct qtee_shm shm;
  235. bool qtee_en = qtee_shmbridge_is_enabled();
  236. num_sids = sde_cfg->sec_sid_mask_count;
  237. if (!num_sids) {
  238. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  239. return -EINVAL;
  240. }
  241. if (qtee_en) {
  242. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  243. &shm);
  244. if (ret)
  245. return -ENOMEM;
  246. sec_sid = (uint32_t *) shm.vaddr;
  247. desc.args[1] = shm.paddr;
  248. desc.args[2] = shm.size;
  249. } else {
  250. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  251. if (!sec_sid)
  252. return -ENOMEM;
  253. desc.args[1] = SCM_BUFFER_PHYS(sec_sid);
  254. desc.args[2] = sizeof(uint32_t) * num_sids;
  255. }
  256. desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL);
  257. desc.args[0] = MDP_DEVICE_ID;
  258. desc.args[3] = vmid;
  259. for (i = 0; i < num_sids; i++) {
  260. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  261. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  262. }
  263. dmac_flush_range(sec_sid, sec_sid + num_sids);
  264. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  265. vmid, num_sids, qtee_en);
  266. ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
  267. mem_protect_sd_ctrl_id), &desc);
  268. if (ret)
  269. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  270. desc.args[3], ret);
  271. SDE_EVT32(mem_protect_sd_ctrl_id, desc.args[0], desc.args[2],
  272. desc.args[3], qtee_en, num_sids, ret);
  273. if (qtee_en)
  274. qtee_shmbridge_free_shm(&shm);
  275. else
  276. kfree(sec_sid);
  277. return ret;
  278. }
  279. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  280. {
  281. u32 ret = 0;
  282. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  283. goto end;
  284. /* detach_all_contexts */
  285. ret = sde_kms_mmu_detach(sde_kms, false);
  286. if (ret) {
  287. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  288. goto end;
  289. }
  290. ret = _sde_kms_scm_call(sde_kms, vmid);
  291. if (ret)
  292. goto end;
  293. end:
  294. return ret;
  295. }
  296. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, int vmid)
  297. {
  298. u32 ret = 0;
  299. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  300. goto end;
  301. ret = _sde_kms_scm_call(sde_kms, vmid);
  302. if (ret)
  303. goto end;
  304. /* attach_all_contexts */
  305. ret = sde_kms_mmu_attach(sde_kms, false);
  306. if (ret) {
  307. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  308. goto end;
  309. }
  310. end:
  311. return ret;
  312. }
  313. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  314. {
  315. u32 ret = 0;
  316. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  317. goto end;
  318. /* detach secure_context */
  319. ret = sde_kms_mmu_detach(sde_kms, true);
  320. if (ret) {
  321. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  322. goto end;
  323. }
  324. ret = _sde_kms_scm_call(sde_kms, vmid);
  325. if (ret)
  326. goto end;
  327. end:
  328. return ret;
  329. }
  330. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, int vmid)
  331. {
  332. u32 ret = 0;
  333. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  334. goto end;
  335. ret = _sde_kms_scm_call(sde_kms, vmid);
  336. if (ret)
  337. goto end;
  338. ret = sde_kms_mmu_attach(sde_kms, true);
  339. if (ret) {
  340. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  341. goto end;
  342. }
  343. end:
  344. return ret;
  345. }
  346. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  347. struct drm_crtc *crtc, bool enable)
  348. {
  349. int ret;
  350. if (enable) {
  351. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  352. if (ret < 0) {
  353. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  354. return ret;
  355. }
  356. sde_crtc_misr_setup(crtc, true, 1);
  357. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  358. if (ret) {
  359. pm_runtime_put_sync(sde_kms->dev->dev);
  360. return ret;
  361. }
  362. } else {
  363. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  364. sde_crtc_misr_setup(crtc, false, 0);
  365. pm_runtime_put_sync(sde_kms->dev->dev);
  366. }
  367. return 0;
  368. }
  369. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  370. bool post_commit)
  371. {
  372. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  373. int old_smmu_state = smmu_state->state;
  374. int ret = 0;
  375. u32 vmid;
  376. if (!sde_kms || !crtc) {
  377. SDE_ERROR("invalid argument(s)\n");
  378. return -EINVAL;
  379. }
  380. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  381. post_commit, smmu_state->sui_misr_state,
  382. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  383. if ((!smmu_state->transition_type) ||
  384. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  385. /* Bail out */
  386. return 0;
  387. /* enable sui misr if requested, before the transition */
  388. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  389. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  390. if (ret)
  391. goto end;
  392. }
  393. mutex_lock(&sde_kms->secure_transition_lock);
  394. switch (smmu_state->state) {
  395. case DETACH_ALL_REQ:
  396. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  397. if (!ret)
  398. smmu_state->state = DETACHED;
  399. break;
  400. case ATTACH_ALL_REQ:
  401. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL);
  402. if (!ret) {
  403. smmu_state->state = ATTACHED;
  404. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  405. }
  406. break;
  407. case DETACH_SEC_REQ:
  408. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  409. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  410. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  411. if (!ret)
  412. smmu_state->state = DETACHED_SEC;
  413. break;
  414. case ATTACH_SEC_REQ:
  415. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL);
  416. if (!ret) {
  417. smmu_state->state = ATTACHED;
  418. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  419. }
  420. break;
  421. default:
  422. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  423. DRMID(crtc), smmu_state->state,
  424. smmu_state->transition_type);
  425. ret = -EINVAL;
  426. break;
  427. }
  428. mutex_unlock(&sde_kms->secure_transition_lock);
  429. /* disable sui misr if requested, after the transition */
  430. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  431. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  432. if (ret)
  433. goto end;
  434. }
  435. end:
  436. smmu_state->sui_misr_state = NONE;
  437. smmu_state->transition_type = NONE;
  438. smmu_state->transition_error = ret ? true : false;
  439. SDE_DEBUG("crtc %d: old_state %d, new_state %d, sec_lvl %d, ret %d\n",
  440. DRMID(crtc), old_smmu_state, smmu_state->state,
  441. smmu_state->secure_level, ret);
  442. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  443. smmu_state->transition_error, smmu_state->secure_level,
  444. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  445. return ret;
  446. }
  447. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  448. struct drm_atomic_state *state)
  449. {
  450. struct drm_crtc *crtc;
  451. struct drm_crtc_state *old_crtc_state;
  452. struct drm_plane *plane;
  453. struct drm_plane_state *plane_state;
  454. struct sde_kms *sde_kms = to_sde_kms(kms);
  455. struct drm_device *dev = sde_kms->dev;
  456. int i, ops = 0, ret = 0;
  457. bool old_valid_fb = false;
  458. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  459. if (!crtc->state || !crtc->state->active)
  460. continue;
  461. /*
  462. * It is safe to assume only one active crtc,
  463. * and compatible translation modes on the
  464. * planes staged on this crtc.
  465. * otherwise validation would have failed.
  466. * For this CRTC,
  467. */
  468. /*
  469. * 1. Check if old state on the CRTC has planes
  470. * staged with valid fbs
  471. */
  472. for_each_old_plane_in_state(state, plane, plane_state, i) {
  473. if (!plane_state->crtc)
  474. continue;
  475. if (plane_state->fb) {
  476. old_valid_fb = true;
  477. break;
  478. }
  479. }
  480. /*
  481. * 2.Get the operations needed to be performed before
  482. * secure transition can be initiated.
  483. */
  484. ops = sde_crtc_get_secure_transition_ops(crtc,
  485. old_crtc_state, old_valid_fb);
  486. if (ops < 0) {
  487. SDE_ERROR("invalid secure operations %x\n", ops);
  488. return ops;
  489. }
  490. if (!ops)
  491. goto no_ops;
  492. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  493. crtc->base.id, ops, crtc->state);
  494. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  495. /* 3. Perform operations needed for secure transition */
  496. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  497. SDE_DEBUG("wait_for_transfer_done\n");
  498. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  499. }
  500. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  501. SDE_DEBUG("cleanup planes\n");
  502. drm_atomic_helper_cleanup_planes(dev, state);
  503. }
  504. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  505. SDE_DEBUG("secure ctrl\n");
  506. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  507. }
  508. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  509. SDE_DEBUG("prepare planes %d",
  510. crtc->state->plane_mask);
  511. drm_atomic_crtc_for_each_plane(plane,
  512. crtc) {
  513. const struct drm_plane_helper_funcs *funcs;
  514. plane_state = plane->state;
  515. funcs = plane->helper_private;
  516. SDE_DEBUG("psde:%d FB[%u]\n",
  517. plane->base.id,
  518. plane->fb->base.id);
  519. if (!funcs)
  520. continue;
  521. if (funcs->prepare_fb(plane, plane_state)) {
  522. ret = funcs->prepare_fb(plane,
  523. plane_state);
  524. if (ret)
  525. return ret;
  526. }
  527. }
  528. }
  529. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  530. SDE_DEBUG("secure operations completed\n");
  531. }
  532. no_ops:
  533. return 0;
  534. }
  535. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  536. unsigned int splash_buffer_size,
  537. unsigned int ramdump_base,
  538. unsigned int ramdump_buffer_size)
  539. {
  540. unsigned long pfn_start, pfn_end, pfn_idx;
  541. int ret = 0;
  542. if (!mem_addr || !splash_buffer_size) {
  543. SDE_ERROR("invalid params\n");
  544. return -EINVAL;
  545. }
  546. /* leave ramdump memory only if base address matches */
  547. if (ramdump_base == mem_addr &&
  548. ramdump_buffer_size <= splash_buffer_size) {
  549. mem_addr += ramdump_buffer_size;
  550. splash_buffer_size -= ramdump_buffer_size;
  551. }
  552. pfn_start = mem_addr >> PAGE_SHIFT;
  553. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  554. ret = memblock_free(mem_addr, splash_buffer_size);
  555. if (ret) {
  556. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  557. return ret;
  558. }
  559. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  560. free_reserved_page(pfn_to_page(pfn_idx));
  561. return ret;
  562. }
  563. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  564. struct sde_splash_mem *splash)
  565. {
  566. struct msm_mmu *mmu = NULL;
  567. int ret = 0;
  568. if (!sde_kms->aspace[0]) {
  569. SDE_ERROR("aspace not found for sde kms node\n");
  570. return -EINVAL;
  571. }
  572. mmu = sde_kms->aspace[0]->mmu;
  573. if (!mmu) {
  574. SDE_ERROR("mmu not found for aspace\n");
  575. return -EINVAL;
  576. }
  577. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  578. SDE_ERROR("invalid input params for map\n");
  579. return -EINVAL;
  580. }
  581. if (!splash->ref_cnt) {
  582. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  583. splash->splash_buf_base,
  584. splash->splash_buf_size,
  585. IOMMU_READ | IOMMU_NOEXEC);
  586. if (ret)
  587. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  588. }
  589. splash->ref_cnt++;
  590. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  591. splash->splash_buf_base,
  592. splash->splash_buf_size,
  593. splash->ref_cnt);
  594. return ret;
  595. }
  596. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  597. {
  598. int i = 0;
  599. int ret = 0;
  600. if (!sde_kms)
  601. return -EINVAL;
  602. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  603. ret = _sde_kms_splash_mem_get(sde_kms,
  604. sde_kms->splash_data.splash_display[i].splash);
  605. if (ret)
  606. return ret;
  607. }
  608. return ret;
  609. }
  610. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  611. struct sde_splash_mem *splash)
  612. {
  613. struct msm_mmu *mmu = NULL;
  614. int rc = 0;
  615. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  616. SDE_ERROR("invalid params\n");
  617. return -EINVAL;
  618. }
  619. mmu = sde_kms->aspace[0]->mmu;
  620. if (!splash || !splash->ref_cnt ||
  621. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  622. return -EINVAL;
  623. splash->ref_cnt--;
  624. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  625. splash->splash_buf_base, splash->ref_cnt);
  626. if (!splash->ref_cnt) {
  627. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  628. splash->splash_buf_size);
  629. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  630. splash->splash_buf_size, splash->ramdump_base,
  631. splash->ramdump_size);
  632. splash->splash_buf_base = 0;
  633. splash->splash_buf_size = 0;
  634. }
  635. return rc;
  636. }
  637. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  638. {
  639. int i = 0;
  640. int ret = 0;
  641. if (!sde_kms)
  642. return -EINVAL;
  643. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  644. ret = _sde_kms_splash_mem_put(sde_kms,
  645. sde_kms->splash_data.splash_display[i].splash);
  646. if (ret)
  647. return ret;
  648. }
  649. return ret;
  650. }
  651. static void sde_kms_prepare_commit(struct msm_kms *kms,
  652. struct drm_atomic_state *state)
  653. {
  654. struct sde_kms *sde_kms;
  655. struct msm_drm_private *priv;
  656. struct drm_device *dev;
  657. struct drm_encoder *encoder;
  658. struct drm_crtc *crtc;
  659. struct drm_crtc_state *crtc_state;
  660. int i, rc;
  661. if (!kms)
  662. return;
  663. sde_kms = to_sde_kms(kms);
  664. dev = sde_kms->dev;
  665. if (!dev || !dev->dev_private)
  666. return;
  667. priv = dev->dev_private;
  668. SDE_ATRACE_BEGIN("prepare_commit");
  669. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  670. if (rc < 0) {
  671. SDE_ERROR("failed to enable power resources %d\n", rc);
  672. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  673. goto end;
  674. }
  675. if (sde_kms->first_kickoff) {
  676. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  677. sde_kms->first_kickoff = false;
  678. }
  679. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  680. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  681. head) {
  682. if (encoder->crtc != crtc)
  683. continue;
  684. sde_encoder_prepare_commit(encoder);
  685. }
  686. }
  687. /*
  688. * NOTE: for secure use cases we want to apply the new HW
  689. * configuration only after completing preparation for secure
  690. * transitions prepare below if any transtions is required.
  691. */
  692. sde_kms_prepare_secure_transition(kms, state);
  693. end:
  694. SDE_ATRACE_END("prepare_commit");
  695. }
  696. static void sde_kms_commit(struct msm_kms *kms,
  697. struct drm_atomic_state *old_state)
  698. {
  699. struct sde_kms *sde_kms;
  700. struct drm_crtc *crtc;
  701. struct drm_crtc_state *old_crtc_state;
  702. int i;
  703. if (!kms || !old_state)
  704. return;
  705. sde_kms = to_sde_kms(kms);
  706. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  707. SDE_ERROR("power resource is not enabled\n");
  708. return;
  709. }
  710. SDE_ATRACE_BEGIN("sde_kms_commit");
  711. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  712. if (crtc->state->active) {
  713. SDE_EVT32(DRMID(crtc));
  714. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  715. }
  716. }
  717. SDE_ATRACE_END("sde_kms_commit");
  718. }
  719. static void _sde_kms_free_splash_region(struct sde_kms *sde_kms,
  720. struct sde_splash_display *splash_display)
  721. {
  722. if (!sde_kms || !splash_display ||
  723. !sde_kms->splash_data.num_splash_displays)
  724. return;
  725. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  726. sde_kms->splash_data.num_splash_displays--;
  727. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  728. sde_kms->splash_data.num_splash_displays);
  729. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  730. }
  731. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  732. struct drm_crtc *crtc)
  733. {
  734. struct msm_drm_private *priv;
  735. struct sde_splash_display *splash_display;
  736. int i;
  737. if (!sde_kms || !crtc)
  738. return;
  739. priv = sde_kms->dev->dev_private;
  740. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  741. return;
  742. SDE_EVT32(DRMID(crtc), crtc->state->active,
  743. sde_kms->splash_data.num_splash_displays);
  744. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  745. splash_display = &sde_kms->splash_data.splash_display[i];
  746. if (splash_display->encoder &&
  747. crtc == splash_display->encoder->crtc)
  748. break;
  749. }
  750. if (i >= MAX_DSI_DISPLAYS)
  751. return;
  752. if (splash_display->cont_splash_enabled) {
  753. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  754. splash_display, false);
  755. _sde_kms_free_splash_region(sde_kms, splash_display);
  756. }
  757. /* remove the votes if all displays are done with splash */
  758. if (!sde_kms->splash_data.num_splash_displays) {
  759. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  760. sde_power_data_bus_set_quota(&priv->phandle, i,
  761. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  762. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  763. pm_runtime_put_sync(sde_kms->dev->dev);
  764. }
  765. }
  766. static void sde_kms_complete_commit(struct msm_kms *kms,
  767. struct drm_atomic_state *old_state)
  768. {
  769. struct sde_kms *sde_kms;
  770. struct msm_drm_private *priv;
  771. struct drm_crtc *crtc;
  772. struct drm_crtc_state *old_crtc_state;
  773. struct drm_connector *connector;
  774. struct drm_connector_state *old_conn_state;
  775. int i, rc = 0;
  776. if (!kms || !old_state)
  777. return;
  778. sde_kms = to_sde_kms(kms);
  779. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  780. return;
  781. priv = sde_kms->dev->dev_private;
  782. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  783. SDE_ERROR("power resource is not enabled\n");
  784. return;
  785. }
  786. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  787. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  788. sde_crtc_complete_commit(crtc, old_crtc_state);
  789. /* complete secure transitions if any */
  790. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  791. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  792. }
  793. for_each_old_connector_in_state(old_state, connector,
  794. old_conn_state, i) {
  795. struct sde_connector *c_conn;
  796. c_conn = to_sde_connector(connector);
  797. if (!c_conn->ops.post_kickoff)
  798. continue;
  799. rc = c_conn->ops.post_kickoff(connector);
  800. if (rc) {
  801. pr_err("Connector Post kickoff failed rc=%d\n",
  802. rc);
  803. }
  804. }
  805. pm_runtime_put_sync(sde_kms->dev->dev);
  806. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  807. _sde_kms_release_splash_resource(sde_kms, crtc);
  808. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  809. SDE_ATRACE_END("sde_kms_complete_commit");
  810. }
  811. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  812. struct drm_crtc *crtc)
  813. {
  814. struct drm_encoder *encoder;
  815. struct drm_device *dev;
  816. int ret;
  817. if (!kms || !crtc || !crtc->state) {
  818. SDE_ERROR("invalid params\n");
  819. return;
  820. }
  821. dev = crtc->dev;
  822. if (!crtc->state->enable) {
  823. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  824. return;
  825. }
  826. if (!crtc->state->active) {
  827. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  828. return;
  829. }
  830. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  831. SDE_ERROR("power resource is not enabled\n");
  832. return;
  833. }
  834. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  835. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  836. if (encoder->crtc != crtc)
  837. continue;
  838. /*
  839. * Wait for post-flush if necessary to delay before
  840. * plane_cleanup. For example, wait for vsync in case of video
  841. * mode panels. This may be a no-op for command mode panels.
  842. */
  843. SDE_EVT32_VERBOSE(DRMID(crtc));
  844. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  845. if (ret && ret != -EWOULDBLOCK) {
  846. SDE_ERROR("wait for commit done returned %d\n", ret);
  847. sde_crtc_request_frame_reset(crtc);
  848. break;
  849. }
  850. sde_crtc_complete_flip(crtc, NULL);
  851. }
  852. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  853. }
  854. static void sde_kms_prepare_fence(struct msm_kms *kms,
  855. struct drm_atomic_state *old_state)
  856. {
  857. struct drm_crtc *crtc;
  858. struct drm_crtc_state *old_crtc_state;
  859. int i, rc;
  860. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  861. SDE_ERROR("invalid argument(s)\n");
  862. return;
  863. }
  864. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  865. retry:
  866. /* attempt to acquire ww mutex for connection */
  867. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  868. old_state->acquire_ctx);
  869. if (rc == -EDEADLK) {
  870. drm_modeset_backoff(old_state->acquire_ctx);
  871. goto retry;
  872. }
  873. /* old_state actually contains updated crtc pointers */
  874. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  875. if (crtc->state->active || crtc->state->active_changed)
  876. sde_crtc_prepare_commit(crtc, old_crtc_state);
  877. }
  878. SDE_ATRACE_END("sde_kms_prepare_fence");
  879. }
  880. /**
  881. * _sde_kms_get_displays - query for underlying display handles and cache them
  882. * @sde_kms: Pointer to sde kms structure
  883. * Returns: Zero on success
  884. */
  885. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  886. {
  887. int rc = -ENOMEM;
  888. if (!sde_kms) {
  889. SDE_ERROR("invalid sde kms\n");
  890. return -EINVAL;
  891. }
  892. /* dsi */
  893. sde_kms->dsi_displays = NULL;
  894. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  895. if (sde_kms->dsi_display_count) {
  896. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  897. sizeof(void *),
  898. GFP_KERNEL);
  899. if (!sde_kms->dsi_displays) {
  900. SDE_ERROR("failed to allocate dsi displays\n");
  901. goto exit_deinit_dsi;
  902. }
  903. sde_kms->dsi_display_count =
  904. dsi_display_get_active_displays(sde_kms->dsi_displays,
  905. sde_kms->dsi_display_count);
  906. }
  907. /* wb */
  908. sde_kms->wb_displays = NULL;
  909. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  910. if (sde_kms->wb_display_count) {
  911. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  912. sizeof(void *),
  913. GFP_KERNEL);
  914. if (!sde_kms->wb_displays) {
  915. SDE_ERROR("failed to allocate wb displays\n");
  916. goto exit_deinit_wb;
  917. }
  918. sde_kms->wb_display_count =
  919. wb_display_get_displays(sde_kms->wb_displays,
  920. sde_kms->wb_display_count);
  921. }
  922. /* dp */
  923. sde_kms->dp_displays = NULL;
  924. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  925. if (sde_kms->dp_display_count) {
  926. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  927. sizeof(void *), GFP_KERNEL);
  928. if (!sde_kms->dp_displays) {
  929. SDE_ERROR("failed to allocate dp displays\n");
  930. goto exit_deinit_dp;
  931. }
  932. sde_kms->dp_display_count =
  933. dp_display_get_displays(sde_kms->dp_displays,
  934. sde_kms->dp_display_count);
  935. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  936. }
  937. return 0;
  938. exit_deinit_dp:
  939. kfree(sde_kms->dp_displays);
  940. sde_kms->dp_stream_count = 0;
  941. sde_kms->dp_display_count = 0;
  942. sde_kms->dp_displays = NULL;
  943. exit_deinit_wb:
  944. kfree(sde_kms->wb_displays);
  945. sde_kms->wb_display_count = 0;
  946. sde_kms->wb_displays = NULL;
  947. exit_deinit_dsi:
  948. kfree(sde_kms->dsi_displays);
  949. sde_kms->dsi_display_count = 0;
  950. sde_kms->dsi_displays = NULL;
  951. return rc;
  952. }
  953. /**
  954. * _sde_kms_release_displays - release cache of underlying display handles
  955. * @sde_kms: Pointer to sde kms structure
  956. */
  957. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  958. {
  959. if (!sde_kms) {
  960. SDE_ERROR("invalid sde kms\n");
  961. return;
  962. }
  963. kfree(sde_kms->wb_displays);
  964. sde_kms->wb_displays = NULL;
  965. sde_kms->wb_display_count = 0;
  966. kfree(sde_kms->dsi_displays);
  967. sde_kms->dsi_displays = NULL;
  968. sde_kms->dsi_display_count = 0;
  969. }
  970. /**
  971. * _sde_kms_setup_displays - create encoders, bridges and connectors
  972. * for underlying displays
  973. * @dev: Pointer to drm device structure
  974. * @priv: Pointer to private drm device data
  975. * @sde_kms: Pointer to sde kms structure
  976. * Returns: Zero on success
  977. */
  978. static int _sde_kms_setup_displays(struct drm_device *dev,
  979. struct msm_drm_private *priv,
  980. struct sde_kms *sde_kms)
  981. {
  982. static const struct sde_connector_ops dsi_ops = {
  983. .set_info_blob = dsi_conn_set_info_blob,
  984. .detect = dsi_conn_detect,
  985. .get_modes = dsi_connector_get_modes,
  986. .pre_destroy = dsi_connector_put_modes,
  987. .mode_valid = dsi_conn_mode_valid,
  988. .get_info = dsi_display_get_info,
  989. .set_backlight = dsi_display_set_backlight,
  990. .soft_reset = dsi_display_soft_reset,
  991. .pre_kickoff = dsi_conn_pre_kickoff,
  992. .clk_ctrl = dsi_display_clk_ctrl,
  993. .set_power = dsi_display_set_power,
  994. .get_mode_info = dsi_conn_get_mode_info,
  995. .get_dst_format = dsi_display_get_dst_format,
  996. .post_kickoff = dsi_conn_post_kickoff,
  997. .check_status = dsi_display_check_status,
  998. .enable_event = dsi_conn_enable_event,
  999. .cmd_transfer = dsi_display_cmd_transfer,
  1000. .cont_splash_config = dsi_display_cont_splash_config,
  1001. .get_panel_vfp = dsi_display_get_panel_vfp,
  1002. .get_default_lms = dsi_display_get_default_lms,
  1003. };
  1004. static const struct sde_connector_ops wb_ops = {
  1005. .post_init = sde_wb_connector_post_init,
  1006. .set_info_blob = sde_wb_connector_set_info_blob,
  1007. .detect = sde_wb_connector_detect,
  1008. .get_modes = sde_wb_connector_get_modes,
  1009. .set_property = sde_wb_connector_set_property,
  1010. .get_info = sde_wb_get_info,
  1011. .soft_reset = NULL,
  1012. .get_mode_info = sde_wb_get_mode_info,
  1013. .get_dst_format = NULL,
  1014. .check_status = NULL,
  1015. .cmd_transfer = NULL,
  1016. .cont_splash_config = NULL,
  1017. .get_panel_vfp = NULL,
  1018. };
  1019. static const struct sde_connector_ops dp_ops = {
  1020. .post_init = dp_connector_post_init,
  1021. .detect = dp_connector_detect,
  1022. .get_modes = dp_connector_get_modes,
  1023. .atomic_check = dp_connector_atomic_check,
  1024. .mode_valid = dp_connector_mode_valid,
  1025. .get_info = dp_connector_get_info,
  1026. .get_mode_info = dp_connector_get_mode_info,
  1027. .post_open = dp_connector_post_open,
  1028. .check_status = NULL,
  1029. .set_colorspace = dp_connector_set_colorspace,
  1030. .config_hdr = dp_connector_config_hdr,
  1031. .cmd_transfer = NULL,
  1032. .cont_splash_config = NULL,
  1033. .get_panel_vfp = NULL,
  1034. .update_pps = dp_connector_update_pps,
  1035. };
  1036. struct msm_display_info info;
  1037. struct drm_encoder *encoder;
  1038. void *display, *connector;
  1039. int i, max_encoders;
  1040. int rc = 0;
  1041. if (!dev || !priv || !sde_kms) {
  1042. SDE_ERROR("invalid argument(s)\n");
  1043. return -EINVAL;
  1044. }
  1045. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1046. sde_kms->dp_display_count +
  1047. sde_kms->dp_stream_count;
  1048. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1049. max_encoders = ARRAY_SIZE(priv->encoders);
  1050. SDE_ERROR("capping number of displays to %d", max_encoders);
  1051. }
  1052. /* dsi */
  1053. for (i = 0; i < sde_kms->dsi_display_count &&
  1054. priv->num_encoders < max_encoders; ++i) {
  1055. display = sde_kms->dsi_displays[i];
  1056. encoder = NULL;
  1057. memset(&info, 0x0, sizeof(info));
  1058. rc = dsi_display_get_info(NULL, &info, display);
  1059. if (rc) {
  1060. SDE_ERROR("dsi get_info %d failed\n", i);
  1061. continue;
  1062. }
  1063. encoder = sde_encoder_init(dev, &info);
  1064. if (IS_ERR_OR_NULL(encoder)) {
  1065. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1066. continue;
  1067. }
  1068. rc = dsi_display_drm_bridge_init(display, encoder);
  1069. if (rc) {
  1070. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1071. sde_encoder_destroy(encoder);
  1072. continue;
  1073. }
  1074. connector = sde_connector_init(dev,
  1075. encoder,
  1076. dsi_display_get_drm_panel(display),
  1077. display,
  1078. &dsi_ops,
  1079. DRM_CONNECTOR_POLL_HPD,
  1080. DRM_MODE_CONNECTOR_DSI);
  1081. if (connector) {
  1082. priv->encoders[priv->num_encoders++] = encoder;
  1083. priv->connectors[priv->num_connectors++] = connector;
  1084. } else {
  1085. SDE_ERROR("dsi %d connector init failed\n", i);
  1086. dsi_display_drm_bridge_deinit(display);
  1087. sde_encoder_destroy(encoder);
  1088. continue;
  1089. }
  1090. }
  1091. rc = dsi_display_drm_ext_bridge_init(display,
  1092. encoder, connector);
  1093. if (rc) {
  1094. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1095. dsi_display_drm_bridge_deinit(display);
  1096. sde_encoder_destroy(encoder);
  1097. sde_connector_destroy(connector);
  1098. }
  1099. /* wb */
  1100. for (i = 0; i < sde_kms->wb_display_count &&
  1101. priv->num_encoders < max_encoders; ++i) {
  1102. display = sde_kms->wb_displays[i];
  1103. encoder = NULL;
  1104. memset(&info, 0x0, sizeof(info));
  1105. rc = sde_wb_get_info(NULL, &info, display);
  1106. if (rc) {
  1107. SDE_ERROR("wb get_info %d failed\n", i);
  1108. continue;
  1109. }
  1110. encoder = sde_encoder_init(dev, &info);
  1111. if (IS_ERR_OR_NULL(encoder)) {
  1112. SDE_ERROR("encoder init failed for wb %d\n", i);
  1113. continue;
  1114. }
  1115. rc = sde_wb_drm_init(display, encoder);
  1116. if (rc) {
  1117. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1118. sde_encoder_destroy(encoder);
  1119. continue;
  1120. }
  1121. connector = sde_connector_init(dev,
  1122. encoder,
  1123. 0,
  1124. display,
  1125. &wb_ops,
  1126. DRM_CONNECTOR_POLL_HPD,
  1127. DRM_MODE_CONNECTOR_VIRTUAL);
  1128. if (connector) {
  1129. priv->encoders[priv->num_encoders++] = encoder;
  1130. priv->connectors[priv->num_connectors++] = connector;
  1131. } else {
  1132. SDE_ERROR("wb %d connector init failed\n", i);
  1133. sde_wb_drm_deinit(display);
  1134. sde_encoder_destroy(encoder);
  1135. }
  1136. }
  1137. /* dp */
  1138. for (i = 0; i < sde_kms->dp_display_count &&
  1139. priv->num_encoders < max_encoders; ++i) {
  1140. int idx;
  1141. display = sde_kms->dp_displays[i];
  1142. encoder = NULL;
  1143. memset(&info, 0x0, sizeof(info));
  1144. rc = dp_connector_get_info(NULL, &info, display);
  1145. if (rc) {
  1146. SDE_ERROR("dp get_info %d failed\n", i);
  1147. continue;
  1148. }
  1149. encoder = sde_encoder_init(dev, &info);
  1150. if (IS_ERR_OR_NULL(encoder)) {
  1151. SDE_ERROR("dp encoder init failed %d\n", i);
  1152. continue;
  1153. }
  1154. rc = dp_drm_bridge_init(display, encoder);
  1155. if (rc) {
  1156. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1157. sde_encoder_destroy(encoder);
  1158. continue;
  1159. }
  1160. connector = sde_connector_init(dev,
  1161. encoder,
  1162. NULL,
  1163. display,
  1164. &dp_ops,
  1165. DRM_CONNECTOR_POLL_HPD,
  1166. DRM_MODE_CONNECTOR_DisplayPort);
  1167. if (connector) {
  1168. priv->encoders[priv->num_encoders++] = encoder;
  1169. priv->connectors[priv->num_connectors++] = connector;
  1170. } else {
  1171. SDE_ERROR("dp %d connector init failed\n", i);
  1172. dp_drm_bridge_deinit(display);
  1173. sde_encoder_destroy(encoder);
  1174. }
  1175. /* update display cap to MST_MODE for DP MST encoders */
  1176. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1177. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1178. info.h_tile_instance[0] = idx;
  1179. encoder = sde_encoder_init(dev, &info);
  1180. if (IS_ERR_OR_NULL(encoder)) {
  1181. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1182. continue;
  1183. }
  1184. rc = dp_mst_drm_bridge_init(display, encoder);
  1185. if (rc) {
  1186. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1187. i, rc);
  1188. sde_encoder_destroy(encoder);
  1189. continue;
  1190. }
  1191. priv->encoders[priv->num_encoders++] = encoder;
  1192. }
  1193. }
  1194. return 0;
  1195. }
  1196. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1197. {
  1198. struct msm_drm_private *priv;
  1199. int i;
  1200. if (!sde_kms) {
  1201. SDE_ERROR("invalid sde_kms\n");
  1202. return;
  1203. } else if (!sde_kms->dev) {
  1204. SDE_ERROR("invalid dev\n");
  1205. return;
  1206. } else if (!sde_kms->dev->dev_private) {
  1207. SDE_ERROR("invalid dev_private\n");
  1208. return;
  1209. }
  1210. priv = sde_kms->dev->dev_private;
  1211. for (i = 0; i < priv->num_crtcs; i++)
  1212. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1213. priv->num_crtcs = 0;
  1214. for (i = 0; i < priv->num_planes; i++)
  1215. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1216. priv->num_planes = 0;
  1217. for (i = 0; i < priv->num_connectors; i++)
  1218. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1219. priv->num_connectors = 0;
  1220. for (i = 0; i < priv->num_encoders; i++)
  1221. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1222. priv->num_encoders = 0;
  1223. _sde_kms_release_displays(sde_kms);
  1224. }
  1225. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1226. {
  1227. struct drm_device *dev;
  1228. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1229. struct drm_crtc *crtc;
  1230. struct msm_drm_private *priv;
  1231. struct sde_mdss_cfg *catalog;
  1232. int primary_planes_idx = 0, i, ret;
  1233. int max_crtc_count;
  1234. u32 sspp_id[MAX_PLANES];
  1235. u32 master_plane_id[MAX_PLANES];
  1236. u32 num_virt_planes = 0;
  1237. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1238. SDE_ERROR("invalid sde_kms\n");
  1239. return -EINVAL;
  1240. }
  1241. dev = sde_kms->dev;
  1242. priv = dev->dev_private;
  1243. catalog = sde_kms->catalog;
  1244. ret = sde_core_irq_domain_add(sde_kms);
  1245. if (ret)
  1246. goto fail_irq;
  1247. /*
  1248. * Query for underlying display drivers, and create connectors,
  1249. * bridges and encoders for them.
  1250. */
  1251. if (!_sde_kms_get_displays(sde_kms))
  1252. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1253. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1254. /* Create the planes */
  1255. for (i = 0; i < catalog->sspp_count; i++) {
  1256. bool primary = true;
  1257. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1258. || primary_planes_idx >= max_crtc_count)
  1259. primary = false;
  1260. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1261. (1UL << max_crtc_count) - 1, 0);
  1262. if (IS_ERR(plane)) {
  1263. SDE_ERROR("sde_plane_init failed\n");
  1264. ret = PTR_ERR(plane);
  1265. goto fail;
  1266. }
  1267. priv->planes[priv->num_planes++] = plane;
  1268. if (primary)
  1269. primary_planes[primary_planes_idx++] = plane;
  1270. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1271. sde_is_custom_client()) {
  1272. int priority =
  1273. catalog->sspp[i].sblk->smart_dma_priority;
  1274. sspp_id[priority - 1] = catalog->sspp[i].id;
  1275. master_plane_id[priority - 1] = plane->base.id;
  1276. num_virt_planes++;
  1277. }
  1278. }
  1279. /* Initialize smart DMA virtual planes */
  1280. for (i = 0; i < num_virt_planes; i++) {
  1281. plane = sde_plane_init(dev, sspp_id[i], false,
  1282. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1283. if (IS_ERR(plane)) {
  1284. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1285. ret = PTR_ERR(plane);
  1286. goto fail;
  1287. }
  1288. priv->planes[priv->num_planes++] = plane;
  1289. }
  1290. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1291. /* Create one CRTC per encoder */
  1292. for (i = 0; i < max_crtc_count; i++) {
  1293. crtc = sde_crtc_init(dev, primary_planes[i]);
  1294. if (IS_ERR(crtc)) {
  1295. ret = PTR_ERR(crtc);
  1296. goto fail;
  1297. }
  1298. priv->crtcs[priv->num_crtcs++] = crtc;
  1299. }
  1300. if (sde_is_custom_client()) {
  1301. /* All CRTCs are compatible with all planes */
  1302. for (i = 0; i < priv->num_planes; i++)
  1303. priv->planes[i]->possible_crtcs =
  1304. (1 << priv->num_crtcs) - 1;
  1305. }
  1306. /* All CRTCs are compatible with all encoders */
  1307. for (i = 0; i < priv->num_encoders; i++)
  1308. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1309. return 0;
  1310. fail:
  1311. _sde_kms_drm_obj_destroy(sde_kms);
  1312. fail_irq:
  1313. sde_core_irq_domain_fini(sde_kms);
  1314. return ret;
  1315. }
  1316. /**
  1317. * sde_kms_timeline_status - provides current timeline status
  1318. * This API should be called without mode config lock.
  1319. * @dev: Pointer to drm device
  1320. */
  1321. void sde_kms_timeline_status(struct drm_device *dev)
  1322. {
  1323. struct drm_crtc *crtc;
  1324. struct drm_connector *conn;
  1325. struct drm_connector_list_iter conn_iter;
  1326. if (!dev) {
  1327. SDE_ERROR("invalid drm device node\n");
  1328. return;
  1329. }
  1330. drm_for_each_crtc(crtc, dev)
  1331. sde_crtc_timeline_status(crtc);
  1332. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1333. /*
  1334. *Probably locked from last close dumping status anyway
  1335. */
  1336. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1337. drm_connector_list_iter_begin(dev, &conn_iter);
  1338. drm_for_each_connector_iter(conn, &conn_iter)
  1339. sde_conn_timeline_status(conn);
  1340. drm_connector_list_iter_end(&conn_iter);
  1341. return;
  1342. }
  1343. mutex_lock(&dev->mode_config.mutex);
  1344. drm_connector_list_iter_begin(dev, &conn_iter);
  1345. drm_for_each_connector_iter(conn, &conn_iter)
  1346. sde_conn_timeline_status(conn);
  1347. drm_connector_list_iter_end(&conn_iter);
  1348. mutex_unlock(&dev->mode_config.mutex);
  1349. }
  1350. static int sde_kms_postinit(struct msm_kms *kms)
  1351. {
  1352. struct sde_kms *sde_kms = to_sde_kms(kms);
  1353. struct drm_device *dev;
  1354. struct drm_crtc *crtc;
  1355. int rc;
  1356. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1357. SDE_ERROR("invalid sde_kms\n");
  1358. return -EINVAL;
  1359. }
  1360. dev = sde_kms->dev;
  1361. rc = _sde_debugfs_init(sde_kms);
  1362. if (rc)
  1363. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1364. drm_for_each_crtc(crtc, dev)
  1365. sde_crtc_post_init(dev, crtc);
  1366. return rc;
  1367. }
  1368. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1369. struct drm_encoder *encoder)
  1370. {
  1371. return rate;
  1372. }
  1373. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1374. struct platform_device *pdev)
  1375. {
  1376. struct drm_device *dev;
  1377. struct msm_drm_private *priv;
  1378. int i;
  1379. if (!sde_kms || !pdev)
  1380. return;
  1381. dev = sde_kms->dev;
  1382. if (!dev)
  1383. return;
  1384. priv = dev->dev_private;
  1385. if (!priv)
  1386. return;
  1387. if (sde_kms->genpd_init) {
  1388. sde_kms->genpd_init = false;
  1389. pm_genpd_remove(&sde_kms->genpd);
  1390. of_genpd_del_provider(pdev->dev.of_node);
  1391. }
  1392. if (sde_kms->hw_intr)
  1393. sde_hw_intr_destroy(sde_kms->hw_intr);
  1394. sde_kms->hw_intr = NULL;
  1395. if (sde_kms->power_event)
  1396. sde_power_handle_unregister_event(
  1397. &priv->phandle, sde_kms->power_event);
  1398. _sde_kms_release_displays(sde_kms);
  1399. _sde_kms_unmap_all_splash_regions(sde_kms);
  1400. /* safe to call these more than once during shutdown */
  1401. _sde_debugfs_destroy(sde_kms);
  1402. _sde_kms_mmu_destroy(sde_kms);
  1403. if (sde_kms->catalog) {
  1404. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1405. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1406. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1407. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1408. }
  1409. }
  1410. if (sde_kms->rm_init)
  1411. sde_rm_destroy(&sde_kms->rm);
  1412. sde_kms->rm_init = false;
  1413. if (sde_kms->catalog)
  1414. sde_hw_catalog_deinit(sde_kms->catalog);
  1415. sde_kms->catalog = NULL;
  1416. if (sde_kms->sid)
  1417. msm_iounmap(pdev, sde_kms->sid);
  1418. sde_kms->sid = NULL;
  1419. if (sde_kms->sw_fuse)
  1420. msm_iounmap(pdev, sde_kms->sw_fuse);
  1421. sde_hw_sw_fuse_destroy(sde_kms->sw_fuse);
  1422. sde_kms->sw_fuse = NULL;
  1423. if (sde_kms->reg_dma)
  1424. msm_iounmap(pdev, sde_kms->reg_dma);
  1425. sde_kms->reg_dma = NULL;
  1426. if (sde_kms->vbif[VBIF_NRT])
  1427. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1428. sde_kms->vbif[VBIF_NRT] = NULL;
  1429. if (sde_kms->vbif[VBIF_RT])
  1430. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1431. sde_kms->vbif[VBIF_RT] = NULL;
  1432. if (sde_kms->mmio)
  1433. msm_iounmap(pdev, sde_kms->mmio);
  1434. sde_kms->mmio = NULL;
  1435. sde_reg_dma_deinit();
  1436. }
  1437. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1438. {
  1439. int i;
  1440. if (!sde_kms)
  1441. return -EINVAL;
  1442. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1443. struct msm_mmu *mmu;
  1444. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1445. if (!aspace)
  1446. continue;
  1447. mmu = sde_kms->aspace[i]->mmu;
  1448. if (secure_only &&
  1449. !aspace->mmu->funcs->is_domain_secure(mmu))
  1450. continue;
  1451. /* cleanup aspace before detaching */
  1452. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1453. SDE_DEBUG("Detaching domain:%d\n", i);
  1454. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1455. ARRAY_SIZE(iommu_ports));
  1456. aspace->domain_attached = false;
  1457. }
  1458. return 0;
  1459. }
  1460. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1461. {
  1462. int i;
  1463. if (!sde_kms)
  1464. return -EINVAL;
  1465. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1466. struct msm_mmu *mmu;
  1467. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1468. if (!aspace)
  1469. continue;
  1470. mmu = sde_kms->aspace[i]->mmu;
  1471. if (secure_only &&
  1472. !aspace->mmu->funcs->is_domain_secure(mmu))
  1473. continue;
  1474. SDE_DEBUG("Attaching domain:%d\n", i);
  1475. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1476. ARRAY_SIZE(iommu_ports));
  1477. aspace->domain_attached = true;
  1478. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1479. }
  1480. return 0;
  1481. }
  1482. static void sde_kms_destroy(struct msm_kms *kms)
  1483. {
  1484. struct sde_kms *sde_kms;
  1485. struct drm_device *dev;
  1486. if (!kms) {
  1487. SDE_ERROR("invalid kms\n");
  1488. return;
  1489. }
  1490. sde_kms = to_sde_kms(kms);
  1491. dev = sde_kms->dev;
  1492. if (!dev || !dev->dev) {
  1493. SDE_ERROR("invalid device\n");
  1494. return;
  1495. }
  1496. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1497. kfree(sde_kms);
  1498. }
  1499. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  1500. struct drm_atomic_state *state)
  1501. {
  1502. struct drm_plane_state *plane_state;
  1503. int ret = 0;
  1504. plane_state = drm_atomic_get_plane_state(state, plane);
  1505. if (IS_ERR(plane_state)) {
  1506. ret = PTR_ERR(plane_state);
  1507. SDE_ERROR("error %d getting plane %d state\n",
  1508. ret, plane->base.id);
  1509. return;
  1510. }
  1511. plane->old_fb = plane->fb;
  1512. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  1513. ret = __drm_atomic_helper_disable_plane(plane, plane_state);
  1514. if (ret != 0)
  1515. SDE_ERROR("error %d disabling plane %d\n", ret,
  1516. plane->base.id);
  1517. }
  1518. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  1519. struct drm_atomic_state *state)
  1520. {
  1521. struct drm_device *dev = sde_kms->dev;
  1522. struct drm_framebuffer *fb, *tfb;
  1523. struct list_head fbs;
  1524. struct drm_plane *plane;
  1525. int ret = 0;
  1526. u32 plane_mask = 0;
  1527. INIT_LIST_HEAD(&fbs);
  1528. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  1529. if (drm_framebuffer_read_refcount(fb) > 1) {
  1530. list_move_tail(&fb->filp_head, &fbs);
  1531. drm_for_each_plane(plane, dev) {
  1532. if (plane->fb == fb) {
  1533. plane_mask |=
  1534. 1 << drm_plane_index(plane);
  1535. _sde_kms_plane_force_remove(
  1536. plane, state);
  1537. }
  1538. }
  1539. } else {
  1540. list_del_init(&fb->filp_head);
  1541. drm_framebuffer_put(fb);
  1542. }
  1543. }
  1544. if (list_empty(&fbs)) {
  1545. SDE_DEBUG("skip commit as no fb(s)\n");
  1546. drm_atomic_state_put(state);
  1547. return 0;
  1548. }
  1549. SDE_DEBUG("committing after removing all the pipes\n");
  1550. ret = drm_atomic_commit(state);
  1551. if (ret) {
  1552. /*
  1553. * move the fbs back to original list, so it would be
  1554. * handled during drm_release
  1555. */
  1556. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  1557. list_move_tail(&fb->filp_head, &file->fbs);
  1558. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  1559. goto end;
  1560. }
  1561. while (!list_empty(&fbs)) {
  1562. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  1563. list_del_init(&fb->filp_head);
  1564. drm_framebuffer_put(fb);
  1565. }
  1566. end:
  1567. return ret;
  1568. }
  1569. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  1570. {
  1571. struct sde_kms *sde_kms = to_sde_kms(kms);
  1572. struct drm_device *dev = sde_kms->dev;
  1573. struct msm_drm_private *priv = dev->dev_private;
  1574. unsigned int i;
  1575. struct drm_atomic_state *state = NULL;
  1576. struct drm_modeset_acquire_ctx ctx;
  1577. int ret = 0;
  1578. /* cancel pending flip event */
  1579. for (i = 0; i < priv->num_crtcs; i++)
  1580. sde_crtc_complete_flip(priv->crtcs[i], file);
  1581. drm_modeset_acquire_init(&ctx, 0);
  1582. retry:
  1583. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1584. if (ret == -EDEADLK) {
  1585. drm_modeset_backoff(&ctx);
  1586. goto retry;
  1587. } else if (WARN_ON(ret)) {
  1588. goto end;
  1589. }
  1590. state = drm_atomic_state_alloc(dev);
  1591. if (!state) {
  1592. ret = -ENOMEM;
  1593. goto end;
  1594. }
  1595. state->acquire_ctx = &ctx;
  1596. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1597. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  1598. if (ret != -EDEADLK)
  1599. break;
  1600. drm_atomic_state_clear(state);
  1601. drm_modeset_backoff(&ctx);
  1602. }
  1603. end:
  1604. if (state)
  1605. drm_atomic_state_put(state);
  1606. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  1607. drm_modeset_drop_locks(&ctx);
  1608. drm_modeset_acquire_fini(&ctx);
  1609. }
  1610. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1611. struct drm_atomic_state *state)
  1612. {
  1613. struct drm_device *dev = sde_kms->dev;
  1614. struct drm_plane *plane;
  1615. struct drm_plane_state *plane_state;
  1616. struct drm_crtc *crtc;
  1617. struct drm_crtc_state *crtc_state;
  1618. struct drm_connector *conn;
  1619. struct drm_connector_state *conn_state;
  1620. struct drm_connector_list_iter conn_iter;
  1621. int ret = 0;
  1622. drm_for_each_plane(plane, dev) {
  1623. plane_state = drm_atomic_get_plane_state(state, plane);
  1624. if (IS_ERR(plane_state)) {
  1625. ret = PTR_ERR(plane_state);
  1626. SDE_ERROR("error %d getting plane %d state\n",
  1627. ret, DRMID(plane));
  1628. return ret;
  1629. }
  1630. ret = sde_plane_helper_reset_custom_properties(plane,
  1631. plane_state);
  1632. if (ret) {
  1633. SDE_ERROR("error %d resetting plane props %d\n",
  1634. ret, DRMID(plane));
  1635. return ret;
  1636. }
  1637. }
  1638. drm_for_each_crtc(crtc, dev) {
  1639. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1640. if (IS_ERR(crtc_state)) {
  1641. ret = PTR_ERR(crtc_state);
  1642. SDE_ERROR("error %d getting crtc %d state\n",
  1643. ret, DRMID(crtc));
  1644. return ret;
  1645. }
  1646. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1647. if (ret) {
  1648. SDE_ERROR("error %d resetting crtc props %d\n",
  1649. ret, DRMID(crtc));
  1650. return ret;
  1651. }
  1652. }
  1653. drm_connector_list_iter_begin(dev, &conn_iter);
  1654. drm_for_each_connector_iter(conn, &conn_iter) {
  1655. conn_state = drm_atomic_get_connector_state(state, conn);
  1656. if (IS_ERR(conn_state)) {
  1657. ret = PTR_ERR(conn_state);
  1658. SDE_ERROR("error %d getting connector %d state\n",
  1659. ret, DRMID(conn));
  1660. return ret;
  1661. }
  1662. ret = sde_connector_helper_reset_custom_properties(conn,
  1663. conn_state);
  1664. if (ret) {
  1665. SDE_ERROR("error %d resetting connector props %d\n",
  1666. ret, DRMID(conn));
  1667. return ret;
  1668. }
  1669. }
  1670. drm_connector_list_iter_end(&conn_iter);
  1671. return ret;
  1672. }
  1673. static void sde_kms_lastclose(struct msm_kms *kms,
  1674. struct drm_modeset_acquire_ctx *ctx)
  1675. {
  1676. struct sde_kms *sde_kms;
  1677. struct drm_device *dev;
  1678. struct drm_atomic_state *state;
  1679. int ret, i;
  1680. if (!kms) {
  1681. SDE_ERROR("invalid argument\n");
  1682. return;
  1683. }
  1684. sde_kms = to_sde_kms(kms);
  1685. dev = sde_kms->dev;
  1686. state = drm_atomic_state_alloc(dev);
  1687. if (!state)
  1688. return;
  1689. state->acquire_ctx = ctx;
  1690. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1691. /* add reset of custom properties to the state */
  1692. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1693. if (ret)
  1694. break;
  1695. ret = drm_atomic_commit(state);
  1696. if (ret != -EDEADLK)
  1697. break;
  1698. drm_atomic_state_clear(state);
  1699. drm_modeset_backoff(ctx);
  1700. SDE_DEBUG("deadlock backoff on attempt %d\n", i);
  1701. }
  1702. if (ret)
  1703. SDE_ERROR("failed to run last close: %d\n", ret);
  1704. drm_atomic_state_put(state);
  1705. }
  1706. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1707. struct drm_atomic_state *state)
  1708. {
  1709. struct sde_kms *sde_kms;
  1710. struct drm_device *dev;
  1711. struct drm_crtc *crtc;
  1712. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1713. struct drm_crtc_state *crtc_state;
  1714. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1715. bool sec_session = false, global_sec_session = false;
  1716. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1717. int i;
  1718. if (!kms || !state) {
  1719. return -EINVAL;
  1720. SDE_ERROR("invalid arguments\n");
  1721. }
  1722. sde_kms = to_sde_kms(kms);
  1723. dev = sde_kms->dev;
  1724. /* iterate state object for active secure/non-secure crtc */
  1725. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1726. if (!crtc_state->active)
  1727. continue;
  1728. active_crtc_cnt++;
  1729. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1730. &fb_sec, &fb_sec_dir);
  1731. if (fb_sec_dir)
  1732. sec_session = true;
  1733. cur_crtc = crtc;
  1734. }
  1735. /* iterate global list for active and secure/non-secure crtc */
  1736. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1737. if (!crtc->state->active)
  1738. continue;
  1739. global_active_crtc_cnt++;
  1740. /* update only when crtc is not the same as current crtc */
  1741. if (crtc != cur_crtc) {
  1742. fb_ns = fb_sec = fb_sec_dir = 0;
  1743. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1744. &fb_sec, &fb_sec_dir);
  1745. if (fb_sec_dir)
  1746. global_sec_session = true;
  1747. global_crtc = crtc;
  1748. }
  1749. }
  1750. if (!global_sec_session && !sec_session)
  1751. return 0;
  1752. /*
  1753. * - fail crtc commit, if secure-camera/secure-ui session is
  1754. * in-progress in any other display
  1755. * - fail secure-camera/secure-ui crtc commit, if any other display
  1756. * session is in-progress
  1757. */
  1758. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1759. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1760. SDE_ERROR(
  1761. "crtc%d secure check failed global_active:%d active:%d\n",
  1762. cur_crtc ? cur_crtc->base.id : -1,
  1763. global_active_crtc_cnt, active_crtc_cnt);
  1764. return -EPERM;
  1765. /*
  1766. * As only one crtc is allowed during secure session, the crtc
  1767. * in this commit should match with the global crtc
  1768. */
  1769. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1770. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1771. cur_crtc->base.id, sec_session,
  1772. global_crtc->base.id, global_sec_session);
  1773. return -EPERM;
  1774. }
  1775. return 0;
  1776. }
  1777. static int sde_kms_atomic_check(struct msm_kms *kms,
  1778. struct drm_atomic_state *state)
  1779. {
  1780. struct sde_kms *sde_kms;
  1781. struct drm_device *dev;
  1782. int ret;
  1783. if (!kms || !state)
  1784. return -EINVAL;
  1785. sde_kms = to_sde_kms(kms);
  1786. dev = sde_kms->dev;
  1787. SDE_ATRACE_BEGIN("atomic_check");
  1788. if (sde_kms_is_suspend_blocked(dev)) {
  1789. SDE_DEBUG("suspended, skip atomic_check\n");
  1790. ret = -EBUSY;
  1791. goto end;
  1792. }
  1793. ret = drm_atomic_helper_check(dev, state);
  1794. if (ret)
  1795. goto end;
  1796. /*
  1797. * Check if any secure transition(moving CRTC between secure and
  1798. * non-secure state and vice-versa) is allowed or not. when moving
  1799. * to secure state, planes with fb_mode set to dir_translated only can
  1800. * be staged on the CRTC, and only one CRTC can be active during
  1801. * Secure state
  1802. */
  1803. ret = sde_kms_check_secure_transition(kms, state);
  1804. end:
  1805. SDE_ATRACE_END("atomic_check");
  1806. return ret;
  1807. }
  1808. static struct msm_gem_address_space*
  1809. _sde_kms_get_address_space(struct msm_kms *kms,
  1810. unsigned int domain)
  1811. {
  1812. struct sde_kms *sde_kms;
  1813. if (!kms) {
  1814. SDE_ERROR("invalid kms\n");
  1815. return NULL;
  1816. }
  1817. sde_kms = to_sde_kms(kms);
  1818. if (!sde_kms) {
  1819. SDE_ERROR("invalid sde_kms\n");
  1820. return NULL;
  1821. }
  1822. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1823. return NULL;
  1824. return (sde_kms->aspace[domain] &&
  1825. sde_kms->aspace[domain]->domain_attached) ?
  1826. sde_kms->aspace[domain] : NULL;
  1827. }
  1828. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1829. unsigned int domain)
  1830. {
  1831. struct msm_gem_address_space *aspace =
  1832. _sde_kms_get_address_space(kms, domain);
  1833. return (aspace && aspace->domain_attached) ?
  1834. msm_gem_get_aspace_device(aspace) : NULL;
  1835. }
  1836. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1837. {
  1838. struct drm_device *dev = NULL;
  1839. struct sde_kms *sde_kms = NULL;
  1840. struct drm_connector *connector = NULL;
  1841. struct drm_connector_list_iter conn_iter;
  1842. struct sde_connector *sde_conn = NULL;
  1843. if (!kms) {
  1844. SDE_ERROR("invalid kms\n");
  1845. return;
  1846. }
  1847. sde_kms = to_sde_kms(kms);
  1848. dev = sde_kms->dev;
  1849. if (!dev) {
  1850. SDE_ERROR("invalid device\n");
  1851. return;
  1852. }
  1853. if (!dev->mode_config.poll_enabled)
  1854. return;
  1855. mutex_lock(&dev->mode_config.mutex);
  1856. drm_connector_list_iter_begin(dev, &conn_iter);
  1857. drm_for_each_connector_iter(connector, &conn_iter) {
  1858. /* Only handle HPD capable connectors. */
  1859. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1860. continue;
  1861. sde_conn = to_sde_connector(connector);
  1862. if (sde_conn->ops.post_open)
  1863. sde_conn->ops.post_open(&sde_conn->base,
  1864. sde_conn->display);
  1865. }
  1866. drm_connector_list_iter_end(&conn_iter);
  1867. mutex_unlock(&dev->mode_config.mutex);
  1868. }
  1869. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1870. struct sde_splash_display *splash_display,
  1871. struct drm_crtc *crtc)
  1872. {
  1873. struct msm_drm_private *priv;
  1874. struct drm_plane *plane;
  1875. struct sde_splash_mem *splash;
  1876. enum sde_sspp plane_id;
  1877. bool is_virtual;
  1878. int i, j;
  1879. if (!sde_kms || !splash_display || !crtc) {
  1880. SDE_ERROR("invalid input args\n");
  1881. return -EINVAL;
  1882. }
  1883. priv = sde_kms->dev->dev_private;
  1884. for (i = 0; i < priv->num_planes; i++) {
  1885. plane = priv->planes[i];
  1886. plane_id = sde_plane_pipe(plane);
  1887. is_virtual = is_sde_plane_virtual(plane);
  1888. splash = splash_display->splash;
  1889. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1890. if ((plane_id != splash_display->pipes[j].sspp) ||
  1891. (splash_display->pipes[j].is_virtual
  1892. != is_virtual))
  1893. continue;
  1894. if (splash && sde_plane_validate_src_addr(plane,
  1895. splash->splash_buf_base,
  1896. splash->splash_buf_size)) {
  1897. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1898. plane_id, crtc->base.id);
  1899. }
  1900. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1901. crtc->base.id, plane_id, is_virtual);
  1902. }
  1903. }
  1904. return 0;
  1905. }
  1906. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1907. {
  1908. void *display;
  1909. struct dsi_display *dsi_display;
  1910. struct msm_display_info info;
  1911. struct drm_encoder *encoder = NULL;
  1912. struct drm_crtc *crtc = NULL;
  1913. int i, rc = 0;
  1914. struct drm_display_mode *drm_mode = NULL;
  1915. struct drm_device *dev;
  1916. struct msm_drm_private *priv;
  1917. struct sde_kms *sde_kms;
  1918. struct drm_connector_list_iter conn_iter;
  1919. struct drm_connector *connector = NULL;
  1920. struct sde_connector *sde_conn = NULL;
  1921. struct sde_splash_display *splash_display;
  1922. if (!kms) {
  1923. SDE_ERROR("invalid kms\n");
  1924. return -EINVAL;
  1925. }
  1926. sde_kms = to_sde_kms(kms);
  1927. dev = sde_kms->dev;
  1928. if (!dev) {
  1929. SDE_ERROR("invalid device\n");
  1930. return -EINVAL;
  1931. }
  1932. if (!sde_kms->splash_data.num_splash_regions ||
  1933. !sde_kms->splash_data.num_splash_displays) {
  1934. DRM_INFO("cont_splash feature not enabled\n");
  1935. return rc;
  1936. }
  1937. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1938. sde_kms->splash_data.num_splash_displays,
  1939. sde_kms->dsi_display_count);
  1940. /* dsi */
  1941. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1942. display = sde_kms->dsi_displays[i];
  1943. dsi_display = (struct dsi_display *)display;
  1944. splash_display = &sde_kms->splash_data.splash_display[i];
  1945. if (!splash_display->cont_splash_enabled) {
  1946. SDE_DEBUG("display->name = %s splash not enabled\n",
  1947. dsi_display->name);
  1948. continue;
  1949. }
  1950. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1951. if (dsi_display->bridge->base.encoder) {
  1952. encoder = dsi_display->bridge->base.encoder;
  1953. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1954. }
  1955. memset(&info, 0x0, sizeof(info));
  1956. rc = dsi_display_get_info(NULL, &info, display);
  1957. if (rc) {
  1958. SDE_ERROR("dsi get_info %d failed\n", i);
  1959. encoder = NULL;
  1960. continue;
  1961. }
  1962. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1963. ((info.is_connected) ? "true" : "false"),
  1964. info.display_type);
  1965. if (!encoder) {
  1966. SDE_ERROR("encoder not initialized\n");
  1967. return -EINVAL;
  1968. }
  1969. priv = sde_kms->dev->dev_private;
  1970. encoder->crtc = priv->crtcs[i];
  1971. crtc = encoder->crtc;
  1972. splash_display->encoder = encoder;
  1973. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1974. i, crtc->base.id, encoder->base.id);
  1975. mutex_lock(&dev->mode_config.mutex);
  1976. drm_connector_list_iter_begin(dev, &conn_iter);
  1977. drm_for_each_connector_iter(connector, &conn_iter) {
  1978. /**
  1979. * SDE_KMS doesn't attach more than one encoder to
  1980. * a DSI connector. So it is safe to check only with
  1981. * the first encoder entry. Revisit this logic if we
  1982. * ever have to support continuous splash for
  1983. * external displays in MST configuration.
  1984. */
  1985. if (connector->encoder_ids[0] == encoder->base.id)
  1986. break;
  1987. }
  1988. drm_connector_list_iter_end(&conn_iter);
  1989. if (!connector) {
  1990. SDE_ERROR("connector not initialized\n");
  1991. mutex_unlock(&dev->mode_config.mutex);
  1992. return -EINVAL;
  1993. }
  1994. if (connector->funcs->fill_modes) {
  1995. connector->funcs->fill_modes(connector,
  1996. dev->mode_config.max_width,
  1997. dev->mode_config.max_height);
  1998. } else {
  1999. SDE_ERROR("fill_modes api not defined\n");
  2000. mutex_unlock(&dev->mode_config.mutex);
  2001. return -EINVAL;
  2002. }
  2003. mutex_unlock(&dev->mode_config.mutex);
  2004. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2005. /* currently consider modes[0] as the preferred mode */
  2006. drm_mode = list_first_entry(&connector->modes,
  2007. struct drm_display_mode, head);
  2008. SDE_DEBUG("drm_mode->name = %s, id=%d, type=0x%x, flags=0x%x\n",
  2009. drm_mode->name, drm_mode->base.id,
  2010. drm_mode->type, drm_mode->flags);
  2011. /* Update CRTC drm structure */
  2012. crtc->state->active = true;
  2013. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2014. if (rc) {
  2015. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2016. return rc;
  2017. }
  2018. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2019. drm_mode_copy(&crtc->mode, drm_mode);
  2020. /* Update encoder structure */
  2021. sde_encoder_update_caps_for_cont_splash(encoder,
  2022. splash_display, true);
  2023. sde_crtc_update_cont_splash_settings(crtc);
  2024. sde_conn = to_sde_connector(connector);
  2025. if (sde_conn && sde_conn->ops.cont_splash_config)
  2026. sde_conn->ops.cont_splash_config(sde_conn->display);
  2027. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2028. splash_display, crtc);
  2029. if (rc) {
  2030. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2031. return rc;
  2032. }
  2033. }
  2034. return rc;
  2035. }
  2036. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2037. {
  2038. struct sde_kms *sde_kms;
  2039. if (!kms) {
  2040. SDE_ERROR("invalid kms\n");
  2041. return false;
  2042. }
  2043. sde_kms = to_sde_kms(kms);
  2044. return sde_kms->splash_data.num_splash_displays;
  2045. }
  2046. static void _sde_kms_null_commit(struct drm_device *dev,
  2047. struct drm_encoder *enc)
  2048. {
  2049. struct drm_modeset_acquire_ctx ctx;
  2050. struct drm_connector *conn = NULL;
  2051. struct drm_connector *tmp_conn = NULL;
  2052. struct drm_connector_list_iter conn_iter;
  2053. struct drm_atomic_state *state = NULL;
  2054. struct drm_crtc_state *crtc_state = NULL;
  2055. struct drm_connector_state *conn_state = NULL;
  2056. int retry_cnt = 0;
  2057. int ret = 0;
  2058. drm_modeset_acquire_init(&ctx, 0);
  2059. retry:
  2060. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2061. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2062. drm_modeset_backoff(&ctx);
  2063. retry_cnt++;
  2064. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2065. goto retry;
  2066. } else if (WARN_ON(ret)) {
  2067. goto end;
  2068. }
  2069. state = drm_atomic_state_alloc(dev);
  2070. if (!state) {
  2071. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2072. goto end;
  2073. }
  2074. state->acquire_ctx = &ctx;
  2075. drm_connector_list_iter_begin(dev, &conn_iter);
  2076. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2077. if (enc == tmp_conn->state->best_encoder) {
  2078. conn = tmp_conn;
  2079. break;
  2080. }
  2081. }
  2082. drm_connector_list_iter_end(&conn_iter);
  2083. if (!conn) {
  2084. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2085. goto end;
  2086. }
  2087. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2088. conn_state = drm_atomic_get_connector_state(state, conn);
  2089. if (IS_ERR(conn_state)) {
  2090. SDE_ERROR("error %d getting connector %d state\n",
  2091. ret, DRMID(conn));
  2092. goto end;
  2093. }
  2094. crtc_state->active = true;
  2095. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2096. if (ret)
  2097. SDE_ERROR("error %d setting the crtc\n", ret);
  2098. ret = drm_atomic_commit(state);
  2099. if (ret)
  2100. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2101. end:
  2102. if (state)
  2103. drm_atomic_state_put(state);
  2104. drm_modeset_drop_locks(&ctx);
  2105. drm_modeset_acquire_fini(&ctx);
  2106. }
  2107. static int sde_kms_pm_suspend(struct device *dev)
  2108. {
  2109. struct drm_device *ddev;
  2110. struct drm_modeset_acquire_ctx ctx;
  2111. struct drm_connector *conn;
  2112. struct drm_encoder *enc;
  2113. struct drm_connector_list_iter conn_iter;
  2114. struct drm_atomic_state *state = NULL;
  2115. struct sde_kms *sde_kms;
  2116. int ret = 0, num_crtcs = 0;
  2117. if (!dev)
  2118. return -EINVAL;
  2119. ddev = dev_get_drvdata(dev);
  2120. if (!ddev || !ddev_to_msm_kms(ddev))
  2121. return -EINVAL;
  2122. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2123. SDE_EVT32(0);
  2124. /* disable hot-plug polling */
  2125. drm_kms_helper_poll_disable(ddev);
  2126. /* if a display stuck in CS trigger a null commit to complete handoff */
  2127. drm_for_each_encoder(enc, ddev) {
  2128. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2129. _sde_kms_null_commit(ddev, enc);
  2130. }
  2131. /* acquire modeset lock(s) */
  2132. drm_modeset_acquire_init(&ctx, 0);
  2133. retry:
  2134. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2135. if (ret)
  2136. goto unlock;
  2137. /* save current state for resume */
  2138. if (sde_kms->suspend_state)
  2139. drm_atomic_state_put(sde_kms->suspend_state);
  2140. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2141. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2142. ret = PTR_ERR(sde_kms->suspend_state);
  2143. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2144. sde_kms->suspend_state = NULL;
  2145. goto unlock;
  2146. }
  2147. /* create atomic state to disable all CRTCs */
  2148. state = drm_atomic_state_alloc(ddev);
  2149. if (!state) {
  2150. ret = -ENOMEM;
  2151. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2152. goto unlock;
  2153. }
  2154. state->acquire_ctx = &ctx;
  2155. drm_connector_list_iter_begin(ddev, &conn_iter);
  2156. drm_for_each_connector_iter(conn, &conn_iter) {
  2157. struct drm_crtc_state *crtc_state;
  2158. uint64_t lp;
  2159. if (!conn->state || !conn->state->crtc ||
  2160. conn->dpms != DRM_MODE_DPMS_ON)
  2161. continue;
  2162. lp = sde_connector_get_lp(conn);
  2163. if (lp == SDE_MODE_DPMS_LP1) {
  2164. /* transition LP1->LP2 on pm suspend */
  2165. ret = sde_connector_set_property_for_commit(conn, state,
  2166. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2167. if (ret) {
  2168. DRM_ERROR("failed to set lp2 for conn %d\n",
  2169. conn->base.id);
  2170. drm_connector_list_iter_end(&conn_iter);
  2171. goto unlock;
  2172. }
  2173. }
  2174. if (lp != SDE_MODE_DPMS_LP2) {
  2175. /* force CRTC to be inactive */
  2176. crtc_state = drm_atomic_get_crtc_state(state,
  2177. conn->state->crtc);
  2178. if (IS_ERR_OR_NULL(crtc_state)) {
  2179. DRM_ERROR("failed to get crtc %d state\n",
  2180. conn->state->crtc->base.id);
  2181. drm_connector_list_iter_end(&conn_iter);
  2182. goto unlock;
  2183. }
  2184. if (lp != SDE_MODE_DPMS_LP1)
  2185. crtc_state->active = false;
  2186. ++num_crtcs;
  2187. }
  2188. }
  2189. drm_connector_list_iter_end(&conn_iter);
  2190. /* check for nothing to do */
  2191. if (num_crtcs == 0) {
  2192. DRM_DEBUG("all crtcs are already in the off state\n");
  2193. sde_kms->suspend_block = true;
  2194. goto unlock;
  2195. }
  2196. /* commit the "disable all" state */
  2197. ret = drm_atomic_commit(state);
  2198. if (ret < 0) {
  2199. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2200. goto unlock;
  2201. }
  2202. sde_kms->suspend_block = true;
  2203. drm_connector_list_iter_begin(ddev, &conn_iter);
  2204. drm_for_each_connector_iter(conn, &conn_iter) {
  2205. uint64_t lp;
  2206. lp = sde_connector_get_lp(conn);
  2207. if (lp != SDE_MODE_DPMS_LP2)
  2208. continue;
  2209. ret = sde_encoder_wait_for_event(conn->encoder,
  2210. MSM_ENC_TX_COMPLETE);
  2211. if (ret && ret != -EWOULDBLOCK)
  2212. SDE_ERROR(
  2213. "[enc: %d] wait for commit done returned %d\n",
  2214. conn->encoder->base.id, ret);
  2215. else if (!ret)
  2216. sde_encoder_idle_request(conn->encoder);
  2217. }
  2218. drm_connector_list_iter_end(&conn_iter);
  2219. unlock:
  2220. if (state) {
  2221. drm_atomic_state_put(state);
  2222. state = NULL;
  2223. }
  2224. if (ret == -EDEADLK) {
  2225. drm_modeset_backoff(&ctx);
  2226. goto retry;
  2227. }
  2228. drm_modeset_drop_locks(&ctx);
  2229. drm_modeset_acquire_fini(&ctx);
  2230. return ret;
  2231. }
  2232. static int sde_kms_pm_resume(struct device *dev)
  2233. {
  2234. struct drm_device *ddev;
  2235. struct sde_kms *sde_kms;
  2236. struct drm_modeset_acquire_ctx ctx;
  2237. int ret, i;
  2238. if (!dev)
  2239. return -EINVAL;
  2240. ddev = dev_get_drvdata(dev);
  2241. if (!ddev || !ddev_to_msm_kms(ddev))
  2242. return -EINVAL;
  2243. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2244. SDE_EVT32(sde_kms->suspend_state != NULL);
  2245. drm_mode_config_reset(ddev);
  2246. drm_modeset_acquire_init(&ctx, 0);
  2247. retry:
  2248. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2249. if (ret == -EDEADLK) {
  2250. drm_modeset_backoff(&ctx);
  2251. goto retry;
  2252. } else if (WARN_ON(ret)) {
  2253. goto end;
  2254. }
  2255. sde_kms->suspend_block = false;
  2256. if (sde_kms->suspend_state) {
  2257. sde_kms->suspend_state->acquire_ctx = &ctx;
  2258. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2259. ret = drm_atomic_helper_commit_duplicated_state(
  2260. sde_kms->suspend_state, &ctx);
  2261. if (ret != -EDEADLK)
  2262. break;
  2263. drm_modeset_backoff(&ctx);
  2264. }
  2265. if (ret < 0)
  2266. DRM_ERROR("failed to restore state, %d\n", ret);
  2267. drm_atomic_state_put(sde_kms->suspend_state);
  2268. sde_kms->suspend_state = NULL;
  2269. }
  2270. end:
  2271. drm_modeset_drop_locks(&ctx);
  2272. drm_modeset_acquire_fini(&ctx);
  2273. /* enable hot-plug polling */
  2274. drm_kms_helper_poll_enable(ddev);
  2275. return 0;
  2276. }
  2277. static const struct msm_kms_funcs kms_funcs = {
  2278. .hw_init = sde_kms_hw_init,
  2279. .postinit = sde_kms_postinit,
  2280. .irq_preinstall = sde_irq_preinstall,
  2281. .irq_postinstall = sde_irq_postinstall,
  2282. .irq_uninstall = sde_irq_uninstall,
  2283. .irq = sde_irq,
  2284. .preclose = sde_kms_preclose,
  2285. .lastclose = sde_kms_lastclose,
  2286. .prepare_fence = sde_kms_prepare_fence,
  2287. .prepare_commit = sde_kms_prepare_commit,
  2288. .commit = sde_kms_commit,
  2289. .complete_commit = sde_kms_complete_commit,
  2290. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2291. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2292. .enable_vblank = sde_kms_enable_vblank,
  2293. .disable_vblank = sde_kms_disable_vblank,
  2294. .check_modified_format = sde_format_check_modified_format,
  2295. .atomic_check = sde_kms_atomic_check,
  2296. .get_format = sde_get_msm_format,
  2297. .round_pixclk = sde_kms_round_pixclk,
  2298. .pm_suspend = sde_kms_pm_suspend,
  2299. .pm_resume = sde_kms_pm_resume,
  2300. .destroy = sde_kms_destroy,
  2301. .cont_splash_config = sde_kms_cont_splash_config,
  2302. .register_events = _sde_kms_register_events,
  2303. .get_address_space = _sde_kms_get_address_space,
  2304. .get_address_space_device = _sde_kms_get_address_space_device,
  2305. .postopen = _sde_kms_post_open,
  2306. .check_for_splash = sde_kms_check_for_splash,
  2307. };
  2308. /* the caller api needs to turn on clock before calling it */
  2309. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2310. {
  2311. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2312. }
  2313. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2314. {
  2315. int i;
  2316. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2317. if (!sde_kms->aspace[i])
  2318. continue;
  2319. msm_gem_address_space_put(sde_kms->aspace[i]);
  2320. sde_kms->aspace[i] = NULL;
  2321. }
  2322. return 0;
  2323. }
  2324. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2325. {
  2326. struct msm_mmu *mmu;
  2327. int i, ret;
  2328. int early_map = 0;
  2329. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2330. struct msm_gem_address_space *aspace;
  2331. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2332. if (IS_ERR(mmu)) {
  2333. ret = PTR_ERR(mmu);
  2334. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2335. i, ret);
  2336. continue;
  2337. }
  2338. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2339. mmu, "sde");
  2340. if (IS_ERR(aspace)) {
  2341. ret = PTR_ERR(aspace);
  2342. goto fail;
  2343. }
  2344. sde_kms->aspace[i] = aspace;
  2345. aspace->domain_attached = true;
  2346. /* Mapping splash memory block */
  2347. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2348. sde_kms->splash_data.num_splash_regions) {
  2349. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2350. if (ret) {
  2351. SDE_ERROR("failed to map ret:%d\n", ret);
  2352. goto fail;
  2353. }
  2354. }
  2355. /*
  2356. * disable early-map which would have been enabled during
  2357. * bootup by smmu through the device-tree hint for cont-spash
  2358. */
  2359. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2360. &early_map);
  2361. if (ret) {
  2362. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2363. ret, early_map);
  2364. goto early_map_fail;
  2365. }
  2366. }
  2367. return 0;
  2368. early_map_fail:
  2369. _sde_kms_unmap_all_splash_regions(sde_kms);
  2370. fail:
  2371. mmu->funcs->destroy(mmu);
  2372. _sde_kms_mmu_destroy(sde_kms);
  2373. return ret;
  2374. }
  2375. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2376. {
  2377. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2378. return;
  2379. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2380. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2381. sde_kms->catalog);
  2382. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2383. }
  2384. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2385. {
  2386. struct sde_vbif_set_qos_params qos_params;
  2387. struct sde_mdss_cfg *catalog;
  2388. if (!sde_kms->catalog)
  2389. return;
  2390. catalog = sde_kms->catalog;
  2391. memset(&qos_params, 0, sizeof(qos_params));
  2392. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2393. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2394. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2395. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2396. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2397. }
  2398. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2399. {
  2400. struct sde_kms *sde_kms = usr;
  2401. struct msm_kms *msm_kms;
  2402. msm_kms = &sde_kms->base;
  2403. if (!sde_kms)
  2404. return;
  2405. SDE_DEBUG("event_type:%d\n", event_type);
  2406. SDE_EVT32_VERBOSE(event_type);
  2407. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2408. sde_irq_update(msm_kms, true);
  2409. sde_vbif_init_memtypes(sde_kms);
  2410. sde_kms_init_shared_hw(sde_kms);
  2411. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2412. sde_kms->first_kickoff = true;
  2413. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2414. sde_irq_update(msm_kms, false);
  2415. sde_kms->first_kickoff = false;
  2416. }
  2417. }
  2418. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2419. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2420. {
  2421. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2422. int rc = -EINVAL;
  2423. SDE_DEBUG("\n");
  2424. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2425. if (rc > 0)
  2426. rc = 0;
  2427. SDE_EVT32(rc, genpd->device_count);
  2428. return rc;
  2429. }
  2430. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2431. {
  2432. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2433. SDE_DEBUG("\n");
  2434. pm_runtime_put_sync(sde_kms->dev->dev);
  2435. SDE_EVT32(genpd->device_count);
  2436. return 0;
  2437. }
  2438. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2439. {
  2440. int i = 0;
  2441. int ret = 0;
  2442. struct device_node *parent, *node, *node1;
  2443. struct resource r, r1;
  2444. const char *node_name = "cont_splash_region";
  2445. struct sde_splash_mem *mem;
  2446. bool share_splash_mem = false;
  2447. int num_displays, num_regions;
  2448. struct sde_splash_display *splash_display;
  2449. if (!data)
  2450. return -EINVAL;
  2451. memset(data, 0, sizeof(*data));
  2452. parent = of_find_node_by_path("/reserved-memory");
  2453. if (!parent) {
  2454. SDE_ERROR("failed to find reserved-memory node\n");
  2455. return -EINVAL;
  2456. }
  2457. node = of_find_node_by_name(parent, node_name);
  2458. if (!node) {
  2459. SDE_DEBUG("failed to find node %s\n", node_name);
  2460. return -EINVAL;
  2461. }
  2462. node1 = of_find_node_by_name(parent, "disp_rdump_region");
  2463. if (!node1)
  2464. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2465. /**
  2466. * Support sharing a single splash memory for all the built in displays
  2467. * and also independent splash region per displays. Incase of
  2468. * independent splash region for each connected display, dtsi node of
  2469. * cont_splash_region should be collection of all memory regions
  2470. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2471. */
  2472. num_displays = dsi_display_get_num_of_displays();
  2473. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2474. data->num_splash_displays = num_displays;
  2475. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2476. if (num_displays > num_regions) {
  2477. share_splash_mem = true;
  2478. pr_info(":%d displays share same splash buf\n", num_displays);
  2479. }
  2480. for (i = 0; i < num_displays; i++) {
  2481. splash_display = &data->splash_display[i];
  2482. if (!i || !share_splash_mem) {
  2483. if (of_address_to_resource(node, i, &r)) {
  2484. SDE_ERROR("invalid data for:%s\n", node_name);
  2485. return -EINVAL;
  2486. }
  2487. mem = &data->splash_mem[i];
  2488. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2489. SDE_DEBUG("failed to find ramdump memory\n");
  2490. mem->ramdump_base = 0;
  2491. mem->ramdump_size = 0;
  2492. } else {
  2493. mem->ramdump_base = (unsigned long)r1.start;
  2494. mem->ramdump_size = (r1.end - r1.start) + 1;
  2495. }
  2496. mem->splash_buf_base = (unsigned long)r.start;
  2497. mem->splash_buf_size = (r.end - r.start) + 1;
  2498. mem->ref_cnt = 0;
  2499. splash_display->splash = mem;
  2500. data->num_splash_regions++;
  2501. } else {
  2502. data->splash_display[i].splash = &data->splash_mem[0];
  2503. }
  2504. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2505. splash_display->splash->splash_buf_base,
  2506. splash_display->splash->splash_buf_size);
  2507. }
  2508. return ret;
  2509. }
  2510. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2511. struct platform_device *platformdev)
  2512. {
  2513. int rc = -EINVAL;
  2514. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2515. if (IS_ERR(sde_kms->mmio)) {
  2516. rc = PTR_ERR(sde_kms->mmio);
  2517. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2518. sde_kms->mmio = NULL;
  2519. goto error;
  2520. }
  2521. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2522. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2523. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2524. sde_kms->mmio_len);
  2525. if (rc)
  2526. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2527. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2528. "vbif_phys");
  2529. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2530. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2531. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2532. sde_kms->vbif[VBIF_RT] = NULL;
  2533. goto error;
  2534. }
  2535. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2536. "vbif_phys");
  2537. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2538. sde_kms->vbif_len[VBIF_RT]);
  2539. if (rc)
  2540. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2541. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2542. "vbif_nrt_phys");
  2543. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2544. sde_kms->vbif[VBIF_NRT] = NULL;
  2545. SDE_DEBUG("VBIF NRT is not defined");
  2546. } else {
  2547. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2548. "vbif_nrt_phys");
  2549. rc = sde_dbg_reg_register_base("vbif_nrt",
  2550. sde_kms->vbif[VBIF_NRT],
  2551. sde_kms->vbif_len[VBIF_NRT]);
  2552. if (rc)
  2553. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2554. rc);
  2555. }
  2556. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2557. "regdma_phys");
  2558. if (IS_ERR(sde_kms->reg_dma)) {
  2559. sde_kms->reg_dma = NULL;
  2560. SDE_DEBUG("REG_DMA is not defined");
  2561. } else {
  2562. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2563. "regdma_phys");
  2564. rc = sde_dbg_reg_register_base("reg_dma",
  2565. sde_kms->reg_dma,
  2566. sde_kms->reg_dma_len);
  2567. if (rc)
  2568. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2569. rc);
  2570. }
  2571. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2572. "sid_phys");
  2573. if (IS_ERR(sde_kms->sid)) {
  2574. rc = PTR_ERR(sde_kms->sid);
  2575. SDE_ERROR("sid register memory map failed: %d\n", rc);
  2576. sde_kms->sid = NULL;
  2577. goto error;
  2578. }
  2579. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2580. rc = sde_dbg_reg_register_base("sid", sde_kms->sid, sde_kms->sid_len);
  2581. if (rc)
  2582. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2583. sde_kms->sw_fuse = msm_ioremap(platformdev, "swfuse_phys",
  2584. "swfuse_phys");
  2585. if (IS_ERR(sde_kms->sw_fuse)) {
  2586. sde_kms->sw_fuse = NULL;
  2587. SDE_DEBUG("sw_fuse is not defined");
  2588. } else {
  2589. sde_kms->sw_fuse_len = msm_iomap_size(platformdev,
  2590. "swfuse_phys");
  2591. rc = sde_dbg_reg_register_base("sw_fuse", sde_kms->sw_fuse,
  2592. sde_kms->sw_fuse_len);
  2593. if (rc)
  2594. SDE_ERROR("dbg base register sw_fuse failed: %d\n", rc);
  2595. }
  2596. error:
  2597. return rc;
  2598. }
  2599. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2600. struct sde_kms *sde_kms)
  2601. {
  2602. int rc = 0;
  2603. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2604. sde_kms->genpd.name = dev->unique;
  2605. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2606. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2607. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2608. if (rc < 0) {
  2609. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2610. sde_kms->genpd.name, rc);
  2611. return rc;
  2612. }
  2613. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2614. &sde_kms->genpd);
  2615. if (rc < 0) {
  2616. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2617. sde_kms->genpd.name, rc);
  2618. pm_genpd_remove(&sde_kms->genpd);
  2619. return rc;
  2620. }
  2621. sde_kms->genpd_init = true;
  2622. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2623. }
  2624. return rc;
  2625. }
  2626. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2627. struct drm_device *dev,
  2628. struct msm_drm_private *priv)
  2629. {
  2630. struct sde_rm *rm = NULL;
  2631. int i, rc = -EINVAL;
  2632. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2633. sde_power_data_bus_set_quota(&priv->phandle, i,
  2634. SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA,
  2635. SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA);
  2636. _sde_kms_core_hw_rev_init(sde_kms);
  2637. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2638. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2639. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2640. rc = PTR_ERR(sde_kms->catalog);
  2641. if (!sde_kms->catalog)
  2642. rc = -EINVAL;
  2643. SDE_ERROR("catalog init failed: %d\n", rc);
  2644. sde_kms->catalog = NULL;
  2645. goto power_error;
  2646. }
  2647. /* initialize power domain if defined */
  2648. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2649. if (rc) {
  2650. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2651. goto genpd_err;
  2652. }
  2653. rc = _sde_kms_mmu_init(sde_kms);
  2654. if (rc) {
  2655. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2656. goto power_error;
  2657. }
  2658. /* Initialize reg dma block which is a singleton */
  2659. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2660. sde_kms->dev);
  2661. if (rc) {
  2662. SDE_ERROR("failed: reg dma init failed\n");
  2663. goto power_error;
  2664. }
  2665. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2666. rm = &sde_kms->rm;
  2667. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2668. sde_kms->dev);
  2669. if (rc) {
  2670. SDE_ERROR("rm init failed: %d\n", rc);
  2671. goto power_error;
  2672. }
  2673. sde_kms->rm_init = true;
  2674. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2675. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2676. rc = PTR_ERR(sde_kms->hw_intr);
  2677. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2678. sde_kms->hw_intr = NULL;
  2679. goto hw_intr_init_err;
  2680. }
  2681. /*
  2682. * Attempt continuous splash handoff only if reserved
  2683. * splash memory is found & release resources on any error
  2684. * in finding display hw config in splash
  2685. */
  2686. if (sde_kms->splash_data.num_splash_regions) {
  2687. struct sde_splash_display *display;
  2688. int ret, display_count =
  2689. sde_kms->splash_data.num_splash_displays;
  2690. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2691. &sde_kms->splash_data, sde_kms->catalog);
  2692. for (i = 0; i < display_count; i++) {
  2693. display = &sde_kms->splash_data.splash_display[i];
  2694. /*
  2695. * free splash region on resource init failure and
  2696. * cont-splash disabled case
  2697. */
  2698. if (!display->cont_splash_enabled || ret)
  2699. _sde_kms_free_splash_region(sde_kms, display);
  2700. }
  2701. }
  2702. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2703. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2704. rc = PTR_ERR(sde_kms->hw_mdp);
  2705. if (!sde_kms->hw_mdp)
  2706. rc = -EINVAL;
  2707. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2708. sde_kms->hw_mdp = NULL;
  2709. goto power_error;
  2710. }
  2711. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2712. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2713. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2714. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2715. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2716. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2717. if (!sde_kms->hw_vbif[vbif_idx])
  2718. rc = -EINVAL;
  2719. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2720. sde_kms->hw_vbif[vbif_idx] = NULL;
  2721. goto power_error;
  2722. }
  2723. }
  2724. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2725. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2726. sde_kms->mmio_len, sde_kms->catalog);
  2727. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2728. rc = PTR_ERR(sde_kms->hw_uidle);
  2729. if (!sde_kms->hw_uidle)
  2730. rc = -EINVAL;
  2731. /* uidle is optional, so do not make it a fatal error */
  2732. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2733. sde_kms->hw_uidle = NULL;
  2734. rc = 0;
  2735. }
  2736. } else {
  2737. sde_kms->hw_uidle = NULL;
  2738. }
  2739. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2740. sde_kms->sid_len, sde_kms->catalog);
  2741. if (IS_ERR(sde_kms->hw_sid)) {
  2742. SDE_ERROR("failed to init sid %ld\n", PTR_ERR(sde_kms->hw_sid));
  2743. sde_kms->hw_sid = NULL;
  2744. goto power_error;
  2745. }
  2746. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2747. &priv->phandle, "core_clk");
  2748. if (rc) {
  2749. SDE_ERROR("failed to init perf %d\n", rc);
  2750. goto perf_err;
  2751. }
  2752. if (sde_kms->sw_fuse) {
  2753. sde_kms->hw_sw_fuse = sde_hw_sw_fuse_init(sde_kms->sw_fuse,
  2754. sde_kms->sw_fuse_len, sde_kms->catalog);
  2755. if (IS_ERR(sde_kms->hw_sw_fuse)) {
  2756. SDE_ERROR("failed to init sw_fuse %ld\n",
  2757. PTR_ERR(sde_kms->hw_sw_fuse));
  2758. sde_kms->hw_sw_fuse = NULL;
  2759. }
  2760. } else {
  2761. sde_kms->hw_sw_fuse = NULL;
  2762. }
  2763. /*
  2764. * _sde_kms_drm_obj_init should create the DRM related objects
  2765. * i.e. CRTCs, planes, encoders, connectors and so forth
  2766. */
  2767. rc = _sde_kms_drm_obj_init(sde_kms);
  2768. if (rc) {
  2769. SDE_ERROR("modeset init failed: %d\n", rc);
  2770. goto drm_obj_init_err;
  2771. }
  2772. return 0;
  2773. genpd_err:
  2774. drm_obj_init_err:
  2775. sde_core_perf_destroy(&sde_kms->perf);
  2776. hw_intr_init_err:
  2777. perf_err:
  2778. power_error:
  2779. return rc;
  2780. }
  2781. static int sde_kms_hw_init(struct msm_kms *kms)
  2782. {
  2783. struct sde_kms *sde_kms;
  2784. struct drm_device *dev;
  2785. struct msm_drm_private *priv;
  2786. struct platform_device *platformdev;
  2787. int i, rc = -EINVAL;
  2788. if (!kms) {
  2789. SDE_ERROR("invalid kms\n");
  2790. goto end;
  2791. }
  2792. sde_kms = to_sde_kms(kms);
  2793. dev = sde_kms->dev;
  2794. if (!dev || !dev->dev) {
  2795. SDE_ERROR("invalid device\n");
  2796. goto end;
  2797. }
  2798. platformdev = to_platform_device(dev->dev);
  2799. priv = dev->dev_private;
  2800. if (!priv) {
  2801. SDE_ERROR("invalid private data\n");
  2802. goto end;
  2803. }
  2804. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2805. if (rc)
  2806. goto error;
  2807. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2808. if (rc)
  2809. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2810. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2811. if (rc < 0) {
  2812. SDE_ERROR("resource enable failed: %d\n", rc);
  2813. goto error;
  2814. }
  2815. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2816. if (rc)
  2817. goto hw_init_err;
  2818. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2819. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2820. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2821. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2822. mutex_init(&sde_kms->secure_transition_lock);
  2823. atomic_set(&sde_kms->detach_sec_cb, 0);
  2824. atomic_set(&sde_kms->detach_all_cb, 0);
  2825. /*
  2826. * Support format modifiers for compression etc.
  2827. */
  2828. dev->mode_config.allow_fb_modifiers = true;
  2829. /*
  2830. * Handle (re)initializations during power enable
  2831. */
  2832. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2833. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2834. SDE_POWER_EVENT_POST_ENABLE |
  2835. SDE_POWER_EVENT_PRE_DISABLE,
  2836. sde_kms_handle_power_event, sde_kms, "kms");
  2837. if (sde_kms->splash_data.num_splash_displays) {
  2838. SDE_DEBUG("Skipping MDP Resources disable\n");
  2839. } else {
  2840. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2841. sde_power_data_bus_set_quota(&priv->phandle, i,
  2842. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2843. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2844. pm_runtime_put_sync(sde_kms->dev->dev);
  2845. }
  2846. return 0;
  2847. hw_init_err:
  2848. pm_runtime_put_sync(sde_kms->dev->dev);
  2849. error:
  2850. _sde_kms_hw_destroy(sde_kms, platformdev);
  2851. end:
  2852. return rc;
  2853. }
  2854. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2855. {
  2856. struct msm_drm_private *priv;
  2857. struct sde_kms *sde_kms;
  2858. if (!dev || !dev->dev_private) {
  2859. SDE_ERROR("drm device node invalid\n");
  2860. return ERR_PTR(-EINVAL);
  2861. }
  2862. priv = dev->dev_private;
  2863. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2864. if (!sde_kms) {
  2865. SDE_ERROR("failed to allocate sde kms\n");
  2866. return ERR_PTR(-ENOMEM);
  2867. }
  2868. msm_kms_init(&sde_kms->base, &kms_funcs);
  2869. sde_kms->dev = dev;
  2870. return &sde_kms->base;
  2871. }
  2872. static int _sde_kms_register_events(struct msm_kms *kms,
  2873. struct drm_mode_object *obj, u32 event, bool en)
  2874. {
  2875. int ret = 0;
  2876. struct drm_crtc *crtc = NULL;
  2877. struct drm_connector *conn = NULL;
  2878. struct sde_kms *sde_kms = NULL;
  2879. if (!kms || !obj) {
  2880. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2881. return -EINVAL;
  2882. }
  2883. sde_kms = to_sde_kms(kms);
  2884. switch (obj->type) {
  2885. case DRM_MODE_OBJECT_CRTC:
  2886. crtc = obj_to_crtc(obj);
  2887. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2888. break;
  2889. case DRM_MODE_OBJECT_CONNECTOR:
  2890. conn = obj_to_connector(obj);
  2891. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2892. en);
  2893. break;
  2894. }
  2895. return ret;
  2896. }
  2897. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  2898. {
  2899. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  2900. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  2901. }