dsi_drm.c 28 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. }
  48. if (msm_is_mode_seamless(drm_mode))
  49. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  50. if (msm_is_mode_dynamic_fps(drm_mode))
  51. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  52. if (msm_needs_vblank_pre_modeset(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  54. if (msm_is_mode_seamless_dms(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  56. if (msm_is_mode_seamless_vrr(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  58. if (msm_is_mode_seamless_poms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  60. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  62. dsi_mode->timing.h_sync_polarity =
  63. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  64. dsi_mode->timing.v_sync_polarity =
  65. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  66. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  67. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  68. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  69. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  70. }
  71. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  72. struct drm_display_mode *drm_mode)
  73. {
  74. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  75. memset(drm_mode, 0, sizeof(*drm_mode));
  76. drm_mode->hdisplay = dsi_mode->timing.h_active;
  77. drm_mode->hsync_start = drm_mode->hdisplay +
  78. dsi_mode->timing.h_front_porch;
  79. drm_mode->hsync_end = drm_mode->hsync_start +
  80. dsi_mode->timing.h_sync_width;
  81. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  82. drm_mode->hskew = dsi_mode->timing.h_skew;
  83. drm_mode->vdisplay = dsi_mode->timing.v_active;
  84. drm_mode->vsync_start = drm_mode->vdisplay +
  85. dsi_mode->timing.v_front_porch;
  86. drm_mode->vsync_end = drm_mode->vsync_start +
  87. dsi_mode->timing.v_sync_width;
  88. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  89. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  90. drm_mode->clock = dsi_mode->pixel_clk_khz;
  91. drm_mode->private = (int *)dsi_mode->priv_info;
  92. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  93. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  94. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  95. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  97. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  106. if (dsi_mode->timing.h_sync_polarity)
  107. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  108. if (dsi_mode->timing.v_sync_polarity)
  109. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  110. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  111. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  112. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  113. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  114. /* set mode name */
  115. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  116. drm_mode->hdisplay, drm_mode->vdisplay,
  117. drm_mode->vrefresh, drm_mode->clock,
  118. video_mode ? "vid" : "cmd");
  119. }
  120. static int dsi_bridge_attach(struct drm_bridge *bridge)
  121. {
  122. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  123. if (!bridge) {
  124. DSI_ERR("Invalid params\n");
  125. return -EINVAL;
  126. }
  127. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  128. return 0;
  129. }
  130. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  131. {
  132. int rc = 0;
  133. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  134. if (!bridge) {
  135. DSI_ERR("Invalid params\n");
  136. return;
  137. }
  138. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  139. DSI_ERR("Incorrect bridge details\n");
  140. return;
  141. }
  142. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  143. /* By this point mode should have been validated through mode_fixup */
  144. rc = dsi_display_set_mode(c_bridge->display,
  145. &(c_bridge->dsi_mode), 0x0);
  146. if (rc) {
  147. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  148. c_bridge->id, rc);
  149. return;
  150. }
  151. if (c_bridge->dsi_mode.dsi_mode_flags &
  152. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  153. DSI_MODE_FLAG_DYN_CLK)) {
  154. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  155. return;
  156. }
  157. SDE_ATRACE_BEGIN("dsi_display_prepare");
  158. rc = dsi_display_prepare(c_bridge->display);
  159. if (rc) {
  160. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  161. c_bridge->id, rc);
  162. SDE_ATRACE_END("dsi_display_prepare");
  163. return;
  164. }
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  175. if (rc)
  176. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  177. rc);
  178. }
  179. static void dsi_bridge_enable(struct drm_bridge *bridge)
  180. {
  181. int rc = 0;
  182. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  183. struct dsi_display *display;
  184. if (!bridge) {
  185. DSI_ERR("Invalid params\n");
  186. return;
  187. }
  188. if (c_bridge->dsi_mode.dsi_mode_flags &
  189. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  190. DSI_MODE_FLAG_DYN_CLK)) {
  191. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  192. return;
  193. }
  194. display = c_bridge->display;
  195. rc = dsi_display_post_enable(display);
  196. if (rc)
  197. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  198. c_bridge->id, rc);
  199. if (display && display->drm_conn)
  200. sde_connector_helper_bridge_enable(display->drm_conn);
  201. }
  202. static void dsi_bridge_disable(struct drm_bridge *bridge)
  203. {
  204. int rc = 0;
  205. struct dsi_display *display;
  206. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  207. if (!bridge) {
  208. DSI_ERR("Invalid params\n");
  209. return;
  210. }
  211. display = c_bridge->display;
  212. if (display && display->drm_conn) {
  213. if (bridge->encoder->crtc->state->adjusted_mode.private_flags &
  214. MSM_MODE_FLAG_SEAMLESS_POMS) {
  215. display->poms_pending = true;
  216. /* Disable ESD thread, during panel mode switch */
  217. sde_connector_schedule_status_work(display->drm_conn,
  218. false);
  219. } else {
  220. display->poms_pending = false;
  221. sde_connector_helper_bridge_disable(display->drm_conn);
  222. }
  223. }
  224. rc = dsi_display_pre_disable(c_bridge->display);
  225. if (rc) {
  226. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  227. c_bridge->id, rc);
  228. }
  229. }
  230. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  231. {
  232. int rc = 0;
  233. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  234. if (!bridge) {
  235. DSI_ERR("Invalid params\n");
  236. return;
  237. }
  238. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  239. SDE_ATRACE_BEGIN("dsi_display_disable");
  240. rc = dsi_display_disable(c_bridge->display);
  241. if (rc) {
  242. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  243. c_bridge->id, rc);
  244. SDE_ATRACE_END("dsi_display_disable");
  245. return;
  246. }
  247. SDE_ATRACE_END("dsi_display_disable");
  248. rc = dsi_display_unprepare(c_bridge->display);
  249. if (rc) {
  250. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  251. c_bridge->id, rc);
  252. SDE_ATRACE_END("dsi_bridge_post_disable");
  253. return;
  254. }
  255. SDE_ATRACE_END("dsi_bridge_post_disable");
  256. }
  257. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  258. struct drm_display_mode *mode,
  259. struct drm_display_mode *adjusted_mode)
  260. {
  261. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  262. if (!bridge || !mode || !adjusted_mode) {
  263. DSI_ERR("Invalid params\n");
  264. return;
  265. }
  266. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  267. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  268. /* restore bit_clk_rate also for dynamic clk use cases */
  269. c_bridge->dsi_mode.timing.clk_rate_hz =
  270. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  271. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  272. }
  273. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  274. const struct drm_display_mode *mode,
  275. struct drm_display_mode *adjusted_mode)
  276. {
  277. int rc = 0;
  278. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  279. struct dsi_display *display;
  280. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  281. struct drm_crtc_state *crtc_state;
  282. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  283. if (!bridge || !mode || !adjusted_mode) {
  284. DSI_ERR("Invalid params\n");
  285. return false;
  286. }
  287. display = c_bridge->display;
  288. if (!display) {
  289. DSI_ERR("Invalid params\n");
  290. return false;
  291. }
  292. /*
  293. * if no timing defined in panel, it must be external mode
  294. * and we'll use empty priv info to populate the mode
  295. */
  296. if (display->panel && !display->panel->num_timing_nodes) {
  297. *adjusted_mode = *mode;
  298. adjusted_mode->private = (int *)&default_priv_info;
  299. adjusted_mode->private_flags = 0;
  300. return true;
  301. }
  302. convert_to_dsi_mode(mode, &dsi_mode);
  303. /*
  304. * retrieve dsi mode from dsi driver's cache since not safe to take
  305. * the drm mode config mutex in all paths
  306. */
  307. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  308. if (rc)
  309. return rc;
  310. /* propagate the private info to the adjusted_mode derived dsi mode */
  311. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  312. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  313. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  314. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  315. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  316. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  317. if (rc) {
  318. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  319. return false;
  320. }
  321. if (bridge->encoder && bridge->encoder->crtc &&
  322. crtc_state->crtc) {
  323. const struct drm_display_mode *cur_mode =
  324. &crtc_state->crtc->state->mode;
  325. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  326. cur_dsi_mode.timing.dsc_enabled =
  327. dsi_mode.priv_info->dsc_enabled;
  328. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  329. rc = dsi_display_validate_mode_change(c_bridge->display,
  330. &cur_dsi_mode, &dsi_mode);
  331. if (rc) {
  332. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  333. c_bridge->display->name, rc);
  334. return false;
  335. }
  336. /* No panel mode switch when drm pipeline is changing */
  337. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  338. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  339. (crtc_state->enable ==
  340. crtc_state->crtc->state->enable))
  341. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  342. /* No DMS/VRR when drm pipeline is changing */
  343. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  344. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  345. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  346. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  347. (!crtc_state->active_changed ||
  348. display->is_cont_splash_enabled))
  349. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  350. }
  351. /* convert back to drm mode, propagating the private info & flags */
  352. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  353. return true;
  354. }
  355. u64 dsi_drm_find_bit_clk_rate(void *display,
  356. const struct drm_display_mode *drm_mode)
  357. {
  358. int i = 0, count = 0;
  359. struct dsi_display *dsi_display = display;
  360. struct dsi_display_mode *dsi_mode;
  361. u64 bit_clk_rate = 0;
  362. if (!dsi_display || !drm_mode)
  363. return 0;
  364. dsi_display_get_mode_count(dsi_display, &count);
  365. for (i = 0; i < count; i++) {
  366. dsi_mode = &dsi_display->modes[i];
  367. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  368. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  369. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  370. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  371. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  372. break;
  373. }
  374. }
  375. return bit_clk_rate;
  376. }
  377. int dsi_conn_get_mode_info(struct drm_connector *connector,
  378. const struct drm_display_mode *drm_mode,
  379. struct msm_mode_info *mode_info,
  380. void *display, const struct msm_resource_caps_info *avail_res)
  381. {
  382. struct dsi_display_mode dsi_mode;
  383. struct dsi_mode_info *timing;
  384. if (!drm_mode || !mode_info)
  385. return -EINVAL;
  386. convert_to_dsi_mode(drm_mode, &dsi_mode);
  387. if (!dsi_mode.priv_info)
  388. return -EINVAL;
  389. memset(mode_info, 0, sizeof(*mode_info));
  390. timing = &dsi_mode.timing;
  391. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  392. mode_info->vtotal = DSI_V_TOTAL(timing);
  393. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  394. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  395. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  396. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  397. mode_info->mdp_transfer_time_us =
  398. dsi_mode.priv_info->mdp_transfer_time_us;
  399. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  400. sizeof(struct msm_display_topology));
  401. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  402. if (dsi_mode.priv_info->dsc_enabled) {
  403. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  404. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  405. sizeof(dsi_mode.priv_info->dsc));
  406. mode_info->comp_info.comp_ratio =
  407. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1;
  408. }
  409. if (dsi_mode.priv_info->roi_caps.enabled) {
  410. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  411. sizeof(dsi_mode.priv_info->roi_caps));
  412. }
  413. return 0;
  414. }
  415. static const struct drm_bridge_funcs dsi_bridge_ops = {
  416. .attach = dsi_bridge_attach,
  417. .mode_fixup = dsi_bridge_mode_fixup,
  418. .pre_enable = dsi_bridge_pre_enable,
  419. .enable = dsi_bridge_enable,
  420. .disable = dsi_bridge_disable,
  421. .post_disable = dsi_bridge_post_disable,
  422. .mode_set = dsi_bridge_mode_set,
  423. };
  424. int dsi_conn_set_info_blob(struct drm_connector *connector,
  425. void *info, void *display, struct msm_mode_info *mode_info)
  426. {
  427. struct dsi_display *dsi_display = display;
  428. struct dsi_panel *panel;
  429. enum dsi_pixel_format fmt;
  430. u32 bpp;
  431. if (!info || !dsi_display)
  432. return -EINVAL;
  433. dsi_display->drm_conn = connector;
  434. sde_kms_info_add_keystr(info,
  435. "display type", dsi_display->display_type);
  436. switch (dsi_display->type) {
  437. case DSI_DISPLAY_SINGLE:
  438. sde_kms_info_add_keystr(info, "display config",
  439. "single display");
  440. break;
  441. case DSI_DISPLAY_EXT_BRIDGE:
  442. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  443. break;
  444. case DSI_DISPLAY_SPLIT:
  445. sde_kms_info_add_keystr(info, "display config",
  446. "split display");
  447. break;
  448. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  449. sde_kms_info_add_keystr(info, "display config",
  450. "split ext bridge");
  451. break;
  452. default:
  453. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  454. break;
  455. }
  456. if (!dsi_display->panel) {
  457. DSI_DEBUG("invalid panel data\n");
  458. goto end;
  459. }
  460. panel = dsi_display->panel;
  461. sde_kms_info_add_keystr(info, "panel name", panel->name);
  462. switch (panel->panel_mode) {
  463. case DSI_OP_VIDEO_MODE:
  464. sde_kms_info_add_keystr(info, "panel mode", "video");
  465. sde_kms_info_add_keystr(info, "qsync support",
  466. panel->qsync_min_fps ? "true" : "false");
  467. break;
  468. case DSI_OP_CMD_MODE:
  469. sde_kms_info_add_keystr(info, "panel mode", "command");
  470. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  471. mode_info->mdp_transfer_time_us);
  472. sde_kms_info_add_keystr(info, "qsync support",
  473. panel->qsync_min_fps ? "true" : "false");
  474. break;
  475. default:
  476. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  477. break;
  478. }
  479. sde_kms_info_add_keystr(info, "dfps support",
  480. panel->dfps_caps.dfps_support ? "true" : "false");
  481. if (panel->dfps_caps.dfps_support) {
  482. sde_kms_info_add_keyint(info, "min_fps",
  483. panel->dfps_caps.min_refresh_rate);
  484. sde_kms_info_add_keyint(info, "max_fps",
  485. panel->dfps_caps.max_refresh_rate);
  486. }
  487. sde_kms_info_add_keystr(info, "dyn bitclk support",
  488. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  489. switch (panel->phy_props.rotation) {
  490. case DSI_PANEL_ROTATE_NONE:
  491. sde_kms_info_add_keystr(info, "panel orientation", "none");
  492. break;
  493. case DSI_PANEL_ROTATE_H_FLIP:
  494. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  495. break;
  496. case DSI_PANEL_ROTATE_V_FLIP:
  497. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  498. break;
  499. case DSI_PANEL_ROTATE_HV_FLIP:
  500. sde_kms_info_add_keystr(info, "panel orientation",
  501. "horz & vert flip");
  502. break;
  503. default:
  504. DSI_DEBUG("invalid panel rotation:%d\n",
  505. panel->phy_props.rotation);
  506. break;
  507. }
  508. switch (panel->bl_config.type) {
  509. case DSI_BACKLIGHT_PWM:
  510. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  511. break;
  512. case DSI_BACKLIGHT_WLED:
  513. sde_kms_info_add_keystr(info, "backlight type", "wled");
  514. break;
  515. case DSI_BACKLIGHT_DCS:
  516. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  517. break;
  518. default:
  519. DSI_DEBUG("invalid panel backlight type:%d\n",
  520. panel->bl_config.type);
  521. break;
  522. }
  523. if (mode_info && mode_info->roi_caps.enabled) {
  524. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  525. mode_info->roi_caps.num_roi);
  526. sde_kms_info_add_keyint(info, "partial_update_xstart",
  527. mode_info->roi_caps.align.xstart_pix_align);
  528. sde_kms_info_add_keyint(info, "partial_update_walign",
  529. mode_info->roi_caps.align.width_pix_align);
  530. sde_kms_info_add_keyint(info, "partial_update_wmin",
  531. mode_info->roi_caps.align.min_width);
  532. sde_kms_info_add_keyint(info, "partial_update_ystart",
  533. mode_info->roi_caps.align.ystart_pix_align);
  534. sde_kms_info_add_keyint(info, "partial_update_halign",
  535. mode_info->roi_caps.align.height_pix_align);
  536. sde_kms_info_add_keyint(info, "partial_update_hmin",
  537. mode_info->roi_caps.align.min_height);
  538. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  539. mode_info->roi_caps.merge_rois);
  540. }
  541. fmt = dsi_display->config.common_config.dst_format;
  542. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  543. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  544. end:
  545. return 0;
  546. }
  547. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  548. bool force,
  549. void *display)
  550. {
  551. enum drm_connector_status status = connector_status_unknown;
  552. struct msm_display_info info;
  553. int rc;
  554. if (!conn || !display)
  555. return status;
  556. /* get display dsi_info */
  557. memset(&info, 0x0, sizeof(info));
  558. rc = dsi_display_get_info(conn, &info, display);
  559. if (rc) {
  560. DSI_ERR("failed to get display info, rc=%d\n", rc);
  561. return connector_status_disconnected;
  562. }
  563. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  564. status = (info.is_connected ? connector_status_connected :
  565. connector_status_disconnected);
  566. else
  567. status = connector_status_connected;
  568. conn->display_info.width_mm = info.width_mm;
  569. conn->display_info.height_mm = info.height_mm;
  570. return status;
  571. }
  572. void dsi_connector_put_modes(struct drm_connector *connector,
  573. void *display)
  574. {
  575. struct drm_display_mode *drm_mode;
  576. struct dsi_display_mode dsi_mode;
  577. struct dsi_display *dsi_display;
  578. if (!connector || !display)
  579. return;
  580. list_for_each_entry(drm_mode, &connector->modes, head) {
  581. convert_to_dsi_mode(drm_mode, &dsi_mode);
  582. dsi_display_put_mode(display, &dsi_mode);
  583. }
  584. /* free the display structure modes also */
  585. dsi_display = display;
  586. kfree(dsi_display->modes);
  587. dsi_display->modes = NULL;
  588. }
  589. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  590. {
  591. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  592. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  593. u32 dtd_size = 18;
  594. u32 header_size = sizeof(standard_header);
  595. if (!name)
  596. return -EINVAL;
  597. /* Fill standard header */
  598. memcpy(dtd, standard_header, header_size);
  599. dtd_size -= header_size;
  600. dtd_size = min_t(u32, dtd_size, strlen(name));
  601. memcpy(dtd + header_size, name, dtd_size);
  602. return 0;
  603. }
  604. static void dsi_drm_update_dtd(struct edid *edid,
  605. struct dsi_display_mode *modes, u32 modes_count)
  606. {
  607. u32 i;
  608. u32 count = min_t(u32, modes_count, 3);
  609. for (i = 0; i < count; i++) {
  610. struct detailed_timing *dtd = &edid->detailed_timings[i];
  611. struct dsi_display_mode *mode = &modes[i];
  612. struct dsi_mode_info *timing = &mode->timing;
  613. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  614. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  615. timing->h_back_porch;
  616. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  617. timing->v_back_porch;
  618. u32 h_img = 0, v_img = 0;
  619. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  620. pd->hactive_lo = timing->h_active & 0xFF;
  621. pd->hblank_lo = h_blank & 0xFF;
  622. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  623. ((timing->h_active >> 8) & 0xF) << 4;
  624. pd->vactive_lo = timing->v_active & 0xFF;
  625. pd->vblank_lo = v_blank & 0xFF;
  626. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  627. ((timing->v_active >> 8) & 0xF) << 4;
  628. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  629. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  630. pd->vsync_offset_pulse_width_lo =
  631. ((timing->v_front_porch & 0xF) << 4) |
  632. (timing->v_sync_width & 0xF);
  633. pd->hsync_vsync_offset_pulse_width_hi =
  634. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  635. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  636. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  637. (((timing->v_sync_width >> 4) & 0x3) << 0);
  638. pd->width_mm_lo = h_img & 0xFF;
  639. pd->height_mm_lo = v_img & 0xFF;
  640. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  641. ((v_img >> 8) & 0xF);
  642. pd->hborder = 0;
  643. pd->vborder = 0;
  644. pd->misc = 0;
  645. }
  646. }
  647. static void dsi_drm_update_checksum(struct edid *edid)
  648. {
  649. u8 *data = (u8 *)edid;
  650. u32 i, sum = 0;
  651. for (i = 0; i < EDID_LENGTH - 1; i++)
  652. sum += data[i];
  653. edid->checksum = 0x100 - (sum & 0xFF);
  654. }
  655. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  656. const struct msm_resource_caps_info *avail_res)
  657. {
  658. int rc, i;
  659. u32 count = 0, edid_size;
  660. struct dsi_display_mode *modes = NULL;
  661. struct drm_display_mode drm_mode;
  662. struct dsi_display *display = data;
  663. struct edid edid;
  664. const u8 edid_buf[EDID_LENGTH] = {
  665. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  666. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  667. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  668. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  669. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  670. 0x01, 0x01, 0x01, 0x01,
  671. };
  672. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  673. memcpy(&edid, edid_buf, edid_size);
  674. rc = dsi_display_get_mode_count(display, &count);
  675. if (rc) {
  676. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  677. goto end;
  678. }
  679. rc = dsi_display_get_modes(display, &modes);
  680. if (rc) {
  681. DSI_ERR("failed to get modes, rc=%d\n", rc);
  682. count = 0;
  683. goto end;
  684. }
  685. for (i = 0; i < count; i++) {
  686. struct drm_display_mode *m;
  687. memset(&drm_mode, 0x0, sizeof(drm_mode));
  688. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  689. m = drm_mode_duplicate(connector->dev, &drm_mode);
  690. if (!m) {
  691. DSI_ERR("failed to add mode %ux%u\n",
  692. drm_mode.hdisplay,
  693. drm_mode.vdisplay);
  694. count = -ENOMEM;
  695. goto end;
  696. }
  697. m->width_mm = connector->display_info.width_mm;
  698. m->height_mm = connector->display_info.height_mm;
  699. /* set the first mode in list as preferred */
  700. if (i == 0)
  701. m->type |= DRM_MODE_TYPE_PREFERRED;
  702. drm_mode_probed_add(connector, m);
  703. }
  704. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  705. if (rc) {
  706. count = 0;
  707. goto end;
  708. }
  709. edid.width_cm = (connector->display_info.width_mm) / 10;
  710. edid.height_cm = (connector->display_info.height_mm) / 10;
  711. dsi_drm_update_dtd(&edid, modes, count);
  712. dsi_drm_update_checksum(&edid);
  713. rc = drm_connector_update_edid_property(connector, &edid);
  714. if (rc)
  715. count = 0;
  716. end:
  717. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  718. return count;
  719. }
  720. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  721. struct drm_display_mode *mode,
  722. void *display, const struct msm_resource_caps_info *avail_res)
  723. {
  724. struct dsi_display_mode dsi_mode;
  725. int rc;
  726. if (!connector || !mode) {
  727. DSI_ERR("Invalid params\n");
  728. return MODE_ERROR;
  729. }
  730. convert_to_dsi_mode(mode, &dsi_mode);
  731. rc = dsi_display_validate_mode(display, &dsi_mode,
  732. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  733. if (rc) {
  734. DSI_ERR("mode not supported, rc=%d\n", rc);
  735. return MODE_BAD;
  736. }
  737. return MODE_OK;
  738. }
  739. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  740. void *display,
  741. struct msm_display_kickoff_params *params)
  742. {
  743. if (!connector || !display || !params) {
  744. DSI_ERR("Invalid params\n");
  745. return -EINVAL;
  746. }
  747. return dsi_display_pre_kickoff(connector, display, params);
  748. }
  749. void dsi_conn_enable_event(struct drm_connector *connector,
  750. uint32_t event_idx, bool enable, void *display)
  751. {
  752. struct dsi_event_cb_info event_info;
  753. memset(&event_info, 0, sizeof(event_info));
  754. event_info.event_cb = sde_connector_trigger_event;
  755. event_info.event_usr_ptr = connector;
  756. dsi_display_enable_event(connector, display,
  757. event_idx, &event_info, enable);
  758. }
  759. int dsi_conn_post_kickoff(struct drm_connector *connector)
  760. {
  761. struct drm_encoder *encoder;
  762. struct dsi_bridge *c_bridge;
  763. struct dsi_display_mode adj_mode;
  764. struct dsi_display *display;
  765. struct dsi_display_ctrl *m_ctrl, *ctrl;
  766. int i, rc = 0;
  767. if (!connector || !connector->state) {
  768. DSI_ERR("invalid connector or connector state\n");
  769. return -EINVAL;
  770. }
  771. encoder = connector->state->best_encoder;
  772. if (!encoder) {
  773. DSI_DEBUG("best encoder is not available\n");
  774. return 0;
  775. }
  776. c_bridge = to_dsi_bridge(encoder->bridge);
  777. adj_mode = c_bridge->dsi_mode;
  778. display = c_bridge->display;
  779. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  780. m_ctrl = &display->ctrl[display->clk_master_idx];
  781. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  782. if (rc) {
  783. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  784. display->name, rc);
  785. return -EINVAL;
  786. }
  787. /* Update the rest of the controllers */
  788. display_for_each_ctrl(i, display) {
  789. ctrl = &display->ctrl[i];
  790. if (!ctrl->ctrl || (ctrl == m_ctrl))
  791. continue;
  792. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  793. if (rc) {
  794. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  795. display->name, rc);
  796. return -EINVAL;
  797. }
  798. }
  799. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  800. }
  801. /* ensure dynamic clk switch flag is reset */
  802. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  803. return 0;
  804. }
  805. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  806. struct drm_device *dev,
  807. struct drm_encoder *encoder)
  808. {
  809. int rc = 0;
  810. struct dsi_bridge *bridge;
  811. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  812. if (!bridge) {
  813. rc = -ENOMEM;
  814. goto error;
  815. }
  816. bridge->display = display;
  817. bridge->base.funcs = &dsi_bridge_ops;
  818. bridge->base.encoder = encoder;
  819. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  820. if (rc) {
  821. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  822. goto error_free_bridge;
  823. }
  824. encoder->bridge = &bridge->base;
  825. return bridge;
  826. error_free_bridge:
  827. kfree(bridge);
  828. error:
  829. return ERR_PTR(rc);
  830. }
  831. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  832. {
  833. if (bridge && bridge->base.encoder)
  834. bridge->base.encoder->bridge = NULL;
  835. kfree(bridge);
  836. }