dp_panel.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DP_PANEL_H_
  6. #define _DP_PANEL_H_
  7. #include <drm/msm_drm.h>
  8. #include "dp_aux.h"
  9. #include "dp_link.h"
  10. #include "dp_usbpd.h"
  11. #include "sde_edid_parser.h"
  12. #include "sde_connector.h"
  13. #include "msm_drv.h"
  14. #define DP_RECEIVER_DSC_CAP_SIZE 15
  15. #define DP_RECEIVER_FEC_STATUS_SIZE 3
  16. #define DP_RECEIVER_EXT_CAP_SIZE 4
  17. /*
  18. * A source initiated power down flag is set
  19. * when the DP is powered off while physical
  20. * DP cable is still connected i.e. without
  21. * HPD or not initiated by sink like HPD_IRQ.
  22. * This can happen if framework reboots or
  23. * device suspends.
  24. */
  25. #define DP_PANEL_SRC_INITIATED_POWER_DOWN BIT(0)
  26. #define DP_EXT_REC_CAP_FIELD BIT(7)
  27. enum dp_lane_count {
  28. DP_LANE_COUNT_1 = 1,
  29. DP_LANE_COUNT_2 = 2,
  30. DP_LANE_COUNT_4 = 4,
  31. };
  32. #define DP_MAX_DOWNSTREAM_PORTS 0x10
  33. struct dp_panel_info {
  34. u32 h_active;
  35. u32 v_active;
  36. u32 h_back_porch;
  37. u32 h_front_porch;
  38. u32 h_sync_width;
  39. u32 h_active_low;
  40. u32 v_back_porch;
  41. u32 v_front_porch;
  42. u32 v_sync_width;
  43. u32 v_active_low;
  44. u32 h_skew;
  45. u32 refresh_rate;
  46. u32 pixel_clk_khz;
  47. u32 bpp;
  48. bool widebus_en;
  49. struct msm_compression_info comp_info;
  50. s64 dsc_overhead_fp;
  51. };
  52. struct dp_display_mode {
  53. struct dp_panel_info timing;
  54. u32 capabilities;
  55. s64 fec_overhead_fp;
  56. s64 dsc_overhead_fp;
  57. };
  58. struct dp_panel;
  59. struct dp_panel_in {
  60. struct device *dev;
  61. struct dp_aux *aux;
  62. struct dp_link *link;
  63. struct dp_catalog_panel *catalog;
  64. struct drm_connector *connector;
  65. struct dp_panel *base_panel;
  66. struct dp_parser *parser;
  67. };
  68. struct dp_dsc_caps {
  69. bool dsc_capable;
  70. u8 version;
  71. bool block_pred_en;
  72. };
  73. struct dp_audio;
  74. #define DP_PANEL_CAPS_DSC BIT(0)
  75. struct dp_panel {
  76. /* dpcd raw data */
  77. u8 dpcd[DP_RECEIVER_CAP_SIZE + DP_RECEIVER_EXT_CAP_SIZE + 1];
  78. u8 ds_ports[DP_MAX_DOWNSTREAM_PORTS];
  79. u8 dsc_dpcd[DP_RECEIVER_DSC_CAP_SIZE + 1];
  80. u8 fec_dpcd;
  81. u8 fec_sts_dpcd[DP_RECEIVER_FEC_STATUS_SIZE + 1];
  82. struct drm_dp_link link_info;
  83. struct sde_edid_ctrl *edid_ctrl;
  84. struct dp_panel_info pinfo;
  85. bool video_test;
  86. bool spd_enabled;
  87. u32 vic;
  88. u32 max_pclk_khz;
  89. s64 mst_target_sc;
  90. /* debug */
  91. u32 max_bw_code;
  92. /* By default, stream_id is assigned to DP_INVALID_STREAM.
  93. * Client sets the stream id value using set_stream_id interface.
  94. */
  95. enum dp_stream_id stream_id;
  96. int vcpi;
  97. u32 channel_start_slot;
  98. u32 channel_total_slots;
  99. u32 pbn;
  100. u32 tot_dsc_blks_in_use;
  101. /* DRM connector assosiated with this panel */
  102. struct drm_connector *connector;
  103. struct dp_audio *audio;
  104. bool audio_supported;
  105. struct dp_dsc_caps sink_dsc_caps;
  106. bool dsc_feature_enable;
  107. bool fec_feature_enable;
  108. bool dsc_en;
  109. bool fec_en;
  110. bool widebus_en;
  111. bool mst_state;
  112. s64 fec_overhead_fp;
  113. int (*init)(struct dp_panel *dp_panel);
  114. int (*deinit)(struct dp_panel *dp_panel, u32 flags);
  115. int (*hw_cfg)(struct dp_panel *dp_panel, bool enable);
  116. int (*read_sink_caps)(struct dp_panel *dp_panel,
  117. struct drm_connector *connector, bool multi_func);
  118. u32 (*get_min_req_link_rate)(struct dp_panel *dp_panel);
  119. u32 (*get_mode_bpp)(struct dp_panel *dp_panel, u32 mode_max_bpp,
  120. u32 mode_pclk_khz);
  121. int (*get_modes)(struct dp_panel *dp_panel,
  122. struct drm_connector *connector, struct dp_display_mode *mode);
  123. void (*handle_sink_request)(struct dp_panel *dp_panel);
  124. int (*set_edid)(struct dp_panel *dp_panel, u8 *edid);
  125. int (*set_dpcd)(struct dp_panel *dp_panel, u8 *dpcd);
  126. int (*setup_hdr)(struct dp_panel *dp_panel,
  127. struct drm_msm_ext_hdr_metadata *hdr_meta,
  128. bool dhdr_update, u64 core_clk_rate, bool flush);
  129. int (*set_colorspace)(struct dp_panel *dp_panel,
  130. u32 colorspace);
  131. void (*tpg_config)(struct dp_panel *dp_panel, bool enable);
  132. int (*spd_config)(struct dp_panel *dp_panel);
  133. bool (*hdr_supported)(struct dp_panel *dp_panel);
  134. int (*set_stream_info)(struct dp_panel *dp_panel,
  135. enum dp_stream_id stream_id, u32 ch_start_slot,
  136. u32 ch_tot_slots, u32 pbn, int vcpi);
  137. int (*read_sink_status)(struct dp_panel *dp_panel, u8 *sts, u32 size);
  138. int (*update_edid)(struct dp_panel *dp_panel, struct edid *edid);
  139. bool (*read_mst_cap)(struct dp_panel *dp_panel);
  140. void (*convert_to_dp_mode)(struct dp_panel *dp_panel,
  141. const struct drm_display_mode *drm_mode,
  142. struct dp_display_mode *dp_mode);
  143. void (*update_pps)(struct dp_panel *dp_panel, char *pps_cmd);
  144. };
  145. struct dp_tu_calc_input {
  146. u64 lclk; /* 162, 270, 540 and 810 */
  147. u64 pclk_khz; /* in KHz */
  148. u64 hactive; /* active h-width */
  149. u64 hporch; /* bp + fp + pulse */
  150. int nlanes; /* no.of.lanes */
  151. int bpp; /* bits */
  152. int pixel_enc; /* 444, 420, 422 */
  153. int dsc_en; /* dsc on/off */
  154. int async_en; /* async mode */
  155. int fec_en; /* fec */
  156. int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
  157. int num_of_dsc_slices; /* number of slices per line */
  158. };
  159. struct dp_vc_tu_mapping_table {
  160. u32 vic;
  161. u8 lanes;
  162. u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
  163. u8 bpp;
  164. u32 valid_boundary_link;
  165. u32 delay_start_link;
  166. bool boundary_moderation_en;
  167. u32 valid_lower_boundary_link;
  168. u32 upper_boundary_count;
  169. u32 lower_boundary_count;
  170. u32 tu_size_minus1;
  171. };
  172. /**
  173. * is_link_rate_valid() - validates the link rate
  174. * @lane_rate: link rate requested by the sink
  175. *
  176. * Returns true if the requested link rate is supported.
  177. */
  178. static inline bool is_link_rate_valid(u32 bw_code)
  179. {
  180. return ((bw_code == DP_LINK_BW_1_62) ||
  181. (bw_code == DP_LINK_BW_2_7) ||
  182. (bw_code == DP_LINK_BW_5_4) ||
  183. (bw_code == DP_LINK_BW_8_1));
  184. }
  185. /**
  186. * dp_link_is_lane_count_valid() - validates the lane count
  187. * @lane_count: lane count requested by the sink
  188. *
  189. * Returns true if the requested lane count is supported.
  190. */
  191. static inline bool is_lane_count_valid(u32 lane_count)
  192. {
  193. return (lane_count == DP_LANE_COUNT_1) ||
  194. (lane_count == DP_LANE_COUNT_2) ||
  195. (lane_count == DP_LANE_COUNT_4);
  196. }
  197. struct dp_panel *dp_panel_get(struct dp_panel_in *in);
  198. void dp_panel_put(struct dp_panel *dp_panel);
  199. void dp_panel_calc_tu_test(struct dp_tu_calc_input *in,
  200. struct dp_vc_tu_mapping_table *tu_table);
  201. #endif /* _DP_PANEL_H_ */