dp_catalog.c 74 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/iopoll.h>
  7. #include "dp_catalog.h"
  8. #include "dp_reg.h"
  9. #include "dp_debug.h"
  10. #define DP_GET_MSB(x) (x >> 8)
  11. #define DP_GET_LSB(x) (x & 0xff)
  12. #define DP_PHY_READY BIT(1)
  13. #define dp_catalog_get_priv(x) ({ \
  14. struct dp_catalog *dp_catalog; \
  15. dp_catalog = container_of(x, struct dp_catalog, x); \
  16. container_of(dp_catalog, struct dp_catalog_private, \
  17. dp_catalog); \
  18. })
  19. #define DP_INTERRUPT_STATUS1 \
  20. (DP_INTR_AUX_I2C_DONE| \
  21. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  22. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  23. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  24. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  25. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  26. #define DP_INTERRUPT_STATUS2 \
  27. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  28. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  29. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  30. #define DP_INTERRUPT_STATUS5 \
  31. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  32. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  33. #define dp_catalog_fill_io(x) { \
  34. catalog->io.x = parser->get_io(parser, #x); \
  35. }
  36. #define dp_catalog_fill_io_buf(x) { \
  37. parser->get_io_buf(parser, #x); \
  38. }
  39. static u8 const vm_pre_emphasis[4][4] = {
  40. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  41. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  42. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  43. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  44. };
  45. /* voltage swing, 0.2v and 1.0v are not support */
  46. static u8 const vm_voltage_swing[4][4] = {
  47. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  48. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  49. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  50. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  51. };
  52. enum dp_flush_bit {
  53. DP_PPS_FLUSH,
  54. DP_DHDR_FLUSH,
  55. };
  56. struct dp_catalog_io {
  57. struct dp_io_data *dp_ahb;
  58. struct dp_io_data *dp_aux;
  59. struct dp_io_data *dp_link;
  60. struct dp_io_data *dp_p0;
  61. struct dp_io_data *dp_phy;
  62. struct dp_io_data *dp_ln_tx0;
  63. struct dp_io_data *dp_ln_tx1;
  64. struct dp_io_data *dp_mmss_cc;
  65. struct dp_io_data *dp_pll;
  66. struct dp_io_data *usb3_dp_com;
  67. struct dp_io_data *hdcp_physical;
  68. struct dp_io_data *dp_p1;
  69. struct dp_io_data *dp_tcsr;
  70. };
  71. /* audio related catalog functions */
  72. struct dp_catalog_private {
  73. struct device *dev;
  74. struct dp_catalog_io io;
  75. struct dp_parser *parser;
  76. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  77. struct dp_catalog dp_catalog;
  78. char exe_mode[SZ_4];
  79. };
  80. /* aux related catalog functions */
  81. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  82. {
  83. struct dp_catalog_private *catalog;
  84. struct dp_io_data *io_data;
  85. if (!aux) {
  86. DP_ERR("invalid input\n");
  87. goto end;
  88. }
  89. catalog = dp_catalog_get_priv(aux);
  90. io_data = catalog->io.dp_aux;
  91. return dp_read(catalog->exe_mode, io_data, DP_AUX_DATA);
  92. end:
  93. return 0;
  94. }
  95. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  96. {
  97. int rc = 0;
  98. struct dp_catalog_private *catalog;
  99. struct dp_io_data *io_data;
  100. if (!aux) {
  101. DP_ERR("invalid input\n");
  102. rc = -EINVAL;
  103. goto end;
  104. }
  105. catalog = dp_catalog_get_priv(aux);
  106. io_data = catalog->io.dp_aux;
  107. dp_write(catalog->exe_mode, io_data, DP_AUX_DATA, aux->data);
  108. end:
  109. return rc;
  110. }
  111. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  112. {
  113. int rc = 0;
  114. struct dp_catalog_private *catalog;
  115. struct dp_io_data *io_data;
  116. if (!aux) {
  117. DP_ERR("invalid input\n");
  118. rc = -EINVAL;
  119. goto end;
  120. }
  121. catalog = dp_catalog_get_priv(aux);
  122. io_data = catalog->io.dp_aux;
  123. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, aux->data);
  124. end:
  125. return rc;
  126. }
  127. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  128. {
  129. int rc = 0;
  130. u32 data = 0;
  131. struct dp_catalog_private *catalog;
  132. struct dp_io_data *io_data;
  133. if (!aux) {
  134. DP_ERR("invalid input\n");
  135. rc = -EINVAL;
  136. goto end;
  137. }
  138. catalog = dp_catalog_get_priv(aux);
  139. io_data = catalog->io.dp_aux;
  140. if (read) {
  141. data = dp_read(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL);
  142. data &= ~BIT(9);
  143. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, data);
  144. } else {
  145. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, 0);
  146. }
  147. end:
  148. return rc;
  149. }
  150. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  151. {
  152. struct dp_catalog_private *catalog;
  153. struct dp_io_data *io_data;
  154. u32 data = 0;
  155. if (!aux) {
  156. DP_ERR("invalid input\n");
  157. return;
  158. }
  159. catalog = dp_catalog_get_priv(aux);
  160. io_data = catalog->io.dp_phy;
  161. data = dp_read(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_STATUS);
  162. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  163. wmb(); /* make sure 0x1f is written before next write */
  164. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  165. wmb(); /* make sure 0x9f is written before next write */
  166. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  167. wmb(); /* make sure register is cleared */
  168. }
  169. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  170. {
  171. u32 aux_ctrl;
  172. struct dp_catalog_private *catalog;
  173. struct dp_io_data *io_data;
  174. if (!aux) {
  175. DP_ERR("invalid input\n");
  176. return;
  177. }
  178. catalog = dp_catalog_get_priv(aux);
  179. io_data = catalog->io.dp_aux;
  180. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  181. aux_ctrl |= BIT(1);
  182. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  183. usleep_range(1000, 1010); /* h/w recommended delay */
  184. aux_ctrl &= ~BIT(1);
  185. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  186. wmb(); /* make sure AUX reset is done here */
  187. }
  188. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  189. {
  190. u32 aux_ctrl;
  191. struct dp_catalog_private *catalog;
  192. struct dp_io_data *io_data;
  193. if (!aux) {
  194. DP_ERR("invalid input\n");
  195. return;
  196. }
  197. catalog = dp_catalog_get_priv(aux);
  198. io_data = catalog->io.dp_aux;
  199. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  200. if (enable) {
  201. aux_ctrl |= BIT(0);
  202. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  203. wmb(); /* make sure AUX module is enabled */
  204. dp_write(catalog->exe_mode, io_data, DP_TIMEOUT_COUNT, 0xffff);
  205. dp_write(catalog->exe_mode, io_data, DP_AUX_LIMITS, 0xffff);
  206. } else {
  207. aux_ctrl &= ~BIT(0);
  208. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  209. }
  210. }
  211. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  212. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  213. {
  214. struct dp_catalog_private *catalog;
  215. u32 new_index = 0, current_index = 0;
  216. struct dp_io_data *io_data;
  217. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  218. DP_ERR("invalid input\n");
  219. return;
  220. }
  221. catalog = dp_catalog_get_priv(aux);
  222. io_data = catalog->io.dp_phy;
  223. current_index = cfg[type].current_index;
  224. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  225. DP_DEBUG("Updating %s from 0x%08x to 0x%08x\n",
  226. dp_phy_aux_config_type_to_string(type),
  227. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  228. dp_write(catalog->exe_mode, io_data, cfg[type].offset,
  229. cfg[type].lut[new_index]);
  230. cfg[type].current_index = new_index;
  231. }
  232. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  233. struct dp_aux_cfg *cfg)
  234. {
  235. struct dp_catalog_private *catalog;
  236. struct dp_io_data *io_data;
  237. int i = 0;
  238. if (!aux || !cfg) {
  239. DP_ERR("invalid input\n");
  240. return;
  241. }
  242. catalog = dp_catalog_get_priv(aux);
  243. io_data = catalog->io.dp_phy;
  244. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x65);
  245. wmb(); /* make sure PD programming happened */
  246. /* Turn on BIAS current for PHY/PLL */
  247. io_data = catalog->io.dp_pll;
  248. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  249. 0x1b);
  250. io_data = catalog->io.dp_phy;
  251. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x02);
  252. wmb(); /* make sure PD programming happened */
  253. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x7d);
  254. /* Turn on BIAS current for PHY/PLL */
  255. io_data = catalog->io.dp_pll;
  256. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  257. 0x3f);
  258. /* DP AUX CFG register programming */
  259. io_data = catalog->io.dp_phy;
  260. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  261. dp_write(catalog->exe_mode, io_data, cfg[i].offset,
  262. cfg[i].lut[cfg[i].current_index]);
  263. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  264. wmb(); /* make sure AUX configuration is done before enabling it */
  265. }
  266. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  267. {
  268. u32 ack;
  269. struct dp_catalog_private *catalog;
  270. struct dp_io_data *io_data;
  271. if (!aux) {
  272. DP_ERR("invalid input\n");
  273. return;
  274. }
  275. catalog = dp_catalog_get_priv(aux);
  276. io_data = catalog->io.dp_ahb;
  277. aux->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS);
  278. aux->isr &= ~DP_INTR_MASK1;
  279. ack = aux->isr & DP_INTERRUPT_STATUS1;
  280. ack <<= 1;
  281. ack |= DP_INTR_MASK1;
  282. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, ack);
  283. }
  284. static bool dp_catalog_ctrl_wait_for_phy_ready(
  285. struct dp_catalog_private *catalog)
  286. {
  287. u32 reg = DP_PHY_STATUS, state;
  288. void __iomem *base = catalog->io.dp_phy->io.base;
  289. bool success = true;
  290. u32 const poll_sleep_us = 500;
  291. u32 const pll_timeout_us = 10000;
  292. if (readl_poll_timeout_atomic((base + reg), state,
  293. ((state & DP_PHY_READY) > 0),
  294. poll_sleep_us, pll_timeout_us)) {
  295. DP_ERR("PHY status failed, status=%x\n", state);
  296. success = false;
  297. }
  298. return success;
  299. }
  300. /* controller related catalog functions */
  301. static int dp_catalog_ctrl_late_phy_init(struct dp_catalog_ctrl *ctrl,
  302. u8 lane_cnt, bool flipped)
  303. {
  304. int rc = 0;
  305. u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
  306. struct dp_catalog_private *catalog;
  307. struct dp_io_data *io_data;
  308. if (!ctrl) {
  309. DP_ERR("invalid input\n");
  310. return -EINVAL;
  311. }
  312. catalog = dp_catalog_get_priv(ctrl);
  313. switch (lane_cnt) {
  314. case 1:
  315. drvr0_en = flipped ? 0x13 : 0x10;
  316. bias0_en = flipped ? 0x3E : 0x15;
  317. drvr1_en = flipped ? 0x10 : 0x13;
  318. bias1_en = flipped ? 0x15 : 0x3E;
  319. break;
  320. case 2:
  321. drvr0_en = flipped ? 0x10 : 0x10;
  322. bias0_en = flipped ? 0x3F : 0x15;
  323. drvr1_en = flipped ? 0x10 : 0x10;
  324. bias1_en = flipped ? 0x15 : 0x3F;
  325. break;
  326. case 4:
  327. default:
  328. drvr0_en = 0x10;
  329. bias0_en = 0x3F;
  330. drvr1_en = 0x10;
  331. bias1_en = 0x3F;
  332. break;
  333. }
  334. io_data = catalog->io.dp_ln_tx0;
  335. dp_write(catalog->exe_mode, io_data, TXn_HIGHZ_DRVR_EN_V420, drvr0_en);
  336. dp_write(catalog->exe_mode, io_data,
  337. TXn_TRANSCEIVER_BIAS_EN_V420, bias0_en);
  338. io_data = catalog->io.dp_ln_tx1;
  339. dp_write(catalog->exe_mode, io_data, TXn_HIGHZ_DRVR_EN_V420, drvr1_en);
  340. dp_write(catalog->exe_mode, io_data,
  341. TXn_TRANSCEIVER_BIAS_EN_V420, bias1_en);
  342. io_data = catalog->io.dp_phy;
  343. dp_write(catalog->exe_mode, io_data, DP_PHY_CFG, 0x18);
  344. /* add hardware recommended delay */
  345. udelay(2000);
  346. dp_write(catalog->exe_mode, io_data, DP_PHY_CFG, 0x19);
  347. /*
  348. * Make sure all the register writes are completed before
  349. * doing any other operation
  350. */
  351. wmb();
  352. if (!dp_catalog_ctrl_wait_for_phy_ready(catalog)) {
  353. rc = -EINVAL;
  354. goto lock_err;
  355. }
  356. io_data = catalog->io.dp_ln_tx0;
  357. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, 0x0a);
  358. io_data = catalog->io.dp_ln_tx1;
  359. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, 0x0a);
  360. io_data = catalog->io.dp_ln_tx0;
  361. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL_V420, 0x27);
  362. io_data = catalog->io.dp_ln_tx1;
  363. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL_V420, 0x27);
  364. io_data = catalog->io.dp_ln_tx0;
  365. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  366. io_data = catalog->io.dp_ln_tx1;
  367. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  368. /* Make sure the PHY register writes are done */
  369. wmb();
  370. lock_err:
  371. return rc;
  372. }
  373. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  374. {
  375. struct dp_catalog_private *catalog;
  376. struct dp_io_data *io_data;
  377. if (!ctrl) {
  378. DP_ERR("invalid input\n");
  379. return -EINVAL;
  380. }
  381. catalog = dp_catalog_get_priv(ctrl);
  382. io_data = catalog->io.dp_ahb;
  383. return dp_read(catalog->exe_mode, io_data, DP_HDCP_STATUS);
  384. }
  385. static void dp_catalog_panel_sdp_update(struct dp_catalog_panel *panel)
  386. {
  387. struct dp_catalog_private *catalog;
  388. struct dp_io_data *io_data;
  389. u32 sdp_cfg3_off = 0;
  390. if (panel->stream_id >= DP_STREAM_MAX) {
  391. pr_err("invalid stream_id:%d\n", panel->stream_id);
  392. return;
  393. }
  394. if (panel->stream_id == DP_STREAM_1)
  395. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  396. catalog = dp_catalog_get_priv(panel);
  397. io_data = catalog->io.dp_link;
  398. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  399. 0x01);
  400. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  401. 0x00);
  402. }
  403. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  404. struct dp_catalog_panel *panel)
  405. {
  406. struct dp_catalog_private *catalog;
  407. struct drm_msm_ext_hdr_metadata *hdr;
  408. struct dp_io_data *io_data;
  409. u32 header, parity, data, mst_offset = 0;
  410. u8 buf[SZ_64], off = 0;
  411. if (panel->stream_id >= DP_STREAM_MAX) {
  412. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  413. return;
  414. }
  415. if (panel->stream_id == DP_STREAM_1)
  416. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  417. catalog = dp_catalog_get_priv(panel);
  418. hdr = &panel->hdr_meta;
  419. io_data = catalog->io.dp_link;
  420. /* HEADER BYTE 1 */
  421. header = panel->dhdr_vsif_sdp.HB1;
  422. parity = dp_header_get_parity(header);
  423. data = ((header << HEADER_BYTE_1_BIT)
  424. | (parity << PARITY_BYTE_1_BIT));
  425. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_0 + mst_offset,
  426. data);
  427. memcpy(buf + off, &data, sizeof(data));
  428. off += sizeof(data);
  429. /* HEADER BYTE 2 */
  430. header = panel->dhdr_vsif_sdp.HB2;
  431. parity = dp_header_get_parity(header);
  432. data = ((header << HEADER_BYTE_2_BIT)
  433. | (parity << PARITY_BYTE_2_BIT));
  434. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  435. data);
  436. /* HEADER BYTE 3 */
  437. header = panel->dhdr_vsif_sdp.HB3;
  438. parity = dp_header_get_parity(header);
  439. data = ((header << HEADER_BYTE_3_BIT)
  440. | (parity << PARITY_BYTE_3_BIT));
  441. data |= dp_read(catalog->exe_mode, io_data,
  442. MMSS_DP_VSCEXT_1 + mst_offset);
  443. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  444. data);
  445. memcpy(buf + off, &data, sizeof(data));
  446. off += sizeof(data);
  447. print_hex_dump(KERN_DEBUG, "[drm-dp] VSCEXT: ",
  448. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  449. }
  450. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  451. struct dp_catalog_panel *panel)
  452. {
  453. struct dp_catalog_private *catalog;
  454. struct drm_msm_ext_hdr_metadata *hdr;
  455. struct dp_io_data *io_data;
  456. u32 header, parity, data, mst_offset = 0;
  457. u8 buf[SZ_64], off = 0;
  458. u32 const version = 0x01;
  459. u32 const length = 0x1a;
  460. if (panel->stream_id >= DP_STREAM_MAX) {
  461. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  462. return;
  463. }
  464. if (panel->stream_id == DP_STREAM_1)
  465. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  466. catalog = dp_catalog_get_priv(panel);
  467. hdr = &panel->hdr_meta;
  468. io_data = catalog->io.dp_link;
  469. /* HEADER BYTE 1 */
  470. header = panel->shdr_if_sdp.HB1;
  471. parity = dp_header_get_parity(header);
  472. data = ((header << HEADER_BYTE_1_BIT)
  473. | (parity << PARITY_BYTE_1_BIT));
  474. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_0 + mst_offset,
  475. data);
  476. memcpy(buf + off, &data, sizeof(data));
  477. off += sizeof(data);
  478. /* HEADER BYTE 2 */
  479. header = panel->shdr_if_sdp.HB2;
  480. parity = dp_header_get_parity(header);
  481. data = ((header << HEADER_BYTE_2_BIT)
  482. | (parity << PARITY_BYTE_2_BIT));
  483. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  484. data);
  485. /* HEADER BYTE 3 */
  486. header = panel->shdr_if_sdp.HB3;
  487. parity = dp_header_get_parity(header);
  488. data = ((header << HEADER_BYTE_3_BIT)
  489. | (parity << PARITY_BYTE_3_BIT));
  490. data |= dp_read(catalog->exe_mode, io_data,
  491. MMSS_DP_VSCEXT_1 + mst_offset);
  492. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  493. data);
  494. memcpy(buf + off, &data, sizeof(data));
  495. off += sizeof(data);
  496. data = version;
  497. data |= length << 8;
  498. data |= hdr->eotf << 16;
  499. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_2 + mst_offset,
  500. data);
  501. memcpy(buf + off, &data, sizeof(data));
  502. off += sizeof(data);
  503. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  504. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  505. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  506. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  507. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_3 + mst_offset,
  508. data);
  509. memcpy(buf + off, &data, sizeof(data));
  510. off += sizeof(data);
  511. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  512. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  513. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  514. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  515. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_4 + mst_offset,
  516. data);
  517. memcpy(buf + off, &data, sizeof(data));
  518. off += sizeof(data);
  519. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  520. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  521. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  522. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  523. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_5 + mst_offset,
  524. data);
  525. memcpy(buf + off, &data, sizeof(data));
  526. off += sizeof(data);
  527. data = (DP_GET_LSB(hdr->white_point_x) |
  528. (DP_GET_MSB(hdr->white_point_x) << 8) |
  529. (DP_GET_LSB(hdr->white_point_y) << 16) |
  530. (DP_GET_MSB(hdr->white_point_y) << 24));
  531. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_6 + mst_offset,
  532. data);
  533. memcpy(buf + off, &data, sizeof(data));
  534. off += sizeof(data);
  535. data = (DP_GET_LSB(hdr->max_luminance) |
  536. (DP_GET_MSB(hdr->max_luminance) << 8) |
  537. (DP_GET_LSB(hdr->min_luminance) << 16) |
  538. (DP_GET_MSB(hdr->min_luminance) << 24));
  539. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_7 + mst_offset,
  540. data);
  541. memcpy(buf + off, &data, sizeof(data));
  542. off += sizeof(data);
  543. data = (DP_GET_LSB(hdr->max_content_light_level) |
  544. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  545. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  546. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  547. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_8 + mst_offset,
  548. data);
  549. memcpy(buf + off, &data, sizeof(data));
  550. off += sizeof(data);
  551. data = 0;
  552. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_9 + mst_offset,
  553. data);
  554. memcpy(buf + off, &data, sizeof(data));
  555. off += sizeof(data);
  556. print_hex_dump(KERN_DEBUG, "[drm-dp] HDR: ",
  557. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  558. }
  559. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  560. {
  561. struct dp_catalog_private *catalog;
  562. struct dp_io_data *io_data;
  563. u32 header, parity, data, mst_offset = 0;
  564. u8 off = 0;
  565. u8 buf[SZ_128];
  566. if (!panel) {
  567. DP_ERR("invalid input\n");
  568. return;
  569. }
  570. if (panel->stream_id >= DP_STREAM_MAX) {
  571. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  572. return;
  573. }
  574. if (panel->stream_id == DP_STREAM_1)
  575. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  576. catalog = dp_catalog_get_priv(panel);
  577. io_data = catalog->io.dp_link;
  578. /* HEADER BYTE 1 */
  579. header = panel->vsc_colorimetry.header.HB1;
  580. parity = dp_header_get_parity(header);
  581. data = ((header << HEADER_BYTE_1_BIT)
  582. | (parity << PARITY_BYTE_1_BIT));
  583. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_0 + mst_offset,
  584. data);
  585. memcpy(buf + off, &data, sizeof(data));
  586. off += sizeof(data);
  587. /* HEADER BYTE 2 */
  588. header = panel->vsc_colorimetry.header.HB2;
  589. parity = dp_header_get_parity(header);
  590. data = ((header << HEADER_BYTE_2_BIT)
  591. | (parity << PARITY_BYTE_2_BIT));
  592. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  593. data);
  594. /* HEADER BYTE 3 */
  595. header = panel->vsc_colorimetry.header.HB3;
  596. parity = dp_header_get_parity(header);
  597. data = ((header << HEADER_BYTE_3_BIT)
  598. | (parity << PARITY_BYTE_3_BIT));
  599. data |= dp_read(catalog->exe_mode, io_data,
  600. MMSS_DP_GENERIC0_1 + mst_offset);
  601. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  602. data);
  603. memcpy(buf + off, &data, sizeof(data));
  604. off += sizeof(data);
  605. data = 0;
  606. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_2 + mst_offset,
  607. data);
  608. memcpy(buf + off, &data, sizeof(data));
  609. off += sizeof(data);
  610. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_3 + mst_offset,
  611. data);
  612. memcpy(buf + off, &data, sizeof(data));
  613. off += sizeof(data);
  614. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_4 + mst_offset,
  615. data);
  616. memcpy(buf + off, &data, sizeof(data));
  617. off += sizeof(data);
  618. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_5 + mst_offset,
  619. data);
  620. memcpy(buf + off, &data, sizeof(data));
  621. off += sizeof(data);
  622. data = (panel->vsc_colorimetry.data[16] & 0xFF) |
  623. ((panel->vsc_colorimetry.data[17] & 0xFF) << 8) |
  624. ((panel->vsc_colorimetry.data[18] & 0x7) << 16);
  625. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_6 + mst_offset,
  626. data);
  627. memcpy(buf + off, &data, sizeof(data));
  628. off += sizeof(data);
  629. data = 0;
  630. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_7 + mst_offset,
  631. data);
  632. memcpy(buf + off, &data, sizeof(data));
  633. off += sizeof(data);
  634. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_8 + mst_offset,
  635. data);
  636. memcpy(buf + off, &data, sizeof(data));
  637. off += sizeof(data);
  638. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_9 + mst_offset,
  639. data);
  640. memcpy(buf + off, &data, sizeof(data));
  641. off += sizeof(data);
  642. print_hex_dump(KERN_DEBUG, "[drm-dp] VSC: ",
  643. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  644. }
  645. static void dp_catalog_panel_config_sdp(struct dp_catalog_panel *panel,
  646. bool en)
  647. {
  648. struct dp_catalog_private *catalog;
  649. struct dp_io_data *io_data;
  650. u32 cfg, cfg2;
  651. u32 sdp_cfg_off = 0;
  652. u32 sdp_cfg2_off = 0;
  653. if (panel->stream_id >= DP_STREAM_MAX) {
  654. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  655. return;
  656. }
  657. catalog = dp_catalog_get_priv(panel);
  658. io_data = catalog->io.dp_link;
  659. if (panel->stream_id == DP_STREAM_1) {
  660. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  661. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  662. }
  663. cfg = dp_read(catalog->exe_mode, io_data,
  664. MMSS_DP_SDP_CFG + sdp_cfg_off);
  665. cfg2 = dp_read(catalog->exe_mode, io_data,
  666. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  667. if (en) {
  668. /* GEN0_SDP_EN */
  669. cfg |= BIT(17);
  670. dp_write(catalog->exe_mode, io_data,
  671. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  672. /* GENERIC0_SDPSIZE */
  673. cfg2 |= BIT(16);
  674. dp_write(catalog->exe_mode, io_data,
  675. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  676. /* setup the GENERIC0 in case of en = true */
  677. dp_catalog_panel_setup_vsc_sdp(panel);
  678. } else {
  679. /* GEN0_SDP_EN */
  680. cfg &= ~BIT(17);
  681. dp_write(catalog->exe_mode, io_data,
  682. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  683. /* GENERIC0_SDPSIZE */
  684. cfg2 &= ~BIT(16);
  685. dp_write(catalog->exe_mode, io_data,
  686. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  687. }
  688. dp_catalog_panel_sdp_update(panel);
  689. }
  690. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  691. {
  692. struct dp_catalog_private *catalog;
  693. struct dp_io_data *io_data;
  694. u32 reg_offset = 0;
  695. if (!panel) {
  696. pr_err("invalid input\n");
  697. return;
  698. }
  699. if (panel->stream_id >= DP_STREAM_MAX) {
  700. pr_err("invalid stream_id:%d\n", panel->stream_id);
  701. return;
  702. }
  703. catalog = dp_catalog_get_priv(panel);
  704. io_data = catalog->io.dp_link;
  705. if (panel->stream_id == DP_STREAM_1)
  706. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  707. DP_DEBUG("misc settings = 0x%x\n", panel->misc_val);
  708. dp_write(catalog->exe_mode, io_data, DP_MISC1_MISC0 + reg_offset,
  709. panel->misc_val);
  710. }
  711. static int dp_catalog_panel_set_colorspace(struct dp_catalog_panel *panel,
  712. bool vsc_supported)
  713. {
  714. struct dp_catalog_private *catalog;
  715. struct dp_io_data *io_data;
  716. if (!panel) {
  717. pr_err("invalid input\n");
  718. return -EINVAL;
  719. }
  720. if (panel->stream_id >= DP_STREAM_MAX) {
  721. pr_err("invalid stream_id:%d\n", panel->stream_id);
  722. return -EINVAL;
  723. }
  724. catalog = dp_catalog_get_priv(panel);
  725. io_data = catalog->io.dp_link;
  726. if (vsc_supported) {
  727. dp_catalog_panel_setup_vsc_sdp(panel);
  728. dp_catalog_panel_sdp_update(panel);
  729. } else
  730. dp_catalog_panel_config_misc(panel);
  731. return 0;
  732. }
  733. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  734. u32 dhdr_max_pkts, bool flush)
  735. {
  736. struct dp_catalog_private *catalog;
  737. struct dp_io_data *io_data;
  738. u32 cfg, cfg2, cfg4, misc;
  739. u32 sdp_cfg_off = 0;
  740. u32 sdp_cfg2_off = 0;
  741. u32 sdp_cfg4_off = 0;
  742. u32 misc1_misc0_off = 0;
  743. if (!panel) {
  744. DP_ERR("invalid input\n");
  745. return;
  746. }
  747. if (panel->stream_id >= DP_STREAM_MAX) {
  748. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  749. return;
  750. }
  751. catalog = dp_catalog_get_priv(panel);
  752. io_data = catalog->io.dp_link;
  753. if (panel->stream_id == DP_STREAM_1) {
  754. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  755. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  756. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  757. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  758. }
  759. cfg = dp_read(catalog->exe_mode, io_data,
  760. MMSS_DP_SDP_CFG + sdp_cfg_off);
  761. cfg2 = dp_read(catalog->exe_mode, io_data,
  762. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  763. misc = dp_read(catalog->exe_mode, io_data,
  764. DP_MISC1_MISC0 + misc1_misc0_off);
  765. if (en) {
  766. if (dhdr_max_pkts) {
  767. /* VSCEXT_SDP_EN */
  768. cfg |= BIT(16);
  769. /* DHDR_EN, DHDR_PACKET_LIMIT */
  770. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  771. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  772. + sdp_cfg4_off, cfg4);
  773. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  774. }
  775. /* GEN2_SDP_EN */
  776. cfg |= BIT(19);
  777. dp_write(catalog->exe_mode, io_data,
  778. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  779. /* GENERIC2_SDPSIZE */
  780. cfg2 |= BIT(20);
  781. dp_write(catalog->exe_mode, io_data,
  782. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  783. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  784. if (panel->hdr_meta.eotf)
  785. DP_DEBUG("Enabled\n");
  786. else
  787. DP_DEBUG("Reset\n");
  788. } else {
  789. /* VSCEXT_SDP_ENG */
  790. cfg &= ~BIT(16) & ~BIT(19);
  791. dp_write(catalog->exe_mode, io_data,
  792. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  793. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  794. cfg2 &= ~BIT(20);
  795. dp_write(catalog->exe_mode, io_data,
  796. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  797. /* DHDR_EN, DHDR_PACKET_LIMIT */
  798. cfg4 = 0;
  799. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  800. + sdp_cfg4_off, cfg4);
  801. DP_DEBUG("Disabled\n");
  802. }
  803. if (flush) {
  804. DP_DEBUG("flushing HDR metadata\n");
  805. dp_catalog_panel_sdp_update(panel);
  806. }
  807. }
  808. static void dp_catalog_panel_update_transfer_unit(
  809. struct dp_catalog_panel *panel)
  810. {
  811. struct dp_catalog_private *catalog;
  812. struct dp_io_data *io_data;
  813. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  814. DP_ERR("invalid input\n");
  815. return;
  816. }
  817. catalog = dp_catalog_get_priv(panel);
  818. io_data = catalog->io.dp_link;
  819. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY,
  820. panel->valid_boundary);
  821. dp_write(catalog->exe_mode, io_data, DP_TU, panel->dp_tu);
  822. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY_2,
  823. panel->valid_boundary2);
  824. }
  825. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  826. {
  827. struct dp_catalog_private *catalog;
  828. struct dp_io_data *io_data;
  829. if (!ctrl) {
  830. DP_ERR("invalid input\n");
  831. return;
  832. }
  833. catalog = dp_catalog_get_priv(ctrl);
  834. io_data = catalog->io.dp_link;
  835. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, state);
  836. /* make sure to change the hw state */
  837. wmb();
  838. }
  839. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  840. {
  841. struct dp_catalog_private *catalog;
  842. struct dp_io_data *io_data;
  843. u32 cfg;
  844. if (!ctrl) {
  845. DP_ERR("invalid input\n");
  846. return;
  847. }
  848. catalog = dp_catalog_get_priv(ctrl);
  849. io_data = catalog->io.dp_link;
  850. cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL);
  851. cfg &= ~(BIT(4) | BIT(5));
  852. cfg |= (ln_cnt - 1) << 4;
  853. dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg);
  854. cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  855. cfg |= 0x02000000;
  856. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, cfg);
  857. DP_DEBUG("DP_MAINLINK_CTRL=0x%x\n", cfg);
  858. }
  859. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  860. u32 cfg)
  861. {
  862. struct dp_catalog_private *catalog;
  863. struct dp_io_data *io_data;
  864. u32 strm_reg_off = 0, mainlink_ctrl;
  865. if (!panel) {
  866. DP_ERR("invalid input\n");
  867. return;
  868. }
  869. if (panel->stream_id >= DP_STREAM_MAX) {
  870. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  871. return;
  872. }
  873. catalog = dp_catalog_get_priv(panel);
  874. io_data = catalog->io.dp_link;
  875. if (panel->stream_id == DP_STREAM_1)
  876. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  877. DP_DEBUG("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  878. dp_write(catalog->exe_mode, io_data,
  879. DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  880. mainlink_ctrl = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  881. if (panel->stream_id == DP_STREAM_0)
  882. io_data = catalog->io.dp_p0;
  883. else if (panel->stream_id == DP_STREAM_1)
  884. io_data = catalog->io.dp_p1;
  885. if (mainlink_ctrl & BIT(8))
  886. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  887. 0x01);
  888. else
  889. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  890. 0x00);
  891. }
  892. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  893. bool ack)
  894. {
  895. struct dp_catalog_private *catalog;
  896. struct dp_io_data *io_data;
  897. u32 dsc_dto;
  898. if (!panel) {
  899. DP_ERR("invalid input\n");
  900. return;
  901. }
  902. if (panel->stream_id >= DP_STREAM_MAX) {
  903. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  904. return;
  905. }
  906. catalog = dp_catalog_get_priv(panel);
  907. io_data = catalog->io.dp_link;
  908. switch (panel->stream_id) {
  909. case DP_STREAM_0:
  910. io_data = catalog->io.dp_p0;
  911. break;
  912. case DP_STREAM_1:
  913. io_data = catalog->io.dp_p1;
  914. break;
  915. default:
  916. DP_ERR("invalid stream id\n");
  917. return;
  918. }
  919. dsc_dto = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  920. if (ack)
  921. dsc_dto = BIT(1);
  922. else
  923. dsc_dto &= ~BIT(1);
  924. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, dsc_dto);
  925. }
  926. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  927. bool flipped, char *lane_map)
  928. {
  929. struct dp_catalog_private *catalog;
  930. struct dp_io_data *io_data;
  931. if (!ctrl) {
  932. DP_ERR("invalid input\n");
  933. return;
  934. }
  935. catalog = dp_catalog_get_priv(ctrl);
  936. io_data = catalog->io.dp_link;
  937. dp_write(catalog->exe_mode, io_data, DP_LOGICAL2PHYSICAL_LANE_MAPPING,
  938. 0xe4);
  939. }
  940. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  941. u8 ln_pnswap)
  942. {
  943. struct dp_catalog_private *catalog;
  944. struct dp_io_data *io_data;
  945. u32 cfg0, cfg1;
  946. catalog = dp_catalog_get_priv(ctrl);
  947. cfg0 = 0x0a;
  948. cfg1 = 0x0a;
  949. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  950. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  951. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  952. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  953. io_data = catalog->io.dp_ln_tx0;
  954. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0);
  955. io_data = catalog->io.dp_ln_tx1;
  956. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1);
  957. }
  958. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  959. bool enable)
  960. {
  961. u32 mainlink_ctrl, reg;
  962. struct dp_catalog_private *catalog;
  963. struct dp_io_data *io_data;
  964. if (!ctrl) {
  965. DP_ERR("invalid input\n");
  966. return;
  967. }
  968. catalog = dp_catalog_get_priv(ctrl);
  969. io_data = catalog->io.dp_link;
  970. if (enable) {
  971. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  972. mainlink_ctrl = reg & ~(0x03);
  973. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  974. mainlink_ctrl);
  975. wmb(); /* make sure mainlink is turned off before reset */
  976. mainlink_ctrl = reg | 0x02;
  977. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  978. mainlink_ctrl);
  979. wmb(); /* make sure mainlink entered reset */
  980. mainlink_ctrl = reg & ~(0x03);
  981. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  982. mainlink_ctrl);
  983. wmb(); /* make sure mainlink reset done */
  984. mainlink_ctrl = reg | 0x01;
  985. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  986. mainlink_ctrl);
  987. wmb(); /* make sure mainlink turned on */
  988. } else {
  989. mainlink_ctrl = dp_read(catalog->exe_mode, io_data,
  990. DP_MAINLINK_CTRL);
  991. mainlink_ctrl &= ~BIT(0);
  992. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  993. mainlink_ctrl);
  994. }
  995. }
  996. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  997. u32 rate, u32 stream_rate_khz)
  998. {
  999. u32 pixel_m, pixel_n;
  1000. u32 mvid, nvid;
  1001. u32 const nvid_fixed = 0x8000;
  1002. u32 const link_rate_hbr2 = 540000;
  1003. u32 const link_rate_hbr3 = 810000;
  1004. struct dp_catalog_private *catalog;
  1005. struct dp_io_data *io_data;
  1006. u32 strm_reg_off = 0;
  1007. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  1008. if (!panel) {
  1009. DP_ERR("invalid input\n");
  1010. return;
  1011. }
  1012. if (panel->stream_id >= DP_STREAM_MAX) {
  1013. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1014. return;
  1015. }
  1016. catalog = dp_catalog_get_priv(panel);
  1017. io_data = catalog->io.dp_mmss_cc;
  1018. if (panel->stream_id == DP_STREAM_1)
  1019. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  1020. pixel_m = dp_read(catalog->exe_mode, io_data,
  1021. MMSS_DP_PIXEL_M + strm_reg_off);
  1022. pixel_n = dp_read(catalog->exe_mode, io_data,
  1023. MMSS_DP_PIXEL_N + strm_reg_off);
  1024. DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  1025. mvid = (pixel_m & 0xFFFF) * 5;
  1026. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  1027. if (nvid < nvid_fixed) {
  1028. u32 temp;
  1029. temp = (nvid_fixed / nvid) * nvid;
  1030. mvid = (nvid_fixed / nvid) * mvid;
  1031. nvid = temp;
  1032. }
  1033. DP_DEBUG("rate = %d\n", rate);
  1034. if (panel->widebus_en)
  1035. mvid <<= 1;
  1036. if (link_rate_hbr2 == rate)
  1037. nvid *= 2;
  1038. if (link_rate_hbr3 == rate)
  1039. nvid *= 3;
  1040. io_data = catalog->io.dp_link;
  1041. if (panel->stream_id == DP_STREAM_1) {
  1042. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  1043. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  1044. }
  1045. DP_DEBUG("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  1046. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID + mvid_reg_off,
  1047. mvid);
  1048. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID + nvid_reg_off,
  1049. nvid);
  1050. }
  1051. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  1052. u32 pattern)
  1053. {
  1054. int bit, cnt = 10;
  1055. u32 data;
  1056. const u32 link_training_offset = 3;
  1057. struct dp_catalog_private *catalog;
  1058. struct dp_io_data *io_data;
  1059. if (!ctrl) {
  1060. DP_ERR("invalid input\n");
  1061. return;
  1062. }
  1063. catalog = dp_catalog_get_priv(ctrl);
  1064. io_data = catalog->io.dp_link;
  1065. switch (pattern) {
  1066. case DP_TRAINING_PATTERN_4:
  1067. bit = 3;
  1068. break;
  1069. case DP_TRAINING_PATTERN_3:
  1070. case DP_TRAINING_PATTERN_2:
  1071. case DP_TRAINING_PATTERN_1:
  1072. bit = pattern - 1;
  1073. break;
  1074. default:
  1075. DP_ERR("invalid pattern\n");
  1076. return;
  1077. }
  1078. DP_DEBUG("hw: bit=%d train=%d\n", bit, pattern);
  1079. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, BIT(bit));
  1080. bit += link_training_offset;
  1081. while (cnt--) {
  1082. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1083. if (data & BIT(bit))
  1084. break;
  1085. }
  1086. if (cnt == 0)
  1087. DP_ERR("set link_train=%d failed\n", pattern);
  1088. }
  1089. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  1090. {
  1091. struct dp_catalog_private *catalog;
  1092. struct dp_io_data *io_data;
  1093. if (!ctrl) {
  1094. DP_ERR("invalid input\n");
  1095. return;
  1096. }
  1097. catalog = dp_catalog_get_priv(ctrl);
  1098. io_data = catalog->io.usb3_dp_com;
  1099. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  1100. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  1101. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x01);
  1102. /* make sure usb3 com phy software reset is done */
  1103. wmb();
  1104. if (!flip) { /* CC1 */
  1105. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  1106. 0x02);
  1107. } else { /* CC2 */
  1108. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  1109. 0x03);
  1110. }
  1111. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SWI_CTRL, 0x00);
  1112. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x00);
  1113. /* make sure the software reset is done */
  1114. wmb();
  1115. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  1116. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  1117. /* make sure phy is brought out of reset */
  1118. wmb();
  1119. }
  1120. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
  1121. bool enable)
  1122. {
  1123. struct dp_catalog_private *catalog;
  1124. struct dp_io_data *io_data;
  1125. if (!panel) {
  1126. DP_ERR("invalid input\n");
  1127. return;
  1128. }
  1129. if (panel->stream_id >= DP_STREAM_MAX) {
  1130. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1131. return;
  1132. }
  1133. catalog = dp_catalog_get_priv(panel);
  1134. if (panel->stream_id == DP_STREAM_0)
  1135. io_data = catalog->io.dp_p0;
  1136. else if (panel->stream_id == DP_STREAM_1)
  1137. io_data = catalog->io.dp_p1;
  1138. if (!enable) {
  1139. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL,
  1140. 0x0);
  1141. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x0);
  1142. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN,
  1143. 0x0);
  1144. wmb(); /* ensure Timing generator is turned off */
  1145. return;
  1146. }
  1147. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, 0x0);
  1148. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_HSYNC_CTL,
  1149. panel->hsync_ctl);
  1150. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F0,
  1151. panel->vsync_period * panel->hsync_period);
  1152. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  1153. panel->v_sync_width * panel->hsync_period);
  1154. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  1155. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1,
  1156. 0);
  1157. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_HCTL,
  1158. panel->display_hctl);
  1159. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_HCTL, 0);
  1160. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F0,
  1161. panel->display_v_start);
  1162. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F0,
  1163. panel->display_v_end);
  1164. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F1, 0);
  1165. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1166. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1167. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1168. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1169. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1170. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_POLARITY_CTL, 0);
  1171. wmb(); /* ensure TPG registers are programmed */
  1172. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL, 0x100);
  1173. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1174. wmb(); /* ensure TPG config is programmed */
  1175. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x1);
  1176. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN, 0x1);
  1177. wmb(); /* ensure Timing generator is turned on */
  1178. }
  1179. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1180. {
  1181. struct dp_catalog_private *catalog;
  1182. struct dp_io_data *io_data;
  1183. u32 reg, offset;
  1184. int i;
  1185. if (!panel) {
  1186. DP_ERR("invalid input\n");
  1187. return;
  1188. }
  1189. if (panel->stream_id >= DP_STREAM_MAX) {
  1190. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1191. return;
  1192. }
  1193. catalog = dp_catalog_get_priv(panel);
  1194. if (panel->stream_id == DP_STREAM_0)
  1195. io_data = catalog->io.dp_p0;
  1196. else
  1197. io_data = catalog->io.dp_p1;
  1198. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO_COUNT,
  1199. panel->dsc.dto_count);
  1200. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  1201. if (panel->dsc.dto_en) {
  1202. reg |= BIT(0);
  1203. reg |= (panel->dsc.dto_n << 8);
  1204. reg |= (panel->dsc.dto_d << 16);
  1205. }
  1206. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, reg);
  1207. io_data = catalog->io.dp_link;
  1208. if (panel->stream_id == DP_STREAM_0)
  1209. offset = 0;
  1210. else
  1211. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1212. dp_write(catalog->exe_mode, io_data, DP_PPS_HB_0_3 + offset, 0x7F1000);
  1213. dp_write(catalog->exe_mode, io_data, DP_PPS_PB_0_3 + offset, 0xA22300);
  1214. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1215. dp_write(catalog->exe_mode, io_data,
  1216. DP_PPS_PB_4_7 + (i << 2) + offset,
  1217. panel->dsc.parity_word[i]);
  1218. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1219. dp_write(catalog->exe_mode, io_data,
  1220. DP_PPS_PPS_0_3 + (i << 2) + offset,
  1221. panel->dsc.pps_word[i]);
  1222. reg = 0;
  1223. if (panel->dsc.dsc_en) {
  1224. reg = BIT(0);
  1225. reg |= (panel->dsc.eol_byte_num << 3);
  1226. reg |= (panel->dsc.slice_per_pkt << 5);
  1227. reg |= (panel->dsc.bytes_per_pkt << 16);
  1228. reg |= (panel->dsc.be_in_lane << 10);
  1229. }
  1230. dp_write(catalog->exe_mode, io_data,
  1231. DP_COMPRESSION_MODE_CTRL + offset, reg);
  1232. DP_DEBUG("compression:0x%x for stream:%d\n",
  1233. reg, panel->stream_id);
  1234. }
  1235. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1236. enum dp_flush_bit flush_bit)
  1237. {
  1238. struct dp_catalog_private *catalog;
  1239. struct dp_io_data *io_data;
  1240. u32 dp_flush, offset;
  1241. if (!panel) {
  1242. DP_ERR("invalid input\n");
  1243. return;
  1244. }
  1245. if (panel->stream_id >= DP_STREAM_MAX) {
  1246. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1247. return;
  1248. }
  1249. catalog = dp_catalog_get_priv(panel);
  1250. io_data = catalog->io.dp_link;
  1251. if (panel->stream_id == DP_STREAM_0)
  1252. offset = 0;
  1253. else
  1254. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1255. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1256. dp_flush |= BIT(flush_bit);
  1257. dp_write(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset, dp_flush);
  1258. }
  1259. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1260. {
  1261. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1262. DP_DEBUG("pps flush for stream:%d\n", panel->stream_id);
  1263. }
  1264. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1265. {
  1266. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1267. DP_DEBUG("dhdr flush for stream:%d\n", panel->stream_id);
  1268. }
  1269. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1270. {
  1271. struct dp_catalog_private *catalog;
  1272. struct dp_io_data *io_data;
  1273. u32 dp_flush, offset;
  1274. if (panel->stream_id >= DP_STREAM_MAX) {
  1275. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1276. return false;
  1277. }
  1278. catalog = dp_catalog_get_priv(panel);
  1279. io_data = catalog->io.dp_link;
  1280. if (panel->stream_id == DP_STREAM_0)
  1281. offset = 0;
  1282. else
  1283. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1284. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1285. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1286. }
  1287. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1288. {
  1289. u32 sw_reset;
  1290. struct dp_catalog_private *catalog;
  1291. struct dp_io_data *io_data;
  1292. if (!ctrl) {
  1293. DP_ERR("invalid input\n");
  1294. return;
  1295. }
  1296. catalog = dp_catalog_get_priv(ctrl);
  1297. io_data = catalog->io.dp_ahb;
  1298. sw_reset = dp_read(catalog->exe_mode, io_data, DP_SW_RESET);
  1299. sw_reset |= BIT(0);
  1300. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1301. usleep_range(1000, 1010); /* h/w recommended delay */
  1302. sw_reset &= ~BIT(0);
  1303. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1304. }
  1305. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1306. {
  1307. u32 data;
  1308. int cnt = 10;
  1309. struct dp_catalog_private *catalog;
  1310. struct dp_io_data *io_data;
  1311. if (!ctrl) {
  1312. DP_ERR("invalid input\n");
  1313. goto end;
  1314. }
  1315. catalog = dp_catalog_get_priv(ctrl);
  1316. io_data = catalog->io.dp_link;
  1317. while (--cnt) {
  1318. /* DP_MAINLINK_READY */
  1319. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1320. if (data & BIT(0))
  1321. return true;
  1322. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1323. }
  1324. DP_ERR("mainlink not ready\n");
  1325. end:
  1326. return false;
  1327. }
  1328. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1329. bool enable)
  1330. {
  1331. struct dp_catalog_private *catalog;
  1332. struct dp_io_data *io_data;
  1333. if (!ctrl) {
  1334. DP_ERR("invalid input\n");
  1335. return;
  1336. }
  1337. catalog = dp_catalog_get_priv(ctrl);
  1338. io_data = catalog->io.dp_ahb;
  1339. if (enable) {
  1340. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS,
  1341. DP_INTR_MASK1);
  1342. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2,
  1343. DP_INTR_MASK2);
  1344. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5,
  1345. DP_INTR_MASK5);
  1346. } else {
  1347. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, 0x00);
  1348. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, 0x00);
  1349. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, 0x00);
  1350. }
  1351. }
  1352. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1353. {
  1354. u32 ack = 0;
  1355. struct dp_catalog_private *catalog;
  1356. struct dp_io_data *io_data;
  1357. if (!ctrl) {
  1358. DP_ERR("invalid input\n");
  1359. return;
  1360. }
  1361. catalog = dp_catalog_get_priv(ctrl);
  1362. io_data = catalog->io.dp_ahb;
  1363. ctrl->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS2);
  1364. ctrl->isr &= ~DP_INTR_MASK2;
  1365. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1366. ack <<= 1;
  1367. ack |= DP_INTR_MASK2;
  1368. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, ack);
  1369. ctrl->isr5 = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS5);
  1370. ctrl->isr5 &= ~DP_INTR_MASK5;
  1371. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1372. ack <<= 1;
  1373. ack |= DP_INTR_MASK5;
  1374. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, ack);
  1375. }
  1376. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1377. {
  1378. struct dp_catalog_private *catalog;
  1379. struct dp_io_data *io_data;
  1380. if (!ctrl) {
  1381. DP_ERR("invalid input\n");
  1382. return;
  1383. }
  1384. catalog = dp_catalog_get_priv(ctrl);
  1385. io_data = catalog->io.dp_ahb;
  1386. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1387. usleep_range(1000, 1010); /* h/w recommended delay */
  1388. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x0);
  1389. wmb(); /* make sure PHY reset done */
  1390. }
  1391. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1392. bool flipped, u8 ln_cnt)
  1393. {
  1394. u32 info = 0x0;
  1395. struct dp_catalog_private *catalog;
  1396. struct dp_io_data *io_data;
  1397. u8 orientation = BIT(!!flipped);
  1398. if (!ctrl) {
  1399. DP_ERR("invalid input\n");
  1400. return;
  1401. }
  1402. catalog = dp_catalog_get_priv(ctrl);
  1403. io_data = catalog->io.dp_phy;
  1404. info |= (ln_cnt & 0x0F);
  1405. info |= ((orientation & 0x0F) << 4);
  1406. DP_DEBUG("Shared Info = 0x%x\n", info);
  1407. dp_write(catalog->exe_mode, io_data, DP_PHY_SPARE0, info);
  1408. }
  1409. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1410. u8 v_level, u8 p_level, bool high)
  1411. {
  1412. struct dp_catalog_private *catalog;
  1413. struct dp_io_data *io_data;
  1414. u8 value0, value1;
  1415. if (!ctrl) {
  1416. DP_ERR("invalid input\n");
  1417. return;
  1418. }
  1419. catalog = dp_catalog_get_priv(ctrl);
  1420. DP_DEBUG("hw: v=%d p=%d\n", v_level, p_level);
  1421. value0 = vm_voltage_swing[v_level][p_level];
  1422. value1 = vm_pre_emphasis[v_level][p_level];
  1423. /* program default setting first */
  1424. io_data = catalog->io.dp_ln_tx0;
  1425. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1426. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1427. io_data = catalog->io.dp_ln_tx1;
  1428. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1429. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1430. /* Enable MUX to use Cursor values from these registers */
  1431. value0 |= BIT(5);
  1432. value1 |= BIT(5);
  1433. /* Configure host and panel only if both values are allowed */
  1434. if (value0 != 0xFF && value1 != 0xFF) {
  1435. io_data = catalog->io.dp_ln_tx0;
  1436. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1437. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1438. value1);
  1439. io_data = catalog->io.dp_ln_tx1;
  1440. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1441. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1442. value1);
  1443. DP_DEBUG("hw: vx_value=0x%x px_value=0x%x\n",
  1444. value0, value1);
  1445. } else {
  1446. DP_ERR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1447. v_level, value0, p_level, value1);
  1448. }
  1449. }
  1450. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1451. u32 pattern)
  1452. {
  1453. struct dp_catalog_private *catalog;
  1454. u32 value = 0x0;
  1455. struct dp_io_data *io_data = NULL;
  1456. if (!ctrl) {
  1457. DP_ERR("invalid input\n");
  1458. return;
  1459. }
  1460. catalog = dp_catalog_get_priv(ctrl);
  1461. io_data = catalog->io.dp_link;
  1462. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x0);
  1463. switch (pattern) {
  1464. case DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING:
  1465. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x1);
  1466. break;
  1467. case DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT:
  1468. value &= ~(1 << 16);
  1469. dp_write(catalog->exe_mode, io_data,
  1470. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1471. value |= 0xFC;
  1472. dp_write(catalog->exe_mode, io_data,
  1473. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1474. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1475. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1476. break;
  1477. case DP_TEST_PHY_PATTERN_PRBS7:
  1478. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x20);
  1479. break;
  1480. case DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN:
  1481. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x40);
  1482. /* 00111110000011111000001111100000 */
  1483. dp_write(catalog->exe_mode, io_data,
  1484. DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1485. /* 00001111100000111110000011111000 */
  1486. dp_write(catalog->exe_mode, io_data,
  1487. DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1488. /* 1111100000111110 */
  1489. dp_write(catalog->exe_mode, io_data,
  1490. DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1491. break;
  1492. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_1:
  1493. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1494. value &= ~BIT(4);
  1495. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1496. value = BIT(16);
  1497. dp_write(catalog->exe_mode, io_data,
  1498. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1499. value |= 0xFC;
  1500. dp_write(catalog->exe_mode, io_data,
  1501. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1502. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1503. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1504. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1505. value |= BIT(0);
  1506. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1507. break;
  1508. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_3:
  1509. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, 0x11);
  1510. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x8);
  1511. break;
  1512. default:
  1513. DP_DEBUG("No valid test pattern requested: 0x%x\n", pattern);
  1514. return;
  1515. }
  1516. /* Make sure the test pattern is programmed in the hardware */
  1517. wmb();
  1518. }
  1519. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1520. {
  1521. struct dp_catalog_private *catalog;
  1522. struct dp_io_data *io_data = NULL;
  1523. if (!ctrl) {
  1524. DP_ERR("invalid input\n");
  1525. return 0;
  1526. }
  1527. catalog = dp_catalog_get_priv(ctrl);
  1528. io_data = catalog->io.dp_link;
  1529. return dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1530. }
  1531. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1532. bool enable)
  1533. {
  1534. struct dp_catalog_private *catalog;
  1535. struct dp_io_data *io_data = NULL;
  1536. u32 reg;
  1537. if (!ctrl) {
  1538. DP_ERR("invalid input\n");
  1539. return;
  1540. }
  1541. catalog = dp_catalog_get_priv(ctrl);
  1542. io_data = catalog->io.dp_link;
  1543. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1544. /*
  1545. * fec_en = BIT(12)
  1546. * fec_seq_mode = BIT(22)
  1547. * sde_flush = BIT(23) | BIT(24)
  1548. * fb_boundary_sel = BIT(25)
  1549. */
  1550. if (enable)
  1551. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1552. else
  1553. reg &= ~BIT(12);
  1554. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1555. /* make sure mainlink configuration is updated with fec sequence */
  1556. wmb();
  1557. }
  1558. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1559. char *name, u8 **out_buf, u32 *out_buf_len)
  1560. {
  1561. int ret = 0;
  1562. u8 *buf;
  1563. u32 len;
  1564. struct dp_io_data *io_data;
  1565. struct dp_catalog_private *catalog;
  1566. struct dp_parser *parser;
  1567. if (!dp_catalog) {
  1568. DP_ERR("invalid input\n");
  1569. return -EINVAL;
  1570. }
  1571. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1572. dp_catalog);
  1573. parser = catalog->parser;
  1574. parser->get_io_buf(parser, name);
  1575. io_data = parser->get_io(parser, name);
  1576. if (!io_data) {
  1577. DP_ERR("IO %s not found\n", name);
  1578. ret = -EINVAL;
  1579. goto end;
  1580. }
  1581. buf = io_data->buf;
  1582. len = io_data->io.len;
  1583. if (!buf || !len) {
  1584. DP_ERR("no buffer available\n");
  1585. ret = -ENOMEM;
  1586. goto end;
  1587. }
  1588. if (!strcmp(catalog->exe_mode, "hw") ||
  1589. !strcmp(catalog->exe_mode, "all")) {
  1590. u32 i, data;
  1591. u32 const rowsize = 4;
  1592. void __iomem *addr = io_data->io.base;
  1593. memset(buf, 0, len);
  1594. for (i = 0; i < len / rowsize; i++) {
  1595. data = readl_relaxed(addr);
  1596. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1597. addr += rowsize;
  1598. }
  1599. }
  1600. *out_buf = buf;
  1601. *out_buf_len = len;
  1602. end:
  1603. if (ret)
  1604. parser->clear_io_buf(parser);
  1605. return ret;
  1606. }
  1607. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1608. bool enable)
  1609. {
  1610. struct dp_catalog_private *catalog;
  1611. struct dp_io_data *io_data = NULL;
  1612. u32 reg;
  1613. if (!ctrl) {
  1614. DP_ERR("invalid input\n");
  1615. return;
  1616. }
  1617. catalog = dp_catalog_get_priv(ctrl);
  1618. io_data = catalog->io.dp_link;
  1619. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1620. if (enable)
  1621. reg |= (0x04000100);
  1622. else
  1623. reg &= ~(0x04000100);
  1624. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1625. /* make sure mainlink MST configuration is updated */
  1626. wmb();
  1627. }
  1628. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1629. {
  1630. struct dp_catalog_private *catalog;
  1631. struct dp_io_data *io_data = NULL;
  1632. if (!ctrl) {
  1633. DP_ERR("invalid input\n");
  1634. return;
  1635. }
  1636. catalog = dp_catalog_get_priv(ctrl);
  1637. io_data = catalog->io.dp_link;
  1638. dp_write(catalog->exe_mode, io_data, DP_MST_ACT, 0x1);
  1639. /* make sure ACT signal is performed */
  1640. wmb();
  1641. }
  1642. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1643. bool *sts)
  1644. {
  1645. struct dp_catalog_private *catalog;
  1646. struct dp_io_data *io_data = NULL;
  1647. u32 reg;
  1648. if (!ctrl || !sts) {
  1649. DP_ERR("invalid input\n");
  1650. return;
  1651. }
  1652. *sts = false;
  1653. catalog = dp_catalog_get_priv(ctrl);
  1654. io_data = catalog->io.dp_link;
  1655. reg = dp_read(catalog->exe_mode, io_data, DP_MST_ACT);
  1656. if (!reg)
  1657. *sts = true;
  1658. }
  1659. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1660. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1661. {
  1662. struct dp_catalog_private *catalog;
  1663. struct dp_io_data *io_data = NULL;
  1664. u32 i, slot_reg_1, slot_reg_2, slot;
  1665. u32 reg_off = 0;
  1666. int const num_slots_per_reg = 32;
  1667. if (!ctrl || ch >= DP_STREAM_MAX) {
  1668. DP_ERR("invalid input. ch %d\n", ch);
  1669. return;
  1670. }
  1671. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1672. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1673. DP_ERR("invalid slots start %d, tot %d\n",
  1674. ch_start_slot, tot_slot_cnt);
  1675. return;
  1676. }
  1677. catalog = dp_catalog_get_priv(ctrl);
  1678. io_data = catalog->io.dp_link;
  1679. DP_DEBUG("ch %d, start_slot %d, tot_slot %d\n",
  1680. ch, ch_start_slot, tot_slot_cnt);
  1681. if (ch == DP_STREAM_1)
  1682. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1683. slot_reg_1 = 0;
  1684. slot_reg_2 = 0;
  1685. if (ch_start_slot && tot_slot_cnt) {
  1686. ch_start_slot--;
  1687. for (i = 0; i < tot_slot_cnt; i++) {
  1688. if (ch_start_slot < num_slots_per_reg) {
  1689. slot_reg_1 |= BIT(ch_start_slot);
  1690. } else {
  1691. slot = ch_start_slot - num_slots_per_reg;
  1692. slot_reg_2 |= BIT(slot);
  1693. }
  1694. ch_start_slot++;
  1695. }
  1696. }
  1697. DP_DEBUG("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1698. slot_reg_1, slot_reg_2);
  1699. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1700. slot_reg_1);
  1701. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1702. slot_reg_2);
  1703. }
  1704. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1705. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1706. {
  1707. struct dp_catalog_private *catalog;
  1708. struct dp_io_data *io_data = NULL;
  1709. u32 i, slot_reg_1, slot_reg_2, slot;
  1710. u32 reg_off = 0;
  1711. if (!ctrl || ch >= DP_STREAM_MAX) {
  1712. DP_ERR("invalid input. ch %d\n", ch);
  1713. return;
  1714. }
  1715. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1716. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1717. DP_ERR("invalid slots start %d, tot %d\n",
  1718. ch_start_slot, tot_slot_cnt);
  1719. return;
  1720. }
  1721. catalog = dp_catalog_get_priv(ctrl);
  1722. io_data = catalog->io.dp_link;
  1723. DP_DEBUG("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1724. ch, ch_start_slot, tot_slot_cnt);
  1725. if (ch == DP_STREAM_1)
  1726. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1727. slot_reg_1 = dp_read(catalog->exe_mode, io_data,
  1728. DP_DP0_TIMESLOT_1_32 + reg_off);
  1729. slot_reg_2 = dp_read(catalog->exe_mode, io_data,
  1730. DP_DP0_TIMESLOT_33_63 + reg_off);
  1731. ch_start_slot = ch_start_slot - 1;
  1732. for (i = 0; i < tot_slot_cnt; i++) {
  1733. if (ch_start_slot < 33) {
  1734. slot_reg_1 &= ~BIT(ch_start_slot);
  1735. } else {
  1736. slot = ch_start_slot - 33;
  1737. slot_reg_2 &= ~BIT(slot);
  1738. }
  1739. ch_start_slot++;
  1740. }
  1741. DP_DEBUG("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1742. slot_reg_1, slot_reg_2);
  1743. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1744. slot_reg_1);
  1745. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1746. slot_reg_2);
  1747. }
  1748. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1749. u32 x_int, u32 y_frac_enum)
  1750. {
  1751. struct dp_catalog_private *catalog;
  1752. struct dp_io_data *io_data = NULL;
  1753. u32 rg, reg_off = 0;
  1754. if (!ctrl || ch >= DP_STREAM_MAX) {
  1755. DP_ERR("invalid input. ch %d\n", ch);
  1756. return;
  1757. }
  1758. catalog = dp_catalog_get_priv(ctrl);
  1759. io_data = catalog->io.dp_link;
  1760. rg = y_frac_enum;
  1761. rg |= (x_int << 16);
  1762. DP_DEBUG("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1763. y_frac_enum, rg);
  1764. if (ch == DP_STREAM_1)
  1765. reg_off = DP_DP1_RG - DP_DP0_RG;
  1766. dp_write(catalog->exe_mode, io_data, DP_DP0_RG + reg_off, rg);
  1767. }
  1768. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1769. u8 lane_cnt)
  1770. {
  1771. struct dp_catalog_private *catalog;
  1772. struct dp_io_data *io_data;
  1773. u32 mainlink_levels, safe_to_exit_level = 14;
  1774. catalog = dp_catalog_get_priv(ctrl);
  1775. io_data = catalog->io.dp_link;
  1776. switch (lane_cnt) {
  1777. case 1:
  1778. safe_to_exit_level = 14;
  1779. break;
  1780. case 2:
  1781. safe_to_exit_level = 8;
  1782. break;
  1783. case 4:
  1784. safe_to_exit_level = 5;
  1785. break;
  1786. default:
  1787. DP_DEBUG("setting the default safe_to_exit_level = %u\n",
  1788. safe_to_exit_level);
  1789. break;
  1790. }
  1791. mainlink_levels = dp_read(catalog->exe_mode, io_data,
  1792. DP_MAINLINK_LEVELS);
  1793. mainlink_levels &= 0xFE0;
  1794. mainlink_levels |= safe_to_exit_level;
  1795. DP_DEBUG("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1796. mainlink_levels, safe_to_exit_level);
  1797. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS,
  1798. mainlink_levels);
  1799. }
  1800. /* panel related catalog functions */
  1801. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1802. {
  1803. struct dp_catalog_private *catalog;
  1804. struct dp_io_data *io_data;
  1805. u32 offset = 0, reg;
  1806. if (!panel) {
  1807. DP_ERR("invalid input\n");
  1808. goto end;
  1809. }
  1810. if (panel->stream_id >= DP_STREAM_MAX) {
  1811. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1812. goto end;
  1813. }
  1814. catalog = dp_catalog_get_priv(panel);
  1815. io_data = catalog->io.dp_link;
  1816. if (panel->stream_id == DP_STREAM_1)
  1817. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1818. dp_write(catalog->exe_mode, io_data, DP_TOTAL_HOR_VER + offset,
  1819. panel->total);
  1820. dp_write(catalog->exe_mode, io_data,
  1821. DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1822. dp_write(catalog->exe_mode, io_data,
  1823. DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1824. dp_write(catalog->exe_mode, io_data, DP_ACTIVE_HOR_VER + offset,
  1825. panel->dp_active);
  1826. if (panel->stream_id == DP_STREAM_0)
  1827. io_data = catalog->io.dp_p0;
  1828. else
  1829. io_data = catalog->io.dp_p1;
  1830. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG);
  1831. if (panel->widebus_en)
  1832. reg |= BIT(4);
  1833. else
  1834. reg &= ~BIT(4);
  1835. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, reg);
  1836. end:
  1837. return 0;
  1838. }
  1839. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1840. {
  1841. struct dp_catalog_private *catalog;
  1842. struct dp_io_data *io_data;
  1843. if (!hpd) {
  1844. DP_ERR("invalid input\n");
  1845. return;
  1846. }
  1847. catalog = dp_catalog_get_priv(hpd);
  1848. io_data = catalog->io.dp_aux;
  1849. if (en) {
  1850. u32 reftimer = dp_read(catalog->exe_mode, io_data,
  1851. DP_DP_HPD_REFTIMER);
  1852. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1853. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, 0xF);
  1854. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_MASK, 0xA);
  1855. /* Enable REFTIMER to count 1ms */
  1856. reftimer |= BIT(16);
  1857. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_REFTIMER,
  1858. reftimer);
  1859. /* Connect_time is 250us & disconnect_time is 2ms */
  1860. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_0,
  1861. 0x3E800FA);
  1862. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_1,
  1863. 0x1F407D0);
  1864. /* Enable HPD */
  1865. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x1);
  1866. } else {
  1867. /* Disable HPD */
  1868. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x0);
  1869. }
  1870. }
  1871. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1872. {
  1873. u32 isr = 0;
  1874. struct dp_catalog_private *catalog;
  1875. struct dp_io_data *io_data;
  1876. if (!hpd) {
  1877. DP_ERR("invalid input\n");
  1878. return isr;
  1879. }
  1880. catalog = dp_catalog_get_priv(hpd);
  1881. io_data = catalog->io.dp_aux;
  1882. isr = dp_read(catalog->exe_mode, io_data, DP_DP_HPD_INT_STATUS);
  1883. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, (isr & 0xf));
  1884. return isr;
  1885. }
  1886. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1887. {
  1888. struct dp_catalog_private *catalog;
  1889. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1890. {
  1891. MMSS_DP_AUDIO_STREAM_0,
  1892. MMSS_DP_AUDIO_STREAM_1,
  1893. MMSS_DP_AUDIO_STREAM_1,
  1894. },
  1895. {
  1896. MMSS_DP_AUDIO_TIMESTAMP_0,
  1897. MMSS_DP_AUDIO_TIMESTAMP_1,
  1898. MMSS_DP_AUDIO_TIMESTAMP_1,
  1899. },
  1900. {
  1901. MMSS_DP_AUDIO_INFOFRAME_0,
  1902. MMSS_DP_AUDIO_INFOFRAME_1,
  1903. MMSS_DP_AUDIO_INFOFRAME_1,
  1904. },
  1905. {
  1906. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1907. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1908. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1909. },
  1910. {
  1911. MMSS_DP_AUDIO_ISRC_0,
  1912. MMSS_DP_AUDIO_ISRC_1,
  1913. MMSS_DP_AUDIO_ISRC_1,
  1914. },
  1915. };
  1916. if (!audio)
  1917. return;
  1918. catalog = dp_catalog_get_priv(audio);
  1919. catalog->audio_map = sdp_map;
  1920. }
  1921. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1922. {
  1923. struct dp_catalog_private *catalog;
  1924. struct dp_io_data *io_data;
  1925. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1926. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1927. if (!audio)
  1928. return;
  1929. if (audio->stream_id >= DP_STREAM_MAX) {
  1930. DP_ERR("invalid stream id:%d\n", audio->stream_id);
  1931. return;
  1932. }
  1933. if (audio->stream_id == DP_STREAM_1) {
  1934. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1935. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1936. }
  1937. catalog = dp_catalog_get_priv(audio);
  1938. io_data = catalog->io.dp_link;
  1939. sdp_cfg = dp_read(catalog->exe_mode, io_data,
  1940. MMSS_DP_SDP_CFG + sdp_cfg_off);
  1941. /* AUDIO_TIMESTAMP_SDP_EN */
  1942. sdp_cfg |= BIT(1);
  1943. /* AUDIO_STREAM_SDP_EN */
  1944. sdp_cfg |= BIT(2);
  1945. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1946. sdp_cfg |= BIT(5);
  1947. /* AUDIO_ISRC_SDP_EN */
  1948. sdp_cfg |= BIT(6);
  1949. /* AUDIO_INFOFRAME_SDP_EN */
  1950. sdp_cfg |= BIT(20);
  1951. DP_DEBUG("sdp_cfg = 0x%x\n", sdp_cfg);
  1952. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  1953. sdp_cfg);
  1954. sdp_cfg2 = dp_read(catalog->exe_mode, io_data,
  1955. MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  1956. /* IFRM_REGSRC -> Do not use reg values */
  1957. sdp_cfg2 &= ~BIT(0);
  1958. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  1959. sdp_cfg2 &= ~BIT(1);
  1960. DP_DEBUG("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  1961. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg_off,
  1962. sdp_cfg2);
  1963. }
  1964. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  1965. {
  1966. struct dp_catalog_private *catalog;
  1967. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1968. struct dp_io_data *io_data;
  1969. enum dp_catalog_audio_sdp_type sdp;
  1970. enum dp_catalog_audio_header_type header;
  1971. if (!audio)
  1972. return;
  1973. catalog = dp_catalog_get_priv(audio);
  1974. io_data = catalog->io.dp_link;
  1975. sdp_map = catalog->audio_map;
  1976. sdp = audio->sdp_type;
  1977. header = audio->sdp_header;
  1978. audio->data = dp_read(catalog->exe_mode, io_data, sdp_map[sdp][header]);
  1979. }
  1980. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  1981. {
  1982. struct dp_catalog_private *catalog;
  1983. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1984. struct dp_io_data *io_data;
  1985. enum dp_catalog_audio_sdp_type sdp;
  1986. enum dp_catalog_audio_header_type header;
  1987. u32 data;
  1988. if (!audio)
  1989. return;
  1990. catalog = dp_catalog_get_priv(audio);
  1991. io_data = catalog->io.dp_link;
  1992. sdp_map = catalog->audio_map;
  1993. sdp = audio->sdp_type;
  1994. header = audio->sdp_header;
  1995. data = audio->data;
  1996. dp_write(catalog->exe_mode, io_data, sdp_map[sdp][header], data);
  1997. }
  1998. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  1999. {
  2000. struct dp_catalog_private *catalog;
  2001. struct dp_io_data *io_data;
  2002. u32 acr_ctrl, select;
  2003. catalog = dp_catalog_get_priv(audio);
  2004. select = audio->data;
  2005. io_data = catalog->io.dp_link;
  2006. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  2007. DP_DEBUG("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  2008. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  2009. }
  2010. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  2011. {
  2012. struct dp_catalog_private *catalog;
  2013. struct dp_io_data *io_data;
  2014. bool enable;
  2015. u32 audio_ctrl;
  2016. catalog = dp_catalog_get_priv(audio);
  2017. io_data = catalog->io.dp_link;
  2018. enable = !!audio->data;
  2019. audio_ctrl = dp_read(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG);
  2020. if (enable)
  2021. audio_ctrl |= BIT(0);
  2022. else
  2023. audio_ctrl &= ~BIT(0);
  2024. DP_DEBUG("dp_audio_cfg = 0x%x\n", audio_ctrl);
  2025. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG, audio_ctrl);
  2026. /* make sure audio engine is disabled */
  2027. wmb();
  2028. }
  2029. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  2030. {
  2031. struct dp_catalog_private *catalog;
  2032. struct dp_io_data *io_data;
  2033. u32 value, new_value, offset = 0;
  2034. u8 parity_byte;
  2035. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2036. return;
  2037. catalog = dp_catalog_get_priv(panel);
  2038. io_data = catalog->io.dp_link;
  2039. if (panel->stream_id == DP_STREAM_1)
  2040. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2041. /* Config header and parity byte 1 */
  2042. value = dp_read(catalog->exe_mode, io_data,
  2043. MMSS_DP_GENERIC1_0 + offset);
  2044. new_value = 0x83;
  2045. parity_byte = dp_header_get_parity(new_value);
  2046. value |= ((new_value << HEADER_BYTE_1_BIT)
  2047. | (parity_byte << PARITY_BYTE_1_BIT));
  2048. DP_DEBUG("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  2049. value, parity_byte);
  2050. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_0 + offset,
  2051. value);
  2052. /* Config header and parity byte 2 */
  2053. value = dp_read(catalog->exe_mode, io_data,
  2054. MMSS_DP_GENERIC1_1 + offset);
  2055. new_value = 0x1b;
  2056. parity_byte = dp_header_get_parity(new_value);
  2057. value |= ((new_value << HEADER_BYTE_2_BIT)
  2058. | (parity_byte << PARITY_BYTE_2_BIT));
  2059. DP_DEBUG("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  2060. value, parity_byte);
  2061. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  2062. value);
  2063. /* Config header and parity byte 3 */
  2064. value = dp_read(catalog->exe_mode, io_data,
  2065. MMSS_DP_GENERIC1_1 + offset);
  2066. new_value = (0x0 | (0x12 << 2));
  2067. parity_byte = dp_header_get_parity(new_value);
  2068. value |= ((new_value << HEADER_BYTE_3_BIT)
  2069. | (parity_byte << PARITY_BYTE_3_BIT));
  2070. DP_DEBUG("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  2071. new_value, parity_byte);
  2072. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  2073. value);
  2074. }
  2075. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  2076. {
  2077. struct dp_catalog_private *catalog;
  2078. struct dp_io_data *io_data;
  2079. u32 spd_cfg = 0, spd_cfg2 = 0;
  2080. u8 *vendor = NULL, *product = NULL;
  2081. u32 offset = 0;
  2082. u32 sdp_cfg_off = 0;
  2083. u32 sdp_cfg2_off = 0;
  2084. /*
  2085. * Source Device Information
  2086. * 00h unknown
  2087. * 01h Digital STB
  2088. * 02h DVD
  2089. * 03h D-VHS
  2090. * 04h HDD Video
  2091. * 05h DVC
  2092. * 06h DSC
  2093. * 07h Video CD
  2094. * 08h Game
  2095. * 09h PC general
  2096. * 0ah Bluray-Disc
  2097. * 0bh Super Audio CD
  2098. * 0ch HD DVD
  2099. * 0dh PMP
  2100. * 0eh-ffh reserved
  2101. */
  2102. u32 device_type = 0;
  2103. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2104. return;
  2105. catalog = dp_catalog_get_priv(panel);
  2106. io_data = catalog->io.dp_link;
  2107. if (panel->stream_id == DP_STREAM_1)
  2108. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2109. dp_catalog_config_spd_header(panel);
  2110. vendor = panel->spd_vendor_name;
  2111. product = panel->spd_product_description;
  2112. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_2 + offset,
  2113. ((vendor[0] & 0x7f) |
  2114. ((vendor[1] & 0x7f) << 8) |
  2115. ((vendor[2] & 0x7f) << 16) |
  2116. ((vendor[3] & 0x7f) << 24)));
  2117. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_3 + offset,
  2118. ((vendor[4] & 0x7f) |
  2119. ((vendor[5] & 0x7f) << 8) |
  2120. ((vendor[6] & 0x7f) << 16) |
  2121. ((vendor[7] & 0x7f) << 24)));
  2122. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_4 + offset,
  2123. ((product[0] & 0x7f) |
  2124. ((product[1] & 0x7f) << 8) |
  2125. ((product[2] & 0x7f) << 16) |
  2126. ((product[3] & 0x7f) << 24)));
  2127. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_5 + offset,
  2128. ((product[4] & 0x7f) |
  2129. ((product[5] & 0x7f) << 8) |
  2130. ((product[6] & 0x7f) << 16) |
  2131. ((product[7] & 0x7f) << 24)));
  2132. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_6 + offset,
  2133. ((product[8] & 0x7f) |
  2134. ((product[9] & 0x7f) << 8) |
  2135. ((product[10] & 0x7f) << 16) |
  2136. ((product[11] & 0x7f) << 24)));
  2137. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_7 + offset,
  2138. ((product[12] & 0x7f) |
  2139. ((product[13] & 0x7f) << 8) |
  2140. ((product[14] & 0x7f) << 16) |
  2141. ((product[15] & 0x7f) << 24)));
  2142. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_8 + offset,
  2143. device_type);
  2144. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_9 + offset, 0x00);
  2145. if (panel->stream_id == DP_STREAM_1) {
  2146. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  2147. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  2148. }
  2149. spd_cfg = dp_read(catalog->exe_mode, io_data,
  2150. MMSS_DP_SDP_CFG + sdp_cfg_off);
  2151. /* GENERIC1_SDP for SPD Infoframe */
  2152. spd_cfg |= BIT(18);
  2153. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  2154. spd_cfg);
  2155. spd_cfg2 = dp_read(catalog->exe_mode, io_data,
  2156. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  2157. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  2158. spd_cfg2 |= BIT(17);
  2159. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off,
  2160. spd_cfg2);
  2161. dp_catalog_panel_sdp_update(panel);
  2162. }
  2163. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2164. {
  2165. struct dp_parser *parser = catalog->parser;
  2166. dp_catalog_fill_io_buf(dp_ahb);
  2167. dp_catalog_fill_io_buf(dp_aux);
  2168. dp_catalog_fill_io_buf(dp_link);
  2169. dp_catalog_fill_io_buf(dp_p0);
  2170. dp_catalog_fill_io_buf(dp_phy);
  2171. dp_catalog_fill_io_buf(dp_ln_tx0);
  2172. dp_catalog_fill_io_buf(dp_ln_tx1);
  2173. dp_catalog_fill_io_buf(dp_pll);
  2174. dp_catalog_fill_io_buf(usb3_dp_com);
  2175. dp_catalog_fill_io_buf(dp_mmss_cc);
  2176. dp_catalog_fill_io_buf(hdcp_physical);
  2177. dp_catalog_fill_io_buf(dp_p1);
  2178. dp_catalog_fill_io_buf(dp_tcsr);
  2179. }
  2180. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2181. {
  2182. struct dp_parser *parser = catalog->parser;
  2183. dp_catalog_fill_io(dp_ahb);
  2184. dp_catalog_fill_io(dp_aux);
  2185. dp_catalog_fill_io(dp_link);
  2186. dp_catalog_fill_io(dp_p0);
  2187. dp_catalog_fill_io(dp_phy);
  2188. dp_catalog_fill_io(dp_ln_tx0);
  2189. dp_catalog_fill_io(dp_ln_tx1);
  2190. dp_catalog_fill_io(dp_pll);
  2191. dp_catalog_fill_io(usb3_dp_com);
  2192. dp_catalog_fill_io(dp_mmss_cc);
  2193. dp_catalog_fill_io(hdcp_physical);
  2194. dp_catalog_fill_io(dp_p1);
  2195. dp_catalog_fill_io(dp_tcsr);
  2196. }
  2197. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2198. {
  2199. struct dp_catalog_private *catalog;
  2200. if (!dp_catalog) {
  2201. DP_ERR("invalid input\n");
  2202. return;
  2203. }
  2204. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2205. dp_catalog);
  2206. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2207. if (!strcmp(catalog->exe_mode, "hw"))
  2208. catalog->parser->clear_io_buf(catalog->parser);
  2209. else
  2210. dp_catalog_get_io_buf(catalog);
  2211. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2212. dp_catalog->priv.set_exe_mode(dp_catalog, mode);
  2213. }
  2214. static int dp_catalog_init(struct device *dev, struct dp_catalog *catalog,
  2215. struct dp_parser *parser)
  2216. {
  2217. int rc = 0;
  2218. struct dp_catalog_private *catalog_priv;
  2219. catalog_priv = container_of(catalog, struct dp_catalog_private,
  2220. dp_catalog);
  2221. if (parser->hw_cfg.phy_version == DP_PHY_VERSION_4_2_0)
  2222. rc = dp_catalog_get_v420(dev, catalog, &catalog_priv->io);
  2223. else if (parser->hw_cfg.phy_version == DP_PHY_VERSION_2_0_0)
  2224. rc = dp_catalog_get_v200(dev, catalog, &catalog_priv->io);
  2225. return rc;
  2226. }
  2227. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2228. {
  2229. struct dp_catalog_private *catalog;
  2230. if (!dp_catalog)
  2231. return;
  2232. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2233. dp_catalog);
  2234. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2235. dp_catalog->priv.put(dp_catalog);
  2236. catalog->parser->clear_io_buf(catalog->parser);
  2237. devm_kfree(catalog->dev, catalog);
  2238. }
  2239. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2240. {
  2241. int rc = 0;
  2242. struct dp_catalog *dp_catalog;
  2243. struct dp_catalog_private *catalog;
  2244. struct dp_catalog_aux aux = {
  2245. .read_data = dp_catalog_aux_read_data,
  2246. .write_data = dp_catalog_aux_write_data,
  2247. .write_trans = dp_catalog_aux_write_trans,
  2248. .clear_trans = dp_catalog_aux_clear_trans,
  2249. .reset = dp_catalog_aux_reset,
  2250. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2251. .enable = dp_catalog_aux_enable,
  2252. .setup = dp_catalog_aux_setup,
  2253. .get_irq = dp_catalog_aux_get_irq,
  2254. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2255. };
  2256. struct dp_catalog_ctrl ctrl = {
  2257. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2258. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2259. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2260. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2261. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2262. .set_pattern = dp_catalog_ctrl_set_pattern,
  2263. .reset = dp_catalog_ctrl_reset,
  2264. .usb_reset = dp_catalog_ctrl_usb_reset,
  2265. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2266. .enable_irq = dp_catalog_ctrl_enable_irq,
  2267. .phy_reset = dp_catalog_ctrl_phy_reset,
  2268. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2269. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2270. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2271. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2272. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2273. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2274. .mst_config = dp_catalog_ctrl_mst_config,
  2275. .trigger_act = dp_catalog_ctrl_trigger_act,
  2276. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2277. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2278. .update_rg = dp_catalog_ctrl_update_rg,
  2279. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2280. .fec_config = dp_catalog_ctrl_fec_config,
  2281. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2282. .late_phy_init = dp_catalog_ctrl_late_phy_init,
  2283. };
  2284. struct dp_catalog_hpd hpd = {
  2285. .config_hpd = dp_catalog_hpd_config_hpd,
  2286. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2287. };
  2288. struct dp_catalog_audio audio = {
  2289. .init = dp_catalog_audio_init,
  2290. .config_acr = dp_catalog_audio_config_acr,
  2291. .enable = dp_catalog_audio_enable,
  2292. .config_sdp = dp_catalog_audio_config_sdp,
  2293. .set_header = dp_catalog_audio_set_header,
  2294. .get_header = dp_catalog_audio_get_header,
  2295. };
  2296. struct dp_catalog_panel panel = {
  2297. .timing_cfg = dp_catalog_panel_timing_cfg,
  2298. .config_hdr = dp_catalog_panel_config_hdr,
  2299. .config_sdp = dp_catalog_panel_config_sdp,
  2300. .tpg_config = dp_catalog_panel_tpg_cfg,
  2301. .config_spd = dp_catalog_panel_config_spd,
  2302. .config_misc = dp_catalog_panel_config_misc,
  2303. .set_colorspace = dp_catalog_panel_set_colorspace,
  2304. .config_msa = dp_catalog_panel_config_msa,
  2305. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2306. .config_ctrl = dp_catalog_panel_config_ctrl,
  2307. .config_dto = dp_catalog_panel_config_dto,
  2308. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2309. .pps_flush = dp_catalog_panel_pps_flush,
  2310. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2311. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2312. };
  2313. if (!dev || !parser) {
  2314. DP_ERR("invalid input\n");
  2315. rc = -EINVAL;
  2316. goto error;
  2317. }
  2318. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2319. if (!catalog) {
  2320. rc = -ENOMEM;
  2321. goto error;
  2322. }
  2323. catalog->dev = dev;
  2324. catalog->parser = parser;
  2325. dp_catalog_get_io(catalog);
  2326. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2327. dp_catalog = &catalog->dp_catalog;
  2328. dp_catalog->aux = aux;
  2329. dp_catalog->ctrl = ctrl;
  2330. dp_catalog->hpd = hpd;
  2331. dp_catalog->audio = audio;
  2332. dp_catalog->panel = panel;
  2333. rc = dp_catalog_init(dev, dp_catalog, parser);
  2334. if (rc) {
  2335. dp_catalog_put(dp_catalog);
  2336. goto error;
  2337. }
  2338. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2339. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2340. return dp_catalog;
  2341. error:
  2342. return ERR_PTR(rc);
  2343. }