dp_main.c 150 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. unsigned int napi_budget = 128;
  71. module_param(napi_budget, uint, 0644);
  72. MODULE_PARM_DESC(napi_budget,
  73. "tasklet mode: more than 0xffff , napi budget if <= 0xffff");
  74. bool rx_hash = 1;
  75. qdf_declare_param(rx_hash, bool);
  76. /**
  77. * default_dscp_tid_map - Default DSCP-TID mapping
  78. *
  79. * DSCP TID AC
  80. * 000000 0 WME_AC_BE
  81. * 001000 1 WME_AC_BK
  82. * 010000 1 WME_AC_BK
  83. * 011000 0 WME_AC_BE
  84. * 100000 5 WME_AC_VI
  85. * 101000 5 WME_AC_VI
  86. * 110000 6 WME_AC_VO
  87. * 111000 6 WME_AC_VO
  88. */
  89. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 1, 1, 1, 1, 1, 1, 1, 1,
  92. 1, 1, 1, 1, 1, 1, 1, 1,
  93. 0, 0, 0, 0, 0, 0, 0, 0,
  94. 5, 5, 5, 5, 5, 5, 5, 5,
  95. 5, 5, 5, 5, 5, 5, 5, 5,
  96. 6, 6, 6, 6, 6, 6, 6, 6,
  97. 6, 6, 6, 6, 6, 6, 6, 6,
  98. };
  99. /*
  100. * struct dp_rate_debug
  101. *
  102. * @mcs_type: print string for a given mcs
  103. * @valid: valid mcs rate?
  104. */
  105. struct dp_rate_debug {
  106. char mcs_type[DP_MAX_MCS_STRING_LEN];
  107. uint8_t valid;
  108. };
  109. #define MCS_VALID 1
  110. #define MCS_INVALID 0
  111. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  112. {
  113. {"CCK 11 Mbps Long ", MCS_VALID},
  114. {"CCK 5.5 Mbps Long ", MCS_VALID},
  115. {"CCK 2 Mbps Long ", MCS_VALID},
  116. {"CCK 1 Mbps Long ", MCS_VALID},
  117. {"CCK 11 Mbps Short ", MCS_VALID},
  118. {"CCK 5.5 Mbps Short", MCS_VALID},
  119. {"CCK 2 Mbps Short ", MCS_VALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_INVALID},
  123. {"INVALID ", MCS_INVALID},
  124. {"INVALID ", MCS_INVALID},
  125. {"INVALID ", MCS_VALID},
  126. },
  127. {
  128. {"OFDM 48 Mbps", MCS_VALID},
  129. {"OFDM 24 Mbps", MCS_VALID},
  130. {"OFDM 12 Mbps", MCS_VALID},
  131. {"OFDM 6 Mbps ", MCS_VALID},
  132. {"OFDM 54 Mbps", MCS_VALID},
  133. {"OFDM 36 Mbps", MCS_VALID},
  134. {"OFDM 18 Mbps", MCS_VALID},
  135. {"OFDM 9 Mbps ", MCS_VALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_INVALID},
  138. {"INVALID ", MCS_INVALID},
  139. {"INVALID ", MCS_INVALID},
  140. {"INVALID ", MCS_VALID},
  141. },
  142. {
  143. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  144. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  145. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  146. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  147. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  148. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  149. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  150. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_INVALID},
  153. {"INVALID ", MCS_INVALID},
  154. {"INVALID ", MCS_INVALID},
  155. {"INVALID ", MCS_VALID},
  156. },
  157. {
  158. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  159. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  160. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  161. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  162. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  163. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  164. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  165. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  166. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  167. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  168. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  169. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  170. {"INVALID ", MCS_VALID},
  171. },
  172. {
  173. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  174. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  175. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  176. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  177. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  178. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  179. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  180. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  181. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  182. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  183. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  184. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  185. {"INVALID ", MCS_VALID},
  186. }
  187. };
  188. /**
  189. * @brief Cpu ring map types
  190. */
  191. enum dp_cpu_ring_map_types {
  192. DP_DEFAULT_MAP,
  193. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  194. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  195. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  196. DP_CPU_RING_MAP_MAX
  197. };
  198. /**
  199. * @brief Cpu to tx ring map
  200. */
  201. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  202. {0x0, 0x1, 0x2, 0x0},
  203. {0x1, 0x2, 0x1, 0x2},
  204. {0x0, 0x2, 0x0, 0x2},
  205. {0x2, 0x2, 0x2, 0x2}
  206. };
  207. /**
  208. * @brief Select the type of statistics
  209. */
  210. enum dp_stats_type {
  211. STATS_FW = 0,
  212. STATS_HOST = 1,
  213. STATS_TYPE_MAX = 2,
  214. };
  215. /**
  216. * @brief General Firmware statistics options
  217. *
  218. */
  219. enum dp_fw_stats {
  220. TXRX_FW_STATS_INVALID = -1,
  221. };
  222. /**
  223. * dp_stats_mapping_table - Firmware and Host statistics
  224. * currently supported
  225. */
  226. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  227. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  238. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  243. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  244. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  245. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  246. /* Last ENUM for HTT FW STATS */
  247. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  248. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  252. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  253. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  254. };
  255. /**
  256. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  257. * @ring_num: ring num of the ring being queried
  258. * @grp_mask: the grp_mask array for the ring type in question.
  259. *
  260. * The grp_mask array is indexed by group number and the bit fields correspond
  261. * to ring numbers. We are finding which interrupt group a ring belongs to.
  262. *
  263. * Return: the index in the grp_mask array with the ring number.
  264. * -QDF_STATUS_E_NOENT if no entry is found
  265. */
  266. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  267. {
  268. int ext_group_num;
  269. int mask = 1 << ring_num;
  270. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  271. ext_group_num++) {
  272. if (mask & grp_mask[ext_group_num])
  273. return ext_group_num;
  274. }
  275. return -QDF_STATUS_E_NOENT;
  276. }
  277. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  278. enum hal_ring_type ring_type,
  279. int ring_num)
  280. {
  281. int *grp_mask;
  282. switch (ring_type) {
  283. case WBM2SW_RELEASE:
  284. /* dp_tx_comp_handler - soc->tx_comp_ring */
  285. if (ring_num < 3)
  286. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  287. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  288. else if (ring_num == 3) {
  289. /* sw treats this as a separate ring type */
  290. grp_mask = &soc->wlan_cfg_ctx->
  291. int_rx_wbm_rel_ring_mask[0];
  292. ring_num = 0;
  293. } else {
  294. qdf_assert(0);
  295. return -QDF_STATUS_E_NOENT;
  296. }
  297. break;
  298. case REO_EXCEPTION:
  299. /* dp_rx_err_process - &soc->reo_exception_ring */
  300. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  301. break;
  302. case REO_DST:
  303. /* dp_rx_process - soc->reo_dest_ring */
  304. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  305. break;
  306. case REO_STATUS:
  307. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  308. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  309. break;
  310. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  311. case RXDMA_MONITOR_STATUS:
  312. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  313. case RXDMA_MONITOR_DST:
  314. /* dp_mon_process */
  315. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  316. break;
  317. case RXDMA_MONITOR_BUF:
  318. case RXDMA_BUF:
  319. /* TODO: support low_thresh interrupt */
  320. return -QDF_STATUS_E_NOENT;
  321. break;
  322. case TCL_DATA:
  323. case TCL_CMD:
  324. case REO_CMD:
  325. case SW2WBM_RELEASE:
  326. case WBM_IDLE_LINK:
  327. /* normally empty SW_TO_HW rings */
  328. return -QDF_STATUS_E_NOENT;
  329. break;
  330. case TCL_STATUS:
  331. case REO_REINJECT:
  332. case RXDMA_DST:
  333. /* misc unused rings */
  334. return -QDF_STATUS_E_NOENT;
  335. break;
  336. case CE_SRC:
  337. case CE_DST:
  338. case CE_DST_STATUS:
  339. /* CE_rings - currently handled by hif */
  340. default:
  341. return -QDF_STATUS_E_NOENT;
  342. break;
  343. }
  344. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  345. }
  346. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  347. *ring_params, int ring_type, int ring_num)
  348. {
  349. int msi_group_number;
  350. int msi_data_count;
  351. int ret;
  352. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  353. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  354. &msi_data_count, &msi_data_start,
  355. &msi_irq_start);
  356. if (ret)
  357. return;
  358. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  359. ring_num);
  360. if (msi_group_number < 0) {
  361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  362. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  363. ring_type, ring_num);
  364. ring_params->msi_addr = 0;
  365. ring_params->msi_data = 0;
  366. return;
  367. }
  368. if (msi_group_number > msi_data_count) {
  369. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  370. FL("2 msi_groups will share an msi; msi_group_num %d"),
  371. msi_group_number);
  372. QDF_ASSERT(0);
  373. }
  374. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  375. ring_params->msi_addr = addr_low;
  376. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  377. ring_params->msi_data = (msi_group_number % msi_data_count)
  378. + msi_data_start;
  379. ring_params->flags |= HAL_SRNG_MSI_INTR;
  380. }
  381. /**
  382. * dp_print_ast_stats() - Dump AST table contents
  383. * @soc: Datapath soc handle
  384. *
  385. * return void
  386. */
  387. #ifdef FEATURE_WDS
  388. static void dp_print_ast_stats(struct dp_soc *soc)
  389. {
  390. uint8_t i;
  391. uint8_t num_entries = 0;
  392. struct dp_vdev *vdev;
  393. struct dp_pdev *pdev;
  394. struct dp_peer *peer;
  395. struct dp_ast_entry *ase, *tmp_ase;
  396. DP_PRINT_STATS("AST Stats:");
  397. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  398. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  399. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  400. DP_PRINT_STATS("AST Table:");
  401. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  402. pdev = soc->pdev_list[i];
  403. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  404. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  405. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  406. DP_PRINT_STATS("%6d mac_addr = %pM"
  407. " peer_mac_addr = %pM"
  408. " type = %d"
  409. " next_hop = %d"
  410. " is_active = %d"
  411. " is_bss = %d",
  412. ++num_entries,
  413. ase->mac_addr.raw,
  414. ase->peer->mac_addr.raw,
  415. ase->type,
  416. ase->next_hop,
  417. ase->is_active,
  418. ase->is_bss);
  419. }
  420. }
  421. }
  422. }
  423. }
  424. #else
  425. static void dp_print_ast_stats(struct dp_soc *soc)
  426. {
  427. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  428. return;
  429. }
  430. #endif
  431. /*
  432. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  433. */
  434. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  435. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  436. {
  437. void *hal_soc = soc->hal_soc;
  438. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  439. /* TODO: See if we should get align size from hal */
  440. uint32_t ring_base_align = 8;
  441. struct hal_srng_params ring_params;
  442. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  443. /* TODO: Currently hal layer takes care of endianness related settings.
  444. * See if these settings need to passed from DP layer
  445. */
  446. ring_params.flags = 0;
  447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  448. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  449. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  450. srng->hal_srng = NULL;
  451. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  452. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  453. soc->osdev, soc->osdev->dev, srng->alloc_size,
  454. &(srng->base_paddr_unaligned));
  455. if (!srng->base_vaddr_unaligned) {
  456. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  457. FL("alloc failed - ring_type: %d, ring_num %d"),
  458. ring_type, ring_num);
  459. return QDF_STATUS_E_NOMEM;
  460. }
  461. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  462. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  463. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  464. ((unsigned long)(ring_params.ring_base_vaddr) -
  465. (unsigned long)srng->base_vaddr_unaligned);
  466. ring_params.num_entries = num_entries;
  467. if (soc->intr_mode == DP_INTR_MSI) {
  468. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  470. FL("Using MSI for ring_type: %d, ring_num %d"),
  471. ring_type, ring_num);
  472. } else {
  473. ring_params.msi_data = 0;
  474. ring_params.msi_addr = 0;
  475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  476. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  477. ring_type, ring_num);
  478. }
  479. /*
  480. * Setup interrupt timer and batch counter thresholds for
  481. * interrupt mitigation based on ring type
  482. */
  483. if (ring_type == REO_DST) {
  484. ring_params.intr_timer_thres_us =
  485. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  486. ring_params.intr_batch_cntr_thres_entries =
  487. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  488. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  489. ring_params.intr_timer_thres_us =
  490. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  491. ring_params.intr_batch_cntr_thres_entries =
  492. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  493. } else {
  494. ring_params.intr_timer_thres_us =
  495. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  496. ring_params.intr_batch_cntr_thres_entries =
  497. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  498. }
  499. /* Enable low threshold interrupts for rx buffer rings (regular and
  500. * monitor buffer rings.
  501. * TODO: See if this is required for any other ring
  502. */
  503. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  504. /* TODO: Setting low threshold to 1/8th of ring size
  505. * see if this needs to be configurable
  506. */
  507. ring_params.low_threshold = num_entries >> 3;
  508. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  509. ring_params.intr_timer_thres_us = 0x1000;
  510. }
  511. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  512. mac_id, &ring_params);
  513. return 0;
  514. }
  515. /**
  516. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  517. * Any buffers allocated and attached to ring entries are expected to be freed
  518. * before calling this function.
  519. */
  520. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  521. int ring_type, int ring_num)
  522. {
  523. if (!srng->hal_srng) {
  524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  525. FL("Ring type: %d, num:%d not setup"),
  526. ring_type, ring_num);
  527. return;
  528. }
  529. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  530. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  531. srng->alloc_size,
  532. srng->base_vaddr_unaligned,
  533. srng->base_paddr_unaligned, 0);
  534. srng->hal_srng = NULL;
  535. }
  536. #ifdef IPA_OFFLOAD
  537. /**
  538. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  539. * @soc: data path instance
  540. * @pdev: core txrx pdev context
  541. *
  542. * Free allocated TX buffers with WBM SRNG
  543. *
  544. * Return: none
  545. */
  546. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  547. {
  548. int idx;
  549. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  550. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  551. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  552. }
  553. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  554. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  555. }
  556. /**
  557. * dp_rx_ipa_uc_detach - free autonomy RX resources
  558. * @soc: data path instance
  559. * @pdev: core txrx pdev context
  560. *
  561. * This function will detach DP RX into main device context
  562. * will free DP Rx resources.
  563. *
  564. * Return: none
  565. */
  566. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  567. {
  568. }
  569. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  570. {
  571. /* TX resource detach */
  572. dp_tx_ipa_uc_detach(soc, pdev);
  573. /* RX resource detach */
  574. dp_rx_ipa_uc_detach(soc, pdev);
  575. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  576. return QDF_STATUS_SUCCESS; /* success */
  577. }
  578. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  579. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  580. /**
  581. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  582. * @soc: data path instance
  583. * @pdev: Physical device handle
  584. *
  585. * Allocate TX buffer from non-cacheable memory
  586. * Attache allocated TX buffers with WBM SRNG
  587. *
  588. * Return: int
  589. */
  590. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  591. {
  592. uint32_t tx_buffer_count;
  593. uint32_t ring_base_align = 8;
  594. void *buffer_vaddr_unaligned;
  595. void *buffer_vaddr;
  596. qdf_dma_addr_t buffer_paddr_unaligned;
  597. qdf_dma_addr_t buffer_paddr;
  598. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  599. uint32_t paddr_lo;
  600. uint32_t paddr_hi;
  601. void *ring_entry;
  602. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  603. int retval = QDF_STATUS_SUCCESS;
  604. /*
  605. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  606. * unsigned int uc_tx_buf_sz =
  607. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  608. */
  609. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  610. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  611. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  612. "requested %d buffers to be posted to wbm ring",
  613. ring_size);
  614. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  615. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  616. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  617. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  618. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  619. return -ENOMEM;
  620. }
  621. hal_srng_access_start(soc->hal_soc, wbm_srng);
  622. /* Allocate TX buffers as many as possible */
  623. for (tx_buffer_count = 0;
  624. tx_buffer_count < ring_size; tx_buffer_count++) {
  625. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  626. if (!ring_entry) {
  627. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  628. "Failed to get WBM ring entry\n");
  629. goto fail;
  630. }
  631. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  632. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  633. if (!buffer_vaddr_unaligned) {
  634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  635. "IPA WDI TX buffer alloc fail %d allocated\n",
  636. tx_buffer_count);
  637. break;
  638. }
  639. buffer_vaddr = buffer_vaddr_unaligned +
  640. ((unsigned long)buffer_vaddr_unaligned %
  641. ring_base_align);
  642. buffer_paddr = buffer_paddr_unaligned +
  643. ((unsigned long)(buffer_vaddr) -
  644. (unsigned long)buffer_vaddr_unaligned);
  645. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  646. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  647. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  648. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  649. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  650. buffer_vaddr;
  651. }
  652. hal_srng_access_end(soc->hal_soc, wbm_srng);
  653. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  654. return retval;
  655. fail:
  656. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  657. return retval;
  658. }
  659. /**
  660. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  661. * @soc: data path instance
  662. * @pdev: core txrx pdev context
  663. *
  664. * This function will attach a DP RX instance into the main
  665. * device (SOC) context.
  666. *
  667. * Return: QDF_STATUS_SUCCESS: success
  668. * QDF_STATUS_E_RESOURCES: Error return
  669. */
  670. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  671. {
  672. return QDF_STATUS_SUCCESS;
  673. }
  674. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  675. {
  676. int error;
  677. /* TX resource attach */
  678. error = dp_tx_ipa_uc_attach(soc, pdev);
  679. if (error) {
  680. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  681. "DP IPA UC TX attach fail code %d\n", error);
  682. return error;
  683. }
  684. /* RX resource attach */
  685. error = dp_rx_ipa_uc_attach(soc, pdev);
  686. if (error) {
  687. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  688. "DP IPA UC RX attach fail code %d\n", error);
  689. dp_tx_ipa_uc_detach(soc, pdev);
  690. return error;
  691. }
  692. return QDF_STATUS_SUCCESS; /* success */
  693. }
  694. #else
  695. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  696. {
  697. return QDF_STATUS_SUCCESS;
  698. }
  699. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  700. {
  701. return QDF_STATUS_SUCCESS;
  702. }
  703. #endif
  704. /* TODO: Need this interface from HIF */
  705. void *hif_get_hal_handle(void *hif_handle);
  706. /*
  707. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  708. * @dp_ctx: DP SOC handle
  709. * @budget: Number of frames/descriptors that can be processed in one shot
  710. *
  711. * Return: remaining budget/quota for the soc device
  712. */
  713. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  714. {
  715. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  716. struct dp_soc *soc = int_ctx->soc;
  717. int ring = 0;
  718. uint32_t work_done = 0;
  719. int budget = dp_budget;
  720. uint8_t tx_mask = int_ctx->tx_ring_mask;
  721. uint8_t rx_mask = int_ctx->rx_ring_mask;
  722. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  723. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  724. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  725. uint32_t remaining_quota = dp_budget;
  726. /* Process Tx completion interrupts first to return back buffers */
  727. while (tx_mask) {
  728. if (tx_mask & 0x1) {
  729. work_done = dp_tx_comp_handler(soc,
  730. soc->tx_comp_ring[ring].hal_srng,
  731. remaining_quota);
  732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  733. "tx mask 0x%x ring %d, budget %d, work_done %d",
  734. tx_mask, ring, budget, work_done);
  735. budget -= work_done;
  736. if (budget <= 0)
  737. goto budget_done;
  738. remaining_quota = budget;
  739. }
  740. tx_mask = tx_mask >> 1;
  741. ring++;
  742. }
  743. /* Process REO Exception ring interrupt */
  744. if (rx_err_mask) {
  745. work_done = dp_rx_err_process(soc,
  746. soc->reo_exception_ring.hal_srng,
  747. remaining_quota);
  748. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  749. "REO Exception Ring: work_done %d budget %d",
  750. work_done, budget);
  751. budget -= work_done;
  752. if (budget <= 0) {
  753. goto budget_done;
  754. }
  755. remaining_quota = budget;
  756. }
  757. /* Process Rx WBM release ring interrupt */
  758. if (rx_wbm_rel_mask) {
  759. work_done = dp_rx_wbm_err_process(soc,
  760. soc->rx_rel_ring.hal_srng, remaining_quota);
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  762. "WBM Release Ring: work_done %d budget %d",
  763. work_done, budget);
  764. budget -= work_done;
  765. if (budget <= 0) {
  766. goto budget_done;
  767. }
  768. remaining_quota = budget;
  769. }
  770. /* Process Rx interrupts */
  771. if (rx_mask) {
  772. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  773. if (rx_mask & (1 << ring)) {
  774. work_done = dp_rx_process(int_ctx,
  775. soc->reo_dest_ring[ring].hal_srng,
  776. remaining_quota);
  777. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  778. "rx mask 0x%x ring %d, work_done %d budget %d",
  779. rx_mask, ring, work_done, budget);
  780. budget -= work_done;
  781. if (budget <= 0)
  782. goto budget_done;
  783. remaining_quota = budget;
  784. }
  785. }
  786. }
  787. if (reo_status_mask)
  788. dp_reo_status_ring_handler(soc);
  789. /* Process LMAC interrupts */
  790. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  791. if (soc->pdev_list[ring] == NULL)
  792. continue;
  793. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  794. work_done = dp_mon_process(soc, ring, remaining_quota);
  795. budget -= work_done;
  796. remaining_quota = budget;
  797. }
  798. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  799. work_done = dp_rxdma_err_process(soc, ring,
  800. remaining_quota);
  801. budget -= work_done;
  802. }
  803. }
  804. qdf_lro_flush(int_ctx->lro_ctx);
  805. budget_done:
  806. return dp_budget - budget;
  807. }
  808. #ifdef DP_INTR_POLL_BASED
  809. /* dp_interrupt_timer()- timer poll for interrupts
  810. *
  811. * @arg: SoC Handle
  812. *
  813. * Return:
  814. *
  815. */
  816. static void dp_interrupt_timer(void *arg)
  817. {
  818. struct dp_soc *soc = (struct dp_soc *) arg;
  819. int i;
  820. if (qdf_atomic_read(&soc->cmn_init_done)) {
  821. for (i = 0;
  822. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  823. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  824. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  825. }
  826. }
  827. /*
  828. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  829. * @txrx_soc: DP SOC handle
  830. *
  831. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  832. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  833. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  834. *
  835. * Return: 0 for success. nonzero for failure.
  836. */
  837. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  838. {
  839. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  840. int i;
  841. soc->intr_mode = DP_INTR_POLL;
  842. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  843. soc->intr_ctx[i].dp_intr_id = i;
  844. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  845. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  847. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  849. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  850. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  851. soc->intr_ctx[i].soc = soc;
  852. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  853. }
  854. qdf_timer_init(soc->osdev, &soc->int_timer,
  855. dp_interrupt_timer, (void *)soc,
  856. QDF_TIMER_TYPE_WAKE_APPS);
  857. return QDF_STATUS_SUCCESS;
  858. }
  859. #ifdef CONFIG_MCL
  860. extern int con_mode_monitor;
  861. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  862. /*
  863. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  864. * @txrx_soc: DP SOC handle
  865. *
  866. * Call the appropriate attach function based on the mode of operation.
  867. * This is a WAR for enabling monitor mode.
  868. *
  869. * Return: 0 for success. nonzero for failure.
  870. */
  871. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  872. {
  873. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  875. FL("Attach interrupts in Poll mode"));
  876. return dp_soc_interrupt_attach_poll(txrx_soc);
  877. } else {
  878. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  879. FL("Attach interrupts in MSI mode"));
  880. return dp_soc_interrupt_attach(txrx_soc);
  881. }
  882. }
  883. #else
  884. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  885. {
  886. return dp_soc_interrupt_attach_poll(txrx_soc);
  887. }
  888. #endif
  889. #endif
  890. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  891. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  892. {
  893. int j;
  894. int num_irq = 0;
  895. int tx_mask =
  896. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  897. int rx_mask =
  898. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  899. int rx_mon_mask =
  900. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  901. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  902. soc->wlan_cfg_ctx, intr_ctx_num);
  903. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  904. soc->wlan_cfg_ctx, intr_ctx_num);
  905. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  906. soc->wlan_cfg_ctx, intr_ctx_num);
  907. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  908. if (tx_mask & (1 << j)) {
  909. irq_id_map[num_irq++] =
  910. (wbm2host_tx_completions_ring1 - j);
  911. }
  912. if (rx_mask & (1 << j)) {
  913. irq_id_map[num_irq++] =
  914. (reo2host_destination_ring1 - j);
  915. }
  916. if (rx_mon_mask & (1 << j)) {
  917. irq_id_map[num_irq++] =
  918. (ppdu_end_interrupts_mac1 - j);
  919. }
  920. if (rx_wbm_rel_ring_mask & (1 << j))
  921. irq_id_map[num_irq++] = wbm2host_rx_release;
  922. if (rx_err_ring_mask & (1 << j))
  923. irq_id_map[num_irq++] = reo2host_exception;
  924. if (reo_status_ring_mask & (1 << j))
  925. irq_id_map[num_irq++] = reo2host_status;
  926. }
  927. *num_irq_r = num_irq;
  928. }
  929. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  930. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  931. int msi_vector_count, int msi_vector_start)
  932. {
  933. int tx_mask = wlan_cfg_get_tx_ring_mask(
  934. soc->wlan_cfg_ctx, intr_ctx_num);
  935. int rx_mask = wlan_cfg_get_rx_ring_mask(
  936. soc->wlan_cfg_ctx, intr_ctx_num);
  937. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  938. soc->wlan_cfg_ctx, intr_ctx_num);
  939. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  940. soc->wlan_cfg_ctx, intr_ctx_num);
  941. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  942. soc->wlan_cfg_ctx, intr_ctx_num);
  943. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  944. soc->wlan_cfg_ctx, intr_ctx_num);
  945. unsigned int vector =
  946. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  947. int num_irq = 0;
  948. soc->intr_mode = DP_INTR_MSI;
  949. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  950. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  951. irq_id_map[num_irq++] =
  952. pld_get_msi_irq(soc->osdev->dev, vector);
  953. *num_irq_r = num_irq;
  954. }
  955. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  956. int *irq_id_map, int *num_irq)
  957. {
  958. int msi_vector_count, ret;
  959. uint32_t msi_base_data, msi_vector_start;
  960. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  961. &msi_vector_count,
  962. &msi_base_data,
  963. &msi_vector_start);
  964. if (ret)
  965. return dp_soc_interrupt_map_calculate_integrated(soc,
  966. intr_ctx_num, irq_id_map, num_irq);
  967. else
  968. dp_soc_interrupt_map_calculate_msi(soc,
  969. intr_ctx_num, irq_id_map, num_irq,
  970. msi_vector_count, msi_vector_start);
  971. }
  972. /*
  973. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  974. * @txrx_soc: DP SOC handle
  975. *
  976. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  977. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  978. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  979. *
  980. * Return: 0 for success. nonzero for failure.
  981. */
  982. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  983. {
  984. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  985. int i = 0;
  986. int num_irq = 0;
  987. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  988. int ret = 0;
  989. /* Map of IRQ ids registered with one interrupt context */
  990. int irq_id_map[HIF_MAX_GRP_IRQ];
  991. int tx_mask =
  992. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  993. int rx_mask =
  994. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  995. int rx_mon_mask =
  996. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  997. int rx_err_ring_mask =
  998. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  999. int rx_wbm_rel_ring_mask =
  1000. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1001. int reo_status_ring_mask =
  1002. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1003. int rxdma2host_ring_mask =
  1004. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1005. soc->intr_ctx[i].dp_intr_id = i;
  1006. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1007. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1008. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1009. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1010. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1011. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1012. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1013. soc->intr_ctx[i].soc = soc;
  1014. num_irq = 0;
  1015. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1016. &num_irq);
  1017. ret = hif_register_ext_group(soc->hif_handle,
  1018. num_irq, irq_id_map, dp_service_srngs,
  1019. &soc->intr_ctx[i], "dp_intr",
  1020. napi_budget);
  1021. if (ret) {
  1022. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1023. FL("failed, ret = %d"), ret);
  1024. return QDF_STATUS_E_FAILURE;
  1025. }
  1026. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1027. }
  1028. hif_configure_ext_group_interrupts(soc->hif_handle);
  1029. return QDF_STATUS_SUCCESS;
  1030. }
  1031. /*
  1032. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1033. * @txrx_soc: DP SOC handle
  1034. *
  1035. * Return: void
  1036. */
  1037. static void dp_soc_interrupt_detach(void *txrx_soc)
  1038. {
  1039. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1040. int i;
  1041. if (soc->intr_mode == DP_INTR_POLL) {
  1042. qdf_timer_stop(&soc->int_timer);
  1043. qdf_timer_free(&soc->int_timer);
  1044. } else {
  1045. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1046. }
  1047. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1048. soc->intr_ctx[i].tx_ring_mask = 0;
  1049. soc->intr_ctx[i].rx_ring_mask = 0;
  1050. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1051. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1052. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1053. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1054. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1055. }
  1056. }
  1057. #define AVG_MAX_MPDUS_PER_TID 128
  1058. #define AVG_TIDS_PER_CLIENT 2
  1059. #define AVG_FLOWS_PER_TID 2
  1060. #define AVG_MSDUS_PER_FLOW 128
  1061. #define AVG_MSDUS_PER_MPDU 4
  1062. /*
  1063. * Allocate and setup link descriptor pool that will be used by HW for
  1064. * various link and queue descriptors and managed by WBM
  1065. */
  1066. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1067. {
  1068. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1069. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1070. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1071. uint32_t num_mpdus_per_link_desc =
  1072. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1073. uint32_t num_msdus_per_link_desc =
  1074. hal_num_msdus_per_link_desc(soc->hal_soc);
  1075. uint32_t num_mpdu_links_per_queue_desc =
  1076. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1077. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1078. uint32_t total_link_descs, total_mem_size;
  1079. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1080. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1081. uint32_t num_link_desc_banks;
  1082. uint32_t last_bank_size = 0;
  1083. uint32_t entry_size, num_entries;
  1084. int i;
  1085. uint32_t desc_id = 0;
  1086. /* Only Tx queue descriptors are allocated from common link descriptor
  1087. * pool Rx queue descriptors are not included in this because (REO queue
  1088. * extension descriptors) they are expected to be allocated contiguously
  1089. * with REO queue descriptors
  1090. */
  1091. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1092. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1093. num_mpdu_queue_descs = num_mpdu_link_descs /
  1094. num_mpdu_links_per_queue_desc;
  1095. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1096. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1097. num_msdus_per_link_desc;
  1098. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1099. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1100. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1101. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1102. /* Round up to power of 2 */
  1103. total_link_descs = 1;
  1104. while (total_link_descs < num_entries)
  1105. total_link_descs <<= 1;
  1106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1107. FL("total_link_descs: %u, link_desc_size: %d"),
  1108. total_link_descs, link_desc_size);
  1109. total_mem_size = total_link_descs * link_desc_size;
  1110. total_mem_size += link_desc_align;
  1111. if (total_mem_size <= max_alloc_size) {
  1112. num_link_desc_banks = 0;
  1113. last_bank_size = total_mem_size;
  1114. } else {
  1115. num_link_desc_banks = (total_mem_size) /
  1116. (max_alloc_size - link_desc_align);
  1117. last_bank_size = total_mem_size %
  1118. (max_alloc_size - link_desc_align);
  1119. }
  1120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1121. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1122. total_mem_size, num_link_desc_banks);
  1123. for (i = 0; i < num_link_desc_banks; i++) {
  1124. soc->link_desc_banks[i].base_vaddr_unaligned =
  1125. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1126. max_alloc_size,
  1127. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1128. soc->link_desc_banks[i].size = max_alloc_size;
  1129. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1130. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1131. ((unsigned long)(
  1132. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1133. link_desc_align));
  1134. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1135. soc->link_desc_banks[i].base_paddr_unaligned) +
  1136. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1137. (unsigned long)(
  1138. soc->link_desc_banks[i].base_vaddr_unaligned));
  1139. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1141. FL("Link descriptor memory alloc failed"));
  1142. goto fail;
  1143. }
  1144. }
  1145. if (last_bank_size) {
  1146. /* Allocate last bank in case total memory required is not exact
  1147. * multiple of max_alloc_size
  1148. */
  1149. soc->link_desc_banks[i].base_vaddr_unaligned =
  1150. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1151. last_bank_size,
  1152. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1153. soc->link_desc_banks[i].size = last_bank_size;
  1154. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1155. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1156. ((unsigned long)(
  1157. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1158. link_desc_align));
  1159. soc->link_desc_banks[i].base_paddr =
  1160. (unsigned long)(
  1161. soc->link_desc_banks[i].base_paddr_unaligned) +
  1162. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1163. (unsigned long)(
  1164. soc->link_desc_banks[i].base_vaddr_unaligned));
  1165. }
  1166. /* Allocate and setup link descriptor idle list for HW internal use */
  1167. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1168. total_mem_size = entry_size * total_link_descs;
  1169. if (total_mem_size <= max_alloc_size) {
  1170. void *desc;
  1171. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1172. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1173. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1174. FL("Link desc idle ring setup failed"));
  1175. goto fail;
  1176. }
  1177. hal_srng_access_start_unlocked(soc->hal_soc,
  1178. soc->wbm_idle_link_ring.hal_srng);
  1179. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1180. soc->link_desc_banks[i].base_paddr; i++) {
  1181. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1182. ((unsigned long)(
  1183. soc->link_desc_banks[i].base_vaddr) -
  1184. (unsigned long)(
  1185. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1186. / link_desc_size;
  1187. unsigned long paddr = (unsigned long)(
  1188. soc->link_desc_banks[i].base_paddr);
  1189. while (num_entries && (desc = hal_srng_src_get_next(
  1190. soc->hal_soc,
  1191. soc->wbm_idle_link_ring.hal_srng))) {
  1192. hal_set_link_desc_addr(desc,
  1193. LINK_DESC_COOKIE(desc_id, i), paddr);
  1194. num_entries--;
  1195. desc_id++;
  1196. paddr += link_desc_size;
  1197. }
  1198. }
  1199. hal_srng_access_end_unlocked(soc->hal_soc,
  1200. soc->wbm_idle_link_ring.hal_srng);
  1201. } else {
  1202. uint32_t num_scatter_bufs;
  1203. uint32_t num_entries_per_buf;
  1204. uint32_t rem_entries;
  1205. uint8_t *scatter_buf_ptr;
  1206. uint16_t scatter_buf_num;
  1207. soc->wbm_idle_scatter_buf_size =
  1208. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1209. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1210. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1211. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1212. soc->hal_soc, total_mem_size,
  1213. soc->wbm_idle_scatter_buf_size);
  1214. for (i = 0; i < num_scatter_bufs; i++) {
  1215. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1216. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1217. soc->wbm_idle_scatter_buf_size,
  1218. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1219. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1220. QDF_TRACE(QDF_MODULE_ID_DP,
  1221. QDF_TRACE_LEVEL_ERROR,
  1222. FL("Scatter list memory alloc failed"));
  1223. goto fail;
  1224. }
  1225. }
  1226. /* Populate idle list scatter buffers with link descriptor
  1227. * pointers
  1228. */
  1229. scatter_buf_num = 0;
  1230. scatter_buf_ptr = (uint8_t *)(
  1231. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1232. rem_entries = num_entries_per_buf;
  1233. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1234. soc->link_desc_banks[i].base_paddr; i++) {
  1235. uint32_t num_link_descs =
  1236. (soc->link_desc_banks[i].size -
  1237. ((unsigned long)(
  1238. soc->link_desc_banks[i].base_vaddr) -
  1239. (unsigned long)(
  1240. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1241. / link_desc_size;
  1242. unsigned long paddr = (unsigned long)(
  1243. soc->link_desc_banks[i].base_paddr);
  1244. while (num_link_descs) {
  1245. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1246. LINK_DESC_COOKIE(desc_id, i), paddr);
  1247. num_link_descs--;
  1248. desc_id++;
  1249. paddr += link_desc_size;
  1250. rem_entries--;
  1251. if (rem_entries) {
  1252. scatter_buf_ptr += entry_size;
  1253. } else {
  1254. rem_entries = num_entries_per_buf;
  1255. scatter_buf_num++;
  1256. if (scatter_buf_num >= num_scatter_bufs)
  1257. break;
  1258. scatter_buf_ptr = (uint8_t *)(
  1259. soc->wbm_idle_scatter_buf_base_vaddr[
  1260. scatter_buf_num]);
  1261. }
  1262. }
  1263. }
  1264. /* Setup link descriptor idle list in HW */
  1265. hal_setup_link_idle_list(soc->hal_soc,
  1266. soc->wbm_idle_scatter_buf_base_paddr,
  1267. soc->wbm_idle_scatter_buf_base_vaddr,
  1268. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1269. (uint32_t)(scatter_buf_ptr -
  1270. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1271. scatter_buf_num-1])), total_link_descs);
  1272. }
  1273. return 0;
  1274. fail:
  1275. if (soc->wbm_idle_link_ring.hal_srng) {
  1276. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1277. WBM_IDLE_LINK, 0);
  1278. }
  1279. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1280. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1281. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1282. soc->wbm_idle_scatter_buf_size,
  1283. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1284. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1285. }
  1286. }
  1287. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1288. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1289. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1290. soc->link_desc_banks[i].size,
  1291. soc->link_desc_banks[i].base_vaddr_unaligned,
  1292. soc->link_desc_banks[i].base_paddr_unaligned,
  1293. 0);
  1294. }
  1295. }
  1296. return QDF_STATUS_E_FAILURE;
  1297. }
  1298. /*
  1299. * Free link descriptor pool that was setup HW
  1300. */
  1301. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1302. {
  1303. int i;
  1304. if (soc->wbm_idle_link_ring.hal_srng) {
  1305. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1306. WBM_IDLE_LINK, 0);
  1307. }
  1308. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1309. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1310. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1311. soc->wbm_idle_scatter_buf_size,
  1312. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1313. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1314. }
  1315. }
  1316. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1317. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1318. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1319. soc->link_desc_banks[i].size,
  1320. soc->link_desc_banks[i].base_vaddr_unaligned,
  1321. soc->link_desc_banks[i].base_paddr_unaligned,
  1322. 0);
  1323. }
  1324. }
  1325. }
  1326. /* TODO: Following should be configurable */
  1327. #define WBM_RELEASE_RING_SIZE 64
  1328. #define TCL_CMD_RING_SIZE 32
  1329. #define TCL_STATUS_RING_SIZE 32
  1330. #if defined(QCA_WIFI_QCA6290)
  1331. #define REO_DST_RING_SIZE 1024
  1332. #else
  1333. #define REO_DST_RING_SIZE 2048
  1334. #endif
  1335. #define REO_REINJECT_RING_SIZE 32
  1336. #define RX_RELEASE_RING_SIZE 1024
  1337. #define REO_EXCEPTION_RING_SIZE 128
  1338. #define REO_CMD_RING_SIZE 32
  1339. #define REO_STATUS_RING_SIZE 32
  1340. #define RXDMA_BUF_RING_SIZE 1024
  1341. #define RXDMA_REFILL_RING_SIZE 2048
  1342. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  1343. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  1344. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1345. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  1346. #define RXDMA_ERR_DST_RING_SIZE 1024
  1347. /*
  1348. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1349. * @soc: Datapath SOC handle
  1350. *
  1351. * This is a timer function used to age out stale WDS nodes from
  1352. * AST table
  1353. */
  1354. #ifdef FEATURE_WDS
  1355. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1356. {
  1357. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1358. struct dp_pdev *pdev;
  1359. struct dp_vdev *vdev;
  1360. struct dp_peer *peer;
  1361. struct dp_ast_entry *ase, *temp_ase;
  1362. int i;
  1363. qdf_spin_lock_bh(&soc->ast_lock);
  1364. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1365. pdev = soc->pdev_list[i];
  1366. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1367. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1368. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1369. /*
  1370. * Do not expire static ast entries
  1371. */
  1372. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1373. continue;
  1374. if (ase->is_active) {
  1375. ase->is_active = FALSE;
  1376. continue;
  1377. }
  1378. DP_STATS_INC(soc, ast.aged_out, 1);
  1379. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1380. pdev->osif_pdev,
  1381. ase->mac_addr.raw);
  1382. dp_peer_del_ast(soc, ase);
  1383. }
  1384. }
  1385. }
  1386. }
  1387. qdf_spin_unlock_bh(&soc->ast_lock);
  1388. if (qdf_atomic_read(&soc->cmn_init_done))
  1389. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1390. }
  1391. /*
  1392. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1393. * @soc: Datapath SOC handle
  1394. *
  1395. * Return: None
  1396. */
  1397. static void dp_soc_wds_attach(struct dp_soc *soc)
  1398. {
  1399. qdf_spinlock_create(&soc->ast_lock);
  1400. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1401. dp_wds_aging_timer_fn, (void *)soc,
  1402. QDF_TIMER_TYPE_WAKE_APPS);
  1403. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1404. }
  1405. /*
  1406. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1407. * @txrx_soc: DP SOC handle
  1408. *
  1409. * Return: None
  1410. */
  1411. static void dp_soc_wds_detach(struct dp_soc *soc)
  1412. {
  1413. qdf_timer_stop(&soc->wds_aging_timer);
  1414. qdf_timer_free(&soc->wds_aging_timer);
  1415. qdf_spinlock_destroy(&soc->ast_lock);
  1416. }
  1417. #else
  1418. static void dp_soc_wds_attach(struct dp_soc *soc)
  1419. {
  1420. }
  1421. static void dp_soc_wds_detach(struct dp_soc *soc)
  1422. {
  1423. }
  1424. #endif
  1425. /*
  1426. * dp_soc_reset_ring_map() - Reset cpu ring map
  1427. * @soc: Datapath soc handler
  1428. *
  1429. * This api resets the default cpu ring map
  1430. */
  1431. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1432. {
  1433. uint8_t i;
  1434. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1435. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1436. if (nss_config == 1) {
  1437. /*
  1438. * Setting Tx ring map for one nss offloaded radio
  1439. */
  1440. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1441. } else if (nss_config == 2) {
  1442. /*
  1443. * Setting Tx ring for two nss offloaded radios
  1444. */
  1445. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1446. } else {
  1447. /*
  1448. * Setting Tx ring map for all nss offloaded radios
  1449. */
  1450. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1451. }
  1452. }
  1453. }
  1454. #ifdef IPA_OFFLOAD
  1455. /**
  1456. * dp_reo_remap_config() - configure reo remap register value based
  1457. * nss configuration.
  1458. * based on offload_radio value below remap configuration
  1459. * get applied.
  1460. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1461. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1462. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1463. * 3 - both Radios handled by NSS (remap not required)
  1464. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1465. *
  1466. * @remap1: output parameter indicates reo remap 1 register value
  1467. * @remap2: output parameter indicates reo remap 2 register value
  1468. * Return: bool type, true if remap is configured else false.
  1469. */
  1470. static bool dp_reo_remap_config(struct dp_soc *soc,
  1471. uint32_t *remap1,
  1472. uint32_t *remap2)
  1473. {
  1474. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1475. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1476. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1477. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1478. return true;
  1479. }
  1480. #else
  1481. static bool dp_reo_remap_config(struct dp_soc *soc,
  1482. uint32_t *remap1,
  1483. uint32_t *remap2)
  1484. {
  1485. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1486. switch (offload_radio) {
  1487. case 0:
  1488. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1489. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1490. (0x3 << 18) | (0x4 << 21)) << 8;
  1491. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1492. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1493. (0x3 << 18) | (0x4 << 21)) << 8;
  1494. break;
  1495. case 1:
  1496. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1497. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1498. (0x2 << 18) | (0x3 << 21)) << 8;
  1499. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1500. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1501. (0x4 << 18) | (0x2 << 21)) << 8;
  1502. break;
  1503. case 2:
  1504. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1505. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1506. (0x1 << 18) | (0x3 << 21)) << 8;
  1507. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1508. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1509. (0x4 << 18) | (0x1 << 21)) << 8;
  1510. break;
  1511. case 3:
  1512. /* return false if both radios are offloaded to NSS */
  1513. return false;
  1514. }
  1515. return true;
  1516. }
  1517. #endif
  1518. /*
  1519. * dp_soc_cmn_setup() - Common SoC level initializion
  1520. * @soc: Datapath SOC handle
  1521. *
  1522. * This is an internal function used to setup common SOC data structures,
  1523. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1524. */
  1525. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1526. {
  1527. int i;
  1528. struct hal_reo_params reo_params;
  1529. int tx_ring_size;
  1530. int tx_comp_ring_size;
  1531. if (qdf_atomic_read(&soc->cmn_init_done))
  1532. return 0;
  1533. if (dp_peer_find_attach(soc))
  1534. goto fail0;
  1535. if (dp_hw_link_desc_pool_setup(soc))
  1536. goto fail1;
  1537. /* Setup SRNG rings */
  1538. /* Common rings */
  1539. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1540. WBM_RELEASE_RING_SIZE)) {
  1541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1542. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1543. goto fail1;
  1544. }
  1545. soc->num_tcl_data_rings = 0;
  1546. /* Tx data rings */
  1547. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1548. soc->num_tcl_data_rings =
  1549. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1550. tx_comp_ring_size =
  1551. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1552. tx_ring_size =
  1553. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1554. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1555. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1556. TCL_DATA, i, 0, tx_ring_size)) {
  1557. QDF_TRACE(QDF_MODULE_ID_DP,
  1558. QDF_TRACE_LEVEL_ERROR,
  1559. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1560. goto fail1;
  1561. }
  1562. /*
  1563. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1564. * count
  1565. */
  1566. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1567. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1568. QDF_TRACE(QDF_MODULE_ID_DP,
  1569. QDF_TRACE_LEVEL_ERROR,
  1570. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1571. goto fail1;
  1572. }
  1573. }
  1574. } else {
  1575. /* This will be incremented during per pdev ring setup */
  1576. soc->num_tcl_data_rings = 0;
  1577. }
  1578. if (dp_tx_soc_attach(soc)) {
  1579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1580. FL("dp_tx_soc_attach failed"));
  1581. goto fail1;
  1582. }
  1583. /* TCL command and status rings */
  1584. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1585. TCL_CMD_RING_SIZE)) {
  1586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1587. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1588. goto fail1;
  1589. }
  1590. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1591. TCL_STATUS_RING_SIZE)) {
  1592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1593. FL("dp_srng_setup failed for tcl_status_ring"));
  1594. goto fail1;
  1595. }
  1596. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1597. * descriptors
  1598. */
  1599. /* Rx data rings */
  1600. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1601. soc->num_reo_dest_rings =
  1602. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1603. QDF_TRACE(QDF_MODULE_ID_DP,
  1604. QDF_TRACE_LEVEL_ERROR,
  1605. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1606. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1607. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1608. i, 0, REO_DST_RING_SIZE)) {
  1609. QDF_TRACE(QDF_MODULE_ID_DP,
  1610. QDF_TRACE_LEVEL_ERROR,
  1611. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1612. goto fail1;
  1613. }
  1614. }
  1615. } else {
  1616. /* This will be incremented during per pdev ring setup */
  1617. soc->num_reo_dest_rings = 0;
  1618. }
  1619. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1620. /* REO reinjection ring */
  1621. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1622. REO_REINJECT_RING_SIZE)) {
  1623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1624. FL("dp_srng_setup failed for reo_reinject_ring"));
  1625. goto fail1;
  1626. }
  1627. /* Rx release ring */
  1628. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1629. RX_RELEASE_RING_SIZE)) {
  1630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1631. FL("dp_srng_setup failed for rx_rel_ring"));
  1632. goto fail1;
  1633. }
  1634. /* Rx exception ring */
  1635. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1636. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1638. FL("dp_srng_setup failed for reo_exception_ring"));
  1639. goto fail1;
  1640. }
  1641. /* REO command and status rings */
  1642. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1643. REO_CMD_RING_SIZE)) {
  1644. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1645. FL("dp_srng_setup failed for reo_cmd_ring"));
  1646. goto fail1;
  1647. }
  1648. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1649. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1650. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1651. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1652. REO_STATUS_RING_SIZE)) {
  1653. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1654. FL("dp_srng_setup failed for reo_status_ring"));
  1655. goto fail1;
  1656. }
  1657. dp_soc_wds_attach(soc);
  1658. /* Reset the cpu ring map if radio is NSS offloaded */
  1659. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1660. dp_soc_reset_cpu_ring_map(soc);
  1661. }
  1662. /* Setup HW REO */
  1663. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1664. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1665. /*
  1666. * Reo ring remap is not required if both radios
  1667. * are offloaded to NSS
  1668. */
  1669. if (!dp_reo_remap_config(soc,
  1670. &reo_params.remap1,
  1671. &reo_params.remap2))
  1672. goto out;
  1673. reo_params.rx_hash_enabled = true;
  1674. }
  1675. out:
  1676. hal_reo_setup(soc->hal_soc, &reo_params);
  1677. qdf_atomic_set(&soc->cmn_init_done, 1);
  1678. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1679. return 0;
  1680. fail1:
  1681. /*
  1682. * Cleanup will be done as part of soc_detach, which will
  1683. * be called on pdev attach failure
  1684. */
  1685. fail0:
  1686. return QDF_STATUS_E_FAILURE;
  1687. }
  1688. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1689. static void dp_lro_hash_setup(struct dp_soc *soc)
  1690. {
  1691. struct cdp_lro_hash_config lro_hash;
  1692. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1693. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1695. FL("LRO disabled RX hash disabled"));
  1696. return;
  1697. }
  1698. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1699. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1700. lro_hash.lro_enable = 1;
  1701. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1702. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1703. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1704. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1705. }
  1706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1707. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1708. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1709. LRO_IPV4_SEED_ARR_SZ));
  1710. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1711. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1712. LRO_IPV6_SEED_ARR_SZ));
  1713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1714. "lro_hash: lro_enable: 0x%x"
  1715. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1716. lro_hash.lro_enable, lro_hash.tcp_flag,
  1717. lro_hash.tcp_flag_mask);
  1718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1719. FL("lro_hash: toeplitz_hash_ipv4:"));
  1720. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1721. QDF_TRACE_LEVEL_ERROR,
  1722. (void *)lro_hash.toeplitz_hash_ipv4,
  1723. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1724. LRO_IPV4_SEED_ARR_SZ));
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. FL("lro_hash: toeplitz_hash_ipv6:"));
  1727. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1728. QDF_TRACE_LEVEL_ERROR,
  1729. (void *)lro_hash.toeplitz_hash_ipv6,
  1730. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1731. LRO_IPV6_SEED_ARR_SZ));
  1732. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1733. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1734. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1735. (soc->osif_soc, &lro_hash);
  1736. }
  1737. /*
  1738. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1739. * @soc: data path SoC handle
  1740. * @pdev: Physical device handle
  1741. *
  1742. * Return: 0 - success, > 0 - failure
  1743. */
  1744. #ifdef QCA_HOST2FW_RXBUF_RING
  1745. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1746. struct dp_pdev *pdev)
  1747. {
  1748. int max_mac_rings =
  1749. wlan_cfg_get_num_mac_rings
  1750. (pdev->wlan_cfg_ctx);
  1751. int i;
  1752. for (i = 0; i < max_mac_rings; i++) {
  1753. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1754. "%s: pdev_id %d mac_id %d\n",
  1755. __func__, pdev->pdev_id, i);
  1756. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1757. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1758. QDF_TRACE(QDF_MODULE_ID_DP,
  1759. QDF_TRACE_LEVEL_ERROR,
  1760. FL("failed rx mac ring setup"));
  1761. return QDF_STATUS_E_FAILURE;
  1762. }
  1763. }
  1764. return QDF_STATUS_SUCCESS;
  1765. }
  1766. #else
  1767. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1768. struct dp_pdev *pdev)
  1769. {
  1770. return QDF_STATUS_SUCCESS;
  1771. }
  1772. #endif
  1773. /**
  1774. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1775. * @pdev - DP_PDEV handle
  1776. *
  1777. * Return: void
  1778. */
  1779. static inline void
  1780. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1781. {
  1782. uint8_t map_id;
  1783. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1784. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1785. sizeof(default_dscp_tid_map));
  1786. }
  1787. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1788. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1789. pdev->dscp_tid_map[map_id],
  1790. map_id);
  1791. }
  1792. }
  1793. /*
  1794. * dp_reset_intr_mask() - reset interrupt mask
  1795. * @dp_soc - DP Soc handle
  1796. * @dp_pdev - DP pdev handle
  1797. *
  1798. * Return: Return void
  1799. */
  1800. static inline
  1801. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1802. {
  1803. /*
  1804. * We will set the interrupt mask to zero for NSS offloaded radio
  1805. */
  1806. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1807. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1808. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1809. }
  1810. /*
  1811. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1812. * @soc: data path SoC handle
  1813. *
  1814. * Return: none
  1815. */
  1816. #ifdef IPA_OFFLOAD
  1817. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1818. struct dp_pdev *pdev)
  1819. {
  1820. void *hal_srng;
  1821. struct hal_srng_params srng_params;
  1822. qdf_dma_addr_t hp_addr, tp_addr;
  1823. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1824. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1825. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1826. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1827. srng_params.ring_base_paddr;
  1828. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1829. srng_params.ring_base_vaddr;
  1830. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1831. srng_params.num_entries * srng_params.entry_size;
  1832. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1833. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1834. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1835. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1836. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1837. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1838. srng_params.ring_base_paddr;
  1839. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1840. srng_params.ring_base_vaddr;
  1841. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1842. srng_params.num_entries * srng_params.entry_size;
  1843. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1844. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1845. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1846. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1847. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1848. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1849. srng_params.ring_base_paddr;
  1850. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1851. srng_params.ring_base_vaddr;
  1852. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1853. srng_params.num_entries * srng_params.entry_size;
  1854. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1855. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1856. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1857. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1858. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1859. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1860. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1861. __func__);
  1862. return -EFAULT;
  1863. }
  1864. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1865. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1866. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1867. srng_params.ring_base_paddr;
  1868. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1869. srng_params.ring_base_vaddr;
  1870. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1871. srng_params.num_entries * srng_params.entry_size;
  1872. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1873. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1874. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1875. "%s: ring_base_paddr:%p, ring_base_vaddr:%p"
  1876. "_entries:%d, hp_addr:%p\n",
  1877. __func__,
  1878. (void *)srng_params.ring_base_paddr,
  1879. (void *)srng_params.ring_base_vaddr,
  1880. srng_params.num_entries,
  1881. (void *)hp_addr);
  1882. return 0;
  1883. }
  1884. #else
  1885. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1886. struct dp_pdev *pdev)
  1887. {
  1888. return 0;
  1889. }
  1890. #endif
  1891. /*
  1892. * dp_pdev_attach_wifi3() - attach txrx pdev
  1893. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1894. * @txrx_soc: Datapath SOC handle
  1895. * @htc_handle: HTC handle for host-target interface
  1896. * @qdf_osdev: QDF OS device
  1897. * @pdev_id: PDEV ID
  1898. *
  1899. * Return: DP PDEV handle on success, NULL on failure
  1900. */
  1901. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1902. struct cdp_cfg *ctrl_pdev,
  1903. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1904. {
  1905. int tx_ring_size;
  1906. int tx_comp_ring_size;
  1907. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1908. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1909. if (!pdev) {
  1910. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1911. FL("DP PDEV memory allocation failed"));
  1912. goto fail0;
  1913. }
  1914. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1915. if (!pdev->wlan_cfg_ctx) {
  1916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1917. FL("pdev cfg_attach failed"));
  1918. qdf_mem_free(pdev);
  1919. goto fail0;
  1920. }
  1921. /*
  1922. * set nss pdev config based on soc config
  1923. */
  1924. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1925. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1926. pdev->soc = soc;
  1927. pdev->osif_pdev = ctrl_pdev;
  1928. pdev->pdev_id = pdev_id;
  1929. soc->pdev_list[pdev_id] = pdev;
  1930. soc->pdev_count++;
  1931. TAILQ_INIT(&pdev->vdev_list);
  1932. pdev->vdev_count = 0;
  1933. qdf_spinlock_create(&pdev->tx_mutex);
  1934. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1935. TAILQ_INIT(&pdev->neighbour_peers_list);
  1936. if (dp_soc_cmn_setup(soc)) {
  1937. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1938. FL("dp_soc_cmn_setup failed"));
  1939. goto fail1;
  1940. }
  1941. /* Setup per PDEV TCL rings if configured */
  1942. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1943. tx_ring_size =
  1944. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1945. tx_comp_ring_size =
  1946. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1947. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1948. pdev_id, pdev_id, tx_ring_size)) {
  1949. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1950. FL("dp_srng_setup failed for tcl_data_ring"));
  1951. goto fail1;
  1952. }
  1953. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1954. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1955. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1956. FL("dp_srng_setup failed for tx_comp_ring"));
  1957. goto fail1;
  1958. }
  1959. soc->num_tcl_data_rings++;
  1960. }
  1961. /* Tx specific init */
  1962. if (dp_tx_pdev_attach(pdev)) {
  1963. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1964. FL("dp_tx_pdev_attach failed"));
  1965. goto fail1;
  1966. }
  1967. /* Setup per PDEV REO rings if configured */
  1968. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1969. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1970. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1971. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1972. FL("dp_srng_setup failed for reo_dest_ringn"));
  1973. goto fail1;
  1974. }
  1975. soc->num_reo_dest_rings++;
  1976. }
  1977. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1978. RXDMA_REFILL_RING_SIZE)) {
  1979. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1980. FL("dp_srng_setup failed rx refill ring"));
  1981. goto fail1;
  1982. }
  1983. if (dp_rxdma_ring_setup(soc, pdev)) {
  1984. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1985. FL("RXDMA ring config failed"));
  1986. goto fail1;
  1987. }
  1988. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1989. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1992. goto fail1;
  1993. }
  1994. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1995. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1996. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1997. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1998. goto fail1;
  1999. }
  2000. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2001. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2002. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2003. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2004. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2005. goto fail1;
  2006. }
  2007. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2008. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2009. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2010. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2011. goto fail1;
  2012. }
  2013. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2014. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2015. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2016. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2017. goto fail1;
  2018. }
  2019. if (dp_ipa_ring_resource_setup(soc, pdev))
  2020. goto fail1;
  2021. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2022. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2023. "%s: dp_ipa_uc_attach failed\n", __func__);
  2024. goto fail1;
  2025. }
  2026. /* Rx specific init */
  2027. if (dp_rx_pdev_attach(pdev)) {
  2028. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2029. FL("dp_rx_pdev_attach failed "));
  2030. goto fail0;
  2031. }
  2032. DP_STATS_INIT(pdev);
  2033. #ifndef CONFIG_WIN
  2034. /* MCL */
  2035. dp_local_peer_id_pool_init(pdev);
  2036. #endif
  2037. dp_dscp_tid_map_setup(pdev);
  2038. /* Rx monitor mode specific init */
  2039. if (dp_rx_pdev_mon_attach(pdev)) {
  2040. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2041. "dp_rx_pdev_attach failed\n");
  2042. goto fail1;
  2043. }
  2044. if (dp_wdi_event_attach(pdev)) {
  2045. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2046. "dp_wdi_evet_attach failed\n");
  2047. goto fail1;
  2048. }
  2049. /* set the reo destination during initialization */
  2050. pdev->reo_dest = pdev->pdev_id + 1;
  2051. /*
  2052. * reset the interrupt mask for offloaded radio
  2053. */
  2054. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2055. dp_soc_reset_intr_mask(soc, pdev);
  2056. }
  2057. return (struct cdp_pdev *)pdev;
  2058. fail1:
  2059. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2060. fail0:
  2061. return NULL;
  2062. }
  2063. /*
  2064. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2065. * @soc: data path SoC handle
  2066. * @pdev: Physical device handle
  2067. *
  2068. * Return: void
  2069. */
  2070. #ifdef QCA_HOST2FW_RXBUF_RING
  2071. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2072. struct dp_pdev *pdev)
  2073. {
  2074. int max_mac_rings =
  2075. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2076. int i;
  2077. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2078. max_mac_rings : MAX_RX_MAC_RINGS;
  2079. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2080. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2081. RXDMA_BUF, 1);
  2082. }
  2083. #else
  2084. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2085. struct dp_pdev *pdev)
  2086. {
  2087. }
  2088. #endif
  2089. /*
  2090. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2091. * @pdev: device object
  2092. *
  2093. * Return: void
  2094. */
  2095. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2096. {
  2097. struct dp_neighbour_peer *peer = NULL;
  2098. struct dp_neighbour_peer *temp_peer = NULL;
  2099. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2100. neighbour_peer_list_elem, temp_peer) {
  2101. /* delete this peer from the list */
  2102. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2103. peer, neighbour_peer_list_elem);
  2104. qdf_mem_free(peer);
  2105. }
  2106. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2107. }
  2108. /*
  2109. * dp_pdev_detach_wifi3() - detach txrx pdev
  2110. * @txrx_pdev: Datapath PDEV handle
  2111. * @force: Force detach
  2112. *
  2113. */
  2114. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2115. {
  2116. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2117. struct dp_soc *soc = pdev->soc;
  2118. dp_wdi_event_detach(pdev);
  2119. dp_tx_pdev_detach(pdev);
  2120. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2121. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2122. TCL_DATA, pdev->pdev_id);
  2123. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2124. WBM2SW_RELEASE, pdev->pdev_id);
  2125. }
  2126. dp_rx_pdev_detach(pdev);
  2127. dp_rx_pdev_mon_detach(pdev);
  2128. dp_neighbour_peers_detach(pdev);
  2129. qdf_spinlock_destroy(&pdev->tx_mutex);
  2130. dp_ipa_uc_detach(soc, pdev);
  2131. /* Cleanup per PDEV REO rings if configured */
  2132. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2133. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2134. REO_DST, pdev->pdev_id);
  2135. }
  2136. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2137. dp_rxdma_ring_cleanup(soc, pdev);
  2138. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2139. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2140. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2141. RXDMA_MONITOR_STATUS, 0);
  2142. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2143. RXDMA_MONITOR_DESC, 0);
  2144. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2145. soc->pdev_list[pdev->pdev_id] = NULL;
  2146. soc->pdev_count--;
  2147. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2148. qdf_mem_free(pdev);
  2149. }
  2150. /*
  2151. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2152. * @soc: DP SOC handle
  2153. */
  2154. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2155. {
  2156. struct reo_desc_list_node *desc;
  2157. struct dp_rx_tid *rx_tid;
  2158. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2159. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2160. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2161. rx_tid = &desc->rx_tid;
  2162. qdf_mem_unmap_nbytes_single(soc->osdev,
  2163. rx_tid->hw_qdesc_paddr,
  2164. QDF_DMA_BIDIRECTIONAL,
  2165. rx_tid->hw_qdesc_alloc_size);
  2166. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2167. qdf_mem_free(desc);
  2168. }
  2169. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2170. qdf_list_destroy(&soc->reo_desc_freelist);
  2171. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2172. }
  2173. /*
  2174. * dp_soc_detach_wifi3() - Detach txrx SOC
  2175. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2176. */
  2177. static void dp_soc_detach_wifi3(void *txrx_soc)
  2178. {
  2179. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2180. int i;
  2181. qdf_atomic_set(&soc->cmn_init_done, 0);
  2182. qdf_flush_work(0, &soc->htt_stats.work);
  2183. qdf_disable_work(0, &soc->htt_stats.work);
  2184. /* Free pending htt stats messages */
  2185. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2186. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2187. if (soc->pdev_list[i])
  2188. dp_pdev_detach_wifi3(
  2189. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2190. }
  2191. dp_peer_find_detach(soc);
  2192. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2193. * SW descriptors
  2194. */
  2195. /* Free the ring memories */
  2196. /* Common rings */
  2197. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2198. dp_tx_soc_detach(soc);
  2199. /* Tx data rings */
  2200. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2201. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2202. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2203. TCL_DATA, i);
  2204. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2205. WBM2SW_RELEASE, i);
  2206. }
  2207. }
  2208. /* TCL command and status rings */
  2209. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2210. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2211. /* Rx data rings */
  2212. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2213. soc->num_reo_dest_rings =
  2214. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2215. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2216. /* TODO: Get number of rings and ring sizes
  2217. * from wlan_cfg
  2218. */
  2219. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2220. REO_DST, i);
  2221. }
  2222. }
  2223. /* REO reinjection ring */
  2224. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2225. /* Rx release ring */
  2226. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2227. /* Rx exception ring */
  2228. /* TODO: Better to store ring_type and ring_num in
  2229. * dp_srng during setup
  2230. */
  2231. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2232. /* REO command and status rings */
  2233. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2234. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2235. dp_hw_link_desc_pool_cleanup(soc);
  2236. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2237. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2238. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2239. htt_soc_detach(soc->htt_handle);
  2240. dp_reo_cmdlist_destroy(soc);
  2241. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2242. dp_reo_desc_freelist_destroy(soc);
  2243. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2244. dp_soc_wds_detach(soc);
  2245. qdf_mem_free(soc);
  2246. }
  2247. /*
  2248. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2249. * @soc: data path SoC handle
  2250. * @pdev: physical device handle
  2251. *
  2252. * Return: void
  2253. */
  2254. #ifdef IPA_OFFLOAD
  2255. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2256. struct dp_pdev *pdev)
  2257. {
  2258. htt_srng_setup(soc->htt_handle, 0,
  2259. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2260. }
  2261. #else
  2262. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2263. struct dp_pdev *pdev)
  2264. {
  2265. }
  2266. #endif
  2267. /*
  2268. * dp_rxdma_ring_config() - configure the RX DMA rings
  2269. *
  2270. * This function is used to configure the MAC rings.
  2271. * On MCL host provides buffers in Host2FW ring
  2272. * FW refills (copies) buffers to the ring and updates
  2273. * ring_idx in register
  2274. *
  2275. * @soc: data path SoC handle
  2276. *
  2277. * Return: void
  2278. */
  2279. #ifdef QCA_HOST2FW_RXBUF_RING
  2280. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2281. {
  2282. int i;
  2283. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2284. struct dp_pdev *pdev = soc->pdev_list[i];
  2285. if (pdev) {
  2286. int mac_id = 0;
  2287. int j;
  2288. bool dbs_enable = 0;
  2289. int max_mac_rings =
  2290. wlan_cfg_get_num_mac_rings
  2291. (pdev->wlan_cfg_ctx);
  2292. htt_srng_setup(soc->htt_handle, 0,
  2293. pdev->rx_refill_buf_ring.hal_srng,
  2294. RXDMA_BUF);
  2295. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2296. if (soc->cdp_soc.ol_ops->
  2297. is_hw_dbs_2x2_capable) {
  2298. dbs_enable = soc->cdp_soc.ol_ops->
  2299. is_hw_dbs_2x2_capable(soc->psoc);
  2300. }
  2301. if (dbs_enable) {
  2302. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2303. QDF_TRACE_LEVEL_ERROR,
  2304. FL("DBS enabled max_mac_rings %d\n"),
  2305. max_mac_rings);
  2306. } else {
  2307. max_mac_rings = 1;
  2308. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2309. QDF_TRACE_LEVEL_ERROR,
  2310. FL("DBS disabled, max_mac_rings %d\n"),
  2311. max_mac_rings);
  2312. }
  2313. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2314. FL("pdev_id %d max_mac_rings %d\n"),
  2315. pdev->pdev_id, max_mac_rings);
  2316. for (j = 0; j < max_mac_rings; j++) {
  2317. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2318. QDF_TRACE_LEVEL_ERROR,
  2319. FL("mac_id %d\n"), mac_id);
  2320. htt_srng_setup(soc->htt_handle, mac_id,
  2321. pdev->rx_mac_buf_ring[j]
  2322. .hal_srng,
  2323. RXDMA_BUF);
  2324. mac_id++;
  2325. }
  2326. /* Configure monitor mode rings */
  2327. htt_srng_setup(soc->htt_handle, i,
  2328. pdev->rxdma_mon_buf_ring.hal_srng,
  2329. RXDMA_MONITOR_BUF);
  2330. htt_srng_setup(soc->htt_handle, i,
  2331. pdev->rxdma_mon_dst_ring.hal_srng,
  2332. RXDMA_MONITOR_DST);
  2333. htt_srng_setup(soc->htt_handle, i,
  2334. pdev->rxdma_mon_status_ring.hal_srng,
  2335. RXDMA_MONITOR_STATUS);
  2336. htt_srng_setup(soc->htt_handle, i,
  2337. pdev->rxdma_mon_desc_ring.hal_srng,
  2338. RXDMA_MONITOR_DESC);
  2339. htt_srng_setup(soc->htt_handle, i,
  2340. pdev->rxdma_err_dst_ring.hal_srng,
  2341. RXDMA_DST);
  2342. }
  2343. }
  2344. }
  2345. #else
  2346. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2347. {
  2348. int i;
  2349. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2350. struct dp_pdev *pdev = soc->pdev_list[i];
  2351. if (pdev) {
  2352. htt_srng_setup(soc->htt_handle, i,
  2353. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2354. htt_srng_setup(soc->htt_handle, i,
  2355. pdev->rxdma_mon_buf_ring.hal_srng,
  2356. RXDMA_MONITOR_BUF);
  2357. htt_srng_setup(soc->htt_handle, i,
  2358. pdev->rxdma_mon_dst_ring.hal_srng,
  2359. RXDMA_MONITOR_DST);
  2360. htt_srng_setup(soc->htt_handle, i,
  2361. pdev->rxdma_mon_status_ring.hal_srng,
  2362. RXDMA_MONITOR_STATUS);
  2363. htt_srng_setup(soc->htt_handle, i,
  2364. pdev->rxdma_mon_desc_ring.hal_srng,
  2365. RXDMA_MONITOR_DESC);
  2366. htt_srng_setup(soc->htt_handle, i,
  2367. pdev->rxdma_err_dst_ring.hal_srng,
  2368. RXDMA_DST);
  2369. }
  2370. }
  2371. }
  2372. #endif
  2373. /*
  2374. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2375. * @txrx_soc: Datapath SOC handle
  2376. */
  2377. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2378. {
  2379. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2380. htt_soc_attach_target(soc->htt_handle);
  2381. dp_rxdma_ring_config(soc);
  2382. DP_STATS_INIT(soc);
  2383. /* initialize work queue for stats processing */
  2384. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2385. return 0;
  2386. }
  2387. /*
  2388. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2389. * @txrx_soc: Datapath SOC handle
  2390. */
  2391. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2392. {
  2393. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2394. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2395. }
  2396. /*
  2397. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2398. * @txrx_soc: Datapath SOC handle
  2399. * @nss_cfg: nss config
  2400. */
  2401. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2402. {
  2403. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2404. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2406. FL("nss-wifi<0> nss config is enabled"));
  2407. }
  2408. /*
  2409. * dp_vdev_attach_wifi3() - attach txrx vdev
  2410. * @txrx_pdev: Datapath PDEV handle
  2411. * @vdev_mac_addr: MAC address of the virtual interface
  2412. * @vdev_id: VDEV Id
  2413. * @wlan_op_mode: VDEV operating mode
  2414. *
  2415. * Return: DP VDEV handle on success, NULL on failure
  2416. */
  2417. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2418. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2419. {
  2420. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2421. struct dp_soc *soc = pdev->soc;
  2422. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2423. int tx_ring_size;
  2424. if (!vdev) {
  2425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2426. FL("DP VDEV memory allocation failed"));
  2427. goto fail0;
  2428. }
  2429. vdev->pdev = pdev;
  2430. vdev->vdev_id = vdev_id;
  2431. vdev->opmode = op_mode;
  2432. vdev->osdev = soc->osdev;
  2433. vdev->osif_rx = NULL;
  2434. vdev->osif_rsim_rx_decap = NULL;
  2435. vdev->osif_get_key = NULL;
  2436. vdev->osif_rx_mon = NULL;
  2437. vdev->osif_tx_free_ext = NULL;
  2438. vdev->osif_vdev = NULL;
  2439. vdev->delete.pending = 0;
  2440. vdev->safemode = 0;
  2441. vdev->drop_unenc = 1;
  2442. #ifdef notyet
  2443. vdev->filters_num = 0;
  2444. #endif
  2445. qdf_mem_copy(
  2446. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2447. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2448. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2449. vdev->dscp_tid_map_id = 0;
  2450. vdev->mcast_enhancement_en = 0;
  2451. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2452. /* TODO: Initialize default HTT meta data that will be used in
  2453. * TCL descriptors for packets transmitted from this VDEV
  2454. */
  2455. TAILQ_INIT(&vdev->peer_list);
  2456. /* add this vdev into the pdev's list */
  2457. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2458. pdev->vdev_count++;
  2459. dp_tx_vdev_attach(vdev);
  2460. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2461. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2462. goto fail1;
  2463. if ((soc->intr_mode == DP_INTR_POLL) &&
  2464. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2465. if (pdev->vdev_count == 1)
  2466. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2467. }
  2468. dp_lro_hash_setup(soc);
  2469. /* LRO */
  2470. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2471. wlan_op_mode_sta == vdev->opmode)
  2472. vdev->lro_enable = true;
  2473. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2474. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2476. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  2477. DP_STATS_INIT(vdev);
  2478. return (struct cdp_vdev *)vdev;
  2479. fail1:
  2480. dp_tx_vdev_detach(vdev);
  2481. qdf_mem_free(vdev);
  2482. fail0:
  2483. return NULL;
  2484. }
  2485. /**
  2486. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2487. * @vdev: Datapath VDEV handle
  2488. * @osif_vdev: OSIF vdev handle
  2489. * @txrx_ops: Tx and Rx operations
  2490. *
  2491. * Return: DP VDEV handle on success, NULL on failure
  2492. */
  2493. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2494. void *osif_vdev,
  2495. struct ol_txrx_ops *txrx_ops)
  2496. {
  2497. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2498. vdev->osif_vdev = osif_vdev;
  2499. vdev->osif_rx = txrx_ops->rx.rx;
  2500. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2501. vdev->osif_get_key = txrx_ops->get_key;
  2502. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2503. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2504. #ifdef notyet
  2505. #if ATH_SUPPORT_WAPI
  2506. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2507. #endif
  2508. #endif
  2509. #ifdef UMAC_SUPPORT_PROXY_ARP
  2510. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2511. #endif
  2512. vdev->me_convert = txrx_ops->me_convert;
  2513. /* TODO: Enable the following once Tx code is integrated */
  2514. txrx_ops->tx.tx = dp_tx_send;
  2515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2516. "DP Vdev Register success");
  2517. }
  2518. /*
  2519. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2520. * @txrx_vdev: Datapath VDEV handle
  2521. * @callback: Callback OL_IF on completion of detach
  2522. * @cb_context: Callback context
  2523. *
  2524. */
  2525. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2526. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2527. {
  2528. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2529. struct dp_pdev *pdev = vdev->pdev;
  2530. struct dp_soc *soc = pdev->soc;
  2531. /* preconditions */
  2532. qdf_assert(vdev);
  2533. /* remove the vdev from its parent pdev's list */
  2534. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2535. /*
  2536. * Use peer_ref_mutex while accessing peer_list, in case
  2537. * a peer is in the process of being removed from the list.
  2538. */
  2539. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2540. /* check that the vdev has no peers allocated */
  2541. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2542. /* debug print - will be removed later */
  2543. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2544. FL("not deleting vdev object %p (%pM)"
  2545. "until deletion finishes for all its peers"),
  2546. vdev, vdev->mac_addr.raw);
  2547. /* indicate that the vdev needs to be deleted */
  2548. vdev->delete.pending = 1;
  2549. vdev->delete.callback = callback;
  2550. vdev->delete.context = cb_context;
  2551. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2552. return;
  2553. }
  2554. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2555. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2556. vdev->vdev_id);
  2557. dp_tx_vdev_detach(vdev);
  2558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2559. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  2560. qdf_mem_free(vdev);
  2561. if (callback)
  2562. callback(cb_context);
  2563. }
  2564. /*
  2565. * dp_peer_create_wifi3() - attach txrx peer
  2566. * @txrx_vdev: Datapath VDEV handle
  2567. * @peer_mac_addr: Peer MAC address
  2568. *
  2569. * Return: DP peeer handle on success, NULL on failure
  2570. */
  2571. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2572. uint8_t *peer_mac_addr)
  2573. {
  2574. struct dp_peer *peer;
  2575. int i;
  2576. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2577. struct dp_pdev *pdev;
  2578. struct dp_soc *soc;
  2579. /* preconditions */
  2580. qdf_assert(vdev);
  2581. qdf_assert(peer_mac_addr);
  2582. pdev = vdev->pdev;
  2583. soc = pdev->soc;
  2584. #ifdef notyet
  2585. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2586. soc->mempool_ol_ath_peer);
  2587. #else
  2588. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2589. #endif
  2590. if (!peer)
  2591. return NULL; /* failure */
  2592. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2593. TAILQ_INIT(&peer->ast_entry_list);
  2594. /* store provided params */
  2595. peer->vdev = vdev;
  2596. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2597. qdf_spinlock_create(&peer->peer_info_lock);
  2598. qdf_mem_copy(
  2599. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2600. /* TODO: See of rx_opt_proc is really required */
  2601. peer->rx_opt_proc = soc->rx_opt_proc;
  2602. /* initialize the peer_id */
  2603. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2604. peer->peer_ids[i] = HTT_INVALID_PEER;
  2605. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2606. qdf_atomic_init(&peer->ref_cnt);
  2607. /* keep one reference for attach */
  2608. qdf_atomic_inc(&peer->ref_cnt);
  2609. /* add this peer into the vdev's list */
  2610. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2611. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2612. /* TODO: See if hash based search is required */
  2613. dp_peer_find_hash_add(soc, peer);
  2614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2615. "vdev %p created peer %p (%pM) ref_cnt: %d",
  2616. vdev, peer, peer->mac_addr.raw,
  2617. qdf_atomic_read(&peer->ref_cnt));
  2618. /*
  2619. * For every peer MAp message search and set if bss_peer
  2620. */
  2621. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2623. "vdev bss_peer!!!!");
  2624. peer->bss_peer = 1;
  2625. vdev->vap_bss_peer = peer;
  2626. }
  2627. #ifndef CONFIG_WIN
  2628. dp_local_peer_id_alloc(pdev, peer);
  2629. #endif
  2630. DP_STATS_INIT(peer);
  2631. return (void *)peer;
  2632. }
  2633. /*
  2634. * dp_peer_setup_wifi3() - initialize the peer
  2635. * @vdev_hdl: virtual device object
  2636. * @peer: Peer object
  2637. *
  2638. * Return: void
  2639. */
  2640. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2641. {
  2642. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2643. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2644. struct dp_pdev *pdev;
  2645. struct dp_soc *soc;
  2646. bool hash_based = 0;
  2647. enum cdp_host_reo_dest_ring reo_dest;
  2648. /* preconditions */
  2649. qdf_assert(vdev);
  2650. qdf_assert(peer);
  2651. pdev = vdev->pdev;
  2652. soc = pdev->soc;
  2653. dp_peer_rx_init(pdev, peer);
  2654. peer->last_assoc_rcvd = 0;
  2655. peer->last_disassoc_rcvd = 0;
  2656. peer->last_deauth_rcvd = 0;
  2657. /*
  2658. * hash based steering is disabled for Radios which are offloaded
  2659. * to NSS
  2660. */
  2661. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2662. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2664. FL("hash based steering for pdev: %d is %d\n"),
  2665. pdev->pdev_id, hash_based);
  2666. if (!hash_based)
  2667. reo_dest = pdev->reo_dest;
  2668. else
  2669. reo_dest = 1;
  2670. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2671. /* TODO: Check the destination ring number to be passed to FW */
  2672. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2673. pdev->osif_pdev, peer->mac_addr.raw,
  2674. peer->vdev->vdev_id, hash_based, reo_dest);
  2675. }
  2676. return;
  2677. }
  2678. /*
  2679. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2680. * @vdev_handle: virtual device object
  2681. * @htt_pkt_type: type of pkt
  2682. *
  2683. * Return: void
  2684. */
  2685. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2686. enum htt_cmn_pkt_type val)
  2687. {
  2688. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2689. vdev->tx_encap_type = val;
  2690. }
  2691. /*
  2692. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2693. * @vdev_handle: virtual device object
  2694. * @htt_pkt_type: type of pkt
  2695. *
  2696. * Return: void
  2697. */
  2698. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2699. enum htt_cmn_pkt_type val)
  2700. {
  2701. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2702. vdev->rx_decap_type = val;
  2703. }
  2704. /*
  2705. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2706. * @pdev_handle: physical device object
  2707. * @val: reo destination ring index (1 - 4)
  2708. *
  2709. * Return: void
  2710. */
  2711. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2712. enum cdp_host_reo_dest_ring val)
  2713. {
  2714. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2715. if (pdev)
  2716. pdev->reo_dest = val;
  2717. }
  2718. /*
  2719. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2720. * @pdev_handle: physical device object
  2721. *
  2722. * Return: reo destination ring index
  2723. */
  2724. static enum cdp_host_reo_dest_ring
  2725. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2726. {
  2727. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2728. if (pdev)
  2729. return pdev->reo_dest;
  2730. else
  2731. return cdp_host_reo_dest_ring_unknown;
  2732. }
  2733. #ifdef QCA_SUPPORT_SON
  2734. static void dp_son_peer_authorize(struct dp_peer *peer)
  2735. {
  2736. struct dp_soc *soc;
  2737. soc = peer->vdev->pdev->soc;
  2738. peer->peer_bs_inact_flag = 0;
  2739. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2740. return;
  2741. }
  2742. #else
  2743. static void dp_son_peer_authorize(struct dp_peer *peer)
  2744. {
  2745. return;
  2746. }
  2747. #endif
  2748. /*
  2749. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2750. * @pdev_handle: device object
  2751. * @val: value to be set
  2752. *
  2753. * Return: void
  2754. */
  2755. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2756. uint32_t val)
  2757. {
  2758. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2759. /* Enable/Disable smart mesh filtering. This flag will be checked
  2760. * during rx processing to check if packets are from NAC clients.
  2761. */
  2762. pdev->filter_neighbour_peers = val;
  2763. return 0;
  2764. }
  2765. /*
  2766. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2767. * address for smart mesh filtering
  2768. * @pdev_handle: device object
  2769. * @cmd: Add/Del command
  2770. * @macaddr: nac client mac address
  2771. *
  2772. * Return: void
  2773. */
  2774. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2775. uint32_t cmd, uint8_t *macaddr)
  2776. {
  2777. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2778. struct dp_neighbour_peer *peer = NULL;
  2779. if (!macaddr)
  2780. goto fail0;
  2781. /* Store address of NAC (neighbour peer) which will be checked
  2782. * against TA of received packets.
  2783. */
  2784. if (cmd == DP_NAC_PARAM_ADD) {
  2785. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2786. sizeof(*peer));
  2787. if (!peer) {
  2788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2789. FL("DP neighbour peer node memory allocation failed"));
  2790. goto fail0;
  2791. }
  2792. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2793. macaddr, DP_MAC_ADDR_LEN);
  2794. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2795. /* add this neighbour peer into the list */
  2796. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2797. neighbour_peer_list_elem);
  2798. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2799. return 1;
  2800. } else if (cmd == DP_NAC_PARAM_DEL) {
  2801. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2802. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2803. neighbour_peer_list_elem) {
  2804. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2805. macaddr, DP_MAC_ADDR_LEN)) {
  2806. /* delete this peer from the list */
  2807. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2808. peer, neighbour_peer_list_elem);
  2809. qdf_mem_free(peer);
  2810. break;
  2811. }
  2812. }
  2813. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2814. return 1;
  2815. }
  2816. fail0:
  2817. return 0;
  2818. }
  2819. /*
  2820. * dp_get_sec_type() - Get the security type
  2821. * @peer: Datapath peer handle
  2822. * @sec_idx: Security id (mcast, ucast)
  2823. *
  2824. * return sec_type: Security type
  2825. */
  2826. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2827. {
  2828. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2829. return dpeer->security[sec_idx].sec_type;
  2830. }
  2831. /*
  2832. * dp_peer_authorize() - authorize txrx peer
  2833. * @peer_handle: Datapath peer handle
  2834. * @authorize
  2835. *
  2836. */
  2837. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2838. {
  2839. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2840. struct dp_soc *soc;
  2841. if (peer != NULL) {
  2842. soc = peer->vdev->pdev->soc;
  2843. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2844. dp_son_peer_authorize(peer);
  2845. peer->authorize = authorize ? 1 : 0;
  2846. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2847. }
  2848. }
  2849. /*
  2850. * dp_peer_unref_delete() - unref and delete peer
  2851. * @peer_handle: Datapath peer handle
  2852. *
  2853. */
  2854. void dp_peer_unref_delete(void *peer_handle)
  2855. {
  2856. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2857. struct dp_vdev *vdev = peer->vdev;
  2858. struct dp_pdev *pdev = vdev->pdev;
  2859. struct dp_soc *soc = pdev->soc;
  2860. struct dp_peer *tmppeer;
  2861. int found = 0;
  2862. uint16_t peer_id;
  2863. /*
  2864. * Hold the lock all the way from checking if the peer ref count
  2865. * is zero until the peer references are removed from the hash
  2866. * table and vdev list (if the peer ref count is zero).
  2867. * This protects against a new HL tx operation starting to use the
  2868. * peer object just after this function concludes it's done being used.
  2869. * Furthermore, the lock needs to be held while checking whether the
  2870. * vdev's list of peers is empty, to make sure that list is not modified
  2871. * concurrently with the empty check.
  2872. */
  2873. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2874. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2875. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2876. peer, qdf_atomic_read(&peer->ref_cnt));
  2877. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2878. peer_id = peer->peer_ids[0];
  2879. /*
  2880. * Make sure that the reference to the peer in
  2881. * peer object map is removed
  2882. */
  2883. if (peer_id != HTT_INVALID_PEER)
  2884. soc->peer_id_to_obj_map[peer_id] = NULL;
  2885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2886. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2887. /* remove the reference to the peer from the hash table */
  2888. dp_peer_find_hash_remove(soc, peer);
  2889. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2890. if (tmppeer == peer) {
  2891. found = 1;
  2892. break;
  2893. }
  2894. }
  2895. if (found) {
  2896. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2897. peer_list_elem);
  2898. } else {
  2899. /*Ignoring the remove operation as peer not found*/
  2900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2901. "peer %p not found in vdev (%p)->peer_list:%p",
  2902. peer, vdev, &peer->vdev->peer_list);
  2903. }
  2904. /* cleanup the peer data */
  2905. dp_peer_cleanup(vdev, peer);
  2906. /* check whether the parent vdev has no peers left */
  2907. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2908. /*
  2909. * Now that there are no references to the peer, we can
  2910. * release the peer reference lock.
  2911. */
  2912. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2913. /*
  2914. * Check if the parent vdev was waiting for its peers
  2915. * to be deleted, in order for it to be deleted too.
  2916. */
  2917. if (vdev->delete.pending) {
  2918. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2919. vdev->delete.callback;
  2920. void *vdev_delete_context =
  2921. vdev->delete.context;
  2922. QDF_TRACE(QDF_MODULE_ID_DP,
  2923. QDF_TRACE_LEVEL_INFO_HIGH,
  2924. FL("deleting vdev object %p (%pM)"
  2925. " - its last peer is done"),
  2926. vdev, vdev->mac_addr.raw);
  2927. /* all peers are gone, go ahead and delete it */
  2928. qdf_mem_free(vdev);
  2929. if (vdev_delete_cb)
  2930. vdev_delete_cb(vdev_delete_context);
  2931. }
  2932. } else {
  2933. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2934. }
  2935. #ifdef notyet
  2936. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2937. #else
  2938. qdf_mem_free(peer);
  2939. #endif
  2940. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2941. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2942. vdev->vdev_id, peer->mac_addr.raw);
  2943. }
  2944. } else {
  2945. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2946. }
  2947. }
  2948. /*
  2949. * dp_peer_detach_wifi3() – Detach txrx peer
  2950. * @peer_handle: Datapath peer handle
  2951. *
  2952. */
  2953. static void dp_peer_delete_wifi3(void *peer_handle)
  2954. {
  2955. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2956. /* redirect the peer's rx delivery function to point to a
  2957. * discard func
  2958. */
  2959. peer->rx_opt_proc = dp_rx_discard;
  2960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2961. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2962. #ifndef CONFIG_WIN
  2963. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2964. #endif
  2965. qdf_spinlock_destroy(&peer->peer_info_lock);
  2966. /*
  2967. * Remove the reference added during peer_attach.
  2968. * The peer will still be left allocated until the
  2969. * PEER_UNMAP message arrives to remove the other
  2970. * reference, added by the PEER_MAP message.
  2971. */
  2972. dp_peer_unref_delete(peer_handle);
  2973. }
  2974. /*
  2975. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2976. * @peer_handle: Datapath peer handle
  2977. *
  2978. */
  2979. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2980. {
  2981. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2982. return vdev->mac_addr.raw;
  2983. }
  2984. /*
  2985. * dp_vdev_set_wds() - Enable per packet stats
  2986. * @vdev_handle: DP VDEV handle
  2987. * @val: value
  2988. *
  2989. * Return: none
  2990. */
  2991. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2992. {
  2993. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2994. vdev->wds_enabled = val;
  2995. return 0;
  2996. }
  2997. /*
  2998. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2999. * @peer_handle: Datapath peer handle
  3000. *
  3001. */
  3002. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3003. uint8_t vdev_id)
  3004. {
  3005. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3006. struct dp_vdev *vdev = NULL;
  3007. if (qdf_unlikely(!pdev))
  3008. return NULL;
  3009. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3010. if (vdev->vdev_id == vdev_id)
  3011. break;
  3012. }
  3013. return (struct cdp_vdev *)vdev;
  3014. }
  3015. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3016. {
  3017. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3018. return vdev->opmode;
  3019. }
  3020. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3021. {
  3022. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3023. struct dp_pdev *pdev = vdev->pdev;
  3024. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3025. }
  3026. /**
  3027. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3028. * @vdev_handle: Datapath VDEV handle
  3029. * @smart_monitor: Flag to denote if its smart monitor mode
  3030. *
  3031. * Return: 0 on success, not 0 on failure
  3032. */
  3033. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3034. uint8_t smart_monitor)
  3035. {
  3036. /* Many monitor VAPs can exists in a system but only one can be up at
  3037. * anytime
  3038. */
  3039. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3040. struct dp_pdev *pdev;
  3041. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3042. struct dp_soc *soc;
  3043. uint8_t pdev_id;
  3044. qdf_assert(vdev);
  3045. pdev = vdev->pdev;
  3046. pdev_id = pdev->pdev_id;
  3047. soc = pdev->soc;
  3048. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3049. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  3050. pdev, pdev_id, soc, vdev);
  3051. /*Check if current pdev's monitor_vdev exists */
  3052. if (pdev->monitor_vdev) {
  3053. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3054. "vdev=%p\n", vdev);
  3055. qdf_assert(vdev);
  3056. }
  3057. pdev->monitor_vdev = vdev;
  3058. /* If smart monitor mode, do not configure monitor ring */
  3059. if (smart_monitor)
  3060. return QDF_STATUS_SUCCESS;
  3061. htt_tlv_filter.mpdu_start = 1;
  3062. htt_tlv_filter.msdu_start = 1;
  3063. htt_tlv_filter.packet = 1;
  3064. htt_tlv_filter.msdu_end = 1;
  3065. htt_tlv_filter.mpdu_end = 1;
  3066. htt_tlv_filter.packet_header = 1;
  3067. htt_tlv_filter.attention = 1;
  3068. htt_tlv_filter.ppdu_start = 0;
  3069. htt_tlv_filter.ppdu_end = 0;
  3070. htt_tlv_filter.ppdu_end_user_stats = 0;
  3071. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3072. htt_tlv_filter.ppdu_end_status_done = 0;
  3073. htt_tlv_filter.enable_fp = 1;
  3074. htt_tlv_filter.enable_md = 0;
  3075. htt_tlv_filter.enable_mo = 1;
  3076. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3077. pdev->rxdma_mon_buf_ring.hal_srng,
  3078. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3079. htt_tlv_filter.mpdu_start = 1;
  3080. htt_tlv_filter.msdu_start = 1;
  3081. htt_tlv_filter.packet = 0;
  3082. htt_tlv_filter.msdu_end = 1;
  3083. htt_tlv_filter.mpdu_end = 1;
  3084. htt_tlv_filter.packet_header = 1;
  3085. htt_tlv_filter.attention = 1;
  3086. htt_tlv_filter.ppdu_start = 1;
  3087. htt_tlv_filter.ppdu_end = 1;
  3088. htt_tlv_filter.ppdu_end_user_stats = 1;
  3089. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3090. htt_tlv_filter.ppdu_end_status_done = 1;
  3091. htt_tlv_filter.enable_fp = 1;
  3092. htt_tlv_filter.enable_md = 0;
  3093. htt_tlv_filter.enable_mo = 1;
  3094. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3095. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3096. RX_BUFFER_SIZE, &htt_tlv_filter);
  3097. return QDF_STATUS_SUCCESS;
  3098. }
  3099. #ifdef MESH_MODE_SUPPORT
  3100. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3101. {
  3102. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3104. FL("val %d"), val);
  3105. vdev->mesh_vdev = val;
  3106. }
  3107. /*
  3108. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3109. * @vdev_hdl: virtual device object
  3110. * @val: value to be set
  3111. *
  3112. * Return: void
  3113. */
  3114. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3115. {
  3116. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3117. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3118. FL("val %d"), val);
  3119. vdev->mesh_rx_filter = val;
  3120. }
  3121. #endif
  3122. /**
  3123. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3124. * @vdev: DP VDEV handle
  3125. *
  3126. * return: void
  3127. */
  3128. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3129. {
  3130. struct dp_peer *peer = NULL;
  3131. struct dp_soc *soc = vdev->pdev->soc;
  3132. int i;
  3133. uint8_t pream_type;
  3134. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3135. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3136. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3137. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3138. for (i = 0; i < MAX_MCS; i++) {
  3139. DP_STATS_AGGR(vdev, peer,
  3140. tx.pkt_type[pream_type].mcs_count[i]);
  3141. DP_STATS_AGGR(vdev, peer,
  3142. rx.pkt_type[pream_type].mcs_count[i]);
  3143. }
  3144. }
  3145. for (i = 0; i < MAX_BW; i++) {
  3146. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3147. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3148. }
  3149. for (i = 0; i < SS_COUNT; i++)
  3150. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3151. for (i = 0; i < WME_AC_MAX; i++) {
  3152. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3153. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3154. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3155. }
  3156. for (i = 0; i < MAX_GI; i++) {
  3157. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3158. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3159. }
  3160. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3161. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3162. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3163. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3164. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3165. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3166. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3167. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3168. DP_STATS_AGGR(vdev, peer, tx.retries);
  3169. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3170. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3171. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3172. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3173. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3174. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3175. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3176. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3177. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3178. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3179. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3180. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3181. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3182. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3183. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3184. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3185. peer->stats.rx.multicast.num;
  3186. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3187. peer->stats.rx.multicast.bytes;
  3188. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3189. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3190. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3191. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3192. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3193. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3194. vdev->stats.tx.last_ack_rssi =
  3195. peer->stats.tx.last_ack_rssi;
  3196. }
  3197. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3198. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3199. }
  3200. /**
  3201. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3202. * @pdev: DP PDEV handle
  3203. *
  3204. * return: void
  3205. */
  3206. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3207. {
  3208. struct dp_vdev *vdev = NULL;
  3209. uint8_t i;
  3210. uint8_t pream_type;
  3211. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3212. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3213. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3214. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3215. dp_aggregate_vdev_stats(vdev);
  3216. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3217. for (i = 0; i < MAX_MCS; i++) {
  3218. DP_STATS_AGGR(pdev, vdev,
  3219. tx.pkt_type[pream_type].mcs_count[i]);
  3220. DP_STATS_AGGR(pdev, vdev,
  3221. rx.pkt_type[pream_type].mcs_count[i]);
  3222. }
  3223. }
  3224. for (i = 0; i < MAX_BW; i++) {
  3225. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3226. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3227. }
  3228. for (i = 0; i < SS_COUNT; i++)
  3229. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3230. for (i = 0; i < WME_AC_MAX; i++) {
  3231. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3232. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3233. DP_STATS_AGGR(pdev, vdev,
  3234. tx.excess_retries_ac[i]);
  3235. }
  3236. for (i = 0; i < MAX_GI; i++) {
  3237. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3238. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3239. }
  3240. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3241. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3242. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3243. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3244. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3245. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3246. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3247. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3248. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3249. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3250. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3251. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3252. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3253. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3254. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3255. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3256. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3257. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3258. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3259. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3260. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3261. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3262. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3263. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3264. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3265. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3266. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3267. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3268. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3269. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3270. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3271. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3272. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3273. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3274. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3275. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3276. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3277. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3278. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3279. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3280. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3281. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3282. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3283. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3284. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3285. DP_STATS_AGGR(pdev, vdev,
  3286. tx_i.mcast_en.dropped_map_error);
  3287. DP_STATS_AGGR(pdev, vdev,
  3288. tx_i.mcast_en.dropped_self_mac);
  3289. DP_STATS_AGGR(pdev, vdev,
  3290. tx_i.mcast_en.dropped_send_fail);
  3291. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3292. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3293. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3294. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3295. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3296. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3297. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3298. pdev->stats.tx_i.dropped.dma_error +
  3299. pdev->stats.tx_i.dropped.ring_full +
  3300. pdev->stats.tx_i.dropped.enqueue_fail +
  3301. pdev->stats.tx_i.dropped.desc_na +
  3302. pdev->stats.tx_i.dropped.res_full;
  3303. pdev->stats.tx.last_ack_rssi =
  3304. vdev->stats.tx.last_ack_rssi;
  3305. pdev->stats.tx_i.tso.num_seg =
  3306. vdev->stats.tx_i.tso.num_seg;
  3307. }
  3308. }
  3309. /**
  3310. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3311. * @pdev: DP_PDEV Handle
  3312. *
  3313. * Return:void
  3314. */
  3315. static inline void
  3316. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3317. {
  3318. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3319. DP_PRINT_STATS("Received From Stack:");
  3320. DP_PRINT_STATS(" Packets = %d",
  3321. pdev->stats.tx_i.rcvd.num);
  3322. DP_PRINT_STATS(" Bytes = %d",
  3323. pdev->stats.tx_i.rcvd.bytes);
  3324. DP_PRINT_STATS("Processed:");
  3325. DP_PRINT_STATS(" Packets = %d",
  3326. pdev->stats.tx_i.processed.num);
  3327. DP_PRINT_STATS(" Bytes = %d",
  3328. pdev->stats.tx_i.processed.bytes);
  3329. DP_PRINT_STATS("Completions:");
  3330. DP_PRINT_STATS(" Packets = %d",
  3331. pdev->stats.tx.comp_pkt.num);
  3332. DP_PRINT_STATS(" Bytes = %d",
  3333. pdev->stats.tx.comp_pkt.bytes);
  3334. DP_PRINT_STATS("Dropped:");
  3335. DP_PRINT_STATS(" Total = %d",
  3336. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3337. DP_PRINT_STATS(" Dma_map_error = %d",
  3338. pdev->stats.tx_i.dropped.dma_error);
  3339. DP_PRINT_STATS(" Ring Full = %d",
  3340. pdev->stats.tx_i.dropped.ring_full);
  3341. DP_PRINT_STATS(" Descriptor Not available = %d",
  3342. pdev->stats.tx_i.dropped.desc_na);
  3343. DP_PRINT_STATS(" HW enqueue failed= %d",
  3344. pdev->stats.tx_i.dropped.enqueue_fail);
  3345. DP_PRINT_STATS(" Resources Full = %d",
  3346. pdev->stats.tx_i.dropped.res_full);
  3347. DP_PRINT_STATS(" FW removed = %d",
  3348. pdev->stats.tx.dropped.fw_rem);
  3349. DP_PRINT_STATS(" FW removed transmitted = %d",
  3350. pdev->stats.tx.dropped.fw_rem_tx);
  3351. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3352. pdev->stats.tx.dropped.fw_rem_notx);
  3353. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3354. pdev->stats.tx.dropped.age_out);
  3355. DP_PRINT_STATS("Scatter Gather:");
  3356. DP_PRINT_STATS(" Packets = %d",
  3357. pdev->stats.tx_i.sg.sg_pkt.num);
  3358. DP_PRINT_STATS(" Bytes = %d",
  3359. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3360. DP_PRINT_STATS(" Dropped By Host = %d",
  3361. pdev->stats.tx_i.sg.dropped_host);
  3362. DP_PRINT_STATS(" Dropped By Target = %d",
  3363. pdev->stats.tx_i.sg.dropped_target);
  3364. DP_PRINT_STATS("TSO:");
  3365. DP_PRINT_STATS(" Number of Segments = %d",
  3366. pdev->stats.tx_i.tso.num_seg);
  3367. DP_PRINT_STATS(" Packets = %d",
  3368. pdev->stats.tx_i.tso.tso_pkt.num);
  3369. DP_PRINT_STATS(" Bytes = %d",
  3370. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3371. DP_PRINT_STATS(" Dropped By Host = %d",
  3372. pdev->stats.tx_i.tso.dropped_host);
  3373. DP_PRINT_STATS("Mcast Enhancement:");
  3374. DP_PRINT_STATS(" Packets = %d",
  3375. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3376. DP_PRINT_STATS(" Bytes = %d",
  3377. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3378. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3379. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3380. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3381. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3382. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3383. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3384. DP_PRINT_STATS(" Unicast sent = %d",
  3385. pdev->stats.tx_i.mcast_en.ucast);
  3386. DP_PRINT_STATS("Raw:");
  3387. DP_PRINT_STATS(" Packets = %d",
  3388. pdev->stats.tx_i.raw.raw_pkt.num);
  3389. DP_PRINT_STATS(" Bytes = %d",
  3390. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3391. DP_PRINT_STATS(" DMA map error = %d",
  3392. pdev->stats.tx_i.raw.dma_map_error);
  3393. DP_PRINT_STATS("Reinjected:");
  3394. DP_PRINT_STATS(" Packets = %d",
  3395. pdev->stats.tx_i.reinject_pkts.num);
  3396. DP_PRINT_STATS("Bytes = %d\n",
  3397. pdev->stats.tx_i.reinject_pkts.bytes);
  3398. DP_PRINT_STATS("Inspected:");
  3399. DP_PRINT_STATS(" Packets = %d",
  3400. pdev->stats.tx_i.inspect_pkts.num);
  3401. DP_PRINT_STATS(" Bytes = %d",
  3402. pdev->stats.tx_i.inspect_pkts.bytes);
  3403. }
  3404. /**
  3405. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3406. * @pdev: DP_PDEV Handle
  3407. *
  3408. * Return: void
  3409. */
  3410. static inline void
  3411. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3412. {
  3413. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3414. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3415. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3416. pdev->stats.rx.rcvd_reo[0].num,
  3417. pdev->stats.rx.rcvd_reo[1].num,
  3418. pdev->stats.rx.rcvd_reo[2].num,
  3419. pdev->stats.rx.rcvd_reo[3].num);
  3420. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3421. pdev->stats.rx.rcvd_reo[0].bytes,
  3422. pdev->stats.rx.rcvd_reo[1].bytes,
  3423. pdev->stats.rx.rcvd_reo[2].bytes,
  3424. pdev->stats.rx.rcvd_reo[3].bytes);
  3425. DP_PRINT_STATS("Replenished:");
  3426. DP_PRINT_STATS(" Packets = %d",
  3427. pdev->stats.replenish.pkts.num);
  3428. DP_PRINT_STATS(" Bytes = %d",
  3429. pdev->stats.replenish.pkts.bytes);
  3430. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3431. pdev->stats.buf_freelist);
  3432. DP_PRINT_STATS("Dropped:");
  3433. DP_PRINT_STATS(" msdu_not_done = %d",
  3434. pdev->stats.dropped.msdu_not_done);
  3435. DP_PRINT_STATS("Sent To Stack:");
  3436. DP_PRINT_STATS(" Packets = %d",
  3437. pdev->stats.rx.to_stack.num);
  3438. DP_PRINT_STATS(" Bytes = %d",
  3439. pdev->stats.rx.to_stack.bytes);
  3440. DP_PRINT_STATS("Multicast/Broadcast:");
  3441. DP_PRINT_STATS(" Packets = %d",
  3442. pdev->stats.rx.multicast.num);
  3443. DP_PRINT_STATS(" Bytes = %d",
  3444. pdev->stats.rx.multicast.bytes);
  3445. DP_PRINT_STATS("Errors:");
  3446. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3447. pdev->stats.replenish.rxdma_err);
  3448. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3449. pdev->stats.err.desc_alloc_fail);
  3450. }
  3451. /**
  3452. * dp_print_soc_tx_stats(): Print SOC level stats
  3453. * @soc DP_SOC Handle
  3454. *
  3455. * Return: void
  3456. */
  3457. static inline void
  3458. dp_print_soc_tx_stats(struct dp_soc *soc)
  3459. {
  3460. DP_PRINT_STATS("SOC Tx Stats:\n");
  3461. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3462. soc->stats.tx.desc_in_use);
  3463. DP_PRINT_STATS("Invalid peer:");
  3464. DP_PRINT_STATS(" Packets = %d",
  3465. soc->stats.tx.tx_invalid_peer.num);
  3466. DP_PRINT_STATS(" Bytes = %d",
  3467. soc->stats.tx.tx_invalid_peer.bytes);
  3468. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3469. soc->stats.tx.tcl_ring_full[0],
  3470. soc->stats.tx.tcl_ring_full[1],
  3471. soc->stats.tx.tcl_ring_full[2]);
  3472. }
  3473. /**
  3474. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3475. * @soc: DP_SOC Handle
  3476. *
  3477. * Return:void
  3478. */
  3479. static inline void
  3480. dp_print_soc_rx_stats(struct dp_soc *soc)
  3481. {
  3482. uint32_t i;
  3483. char reo_error[DP_REO_ERR_LENGTH];
  3484. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3485. uint8_t index = 0;
  3486. DP_PRINT_STATS("SOC Rx Stats:\n");
  3487. DP_PRINT_STATS("Errors:\n");
  3488. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3489. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3490. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3491. DP_PRINT_STATS("Invalid RBM = %d",
  3492. soc->stats.rx.err.invalid_rbm);
  3493. DP_PRINT_STATS("Invalid Vdev = %d",
  3494. soc->stats.rx.err.invalid_vdev);
  3495. DP_PRINT_STATS("Invalid Pdev = %d",
  3496. soc->stats.rx.err.invalid_pdev);
  3497. DP_PRINT_STATS("Invalid Peer = %d",
  3498. soc->stats.rx.err.rx_invalid_peer.num);
  3499. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3500. soc->stats.rx.err.hal_ring_access_fail);
  3501. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3502. index += qdf_snprint(&rxdma_error[index],
  3503. DP_RXDMA_ERR_LENGTH - index,
  3504. " %d", soc->stats.rx.err.rxdma_error[i]);
  3505. }
  3506. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3507. rxdma_error);
  3508. index = 0;
  3509. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3510. index += qdf_snprint(&reo_error[index],
  3511. DP_REO_ERR_LENGTH - index,
  3512. " %d", soc->stats.rx.err.reo_error[i]);
  3513. }
  3514. DP_PRINT_STATS("REO Error(0-14):%s",
  3515. reo_error);
  3516. }
  3517. /**
  3518. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3519. * @vdev: DP_VDEV handle
  3520. *
  3521. * Return:void
  3522. */
  3523. static inline void
  3524. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3525. {
  3526. struct dp_peer *peer = NULL;
  3527. DP_STATS_CLR(vdev->pdev);
  3528. DP_STATS_CLR(vdev->pdev->soc);
  3529. DP_STATS_CLR(vdev);
  3530. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3531. if (!peer)
  3532. return;
  3533. DP_STATS_CLR(peer);
  3534. }
  3535. }
  3536. /**
  3537. * dp_print_rx_rates(): Print Rx rate stats
  3538. * @vdev: DP_VDEV handle
  3539. *
  3540. * Return:void
  3541. */
  3542. static inline void
  3543. dp_print_rx_rates(struct dp_vdev *vdev)
  3544. {
  3545. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3546. uint8_t i, mcs, pkt_type;
  3547. uint8_t index = 0;
  3548. char nss[DP_NSS_LENGTH];
  3549. DP_PRINT_STATS("Rx Rate Info:\n");
  3550. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3551. index = 0;
  3552. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3553. if (!dp_rate_string[pkt_type][mcs].valid)
  3554. continue;
  3555. DP_PRINT_STATS(" %s = %d",
  3556. dp_rate_string[pkt_type][mcs].mcs_type,
  3557. pdev->stats.rx.pkt_type[pkt_type].
  3558. mcs_count[mcs]);
  3559. }
  3560. DP_PRINT_STATS("\n");
  3561. }
  3562. index = 0;
  3563. for (i = 0; i < SS_COUNT; i++) {
  3564. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3565. " %d", pdev->stats.rx.nss[i]);
  3566. }
  3567. DP_PRINT_STATS("NSS(0-7) = %s",
  3568. nss);
  3569. DP_PRINT_STATS("SGI ="
  3570. " 0.8us %d,"
  3571. " 0.4us %d,"
  3572. " 1.6us %d,"
  3573. " 3.2us %d,",
  3574. pdev->stats.rx.sgi_count[0],
  3575. pdev->stats.rx.sgi_count[1],
  3576. pdev->stats.rx.sgi_count[2],
  3577. pdev->stats.rx.sgi_count[3]);
  3578. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3579. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3580. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3581. DP_PRINT_STATS("Reception Type ="
  3582. " SU: %d,"
  3583. " MU_MIMO:%d,"
  3584. " MU_OFDMA:%d,"
  3585. " MU_OFDMA_MIMO:%d\n",
  3586. pdev->stats.rx.reception_type[0],
  3587. pdev->stats.rx.reception_type[1],
  3588. pdev->stats.rx.reception_type[2],
  3589. pdev->stats.rx.reception_type[3]);
  3590. DP_PRINT_STATS("Aggregation:\n");
  3591. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3592. pdev->stats.rx.ampdu_cnt);
  3593. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3594. pdev->stats.rx.non_ampdu_cnt);
  3595. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3596. pdev->stats.rx.amsdu_cnt);
  3597. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3598. pdev->stats.rx.non_amsdu_cnt);
  3599. }
  3600. /**
  3601. * dp_print_tx_rates(): Print tx rates
  3602. * @vdev: DP_VDEV handle
  3603. *
  3604. * Return:void
  3605. */
  3606. static inline void
  3607. dp_print_tx_rates(struct dp_vdev *vdev)
  3608. {
  3609. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3610. uint8_t mcs, pkt_type;
  3611. uint32_t index;
  3612. DP_PRINT_STATS("Tx Rate Info:\n");
  3613. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3614. index = 0;
  3615. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3616. if (!dp_rate_string[pkt_type][mcs].valid)
  3617. continue;
  3618. DP_PRINT_STATS(" %s = %d",
  3619. dp_rate_string[pkt_type][mcs].mcs_type,
  3620. pdev->stats.tx.pkt_type[pkt_type].
  3621. mcs_count[mcs]);
  3622. }
  3623. DP_PRINT_STATS("\n");
  3624. }
  3625. DP_PRINT_STATS("SGI ="
  3626. " 0.8us %d"
  3627. " 0.4us %d"
  3628. " 1.6us %d"
  3629. " 3.2us %d",
  3630. pdev->stats.tx.sgi_count[0],
  3631. pdev->stats.tx.sgi_count[1],
  3632. pdev->stats.tx.sgi_count[2],
  3633. pdev->stats.tx.sgi_count[3]);
  3634. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3635. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3636. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3637. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3638. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3639. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3640. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3641. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3642. DP_PRINT_STATS("Aggregation:\n");
  3643. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3644. pdev->stats.tx.amsdu_cnt);
  3645. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3646. pdev->stats.tx.non_amsdu_cnt);
  3647. }
  3648. /**
  3649. * dp_print_peer_stats():print peer stats
  3650. * @peer: DP_PEER handle
  3651. *
  3652. * return void
  3653. */
  3654. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3655. {
  3656. uint8_t i, mcs, pkt_type;
  3657. uint32_t index;
  3658. char nss[DP_NSS_LENGTH];
  3659. DP_PRINT_STATS("Node Tx Stats:\n");
  3660. DP_PRINT_STATS("Total Packet Completions = %d",
  3661. peer->stats.tx.comp_pkt.num);
  3662. DP_PRINT_STATS("Total Bytes Completions = %d",
  3663. peer->stats.tx.comp_pkt.bytes);
  3664. DP_PRINT_STATS("Success Packets = %d",
  3665. peer->stats.tx.tx_success.num);
  3666. DP_PRINT_STATS("Success Bytes = %d",
  3667. peer->stats.tx.tx_success.bytes);
  3668. DP_PRINT_STATS("Packets Failed = %d",
  3669. peer->stats.tx.tx_failed);
  3670. DP_PRINT_STATS("Packets In OFDMA = %d",
  3671. peer->stats.tx.ofdma);
  3672. DP_PRINT_STATS("Packets In STBC = %d",
  3673. peer->stats.tx.stbc);
  3674. DP_PRINT_STATS("Packets In LDPC = %d",
  3675. peer->stats.tx.ldpc);
  3676. DP_PRINT_STATS("Packet Retries = %d",
  3677. peer->stats.tx.retries);
  3678. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3679. peer->stats.tx.amsdu_cnt);
  3680. DP_PRINT_STATS("Last Packet RSSI = %d",
  3681. peer->stats.tx.last_ack_rssi);
  3682. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3683. peer->stats.tx.dropped.fw_rem);
  3684. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3685. peer->stats.tx.dropped.fw_rem_tx);
  3686. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3687. peer->stats.tx.dropped.fw_rem_notx);
  3688. DP_PRINT_STATS("Dropped : Age Out = %d",
  3689. peer->stats.tx.dropped.age_out);
  3690. DP_PRINT_STATS("Rate Info:");
  3691. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3692. index = 0;
  3693. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3694. if (!dp_rate_string[pkt_type][mcs].valid)
  3695. continue;
  3696. DP_PRINT_STATS(" %s = %d",
  3697. dp_rate_string[pkt_type][mcs].mcs_type,
  3698. peer->stats.tx.pkt_type[pkt_type].
  3699. mcs_count[mcs]);
  3700. }
  3701. DP_PRINT_STATS("\n");
  3702. }
  3703. DP_PRINT_STATS("SGI = "
  3704. " 0.8us %d"
  3705. " 0.4us %d"
  3706. " 1.6us %d"
  3707. " 3.2us %d",
  3708. peer->stats.tx.sgi_count[0],
  3709. peer->stats.tx.sgi_count[1],
  3710. peer->stats.tx.sgi_count[2],
  3711. peer->stats.tx.sgi_count[3]);
  3712. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3713. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3714. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3715. DP_PRINT_STATS("Aggregation:");
  3716. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3717. peer->stats.tx.amsdu_cnt);
  3718. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3719. peer->stats.tx.non_amsdu_cnt);
  3720. DP_PRINT_STATS("Node Rx Stats:");
  3721. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3722. peer->stats.rx.to_stack.num);
  3723. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3724. peer->stats.rx.to_stack.bytes);
  3725. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3726. DP_PRINT_STATS("Packets Received = %d",
  3727. peer->stats.rx.rcvd_reo[i].num);
  3728. DP_PRINT_STATS("Bytes Received = %d",
  3729. peer->stats.rx.rcvd_reo[i].bytes);
  3730. }
  3731. DP_PRINT_STATS("Multicast Packets Received = %d",
  3732. peer->stats.rx.multicast.num);
  3733. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3734. peer->stats.rx.multicast.bytes);
  3735. DP_PRINT_STATS("WDS Packets Received = %d",
  3736. peer->stats.rx.wds.num);
  3737. DP_PRINT_STATS("WDS Bytes Received = %d",
  3738. peer->stats.rx.wds.bytes);
  3739. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3740. peer->stats.rx.intra_bss.pkts.num);
  3741. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3742. peer->stats.rx.intra_bss.pkts.bytes);
  3743. DP_PRINT_STATS("Raw Packets Received = %d",
  3744. peer->stats.rx.raw.num);
  3745. DP_PRINT_STATS("Raw Bytes Received = %d",
  3746. peer->stats.rx.raw.bytes);
  3747. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3748. peer->stats.rx.err.mic_err);
  3749. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3750. peer->stats.rx.err.decrypt_err);
  3751. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3752. peer->stats.rx.non_ampdu_cnt);
  3753. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3754. peer->stats.rx.ampdu_cnt);
  3755. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3756. peer->stats.rx.non_amsdu_cnt);
  3757. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3758. peer->stats.rx.amsdu_cnt);
  3759. DP_PRINT_STATS("SGI ="
  3760. " 0.8us %d"
  3761. " 0.4us %d"
  3762. " 1.6us %d"
  3763. " 3.2us %d",
  3764. peer->stats.rx.sgi_count[0],
  3765. peer->stats.rx.sgi_count[1],
  3766. peer->stats.rx.sgi_count[2],
  3767. peer->stats.rx.sgi_count[3]);
  3768. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3769. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3770. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3771. DP_PRINT_STATS("Reception Type ="
  3772. " SU %d,"
  3773. " MU_MIMO %d,"
  3774. " MU_OFDMA %d,"
  3775. " MU_OFDMA_MIMO %d",
  3776. peer->stats.rx.reception_type[0],
  3777. peer->stats.rx.reception_type[1],
  3778. peer->stats.rx.reception_type[2],
  3779. peer->stats.rx.reception_type[3]);
  3780. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3781. index = 0;
  3782. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3783. if (!dp_rate_string[pkt_type][mcs].valid)
  3784. continue;
  3785. DP_PRINT_STATS(" %s = %d",
  3786. dp_rate_string[pkt_type][mcs].mcs_type,
  3787. peer->stats.rx.pkt_type[pkt_type].
  3788. mcs_count[mcs]);
  3789. }
  3790. DP_PRINT_STATS("\n");
  3791. }
  3792. index = 0;
  3793. for (i = 0; i < SS_COUNT; i++) {
  3794. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3795. " %d", peer->stats.rx.nss[i]);
  3796. }
  3797. DP_PRINT_STATS("NSS(0-7) = %s",
  3798. nss);
  3799. DP_PRINT_STATS("Aggregation:");
  3800. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3801. peer->stats.rx.ampdu_cnt);
  3802. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3803. peer->stats.rx.non_ampdu_cnt);
  3804. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3805. peer->stats.rx.amsdu_cnt);
  3806. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3807. peer->stats.rx.non_amsdu_cnt);
  3808. }
  3809. /**
  3810. * dp_print_host_stats()- Function to print the stats aggregated at host
  3811. * @vdev_handle: DP_VDEV handle
  3812. * @type: host stats type
  3813. *
  3814. * Available Stat types
  3815. * TXRX_CLEAR_STATS : Clear the stats
  3816. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3817. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3818. * TXRX_TX_HOST_STATS: Print Tx Stats
  3819. * TXRX_RX_HOST_STATS: Print Rx Stats
  3820. * TXRX_AST_STATS: Print AST Stats
  3821. *
  3822. * Return: 0 on success, print error message in case of failure
  3823. */
  3824. static int
  3825. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3826. {
  3827. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3828. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3829. dp_aggregate_pdev_stats(pdev);
  3830. switch (type) {
  3831. case TXRX_CLEAR_STATS:
  3832. dp_txrx_host_stats_clr(vdev);
  3833. break;
  3834. case TXRX_RX_RATE_STATS:
  3835. dp_print_rx_rates(vdev);
  3836. break;
  3837. case TXRX_TX_RATE_STATS:
  3838. dp_print_tx_rates(vdev);
  3839. break;
  3840. case TXRX_TX_HOST_STATS:
  3841. dp_print_pdev_tx_stats(pdev);
  3842. dp_print_soc_tx_stats(pdev->soc);
  3843. break;
  3844. case TXRX_RX_HOST_STATS:
  3845. dp_print_pdev_rx_stats(pdev);
  3846. dp_print_soc_rx_stats(pdev->soc);
  3847. break;
  3848. case TXRX_AST_STATS:
  3849. dp_print_ast_stats(pdev->soc);
  3850. break;
  3851. default:
  3852. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3853. break;
  3854. }
  3855. return 0;
  3856. }
  3857. /*
  3858. * dp_get_host_peer_stats()- function to print peer stats
  3859. * @pdev_handle: DP_PDEV handle
  3860. * @mac_addr: mac address of the peer
  3861. *
  3862. * Return: void
  3863. */
  3864. static void
  3865. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3866. {
  3867. struct dp_peer *peer;
  3868. uint8_t local_id;
  3869. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3870. &local_id);
  3871. if (!peer) {
  3872. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3873. "%s: Invalid peer\n", __func__);
  3874. return;
  3875. }
  3876. dp_print_peer_stats(peer);
  3877. dp_peer_rxtid_stats(peer);
  3878. return;
  3879. }
  3880. /*
  3881. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  3882. * @pdev: DP_PDEV handle
  3883. *
  3884. * Return: void
  3885. */
  3886. static void
  3887. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  3888. {
  3889. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  3890. htt_tlv_filter.mpdu_start = 0;
  3891. htt_tlv_filter.msdu_start = 0;
  3892. htt_tlv_filter.packet = 0;
  3893. htt_tlv_filter.msdu_end = 0;
  3894. htt_tlv_filter.mpdu_end = 0;
  3895. htt_tlv_filter.packet_header = 1;
  3896. htt_tlv_filter.attention = 1;
  3897. htt_tlv_filter.ppdu_start = 1;
  3898. htt_tlv_filter.ppdu_end = 1;
  3899. htt_tlv_filter.ppdu_end_user_stats = 1;
  3900. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3901. htt_tlv_filter.ppdu_end_status_done = 1;
  3902. htt_tlv_filter.enable_fp = 1;
  3903. htt_tlv_filter.enable_md = 0;
  3904. htt_tlv_filter.enable_mo = 0;
  3905. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  3906. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3907. RX_BUFFER_SIZE, &htt_tlv_filter);
  3908. }
  3909. /*
  3910. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3911. * @pdev_handle: DP_PDEV handle
  3912. *
  3913. * Return: void
  3914. */
  3915. static void
  3916. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3917. {
  3918. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3919. pdev->enhanced_stats_en = 1;
  3920. dp_ppdu_ring_cfg(pdev);
  3921. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  3922. }
  3923. /*
  3924. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3925. * @pdev_handle: DP_PDEV handle
  3926. *
  3927. * Return: void
  3928. */
  3929. static void
  3930. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3931. {
  3932. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3933. pdev->enhanced_stats_en = 0;
  3934. }
  3935. /*
  3936. * dp_get_fw_peer_stats()- function to print peer stats
  3937. * @pdev_handle: DP_PDEV handle
  3938. * @mac_addr: mac address of the peer
  3939. * @cap: Type of htt stats requested
  3940. *
  3941. * Currently Supporting only MAC ID based requests Only
  3942. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3943. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3944. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3945. *
  3946. * Return: void
  3947. */
  3948. static void
  3949. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3950. uint32_t cap)
  3951. {
  3952. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3953. uint32_t config_param0 = 0;
  3954. uint32_t config_param1 = 0;
  3955. uint32_t config_param2 = 0;
  3956. uint32_t config_param3 = 0;
  3957. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3958. config_param0 |= (1 << (cap + 1));
  3959. config_param1 = 0x8f;
  3960. config_param2 |= (mac_addr[0] & 0x000000ff);
  3961. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3962. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3963. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3964. config_param3 |= (mac_addr[4] & 0x000000ff);
  3965. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3966. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3967. config_param0, config_param1, config_param2,
  3968. config_param3);
  3969. }
  3970. /*
  3971. * dp_set_vdev_param: function to set parameters in vdev
  3972. * @param: parameter type to be set
  3973. * @val: value of parameter to be set
  3974. *
  3975. * return: void
  3976. */
  3977. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3978. enum cdp_vdev_param_type param, uint32_t val)
  3979. {
  3980. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3981. switch (param) {
  3982. case CDP_ENABLE_WDS:
  3983. vdev->wds_enabled = val;
  3984. break;
  3985. case CDP_ENABLE_NAWDS:
  3986. vdev->nawds_enabled = val;
  3987. break;
  3988. case CDP_ENABLE_MCAST_EN:
  3989. vdev->mcast_enhancement_en = val;
  3990. break;
  3991. case CDP_ENABLE_PROXYSTA:
  3992. vdev->proxysta_vdev = val;
  3993. break;
  3994. case CDP_UPDATE_TDLS_FLAGS:
  3995. vdev->tdls_link_connected = val;
  3996. break;
  3997. case CDP_CFG_WDS_AGING_TIMER:
  3998. if (val == 0)
  3999. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4000. else if (val != vdev->wds_aging_timer_val)
  4001. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4002. vdev->wds_aging_timer_val = val;
  4003. break;
  4004. case CDP_ENABLE_AP_BRIDGE:
  4005. if (wlan_op_mode_sta != vdev->opmode)
  4006. vdev->ap_bridge_enabled = val;
  4007. else
  4008. vdev->ap_bridge_enabled = false;
  4009. break;
  4010. default:
  4011. break;
  4012. }
  4013. dp_tx_vdev_update_search_flags(vdev);
  4014. }
  4015. /**
  4016. * dp_peer_set_nawds: set nawds bit in peer
  4017. * @peer_handle: pointer to peer
  4018. * @value: enable/disable nawds
  4019. *
  4020. * return: void
  4021. */
  4022. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4023. {
  4024. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4025. peer->nawds_enabled = value;
  4026. }
  4027. /*
  4028. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4029. * @vdev_handle: DP_VDEV handle
  4030. * @map_id:ID of map that needs to be updated
  4031. *
  4032. * Return: void
  4033. */
  4034. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4035. uint8_t map_id)
  4036. {
  4037. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4038. vdev->dscp_tid_map_id = map_id;
  4039. return;
  4040. }
  4041. /**
  4042. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4043. * @pdev: DP_PDEV handle
  4044. * @map_id: ID of map that needs to be updated
  4045. * @tos: index value in map
  4046. * @tid: tid value passed by the user
  4047. *
  4048. * Return: void
  4049. */
  4050. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4051. uint8_t map_id, uint8_t tos, uint8_t tid)
  4052. {
  4053. uint8_t dscp;
  4054. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4055. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4056. pdev->dscp_tid_map[map_id][dscp] = tid;
  4057. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4058. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4059. map_id, dscp);
  4060. return;
  4061. }
  4062. /**
  4063. * dp_fw_stats_process(): Process TxRX FW stats request
  4064. * @vdev_handle: DP VDEV handle
  4065. * @val: value passed by user
  4066. *
  4067. * return: int
  4068. */
  4069. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4070. {
  4071. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4072. struct dp_pdev *pdev = NULL;
  4073. if (!vdev) {
  4074. DP_TRACE(NONE, "VDEV not found");
  4075. return 1;
  4076. }
  4077. pdev = vdev->pdev;
  4078. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4079. }
  4080. /*
  4081. * dp_txrx_stats() - function to map to firmware and host stats
  4082. * @vdev: virtual handle
  4083. * @stats: type of statistics requested
  4084. *
  4085. * Return: integer
  4086. */
  4087. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4088. {
  4089. int host_stats;
  4090. int fw_stats;
  4091. if (stats >= CDP_TXRX_MAX_STATS)
  4092. return 0;
  4093. /*
  4094. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4095. * has to be updated if new FW HTT stats added
  4096. */
  4097. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4098. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4099. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4100. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4101. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4102. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4103. stats, fw_stats, host_stats);
  4104. if (fw_stats != TXRX_FW_STATS_INVALID)
  4105. return dp_fw_stats_process(vdev, fw_stats);
  4106. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4107. (host_stats <= TXRX_HOST_STATS_MAX))
  4108. return dp_print_host_stats(vdev, host_stats);
  4109. else
  4110. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4111. "Wrong Input for TxRx Stats");
  4112. return 0;
  4113. }
  4114. /*
  4115. * dp_print_napi_stats(): NAPI stats
  4116. * @soc - soc handle
  4117. */
  4118. static void dp_print_napi_stats(struct dp_soc *soc)
  4119. {
  4120. hif_print_napi_stats(soc->hif_handle);
  4121. }
  4122. /*
  4123. * dp_print_per_ring_stats(): Packet count per ring
  4124. * @soc - soc handle
  4125. */
  4126. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4127. {
  4128. uint8_t core, ring;
  4129. uint64_t total_packets;
  4130. DP_TRACE(FATAL, "Reo packets per ring:");
  4131. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4132. total_packets = 0;
  4133. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4134. for (core = 0; core < NR_CPUS; core++) {
  4135. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4136. core, soc->stats.rx.ring_packets[core][ring]);
  4137. total_packets += soc->stats.rx.ring_packets[core][ring];
  4138. }
  4139. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4140. ring, total_packets);
  4141. }
  4142. }
  4143. /*
  4144. * dp_txrx_path_stats() - Function to display dump stats
  4145. * @soc - soc handle
  4146. *
  4147. * return: none
  4148. */
  4149. static void dp_txrx_path_stats(struct dp_soc *soc)
  4150. {
  4151. uint8_t error_code;
  4152. uint8_t loop_pdev;
  4153. struct dp_pdev *pdev;
  4154. uint8_t i;
  4155. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4156. pdev = soc->pdev_list[loop_pdev];
  4157. dp_aggregate_pdev_stats(pdev);
  4158. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4159. "Tx path Statistics:");
  4160. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4161. pdev->stats.tx_i.rcvd.num,
  4162. pdev->stats.tx_i.rcvd.bytes);
  4163. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4164. pdev->stats.tx_i.processed.num,
  4165. pdev->stats.tx_i.processed.bytes);
  4166. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4167. pdev->stats.tx.tx_success.num,
  4168. pdev->stats.tx.tx_success.bytes);
  4169. DP_TRACE(FATAL, "Dropped in host:");
  4170. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4171. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4172. DP_TRACE(FATAL, "Descriptor not available: %u",
  4173. pdev->stats.tx_i.dropped.desc_na);
  4174. DP_TRACE(FATAL, "Ring full: %u",
  4175. pdev->stats.tx_i.dropped.ring_full);
  4176. DP_TRACE(FATAL, "Enqueue fail: %u",
  4177. pdev->stats.tx_i.dropped.enqueue_fail);
  4178. DP_TRACE(FATAL, "DMA Error: %u",
  4179. pdev->stats.tx_i.dropped.dma_error);
  4180. DP_TRACE(FATAL, "Dropped in hardware:");
  4181. DP_TRACE(FATAL, "total packets dropped: %u",
  4182. pdev->stats.tx.tx_failed);
  4183. DP_TRACE(FATAL, "mpdu age out: %u",
  4184. pdev->stats.tx.dropped.age_out);
  4185. DP_TRACE(FATAL, "firmware removed: %u",
  4186. pdev->stats.tx.dropped.fw_rem);
  4187. DP_TRACE(FATAL, "firmware removed tx: %u",
  4188. pdev->stats.tx.dropped.fw_rem_tx);
  4189. DP_TRACE(FATAL, "firmware removed notx %u",
  4190. pdev->stats.tx.dropped.fw_rem_notx);
  4191. DP_TRACE(FATAL, "peer_invalid: %u",
  4192. pdev->soc->stats.tx.tx_invalid_peer.num);
  4193. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4194. DP_TRACE(FATAL, "Single Packet: %u",
  4195. pdev->stats.tx_comp_histogram.pkts_1);
  4196. DP_TRACE(FATAL, "2-20 Packets: %u",
  4197. pdev->stats.tx_comp_histogram.pkts_2_20);
  4198. DP_TRACE(FATAL, "21-40 Packets: %u",
  4199. pdev->stats.tx_comp_histogram.pkts_21_40);
  4200. DP_TRACE(FATAL, "41-60 Packets: %u",
  4201. pdev->stats.tx_comp_histogram.pkts_41_60);
  4202. DP_TRACE(FATAL, "61-80 Packets: %u",
  4203. pdev->stats.tx_comp_histogram.pkts_61_80);
  4204. DP_TRACE(FATAL, "81-100 Packets: %u",
  4205. pdev->stats.tx_comp_histogram.pkts_81_100);
  4206. DP_TRACE(FATAL, "101-200 Packets: %u",
  4207. pdev->stats.tx_comp_histogram.pkts_101_200);
  4208. DP_TRACE(FATAL, " 201+ Packets: %u",
  4209. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4210. DP_TRACE(FATAL, "Rx path statistics");
  4211. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4212. pdev->stats.rx.to_stack.num,
  4213. pdev->stats.rx.to_stack.bytes);
  4214. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4215. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4216. i, pdev->stats.rx.rcvd_reo[i].num,
  4217. pdev->stats.rx.rcvd_reo[i].bytes);
  4218. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4219. pdev->stats.rx.intra_bss.pkts.num,
  4220. pdev->stats.rx.intra_bss.pkts.bytes);
  4221. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4222. pdev->stats.rx.raw.num,
  4223. pdev->stats.rx.raw.bytes);
  4224. DP_TRACE(FATAL, "dropped: error %u msdus",
  4225. pdev->stats.rx.err.mic_err);
  4226. DP_TRACE(FATAL, "peer invalid %u",
  4227. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4228. DP_TRACE(FATAL, "Reo Statistics");
  4229. DP_TRACE(FATAL, "rbm error: %u msdus",
  4230. pdev->soc->stats.rx.err.invalid_rbm);
  4231. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4232. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4233. DP_TRACE(FATAL, "Reo errors");
  4234. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4235. error_code++) {
  4236. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4237. error_code,
  4238. pdev->soc->stats.rx.err.reo_error[error_code]);
  4239. }
  4240. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4241. error_code++) {
  4242. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4243. error_code,
  4244. pdev->soc->stats.rx.err
  4245. .rxdma_error[error_code]);
  4246. }
  4247. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4248. DP_TRACE(FATAL, "Single Packet: %u",
  4249. pdev->stats.rx_ind_histogram.pkts_1);
  4250. DP_TRACE(FATAL, "2-20 Packets: %u",
  4251. pdev->stats.rx_ind_histogram.pkts_2_20);
  4252. DP_TRACE(FATAL, "21-40 Packets: %u",
  4253. pdev->stats.rx_ind_histogram.pkts_21_40);
  4254. DP_TRACE(FATAL, "41-60 Packets: %u",
  4255. pdev->stats.rx_ind_histogram.pkts_41_60);
  4256. DP_TRACE(FATAL, "61-80 Packets: %u",
  4257. pdev->stats.rx_ind_histogram.pkts_61_80);
  4258. DP_TRACE(FATAL, "81-100 Packets: %u",
  4259. pdev->stats.rx_ind_histogram.pkts_81_100);
  4260. DP_TRACE(FATAL, "101-200 Packets: %u",
  4261. pdev->stats.rx_ind_histogram.pkts_101_200);
  4262. DP_TRACE(FATAL, " 201+ Packets: %u",
  4263. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4264. }
  4265. }
  4266. /*
  4267. * dp_txrx_dump_stats() - Dump statistics
  4268. * @value - Statistics option
  4269. */
  4270. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4271. {
  4272. struct dp_soc *soc =
  4273. (struct dp_soc *)psoc;
  4274. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4275. if (!soc) {
  4276. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4277. "%s: soc is NULL", __func__);
  4278. return QDF_STATUS_E_INVAL;
  4279. }
  4280. switch (value) {
  4281. case CDP_TXRX_PATH_STATS:
  4282. dp_txrx_path_stats(soc);
  4283. break;
  4284. case CDP_RX_RING_STATS:
  4285. dp_print_per_ring_stats(soc);
  4286. break;
  4287. case CDP_TXRX_TSO_STATS:
  4288. /* TODO: NOT IMPLEMENTED */
  4289. break;
  4290. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4291. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4292. break;
  4293. case CDP_DP_NAPI_STATS:
  4294. dp_print_napi_stats(soc);
  4295. break;
  4296. case CDP_TXRX_DESC_STATS:
  4297. /* TODO: NOT IMPLEMENTED */
  4298. break;
  4299. default:
  4300. status = QDF_STATUS_E_INVAL;
  4301. break;
  4302. }
  4303. return status;
  4304. }
  4305. static struct cdp_wds_ops dp_ops_wds = {
  4306. .vdev_set_wds = dp_vdev_set_wds,
  4307. };
  4308. /*
  4309. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4310. * @soc - datapath soc handle
  4311. * @peer - datapath peer handle
  4312. *
  4313. * Delete the AST entries belonging to a peer
  4314. */
  4315. #ifdef FEATURE_WDS
  4316. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4317. struct dp_peer *peer)
  4318. {
  4319. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4320. qdf_spin_lock_bh(&soc->ast_lock);
  4321. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4322. if (ast_entry->next_hop) {
  4323. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4324. peer->vdev->pdev->osif_pdev,
  4325. ast_entry->mac_addr.raw);
  4326. }
  4327. dp_peer_del_ast(soc, ast_entry);
  4328. }
  4329. qdf_spin_unlock_bh(&soc->ast_lock);
  4330. }
  4331. #else
  4332. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4333. struct dp_peer *peer)
  4334. {
  4335. }
  4336. #endif
  4337. #ifdef CONFIG_WIN
  4338. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4339. {
  4340. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4341. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4342. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4343. dp_peer_delete_ast_entries(soc, peer);
  4344. }
  4345. #endif
  4346. static struct cdp_cmn_ops dp_ops_cmn = {
  4347. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4348. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4349. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4350. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4351. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4352. .txrx_peer_create = dp_peer_create_wifi3,
  4353. .txrx_peer_setup = dp_peer_setup_wifi3,
  4354. #ifdef CONFIG_WIN
  4355. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4356. #else
  4357. .txrx_peer_teardown = NULL,
  4358. #endif
  4359. .txrx_peer_delete = dp_peer_delete_wifi3,
  4360. .txrx_vdev_register = dp_vdev_register_wifi3,
  4361. .txrx_soc_detach = dp_soc_detach_wifi3,
  4362. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4363. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4364. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4365. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4366. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4367. .delba_process = dp_delba_process_wifi3,
  4368. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4369. .flush_cache_rx_queue = NULL,
  4370. /* TODO: get API's for dscp-tid need to be added*/
  4371. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4372. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4373. .txrx_stats = dp_txrx_stats,
  4374. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4375. .display_stats = dp_txrx_dump_stats,
  4376. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4377. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4378. #ifdef DP_INTR_POLL_BASED
  4379. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4380. #else
  4381. .txrx_intr_attach = dp_soc_interrupt_attach,
  4382. #endif
  4383. .txrx_intr_detach = dp_soc_interrupt_detach,
  4384. .set_pn_check = dp_set_pn_check_wifi3,
  4385. /* TODO: Add other functions */
  4386. };
  4387. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4388. .txrx_peer_authorize = dp_peer_authorize,
  4389. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4390. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4391. #ifdef MESH_MODE_SUPPORT
  4392. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4393. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4394. #endif
  4395. .txrx_set_vdev_param = dp_set_vdev_param,
  4396. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4397. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4398. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4399. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4400. .txrx_update_filter_neighbour_peers =
  4401. dp_update_filter_neighbour_peers,
  4402. .txrx_get_sec_type = dp_get_sec_type,
  4403. /* TODO: Add other functions */
  4404. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4405. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4406. };
  4407. static struct cdp_me_ops dp_ops_me = {
  4408. #ifdef ATH_SUPPORT_IQUE
  4409. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4410. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4411. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4412. #endif
  4413. };
  4414. static struct cdp_mon_ops dp_ops_mon = {
  4415. .txrx_monitor_set_filter_ucast_data = NULL,
  4416. .txrx_monitor_set_filter_mcast_data = NULL,
  4417. .txrx_monitor_set_filter_non_data = NULL,
  4418. .txrx_monitor_get_filter_ucast_data = NULL,
  4419. .txrx_monitor_get_filter_mcast_data = NULL,
  4420. .txrx_monitor_get_filter_non_data = NULL,
  4421. .txrx_reset_monitor_mode = NULL,
  4422. };
  4423. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4424. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4425. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4426. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4427. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4428. /* TODO */
  4429. };
  4430. static struct cdp_raw_ops dp_ops_raw = {
  4431. /* TODO */
  4432. };
  4433. #ifdef CONFIG_WIN
  4434. static struct cdp_pflow_ops dp_ops_pflow = {
  4435. /* TODO */
  4436. };
  4437. #endif /* CONFIG_WIN */
  4438. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4439. {
  4440. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4441. struct dp_soc *soc = pdev->soc;
  4442. if (soc->intr_mode == DP_INTR_POLL)
  4443. qdf_timer_stop(&soc->int_timer);
  4444. return QDF_STATUS_SUCCESS;
  4445. }
  4446. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4447. {
  4448. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4449. struct dp_soc *soc = pdev->soc;
  4450. if (soc->intr_mode == DP_INTR_POLL)
  4451. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4452. return QDF_STATUS_SUCCESS;
  4453. }
  4454. #ifndef CONFIG_WIN
  4455. static struct cdp_misc_ops dp_ops_misc = {
  4456. .get_opmode = dp_get_opmode,
  4457. #ifdef FEATURE_RUNTIME_PM
  4458. .runtime_suspend = dp_bus_suspend,
  4459. .runtime_resume = dp_bus_resume,
  4460. #endif
  4461. };
  4462. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4463. /* WIFI 3.0 DP implement as required. */
  4464. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4465. .register_pause_cb = dp_txrx_register_pause_cb,
  4466. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4467. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4468. };
  4469. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4470. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4471. };
  4472. #ifdef IPA_OFFLOAD
  4473. static struct cdp_ipa_ops dp_ops_ipa = {
  4474. .ipa_get_resource = dp_ipa_get_resource,
  4475. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4476. .ipa_op_response = dp_ipa_op_response,
  4477. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4478. .ipa_get_stat = dp_ipa_get_stat,
  4479. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4480. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4481. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4482. .ipa_setup = dp_ipa_setup,
  4483. .ipa_cleanup = dp_ipa_cleanup,
  4484. .ipa_setup_iface = dp_ipa_setup_iface,
  4485. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4486. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4487. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4488. .ipa_set_perf_level = dp_ipa_set_perf_level
  4489. };
  4490. #endif
  4491. static struct cdp_bus_ops dp_ops_bus = {
  4492. .bus_suspend = dp_bus_suspend,
  4493. .bus_resume = dp_bus_resume
  4494. };
  4495. static struct cdp_ocb_ops dp_ops_ocb = {
  4496. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4497. };
  4498. static struct cdp_throttle_ops dp_ops_throttle = {
  4499. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4500. };
  4501. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4502. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4503. };
  4504. static struct cdp_cfg_ops dp_ops_cfg = {
  4505. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4506. };
  4507. static struct cdp_peer_ops dp_ops_peer = {
  4508. .register_peer = dp_register_peer,
  4509. .clear_peer = dp_clear_peer,
  4510. .find_peer_by_addr = dp_find_peer_by_addr,
  4511. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4512. .local_peer_id = dp_local_peer_id,
  4513. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4514. .peer_state_update = dp_peer_state_update,
  4515. .get_vdevid = dp_get_vdevid,
  4516. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4517. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4518. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4519. .get_peer_state = dp_get_peer_state,
  4520. .last_assoc_received = dp_get_last_assoc_received,
  4521. .last_disassoc_received = dp_get_last_disassoc_received,
  4522. .last_deauth_received = dp_get_last_deauth_received,
  4523. };
  4524. #endif
  4525. static struct cdp_ops dp_txrx_ops = {
  4526. .cmn_drv_ops = &dp_ops_cmn,
  4527. .ctrl_ops = &dp_ops_ctrl,
  4528. .me_ops = &dp_ops_me,
  4529. .mon_ops = &dp_ops_mon,
  4530. .host_stats_ops = &dp_ops_host_stats,
  4531. .wds_ops = &dp_ops_wds,
  4532. .raw_ops = &dp_ops_raw,
  4533. #ifdef CONFIG_WIN
  4534. .pflow_ops = &dp_ops_pflow,
  4535. #endif /* CONFIG_WIN */
  4536. #ifndef CONFIG_WIN
  4537. .misc_ops = &dp_ops_misc,
  4538. .cfg_ops = &dp_ops_cfg,
  4539. .flowctl_ops = &dp_ops_flowctl,
  4540. .l_flowctl_ops = &dp_ops_l_flowctl,
  4541. #ifdef IPA_OFFLOAD
  4542. .ipa_ops = &dp_ops_ipa,
  4543. #endif
  4544. .bus_ops = &dp_ops_bus,
  4545. .ocb_ops = &dp_ops_ocb,
  4546. .peer_ops = &dp_ops_peer,
  4547. .throttle_ops = &dp_ops_throttle,
  4548. .mob_stats_ops = &dp_ops_mob_stats,
  4549. #endif
  4550. };
  4551. /*
  4552. * dp_soc_set_txrx_ring_map()
  4553. * @dp_soc: DP handler for soc
  4554. *
  4555. * Return: Void
  4556. */
  4557. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4558. {
  4559. uint32_t i;
  4560. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4561. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4562. }
  4563. }
  4564. /*
  4565. * dp_soc_attach_wifi3() - Attach txrx SOC
  4566. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4567. * @htc_handle: Opaque HTC handle
  4568. * @hif_handle: Opaque HIF handle
  4569. * @qdf_osdev: QDF device
  4570. *
  4571. * Return: DP SOC handle on success, NULL on failure
  4572. */
  4573. /*
  4574. * Local prototype added to temporarily address warning caused by
  4575. * -Wmissing-prototypes. A more correct solution, namely to expose
  4576. * a prototype in an appropriate header file, will come later.
  4577. */
  4578. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4579. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4580. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4581. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4582. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4583. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4584. {
  4585. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4586. if (!soc) {
  4587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4588. FL("DP SOC memory allocation failed"));
  4589. goto fail0;
  4590. }
  4591. soc->cdp_soc.ops = &dp_txrx_ops;
  4592. soc->cdp_soc.ol_ops = ol_ops;
  4593. soc->osif_soc = osif_soc;
  4594. soc->osdev = qdf_osdev;
  4595. soc->hif_handle = hif_handle;
  4596. soc->psoc = psoc;
  4597. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4598. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4599. soc->hal_soc, qdf_osdev);
  4600. if (!soc->htt_handle) {
  4601. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4602. FL("HTT attach failed"));
  4603. goto fail1;
  4604. }
  4605. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4606. if (!soc->wlan_cfg_ctx) {
  4607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4608. FL("wlan_cfg_soc_attach failed"));
  4609. goto fail2;
  4610. }
  4611. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4612. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4613. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4614. CDP_CFG_MAX_PEER_ID);
  4615. if (ret != -EINVAL) {
  4616. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4617. }
  4618. }
  4619. qdf_spinlock_create(&soc->peer_ref_mutex);
  4620. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4621. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4622. /* fill the tx/rx cpu ring map*/
  4623. dp_soc_set_txrx_ring_map(soc);
  4624. qdf_spinlock_create(&soc->htt_stats.lock);
  4625. /* initialize work queue for stats processing */
  4626. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4627. return (void *)soc;
  4628. fail2:
  4629. htt_soc_detach(soc->htt_handle);
  4630. fail1:
  4631. qdf_mem_free(soc);
  4632. fail0:
  4633. return NULL;
  4634. }
  4635. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4636. /*
  4637. * dp_set_pktlog_wifi3() - attach txrx vdev
  4638. * @pdev: Datapath PDEV handle
  4639. * @event: which event's notifications are being subscribed to
  4640. * @enable: WDI event subscribe or not. (True or False)
  4641. *
  4642. * Return: Success, NULL on failure
  4643. */
  4644. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4645. bool enable)
  4646. {
  4647. struct dp_soc *soc = pdev->soc;
  4648. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4649. if (enable) {
  4650. switch (event) {
  4651. case WDI_EVENT_RX_DESC:
  4652. if (pdev->monitor_vdev) {
  4653. /* Nothing needs to be done if monitor mode is
  4654. * enabled
  4655. */
  4656. return 0;
  4657. }
  4658. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4659. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4660. htt_tlv_filter.mpdu_start = 1;
  4661. htt_tlv_filter.msdu_start = 1;
  4662. htt_tlv_filter.msdu_end = 1;
  4663. htt_tlv_filter.mpdu_end = 1;
  4664. htt_tlv_filter.packet_header = 1;
  4665. htt_tlv_filter.attention = 1;
  4666. htt_tlv_filter.ppdu_start = 1;
  4667. htt_tlv_filter.ppdu_end = 1;
  4668. htt_tlv_filter.ppdu_end_user_stats = 1;
  4669. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4670. htt_tlv_filter.ppdu_end_status_done = 1;
  4671. htt_tlv_filter.enable_fp = 1;
  4672. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4673. pdev->pdev_id,
  4674. pdev->rxdma_mon_status_ring.hal_srng,
  4675. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4676. &htt_tlv_filter);
  4677. }
  4678. break;
  4679. case WDI_EVENT_LITE_RX:
  4680. if (pdev->monitor_vdev) {
  4681. /* Nothing needs to be done if monitor mode is
  4682. * enabled
  4683. */
  4684. return 0;
  4685. }
  4686. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4687. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4688. htt_tlv_filter.ppdu_start = 1;
  4689. htt_tlv_filter.ppdu_end = 1;
  4690. htt_tlv_filter.ppdu_end_user_stats = 1;
  4691. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4692. htt_tlv_filter.ppdu_end_status_done = 1;
  4693. htt_tlv_filter.enable_fp = 1;
  4694. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4695. pdev->pdev_id,
  4696. pdev->rxdma_mon_status_ring.hal_srng,
  4697. RXDMA_MONITOR_STATUS,
  4698. RX_BUFFER_SIZE_PKTLOG_LITE,
  4699. &htt_tlv_filter);
  4700. }
  4701. break;
  4702. case WDI_EVENT_LITE_T2H:
  4703. if (pdev->monitor_vdev) {
  4704. /* Nothing needs to be done if monitor mode is
  4705. * enabled
  4706. */
  4707. return 0;
  4708. }
  4709. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4710. * passing value 0xffff. Once these macros will define in htt
  4711. * header file will use proper macros
  4712. */
  4713. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4714. break;
  4715. default:
  4716. /* Nothing needs to be done for other pktlog types */
  4717. break;
  4718. }
  4719. } else {
  4720. switch (event) {
  4721. case WDI_EVENT_RX_DESC:
  4722. case WDI_EVENT_LITE_RX:
  4723. if (pdev->monitor_vdev) {
  4724. /* Nothing needs to be done if monitor mode is
  4725. * enabled
  4726. */
  4727. return 0;
  4728. }
  4729. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4730. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4731. /* htt_tlv_filter is initialized to 0 */
  4732. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4733. pdev->pdev_id,
  4734. pdev->rxdma_mon_status_ring.hal_srng,
  4735. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4736. &htt_tlv_filter);
  4737. }
  4738. break;
  4739. case WDI_EVENT_LITE_T2H:
  4740. if (pdev->monitor_vdev) {
  4741. /* Nothing needs to be done if monitor mode is
  4742. * enabled
  4743. */
  4744. return 0;
  4745. }
  4746. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4747. * passing value 0. Once these macros will define in htt
  4748. * header file will use proper macros
  4749. */
  4750. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4751. break;
  4752. default:
  4753. /* Nothing needs to be done for other pktlog types */
  4754. break;
  4755. }
  4756. }
  4757. return 0;
  4758. }
  4759. #endif