sde_plane.c 130 KB

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  1. /*
  2. * Copyright (C) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. /**
  59. * enum sde_plane_qos - Different qos configurations for each pipe
  60. *
  61. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  62. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  63. * this configuration is mutually exclusive from VBLANK_CTRL.
  64. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  65. */
  66. enum sde_plane_qos {
  67. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  68. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  69. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  70. };
  71. /*
  72. * struct sde_plane - local sde plane structure
  73. * @aspace: address space pointer
  74. * @csc_cfg: Decoded user configuration for csc
  75. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  76. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  77. * @mplane_list: List of multirect planes of the same pipe
  78. * @catalog: Points to sde catalog structure
  79. * @revalidate: force revalidation of all the plane properties
  80. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  81. * @blob_rot_caps: Pointer to rotator capability blob
  82. */
  83. struct sde_plane {
  84. struct drm_plane base;
  85. struct mutex lock;
  86. enum sde_sspp pipe;
  87. uint32_t features; /* capabilities from catalog */
  88. uint32_t perf_features; /* perf capabilities from catalog */
  89. uint32_t nformats;
  90. uint32_t formats[64];
  91. struct sde_hw_pipe *pipe_hw;
  92. struct sde_hw_pipe_cfg pipe_cfg;
  93. struct sde_hw_sharp_cfg sharp_cfg;
  94. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  95. uint32_t color_fill;
  96. bool is_error;
  97. bool is_rt_pipe;
  98. bool is_virtual;
  99. struct list_head mplane_list;
  100. struct sde_mdss_cfg *catalog;
  101. bool revalidate;
  102. bool xin_halt_forced_clk;
  103. struct sde_csc_cfg csc_cfg;
  104. struct sde_csc_cfg *csc_usr_ptr;
  105. struct sde_csc_cfg *csc_ptr;
  106. const struct sde_sspp_sub_blks *pipe_sblk;
  107. char pipe_name[SDE_NAME_SIZE];
  108. struct msm_property_info property_info;
  109. struct msm_property_data property_data[PLANE_PROP_COUNT];
  110. struct drm_property_blob *blob_info;
  111. struct drm_property_blob *blob_rot_caps;
  112. /* debugfs related stuff */
  113. struct dentry *debugfs_root;
  114. bool debugfs_default_scale;
  115. };
  116. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  117. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  118. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  119. {
  120. struct msm_drm_private *priv;
  121. if (!plane || !plane->dev)
  122. return NULL;
  123. priv = plane->dev->dev_private;
  124. if (!priv)
  125. return NULL;
  126. return to_sde_kms(priv->kms);
  127. }
  128. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  129. {
  130. struct drm_plane_state *pstate = NULL;
  131. struct drm_crtc *drm_crtc = NULL;
  132. struct sde_crtc *sde_crtc = NULL;
  133. struct sde_crtc_mixer *mixer = NULL;
  134. struct sde_hw_ctl *ctl = NULL;
  135. if (!plane) {
  136. DRM_ERROR("Invalid plane %pK\n", plane);
  137. return NULL;
  138. }
  139. pstate = plane->state;
  140. if (!pstate) {
  141. DRM_ERROR("Invalid plane state %pK\n", pstate);
  142. return NULL;
  143. }
  144. drm_crtc = pstate->crtc;
  145. if (!drm_crtc) {
  146. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  147. return NULL;
  148. }
  149. sde_crtc = to_sde_crtc(drm_crtc);
  150. if (!sde_crtc) {
  151. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  152. return NULL;
  153. }
  154. /* it will always return the first mixer and single CTL */
  155. mixer = sde_crtc->mixers;
  156. if (!mixer) {
  157. DRM_ERROR("invalid mixer %pK\n", mixer);
  158. return NULL;
  159. }
  160. ctl = mixer->hw_ctl;
  161. if (!mixer) {
  162. DRM_ERROR("invalid ctl %pK\n", ctl);
  163. return NULL;
  164. }
  165. return ctl;
  166. }
  167. static bool sde_plane_enabled(const struct drm_plane_state *state)
  168. {
  169. return state && state->fb && state->crtc;
  170. }
  171. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  172. {
  173. struct sde_plane *psde;
  174. if (!plane)
  175. return false;
  176. psde = to_sde_plane(plane);
  177. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  178. }
  179. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  180. enum sde_sspp_multirect_index rect_mode, bool enable)
  181. {
  182. struct sde_plane *psde;
  183. if (!plane)
  184. return;
  185. psde = to_sde_plane(plane);
  186. if (psde->pipe_hw->ops.set_src_split_order)
  187. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  188. rect_mode, enable);
  189. }
  190. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  191. {
  192. struct sde_plane *psde;
  193. struct sde_kms *sde_kms;
  194. struct msm_drm_private *priv;
  195. if (!plane || !plane->dev) {
  196. SDE_ERROR("invalid plane %d\n");
  197. return;
  198. }
  199. priv = plane->dev->dev_private;
  200. if (!priv || !priv->kms) {
  201. SDE_ERROR("invalid KMS reference\n");
  202. return;
  203. }
  204. sde_kms = to_sde_kms(priv->kms);
  205. psde = to_sde_plane(plane);
  206. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  207. }
  208. void _sde_plane_set_qos_lut(struct drm_plane *plane,
  209. struct drm_crtc *crtc,
  210. struct drm_framebuffer *fb)
  211. {
  212. struct sde_plane *psde;
  213. const struct sde_format *fmt = NULL;
  214. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  215. struct sde_perf_cfg *perf;
  216. struct sde_plane_state *pstate;
  217. if (!plane || !fb) {
  218. SDE_ERROR("invalid arguments\n");
  219. return;
  220. }
  221. psde = to_sde_plane(plane);
  222. pstate = to_sde_plane_state(plane->state);
  223. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  224. SDE_ERROR("invalid arguments\n");
  225. return;
  226. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  227. return;
  228. }
  229. frame_rate = crtc->mode.vrefresh;
  230. perf = &psde->catalog->perf;
  231. qos_count = perf->qos_refresh_count;
  232. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  233. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  234. (fps_index == qos_count - 1))
  235. break;
  236. fps_index++;
  237. }
  238. if (!psde->is_rt_pipe) {
  239. lut_index = SDE_QOS_LUT_USAGE_NRT;
  240. } else {
  241. fmt = sde_get_sde_format_ext(
  242. fb->format->format,
  243. fb->modifier);
  244. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  245. pstate->scaler3_cfg.enable)
  246. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  247. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  248. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  249. else if (pstate->scaler3_cfg.enable)
  250. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  251. else
  252. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  253. }
  254. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  255. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  256. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  257. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  258. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  259. (fmt) ? fmt->base.pixel_format : 0,
  260. (fmt) ? fmt->fetch_mode : 0,
  261. psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut,
  263. psde->pipe_qos_cfg.creq_lut);
  264. SDE_DEBUG(
  265. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  266. plane->base.id,
  267. psde->pipe - SSPP_VIG0,
  268. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  269. fmt ? fmt->fetch_mode : -1,
  270. psde->pipe_qos_cfg.danger_lut,
  271. psde->pipe_qos_cfg.safe_lut,
  272. psde->pipe_qos_cfg.creq_lut);
  273. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  274. }
  275. /**
  276. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  277. * @plane: Pointer to drm plane
  278. * @enable: true to enable QoS control
  279. * @flags: QoS control mode (enum sde_plane_qos)
  280. */
  281. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  282. bool enable, u32 flags)
  283. {
  284. struct sde_plane *psde;
  285. if (!plane) {
  286. SDE_ERROR("invalid arguments\n");
  287. return;
  288. }
  289. psde = to_sde_plane(plane);
  290. if (!psde->pipe_hw || !psde->pipe_sblk) {
  291. SDE_ERROR("invalid arguments\n");
  292. return;
  293. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  294. return;
  295. }
  296. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  297. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  298. psde->pipe_qos_cfg.danger_vblank =
  299. psde->pipe_sblk->danger_vblank;
  300. psde->pipe_qos_cfg.vblank_en = enable;
  301. }
  302. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  303. /* this feature overrules previous VBLANK_CTRL */
  304. psde->pipe_qos_cfg.vblank_en = false;
  305. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  306. }
  307. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  308. psde->pipe_qos_cfg.danger_safe_en = enable;
  309. if (!psde->is_rt_pipe) {
  310. psde->pipe_qos_cfg.vblank_en = false;
  311. psde->pipe_qos_cfg.danger_safe_en = false;
  312. }
  313. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  314. plane->base.id,
  315. psde->pipe - SSPP_VIG0,
  316. psde->pipe_qos_cfg.danger_safe_en,
  317. psde->pipe_qos_cfg.vblank_en,
  318. psde->pipe_qos_cfg.creq_vblank,
  319. psde->pipe_qos_cfg.danger_vblank,
  320. psde->is_rt_pipe);
  321. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  322. &psde->pipe_qos_cfg);
  323. }
  324. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  325. {
  326. struct sde_plane *psde;
  327. if (!plane)
  328. return;
  329. psde = to_sde_plane(plane);
  330. psde->revalidate = enable;
  331. }
  332. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. int rc;
  336. if (!plane) {
  337. SDE_ERROR("invalid arguments\n");
  338. return -EINVAL;
  339. }
  340. psde = to_sde_plane(plane);
  341. if (!psde->is_rt_pipe)
  342. goto end;
  343. rc = pm_runtime_get_sync(plane->dev->dev);
  344. if (rc < 0) {
  345. SDE_ERROR("failed to enable power resource %d\n", rc);
  346. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  347. return rc;
  348. }
  349. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  350. pm_runtime_put_sync(plane->dev->dev);
  351. end:
  352. return 0;
  353. }
  354. /**
  355. * _sde_plane_set_ot_limit - set OT limit for the given plane
  356. * @plane: Pointer to drm plane
  357. * @crtc: Pointer to drm crtc
  358. */
  359. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  360. struct drm_crtc *crtc)
  361. {
  362. struct sde_plane *psde;
  363. struct sde_vbif_set_ot_params ot_params;
  364. struct msm_drm_private *priv;
  365. struct sde_kms *sde_kms;
  366. if (!plane || !plane->dev || !crtc) {
  367. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  368. !plane, !crtc);
  369. return;
  370. }
  371. priv = plane->dev->dev_private;
  372. if (!priv || !priv->kms) {
  373. SDE_ERROR("invalid KMS reference\n");
  374. return;
  375. }
  376. sde_kms = to_sde_kms(priv->kms);
  377. psde = to_sde_plane(plane);
  378. if (!psde->pipe_hw) {
  379. SDE_ERROR("invalid pipe reference\n");
  380. return;
  381. }
  382. memset(&ot_params, 0, sizeof(ot_params));
  383. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  384. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  385. ot_params.width = psde->pipe_cfg.src_rect.w;
  386. ot_params.height = psde->pipe_cfg.src_rect.h;
  387. ot_params.is_wfd = !psde->is_rt_pipe;
  388. ot_params.frame_rate = crtc->mode.vrefresh;
  389. ot_params.vbif_idx = VBIF_RT;
  390. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  391. ot_params.rd = true;
  392. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  393. }
  394. /**
  395. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  396. * @plane: Pointer to drm plane
  397. */
  398. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  399. {
  400. struct sde_plane *psde;
  401. struct sde_vbif_set_qos_params qos_params;
  402. struct msm_drm_private *priv;
  403. struct sde_kms *sde_kms;
  404. if (!plane || !plane->dev) {
  405. SDE_ERROR("invalid arguments\n");
  406. return;
  407. }
  408. priv = plane->dev->dev_private;
  409. if (!priv || !priv->kms) {
  410. SDE_ERROR("invalid KMS reference\n");
  411. return;
  412. }
  413. sde_kms = to_sde_kms(priv->kms);
  414. psde = to_sde_plane(plane);
  415. if (!psde->pipe_hw) {
  416. SDE_ERROR("invalid pipe reference\n");
  417. return;
  418. }
  419. memset(&qos_params, 0, sizeof(qos_params));
  420. qos_params.vbif_idx = VBIF_RT;
  421. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  422. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  423. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  424. qos_params.client_type = psde->is_rt_pipe ?
  425. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  426. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  427. plane->base.id, qos_params.num,
  428. qos_params.vbif_idx,
  429. qos_params.xin_id, qos_params.client_type,
  430. qos_params.clk_ctrl);
  431. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  432. }
  433. /**
  434. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  435. * @plane: Pointer to drm plane
  436. * @pstate: Pointer to sde plane state
  437. */
  438. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  439. struct sde_plane_state *pstate)
  440. {
  441. struct sde_plane *psde;
  442. struct sde_hw_pipe_ts_cfg cfg;
  443. struct msm_drm_private *priv;
  444. struct sde_kms *sde_kms;
  445. if (!plane || !plane->dev) {
  446. SDE_ERROR("invalid arguments");
  447. return;
  448. }
  449. priv = plane->dev->dev_private;
  450. if (!priv || !priv->kms) {
  451. SDE_ERROR("invalid KMS reference\n");
  452. return;
  453. }
  454. sde_kms = to_sde_kms(priv->kms);
  455. psde = to_sde_plane(plane);
  456. if (!psde->pipe_hw) {
  457. SDE_ERROR("invalid pipe reference\n");
  458. return;
  459. }
  460. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  461. return;
  462. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  463. memset(&cfg, 0, sizeof(cfg));
  464. cfg.size = sde_plane_get_property(pstate,
  465. PLANE_PROP_PREFILL_SIZE);
  466. cfg.time = sde_plane_get_property(pstate,
  467. PLANE_PROP_PREFILL_TIME);
  468. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  469. plane->base.id, cfg.size, cfg.time);
  470. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  471. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  472. pstate->multirect_index);
  473. }
  474. /* helper to update a state's input fence pointer from the property */
  475. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  476. struct sde_plane_state *pstate, uint64_t fd)
  477. {
  478. if (!psde || !pstate) {
  479. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  480. !psde, !pstate);
  481. return;
  482. }
  483. /* clear previous reference */
  484. if (pstate->input_fence)
  485. sde_sync_put(pstate->input_fence);
  486. /* get fence pointer for later */
  487. if (fd == 0)
  488. pstate->input_fence = NULL;
  489. else
  490. pstate->input_fence = sde_sync_get(fd);
  491. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  492. }
  493. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  494. {
  495. struct sde_plane *psde;
  496. struct sde_plane_state *pstate;
  497. uint32_t prefix;
  498. void *input_fence;
  499. int ret = -EINVAL;
  500. signed long rc;
  501. if (!plane) {
  502. SDE_ERROR("invalid plane\n");
  503. } else if (!plane->state) {
  504. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  505. } else {
  506. psde = to_sde_plane(plane);
  507. pstate = to_sde_plane_state(plane->state);
  508. input_fence = pstate->input_fence;
  509. if (input_fence) {
  510. prefix = sde_sync_get_name_prefix(input_fence);
  511. rc = sde_sync_wait(input_fence, wait_ms);
  512. switch (rc) {
  513. case 0:
  514. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  515. wait_ms, prefix, sde_plane_get_property(pstate,
  516. PLANE_PROP_INPUT_FENCE));
  517. psde->is_error = true;
  518. sde_kms_timeline_status(plane->dev);
  519. ret = -ETIMEDOUT;
  520. break;
  521. case -ERESTARTSYS:
  522. SDE_ERROR_PLANE(psde,
  523. "%ums wait interrupted on %08X\n",
  524. wait_ms, prefix);
  525. psde->is_error = true;
  526. ret = -ERESTARTSYS;
  527. break;
  528. case -EINVAL:
  529. SDE_ERROR_PLANE(psde,
  530. "invalid fence param for %08X\n",
  531. prefix);
  532. psde->is_error = true;
  533. ret = -EINVAL;
  534. break;
  535. default:
  536. SDE_DEBUG_PLANE(psde, "signaled\n");
  537. ret = 0;
  538. break;
  539. }
  540. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  541. } else {
  542. ret = 0;
  543. }
  544. }
  545. return ret;
  546. }
  547. /**
  548. * _sde_plane_get_aspace: gets the address space based on the
  549. * fb_translation mode property
  550. */
  551. static int _sde_plane_get_aspace(
  552. struct sde_plane *psde,
  553. struct sde_plane_state *pstate,
  554. struct msm_gem_address_space **aspace)
  555. {
  556. struct sde_kms *kms;
  557. int mode;
  558. if (!psde || !pstate || !aspace) {
  559. SDE_ERROR("invalid parameters\n");
  560. return -EINVAL;
  561. }
  562. kms = _sde_plane_get_kms(&psde->base);
  563. if (!kms) {
  564. SDE_ERROR("invalid kms\n");
  565. return -EINVAL;
  566. }
  567. mode = sde_plane_get_property(pstate,
  568. PLANE_PROP_FB_TRANSLATION_MODE);
  569. switch (mode) {
  570. case SDE_DRM_FB_NON_SEC:
  571. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  572. if (!aspace)
  573. return -EINVAL;
  574. break;
  575. case SDE_DRM_FB_SEC:
  576. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  577. if (!aspace)
  578. return -EINVAL;
  579. break;
  580. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  581. case SDE_DRM_FB_SEC_DIR_TRANS:
  582. *aspace = NULL;
  583. break;
  584. default:
  585. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  586. return -EFAULT;
  587. }
  588. return 0;
  589. }
  590. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  591. struct sde_plane_state *pstate,
  592. struct sde_hw_pipe_cfg *pipe_cfg,
  593. struct drm_framebuffer *fb)
  594. {
  595. struct sde_plane *psde;
  596. struct msm_gem_address_space *aspace = NULL;
  597. int ret, mode;
  598. bool secure = false;
  599. if (!plane || !pstate || !pipe_cfg || !fb) {
  600. SDE_ERROR(
  601. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  602. !plane, !pstate, !pipe_cfg, !fb);
  603. return;
  604. }
  605. psde = to_sde_plane(plane);
  606. if (!psde->pipe_hw) {
  607. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  608. return;
  609. }
  610. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  611. if (ret) {
  612. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  613. return;
  614. }
  615. /*
  616. * framebuffer prepare is deferred for prepare_fb calls that
  617. * happen during the transition from secure to non-secure.
  618. * Handle the prepare at this point for such cases. This can be
  619. * expected for one or two frames during the transition.
  620. */
  621. if (aspace && pstate->defer_prepare_fb) {
  622. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  623. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  624. if (ret) {
  625. SDE_ERROR_PLANE(psde,
  626. "failed to prepare framebuffer %d\n", ret);
  627. return;
  628. }
  629. pstate->defer_prepare_fb = false;
  630. }
  631. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  632. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  633. secure = true;
  634. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  635. if (ret == -EAGAIN)
  636. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  637. else if (ret) {
  638. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  639. /*
  640. * Force solid fill color on error. This is to prevent
  641. * smmu faults during secure session transition.
  642. */
  643. psde->is_error = true;
  644. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  645. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  646. pipe_cfg->layout.width,
  647. pipe_cfg->layout.height,
  648. pipe_cfg->layout.plane_addr[0],
  649. pipe_cfg->layout.plane_size[0],
  650. pipe_cfg->layout.plane_addr[1],
  651. pipe_cfg->layout.plane_size[1],
  652. pipe_cfg->layout.plane_addr[2],
  653. pipe_cfg->layout.plane_size[2],
  654. pipe_cfg->layout.plane_addr[3],
  655. pipe_cfg->layout.plane_size[3],
  656. pstate->multirect_index,
  657. secure);
  658. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  659. pstate->multirect_index);
  660. }
  661. }
  662. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  663. struct sde_plane_state *pstate)
  664. {
  665. struct sde_hw_scaler3_cfg *cfg;
  666. int ret = 0;
  667. if (!psde || !pstate) {
  668. SDE_ERROR("invalid args\n");
  669. return -EINVAL;
  670. }
  671. cfg = &pstate->scaler3_cfg;
  672. cfg->dir_lut = msm_property_get_blob(
  673. &psde->property_info,
  674. &pstate->property_state, &cfg->dir_len,
  675. PLANE_PROP_SCALER_LUT_ED);
  676. cfg->cir_lut = msm_property_get_blob(
  677. &psde->property_info,
  678. &pstate->property_state, &cfg->cir_len,
  679. PLANE_PROP_SCALER_LUT_CIR);
  680. cfg->sep_lut = msm_property_get_blob(
  681. &psde->property_info,
  682. &pstate->property_state, &cfg->sep_len,
  683. PLANE_PROP_SCALER_LUT_SEP);
  684. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  685. ret = -ENODATA;
  686. return ret;
  687. }
  688. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  689. struct sde_plane_state *pstate)
  690. {
  691. struct sde_hw_scaler3_cfg *cfg;
  692. cfg = &pstate->scaler3_cfg;
  693. cfg->sep_lut = msm_property_get_blob(
  694. &psde->property_info,
  695. &pstate->property_state, &cfg->sep_len,
  696. PLANE_PROP_SCALER_LUT_SEP);
  697. return cfg->sep_lut ? 0 : -ENODATA;
  698. }
  699. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  700. struct sde_plane_state *pstate, const struct sde_format *fmt,
  701. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  702. {
  703. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  704. struct sde_hw_scaler3_cfg *scale_cfg;
  705. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  706. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  707. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  708. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  709. chroma_subsmpl_h, chroma_subsmpl_v);
  710. return;
  711. }
  712. scale_cfg = &pstate->scaler3_cfg;
  713. src_w = psde->pipe_cfg.src_rect.w;
  714. src_h = psde->pipe_cfg.src_rect.h;
  715. dst_w = psde->pipe_cfg.dst_rect.w;
  716. dst_h = psde->pipe_cfg.dst_rect.h;
  717. memset(scale_cfg, 0, sizeof(*scale_cfg));
  718. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  719. /*
  720. * For inline rotation cases, scaler config is post-rotation,
  721. * so swap the dimensions here. However, pixel extension will
  722. * need pre-rotation settings, this will be corrected below
  723. * when calculating pixel extension settings.
  724. */
  725. if (inline_rotation)
  726. swap(src_w, src_h);
  727. decimated = DECIMATED_DIMENSION(src_w,
  728. psde->pipe_cfg.horz_decimation);
  729. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  730. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  731. decimated = DECIMATED_DIMENSION(src_h,
  732. psde->pipe_cfg.vert_decimation);
  733. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  734. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  735. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  736. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  738. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  739. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  740. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  741. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  743. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  744. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  747. for (i = 0; i < SDE_MAX_PLANES; i++) {
  748. /*
  749. * For inline rotation cases with pre-downscaling enabled
  750. * set x pre-downscale value if required. Only x direction
  751. * is currently supported. Use src_h as values have been swapped
  752. * and x direction corresponds to height value.
  753. */
  754. src_h_pre_down = src_h;
  755. if (pre_down_supported && inline_rotation) {
  756. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  757. src_h_pre_down = src_h / 2;
  758. }
  759. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  760. psde->pipe_cfg.horz_decimation);
  761. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  762. psde->pipe_cfg.vert_decimation);
  763. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  764. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  765. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  766. }
  767. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  768. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  769. /* For pixel extension we need the pre-rotated orientation */
  770. if (inline_rotation) {
  771. pstate->pixel_ext.num_ext_pxls_top[i] =
  772. scale_cfg->src_width[i];
  773. pstate->pixel_ext.num_ext_pxls_left[i] =
  774. scale_cfg->src_height[i];
  775. } else {
  776. pstate->pixel_ext.num_ext_pxls_top[i] =
  777. scale_cfg->src_height[i];
  778. pstate->pixel_ext.num_ext_pxls_left[i] =
  779. scale_cfg->src_width[i];
  780. }
  781. }
  782. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  783. && (src_w == dst_w) && !inline_rotation) ||
  784. pstate->multirect_mode)
  785. return;
  786. SDE_DEBUG_PLANE(psde,
  787. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  788. src_w, src_h, dst_w, dst_h,
  789. chroma_subsmpl_v, chroma_subsmpl_h,
  790. fmt->base.pixel_format);
  791. scale_cfg->dst_width = dst_w;
  792. scale_cfg->dst_height = dst_h;
  793. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  794. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  795. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  796. scale_cfg->lut_flag = 0;
  797. scale_cfg->blend_cfg = 1;
  798. scale_cfg->enable = 1;
  799. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  800. }
  801. /**
  802. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  803. * @psde: Pointer to SDE plane object
  804. * @src: Source size
  805. * @dst: Destination size
  806. * @phase_steps: Pointer to output array for phase steps
  807. * @filter: Pointer to output array for filter type
  808. * @fmt: Pointer to format definition
  809. * @chroma_subsampling: Subsampling amount for chroma channel
  810. *
  811. * Returns: 0 on success
  812. */
  813. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  814. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  815. enum sde_hw_filter *filter, const struct sde_format *fmt,
  816. uint32_t chroma_subsampling)
  817. {
  818. if (!psde || !phase_steps || !filter || !fmt) {
  819. SDE_ERROR(
  820. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  821. !psde, !phase_steps, !filter, !fmt);
  822. return -EINVAL;
  823. }
  824. /* calculate phase steps, leave init phase as zero */
  825. phase_steps[SDE_SSPP_COMP_0] =
  826. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  827. phase_steps[SDE_SSPP_COMP_1_2] =
  828. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  829. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  830. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  831. /* calculate scaler config, if necessary */
  832. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  833. filter[SDE_SSPP_COMP_3] =
  834. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  835. SDE_SCALE_FILTER_PCMN;
  836. if (SDE_FORMAT_IS_YUV(fmt)) {
  837. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  838. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  839. } else {
  840. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  841. filter[SDE_SSPP_COMP_1_2] =
  842. SDE_SCALE_FILTER_NEAREST;
  843. }
  844. } else {
  845. /* disable scaler */
  846. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  847. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  848. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  849. }
  850. return 0;
  851. }
  852. /**
  853. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  854. * @psde: Pointer to SDE plane object
  855. * @src: Source size
  856. * @dst: Destination size
  857. * @decimated_src: Source size after decimation, if any
  858. * @phase_steps: Pointer to output array for phase steps
  859. * @out_src: Output array for pixel extension values
  860. * @out_edge1: Output array for pixel extension first edge
  861. * @out_edge2: Output array for pixel extension second edge
  862. * @filter: Pointer to array for filter type
  863. * @fmt: Pointer to format definition
  864. * @chroma_subsampling: Subsampling amount for chroma channel
  865. * @post_compare: Whether to chroma subsampled source size for comparisions
  866. */
  867. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  868. uint32_t src, uint32_t dst, uint32_t decimated_src,
  869. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  870. int *out_edge2, enum sde_hw_filter *filter,
  871. const struct sde_format *fmt, uint32_t chroma_subsampling,
  872. bool post_compare)
  873. {
  874. int64_t edge1, edge2, caf;
  875. uint32_t src_work;
  876. int i, tmp;
  877. if (psde && phase_steps && out_src && out_edge1 &&
  878. out_edge2 && filter && fmt) {
  879. /* handle CAF for YUV formats */
  880. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  881. caf = PHASE_STEP_UNIT_SCALE;
  882. else
  883. caf = 0;
  884. for (i = 0; i < SDE_MAX_PLANES; i++) {
  885. src_work = decimated_src;
  886. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  887. src_work /= chroma_subsampling;
  888. if (post_compare)
  889. src = src_work;
  890. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  891. /* unity */
  892. edge1 = 0;
  893. edge2 = 0;
  894. } else if (dst >= src) {
  895. /* upscale */
  896. edge1 = (1 << PHASE_RESIDUAL);
  897. edge1 -= caf;
  898. edge2 = (1 << PHASE_RESIDUAL);
  899. edge2 += (dst - 1) * *(phase_steps + i);
  900. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  901. edge2 += caf;
  902. edge2 = -(edge2);
  903. } else {
  904. /* downscale */
  905. edge1 = 0;
  906. edge2 = (dst - 1) * *(phase_steps + i);
  907. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  908. edge2 += *(phase_steps + i);
  909. edge2 = -(edge2);
  910. }
  911. /* only enable CAF for luma plane */
  912. caf = 0;
  913. /* populate output arrays */
  914. *(out_src + i) = src_work;
  915. /* edge updates taken from __pxl_extn_helper */
  916. if (edge1 >= 0) {
  917. tmp = (uint32_t)edge1;
  918. tmp >>= PHASE_STEP_SHIFT;
  919. *(out_edge1 + i) = -tmp;
  920. } else {
  921. tmp = (uint32_t)(-edge1);
  922. *(out_edge1 + i) =
  923. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  924. PHASE_STEP_SHIFT;
  925. }
  926. if (edge2 >= 0) {
  927. tmp = (uint32_t)edge2;
  928. tmp >>= PHASE_STEP_SHIFT;
  929. *(out_edge2 + i) = -tmp;
  930. } else {
  931. tmp = (uint32_t)(-edge2);
  932. *(out_edge2 + i) =
  933. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  934. PHASE_STEP_SHIFT;
  935. }
  936. }
  937. }
  938. }
  939. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  940. {
  941. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  942. {
  943. /* S15.16 format */
  944. 0x00012A00, 0x00000000, 0x00019880,
  945. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  946. 0x00012A00, 0x00020480, 0x00000000,
  947. },
  948. /* signed bias */
  949. { 0xfff0, 0xff80, 0xff80,},
  950. { 0x0, 0x0, 0x0,},
  951. /* unsigned clamp */
  952. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  953. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  954. };
  955. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  956. {
  957. /* S15.16 format */
  958. 0x00012A00, 0x00000000, 0x00019880,
  959. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  960. 0x00012A00, 0x00020480, 0x00000000,
  961. },
  962. /* signed bias */
  963. { 0xffc0, 0xfe00, 0xfe00,},
  964. { 0x0, 0x0, 0x0,},
  965. /* unsigned clamp */
  966. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  967. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  968. };
  969. if (!psde) {
  970. SDE_ERROR("invalid plane\n");
  971. return;
  972. }
  973. /* revert to kernel default if override not available */
  974. if (psde->csc_usr_ptr)
  975. psde->csc_ptr = psde->csc_usr_ptr;
  976. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  977. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  978. else
  979. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  980. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  981. psde->csc_ptr->csc_mv[0],
  982. psde->csc_ptr->csc_mv[1],
  983. psde->csc_ptr->csc_mv[2]);
  984. }
  985. static void sde_color_process_plane_setup(struct drm_plane *plane)
  986. {
  987. struct sde_plane *psde;
  988. struct sde_plane_state *pstate;
  989. uint32_t hue, saturation, value, contrast;
  990. struct drm_msm_memcol *memcol = NULL;
  991. struct drm_msm_3d_gamut *vig_gamut = NULL;
  992. struct drm_msm_igc_lut *igc = NULL;
  993. struct drm_msm_pgc_lut *gc = NULL;
  994. size_t memcol_sz = 0, size = 0;
  995. struct sde_hw_cp_cfg hw_cfg = {};
  996. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  997. psde = to_sde_plane(plane);
  998. pstate = to_sde_plane_state(plane->state);
  999. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1000. if (psde->pipe_hw->ops.setup_pa_hue)
  1001. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1002. saturation = (uint32_t) sde_plane_get_property(pstate,
  1003. PLANE_PROP_SATURATION_ADJUST);
  1004. if (psde->pipe_hw->ops.setup_pa_sat)
  1005. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1006. value = (uint32_t) sde_plane_get_property(pstate,
  1007. PLANE_PROP_VALUE_ADJUST);
  1008. if (psde->pipe_hw->ops.setup_pa_val)
  1009. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1010. contrast = (uint32_t) sde_plane_get_property(pstate,
  1011. PLANE_PROP_CONTRAST_ADJUST);
  1012. if (psde->pipe_hw->ops.setup_pa_cont)
  1013. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1014. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1015. /* Skin memory color setup */
  1016. memcol = msm_property_get_blob(&psde->property_info,
  1017. &pstate->property_state,
  1018. &memcol_sz,
  1019. PLANE_PROP_SKIN_COLOR);
  1020. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1021. MEMCOLOR_SKIN, memcol);
  1022. /* Sky memory color setup */
  1023. memcol = msm_property_get_blob(&psde->property_info,
  1024. &pstate->property_state,
  1025. &memcol_sz,
  1026. PLANE_PROP_SKY_COLOR);
  1027. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1028. MEMCOLOR_SKY, memcol);
  1029. /* Foliage memory color setup */
  1030. memcol = msm_property_get_blob(&psde->property_info,
  1031. &pstate->property_state,
  1032. &memcol_sz,
  1033. PLANE_PROP_FOLIAGE_COLOR);
  1034. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1035. MEMCOLOR_FOLIAGE, memcol);
  1036. }
  1037. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1038. psde->pipe_hw->ops.setup_vig_gamut) {
  1039. vig_gamut = msm_property_get_blob(&psde->property_info,
  1040. &pstate->property_state,
  1041. &size,
  1042. PLANE_PROP_VIG_GAMUT);
  1043. hw_cfg.last_feature = 0;
  1044. hw_cfg.ctl = ctl;
  1045. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1046. hw_cfg.payload = vig_gamut;
  1047. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1048. }
  1049. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1050. psde->pipe_hw->ops.setup_vig_igc) {
  1051. igc = msm_property_get_blob(&psde->property_info,
  1052. &pstate->property_state,
  1053. &size,
  1054. PLANE_PROP_VIG_IGC);
  1055. hw_cfg.last_feature = 0;
  1056. hw_cfg.ctl = ctl;
  1057. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1058. hw_cfg.payload = igc;
  1059. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1060. }
  1061. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1062. psde->pipe_hw->ops.setup_dma_igc) {
  1063. igc = msm_property_get_blob(&psde->property_info,
  1064. &pstate->property_state,
  1065. &size,
  1066. PLANE_PROP_DMA_IGC);
  1067. hw_cfg.last_feature = 0;
  1068. hw_cfg.ctl = ctl;
  1069. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1070. hw_cfg.payload = igc;
  1071. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1072. pstate->multirect_index);
  1073. }
  1074. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1075. psde->pipe_hw->ops.setup_dma_gc) {
  1076. gc = msm_property_get_blob(&psde->property_info,
  1077. &pstate->property_state,
  1078. &size,
  1079. PLANE_PROP_DMA_GC);
  1080. hw_cfg.last_feature = 0;
  1081. hw_cfg.ctl = ctl;
  1082. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1083. hw_cfg.payload = gc;
  1084. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1085. pstate->multirect_index);
  1086. }
  1087. }
  1088. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1089. struct sde_plane_state *pstate,
  1090. const struct sde_format *fmt, bool color_fill)
  1091. {
  1092. struct sde_hw_pixel_ext *pe;
  1093. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1094. const struct drm_format_info *info = NULL;
  1095. if (!psde || !fmt || !pstate) {
  1096. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1097. !psde, !fmt, !pstate);
  1098. return;
  1099. }
  1100. info = drm_format_info(fmt->base.pixel_format);
  1101. pe = &pstate->pixel_ext;
  1102. psde->pipe_cfg.horz_decimation =
  1103. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1104. psde->pipe_cfg.vert_decimation =
  1105. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1106. /* don't chroma subsample if decimating */
  1107. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1108. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1109. /* update scaler */
  1110. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1111. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1112. int rc = -EINVAL;
  1113. if (!color_fill && !psde->debugfs_default_scale)
  1114. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1115. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1116. _sde_plane_setup_scaler3_lut(psde, pstate);
  1117. if (rc || pstate->scaler_check_state !=
  1118. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1119. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1120. pstate->scaler_check_state,
  1121. psde->debugfs_default_scale, rc,
  1122. psde->pipe_cfg.src_rect.w,
  1123. psde->pipe_cfg.src_rect.h,
  1124. psde->pipe_cfg.dst_rect.w,
  1125. psde->pipe_cfg.dst_rect.h,
  1126. pstate->multirect_mode);
  1127. /* calculate default config for QSEED3 */
  1128. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1129. chroma_subsmpl_h, chroma_subsmpl_v);
  1130. }
  1131. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1132. color_fill || psde->debugfs_default_scale) {
  1133. uint32_t deci_dim, i;
  1134. /* calculate default configuration for QSEED2 */
  1135. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1136. SDE_DEBUG_PLANE(psde, "default config\n");
  1137. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1138. psde->pipe_cfg.horz_decimation);
  1139. _sde_plane_setup_scaler2(psde,
  1140. deci_dim,
  1141. psde->pipe_cfg.dst_rect.w,
  1142. pe->phase_step_x,
  1143. pe->horz_filter, fmt, chroma_subsmpl_h);
  1144. if (SDE_FORMAT_IS_YUV(fmt))
  1145. deci_dim &= ~0x1;
  1146. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1147. psde->pipe_cfg.dst_rect.w, deci_dim,
  1148. pe->phase_step_x,
  1149. pe->roi_w,
  1150. pe->num_ext_pxls_left,
  1151. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1152. chroma_subsmpl_h, 0);
  1153. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1154. psde->pipe_cfg.vert_decimation);
  1155. _sde_plane_setup_scaler2(psde,
  1156. deci_dim,
  1157. psde->pipe_cfg.dst_rect.h,
  1158. pe->phase_step_y,
  1159. pe->vert_filter, fmt, chroma_subsmpl_v);
  1160. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1161. psde->pipe_cfg.dst_rect.h, deci_dim,
  1162. pe->phase_step_y,
  1163. pe->roi_h,
  1164. pe->num_ext_pxls_top,
  1165. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1166. chroma_subsmpl_v, 1);
  1167. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1168. if (pe->num_ext_pxls_left[i] >= 0)
  1169. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1170. else
  1171. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1172. if (pe->num_ext_pxls_right[i] >= 0)
  1173. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1174. else
  1175. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1176. if (pe->num_ext_pxls_top[i] >= 0)
  1177. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1178. else
  1179. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1180. if (pe->num_ext_pxls_btm[i] >= 0)
  1181. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1182. else
  1183. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1184. }
  1185. }
  1186. if (psde->pipe_hw->ops.setup_pre_downscale)
  1187. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1188. &pstate->pre_down);
  1189. }
  1190. /**
  1191. * _sde_plane_color_fill - enables color fill on plane
  1192. * @psde: Pointer to SDE plane object
  1193. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1194. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1195. * Returns: 0 on success
  1196. */
  1197. static int _sde_plane_color_fill(struct sde_plane *psde,
  1198. uint32_t color, uint32_t alpha)
  1199. {
  1200. const struct sde_format *fmt;
  1201. const struct drm_plane *plane;
  1202. struct sde_plane_state *pstate;
  1203. bool blend_enable = true;
  1204. if (!psde || !psde->base.state) {
  1205. SDE_ERROR("invalid plane\n");
  1206. return -EINVAL;
  1207. }
  1208. if (!psde->pipe_hw) {
  1209. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1210. return -EINVAL;
  1211. }
  1212. plane = &psde->base;
  1213. pstate = to_sde_plane_state(plane->state);
  1214. SDE_DEBUG_PLANE(psde, "\n");
  1215. /*
  1216. * select fill format to match user property expectation,
  1217. * h/w only supports RGB variants
  1218. */
  1219. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1220. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1221. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1222. /* update sspp */
  1223. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1224. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1225. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1226. pstate->multirect_index);
  1227. /* override scaler/decimation if solid fill */
  1228. psde->pipe_cfg.src_rect.x = 0;
  1229. psde->pipe_cfg.src_rect.y = 0;
  1230. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1231. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1232. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1233. if (psde->pipe_hw->ops.setup_format)
  1234. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1235. fmt, blend_enable,
  1236. SDE_SSPP_SOLID_FILL,
  1237. pstate->multirect_index);
  1238. if (psde->pipe_hw->ops.setup_rects)
  1239. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1240. &psde->pipe_cfg,
  1241. pstate->multirect_index);
  1242. if (psde->pipe_hw->ops.setup_pe)
  1243. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1244. &pstate->pixel_ext);
  1245. if (psde->pipe_hw->ops.setup_scaler &&
  1246. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1247. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1248. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1249. &psde->pipe_cfg, &pstate->pixel_ext,
  1250. &pstate->scaler3_cfg);
  1251. }
  1252. }
  1253. return 0;
  1254. }
  1255. /**
  1256. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1257. * @plane: Pointer to drm plane
  1258. * @state: Pointer to drm plane state to be validated
  1259. * return: 0 if success; error code otherwise
  1260. */
  1261. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1262. struct drm_plane_state *state)
  1263. {
  1264. struct sde_plane *psde;
  1265. struct sde_plane_state *pstate, *old_pstate;
  1266. int ret = 0;
  1267. u32 rotation;
  1268. if (!plane || !state) {
  1269. SDE_ERROR("invalid plane/state\n");
  1270. return -EINVAL;
  1271. }
  1272. psde = to_sde_plane(plane);
  1273. pstate = to_sde_plane_state(state);
  1274. old_pstate = to_sde_plane_state(plane->state);
  1275. /* check inline rotation and simplify the transform */
  1276. rotation = drm_rotation_simplify(
  1277. state->rotation,
  1278. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1279. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1280. if ((rotation & DRM_MODE_ROTATE_180) ||
  1281. (rotation & DRM_MODE_ROTATE_270)) {
  1282. SDE_ERROR_PLANE(psde,
  1283. "invalid rotation transform must be simplified 0x%x\n",
  1284. rotation);
  1285. ret = -EINVAL;
  1286. goto exit;
  1287. }
  1288. if (rotation & DRM_MODE_ROTATE_90) {
  1289. struct msm_drm_private *priv = plane->dev->dev_private;
  1290. struct sde_kms *sde_kms;
  1291. const struct msm_format *msm_fmt;
  1292. const struct sde_format *fmt;
  1293. struct sde_rect src;
  1294. bool q16_data = true;
  1295. POPULATE_RECT(&src, state->src_x, state->src_y,
  1296. state->src_w, state->src_h, q16_data);
  1297. /*
  1298. * DRM framework expects rotation flag in counter-clockwise
  1299. * direction and the HW expects in clockwise direction.
  1300. * Flip the flags to match with HW.
  1301. */
  1302. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1303. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1304. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1305. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1306. !psde->pipe_sblk->in_rot_maxheight ||
  1307. !psde->pipe_sblk->in_rot_format_list ||
  1308. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1309. SDE_ERROR_PLANE(psde,
  1310. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1311. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1312. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1313. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1314. !psde->pipe_sblk->in_rot_format_list,
  1315. !psde->pipe_sblk->in_rot_maxheight,
  1316. psde->features);
  1317. ret = -EINVAL;
  1318. goto exit;
  1319. }
  1320. /* check for valid height */
  1321. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1322. SDE_ERROR_PLANE(psde,
  1323. "invalid height for inline rot:%d max:%d\n",
  1324. src.h, psde->pipe_sblk->in_rot_maxheight);
  1325. ret = -EINVAL;
  1326. goto exit;
  1327. }
  1328. if (!sde_plane_enabled(state))
  1329. goto exit;
  1330. /* check for valid formats supported by inline rot */
  1331. sde_kms = to_sde_kms(priv->kms);
  1332. msm_fmt = msm_framebuffer_format(state->fb);
  1333. fmt = to_sde_format(msm_fmt);
  1334. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1335. psde->pipe_sblk->in_rot_format_list);
  1336. }
  1337. exit:
  1338. pstate->rotation = rotation;
  1339. return ret;
  1340. }
  1341. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1342. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1343. {
  1344. struct sde_plane *psde;
  1345. struct msm_drm_private *priv;
  1346. struct sde_vbif_set_xin_halt_params halt_params;
  1347. if (!plane || !plane->dev) {
  1348. SDE_ERROR("invalid arguments\n");
  1349. return false;
  1350. }
  1351. psde = to_sde_plane(plane);
  1352. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1353. SDE_ERROR("invalid pipe reference\n");
  1354. return false;
  1355. }
  1356. priv = plane->dev->dev_private;
  1357. if (!priv || !priv->kms) {
  1358. SDE_ERROR("invalid KMS reference\n");
  1359. return false;
  1360. }
  1361. memset(&halt_params, 0, sizeof(halt_params));
  1362. halt_params.vbif_idx = VBIF_RT;
  1363. halt_params.xin_id = xin_id;
  1364. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1365. halt_params.forced_on = halt_forced_clk;
  1366. halt_params.enable = enable;
  1367. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1368. }
  1369. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1370. {
  1371. struct sde_plane *psde;
  1372. if (!plane) {
  1373. SDE_ERROR("invalid plane\n");
  1374. return;
  1375. }
  1376. psde = to_sde_plane(plane);
  1377. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1378. SDE_ERROR("invalid pipe reference\n");
  1379. return;
  1380. }
  1381. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1382. psde->xin_halt_forced_clk =
  1383. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1384. psde->xin_halt_forced_clk, enable);
  1385. }
  1386. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1387. struct drm_crtc *crtc)
  1388. {
  1389. struct sde_plane *psde;
  1390. if (!plane || !crtc) {
  1391. SDE_ERROR("invalid plane/crtc\n");
  1392. return;
  1393. }
  1394. psde = to_sde_plane(plane);
  1395. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1396. return;
  1397. /* do all VBIF programming for the sec-ui allowed SSPP */
  1398. _sde_plane_set_qos_remap(plane);
  1399. _sde_plane_set_ot_limit(plane, crtc);
  1400. }
  1401. /**
  1402. * sde_plane_rot_install_properties - install plane rotator properties
  1403. * @plane: Pointer to drm plane
  1404. * @catalog: Pointer to mdss configuration
  1405. * return: none
  1406. */
  1407. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1408. struct sde_mdss_cfg *catalog)
  1409. {
  1410. struct sde_plane *psde = to_sde_plane(plane);
  1411. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1412. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1413. int ret = 0;
  1414. if (!plane || !psde) {
  1415. SDE_ERROR("invalid plane\n");
  1416. return;
  1417. } else if (!catalog) {
  1418. SDE_ERROR("invalid catalog\n");
  1419. return;
  1420. }
  1421. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1422. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1423. ret = drm_plane_create_rotation_property(plane,
  1424. DRM_MODE_ROTATE_0, supported_rotations);
  1425. if (ret) {
  1426. DRM_ERROR("create rotation property failed: %d\n", ret);
  1427. return;
  1428. }
  1429. }
  1430. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1431. {
  1432. struct sde_plane_state *pstate;
  1433. if (!drm_state)
  1434. return;
  1435. pstate = to_sde_plane_state(drm_state);
  1436. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1437. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1438. }
  1439. /**
  1440. * multi_rect validate API allows to validate only R0 and R1 RECT
  1441. * passing for each plane. Client of this API must not pass multiple
  1442. * plane which are not sharing same XIN client. Such calls will fail
  1443. * even though kernel client is passing valid multirect configuration.
  1444. */
  1445. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1446. {
  1447. struct sde_plane_state *pstate[R_MAX];
  1448. const struct drm_plane_state *drm_state[R_MAX];
  1449. struct sde_rect src[R_MAX], dst[R_MAX];
  1450. struct sde_plane *sde_plane[R_MAX];
  1451. const struct sde_format *fmt[R_MAX];
  1452. int xin_id[R_MAX];
  1453. bool q16_data = true;
  1454. int i, j, buffer_lines, width_threshold[R_MAX];
  1455. unsigned int max_tile_height = 1;
  1456. bool parallel_fetch_qualified = true;
  1457. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1458. const struct msm_format *msm_fmt;
  1459. bool const_alpha_enable = true;
  1460. for (i = 0; i < R_MAX; i++) {
  1461. drm_state[i] = i ? plane->r1 : plane->r0;
  1462. if (!drm_state[i]) {
  1463. SDE_ERROR("drm plane state is NULL\n");
  1464. return -EINVAL;
  1465. }
  1466. pstate[i] = to_sde_plane_state(drm_state[i]);
  1467. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1468. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1469. for (j = 0; j < i; j++) {
  1470. if (xin_id[i] != xin_id[j]) {
  1471. SDE_ERROR_PLANE(sde_plane[i],
  1472. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1473. j, xin_id[j], i, xin_id[i]);
  1474. return -EINVAL;
  1475. }
  1476. }
  1477. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1478. if (!msm_fmt) {
  1479. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1480. return -EINVAL;
  1481. }
  1482. fmt[i] = to_sde_format(msm_fmt);
  1483. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1484. (fmt[i]->tile_height > max_tile_height))
  1485. max_tile_height = fmt[i]->tile_height;
  1486. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1487. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1488. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1489. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1490. drm_state[i]->crtc_h, !q16_data);
  1491. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1492. SDE_ERROR_PLANE(sde_plane[i],
  1493. "scaling is not supported in multirect mode\n");
  1494. return -EINVAL;
  1495. }
  1496. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1497. SDE_ERROR_PLANE(sde_plane[i],
  1498. "inline rotation is not supported in mulirect mode\n");
  1499. return -EINVAL;
  1500. }
  1501. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1502. SDE_ERROR_PLANE(sde_plane[i],
  1503. "Unsupported format for multirect mode\n");
  1504. return -EINVAL;
  1505. }
  1506. /**
  1507. * SSPP PD_MEM is split half - one for each RECT.
  1508. * Tiled formats need 5 lines of buffering while fetching
  1509. * whereas linear formats need only 2 lines.
  1510. * So we cannot support more than half of the supported SSPP
  1511. * width for tiled formats.
  1512. */
  1513. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1514. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1515. width_threshold[i] /= 2;
  1516. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1517. parallel_fetch_qualified = false;
  1518. if (sde_plane[i]->is_virtual)
  1519. mode = sde_plane_get_property(pstate[i],
  1520. PLANE_PROP_MULTIRECT_MODE);
  1521. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1522. const_alpha_enable = false;
  1523. }
  1524. buffer_lines = 2 * max_tile_height;
  1525. /**
  1526. * fallback to driver mode selection logic if client is using
  1527. * multirect plane without setting property.
  1528. *
  1529. * validate multirect mode configuration based on rectangle
  1530. */
  1531. switch (mode) {
  1532. case SDE_SSPP_MULTIRECT_NONE:
  1533. if (parallel_fetch_qualified)
  1534. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1535. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1536. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1537. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1538. else
  1539. SDE_ERROR(
  1540. "planes(%d - %d) multirect mode selection fail\n",
  1541. drm_state[R0]->plane->base.id,
  1542. drm_state[R1]->plane->base.id);
  1543. break;
  1544. case SDE_SSPP_MULTIRECT_PARALLEL:
  1545. if (!parallel_fetch_qualified) {
  1546. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1547. drm_state[R0]->plane->base.id,
  1548. width_threshold[R0], src[R0].w);
  1549. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1550. drm_state[R1]->plane->base.id,
  1551. width_threshold[R1], src[R1].w);
  1552. SDE_ERROR("parallel fetch not qualified\n");
  1553. mode = SDE_SSPP_MULTIRECT_NONE;
  1554. }
  1555. break;
  1556. case SDE_SSPP_MULTIRECT_TIME_MX:
  1557. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1558. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1559. SDE_ERROR(
  1560. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1561. buffer_lines, drm_state[R0]->plane->base.id,
  1562. dst[R0].y, dst[R0].h);
  1563. SDE_ERROR(
  1564. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1565. buffer_lines, drm_state[R1]->plane->base.id,
  1566. dst[R1].y, dst[R1].h);
  1567. SDE_ERROR("time multiplexed fetch not qualified\n");
  1568. mode = SDE_SSPP_MULTIRECT_NONE;
  1569. }
  1570. break;
  1571. default:
  1572. SDE_ERROR("bad mode:%d selection\n", mode);
  1573. mode = SDE_SSPP_MULTIRECT_NONE;
  1574. break;
  1575. }
  1576. for (i = 0; i < R_MAX; i++) {
  1577. pstate[i]->multirect_mode = mode;
  1578. pstate[i]->const_alpha_en = const_alpha_enable;
  1579. }
  1580. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1581. return -EINVAL;
  1582. if (sde_plane[R0]->is_virtual) {
  1583. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1584. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1585. } else {
  1586. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1587. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1588. }
  1589. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1590. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1591. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1592. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1593. return 0;
  1594. }
  1595. /**
  1596. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1597. * @plane: Pointer to drm plane structure
  1598. * @ctl: Pointer to hardware control driver
  1599. * @set: set if true else clear
  1600. */
  1601. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1602. bool set)
  1603. {
  1604. if (!plane || !ctl) {
  1605. SDE_ERROR("invalid parameters\n");
  1606. return;
  1607. }
  1608. if (!ctl->ops.update_bitmask_sspp) {
  1609. SDE_ERROR("invalid ops\n");
  1610. return;
  1611. }
  1612. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1613. }
  1614. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1615. struct drm_plane_state *new_state)
  1616. {
  1617. struct drm_framebuffer *fb = new_state->fb;
  1618. struct sde_plane *psde = to_sde_plane(plane);
  1619. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1620. struct sde_hw_fmt_layout layout;
  1621. struct msm_gem_address_space *aspace;
  1622. int ret;
  1623. if (!fb)
  1624. return 0;
  1625. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1626. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1627. if (ret) {
  1628. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1629. return ret;
  1630. }
  1631. /* cache aspace */
  1632. pstate->aspace = aspace;
  1633. /*
  1634. * when transitioning from secure to non-secure,
  1635. * plane->prepare_fb happens before the commit. In such case,
  1636. * defer the prepare_fb and handled it late, during the commit
  1637. * after attaching the domains as part of the transition
  1638. */
  1639. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1640. true : false;
  1641. if (pstate->defer_prepare_fb) {
  1642. SDE_EVT32(DRMID(plane), psde->pipe);
  1643. SDE_DEBUG_PLANE(psde,
  1644. "domain not attached, prepare_fb handled later\n");
  1645. return 0;
  1646. }
  1647. if (pstate->aspace && fb) {
  1648. ret = msm_framebuffer_prepare(fb,
  1649. pstate->aspace);
  1650. if (ret) {
  1651. SDE_ERROR("failed to prepare framebuffer\n");
  1652. return ret;
  1653. }
  1654. }
  1655. /* validate framebuffer layout before commit */
  1656. ret = sde_format_populate_layout(pstate->aspace,
  1657. fb, &layout);
  1658. if (ret) {
  1659. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1660. return ret;
  1661. }
  1662. return 0;
  1663. }
  1664. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1665. struct drm_plane_state *old_state)
  1666. {
  1667. struct sde_plane *psde = to_sde_plane(plane);
  1668. struct sde_plane_state *old_pstate;
  1669. if (!old_state || !old_state->fb || !plane)
  1670. return;
  1671. old_pstate = to_sde_plane_state(old_state);
  1672. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1673. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1674. }
  1675. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1676. struct drm_plane_state *state,
  1677. struct drm_plane_state *old_state)
  1678. {
  1679. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1680. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1681. struct drm_framebuffer *fb, *old_fb;
  1682. /* no need to check it again */
  1683. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1684. return;
  1685. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1686. || psde->is_error) {
  1687. SDE_DEBUG_PLANE(psde,
  1688. "enabling/disabling full modeset required\n");
  1689. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1690. } else if (to_sde_plane_state(old_state)->pending) {
  1691. SDE_DEBUG_PLANE(psde, "still pending\n");
  1692. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1693. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1694. pstate->multirect_mode != old_pstate->multirect_mode) {
  1695. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1696. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1697. } else if (state->src_w != old_state->src_w ||
  1698. state->src_h != old_state->src_h ||
  1699. state->src_x != old_state->src_x ||
  1700. state->src_y != old_state->src_y) {
  1701. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1702. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1703. } else if (state->crtc_w != old_state->crtc_w ||
  1704. state->crtc_h != old_state->crtc_h ||
  1705. state->crtc_x != old_state->crtc_x ||
  1706. state->crtc_y != old_state->crtc_y) {
  1707. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1708. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1709. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1710. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1711. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1712. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1713. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1714. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1715. } else if (pstate->rotation != old_pstate->rotation) {
  1716. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1717. pstate->rotation, old_pstate->rotation);
  1718. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1719. }
  1720. fb = state->fb;
  1721. old_fb = old_state->fb;
  1722. if (!fb || !old_fb) {
  1723. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1724. } else if ((fb->format->format != old_fb->format->format) ||
  1725. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1726. SDE_DEBUG_PLANE(psde, "format change\n");
  1727. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1728. } else {
  1729. uint64_t new_mod = fb->modifier;
  1730. uint64_t old_mod = old_fb->modifier;
  1731. uint32_t *new_pitches = fb->pitches;
  1732. uint32_t *old_pitches = old_fb->pitches;
  1733. uint32_t *new_offset = fb->offsets;
  1734. uint32_t *old_offset = old_fb->offsets;
  1735. int i;
  1736. if (new_mod != old_mod) {
  1737. SDE_DEBUG_PLANE(psde,
  1738. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1739. new_mod, old_mod);
  1740. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1741. SDE_PLANE_DIRTY_RECTS;
  1742. }
  1743. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1744. if (new_pitches[i] != old_pitches[i]) {
  1745. SDE_DEBUG_PLANE(psde,
  1746. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1747. i, old_pitches[i], new_pitches[i]);
  1748. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1749. break;
  1750. }
  1751. }
  1752. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1753. if (new_offset[i] != old_offset[i]) {
  1754. SDE_DEBUG_PLANE(psde,
  1755. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1756. i, old_offset[i], new_offset[i]);
  1757. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1758. SDE_PLANE_DIRTY_RECTS;
  1759. break;
  1760. }
  1761. }
  1762. }
  1763. }
  1764. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1765. unsigned long base_addr, u32 size)
  1766. {
  1767. int ret = -EINVAL;
  1768. u32 addr;
  1769. struct sde_plane *psde = to_sde_plane(plane);
  1770. if (!psde || !base_addr || !size) {
  1771. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1772. return ret;
  1773. }
  1774. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1775. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1776. is_sde_plane_virtual(plane));
  1777. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1778. ret = 0;
  1779. }
  1780. return ret;
  1781. }
  1782. static inline bool _sde_plane_is_pre_downscale_enabled(
  1783. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1784. {
  1785. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1786. }
  1787. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1788. struct sde_plane_state *pstate,
  1789. const struct sde_format *fmt,
  1790. uint32_t img_w, uint32_t img_h,
  1791. uint32_t src_w, uint32_t src_h,
  1792. uint32_t deci_w, uint32_t deci_h)
  1793. {
  1794. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1795. bool pre_down_en;
  1796. int i;
  1797. if (!psde || !pstate || !fmt) {
  1798. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1799. return -EINVAL;
  1800. }
  1801. if (psde->debugfs_default_scale ||
  1802. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1803. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1804. return 0;
  1805. pd_cfg = &pstate->pre_down;
  1806. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1807. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1808. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1809. uint32_t hor_req_pixels, hor_fetch_pixels;
  1810. uint32_t vert_req_pixels, vert_fetch_pixels;
  1811. uint32_t src_w_tmp, src_h_tmp;
  1812. uint32_t scaler_w, scaler_h;
  1813. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1814. bool rot;
  1815. /* re-use color plane 1's config for plane 2 */
  1816. if (i == 2)
  1817. continue;
  1818. if (pre_down_en) {
  1819. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1820. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1821. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1822. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1823. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1824. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1825. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1826. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1827. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1828. i, pre_down_ratio_x, pre_down_ratio_y);
  1829. }
  1830. src_w_tmp = src_w;
  1831. src_h_tmp = src_h;
  1832. /*
  1833. * For chroma plane, width is half for the following sub sampled
  1834. * formats. Except in case of decimation, where hardware avoids
  1835. * 1 line of decimation instead of downsampling.
  1836. */
  1837. if (i == 1) {
  1838. if (!deci_w &&
  1839. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1840. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1841. src_w_tmp >>= 1;
  1842. if (!deci_h &&
  1843. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1844. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1845. src_h_tmp >>= 1;
  1846. }
  1847. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1848. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1849. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1850. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1851. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1852. deci_w);
  1853. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1854. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1855. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1856. deci_h);
  1857. if ((hor_req_pixels != hor_fetch_pixels) ||
  1858. (hor_fetch_pixels > img_w) ||
  1859. (vert_req_pixels != vert_fetch_pixels) ||
  1860. (vert_fetch_pixels > img_h)) {
  1861. SDE_ERROR_PLANE(psde,
  1862. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1863. hor_req_pixels, vert_req_pixels,
  1864. hor_fetch_pixels, vert_fetch_pixels,
  1865. img_w, img_h);
  1866. return -EINVAL;
  1867. }
  1868. /*
  1869. * swap the scaler src width & height for inline-rotation 90
  1870. * comparison with Pixel-Extension, as PE is based on
  1871. * pre-rotation and QSEED is based on post-rotation
  1872. */
  1873. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1874. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1875. : pstate->scaler3_cfg.src_width[i];
  1876. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1877. : pstate->scaler3_cfg.src_height[i];
  1878. /*
  1879. * Alpha plane can only be scaled using bilinear or pixel
  1880. * repeat/drop, src_width and src_height are only specified
  1881. * for Y and UV plane
  1882. */
  1883. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1884. vert_req_pixels / pre_down_ratio_y !=
  1885. scaler_h)) {
  1886. SDE_ERROR_PLANE(psde,
  1887. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1888. i, pstate->pixel_ext.roi_w[i],
  1889. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1890. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1891. return -EINVAL;
  1892. }
  1893. /*
  1894. * SSPP fetch , unpack output and QSEED3 input lines need
  1895. * to match for Y plane
  1896. */
  1897. if (i == 0 &&
  1898. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1899. BIT(SDE_DRM_DEINTERLACE)) &&
  1900. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1901. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1902. SDE_ERROR_PLANE(psde,
  1903. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1904. i, pstate->pixel_ext.roi_w[i],
  1905. pstate->pixel_ext.roi_h[i],
  1906. pstate->scaler3_cfg.src_width[i],
  1907. pstate->scaler3_cfg.src_height[i],
  1908. src_w, src_h);
  1909. return -EINVAL;
  1910. }
  1911. }
  1912. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1913. return 0;
  1914. }
  1915. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1916. {
  1917. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1918. }
  1919. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1920. struct sde_plane_state *pstate, struct sde_rect *dst,
  1921. u32 src_w, u32 src_h)
  1922. {
  1923. int ret = 0;
  1924. u32 min_ratio_numer, min_ratio_denom;
  1925. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1926. bool pd_x;
  1927. bool pd_y;
  1928. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1929. return ret;
  1930. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1931. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1932. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1933. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1934. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1935. SDE_ERROR_PLANE(psde,
  1936. "hw does not support pre-downscale X: 0x%x\n",
  1937. psde->features);
  1938. ret = -EINVAL;
  1939. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1940. SDE_ERROR_PLANE(psde,
  1941. "hw does not support pre-downscale Y: 0x%x\n",
  1942. psde->features);
  1943. ret = -EINVAL;
  1944. } else if (!min_ratio_numer || !min_ratio_denom) {
  1945. SDE_ERROR_PLANE(psde,
  1946. "min downscale ratio not set! %u / %u\n",
  1947. min_ratio_numer, min_ratio_denom);
  1948. ret = -EINVAL;
  1949. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  1950. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  1951. min_ratio_denom))) {
  1952. SDE_ERROR_PLANE(psde,
  1953. "failed min downscale-x check %u->%u, %u/%u\n",
  1954. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  1955. ret = -EINVAL;
  1956. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  1957. min_ratio_denom))) {
  1958. SDE_ERROR_PLANE(psde,
  1959. "failed min downscale-y check %u->%u, %u/%u\n",
  1960. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  1961. ret = -EINVAL;
  1962. }
  1963. return ret;
  1964. }
  1965. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  1966. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  1967. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  1968. u32 *max_numer_h, u32 *max_denom_h)
  1969. {
  1970. bool rotated, has_predown, default_scale;
  1971. const struct sde_sspp_sub_blks *sblk;
  1972. struct sde_hw_inline_pre_downscale_cfg *pd;
  1973. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  1974. sblk = psde->pipe_sblk;
  1975. *max_numer_w = sblk->maxdwnscale;
  1976. *max_denom_w = 1;
  1977. *max_numer_h = sblk->maxdwnscale;
  1978. *max_denom_h = 1;
  1979. has_predown = _sde_plane_has_pre_downscale(psde);
  1980. if (has_predown)
  1981. pd = &pstate->pre_down;
  1982. default_scale = psde->debugfs_default_scale ||
  1983. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1984. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  1985. /**
  1986. * Inline rotation has different max vertical downscaling limits since
  1987. * the source-width becomes the scaler's pre-downscaled source-height.
  1988. **/
  1989. if (rotated) {
  1990. if (rt_client && has_predown) {
  1991. if (default_scale)
  1992. pd->pre_downscale_x_0 = (src_h >
  1993. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  1994. *max_numer_h = pd->pre_downscale_x_0 ?
  1995. sblk->in_rot_maxdwnscale_rt_num :
  1996. sblk->in_rot_maxdwnscale_rt_nopd_num;
  1997. *max_denom_h = pd->pre_downscale_x_0 ?
  1998. sblk->in_rot_maxdwnscale_rt_denom :
  1999. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2000. } else if (rt_client) {
  2001. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2002. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2003. } else {
  2004. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2005. }
  2006. }
  2007. }
  2008. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2009. struct sde_plane *psde, const struct sde_format *fmt,
  2010. struct sde_plane_state *pstate, struct sde_rect *src,
  2011. struct sde_rect *dst, u32 width, u32 height)
  2012. {
  2013. int ret = 0;
  2014. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2015. uint32_t scaler_src_w, scaler_src_h;
  2016. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2017. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2018. uint32_t max_upscale, max_linewidth;
  2019. bool inline_rotation, rt_client;
  2020. struct drm_crtc *crtc;
  2021. struct drm_crtc_state *new_cstate;
  2022. const struct sde_sspp_sub_blks *sblk;
  2023. if (!state || !state->state || !state->crtc) {
  2024. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2025. return -EINVAL;
  2026. }
  2027. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2028. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2029. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2030. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2031. /* with inline rotator, the source of the scaler is post-rotated */
  2032. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2033. if (inline_rotation) {
  2034. scaler_src_w = src_deci_h;
  2035. scaler_src_h = src_deci_w;
  2036. } else {
  2037. scaler_src_w = src_deci_w;
  2038. scaler_src_h = src_deci_h;
  2039. }
  2040. sblk = psde->pipe_sblk;
  2041. max_upscale = sblk->maxupscale;
  2042. if (inline_rotation)
  2043. max_linewidth = sblk->in_rot_maxheight;
  2044. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2045. max_linewidth = sblk->scaling_linewidth;
  2046. else
  2047. max_linewidth = sblk->maxlinewidth;
  2048. crtc = state->crtc;
  2049. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2050. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2051. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2052. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2053. &max_downscale_num_h, &max_downscale_denom_h);
  2054. /* decimation validation */
  2055. if ((deci_w || deci_h)
  2056. && ((deci_w > sblk->maxhdeciexp)
  2057. || (deci_h > sblk->maxvdeciexp))) {
  2058. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2059. ret = -EINVAL;
  2060. } else if ((deci_w || deci_h)
  2061. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2062. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2063. ret = -EINVAL;
  2064. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2065. ((src->w != dst->w) || (src->h != dst->h))) {
  2066. SDE_ERROR_PLANE(psde,
  2067. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2068. src->w, src->h, dst->w, dst->h);
  2069. ret = -EINVAL;
  2070. /* check scaler source width */
  2071. } else if (scaler_src_w > max_linewidth) {
  2072. SDE_ERROR_PLANE(psde,
  2073. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2074. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2075. ret = -E2BIG;
  2076. /* check max scaler capability */
  2077. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2078. ((scaler_src_h * max_upscale) < dst->h) ||
  2079. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2080. < scaler_src_w) ||
  2081. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2082. < scaler_src_h)) {
  2083. SDE_ERROR_PLANE(psde,
  2084. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2085. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2086. inline_rotation, max_downscale_num_w,
  2087. max_downscale_denom_w, max_downscale_num_h,
  2088. max_downscale_denom_h);
  2089. ret = -E2BIG;
  2090. /* check inline pre-downscale support */
  2091. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2092. pstate, dst, src_deci_w, src_deci_h)) {
  2093. ret = -EINVAL;
  2094. /* QSEED validation */
  2095. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2096. width, height, src->w, src->h,
  2097. deci_w, deci_h)) {
  2098. ret = -EINVAL;
  2099. }
  2100. return ret;
  2101. }
  2102. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2103. struct sde_plane_state *pstate, struct sde_rect *src,
  2104. const struct sde_format *fmt, int ret)
  2105. {
  2106. /* check excl rect configs */
  2107. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2108. struct sde_rect intersect;
  2109. /*
  2110. * Check exclusion rect against src rect.
  2111. * it must intersect with source rect.
  2112. */
  2113. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2114. if (intersect.w != pstate->excl_rect.w ||
  2115. intersect.h != pstate->excl_rect.h ||
  2116. SDE_FORMAT_IS_YUV(fmt)) {
  2117. SDE_ERROR_PLANE(psde,
  2118. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2119. pstate->excl_rect.x, pstate->excl_rect.y,
  2120. pstate->excl_rect.w, pstate->excl_rect.h,
  2121. src->x, src->y, src->w, src->h,
  2122. (char *)&fmt->base.pixel_format);
  2123. ret = -EINVAL;
  2124. }
  2125. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2126. pstate->excl_rect.x, pstate->excl_rect.y,
  2127. pstate->excl_rect.w, pstate->excl_rect.h);
  2128. }
  2129. return ret;
  2130. }
  2131. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2132. struct drm_plane_state *state)
  2133. {
  2134. struct sde_kms *sde_kms;
  2135. struct sde_splash_display *splash_display;
  2136. int i, j;
  2137. sde_kms = _sde_plane_get_kms(&psde->base);
  2138. if (!sde_kms || !state->crtc)
  2139. return 0;
  2140. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2141. splash_display = &sde_kms->splash_data.splash_display[i];
  2142. if (splash_display && splash_display->cont_splash_enabled &&
  2143. splash_display->encoder &&
  2144. state->crtc != splash_display->encoder->crtc) {
  2145. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2146. if (splash_display->pipes[j].sspp ==
  2147. psde->pipe) {
  2148. SDE_ERROR_PLANE(psde,
  2149. "pipe:%d used in cont-splash on crtc:%d\n",
  2150. psde->pipe,
  2151. splash_display->encoder->crtc->base.id);
  2152. return -EINVAL;
  2153. }
  2154. }
  2155. }
  2156. }
  2157. return 0;
  2158. }
  2159. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2160. const struct sde_format *fmt,
  2161. struct sde_rect src, struct sde_rect dst,
  2162. u32 width, u32 height)
  2163. {
  2164. int ret = 0;
  2165. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2166. if (SDE_FORMAT_IS_YUV(fmt) &&
  2167. (!(psde->features & SDE_SSPP_SCALER) ||
  2168. !(psde->features & (BIT(SDE_SSPP_CSC)
  2169. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2170. SDE_ERROR_PLANE(psde,
  2171. "plane doesn't have scaler/csc for yuv\n");
  2172. ret = -EINVAL;
  2173. /* check src bounds */
  2174. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2175. src.w < min_src_size || src.h < min_src_size ||
  2176. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2177. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2178. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2179. src.x, src.y, src.w, src.h);
  2180. ret = -E2BIG;
  2181. /* valid yuv image */
  2182. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2183. (src.w & 0x1) || (src.h & 0x1))) {
  2184. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2185. src.x, src.y, src.w, src.h);
  2186. ret = -EINVAL;
  2187. /* min dst support */
  2188. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2189. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2190. dst.x, dst.y, dst.w, dst.h);
  2191. ret = -EINVAL;
  2192. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2193. !psde->catalog->ubwc_version) {
  2194. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2195. ret = -EINVAL;
  2196. }
  2197. return ret;
  2198. }
  2199. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2200. struct drm_plane_state *state)
  2201. {
  2202. int ret = 0;
  2203. struct sde_plane *psde;
  2204. struct sde_plane_state *pstate;
  2205. const struct msm_format *msm_fmt;
  2206. const struct sde_format *fmt;
  2207. struct sde_rect src, dst;
  2208. bool q16_data = true;
  2209. struct drm_framebuffer *fb;
  2210. u32 width;
  2211. u32 height;
  2212. psde = to_sde_plane(plane);
  2213. pstate = to_sde_plane_state(state);
  2214. if (!psde->pipe_sblk) {
  2215. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2216. return -EINVAL;
  2217. }
  2218. /* src values are in Q16 fixed point, convert to integer */
  2219. POPULATE_RECT(&src, state->src_x, state->src_y,
  2220. state->src_w, state->src_h, q16_data);
  2221. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2222. state->crtc_h, !q16_data);
  2223. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2224. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2225. if (!sde_plane_enabled(state))
  2226. goto modeset_update;
  2227. fb = state->fb;
  2228. width = fb ? state->fb->width : 0x0;
  2229. height = fb ? state->fb->height : 0x0;
  2230. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2231. plane->base.id,
  2232. pstate->rotation,
  2233. width, height,
  2234. fb ? (char *) &state->fb->format->format : 0x0,
  2235. fb ? state->fb->modifier : 0x0);
  2236. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2237. state->src_w >> 16, state->src_h >> 16,
  2238. state->src_x >> 16, state->src_y >> 16,
  2239. state->crtc_w, state->crtc_h,
  2240. state->crtc_x, state->crtc_y);
  2241. msm_fmt = msm_framebuffer_format(fb);
  2242. fmt = to_sde_format(msm_fmt);
  2243. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2244. height);
  2245. if (ret)
  2246. return ret;
  2247. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2248. &src, &dst, width, height);
  2249. if (ret)
  2250. return ret;
  2251. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2252. &src, fmt, ret);
  2253. if (ret)
  2254. return ret;
  2255. ret = _sde_plane_validate_shared_crtc(psde, state);
  2256. if (ret)
  2257. return ret;
  2258. pstate->const_alpha_en = fmt->alpha_enable &&
  2259. (SDE_DRM_BLEND_OP_OPAQUE !=
  2260. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2261. (pstate->stage != SDE_STAGE_0);
  2262. modeset_update:
  2263. if (!ret)
  2264. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2265. state, plane->state);
  2266. return ret;
  2267. }
  2268. static int sde_plane_atomic_check(struct drm_plane *plane,
  2269. struct drm_plane_state *state)
  2270. {
  2271. int ret = 0;
  2272. struct sde_plane *psde;
  2273. struct sde_plane_state *pstate;
  2274. if (!plane || !state) {
  2275. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2276. !plane, !state);
  2277. ret = -EINVAL;
  2278. goto exit;
  2279. }
  2280. psde = to_sde_plane(plane);
  2281. pstate = to_sde_plane_state(state);
  2282. SDE_DEBUG_PLANE(psde, "\n");
  2283. ret = sde_plane_rot_atomic_check(plane, state);
  2284. if (ret)
  2285. goto exit;
  2286. ret = sde_plane_sspp_atomic_check(plane, state);
  2287. exit:
  2288. return ret;
  2289. }
  2290. void sde_plane_flush(struct drm_plane *plane)
  2291. {
  2292. struct sde_plane *psde;
  2293. struct sde_plane_state *pstate;
  2294. if (!plane || !plane->state) {
  2295. SDE_ERROR("invalid plane\n");
  2296. return;
  2297. }
  2298. psde = to_sde_plane(plane);
  2299. pstate = to_sde_plane_state(plane->state);
  2300. /*
  2301. * These updates have to be done immediately before the plane flush
  2302. * timing, and may not be moved to the atomic_update/mode_set functions.
  2303. */
  2304. if (psde->is_error)
  2305. /* force white frame with 100% alpha pipe output on error */
  2306. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2307. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2308. /* force 100% alpha */
  2309. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2310. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2311. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2312. /* flag h/w flush complete */
  2313. if (plane->state)
  2314. pstate->pending = false;
  2315. }
  2316. /**
  2317. * sde_plane_set_error: enable/disable error condition
  2318. * @plane: pointer to drm_plane structure
  2319. */
  2320. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2321. {
  2322. struct sde_plane *psde;
  2323. if (!plane)
  2324. return;
  2325. psde = to_sde_plane(plane);
  2326. psde->is_error = error;
  2327. }
  2328. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2329. struct sde_plane_state *pstate, bool is_tp10)
  2330. {
  2331. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2332. bool prev_rd_en;
  2333. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2334. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2335. return;
  2336. prev_rd_en = pstate->sc_cfg.rd_en;
  2337. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2338. psde->features, pstate->rotation);
  2339. pstate->sc_cfg.rd_en = false;
  2340. pstate->sc_cfg.rd_scid = 0x0;
  2341. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2342. SSPP_SYS_CACHE_SCID;
  2343. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2344. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2345. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2346. pstate->sc_cfg.rd_en = true;
  2347. pstate->sc_cfg.rd_scid =
  2348. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2349. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2350. SSPP_SYS_CACHE_SCID;
  2351. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2352. }
  2353. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2354. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2355. pstate->sc_cfg.rd_en = true;
  2356. pstate->sc_cfg.rd_scid =
  2357. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2358. pstate->sc_cfg.rd_noallocate = false;
  2359. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2360. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2361. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2362. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2363. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2364. pstate->sc_cfg.rd_en = true;
  2365. pstate->sc_cfg.rd_scid =
  2366. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2367. pstate->sc_cfg.rd_noallocate = true;
  2368. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2369. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2370. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2371. }
  2372. if (!pstate->sc_cfg.rd_en && !prev_rd_en)
  2373. return;
  2374. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2375. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2376. psde->pipe_hw->ops.setup_sys_cache(
  2377. psde->pipe_hw, &pstate->sc_cfg);
  2378. }
  2379. void sde_plane_static_img_control(struct drm_plane *plane,
  2380. enum sde_crtc_cache_state state)
  2381. {
  2382. struct sde_plane *psde;
  2383. struct sde_plane_state *pstate;
  2384. if (!plane || !plane->state) {
  2385. SDE_ERROR("invalid plane\n");
  2386. return;
  2387. }
  2388. psde = to_sde_plane(plane);
  2389. pstate = to_sde_plane_state(plane->state);
  2390. pstate->static_cache_state = state;
  2391. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2392. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2393. }
  2394. static void _sde_plane_map_prop_to_dirty_bits(void)
  2395. {
  2396. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2397. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2398. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2399. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2400. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2401. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2402. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2403. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2404. plane_prop_array[PLANE_PROP_ZPOS] =
  2405. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2406. SDE_PLANE_DIRTY_RECTS;
  2407. plane_prop_array[PLANE_PROP_CSC_V1] =
  2408. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2409. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2410. SDE_PLANE_DIRTY_FORMAT;
  2411. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2412. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2413. SDE_PLANE_DIRTY_ALL;
  2414. /* no special action required */
  2415. plane_prop_array[PLANE_PROP_INFO] =
  2416. plane_prop_array[PLANE_PROP_ALPHA] =
  2417. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2418. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2419. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2420. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2421. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2422. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2423. SDE_PLANE_DIRTY_PERF;
  2424. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2425. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2426. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2427. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2428. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2429. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2430. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2431. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2432. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2433. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2434. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2435. SDE_PLANE_DIRTY_ALL;
  2436. }
  2437. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2438. struct sde_rect *src, struct sde_rect *dst)
  2439. {
  2440. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2441. u32 downscale = (src->h * 1000)/dst->h;
  2442. return (downscale > max_downscale) ? false : true;
  2443. }
  2444. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2445. struct sde_plane *psde, struct sde_plane_state *pstate,
  2446. struct sde_rect *src, struct sde_rect *dst)
  2447. {
  2448. struct sde_hw_pipe_uidle_cfg cfg;
  2449. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2450. u32 fal1_threshold_max = 15;
  2451. u32 line_time = sde_get_linetime(&crtc->mode,
  2452. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2453. u32 fal1_target_idle_time_ns =
  2454. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2455. u32 fal10_target_idle_time_ns =
  2456. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2457. u32 fal10_threshold =
  2458. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2459. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2460. fal1_target_idle_time_ns) {
  2461. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2462. cfg.fal10_threshold = fal10_threshold;
  2463. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2464. cfg.fal1_threshold = min(1 +
  2465. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2466. fal1_threshold_max);
  2467. cfg.fal_allowed_threshold = fal10_threshold +
  2468. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2469. } else {
  2470. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2471. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2472. fal1_target_idle_time_ns);
  2473. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2474. }
  2475. SDE_DEBUG_PLANE(psde,
  2476. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2477. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2478. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2479. SDE_DEBUG_PLANE(psde,
  2480. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2481. line_time, fal1_target_idle_time_ns,
  2482. fal10_target_idle_time_ns,
  2483. psde->catalog->uidle_cfg.max_dwnscale);
  2484. SDE_EVT32_VERBOSE(cfg.enable,
  2485. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2486. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2487. psde->catalog->uidle_cfg.max_dwnscale);
  2488. psde->pipe_hw->ops.setup_uidle(
  2489. psde->pipe_hw, &cfg,
  2490. pstate->multirect_index);
  2491. }
  2492. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2493. struct sde_plane_state *pstate)
  2494. {
  2495. bool enable = false;
  2496. int mode = sde_plane_get_property(pstate,
  2497. PLANE_PROP_FB_TRANSLATION_MODE);
  2498. if ((mode == SDE_DRM_FB_SEC) ||
  2499. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2500. enable = true;
  2501. /* update secure session flag */
  2502. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2503. pstate->multirect_index,
  2504. enable);
  2505. }
  2506. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2507. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2508. {
  2509. const struct sde_format *fmt;
  2510. const struct msm_format *msm_fmt;
  2511. struct sde_plane *psde;
  2512. struct drm_plane_state *state;
  2513. struct sde_plane_state *pstate;
  2514. struct sde_rect src, dst;
  2515. const struct sde_rect *crtc_roi;
  2516. bool q16_data = true;
  2517. int idx;
  2518. psde = to_sde_plane(plane);
  2519. state = plane->state;
  2520. pstate = to_sde_plane_state(state);
  2521. msm_fmt = msm_framebuffer_format(fb);
  2522. if (!msm_fmt) {
  2523. SDE_ERROR("crtc%d plane%d: null format\n",
  2524. DRMID(crtc), DRMID(plane));
  2525. return;
  2526. }
  2527. fmt = to_sde_format(msm_fmt);
  2528. POPULATE_RECT(&src, state->src_x, state->src_y,
  2529. state->src_w, state->src_h, q16_data);
  2530. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2531. state->crtc_w, state->crtc_h, !q16_data);
  2532. SDE_DEBUG_PLANE(psde,
  2533. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2534. fb->base.id, src.x, src.y, src.w, src.h,
  2535. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2536. (char *)&fmt->base.pixel_format,
  2537. SDE_FORMAT_IS_UBWC(fmt));
  2538. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2539. BIT(SDE_DRM_DEINTERLACE)) {
  2540. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2541. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2542. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2543. src.h /= 2;
  2544. src.y = DIV_ROUND_UP(src.y, 2);
  2545. src.y &= ~0x1;
  2546. }
  2547. /*
  2548. * adjust layer mixer position of the sspp in the presence
  2549. * of a partial update to the active lm origin
  2550. */
  2551. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2552. dst.x -= crtc_roi->x;
  2553. dst.y -= crtc_roi->y;
  2554. /* check for UIDLE */
  2555. if (psde->pipe_hw->ops.setup_uidle)
  2556. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2557. psde->pipe_cfg.src_rect = src;
  2558. psde->pipe_cfg.dst_rect = dst;
  2559. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2560. /* check for color fill */
  2561. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2562. PLANE_PROP_COLOR_FILL);
  2563. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2564. /* skip remaining processing on color fill */
  2565. pstate->dirty = 0x0;
  2566. } else if (psde->pipe_hw->ops.setup_rects) {
  2567. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2568. &psde->pipe_cfg,
  2569. pstate->multirect_index);
  2570. }
  2571. if (psde->pipe_hw->ops.setup_pe &&
  2572. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2573. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2574. &pstate->pixel_ext);
  2575. /**
  2576. * when programmed in multirect mode, scalar block will be
  2577. * bypassed. Still we need to update alpha and bitwidth
  2578. * ONLY for RECT0
  2579. */
  2580. if (psde->pipe_hw->ops.setup_scaler &&
  2581. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2582. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2583. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2584. &psde->pipe_cfg, &pstate->pixel_ext,
  2585. &pstate->scaler3_cfg);
  2586. }
  2587. /* update excl rect */
  2588. if (psde->pipe_hw->ops.setup_excl_rect)
  2589. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2590. &pstate->excl_rect,
  2591. pstate->multirect_index);
  2592. /* enable multirect config of corresponding rect */
  2593. if (psde->pipe_hw->ops.update_multirect)
  2594. psde->pipe_hw->ops.update_multirect(
  2595. psde->pipe_hw,
  2596. true,
  2597. pstate->multirect_index,
  2598. pstate->multirect_mode);
  2599. }
  2600. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2601. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2602. {
  2603. uint32_t src_flags = 0;
  2604. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2605. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2606. src_flags |= SDE_SSPP_FLIP_LR;
  2607. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2608. src_flags |= SDE_SSPP_FLIP_UD;
  2609. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2610. src_flags |= SDE_SSPP_ROT_90;
  2611. /* update format */
  2612. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2613. pstate->const_alpha_en, src_flags,
  2614. pstate->multirect_index);
  2615. if (psde->pipe_hw->ops.setup_cdp) {
  2616. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2617. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2618. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2619. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2620. cdp_cfg->ubwc_meta_enable =
  2621. SDE_FORMAT_IS_UBWC(fmt);
  2622. cdp_cfg->tile_amortize_enable =
  2623. SDE_FORMAT_IS_UBWC(fmt) ||
  2624. SDE_FORMAT_IS_TILE(fmt);
  2625. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2626. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2627. pstate->multirect_index);
  2628. }
  2629. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2630. sde_format_is_tp10_ubwc(fmt));
  2631. /* update csc */
  2632. if (SDE_FORMAT_IS_YUV(fmt))
  2633. _sde_plane_setup_csc(psde);
  2634. else
  2635. psde->csc_ptr = 0;
  2636. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2637. uint32_t pma_mode = 0;
  2638. if (fmt->alpha_enable)
  2639. pma_mode = (uint32_t) sde_plane_get_property(
  2640. pstate, PLANE_PROP_INVERSE_PMA);
  2641. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2642. pstate->multirect_index, pma_mode);
  2643. }
  2644. if (psde->pipe_hw->ops.setup_dgm_csc)
  2645. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2646. pstate->multirect_index, psde->csc_usr_ptr);
  2647. }
  2648. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2649. {
  2650. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2651. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2652. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2653. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2654. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2655. &psde->sharp_cfg);
  2656. }
  2657. static void _sde_plane_update_properties(struct drm_plane *plane,
  2658. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2659. {
  2660. uint32_t nplanes;
  2661. const struct msm_format *msm_fmt;
  2662. const struct sde_format *fmt;
  2663. struct sde_plane *psde;
  2664. struct drm_plane_state *state;
  2665. struct sde_plane_state *pstate;
  2666. psde = to_sde_plane(plane);
  2667. state = plane->state;
  2668. pstate = to_sde_plane_state(state);
  2669. if (!pstate) {
  2670. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2671. return;
  2672. }
  2673. msm_fmt = msm_framebuffer_format(fb);
  2674. if (!msm_fmt) {
  2675. SDE_ERROR("crtc%d plane%d: null format\n",
  2676. DRMID(crtc), DRMID(plane));
  2677. return;
  2678. }
  2679. fmt = to_sde_format(msm_fmt);
  2680. nplanes = fmt->num_planes;
  2681. /* update secure session flag */
  2682. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2683. _sde_plane_update_secure_session(psde, pstate);
  2684. /* update roi config */
  2685. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2686. _sde_plane_update_roi_config(plane, crtc, fb);
  2687. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2688. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2689. psde->pipe_hw->ops.setup_format)
  2690. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2691. sde_color_process_plane_setup(plane);
  2692. /* update sharpening */
  2693. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2694. psde->pipe_hw->ops.setup_sharpening)
  2695. _sde_plane_update_sharpening(psde);
  2696. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2697. SDE_PLANE_DIRTY_FORMAT))
  2698. _sde_plane_set_qos_lut(plane, crtc, fb);
  2699. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2700. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2701. _sde_plane_set_ot_limit(plane, crtc);
  2702. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2703. _sde_plane_set_ts_prefill(plane, pstate);
  2704. }
  2705. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2706. _sde_plane_set_qos_remap(plane);
  2707. /* clear dirty */
  2708. pstate->dirty = 0x0;
  2709. }
  2710. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2711. struct drm_plane_state *old_state)
  2712. {
  2713. struct sde_plane *psde;
  2714. struct drm_plane_state *state;
  2715. struct sde_plane_state *pstate;
  2716. struct sde_plane_state *old_pstate;
  2717. struct drm_crtc *crtc;
  2718. struct drm_framebuffer *fb;
  2719. int idx;
  2720. int dirty_prop_flag;
  2721. bool is_rt;
  2722. if (!plane) {
  2723. SDE_ERROR("invalid plane\n");
  2724. return -EINVAL;
  2725. } else if (!plane->state) {
  2726. SDE_ERROR("invalid plane state\n");
  2727. return -EINVAL;
  2728. } else if (!old_state) {
  2729. SDE_ERROR("invalid old state\n");
  2730. return -EINVAL;
  2731. }
  2732. psde = to_sde_plane(plane);
  2733. state = plane->state;
  2734. pstate = to_sde_plane_state(state);
  2735. old_pstate = to_sde_plane_state(old_state);
  2736. crtc = state->crtc;
  2737. fb = state->fb;
  2738. if (!crtc || !fb) {
  2739. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2740. !crtc, !fb);
  2741. return -EINVAL;
  2742. }
  2743. SDE_DEBUG(
  2744. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2745. plane->base.id,
  2746. state->fb->width, state->fb->height,
  2747. (char *) &state->fb->format->format,
  2748. state->fb->modifier,
  2749. state->src_w >> 16, state->src_h >> 16,
  2750. state->src_x >> 16, state->src_y >> 16,
  2751. pstate->rotation,
  2752. state->crtc_w, state->crtc_h,
  2753. state->crtc_x, state->crtc_y);
  2754. /* force reprogramming of all the parameters, if the flag is set */
  2755. if (psde->revalidate) {
  2756. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2757. plane->base.id);
  2758. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2759. psde->revalidate = false;
  2760. }
  2761. /* determine what needs to be refreshed */
  2762. mutex_lock(&psde->property_info.property_lock);
  2763. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2764. &pstate->property_state)) >= 0) {
  2765. dirty_prop_flag = plane_prop_array[idx];
  2766. pstate->dirty |= dirty_prop_flag;
  2767. }
  2768. mutex_unlock(&psde->property_info.property_lock);
  2769. /**
  2770. * since plane_atomic_check is invoked before crtc_atomic_check
  2771. * in the commit sequence, all the parameters for updating the
  2772. * plane dirty flag will not be available during
  2773. * plane_atomic_check as some features params are updated
  2774. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2775. * before sspp update.
  2776. */
  2777. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2778. old_state);
  2779. /* re-program the output rects always if partial update roi changed */
  2780. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2781. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2782. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2783. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2784. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2785. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2786. if (is_rt != psde->is_rt_pipe) {
  2787. psde->is_rt_pipe = is_rt;
  2788. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2789. }
  2790. /* early out if nothing dirty */
  2791. if (!pstate->dirty)
  2792. return 0;
  2793. pstate->pending = true;
  2794. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2795. _sde_plane_update_properties(plane, crtc, fb);
  2796. return 0;
  2797. }
  2798. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2799. struct drm_plane_state *old_state)
  2800. {
  2801. struct sde_plane *psde;
  2802. struct drm_plane_state *state;
  2803. struct sde_plane_state *pstate;
  2804. u32 multirect_index = SDE_SSPP_RECT_0;
  2805. if (!plane) {
  2806. SDE_ERROR("invalid plane\n");
  2807. return;
  2808. } else if (!plane->state) {
  2809. SDE_ERROR("invalid plane state\n");
  2810. return;
  2811. } else if (!old_state) {
  2812. SDE_ERROR("invalid old state\n");
  2813. return;
  2814. }
  2815. psde = to_sde_plane(plane);
  2816. state = plane->state;
  2817. pstate = to_sde_plane_state(state);
  2818. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2819. pstate->multirect_mode);
  2820. pstate->pending = true;
  2821. if (is_sde_plane_virtual(plane))
  2822. multirect_index = SDE_SSPP_RECT_1;
  2823. /* disable multirect config of corresponding rect */
  2824. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2825. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2826. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2827. }
  2828. static void sde_plane_atomic_update(struct drm_plane *plane,
  2829. struct drm_plane_state *old_state)
  2830. {
  2831. struct sde_plane *psde;
  2832. struct drm_plane_state *state;
  2833. if (!plane) {
  2834. SDE_ERROR("invalid plane\n");
  2835. return;
  2836. } else if (!plane->state) {
  2837. SDE_ERROR("invalid plane state\n");
  2838. return;
  2839. }
  2840. psde = to_sde_plane(plane);
  2841. psde->is_error = false;
  2842. state = plane->state;
  2843. SDE_DEBUG_PLANE(psde, "\n");
  2844. if (!sde_plane_enabled(state)) {
  2845. _sde_plane_atomic_disable(plane, old_state);
  2846. } else {
  2847. int ret;
  2848. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2849. /* atomic_check should have ensured that this doesn't fail */
  2850. WARN_ON(ret < 0);
  2851. }
  2852. }
  2853. void sde_plane_restore(struct drm_plane *plane)
  2854. {
  2855. struct sde_plane *psde;
  2856. if (!plane || !plane->state) {
  2857. SDE_ERROR("invalid plane\n");
  2858. return;
  2859. }
  2860. psde = to_sde_plane(plane);
  2861. /*
  2862. * Revalidate is only true here if idle PC occurred and
  2863. * there is no plane state update in current commit cycle.
  2864. */
  2865. if (!psde->revalidate)
  2866. return;
  2867. SDE_DEBUG_PLANE(psde, "\n");
  2868. /* last plane state is same as current state */
  2869. sde_plane_atomic_update(plane, plane->state);
  2870. }
  2871. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2872. enum sde_sys_cache_type type)
  2873. {
  2874. struct sde_plane_state *pstate;
  2875. if (!plane || !plane->state) {
  2876. SDE_ERROR("invalid plane\n");
  2877. return false;
  2878. }
  2879. pstate = to_sde_plane_state(plane->state);
  2880. /* check if llcc is required for the plane */
  2881. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2882. return true;
  2883. else
  2884. return false;
  2885. }
  2886. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2887. {
  2888. char feature_name[256];
  2889. if (psde->pipe_sblk->maxhdeciexp) {
  2890. msm_property_install_range(&psde->property_info,
  2891. "h_decimate", 0x0, 0,
  2892. psde->pipe_sblk->maxhdeciexp, 0,
  2893. PLANE_PROP_H_DECIMATE);
  2894. }
  2895. if (psde->pipe_sblk->maxvdeciexp) {
  2896. msm_property_install_range(&psde->property_info,
  2897. "v_decimate", 0x0, 0,
  2898. psde->pipe_sblk->maxvdeciexp, 0,
  2899. PLANE_PROP_V_DECIMATE);
  2900. }
  2901. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2902. msm_property_install_range(
  2903. &psde->property_info, "scaler_v2",
  2904. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2905. msm_property_install_blob(&psde->property_info,
  2906. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2907. msm_property_install_blob(&psde->property_info,
  2908. "lut_cir", 0,
  2909. PLANE_PROP_SCALER_LUT_CIR);
  2910. msm_property_install_blob(&psde->property_info,
  2911. "lut_sep", 0,
  2912. PLANE_PROP_SCALER_LUT_SEP);
  2913. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2914. msm_property_install_range(
  2915. &psde->property_info, "scaler_v2",
  2916. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2917. msm_property_install_blob(&psde->property_info,
  2918. "lut_sep", 0,
  2919. PLANE_PROP_SCALER_LUT_SEP);
  2920. } else if (psde->features & SDE_SSPP_SCALER) {
  2921. msm_property_install_range(
  2922. &psde->property_info, "scaler_v1", 0x0,
  2923. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2924. }
  2925. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2926. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2927. msm_property_install_volatile_range(
  2928. &psde->property_info, "csc_v1", 0x0,
  2929. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2930. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2931. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2932. "SDE_SSPP_HUE_V",
  2933. psde->pipe_sblk->hsic_blk.version >> 16);
  2934. msm_property_install_range(&psde->property_info,
  2935. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2936. PLANE_PROP_HUE_ADJUST);
  2937. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2938. "SDE_SSPP_SATURATION_V",
  2939. psde->pipe_sblk->hsic_blk.version >> 16);
  2940. msm_property_install_range(&psde->property_info,
  2941. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2942. PLANE_PROP_SATURATION_ADJUST);
  2943. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2944. "SDE_SSPP_VALUE_V",
  2945. psde->pipe_sblk->hsic_blk.version >> 16);
  2946. msm_property_install_range(&psde->property_info,
  2947. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2948. PLANE_PROP_VALUE_ADJUST);
  2949. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2950. "SDE_SSPP_CONTRAST_V",
  2951. psde->pipe_sblk->hsic_blk.version >> 16);
  2952. msm_property_install_range(&psde->property_info,
  2953. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2954. PLANE_PROP_CONTRAST_ADJUST);
  2955. }
  2956. }
  2957. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  2958. struct sde_kms_info *info)
  2959. {
  2960. char feature_name[256];
  2961. bool is_master = !psde->is_virtual;
  2962. if ((is_master &&
  2963. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  2964. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  2965. msm_property_install_range(&psde->property_info,
  2966. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  2967. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  2968. }
  2969. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  2970. msm_property_install_volatile_range(
  2971. &psde->property_info, "csc_dma_v1", 0x0,
  2972. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  2973. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  2974. }
  2975. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  2976. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2977. "SDE_SSPP_SKIN_COLOR_V",
  2978. psde->pipe_sblk->memcolor_blk.version >> 16);
  2979. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2980. PLANE_PROP_SKIN_COLOR);
  2981. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2982. "SDE_SSPP_SKY_COLOR_V",
  2983. psde->pipe_sblk->memcolor_blk.version >> 16);
  2984. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2985. PLANE_PROP_SKY_COLOR);
  2986. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2987. "SDE_SSPP_FOLIAGE_COLOR_V",
  2988. psde->pipe_sblk->memcolor_blk.version >> 16);
  2989. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2990. PLANE_PROP_FOLIAGE_COLOR);
  2991. }
  2992. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  2993. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2994. "SDE_VIG_3D_LUT_GAMUT_V",
  2995. psde->pipe_sblk->gamut_blk.version >> 16);
  2996. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2997. PLANE_PROP_VIG_GAMUT);
  2998. }
  2999. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3000. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3001. "SDE_VIG_1D_LUT_IGC_V",
  3002. psde->pipe_sblk->igc_blk[0].version >> 16);
  3003. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3004. PLANE_PROP_VIG_IGC);
  3005. }
  3006. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3007. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3008. "SDE_DGM_1D_LUT_IGC_V",
  3009. psde->pipe_sblk->igc_blk[0].version >> 16);
  3010. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3011. PLANE_PROP_DMA_IGC);
  3012. }
  3013. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3014. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3015. "SDE_DGM_1D_LUT_GC_V",
  3016. psde->pipe_sblk->gc_blk[0].version >> 16);
  3017. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3018. PLANE_PROP_DMA_GC);
  3019. }
  3020. }
  3021. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3022. u32 master_plane_id, struct sde_kms_info *info,
  3023. struct sde_mdss_cfg *catalog)
  3024. {
  3025. bool is_master = !psde->is_virtual;
  3026. const struct sde_format_extended *format_list;
  3027. u32 index;
  3028. if (is_master) {
  3029. format_list = psde->pipe_sblk->format_list;
  3030. } else {
  3031. format_list = psde->pipe_sblk->virt_format_list;
  3032. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3033. master_plane_id);
  3034. }
  3035. if (format_list) {
  3036. sde_kms_info_start(info, "pixel_formats");
  3037. while (format_list->fourcc_format) {
  3038. sde_kms_info_append_format(info,
  3039. format_list->fourcc_format,
  3040. format_list->modifier);
  3041. ++format_list;
  3042. }
  3043. sde_kms_info_stop(info);
  3044. }
  3045. if (psde->pipe_hw && catalog->qseed_hw_version)
  3046. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3047. catalog->qseed_hw_version);
  3048. sde_kms_info_add_keyint(info, "max_linewidth",
  3049. psde->pipe_sblk->maxlinewidth);
  3050. sde_kms_info_add_keyint(info, "max_upscale",
  3051. psde->pipe_sblk->maxupscale);
  3052. sde_kms_info_add_keyint(info, "max_downscale",
  3053. psde->pipe_sblk->maxdwnscale);
  3054. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3055. psde->pipe_sblk->maxhdeciexp);
  3056. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3057. psde->pipe_sblk->maxvdeciexp);
  3058. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3059. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3060. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3061. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3062. index = (master_plane_id == 0) ? 0 : 1;
  3063. if (catalog->has_demura &&
  3064. catalog->demura_supported[psde->pipe][index] != ~0x0) {
  3065. sde_kms_info_add_keyint(info, "demura_block", index);
  3066. sde_kms_info_add_keyint(info, "demura_pipe_id",
  3067. psde->pipe - SSPP_DMA0);
  3068. }
  3069. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3070. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3071. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3072. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3073. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3074. const struct sde_format_extended *inline_rot_fmt_list;
  3075. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3076. catalog->true_inline_rot_rev);
  3077. sde_kms_info_add_keyint(info,
  3078. "true_inline_dwnscale_rt",
  3079. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3080. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3081. sde_kms_info_add_keyint(info,
  3082. "true_inline_dwnscale_rt_numerator",
  3083. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3084. sde_kms_info_add_keyint(info,
  3085. "true_inline_dwnscale_rt_denominator",
  3086. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3087. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3088. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3089. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3090. psde->pipe_sblk->in_rot_maxheight);
  3091. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3092. if (inline_rot_fmt_list) {
  3093. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3094. while (inline_rot_fmt_list->fourcc_format) {
  3095. sde_kms_info_append_format(info,
  3096. inline_rot_fmt_list->fourcc_format,
  3097. inline_rot_fmt_list->modifier);
  3098. ++inline_rot_fmt_list;
  3099. }
  3100. sde_kms_info_stop(info);
  3101. }
  3102. }
  3103. }
  3104. /* helper to install properties which are common to planes and crtcs */
  3105. static void _sde_plane_install_properties(struct drm_plane *plane,
  3106. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3107. {
  3108. static const struct drm_prop_enum_list e_blend_op[] = {
  3109. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3110. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3111. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3112. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3113. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3114. };
  3115. static const struct drm_prop_enum_list e_src_config[] = {
  3116. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3117. };
  3118. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3119. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3120. {SDE_DRM_FB_SEC, "sec"},
  3121. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3122. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3123. };
  3124. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3125. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3126. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3127. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3128. };
  3129. struct sde_kms_info *info;
  3130. struct sde_plane *psde = to_sde_plane(plane);
  3131. bool is_master;
  3132. int zpos_max = 255;
  3133. int zpos_def = 0;
  3134. if (!plane || !psde) {
  3135. SDE_ERROR("invalid plane\n");
  3136. return;
  3137. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3138. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3139. !psde->pipe_hw, !psde->pipe_sblk);
  3140. return;
  3141. } else if (!catalog) {
  3142. SDE_ERROR("invalid catalog\n");
  3143. return;
  3144. }
  3145. psde->catalog = catalog;
  3146. is_master = !psde->is_virtual;
  3147. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3148. if (!info) {
  3149. SDE_ERROR("failed to allocate info memory\n");
  3150. return;
  3151. }
  3152. if (sde_is_custom_client()) {
  3153. if (catalog->mixer_count &&
  3154. catalog->mixer[0].sblk->maxblendstages) {
  3155. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3156. if (catalog->has_base_layer &&
  3157. (zpos_max > SDE_STAGE_MAX - 1))
  3158. zpos_max = SDE_STAGE_MAX - 1;
  3159. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3160. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3161. }
  3162. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3163. /* reserve zpos == 0 for primary planes */
  3164. zpos_def = drm_plane_index(plane) + 1;
  3165. }
  3166. msm_property_install_range(&psde->property_info, "zpos",
  3167. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3168. msm_property_install_range(&psde->property_info, "alpha",
  3169. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3170. /* linux default file descriptor range on each process */
  3171. msm_property_install_range(&psde->property_info, "input_fence",
  3172. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3173. if (is_master)
  3174. _sde_plane_install_master_only_properties(psde);
  3175. else
  3176. msm_property_install_enum(&psde->property_info,
  3177. "multirect_mode", 0x0, 0, e_multirect_mode,
  3178. ARRAY_SIZE(e_multirect_mode), 0,
  3179. PLANE_PROP_MULTIRECT_MODE);
  3180. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3181. msm_property_install_volatile_range(&psde->property_info,
  3182. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3183. sde_plane_rot_install_properties(plane, catalog);
  3184. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3185. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3186. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3187. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3188. PLANE_PROP_SRC_CONFIG);
  3189. if (psde->pipe_hw->ops.setup_solidfill)
  3190. msm_property_install_range(&psde->property_info, "color_fill",
  3191. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3192. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3193. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3194. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3195. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3196. msm_property_install_blob(&psde->property_info, "capabilities",
  3197. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3198. sde_kms_info_reset(info);
  3199. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3200. catalog);
  3201. _sde_plane_install_colorproc_properties(psde, info);
  3202. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3203. info->data, SDE_KMS_INFO_DATALEN(info),
  3204. PLANE_PROP_INFO);
  3205. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3206. 0x0, 0, e_fb_translation_mode,
  3207. ARRAY_SIZE(e_fb_translation_mode), 0,
  3208. PLANE_PROP_FB_TRANSLATION_MODE);
  3209. kfree(info);
  3210. }
  3211. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3212. void __user *usr_ptr)
  3213. {
  3214. struct sde_drm_csc_v1 csc_v1;
  3215. int i;
  3216. if (!psde) {
  3217. SDE_ERROR("invalid plane\n");
  3218. return;
  3219. }
  3220. psde->csc_usr_ptr = NULL;
  3221. if (!usr_ptr) {
  3222. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3223. return;
  3224. }
  3225. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3226. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3227. return;
  3228. }
  3229. /* populate from user space */
  3230. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3231. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3232. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3233. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3234. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3235. }
  3236. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3237. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3238. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3239. }
  3240. psde->csc_usr_ptr = &psde->csc_cfg;
  3241. }
  3242. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3243. struct sde_plane_state *pstate, void __user *usr)
  3244. {
  3245. struct sde_drm_scaler_v1 scale_v1;
  3246. struct sde_hw_pixel_ext *pe;
  3247. int i;
  3248. if (!psde || !pstate) {
  3249. SDE_ERROR("invalid argument(s)\n");
  3250. return;
  3251. }
  3252. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3253. if (!usr) {
  3254. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3255. return;
  3256. }
  3257. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3258. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3259. return;
  3260. }
  3261. /* force property to be dirty, even if the pointer didn't change */
  3262. msm_property_set_dirty(&psde->property_info,
  3263. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3264. /* populate from user space */
  3265. pe = &pstate->pixel_ext;
  3266. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3267. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3268. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3269. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3270. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3271. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3272. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3273. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3274. }
  3275. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3276. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3277. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3278. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3279. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3280. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3281. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3282. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3283. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3284. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3285. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3286. }
  3287. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3288. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3289. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3290. }
  3291. static void _sde_plane_clear_predownscale_settings(
  3292. struct sde_plane_state *pstate)
  3293. {
  3294. pstate->pre_down.pre_downscale_x_0 = 0;
  3295. pstate->pre_down.pre_downscale_x_1 = 0;
  3296. pstate->pre_down.pre_downscale_y_0 = 0;
  3297. pstate->pre_down.pre_downscale_y_1 = 0;
  3298. }
  3299. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3300. struct sde_plane_state *pstate, void __user *usr)
  3301. {
  3302. struct sde_drm_scaler_v2 scale_v2;
  3303. struct sde_hw_pixel_ext *pe;
  3304. int i;
  3305. struct sde_hw_scaler3_cfg *cfg;
  3306. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3307. if (!psde || !pstate) {
  3308. SDE_ERROR("invalid argument(s)\n");
  3309. return;
  3310. }
  3311. cfg = &pstate->scaler3_cfg;
  3312. pd_cfg = &pstate->pre_down;
  3313. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3314. if (!usr) {
  3315. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3316. cfg->enable = 0;
  3317. _sde_plane_clear_predownscale_settings(pstate);
  3318. goto end;
  3319. }
  3320. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3321. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3322. return;
  3323. }
  3324. /* detach/ignore user data if 'disabled' */
  3325. if (!scale_v2.enable) {
  3326. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3327. cfg->enable = 0;
  3328. _sde_plane_clear_predownscale_settings(pstate);
  3329. goto end;
  3330. }
  3331. /* populate from user space */
  3332. sde_set_scaler_v2(cfg, &scale_v2);
  3333. if (_sde_plane_has_pre_downscale(psde)) {
  3334. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3335. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3336. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3337. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3338. }
  3339. pe = &pstate->pixel_ext;
  3340. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3341. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3342. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3343. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3344. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3345. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3346. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3347. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3348. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3349. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3350. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3351. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3352. }
  3353. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3354. end:
  3355. /* force property to be dirty, even if the pointer didn't change */
  3356. msm_property_set_dirty(&psde->property_info,
  3357. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3358. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3359. cfg->src_width[0], cfg->src_height[0],
  3360. cfg->dst_width, cfg->dst_height);
  3361. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3362. }
  3363. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3364. struct sde_plane_state *pstate, void __user *usr_ptr)
  3365. {
  3366. struct drm_clip_rect excl_rect_v1;
  3367. if (!psde || !pstate) {
  3368. SDE_ERROR("invalid argument(s)\n");
  3369. return;
  3370. }
  3371. if (!usr_ptr) {
  3372. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3373. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3374. return;
  3375. }
  3376. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3377. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3378. return;
  3379. }
  3380. /* populate from user space */
  3381. pstate->excl_rect.x = excl_rect_v1.x1;
  3382. pstate->excl_rect.y = excl_rect_v1.y1;
  3383. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3384. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3385. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3386. pstate->excl_rect.x, pstate->excl_rect.y,
  3387. pstate->excl_rect.w, pstate->excl_rect.h);
  3388. }
  3389. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3390. struct drm_plane_state *state, struct drm_property *property,
  3391. uint64_t val)
  3392. {
  3393. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3394. struct sde_plane_state *pstate;
  3395. int idx, ret = -EINVAL;
  3396. SDE_DEBUG_PLANE(psde, "\n");
  3397. if (!plane) {
  3398. SDE_ERROR("invalid plane\n");
  3399. } else if (!state) {
  3400. SDE_ERROR_PLANE(psde, "invalid state\n");
  3401. } else {
  3402. pstate = to_sde_plane_state(state);
  3403. ret = msm_property_atomic_set(&psde->property_info,
  3404. &pstate->property_state, property, val);
  3405. if (!ret) {
  3406. idx = msm_property_index(&psde->property_info,
  3407. property);
  3408. switch (idx) {
  3409. case PLANE_PROP_INPUT_FENCE:
  3410. _sde_plane_set_input_fence(psde, pstate, val);
  3411. break;
  3412. case PLANE_PROP_CSC_V1:
  3413. case PLANE_PROP_CSC_DMA_V1:
  3414. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3415. break;
  3416. case PLANE_PROP_SCALER_V1:
  3417. _sde_plane_set_scaler_v1(psde, pstate,
  3418. (void *)(uintptr_t)val);
  3419. break;
  3420. case PLANE_PROP_SCALER_V2:
  3421. _sde_plane_set_scaler_v2(psde, pstate,
  3422. (void *)(uintptr_t)val);
  3423. break;
  3424. case PLANE_PROP_EXCL_RECT_V1:
  3425. _sde_plane_set_excl_rect_v1(psde, pstate,
  3426. (void *)(uintptr_t)val);
  3427. break;
  3428. default:
  3429. /* nothing to do */
  3430. break;
  3431. }
  3432. }
  3433. }
  3434. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3435. property->name, property->base.id, val, ret);
  3436. return ret;
  3437. }
  3438. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3439. const struct drm_plane_state *state,
  3440. struct drm_property *property, uint64_t *val)
  3441. {
  3442. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3443. struct sde_plane_state *pstate;
  3444. int ret = -EINVAL;
  3445. if (!plane) {
  3446. SDE_ERROR("invalid plane\n");
  3447. } else if (!state) {
  3448. SDE_ERROR("invalid state\n");
  3449. } else {
  3450. SDE_DEBUG_PLANE(psde, "\n");
  3451. pstate = to_sde_plane_state(state);
  3452. ret = msm_property_atomic_get(&psde->property_info,
  3453. &pstate->property_state, property, val);
  3454. }
  3455. return ret;
  3456. }
  3457. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3458. struct drm_plane_state *plane_state)
  3459. {
  3460. struct sde_plane *psde;
  3461. struct sde_plane_state *pstate;
  3462. struct drm_property *drm_prop;
  3463. enum msm_mdp_plane_property prop_idx;
  3464. if (!plane || !plane_state) {
  3465. SDE_ERROR("invalid params\n");
  3466. return -EINVAL;
  3467. }
  3468. psde = to_sde_plane(plane);
  3469. pstate = to_sde_plane_state(plane_state);
  3470. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3471. uint64_t val = pstate->property_values[prop_idx].value;
  3472. uint64_t def;
  3473. int ret;
  3474. drm_prop = msm_property_index_to_drm_property(
  3475. &psde->property_info, prop_idx);
  3476. if (!drm_prop) {
  3477. /* not all props will be installed, based on caps */
  3478. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3479. prop_idx);
  3480. continue;
  3481. }
  3482. def = msm_property_get_default(&psde->property_info, prop_idx);
  3483. if (val == def)
  3484. continue;
  3485. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3486. drm_prop->name, prop_idx, val, def);
  3487. ret = sde_plane_atomic_set_property(plane, plane_state,
  3488. drm_prop, def);
  3489. if (ret) {
  3490. SDE_ERROR_PLANE(psde,
  3491. "set property failed, idx %d ret %d\n",
  3492. prop_idx, ret);
  3493. continue;
  3494. }
  3495. }
  3496. return 0;
  3497. }
  3498. static void sde_plane_destroy(struct drm_plane *plane)
  3499. {
  3500. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3501. SDE_DEBUG_PLANE(psde, "\n");
  3502. if (psde) {
  3503. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3504. if (psde->blob_info)
  3505. drm_property_blob_put(psde->blob_info);
  3506. msm_property_destroy(&psde->property_info);
  3507. mutex_destroy(&psde->lock);
  3508. /* this will destroy the states as well */
  3509. drm_plane_cleanup(plane);
  3510. if (psde->pipe_hw)
  3511. sde_hw_sspp_destroy(psde->pipe_hw);
  3512. kfree(psde);
  3513. }
  3514. }
  3515. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3516. {
  3517. struct sde_plane_state *pstate;
  3518. if (!state) {
  3519. SDE_ERROR("invalid arg state %d\n", !state);
  3520. return;
  3521. }
  3522. pstate = to_sde_plane_state(state);
  3523. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3524. SDE_DRM_FB_SEC) {
  3525. /* remove ref count for frame buffers */
  3526. if (state->fb) {
  3527. drm_framebuffer_put(state->fb);
  3528. state->fb = NULL;
  3529. }
  3530. }
  3531. }
  3532. static void sde_plane_destroy_state(struct drm_plane *plane,
  3533. struct drm_plane_state *state)
  3534. {
  3535. struct sde_plane *psde;
  3536. struct sde_plane_state *pstate;
  3537. if (!plane || !state) {
  3538. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3539. !plane, !state);
  3540. return;
  3541. }
  3542. psde = to_sde_plane(plane);
  3543. pstate = to_sde_plane_state(state);
  3544. SDE_DEBUG_PLANE(psde, "\n");
  3545. /* remove ref count for frame buffers */
  3546. if (state->fb)
  3547. drm_framebuffer_put(state->fb);
  3548. /* remove ref count for fence */
  3549. if (pstate->input_fence)
  3550. sde_sync_put(pstate->input_fence);
  3551. pstate->input_fence = 0;
  3552. /* destroy value helper */
  3553. msm_property_destroy_state(&psde->property_info, pstate,
  3554. &pstate->property_state);
  3555. }
  3556. static struct drm_plane_state *
  3557. sde_plane_duplicate_state(struct drm_plane *plane)
  3558. {
  3559. struct sde_plane *psde;
  3560. struct sde_plane_state *pstate;
  3561. struct sde_plane_state *old_state;
  3562. struct drm_property *drm_prop;
  3563. uint64_t input_fence_default;
  3564. if (!plane) {
  3565. SDE_ERROR("invalid plane\n");
  3566. return NULL;
  3567. } else if (!plane->state) {
  3568. SDE_ERROR("invalid plane state\n");
  3569. return NULL;
  3570. }
  3571. old_state = to_sde_plane_state(plane->state);
  3572. psde = to_sde_plane(plane);
  3573. pstate = msm_property_alloc_state(&psde->property_info);
  3574. if (!pstate) {
  3575. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3576. return NULL;
  3577. }
  3578. SDE_DEBUG_PLANE(psde, "\n");
  3579. /* duplicate value helper */
  3580. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3581. &pstate->property_state, pstate->property_values);
  3582. /* clear out any input fence */
  3583. pstate->input_fence = 0;
  3584. input_fence_default = msm_property_get_default(
  3585. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3586. drm_prop = msm_property_index_to_drm_property(
  3587. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3588. if (msm_property_atomic_set(&psde->property_info,
  3589. &pstate->property_state, drm_prop,
  3590. input_fence_default))
  3591. SDE_DEBUG_PLANE(psde,
  3592. "error clearing duplicated input fence\n");
  3593. pstate->dirty = 0x0;
  3594. pstate->pending = false;
  3595. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3596. /* reset layout offset */
  3597. if (pstate->layout_offset) {
  3598. if (pstate->layout_offset > 0)
  3599. pstate->base.crtc_x += pstate->layout_offset;
  3600. pstate->layout = SDE_LAYOUT_NONE;
  3601. pstate->layout_offset = 0;
  3602. }
  3603. return &pstate->base;
  3604. }
  3605. static void sde_plane_reset(struct drm_plane *plane)
  3606. {
  3607. struct sde_plane *psde;
  3608. struct sde_plane_state *pstate;
  3609. if (!plane) {
  3610. SDE_ERROR("invalid plane\n");
  3611. return;
  3612. }
  3613. psde = to_sde_plane(plane);
  3614. SDE_DEBUG_PLANE(psde, "\n");
  3615. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3616. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3617. return;
  3618. }
  3619. /* remove previous state, if present */
  3620. if (plane->state) {
  3621. sde_plane_destroy_state(plane, plane->state);
  3622. plane->state = 0;
  3623. }
  3624. pstate = msm_property_alloc_state(&psde->property_info);
  3625. if (!pstate) {
  3626. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3627. return;
  3628. }
  3629. /* reset value helper */
  3630. msm_property_reset_state(&psde->property_info, pstate,
  3631. &pstate->property_state,
  3632. pstate->property_values);
  3633. pstate->base.plane = plane;
  3634. plane->state = &pstate->base;
  3635. }
  3636. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3637. {
  3638. u32 ubwc_error = 0;
  3639. struct sde_plane *psde;
  3640. if (!plane) {
  3641. SDE_ERROR("invalid plane\n");
  3642. return 0;
  3643. }
  3644. psde = to_sde_plane(plane);
  3645. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3646. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
  3647. return ubwc_error;
  3648. }
  3649. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3650. {
  3651. struct sde_plane *psde;
  3652. if (!plane) {
  3653. SDE_ERROR("invalid plane\n");
  3654. return;
  3655. }
  3656. psde = to_sde_plane(plane);
  3657. if (psde->pipe_hw->ops.clear_ubwc_error)
  3658. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
  3659. }
  3660. #ifdef CONFIG_DEBUG_FS
  3661. static ssize_t _sde_plane_danger_read(struct file *file,
  3662. char __user *buff, size_t count, loff_t *ppos)
  3663. {
  3664. struct sde_kms *kms = file->private_data;
  3665. struct sde_mdss_cfg *cfg = kms->catalog;
  3666. int len = 0;
  3667. char buf[40] = {'\0'};
  3668. if (!cfg)
  3669. return -ENODEV;
  3670. if (*ppos)
  3671. return 0; /* the end */
  3672. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3673. if (len < 0 || len >= sizeof(buf))
  3674. return 0;
  3675. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3676. return -EFAULT;
  3677. *ppos += len; /* increase offset */
  3678. return len;
  3679. }
  3680. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3681. {
  3682. struct drm_plane *plane;
  3683. drm_for_each_plane(plane, kms->dev) {
  3684. if (plane->fb && plane->state) {
  3685. sde_plane_danger_signal_ctrl(plane, enable);
  3686. SDE_DEBUG("plane:%d img:%dx%d ",
  3687. plane->base.id, plane->fb->width,
  3688. plane->fb->height);
  3689. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3690. plane->state->src_x >> 16,
  3691. plane->state->src_y >> 16,
  3692. plane->state->src_w >> 16,
  3693. plane->state->src_h >> 16,
  3694. plane->state->crtc_x, plane->state->crtc_y,
  3695. plane->state->crtc_w, plane->state->crtc_h);
  3696. } else {
  3697. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3698. }
  3699. }
  3700. }
  3701. static ssize_t _sde_plane_danger_write(struct file *file,
  3702. const char __user *user_buf, size_t count, loff_t *ppos)
  3703. {
  3704. struct sde_kms *kms = file->private_data;
  3705. struct sde_mdss_cfg *cfg = kms->catalog;
  3706. int disable_panic;
  3707. char buf[10];
  3708. if (!cfg)
  3709. return -EFAULT;
  3710. if (count >= sizeof(buf))
  3711. return -EFAULT;
  3712. if (copy_from_user(buf, user_buf, count))
  3713. return -EFAULT;
  3714. buf[count] = 0; /* end of string */
  3715. if (kstrtoint(buf, 0, &disable_panic))
  3716. return -EFAULT;
  3717. if (disable_panic) {
  3718. /* Disable panic signal for all active pipes */
  3719. SDE_DEBUG("Disabling danger:\n");
  3720. _sde_plane_set_danger_state(kms, false);
  3721. kms->has_danger_ctrl = false;
  3722. } else {
  3723. /* Enable panic signal for all active pipes */
  3724. SDE_DEBUG("Enabling danger:\n");
  3725. kms->has_danger_ctrl = true;
  3726. _sde_plane_set_danger_state(kms, true);
  3727. }
  3728. return count;
  3729. }
  3730. static const struct file_operations sde_plane_danger_enable = {
  3731. .open = simple_open,
  3732. .read = _sde_plane_danger_read,
  3733. .write = _sde_plane_danger_write,
  3734. };
  3735. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3736. {
  3737. struct sde_plane *psde;
  3738. struct sde_kms *kms;
  3739. struct msm_drm_private *priv;
  3740. const struct sde_sspp_sub_blks *sblk = 0;
  3741. const struct sde_sspp_cfg *cfg = 0;
  3742. if (!plane || !plane->dev) {
  3743. SDE_ERROR("invalid arguments\n");
  3744. return -EINVAL;
  3745. }
  3746. priv = plane->dev->dev_private;
  3747. if (!priv || !priv->kms) {
  3748. SDE_ERROR("invalid KMS reference\n");
  3749. return -EINVAL;
  3750. }
  3751. kms = to_sde_kms(priv->kms);
  3752. psde = to_sde_plane(plane);
  3753. if (psde && psde->pipe_hw)
  3754. cfg = psde->pipe_hw->cap;
  3755. if (cfg)
  3756. sblk = cfg->sblk;
  3757. if (!sblk)
  3758. return 0;
  3759. /* create overall sub-directory for the pipe */
  3760. psde->debugfs_root =
  3761. debugfs_create_dir(psde->pipe_name,
  3762. plane->dev->primary->debugfs_root);
  3763. if (!psde->debugfs_root)
  3764. return -ENOMEM;
  3765. /* don't error check these */
  3766. debugfs_create_x32("features", 0400,
  3767. psde->debugfs_root, &psde->features);
  3768. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3769. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3770. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3771. debugfs_create_bool("default_scaling",
  3772. 0600,
  3773. psde->debugfs_root,
  3774. &psde->debugfs_default_scale);
  3775. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3776. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3777. 0600,
  3778. psde->debugfs_root,
  3779. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3780. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3781. 0600,
  3782. psde->debugfs_root,
  3783. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3784. debugfs_create_u32("in_rot_max_downscale_nrt",
  3785. 0600,
  3786. psde->debugfs_root,
  3787. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3788. debugfs_create_u32("in_rot_max_height",
  3789. 0600,
  3790. psde->debugfs_root,
  3791. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3792. }
  3793. debugfs_create_u32("xin_id",
  3794. 0400,
  3795. psde->debugfs_root,
  3796. (u32 *) &cfg->xin_id);
  3797. debugfs_create_x32("creq_vblank",
  3798. 0600,
  3799. psde->debugfs_root,
  3800. (u32 *) &sblk->creq_vblank);
  3801. debugfs_create_x32("danger_vblank",
  3802. 0600,
  3803. psde->debugfs_root,
  3804. (u32 *) &sblk->danger_vblank);
  3805. debugfs_create_file("disable_danger",
  3806. 0600,
  3807. psde->debugfs_root,
  3808. kms, &sde_plane_danger_enable);
  3809. return 0;
  3810. }
  3811. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3812. {
  3813. struct sde_plane *psde;
  3814. if (!plane)
  3815. return;
  3816. psde = to_sde_plane(plane);
  3817. debugfs_remove_recursive(psde->debugfs_root);
  3818. }
  3819. #else
  3820. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3821. {
  3822. return 0;
  3823. }
  3824. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3825. {
  3826. }
  3827. #endif
  3828. static int sde_plane_late_register(struct drm_plane *plane)
  3829. {
  3830. return _sde_plane_init_debugfs(plane);
  3831. }
  3832. static void sde_plane_early_unregister(struct drm_plane *plane)
  3833. {
  3834. _sde_plane_destroy_debugfs(plane);
  3835. }
  3836. static const struct drm_plane_funcs sde_plane_funcs = {
  3837. .update_plane = drm_atomic_helper_update_plane,
  3838. .disable_plane = drm_atomic_helper_disable_plane,
  3839. .destroy = sde_plane_destroy,
  3840. .atomic_set_property = sde_plane_atomic_set_property,
  3841. .atomic_get_property = sde_plane_atomic_get_property,
  3842. .reset = sde_plane_reset,
  3843. .atomic_duplicate_state = sde_plane_duplicate_state,
  3844. .atomic_destroy_state = sde_plane_destroy_state,
  3845. .late_register = sde_plane_late_register,
  3846. .early_unregister = sde_plane_early_unregister,
  3847. };
  3848. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3849. .prepare_fb = sde_plane_prepare_fb,
  3850. .cleanup_fb = sde_plane_cleanup_fb,
  3851. .atomic_check = sde_plane_atomic_check,
  3852. .atomic_update = sde_plane_atomic_update,
  3853. };
  3854. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3855. {
  3856. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3857. }
  3858. bool is_sde_plane_virtual(struct drm_plane *plane)
  3859. {
  3860. return plane ? to_sde_plane(plane)->is_virtual : false;
  3861. }
  3862. /* initialize plane */
  3863. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3864. uint32_t pipe, bool primary_plane,
  3865. unsigned long possible_crtcs, u32 master_plane_id)
  3866. {
  3867. struct drm_plane *plane = NULL, *master_plane = NULL;
  3868. const struct sde_format_extended *format_list;
  3869. struct sde_plane *psde;
  3870. struct msm_drm_private *priv;
  3871. struct sde_kms *kms;
  3872. enum drm_plane_type type;
  3873. int ret = -EINVAL;
  3874. if (!dev) {
  3875. SDE_ERROR("[%u]device is NULL\n", pipe);
  3876. goto exit;
  3877. }
  3878. priv = dev->dev_private;
  3879. if (!priv) {
  3880. SDE_ERROR("[%u]private data is NULL\n", pipe);
  3881. goto exit;
  3882. }
  3883. if (!priv->kms) {
  3884. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  3885. goto exit;
  3886. }
  3887. kms = to_sde_kms(priv->kms);
  3888. if (!kms->catalog) {
  3889. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  3890. goto exit;
  3891. }
  3892. /* create and zero local structure */
  3893. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  3894. if (!psde) {
  3895. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  3896. ret = -ENOMEM;
  3897. goto exit;
  3898. }
  3899. /* cache local stuff for later */
  3900. plane = &psde->base;
  3901. psde->pipe = pipe;
  3902. psde->is_virtual = (master_plane_id != 0);
  3903. INIT_LIST_HEAD(&psde->mplane_list);
  3904. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  3905. if (master_plane) {
  3906. struct sde_plane *mpsde = to_sde_plane(master_plane);
  3907. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  3908. }
  3909. /* initialize underlying h/w driver */
  3910. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  3911. psde->is_virtual);
  3912. if (IS_ERR(psde->pipe_hw)) {
  3913. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  3914. ret = PTR_ERR(psde->pipe_hw);
  3915. goto clean_plane;
  3916. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  3917. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  3918. goto clean_sspp;
  3919. }
  3920. /* cache features mask for later */
  3921. psde->features = psde->pipe_hw->cap->features;
  3922. psde->perf_features = psde->pipe_hw->cap->perf_features;
  3923. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  3924. if (!psde->pipe_sblk) {
  3925. SDE_ERROR("[%u]invalid sblk\n", pipe);
  3926. goto clean_sspp;
  3927. }
  3928. if (psde->is_virtual)
  3929. format_list = psde->pipe_sblk->virt_format_list;
  3930. else
  3931. format_list = psde->pipe_sblk->format_list;
  3932. psde->nformats = sde_populate_formats(format_list,
  3933. psde->formats,
  3934. 0,
  3935. ARRAY_SIZE(psde->formats));
  3936. if (!psde->nformats) {
  3937. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  3938. goto clean_sspp;
  3939. }
  3940. if (psde->features & BIT(SDE_SSPP_CURSOR))
  3941. type = DRM_PLANE_TYPE_CURSOR;
  3942. else if (primary_plane)
  3943. type = DRM_PLANE_TYPE_PRIMARY;
  3944. else
  3945. type = DRM_PLANE_TYPE_OVERLAY;
  3946. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  3947. psde->formats, psde->nformats,
  3948. NULL, type, NULL);
  3949. if (ret)
  3950. goto clean_sspp;
  3951. /* Populate static array of plane property flags */
  3952. _sde_plane_map_prop_to_dirty_bits();
  3953. /* success! finalize initialization */
  3954. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  3955. msm_property_init(&psde->property_info, &plane->base, dev,
  3956. priv->plane_property, psde->property_data,
  3957. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  3958. sizeof(struct sde_plane_state));
  3959. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  3960. /* save user friendly pipe name for later */
  3961. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  3962. mutex_init(&psde->lock);
  3963. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  3964. pipe, plane->base.id, master_plane_id);
  3965. return plane;
  3966. clean_sspp:
  3967. if (psde && psde->pipe_hw)
  3968. sde_hw_sspp_destroy(psde->pipe_hw);
  3969. clean_plane:
  3970. kfree(psde);
  3971. exit:
  3972. return ERR_PTR(ret);
  3973. }