hal_be_generic_api.h 53 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include <hal_be_api_mon.h>
  27. /**
  28. * hal_tx_comp_get_status() - TQM Release reason
  29. * @hal_desc: completion ring Tx status
  30. *
  31. * This function will parse the WBM completion descriptor and populate in
  32. * HAL structure
  33. *
  34. * Return: none
  35. */
  36. static inline void
  37. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  38. struct hal_soc *hal)
  39. {
  40. uint8_t rate_stats_valid = 0;
  41. uint32_t rate_stats = 0;
  42. struct hal_tx_completion_status *ts =
  43. (struct hal_tx_completion_status *)ts1;
  44. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  45. TQM_STATUS_NUMBER);
  46. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  47. ACK_FRAME_RSSI);
  48. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  49. FIRST_MSDU);
  50. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  51. LAST_MSDU);
  52. #if 0
  53. // TODO - This has to be calculated form first and last msdu
  54. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  55. WBM2SW_COMPLETION_RING_TX,
  56. MSDU_PART_OF_AMSDU);
  57. #endif
  58. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  59. SW_PEER_ID);
  60. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  61. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  62. TRANSMIT_COUNT);
  63. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  64. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  65. TX_RATE_STATS_INFO_VALID, rate_stats);
  66. ts->valid = rate_stats_valid;
  67. if (rate_stats_valid) {
  68. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  69. rate_stats);
  70. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  71. TRANSMIT_PKT_TYPE, rate_stats);
  72. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  73. TRANSMIT_STBC, rate_stats);
  74. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  75. rate_stats);
  76. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  77. rate_stats);
  78. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  79. rate_stats);
  80. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  81. rate_stats);
  82. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  83. rate_stats);
  84. }
  85. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  86. ts->status = hal_tx_comp_get_release_reason(
  87. desc,
  88. hal_soc_to_hal_soc_handle(hal));
  89. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  90. TX_RATE_STATS_INFO_TX_RATE_STATS);
  91. }
  92. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  93. /**
  94. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  95. * tlv_tag: Taf of the TLVs
  96. * rx_tlv: the pointer to the TLVs
  97. * @ppdu_info: pointer to ppdu_info
  98. *
  99. * Return: true if the tlv is handled, false if not
  100. */
  101. static inline bool
  102. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  103. struct hal_rx_ppdu_info *ppdu_info)
  104. {
  105. uint32_t value;
  106. switch (tlv_tag) {
  107. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  108. {
  109. uint8_t *he_sig_a_mu_ul_info =
  110. (uint8_t *)rx_tlv +
  111. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL,
  112. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  113. ppdu_info->rx_status.he_flags = 1;
  114. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  115. FORMAT_INDICATION);
  116. if (value == 0) {
  117. ppdu_info->rx_status.he_data1 =
  118. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  119. } else {
  120. ppdu_info->rx_status.he_data1 =
  121. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  122. }
  123. /* data1 */
  124. ppdu_info->rx_status.he_data1 |=
  125. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  126. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  127. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  128. /* data2 */
  129. ppdu_info->rx_status.he_data2 |=
  130. QDF_MON_STATUS_TXOP_KNOWN;
  131. /*data3*/
  132. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  133. HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID);
  134. ppdu_info->rx_status.he_data3 = value;
  135. /* 1 for UL and 0 for DL */
  136. value = 1;
  137. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  138. ppdu_info->rx_status.he_data3 |= value;
  139. /*data4*/
  140. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  141. SPATIAL_REUSE);
  142. ppdu_info->rx_status.he_data4 = value;
  143. /*data5*/
  144. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  145. HE_SIG_A_MU_UL_INFO, TRANSMIT_BW);
  146. ppdu_info->rx_status.he_data5 = value;
  147. ppdu_info->rx_status.bw = value;
  148. /*data6*/
  149. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  150. TXOP_DURATION);
  151. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  152. ppdu_info->rx_status.he_data6 |= value;
  153. return true;
  154. }
  155. default:
  156. return false;
  157. }
  158. }
  159. #else
  160. static inline bool
  161. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  162. struct hal_rx_ppdu_info *ppdu_info)
  163. {
  164. return false;
  165. }
  166. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  167. #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \
  168. defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  169. static inline void
  170. hal_rx_handle_mu_ul_info(void *rx_tlv,
  171. struct mon_rx_user_status *mon_rx_user_status)
  172. {
  173. mon_rx_user_status->mu_ul_user_v0_word0 =
  174. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  175. SW_RESPONSE_REFERENCE_PTR);
  176. mon_rx_user_status->mu_ul_user_v0_word1 =
  177. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  178. SW_RESPONSE_REFERENCE_PTR_EXT);
  179. }
  180. static inline void
  181. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  182. struct mon_rx_user_status *mon_rx_user_status)
  183. {
  184. uint32_t mpdu_ok_byte_count;
  185. uint32_t mpdu_err_byte_count;
  186. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  187. RX_PPDU_END_USER_STATS,
  188. MPDU_OK_BYTE_COUNT);
  189. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  190. RX_PPDU_END_USER_STATS,
  191. MPDU_ERR_BYTE_COUNT);
  192. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  193. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  194. }
  195. #else
  196. static inline void
  197. hal_rx_handle_mu_ul_info(void *rx_tlv,
  198. struct mon_rx_user_status *mon_rx_user_status)
  199. {
  200. }
  201. static inline void
  202. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  203. struct mon_rx_user_status *mon_rx_user_status)
  204. {
  205. struct hal_rx_ppdu_info *ppdu_info =
  206. (struct hal_rx_ppdu_info *)ppduinfo;
  207. /* HKV1: doesn't support mpdu byte count */
  208. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  209. mon_rx_user_status->mpdu_err_byte_count = 0;
  210. }
  211. #endif
  212. static inline void
  213. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  214. struct mon_rx_user_status *mon_rx_user_status)
  215. {
  216. struct mon_rx_info *mon_rx_info;
  217. struct mon_rx_user_info *mon_rx_user_info;
  218. struct hal_rx_ppdu_info *ppdu_info =
  219. (struct hal_rx_ppdu_info *)ppduinfo;
  220. mon_rx_info = &ppdu_info->rx_info;
  221. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  222. mon_rx_user_info->qos_control_info_valid =
  223. mon_rx_info->qos_control_info_valid;
  224. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  225. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  226. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  227. mon_rx_user_status->tcp_msdu_count =
  228. ppdu_info->rx_status.tcp_msdu_count;
  229. mon_rx_user_status->udp_msdu_count =
  230. ppdu_info->rx_status.udp_msdu_count;
  231. mon_rx_user_status->other_msdu_count =
  232. ppdu_info->rx_status.other_msdu_count;
  233. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  234. mon_rx_user_status->frame_control_info_valid =
  235. ppdu_info->rx_status.frame_control_info_valid;
  236. mon_rx_user_status->data_sequence_control_info_valid =
  237. ppdu_info->rx_status.data_sequence_control_info_valid;
  238. mon_rx_user_status->first_data_seq_ctrl =
  239. ppdu_info->rx_status.first_data_seq_ctrl;
  240. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  241. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  242. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  243. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  244. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  245. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  246. mon_rx_user_status->mpdu_cnt_fcs_ok =
  247. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  248. mon_rx_user_status->mpdu_cnt_fcs_err =
  249. ppdu_info->com_info.mpdu_cnt_fcs_err;
  250. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  251. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  252. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  253. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  254. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  255. }
  256. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \
  257. ppdu_info, rssi_info_tlv) \
  258. { \
  259. ppdu_info->rx_status.rssi_chain[chain][0] = \
  260. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  261. RSSI_PRI20_CHAIN##chain); \
  262. ppdu_info->rx_status.rssi_chain[chain][1] = \
  263. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  264. RSSI_EXT20_CHAIN##chain); \
  265. ppdu_info->rx_status.rssi_chain[chain][2] = \
  266. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  267. RSSI_EXT40_LOW20_CHAIN##chain); \
  268. ppdu_info->rx_status.rssi_chain[chain][3] = \
  269. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  270. RSSI_EXT40_HIGH20_CHAIN##chain); \
  271. ppdu_info->rx_status.rssi_chain[chain][4] = \
  272. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  273. RSSI_EXT80_LOW20_CHAIN##chain); \
  274. ppdu_info->rx_status.rssi_chain[chain][5] = \
  275. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  276. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  277. ppdu_info->rx_status.rssi_chain[chain][6] = \
  278. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  279. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  280. ppdu_info->rx_status.rssi_chain[chain][7] = \
  281. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  282. RSSI_EXT80_HIGH20_CHAIN##chain); \
  283. } \
  284. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  285. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \
  286. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \
  287. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \
  288. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \
  289. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, ppdu_info, rssi_info_tlv) \
  290. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, ppdu_info, rssi_info_tlv) \
  291. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, ppdu_info, rssi_info_tlv) \
  292. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, ppdu_info, rssi_info_tlv)} \
  293. static inline uint32_t
  294. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  295. uint8_t *rssi_info_tlv)
  296. {
  297. // TODO - Find all these registers for kiwi
  298. #if 0
  299. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  300. #endif
  301. return 0;
  302. }
  303. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  304. static inline void
  305. hal_get_qos_control(void *rx_tlv,
  306. struct hal_rx_ppdu_info *ppdu_info)
  307. {
  308. ppdu_info->rx_info.qos_control_info_valid =
  309. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  310. QOS_CONTROL_INFO_VALID);
  311. if (ppdu_info->rx_info.qos_control_info_valid)
  312. ppdu_info->rx_info.qos_control =
  313. HAL_RX_GET(rx_tlv,
  314. RX_PPDU_END_USER_STATS,
  315. QOS_CONTROL_FIELD);
  316. }
  317. static inline void
  318. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  319. struct hal_rx_ppdu_info *ppdu_info)
  320. {
  321. if ((ppdu_info->sw_frame_group_id
  322. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  323. (ppdu_info->sw_frame_group_id ==
  324. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  325. ppdu_info->rx_info.mac_addr1_valid =
  326. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  327. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  328. HAL_RX_GET(rx_mpdu_start,
  329. RX_MPDU_INFO,
  330. MAC_ADDR_AD1_31_0);
  331. if (ppdu_info->sw_frame_group_id ==
  332. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  333. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  334. HAL_RX_GET(rx_mpdu_start,
  335. RX_MPDU_INFO,
  336. MAC_ADDR_AD1_47_32);
  337. }
  338. }
  339. }
  340. #else
  341. static inline void
  342. hal_get_qos_control(void *rx_tlv,
  343. struct hal_rx_ppdu_info *ppdu_info)
  344. {
  345. }
  346. static inline void
  347. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  348. struct hal_rx_ppdu_info *ppdu_info)
  349. {
  350. }
  351. #endif
  352. /**
  353. * hal_rx_status_get_tlv_info() - process receive info TLV
  354. * @rx_tlv_hdr: pointer to TLV header
  355. * @ppdu_info: pointer to ppdu_info
  356. *
  357. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  358. */
  359. static inline uint32_t
  360. hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
  361. hal_soc_handle_t hal_soc_hdl,
  362. qdf_nbuf_t nbuf)
  363. {
  364. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  365. uint32_t tlv_tag, user_id, tlv_len, value;
  366. uint8_t group_id = 0;
  367. uint8_t he_dcm = 0;
  368. uint8_t he_stbc = 0;
  369. uint16_t he_gi = 0;
  370. uint16_t he_ltf = 0;
  371. void *rx_tlv;
  372. bool unhandled = false;
  373. struct mon_rx_user_status *mon_rx_user_status;
  374. struct hal_rx_ppdu_info *ppdu_info =
  375. (struct hal_rx_ppdu_info *)ppduinfo;
  376. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  377. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  378. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  379. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  380. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  381. rx_tlv, tlv_len);
  382. switch (tlv_tag) {
  383. case WIFIRX_PPDU_START_E:
  384. {
  385. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  386. HAL_RX_GET(rx_tlv, RX_PPDU_START, PHY_PPDU_ID)))
  387. hal_err("Matching ppdu_id(%u) detected",
  388. ppdu_info->com_info.last_ppdu_id);
  389. /* Reset ppdu_info before processing the ppdu */
  390. qdf_mem_zero(ppdu_info,
  391. sizeof(struct hal_rx_ppdu_info));
  392. ppdu_info->com_info.last_ppdu_id =
  393. ppdu_info->com_info.ppdu_id =
  394. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  395. PHY_PPDU_ID);
  396. /* channel number is set in PHY meta data */
  397. ppdu_info->rx_status.chan_num =
  398. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  399. SW_PHY_META_DATA) & 0x0000FFFF);
  400. ppdu_info->rx_status.chan_freq =
  401. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  402. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  403. if (ppdu_info->rx_status.chan_num &&
  404. ppdu_info->rx_status.chan_freq) {
  405. ppdu_info->rx_status.chan_freq =
  406. hal_rx_radiotap_num_to_freq(
  407. ppdu_info->rx_status.chan_num,
  408. ppdu_info->rx_status.chan_freq);
  409. }
  410. ppdu_info->com_info.ppdu_timestamp =
  411. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  412. PPDU_START_TIMESTAMP_31_0);
  413. ppdu_info->rx_status.ppdu_timestamp =
  414. ppdu_info->com_info.ppdu_timestamp;
  415. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  416. break;
  417. }
  418. case WIFIRX_PPDU_START_USER_INFO_E:
  419. break;
  420. case WIFIRX_PPDU_END_E:
  421. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  422. "[%s][%d] ppdu_end_e len=%d",
  423. __func__, __LINE__, tlv_len);
  424. /* This is followed by sub-TLVs of PPDU_END */
  425. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  426. break;
  427. case WIFIPHYRX_LOCATION_E:
  428. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  429. break;
  430. case WIFIRXPCU_PPDU_END_INFO_E:
  431. ppdu_info->rx_status.rx_antenna =
  432. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA);
  433. ppdu_info->rx_status.tsft =
  434. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  435. WB_TIMESTAMP_UPPER_32);
  436. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  437. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  438. WB_TIMESTAMP_LOWER_32);
  439. ppdu_info->rx_status.duration =
  440. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  441. RX_PPDU_DURATION);
  442. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  443. break;
  444. /*
  445. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  446. * for MU, based on num users we see this tlv that many times.
  447. */
  448. case WIFIRX_PPDU_END_USER_STATS_E:
  449. {
  450. unsigned long tid = 0;
  451. uint16_t seq = 0;
  452. ppdu_info->rx_status.ast_index =
  453. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  454. AST_INDEX);
  455. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  456. RECEIVED_QOS_DATA_TID_BITMAP);
  457. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  458. sizeof(tid) * 8);
  459. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  460. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  461. ppdu_info->rx_status.tcp_msdu_count =
  462. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  463. TCP_MSDU_COUNT) +
  464. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  465. TCP_ACK_MSDU_COUNT);
  466. ppdu_info->rx_status.udp_msdu_count =
  467. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  468. UDP_MSDU_COUNT);
  469. ppdu_info->rx_status.other_msdu_count =
  470. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  471. OTHER_MSDU_COUNT);
  472. if (ppdu_info->sw_frame_group_id
  473. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  474. ppdu_info->rx_status.frame_control_info_valid =
  475. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  476. FRAME_CONTROL_INFO_VALID);
  477. if (ppdu_info->rx_status.frame_control_info_valid)
  478. ppdu_info->rx_status.frame_control =
  479. HAL_RX_GET(rx_tlv,
  480. RX_PPDU_END_USER_STATS,
  481. FRAME_CONTROL_FIELD);
  482. hal_get_qos_control(rx_tlv, ppdu_info);
  483. }
  484. ppdu_info->rx_status.data_sequence_control_info_valid =
  485. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  486. DATA_SEQUENCE_CONTROL_INFO_VALID);
  487. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  488. FIRST_DATA_SEQ_CTRL);
  489. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  490. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  491. ppdu_info->rx_status.preamble_type =
  492. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  493. HT_CONTROL_FIELD_PKT_TYPE);
  494. switch (ppdu_info->rx_status.preamble_type) {
  495. case HAL_RX_PKT_TYPE_11N:
  496. ppdu_info->rx_status.ht_flags = 1;
  497. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  498. break;
  499. case HAL_RX_PKT_TYPE_11AC:
  500. ppdu_info->rx_status.vht_flags = 1;
  501. break;
  502. case HAL_RX_PKT_TYPE_11AX:
  503. ppdu_info->rx_status.he_flags = 1;
  504. break;
  505. default:
  506. break;
  507. }
  508. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  509. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  510. MPDU_CNT_FCS_OK);
  511. ppdu_info->com_info.mpdu_cnt_fcs_err =
  512. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  513. MPDU_CNT_FCS_ERR);
  514. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  515. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  516. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  517. else
  518. ppdu_info->rx_status.rs_flags &=
  519. (~IEEE80211_AMPDU_FLAG);
  520. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  521. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  522. FCS_OK_BITMAP_31_0);
  523. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  524. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  525. FCS_OK_BITMAP_63_32);
  526. if (user_id < HAL_MAX_UL_MU_USERS) {
  527. mon_rx_user_status =
  528. &ppdu_info->rx_user_status[user_id];
  529. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  530. ppdu_info->com_info.num_users++;
  531. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  532. user_id,
  533. mon_rx_user_status);
  534. }
  535. break;
  536. }
  537. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  538. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  539. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  540. FCS_OK_BITMAP_95_64);
  541. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  542. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  543. FCS_OK_BITMAP_127_96);
  544. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  545. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  546. FCS_OK_BITMAP_159_128);
  547. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  548. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  549. FCS_OK_BITMAP_191_160);
  550. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  551. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  552. FCS_OK_BITMAP_223_192);
  553. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  554. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  555. FCS_OK_BITMAP_255_224);
  556. break;
  557. case WIFIRX_PPDU_END_STATUS_DONE_E:
  558. return HAL_TLV_STATUS_PPDU_DONE;
  559. case WIFIDUMMY_E:
  560. return HAL_TLV_STATUS_BUF_DONE;
  561. case WIFIPHYRX_HT_SIG_E:
  562. {
  563. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  564. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  565. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  566. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO,
  567. FEC_CODING);
  568. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  569. 1 : 0;
  570. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  571. HT_SIG_INFO, MCS);
  572. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  573. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  574. HT_SIG_INFO, CBW);
  575. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  576. HT_SIG_INFO, SHORT_GI);
  577. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  578. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  579. HT_SIG_SU_NSS_SHIFT) + 1;
  580. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  581. break;
  582. }
  583. case WIFIPHYRX_L_SIG_B_E:
  584. {
  585. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  586. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  587. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  588. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE);
  589. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  590. switch (value) {
  591. case 1:
  592. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  593. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  594. break;
  595. case 2:
  596. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  597. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  598. break;
  599. case 3:
  600. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  601. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  602. break;
  603. case 4:
  604. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  605. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  606. break;
  607. case 5:
  608. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  609. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  610. break;
  611. case 6:
  612. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  613. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  614. break;
  615. case 7:
  616. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  617. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  618. break;
  619. default:
  620. break;
  621. }
  622. ppdu_info->rx_status.cck_flag = 1;
  623. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  624. break;
  625. }
  626. case WIFIPHYRX_L_SIG_A_E:
  627. {
  628. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  629. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  630. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  631. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE);
  632. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  633. switch (value) {
  634. case 8:
  635. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  636. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  637. break;
  638. case 9:
  639. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  640. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  641. break;
  642. case 10:
  643. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  644. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  645. break;
  646. case 11:
  647. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  648. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  649. break;
  650. case 12:
  651. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  652. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  653. break;
  654. case 13:
  655. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  656. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  657. break;
  658. case 14:
  659. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  660. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  661. break;
  662. case 15:
  663. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  664. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  665. break;
  666. default:
  667. break;
  668. }
  669. ppdu_info->rx_status.ofdm_flag = 1;
  670. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  671. break;
  672. }
  673. case WIFIPHYRX_VHT_SIG_A_E:
  674. {
  675. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  676. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  677. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  678. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO,
  679. SU_MU_CODING);
  680. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  681. 1 : 0;
  682. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID);
  683. ppdu_info->rx_status.vht_flag_values5 = group_id;
  684. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  685. VHT_SIG_A_INFO, MCS);
  686. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  687. VHT_SIG_A_INFO, GI_SETTING);
  688. switch (hal->target_type) {
  689. case TARGET_TYPE_QCA8074:
  690. case TARGET_TYPE_QCA8074V2:
  691. case TARGET_TYPE_QCA6018:
  692. case TARGET_TYPE_QCA5018:
  693. case TARGET_TYPE_QCN9000:
  694. case TARGET_TYPE_QCN6122:
  695. #ifdef QCA_WIFI_QCA6390
  696. case TARGET_TYPE_QCA6390:
  697. #endif
  698. ppdu_info->rx_status.is_stbc =
  699. HAL_RX_GET(vht_sig_a_info,
  700. VHT_SIG_A_INFO, STBC);
  701. value = HAL_RX_GET(vht_sig_a_info,
  702. VHT_SIG_A_INFO, N_STS);
  703. value = value & VHT_SIG_SU_NSS_MASK;
  704. if (ppdu_info->rx_status.is_stbc && (value > 0))
  705. value = ((value + 1) >> 1) - 1;
  706. ppdu_info->rx_status.nss =
  707. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  708. break;
  709. case TARGET_TYPE_QCA6290:
  710. #if !defined(QCA_WIFI_QCA6290_11AX)
  711. ppdu_info->rx_status.is_stbc =
  712. HAL_RX_GET(vht_sig_a_info,
  713. VHT_SIG_A_INFO, STBC);
  714. value = HAL_RX_GET(vht_sig_a_info,
  715. VHT_SIG_A_INFO, N_STS);
  716. value = value & VHT_SIG_SU_NSS_MASK;
  717. if (ppdu_info->rx_status.is_stbc && (value > 0))
  718. value = ((value + 1) >> 1) - 1;
  719. ppdu_info->rx_status.nss =
  720. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  721. #else
  722. ppdu_info->rx_status.nss = 0;
  723. #endif
  724. break;
  725. case TARGET_TYPE_QCA6490:
  726. case TARGET_TYPE_QCA6750:
  727. case TARGET_TYPE_KIWI:
  728. ppdu_info->rx_status.nss = 0;
  729. break;
  730. default:
  731. break;
  732. }
  733. ppdu_info->rx_status.vht_flag_values3[0] =
  734. (((ppdu_info->rx_status.mcs) << 4)
  735. | ppdu_info->rx_status.nss);
  736. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  737. VHT_SIG_A_INFO, BANDWIDTH);
  738. ppdu_info->rx_status.vht_flag_values2 =
  739. ppdu_info->rx_status.bw;
  740. ppdu_info->rx_status.vht_flag_values4 =
  741. HAL_RX_GET(vht_sig_a_info,
  742. VHT_SIG_A_INFO, SU_MU_CODING);
  743. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  744. VHT_SIG_A_INFO, BEAMFORMED);
  745. if (group_id == 0 || group_id == 63)
  746. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  747. else
  748. ppdu_info->rx_status.reception_type =
  749. HAL_RX_TYPE_MU_MIMO;
  750. break;
  751. }
  752. case WIFIPHYRX_HE_SIG_A_SU_E:
  753. {
  754. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  755. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  756. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  757. ppdu_info->rx_status.he_flags = 1;
  758. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  759. FORMAT_INDICATION);
  760. if (value == 0) {
  761. ppdu_info->rx_status.he_data1 =
  762. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  763. } else {
  764. ppdu_info->rx_status.he_data1 =
  765. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  766. }
  767. /* data1 */
  768. ppdu_info->rx_status.he_data1 |=
  769. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  770. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  771. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  772. QDF_MON_STATUS_HE_MCS_KNOWN |
  773. QDF_MON_STATUS_HE_DCM_KNOWN |
  774. QDF_MON_STATUS_HE_CODING_KNOWN |
  775. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  776. QDF_MON_STATUS_HE_STBC_KNOWN |
  777. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  778. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  779. /* data2 */
  780. ppdu_info->rx_status.he_data2 =
  781. QDF_MON_STATUS_HE_GI_KNOWN;
  782. ppdu_info->rx_status.he_data2 |=
  783. QDF_MON_STATUS_TXBF_KNOWN |
  784. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  785. QDF_MON_STATUS_TXOP_KNOWN |
  786. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  787. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  788. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  789. /* data3 */
  790. value = HAL_RX_GET(he_sig_a_su_info,
  791. HE_SIG_A_SU_INFO, BSS_COLOR_ID);
  792. ppdu_info->rx_status.he_data3 = value;
  793. value = HAL_RX_GET(he_sig_a_su_info,
  794. HE_SIG_A_SU_INFO, BEAM_CHANGE);
  795. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  796. ppdu_info->rx_status.he_data3 |= value;
  797. value = HAL_RX_GET(he_sig_a_su_info,
  798. HE_SIG_A_SU_INFO, DL_UL_FLAG);
  799. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  800. ppdu_info->rx_status.he_data3 |= value;
  801. value = HAL_RX_GET(he_sig_a_su_info,
  802. HE_SIG_A_SU_INFO, TRANSMIT_MCS);
  803. ppdu_info->rx_status.mcs = value;
  804. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  805. ppdu_info->rx_status.he_data3 |= value;
  806. value = HAL_RX_GET(he_sig_a_su_info,
  807. HE_SIG_A_SU_INFO, DCM);
  808. he_dcm = value;
  809. value = value << QDF_MON_STATUS_DCM_SHIFT;
  810. ppdu_info->rx_status.he_data3 |= value;
  811. value = HAL_RX_GET(he_sig_a_su_info,
  812. HE_SIG_A_SU_INFO, CODING);
  813. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  814. 1 : 0;
  815. value = value << QDF_MON_STATUS_CODING_SHIFT;
  816. ppdu_info->rx_status.he_data3 |= value;
  817. value = HAL_RX_GET(he_sig_a_su_info,
  818. HE_SIG_A_SU_INFO,
  819. LDPC_EXTRA_SYMBOL);
  820. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  821. ppdu_info->rx_status.he_data3 |= value;
  822. value = HAL_RX_GET(he_sig_a_su_info,
  823. HE_SIG_A_SU_INFO, STBC);
  824. he_stbc = value;
  825. value = value << QDF_MON_STATUS_STBC_SHIFT;
  826. ppdu_info->rx_status.he_data3 |= value;
  827. /* data4 */
  828. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  829. SPATIAL_REUSE);
  830. ppdu_info->rx_status.he_data4 = value;
  831. /* data5 */
  832. value = HAL_RX_GET(he_sig_a_su_info,
  833. HE_SIG_A_SU_INFO, TRANSMIT_BW);
  834. ppdu_info->rx_status.he_data5 = value;
  835. ppdu_info->rx_status.bw = value;
  836. value = HAL_RX_GET(he_sig_a_su_info,
  837. HE_SIG_A_SU_INFO, CP_LTF_SIZE);
  838. switch (value) {
  839. case 0:
  840. he_gi = HE_GI_0_8;
  841. he_ltf = HE_LTF_1_X;
  842. break;
  843. case 1:
  844. he_gi = HE_GI_0_8;
  845. he_ltf = HE_LTF_2_X;
  846. break;
  847. case 2:
  848. he_gi = HE_GI_1_6;
  849. he_ltf = HE_LTF_2_X;
  850. break;
  851. case 3:
  852. if (he_dcm && he_stbc) {
  853. he_gi = HE_GI_0_8;
  854. he_ltf = HE_LTF_4_X;
  855. } else {
  856. he_gi = HE_GI_3_2;
  857. he_ltf = HE_LTF_4_X;
  858. }
  859. break;
  860. }
  861. ppdu_info->rx_status.sgi = he_gi;
  862. ppdu_info->rx_status.ltf_size = he_ltf;
  863. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  864. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  865. ppdu_info->rx_status.he_data5 |= value;
  866. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  867. ppdu_info->rx_status.he_data5 |= value;
  868. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  869. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  870. ppdu_info->rx_status.he_data5 |= value;
  871. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  872. PACKET_EXTENSION_A_FACTOR);
  873. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  874. ppdu_info->rx_status.he_data5 |= value;
  875. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF);
  876. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  877. ppdu_info->rx_status.he_data5 |= value;
  878. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  879. PACKET_EXTENSION_PE_DISAMBIGUITY);
  880. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  881. ppdu_info->rx_status.he_data5 |= value;
  882. /* data6 */
  883. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  884. value++;
  885. ppdu_info->rx_status.nss = value;
  886. ppdu_info->rx_status.he_data6 = value;
  887. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  888. DOPPLER_INDICATION);
  889. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  890. ppdu_info->rx_status.he_data6 |= value;
  891. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  892. TXOP_DURATION);
  893. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  894. ppdu_info->rx_status.he_data6 |= value;
  895. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  896. HE_SIG_A_SU_INFO, TXBF);
  897. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  898. break;
  899. }
  900. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  901. {
  902. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  903. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  904. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  905. ppdu_info->rx_status.he_mu_flags = 1;
  906. /* HE Flags */
  907. /*data1*/
  908. ppdu_info->rx_status.he_data1 =
  909. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  910. ppdu_info->rx_status.he_data1 |=
  911. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  912. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  913. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  914. QDF_MON_STATUS_HE_STBC_KNOWN |
  915. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  916. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  917. /* data2 */
  918. ppdu_info->rx_status.he_data2 =
  919. QDF_MON_STATUS_HE_GI_KNOWN;
  920. ppdu_info->rx_status.he_data2 |=
  921. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  922. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  923. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  924. QDF_MON_STATUS_TXOP_KNOWN |
  925. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  926. /*data3*/
  927. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  928. HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID);
  929. ppdu_info->rx_status.he_data3 = value;
  930. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  931. HE_SIG_A_MU_DL_INFO, DL_UL_FLAG);
  932. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  933. ppdu_info->rx_status.he_data3 |= value;
  934. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  935. HE_SIG_A_MU_DL_INFO,
  936. LDPC_EXTRA_SYMBOL);
  937. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  938. ppdu_info->rx_status.he_data3 |= value;
  939. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  940. HE_SIG_A_MU_DL_INFO, STBC);
  941. he_stbc = value;
  942. value = value << QDF_MON_STATUS_STBC_SHIFT;
  943. ppdu_info->rx_status.he_data3 |= value;
  944. /*data4*/
  945. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  946. SPATIAL_REUSE);
  947. ppdu_info->rx_status.he_data4 = value;
  948. /*data5*/
  949. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  950. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  951. ppdu_info->rx_status.he_data5 = value;
  952. ppdu_info->rx_status.bw = value;
  953. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  954. HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE);
  955. switch (value) {
  956. case 0:
  957. he_gi = HE_GI_0_8;
  958. he_ltf = HE_LTF_4_X;
  959. break;
  960. case 1:
  961. he_gi = HE_GI_0_8;
  962. he_ltf = HE_LTF_2_X;
  963. break;
  964. case 2:
  965. he_gi = HE_GI_1_6;
  966. he_ltf = HE_LTF_2_X;
  967. break;
  968. case 3:
  969. he_gi = HE_GI_3_2;
  970. he_ltf = HE_LTF_4_X;
  971. break;
  972. }
  973. ppdu_info->rx_status.sgi = he_gi;
  974. ppdu_info->rx_status.ltf_size = he_ltf;
  975. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  976. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  977. ppdu_info->rx_status.he_data5 |= value;
  978. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  979. ppdu_info->rx_status.he_data5 |= value;
  980. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  981. HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS);
  982. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  983. ppdu_info->rx_status.he_data5 |= value;
  984. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  985. PACKET_EXTENSION_A_FACTOR);
  986. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  987. ppdu_info->rx_status.he_data5 |= value;
  988. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  989. PACKET_EXTENSION_PE_DISAMBIGUITY);
  990. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  991. ppdu_info->rx_status.he_data5 |= value;
  992. /*data6*/
  993. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  994. DOPPLER_INDICATION);
  995. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  996. ppdu_info->rx_status.he_data6 |= value;
  997. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  998. TXOP_DURATION);
  999. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1000. ppdu_info->rx_status.he_data6 |= value;
  1001. /* HE-MU Flags */
  1002. /* HE-MU-flags1 */
  1003. ppdu_info->rx_status.he_flags1 =
  1004. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1005. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1006. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1007. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1008. QDF_MON_STATUS_RU_0_KNOWN;
  1009. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1010. HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B);
  1011. ppdu_info->rx_status.he_flags1 |= value;
  1012. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1013. HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B);
  1014. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1015. ppdu_info->rx_status.he_flags1 |= value;
  1016. /* HE-MU-flags2 */
  1017. ppdu_info->rx_status.he_flags2 =
  1018. QDF_MON_STATUS_BW_KNOWN;
  1019. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1020. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  1021. ppdu_info->rx_status.he_flags2 |= value;
  1022. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1023. HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B);
  1024. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1025. ppdu_info->rx_status.he_flags2 |= value;
  1026. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1027. HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS);
  1028. value = value - 1;
  1029. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1030. ppdu_info->rx_status.he_flags2 |= value;
  1031. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1032. break;
  1033. }
  1034. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1035. {
  1036. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1037. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1038. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1039. ppdu_info->rx_status.he_sig_b_common_known |=
  1040. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1041. /* TODO: Check on the availability of other fields in
  1042. * sig_b_common
  1043. */
  1044. value = HAL_RX_GET(he_sig_b1_mu_info,
  1045. HE_SIG_B1_MU_INFO, RU_ALLOCATION);
  1046. ppdu_info->rx_status.he_RU[0] = value;
  1047. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1048. break;
  1049. }
  1050. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1051. {
  1052. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1053. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1054. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1055. /*
  1056. * Not all "HE" fields can be updated from
  1057. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1058. * to populate rest of the "HE" fields for MU scenarios.
  1059. */
  1060. /* HE-data1 */
  1061. ppdu_info->rx_status.he_data1 |=
  1062. QDF_MON_STATUS_HE_MCS_KNOWN |
  1063. QDF_MON_STATUS_HE_CODING_KNOWN;
  1064. /* HE-data2 */
  1065. /* HE-data3 */
  1066. value = HAL_RX_GET(he_sig_b2_mu_info,
  1067. HE_SIG_B2_MU_INFO, STA_MCS);
  1068. ppdu_info->rx_status.mcs = value;
  1069. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1070. ppdu_info->rx_status.he_data3 |= value;
  1071. value = HAL_RX_GET(he_sig_b2_mu_info,
  1072. HE_SIG_B2_MU_INFO, STA_CODING);
  1073. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1074. ppdu_info->rx_status.he_data3 |= value;
  1075. /* HE-data4 */
  1076. value = HAL_RX_GET(he_sig_b2_mu_info,
  1077. HE_SIG_B2_MU_INFO, STA_ID);
  1078. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1079. ppdu_info->rx_status.he_data4 |= value;
  1080. /* HE-data5 */
  1081. /* HE-data6 */
  1082. value = HAL_RX_GET(he_sig_b2_mu_info,
  1083. HE_SIG_B2_MU_INFO, NSTS);
  1084. /* value n indicates n+1 spatial streams */
  1085. value++;
  1086. ppdu_info->rx_status.nss = value;
  1087. ppdu_info->rx_status.he_data6 |= value;
  1088. break;
  1089. }
  1090. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1091. {
  1092. uint8_t *he_sig_b2_ofdma_info =
  1093. (uint8_t *)rx_tlv +
  1094. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1095. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1096. /*
  1097. * Not all "HE" fields can be updated from
  1098. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1099. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1100. */
  1101. /* HE-data1 */
  1102. ppdu_info->rx_status.he_data1 |=
  1103. QDF_MON_STATUS_HE_MCS_KNOWN |
  1104. QDF_MON_STATUS_HE_DCM_KNOWN |
  1105. QDF_MON_STATUS_HE_CODING_KNOWN;
  1106. /* HE-data2 */
  1107. ppdu_info->rx_status.he_data2 |=
  1108. QDF_MON_STATUS_TXBF_KNOWN;
  1109. /* HE-data3 */
  1110. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1111. HE_SIG_B2_OFDMA_INFO, STA_MCS);
  1112. ppdu_info->rx_status.mcs = value;
  1113. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1114. ppdu_info->rx_status.he_data3 |= value;
  1115. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1116. HE_SIG_B2_OFDMA_INFO, STA_DCM);
  1117. he_dcm = value;
  1118. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1119. ppdu_info->rx_status.he_data3 |= value;
  1120. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1121. HE_SIG_B2_OFDMA_INFO, STA_CODING);
  1122. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1123. ppdu_info->rx_status.he_data3 |= value;
  1124. /* HE-data4 */
  1125. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1126. HE_SIG_B2_OFDMA_INFO, STA_ID);
  1127. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1128. ppdu_info->rx_status.he_data4 |= value;
  1129. /* HE-data5 */
  1130. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1131. HE_SIG_B2_OFDMA_INFO, TXBF);
  1132. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1133. ppdu_info->rx_status.he_data5 |= value;
  1134. /* HE-data6 */
  1135. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1136. HE_SIG_B2_OFDMA_INFO, NSTS);
  1137. /* value n indicates n+1 spatial streams */
  1138. value++;
  1139. ppdu_info->rx_status.nss = value;
  1140. ppdu_info->rx_status.he_data6 |= value;
  1141. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1142. break;
  1143. }
  1144. case WIFIPHYRX_RSSI_LEGACY_E:
  1145. {
  1146. uint8_t reception_type;
  1147. int8_t rssi_value;
  1148. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1149. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1150. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1151. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1152. PHYRX_RSSI_LEGACY, RSSI_COMB);
  1153. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1154. ppdu_info->rx_status.he_re = 0;
  1155. reception_type = HAL_RX_GET(rx_tlv,
  1156. PHYRX_RSSI_LEGACY,
  1157. RECEPTION_TYPE);
  1158. switch (reception_type) {
  1159. case QDF_RECEPTION_TYPE_ULOFMDA:
  1160. ppdu_info->rx_status.reception_type =
  1161. HAL_RX_TYPE_MU_OFDMA;
  1162. ppdu_info->rx_status.ulofdma_flag = 1;
  1163. ppdu_info->rx_status.he_data1 =
  1164. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1165. break;
  1166. case QDF_RECEPTION_TYPE_ULMIMO:
  1167. ppdu_info->rx_status.reception_type =
  1168. HAL_RX_TYPE_MU_MIMO;
  1169. ppdu_info->rx_status.he_data1 =
  1170. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1171. break;
  1172. default:
  1173. ppdu_info->rx_status.reception_type =
  1174. HAL_RX_TYPE_SU;
  1175. break;
  1176. }
  1177. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1178. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1179. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN0);
  1180. ppdu_info->rx_status.rssi[0] = rssi_value;
  1181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1182. "RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1183. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1184. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN1);
  1185. ppdu_info->rx_status.rssi[1] = rssi_value;
  1186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1187. "RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1188. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1189. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN2);
  1190. ppdu_info->rx_status.rssi[2] = rssi_value;
  1191. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1192. "RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1193. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1194. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN3);
  1195. ppdu_info->rx_status.rssi[3] = rssi_value;
  1196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1197. "RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1198. #ifdef DP_BE_NOTYET_WAR
  1199. // TODO - this is not preset for kiwi
  1200. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1201. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN4);
  1202. ppdu_info->rx_status.rssi[4] = rssi_value;
  1203. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1204. "RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1205. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1206. RECEIVE_RSSI_INFO,
  1207. RSSI_PRI20_CHAIN5);
  1208. ppdu_info->rx_status.rssi[5] = rssi_value;
  1209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1210. "RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1211. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1212. RECEIVE_RSSI_INFO,
  1213. RSSI_PRI20_CHAIN6);
  1214. ppdu_info->rx_status.rssi[6] = rssi_value;
  1215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1216. "RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1217. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1218. RECEIVE_RSSI_INFO,
  1219. RSSI_PRI20_CHAIN7);
  1220. ppdu_info->rx_status.rssi[7] = rssi_value;
  1221. #endif
  1222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1223. "RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1224. break;
  1225. }
  1226. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1227. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1228. ppdu_info);
  1229. break;
  1230. case WIFIRX_HEADER_E:
  1231. {
  1232. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1233. if (ppdu_info->fcs_ok_cnt >=
  1234. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1235. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1236. ppdu_info->fcs_ok_cnt);
  1237. break;
  1238. }
  1239. /* Update first_msdu_payload for every mpdu and increment
  1240. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1241. */
  1242. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1243. rx_tlv;
  1244. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1245. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1246. ppdu_info->msdu_info.payload_len = tlv_len;
  1247. ppdu_info->user_id = user_id;
  1248. ppdu_info->hdr_len = tlv_len;
  1249. ppdu_info->data = rx_tlv;
  1250. ppdu_info->data += 4;
  1251. /* for every RX_HEADER TLV increment mpdu_cnt */
  1252. com_info->mpdu_cnt++;
  1253. return HAL_TLV_STATUS_HEADER;
  1254. }
  1255. case WIFIRX_MPDU_START_E:
  1256. {
  1257. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1258. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_tlv);
  1259. uint8_t filter_category = 0;
  1260. ppdu_info->nac_info.fc_valid =
  1261. HAL_RX_MON_GET_FC_VALID(rx_tlv);
  1262. ppdu_info->nac_info.to_ds_flag =
  1263. HAL_RX_MON_GET_TO_DS_FLAG(rx_tlv);
  1264. ppdu_info->nac_info.frame_control =
  1265. HAL_RX_GET(rx_mpdu_start,
  1266. RX_MPDU_INFO,
  1267. MPDU_FRAME_CONTROL_FIELD);
  1268. ppdu_info->sw_frame_group_id =
  1269. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_tlv);
  1270. ppdu_info->rx_user_status[user_id].sw_peer_id =
  1271. HAL_RX_GET(rx_mpdu_start,
  1272. RX_MPDU_INFO,
  1273. SW_PEER_ID);
  1274. if (ppdu_info->sw_frame_group_id ==
  1275. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1276. ppdu_info->rx_status.frame_control_info_valid =
  1277. ppdu_info->nac_info.fc_valid;
  1278. ppdu_info->rx_status.frame_control =
  1279. ppdu_info->nac_info.frame_control;
  1280. }
  1281. hal_get_mac_addr1(rx_mpdu_start,
  1282. ppdu_info);
  1283. ppdu_info->nac_info.mac_addr2_valid =
  1284. HAL_RX_MON_GET_MAC_ADDR2_VALID(rx_mpdu_start);
  1285. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1286. HAL_RX_GET(rx_mpdu_start,
  1287. RX_MPDU_INFO,
  1288. MAC_ADDR_AD2_15_0);
  1289. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1290. HAL_RX_GET(rx_mpdu_start,
  1291. RX_MPDU_INFO,
  1292. MAC_ADDR_AD2_47_16);
  1293. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1294. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1295. ppdu_info->rx_status.ppdu_len =
  1296. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1297. MPDU_LENGTH);
  1298. } else {
  1299. ppdu_info->rx_status.ppdu_len +=
  1300. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1301. MPDU_LENGTH);
  1302. }
  1303. filter_category =
  1304. HAL_RX_GET_FILTER_CATEGORY(rx_tlv);
  1305. if (filter_category == 0)
  1306. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1307. else if (filter_category == 1)
  1308. ppdu_info->rx_status.monitor_direct_used = 1;
  1309. ppdu_info->nac_info.mcast_bcast =
  1310. HAL_RX_GET(rx_mpdu_start,
  1311. RX_MPDU_INFO,
  1312. MCAST_BCAST);
  1313. break;
  1314. }
  1315. case WIFIRX_MPDU_END_E:
  1316. ppdu_info->user_id = user_id;
  1317. ppdu_info->fcs_err =
  1318. HAL_RX_GET(rx_tlv, RX_MPDU_END,
  1319. FCS_ERR);
  1320. return HAL_TLV_STATUS_MPDU_END;
  1321. case WIFIRX_MSDU_END_E:
  1322. if (user_id < HAL_MAX_UL_MU_USERS) {
  1323. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1324. HAL_RX_TLV_CCE_METADATA_GET(rx_tlv);
  1325. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1326. HAL_RX_TLV_FSE_METADATA_GET(rx_tlv);
  1327. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1328. HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1329. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1330. HAL_RX_TLV_FLOW_IDX_INVALID_GET(rx_tlv);
  1331. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1332. HAL_RX_TLV_FLOW_IDX_GET(rx_tlv);
  1333. }
  1334. return HAL_TLV_STATUS_MSDU_END;
  1335. case 0:
  1336. return HAL_TLV_STATUS_PPDU_DONE;
  1337. default:
  1338. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1339. unhandled = false;
  1340. else
  1341. unhandled = true;
  1342. break;
  1343. }
  1344. if (!unhandled)
  1345. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1346. "%s TLV type: %d, TLV len:%d %s",
  1347. __func__, tlv_tag, tlv_len,
  1348. unhandled == true ? "unhandled" : "");
  1349. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1350. rx_tlv, tlv_len);
  1351. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1352. }
  1353. /**
  1354. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  1355. * @soc: HAL SoC context
  1356. * @map: PCP-TID mapping table
  1357. *
  1358. * PCP are mapped to 8 TID values using TID values programmed
  1359. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  1360. * The mapping register has TID mapping for 8 PCP values
  1361. *
  1362. * Return: none
  1363. */
  1364. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  1365. {
  1366. uint32_t addr, value;
  1367. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1368. MAC_TCL_REG_REG_BASE);
  1369. value = (map[0] |
  1370. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  1371. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  1372. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  1373. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  1374. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  1375. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  1376. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  1377. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1378. }
  1379. /**
  1380. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  1381. * value received from user-space
  1382. * @soc: HAL SoC context
  1383. * @pcp: pcp value
  1384. * @tid : tid value
  1385. *
  1386. * Return: void
  1387. */
  1388. static void
  1389. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  1390. uint8_t pcp, uint8_t tid)
  1391. {
  1392. uint32_t addr, value, regval;
  1393. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1394. MAC_TCL_REG_REG_BASE);
  1395. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  1396. /* Read back previous PCP TID config and update
  1397. * with new config.
  1398. */
  1399. regval = HAL_REG_READ(soc, addr);
  1400. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  1401. regval |= value;
  1402. HAL_REG_WRITE(soc, addr,
  1403. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1404. }
  1405. /**
  1406. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  1407. * @soc: HAL SoC context
  1408. * @val: priority value
  1409. *
  1410. * Return: void
  1411. */
  1412. static
  1413. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  1414. {
  1415. uint32_t addr;
  1416. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  1417. MAC_TCL_REG_REG_BASE);
  1418. HAL_REG_WRITE(soc, addr,
  1419. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  1420. }
  1421. /**
  1422. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  1423. * @rx_pkt_tlv_size: TLV size for regular RX packets
  1424. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  1425. *
  1426. * Return: size of rx pkt tlv before the actual data
  1427. */
  1428. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  1429. uint16_t *rx_mon_pkt_tlv_size)
  1430. {
  1431. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1432. /* For now mon pkt tlv is same as rx pkt tlv */
  1433. *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1434. }
  1435. /**
  1436. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  1437. * @fst: Pointer to the Rx Flow Search Table
  1438. * @hal_hash: HAL 5 tuple hash
  1439. * @tuple_info: 5-tuple info of the flow returned to the caller
  1440. *
  1441. * Return: Success/Failure
  1442. */
  1443. static void *
  1444. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  1445. uint8_t *flow_tuple_info)
  1446. {
  1447. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1448. void *hal_fse = NULL;
  1449. struct hal_flow_tuple_info *tuple_info
  1450. = (struct hal_flow_tuple_info *)flow_tuple_info;
  1451. hal_fse = (uint8_t *)fst->base_vaddr +
  1452. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  1453. if (!hal_fse || !tuple_info)
  1454. return NULL;
  1455. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  1456. return NULL;
  1457. tuple_info->src_ip_127_96 =
  1458. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1459. RX_FLOW_SEARCH_ENTRY,
  1460. SRC_IP_127_96));
  1461. tuple_info->src_ip_95_64 =
  1462. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1463. RX_FLOW_SEARCH_ENTRY,
  1464. SRC_IP_95_64));
  1465. tuple_info->src_ip_63_32 =
  1466. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1467. RX_FLOW_SEARCH_ENTRY,
  1468. SRC_IP_63_32));
  1469. tuple_info->src_ip_31_0 =
  1470. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1471. RX_FLOW_SEARCH_ENTRY,
  1472. SRC_IP_31_0));
  1473. tuple_info->dest_ip_127_96 =
  1474. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1475. RX_FLOW_SEARCH_ENTRY,
  1476. DEST_IP_127_96));
  1477. tuple_info->dest_ip_95_64 =
  1478. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1479. RX_FLOW_SEARCH_ENTRY,
  1480. DEST_IP_95_64));
  1481. tuple_info->dest_ip_63_32 =
  1482. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1483. RX_FLOW_SEARCH_ENTRY,
  1484. DEST_IP_63_32));
  1485. tuple_info->dest_ip_31_0 =
  1486. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1487. RX_FLOW_SEARCH_ENTRY,
  1488. DEST_IP_31_0));
  1489. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  1490. RX_FLOW_SEARCH_ENTRY,
  1491. DEST_PORT);
  1492. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  1493. RX_FLOW_SEARCH_ENTRY,
  1494. SRC_PORT);
  1495. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  1496. RX_FLOW_SEARCH_ENTRY,
  1497. L4_PROTOCOL);
  1498. return hal_fse;
  1499. }
  1500. /**
  1501. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  1502. * @fst: Pointer to the Rx Flow Search Table
  1503. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  1504. *
  1505. * Return: Success/Failure
  1506. */
  1507. static QDF_STATUS
  1508. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  1509. {
  1510. uint8_t *fse = (uint8_t *)hal_rx_fse;
  1511. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  1512. return QDF_STATUS_E_NOENT;
  1513. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1514. return QDF_STATUS_SUCCESS;
  1515. }
  1516. /**
  1517. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  1518. *
  1519. * Return: size of each entry/flow in Rx FST
  1520. */
  1521. static inline uint32_t
  1522. hal_rx_fst_get_fse_size_be(void)
  1523. {
  1524. return HAL_RX_FST_ENTRY_SIZE;
  1525. }
  1526. /*
  1527. * TX MONITOR
  1528. */
  1529. #ifdef QCA_MONITOR_2_0_SUPPORT
  1530. /**
  1531. * hal_txmon_get_buffer_addr_generic_be() - api to get buffer address
  1532. * @tx_tlv: pointer to TLV header
  1533. * @status: hal mon buffer address status
  1534. *
  1535. * Return: Address to qdf_frag_t
  1536. */
  1537. static inline qdf_frag_t
  1538. hal_txmon_get_buffer_addr_generic_be(void *tx_tlv,
  1539. struct hal_mon_buf_addr_status *status)
  1540. {
  1541. struct mon_buffer_addr *hal_buffer_addr =
  1542. (struct mon_buffer_addr *)((uint8_t *)tx_tlv +
  1543. HAL_RX_TLV32_HDR_SIZE);
  1544. qdf_frag_t buf_addr = NULL;
  1545. buf_addr = (qdf_frag_t)((u64)hal_buffer_addr->buffer_virt_addr_31_0 |
  1546. ((u64)hal_buffer_addr->buffer_virt_addr_63_32 <<
  1547. 32));
  1548. /* qdf_frag_t is derived from buffer address tlv */
  1549. if (qdf_unlikely(status)) {
  1550. qdf_mem_copy(status,
  1551. (uint8_t *)tx_tlv + HAL_RX_TLV32_HDR_SIZE,
  1552. sizeof(struct hal_mon_buf_addr_status));
  1553. /* update hal_mon_buf_addr_status */
  1554. }
  1555. return buf_addr;
  1556. }
  1557. /**
  1558. * hal_txmon_free_status_buffer() - api to free status buffer
  1559. * @pdev_handle: DP_PDEV handle
  1560. * @status_frag: qdf_frag_t buffer
  1561. *
  1562. * Return void
  1563. */
  1564. static inline void
  1565. hal_txmon_status_free_buffer_generic_be(qdf_frag_t status_frag)
  1566. {
  1567. uint32_t tlv_tag, tlv_len;
  1568. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1569. uint8_t *tx_tlv;
  1570. uint8_t *tx_tlv_start;
  1571. qdf_frag_t frag_buf = NULL;
  1572. tx_tlv = (uint8_t *)status_frag;
  1573. tx_tlv_start = tx_tlv;
  1574. /* parse tlv and populate tx_ppdu_info */
  1575. do {
  1576. /* TODO: check config_length is full monitor mode */
  1577. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv);
  1578. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv);
  1579. if (tlv_tag == WIFIMON_BUFFER_ADDR_E) {
  1580. frag_buf = hal_txmon_get_buffer_addr_generic_be(tx_tlv,
  1581. NULL);
  1582. if (frag_buf)
  1583. qdf_frag_free(frag_buf);
  1584. frag_buf = NULL;
  1585. }
  1586. /* need api definition for hal_tx_status_get_next_tlv */
  1587. tx_tlv = hal_tx_status_get_next_tlv(tx_tlv);
  1588. if ((tx_tlv - tx_tlv_start) >= TX_MON_STATUS_BUF_SIZE)
  1589. break;
  1590. } while (tlv_status == HAL_MON_TX_STATUS_PPDU_NOT_DONE);
  1591. }
  1592. #endif /* QCA_MONITOR_2_0_SUPPORT */
  1593. #endif /* _HAL_BE_GENERIC_API_H_ */