dp_tx.c 145 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. /* Flag to skip CCE classify when mesh or tid override enabled */
  52. #define DP_TX_SKIP_CCE_CLASSIFY \
  53. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  54. /* TODO Add support in TSO */
  55. #define DP_DESC_NUM_FRAG(x) 0
  56. /* disable TQM_BYPASS */
  57. #define TQM_BYPASS_WAR 0
  58. /* invalid peer id for reinject*/
  59. #define DP_INVALID_PEER 0XFFFE
  60. #define DP_RETRY_COUNT 7
  61. #ifdef WLAN_MCAST_MLO
  62. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  63. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  64. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  65. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  66. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  67. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  74. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  75. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  76. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  77. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  78. #else
  79. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  80. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  81. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  82. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  83. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  84. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  91. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  92. HTT_TCL_METADATA_TYPE_PEER_BASED
  93. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  94. HTT_TCL_METADATA_TYPE_VDEV_BASED
  95. #endif
  96. /*mapping between hal encrypt type and cdp_sec_type*/
  97. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  98. HAL_TX_ENCRYPT_TYPE_WEP_128,
  99. HAL_TX_ENCRYPT_TYPE_WEP_104,
  100. HAL_TX_ENCRYPT_TYPE_WEP_40,
  101. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  102. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  103. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  104. HAL_TX_ENCRYPT_TYPE_WAPI,
  105. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  106. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  107. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  108. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  109. qdf_export_symbol(sec_type_map);
  110. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  111. /**
  112. * dp_update_tx_desc_stats - Update the increase or decrease in
  113. * outstanding tx desc count
  114. * values on pdev and soc
  115. * @vdev: DP pdev handle
  116. *
  117. * Return: void
  118. */
  119. static inline void
  120. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  121. {
  122. int32_t tx_descs_cnt =
  123. qdf_atomic_read(&pdev->num_tx_outstanding);
  124. if (pdev->tx_descs_max < tx_descs_cnt)
  125. pdev->tx_descs_max = tx_descs_cnt;
  126. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  127. pdev->tx_descs_max);
  128. }
  129. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  130. static inline void
  131. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  135. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  136. static inline
  137. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  138. {
  139. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  140. QDF_DMA_TO_DEVICE,
  141. desc->nbuf->len);
  142. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  143. }
  144. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  145. {
  146. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  147. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  148. QDF_DMA_TO_DEVICE,
  149. desc->nbuf->len);
  150. }
  151. #else
  152. static inline
  153. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  154. {
  155. }
  156. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  157. {
  158. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  159. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  160. }
  161. #endif
  162. #ifdef QCA_TX_LIMIT_CHECK
  163. /**
  164. * dp_tx_limit_check - Check if allocated tx descriptors reached
  165. * soc max limit and pdev max limit
  166. * @vdev: DP vdev handle
  167. *
  168. * Return: true if allocated tx descriptors reached max configured value, else
  169. * false
  170. */
  171. static inline bool
  172. dp_tx_limit_check(struct dp_vdev *vdev)
  173. {
  174. struct dp_pdev *pdev = vdev->pdev;
  175. struct dp_soc *soc = pdev->soc;
  176. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  177. soc->num_tx_allowed) {
  178. dp_tx_info("queued packets are more than max tx, drop the frame");
  179. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  180. return true;
  181. }
  182. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  183. pdev->num_tx_allowed) {
  184. dp_tx_info("queued packets are more than max tx, drop the frame");
  185. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  186. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  187. return true;
  188. }
  189. return false;
  190. }
  191. /**
  192. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  193. * reached soc max limit
  194. * @vdev: DP vdev handle
  195. *
  196. * Return: true if allocated tx descriptors reached max configured value, else
  197. * false
  198. */
  199. static inline bool
  200. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  201. {
  202. struct dp_pdev *pdev = vdev->pdev;
  203. struct dp_soc *soc = pdev->soc;
  204. if (qdf_atomic_read(&soc->num_tx_exception) >=
  205. soc->num_msdu_exception_desc) {
  206. dp_info("exc packets are more than max drop the exc pkt");
  207. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  208. return true;
  209. }
  210. return false;
  211. }
  212. /**
  213. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  214. * @vdev: DP pdev handle
  215. *
  216. * Return: void
  217. */
  218. static inline void
  219. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  220. {
  221. struct dp_soc *soc = pdev->soc;
  222. qdf_atomic_inc(&pdev->num_tx_outstanding);
  223. qdf_atomic_inc(&soc->num_tx_outstanding);
  224. dp_update_tx_desc_stats(pdev);
  225. }
  226. /**
  227. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  228. * @vdev: DP pdev handle
  229. *
  230. * Return: void
  231. */
  232. static inline void
  233. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  234. {
  235. struct dp_soc *soc = pdev->soc;
  236. qdf_atomic_dec(&pdev->num_tx_outstanding);
  237. qdf_atomic_dec(&soc->num_tx_outstanding);
  238. dp_update_tx_desc_stats(pdev);
  239. }
  240. #else //QCA_TX_LIMIT_CHECK
  241. static inline bool
  242. dp_tx_limit_check(struct dp_vdev *vdev)
  243. {
  244. return false;
  245. }
  246. static inline bool
  247. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  248. {
  249. return false;
  250. }
  251. static inline void
  252. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  253. {
  254. qdf_atomic_inc(&pdev->num_tx_outstanding);
  255. dp_update_tx_desc_stats(pdev);
  256. }
  257. static inline void
  258. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  259. {
  260. qdf_atomic_dec(&pdev->num_tx_outstanding);
  261. dp_update_tx_desc_stats(pdev);
  262. }
  263. #endif //QCA_TX_LIMIT_CHECK
  264. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  265. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  266. {
  267. enum dp_tx_event_type type;
  268. if (flags & DP_TX_DESC_FLAG_FLUSH)
  269. type = DP_TX_DESC_FLUSH;
  270. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  271. type = DP_TX_COMP_UNMAP_ERR;
  272. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  273. type = DP_TX_COMP_UNMAP;
  274. else
  275. type = DP_TX_DESC_UNMAP;
  276. return type;
  277. }
  278. static inline void
  279. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  280. qdf_nbuf_t skb, uint32_t sw_cookie,
  281. enum dp_tx_event_type type)
  282. {
  283. struct dp_tx_desc_event *entry;
  284. uint32_t idx;
  285. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  286. return;
  287. switch (type) {
  288. case DP_TX_COMP_UNMAP:
  289. case DP_TX_COMP_UNMAP_ERR:
  290. case DP_TX_COMP_MSDU_EXT:
  291. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  292. DP_TX_COMP_HISTORY_SIZE);
  293. entry = &soc->tx_comp_history->entry[idx];
  294. break;
  295. case DP_TX_DESC_MAP:
  296. case DP_TX_DESC_UNMAP:
  297. case DP_TX_DESC_COOKIE:
  298. case DP_TX_DESC_FLUSH:
  299. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  300. DP_TX_TCL_HISTORY_SIZE);
  301. entry = &soc->tx_tcl_history->entry[idx];
  302. break;
  303. default:
  304. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  305. return;
  306. }
  307. entry->skb = skb;
  308. entry->paddr = paddr;
  309. entry->sw_cookie = sw_cookie;
  310. entry->type = type;
  311. entry->ts = qdf_get_log_timestamp();
  312. }
  313. static inline void
  314. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  315. struct qdf_tso_seg_elem_t *tso_seg,
  316. qdf_nbuf_t skb, uint32_t sw_cookie,
  317. enum dp_tx_event_type type)
  318. {
  319. int i;
  320. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  321. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  322. skb, sw_cookie, type);
  323. }
  324. if (!tso_seg->next)
  325. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  326. skb, 0xFFFFFFFF, type);
  327. }
  328. static inline void
  329. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  330. qdf_nbuf_t skb, uint32_t sw_cookie,
  331. enum dp_tx_event_type type)
  332. {
  333. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  334. uint32_t num_segs = tso_info.num_segs;
  335. while (num_segs) {
  336. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  337. curr_seg = curr_seg->next;
  338. num_segs--;
  339. }
  340. }
  341. #else
  342. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  343. {
  344. return DP_TX_DESC_INVAL_EVT;
  345. }
  346. static inline void
  347. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  348. qdf_nbuf_t skb, uint32_t sw_cookie,
  349. enum dp_tx_event_type type)
  350. {
  351. }
  352. static inline void
  353. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  354. struct qdf_tso_seg_elem_t *tso_seg,
  355. qdf_nbuf_t skb, uint32_t sw_cookie,
  356. enum dp_tx_event_type type)
  357. {
  358. }
  359. static inline void
  360. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  361. qdf_nbuf_t skb, uint32_t sw_cookie,
  362. enum dp_tx_event_type type)
  363. {
  364. }
  365. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  366. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  367. /**
  368. * dp_is_tput_high() - Check if throughput is high
  369. *
  370. * @soc - core txrx main context
  371. *
  372. * The current function is based of the RTPM tput policy variable where RTPM is
  373. * avoided based on throughput.
  374. */
  375. static inline int dp_is_tput_high(struct dp_soc *soc)
  376. {
  377. return dp_get_rtpm_tput_policy_requirement(soc);
  378. }
  379. #if defined(FEATURE_TSO)
  380. /**
  381. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  382. *
  383. * @soc - core txrx main context
  384. * @seg_desc - tso segment descriptor
  385. * @num_seg_desc - tso number segment descriptor
  386. */
  387. static void dp_tx_tso_unmap_segment(
  388. struct dp_soc *soc,
  389. struct qdf_tso_seg_elem_t *seg_desc,
  390. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  391. {
  392. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  393. if (qdf_unlikely(!seg_desc)) {
  394. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  395. __func__, __LINE__);
  396. qdf_assert(0);
  397. } else if (qdf_unlikely(!num_seg_desc)) {
  398. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  399. __func__, __LINE__);
  400. qdf_assert(0);
  401. } else {
  402. bool is_last_seg;
  403. /* no tso segment left to do dma unmap */
  404. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  405. return;
  406. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  407. true : false;
  408. qdf_nbuf_unmap_tso_segment(soc->osdev,
  409. seg_desc, is_last_seg);
  410. num_seg_desc->num_seg.tso_cmn_num_seg--;
  411. }
  412. }
  413. /**
  414. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  415. * back to the freelist
  416. *
  417. * @soc - soc device handle
  418. * @tx_desc - Tx software descriptor
  419. */
  420. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  421. struct dp_tx_desc_s *tx_desc)
  422. {
  423. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  424. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  425. dp_tx_err("SO desc is NULL!");
  426. qdf_assert(0);
  427. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  428. dp_tx_err("TSO num desc is NULL!");
  429. qdf_assert(0);
  430. } else {
  431. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  432. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  433. msdu_ext_desc->tso_num_desc;
  434. /* Add the tso num segment into the free list */
  435. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  436. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  437. tx_desc->msdu_ext_desc->
  438. tso_num_desc);
  439. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  440. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  441. }
  442. /* Add the tso segment into the free list*/
  443. dp_tx_tso_desc_free(soc,
  444. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  445. tso_desc);
  446. tx_desc->msdu_ext_desc->tso_desc = NULL;
  447. }
  448. }
  449. #else
  450. static void dp_tx_tso_unmap_segment(
  451. struct dp_soc *soc,
  452. struct qdf_tso_seg_elem_t *seg_desc,
  453. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  454. {
  455. }
  456. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  457. struct dp_tx_desc_s *tx_desc)
  458. {
  459. }
  460. #endif
  461. /**
  462. * dp_tx_desc_release() - Release Tx Descriptor
  463. * @tx_desc : Tx Descriptor
  464. * @desc_pool_id: Descriptor Pool ID
  465. *
  466. * Deallocate all resources attached to Tx descriptor and free the Tx
  467. * descriptor.
  468. *
  469. * Return:
  470. */
  471. void
  472. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  473. {
  474. struct dp_pdev *pdev = tx_desc->pdev;
  475. struct dp_soc *soc;
  476. uint8_t comp_status = 0;
  477. qdf_assert(pdev);
  478. soc = pdev->soc;
  479. dp_tx_outstanding_dec(pdev);
  480. if (tx_desc->msdu_ext_desc) {
  481. if (tx_desc->frm_type == dp_tx_frm_tso)
  482. dp_tx_tso_desc_release(soc, tx_desc);
  483. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  484. dp_tx_me_free_buf(tx_desc->pdev,
  485. tx_desc->msdu_ext_desc->me_buffer);
  486. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  487. }
  488. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  489. qdf_atomic_dec(&soc->num_tx_exception);
  490. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  491. tx_desc->buffer_src)
  492. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  493. soc->hal_soc);
  494. else
  495. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  496. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  497. tx_desc->id, comp_status,
  498. qdf_atomic_read(&pdev->num_tx_outstanding));
  499. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  500. return;
  501. }
  502. /**
  503. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  504. * @vdev: DP vdev Handle
  505. * @nbuf: skb
  506. * @msdu_info: msdu_info required to create HTT metadata
  507. *
  508. * Prepares and fills HTT metadata in the frame pre-header for special frames
  509. * that should be transmitted using varying transmit parameters.
  510. * There are 2 VDEV modes that currently needs this special metadata -
  511. * 1) Mesh Mode
  512. * 2) DSRC Mode
  513. *
  514. * Return: HTT metadata size
  515. *
  516. */
  517. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  518. struct dp_tx_msdu_info_s *msdu_info)
  519. {
  520. uint32_t *meta_data = msdu_info->meta_data;
  521. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  522. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  523. uint8_t htt_desc_size;
  524. /* Size rounded of multiple of 8 bytes */
  525. uint8_t htt_desc_size_aligned;
  526. uint8_t *hdr = NULL;
  527. /*
  528. * Metadata - HTT MSDU Extension header
  529. */
  530. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  531. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  532. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  533. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  534. meta_data[0])) {
  535. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  536. htt_desc_size_aligned)) {
  537. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  538. htt_desc_size_aligned);
  539. if (!nbuf) {
  540. /*
  541. * qdf_nbuf_realloc_headroom won't do skb_clone
  542. * as skb_realloc_headroom does. so, no free is
  543. * needed here.
  544. */
  545. DP_STATS_INC(vdev,
  546. tx_i.dropped.headroom_insufficient,
  547. 1);
  548. qdf_print(" %s[%d] skb_realloc_headroom failed",
  549. __func__, __LINE__);
  550. return 0;
  551. }
  552. }
  553. /* Fill and add HTT metaheader */
  554. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  555. if (!hdr) {
  556. dp_tx_err("Error in filling HTT metadata");
  557. return 0;
  558. }
  559. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  560. } else if (vdev->opmode == wlan_op_mode_ocb) {
  561. /* Todo - Add support for DSRC */
  562. }
  563. return htt_desc_size_aligned;
  564. }
  565. /**
  566. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  567. * @tso_seg: TSO segment to process
  568. * @ext_desc: Pointer to MSDU extension descriptor
  569. *
  570. * Return: void
  571. */
  572. #if defined(FEATURE_TSO)
  573. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  574. void *ext_desc)
  575. {
  576. uint8_t num_frag;
  577. uint32_t tso_flags;
  578. /*
  579. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  580. * tcp_flag_mask
  581. *
  582. * Checksum enable flags are set in TCL descriptor and not in Extension
  583. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  584. */
  585. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  586. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  587. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  588. tso_seg->tso_flags.ip_len);
  589. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  590. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  591. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  592. uint32_t lo = 0;
  593. uint32_t hi = 0;
  594. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  595. (tso_seg->tso_frags[num_frag].length));
  596. qdf_dmaaddr_to_32s(
  597. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  598. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  599. tso_seg->tso_frags[num_frag].length);
  600. }
  601. return;
  602. }
  603. #else
  604. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  605. void *ext_desc)
  606. {
  607. return;
  608. }
  609. #endif
  610. #if defined(FEATURE_TSO)
  611. /**
  612. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  613. * allocated and free them
  614. *
  615. * @soc: soc handle
  616. * @free_seg: list of tso segments
  617. * @msdu_info: msdu descriptor
  618. *
  619. * Return - void
  620. */
  621. static void dp_tx_free_tso_seg_list(
  622. struct dp_soc *soc,
  623. struct qdf_tso_seg_elem_t *free_seg,
  624. struct dp_tx_msdu_info_s *msdu_info)
  625. {
  626. struct qdf_tso_seg_elem_t *next_seg;
  627. while (free_seg) {
  628. next_seg = free_seg->next;
  629. dp_tx_tso_desc_free(soc,
  630. msdu_info->tx_queue.desc_pool_id,
  631. free_seg);
  632. free_seg = next_seg;
  633. }
  634. }
  635. /**
  636. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  637. * allocated and free them
  638. *
  639. * @soc: soc handle
  640. * @free_num_seg: list of tso number segments
  641. * @msdu_info: msdu descriptor
  642. * Return - void
  643. */
  644. static void dp_tx_free_tso_num_seg_list(
  645. struct dp_soc *soc,
  646. struct qdf_tso_num_seg_elem_t *free_num_seg,
  647. struct dp_tx_msdu_info_s *msdu_info)
  648. {
  649. struct qdf_tso_num_seg_elem_t *next_num_seg;
  650. while (free_num_seg) {
  651. next_num_seg = free_num_seg->next;
  652. dp_tso_num_seg_free(soc,
  653. msdu_info->tx_queue.desc_pool_id,
  654. free_num_seg);
  655. free_num_seg = next_num_seg;
  656. }
  657. }
  658. /**
  659. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  660. * do dma unmap for each segment
  661. *
  662. * @soc: soc handle
  663. * @free_seg: list of tso segments
  664. * @num_seg_desc: tso number segment descriptor
  665. *
  666. * Return - void
  667. */
  668. static void dp_tx_unmap_tso_seg_list(
  669. struct dp_soc *soc,
  670. struct qdf_tso_seg_elem_t *free_seg,
  671. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  672. {
  673. struct qdf_tso_seg_elem_t *next_seg;
  674. if (qdf_unlikely(!num_seg_desc)) {
  675. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  676. return;
  677. }
  678. while (free_seg) {
  679. next_seg = free_seg->next;
  680. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  681. free_seg = next_seg;
  682. }
  683. }
  684. #ifdef FEATURE_TSO_STATS
  685. /**
  686. * dp_tso_get_stats_idx: Retrieve the tso packet id
  687. * @pdev - pdev handle
  688. *
  689. * Return: id
  690. */
  691. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  692. {
  693. uint32_t stats_idx;
  694. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  695. % CDP_MAX_TSO_PACKETS);
  696. return stats_idx;
  697. }
  698. #else
  699. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  700. {
  701. return 0;
  702. }
  703. #endif /* FEATURE_TSO_STATS */
  704. /**
  705. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  706. * free the tso segments descriptor and
  707. * tso num segments descriptor
  708. *
  709. * @soc: soc handle
  710. * @msdu_info: msdu descriptor
  711. * @tso_seg_unmap: flag to show if dma unmap is necessary
  712. *
  713. * Return - void
  714. */
  715. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  716. struct dp_tx_msdu_info_s *msdu_info,
  717. bool tso_seg_unmap)
  718. {
  719. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  720. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  721. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  722. tso_info->tso_num_seg_list;
  723. /* do dma unmap for each segment */
  724. if (tso_seg_unmap)
  725. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  726. /* free all tso number segment descriptor though looks only have 1 */
  727. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  728. /* free all tso segment descriptor */
  729. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  730. }
  731. /**
  732. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  733. * @vdev: virtual device handle
  734. * @msdu: network buffer
  735. * @msdu_info: meta data associated with the msdu
  736. *
  737. * Return: QDF_STATUS_SUCCESS success
  738. */
  739. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  740. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  741. {
  742. struct qdf_tso_seg_elem_t *tso_seg;
  743. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  744. struct dp_soc *soc = vdev->pdev->soc;
  745. struct dp_pdev *pdev = vdev->pdev;
  746. struct qdf_tso_info_t *tso_info;
  747. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  748. tso_info = &msdu_info->u.tso_info;
  749. tso_info->curr_seg = NULL;
  750. tso_info->tso_seg_list = NULL;
  751. tso_info->num_segs = num_seg;
  752. msdu_info->frm_type = dp_tx_frm_tso;
  753. tso_info->tso_num_seg_list = NULL;
  754. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  755. while (num_seg) {
  756. tso_seg = dp_tx_tso_desc_alloc(
  757. soc, msdu_info->tx_queue.desc_pool_id);
  758. if (tso_seg) {
  759. tso_seg->next = tso_info->tso_seg_list;
  760. tso_info->tso_seg_list = tso_seg;
  761. num_seg--;
  762. } else {
  763. dp_err_rl("Failed to alloc tso seg desc");
  764. DP_STATS_INC_PKT(vdev->pdev,
  765. tso_stats.tso_no_mem_dropped, 1,
  766. qdf_nbuf_len(msdu));
  767. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  768. return QDF_STATUS_E_NOMEM;
  769. }
  770. }
  771. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  772. tso_num_seg = dp_tso_num_seg_alloc(soc,
  773. msdu_info->tx_queue.desc_pool_id);
  774. if (tso_num_seg) {
  775. tso_num_seg->next = tso_info->tso_num_seg_list;
  776. tso_info->tso_num_seg_list = tso_num_seg;
  777. } else {
  778. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  779. __func__);
  780. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  781. return QDF_STATUS_E_NOMEM;
  782. }
  783. msdu_info->num_seg =
  784. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  785. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  786. msdu_info->num_seg);
  787. if (!(msdu_info->num_seg)) {
  788. /*
  789. * Free allocated TSO seg desc and number seg desc,
  790. * do unmap for segments if dma map has done.
  791. */
  792. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  793. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  794. return QDF_STATUS_E_INVAL;
  795. }
  796. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  797. msdu, 0, DP_TX_DESC_MAP);
  798. tso_info->curr_seg = tso_info->tso_seg_list;
  799. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  800. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  801. msdu, msdu_info->num_seg);
  802. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  803. tso_info->msdu_stats_idx);
  804. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  805. return QDF_STATUS_SUCCESS;
  806. }
  807. #else
  808. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  809. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  810. {
  811. return QDF_STATUS_E_NOMEM;
  812. }
  813. #endif
  814. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  815. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  816. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  817. /**
  818. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  819. * @vdev: DP Vdev handle
  820. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  821. * @desc_pool_id: Descriptor Pool ID
  822. *
  823. * Return:
  824. */
  825. static
  826. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  827. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  828. {
  829. uint8_t i;
  830. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  831. struct dp_tx_seg_info_s *seg_info;
  832. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  833. struct dp_soc *soc = vdev->pdev->soc;
  834. /* Allocate an extension descriptor */
  835. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  836. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  837. if (!msdu_ext_desc) {
  838. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  839. return NULL;
  840. }
  841. if (msdu_info->exception_fw &&
  842. qdf_unlikely(vdev->mesh_vdev)) {
  843. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  844. &msdu_info->meta_data[0],
  845. sizeof(struct htt_tx_msdu_desc_ext2_t));
  846. qdf_atomic_inc(&soc->num_tx_exception);
  847. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  848. }
  849. switch (msdu_info->frm_type) {
  850. case dp_tx_frm_sg:
  851. case dp_tx_frm_me:
  852. case dp_tx_frm_raw:
  853. seg_info = msdu_info->u.sg_info.curr_seg;
  854. /* Update the buffer pointers in MSDU Extension Descriptor */
  855. for (i = 0; i < seg_info->frag_cnt; i++) {
  856. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  857. seg_info->frags[i].paddr_lo,
  858. seg_info->frags[i].paddr_hi,
  859. seg_info->frags[i].len);
  860. }
  861. break;
  862. case dp_tx_frm_tso:
  863. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  864. &cached_ext_desc[0]);
  865. break;
  866. default:
  867. break;
  868. }
  869. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  870. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  871. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  872. msdu_ext_desc->vaddr);
  873. return msdu_ext_desc;
  874. }
  875. /**
  876. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  877. *
  878. * @skb: skb to be traced
  879. * @msdu_id: msdu_id of the packet
  880. * @vdev_id: vdev_id of the packet
  881. *
  882. * Return: None
  883. */
  884. #ifdef DP_DISABLE_TX_PKT_TRACE
  885. static void dp_tx_trace_pkt(struct dp_soc *soc,
  886. qdf_nbuf_t skb, uint16_t msdu_id,
  887. uint8_t vdev_id)
  888. {
  889. }
  890. #else
  891. static void dp_tx_trace_pkt(struct dp_soc *soc,
  892. qdf_nbuf_t skb, uint16_t msdu_id,
  893. uint8_t vdev_id)
  894. {
  895. if (dp_is_tput_high(soc))
  896. return;
  897. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  898. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  899. DPTRACE(qdf_dp_trace_ptr(skb,
  900. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  901. QDF_TRACE_DEFAULT_PDEV_ID,
  902. qdf_nbuf_data_addr(skb),
  903. sizeof(qdf_nbuf_data(skb)),
  904. msdu_id, vdev_id, 0));
  905. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  906. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  907. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  908. msdu_id, QDF_TX));
  909. }
  910. #endif
  911. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  912. /**
  913. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  914. * exception by the upper layer (OS_IF)
  915. * @soc: DP soc handle
  916. * @nbuf: packet to be transmitted
  917. *
  918. * Returns: 1 if the packet is marked as exception,
  919. * 0, if the packet is not marked as exception.
  920. */
  921. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  922. qdf_nbuf_t nbuf)
  923. {
  924. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  925. }
  926. #else
  927. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  928. qdf_nbuf_t nbuf)
  929. {
  930. return 0;
  931. }
  932. #endif
  933. /**
  934. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  935. * @vdev: DP vdev handle
  936. * @nbuf: skb
  937. * @desc_pool_id: Descriptor pool ID
  938. * @meta_data: Metadata to the fw
  939. * @tx_exc_metadata: Handle that holds exception path metadata
  940. * Allocate and prepare Tx descriptor with msdu information.
  941. *
  942. * Return: Pointer to Tx Descriptor on success,
  943. * NULL on failure
  944. */
  945. static
  946. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  947. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  948. struct dp_tx_msdu_info_s *msdu_info,
  949. struct cdp_tx_exception_metadata *tx_exc_metadata)
  950. {
  951. uint8_t align_pad;
  952. uint8_t is_exception = 0;
  953. uint8_t htt_hdr_size;
  954. struct dp_tx_desc_s *tx_desc;
  955. struct dp_pdev *pdev = vdev->pdev;
  956. struct dp_soc *soc = pdev->soc;
  957. if (dp_tx_limit_check(vdev))
  958. return NULL;
  959. /* Allocate software Tx descriptor */
  960. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  961. if (qdf_unlikely(!tx_desc)) {
  962. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  963. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  964. return NULL;
  965. }
  966. dp_tx_outstanding_inc(pdev);
  967. /* Initialize the SW tx descriptor */
  968. tx_desc->nbuf = nbuf;
  969. tx_desc->frm_type = dp_tx_frm_std;
  970. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  971. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  972. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  973. tx_desc->vdev_id = vdev->vdev_id;
  974. tx_desc->pdev = pdev;
  975. tx_desc->msdu_ext_desc = NULL;
  976. tx_desc->pkt_offset = 0;
  977. tx_desc->length = qdf_nbuf_headlen(nbuf);
  978. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  979. if (qdf_unlikely(vdev->multipass_en)) {
  980. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  981. goto failure;
  982. }
  983. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  984. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  985. is_exception = 1;
  986. /*
  987. * For special modes (vdev_type == ocb or mesh), data frames should be
  988. * transmitted using varying transmit parameters (tx spec) which include
  989. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  990. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  991. * These frames are sent as exception packets to firmware.
  992. *
  993. * HW requirement is that metadata should always point to a
  994. * 8-byte aligned address. So we add alignment pad to start of buffer.
  995. * HTT Metadata should be ensured to be multiple of 8-bytes,
  996. * to get 8-byte aligned start address along with align_pad added
  997. *
  998. * |-----------------------------|
  999. * | |
  1000. * |-----------------------------| <-----Buffer Pointer Address given
  1001. * | | ^ in HW descriptor (aligned)
  1002. * | HTT Metadata | |
  1003. * | | |
  1004. * | | | Packet Offset given in descriptor
  1005. * | | |
  1006. * |-----------------------------| |
  1007. * | Alignment Pad | v
  1008. * |-----------------------------| <----- Actual buffer start address
  1009. * | SKB Data | (Unaligned)
  1010. * | |
  1011. * | |
  1012. * | |
  1013. * | |
  1014. * | |
  1015. * |-----------------------------|
  1016. */
  1017. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1018. (vdev->opmode == wlan_op_mode_ocb) ||
  1019. (tx_exc_metadata &&
  1020. tx_exc_metadata->is_tx_sniffer)) {
  1021. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1022. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1023. DP_STATS_INC(vdev,
  1024. tx_i.dropped.headroom_insufficient, 1);
  1025. goto failure;
  1026. }
  1027. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1028. dp_tx_err("qdf_nbuf_push_head failed");
  1029. goto failure;
  1030. }
  1031. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1032. msdu_info);
  1033. if (htt_hdr_size == 0)
  1034. goto failure;
  1035. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1036. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1037. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1038. is_exception = 1;
  1039. tx_desc->length -= tx_desc->pkt_offset;
  1040. }
  1041. #if !TQM_BYPASS_WAR
  1042. if (is_exception || tx_exc_metadata)
  1043. #endif
  1044. {
  1045. /* Temporary WAR due to TQM VP issues */
  1046. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1047. qdf_atomic_inc(&soc->num_tx_exception);
  1048. }
  1049. return tx_desc;
  1050. failure:
  1051. dp_tx_desc_release(tx_desc, desc_pool_id);
  1052. return NULL;
  1053. }
  1054. /**
  1055. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1056. * @vdev: DP vdev handle
  1057. * @nbuf: skb
  1058. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1059. * @desc_pool_id : Descriptor Pool ID
  1060. *
  1061. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1062. * information. For frames wth fragments, allocate and prepare
  1063. * an MSDU extension descriptor
  1064. *
  1065. * Return: Pointer to Tx Descriptor on success,
  1066. * NULL on failure
  1067. */
  1068. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1069. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1070. uint8_t desc_pool_id)
  1071. {
  1072. struct dp_tx_desc_s *tx_desc;
  1073. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1074. struct dp_pdev *pdev = vdev->pdev;
  1075. struct dp_soc *soc = pdev->soc;
  1076. if (dp_tx_limit_check(vdev))
  1077. return NULL;
  1078. /* Allocate software Tx descriptor */
  1079. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1080. if (!tx_desc) {
  1081. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1082. return NULL;
  1083. }
  1084. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1085. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1086. dp_tx_outstanding_inc(pdev);
  1087. /* Initialize the SW tx descriptor */
  1088. tx_desc->nbuf = nbuf;
  1089. tx_desc->frm_type = msdu_info->frm_type;
  1090. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1091. tx_desc->vdev_id = vdev->vdev_id;
  1092. tx_desc->pdev = pdev;
  1093. tx_desc->pkt_offset = 0;
  1094. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1095. /* Handle scattered frames - TSO/SG/ME */
  1096. /* Allocate and prepare an extension descriptor for scattered frames */
  1097. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1098. if (!msdu_ext_desc) {
  1099. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1100. goto failure;
  1101. }
  1102. #if TQM_BYPASS_WAR
  1103. /* Temporary WAR due to TQM VP issues */
  1104. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1105. qdf_atomic_inc(&soc->num_tx_exception);
  1106. #endif
  1107. if (qdf_unlikely(msdu_info->exception_fw))
  1108. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1109. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1110. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1111. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1112. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1113. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1114. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1115. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1116. else
  1117. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1118. return tx_desc;
  1119. failure:
  1120. dp_tx_desc_release(tx_desc, desc_pool_id);
  1121. return NULL;
  1122. }
  1123. /**
  1124. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1125. * @vdev: DP vdev handle
  1126. * @nbuf: buffer pointer
  1127. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1128. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1129. * descriptor
  1130. *
  1131. * Return:
  1132. */
  1133. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1134. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1135. {
  1136. qdf_nbuf_t curr_nbuf = NULL;
  1137. uint16_t total_len = 0;
  1138. qdf_dma_addr_t paddr;
  1139. int32_t i;
  1140. int32_t mapped_buf_num = 0;
  1141. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1142. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1143. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1144. /* Continue only if frames are of DATA type */
  1145. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1146. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1147. dp_tx_debug("Pkt. recd is of not data type");
  1148. goto error;
  1149. }
  1150. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1151. if (vdev->raw_mode_war &&
  1152. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1153. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1154. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1155. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1156. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1157. /*
  1158. * Number of nbuf's must not exceed the size of the frags
  1159. * array in seg_info.
  1160. */
  1161. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1162. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1163. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1164. goto error;
  1165. }
  1166. if (QDF_STATUS_SUCCESS !=
  1167. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1168. curr_nbuf,
  1169. QDF_DMA_TO_DEVICE,
  1170. curr_nbuf->len)) {
  1171. dp_tx_err("%s dma map error ", __func__);
  1172. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1173. goto error;
  1174. }
  1175. /* Update the count of mapped nbuf's */
  1176. mapped_buf_num++;
  1177. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1178. seg_info->frags[i].paddr_lo = paddr;
  1179. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1180. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1181. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1182. total_len += qdf_nbuf_len(curr_nbuf);
  1183. }
  1184. seg_info->frag_cnt = i;
  1185. seg_info->total_len = total_len;
  1186. seg_info->next = NULL;
  1187. sg_info->curr_seg = seg_info;
  1188. msdu_info->frm_type = dp_tx_frm_raw;
  1189. msdu_info->num_seg = 1;
  1190. return nbuf;
  1191. error:
  1192. i = 0;
  1193. while (nbuf) {
  1194. curr_nbuf = nbuf;
  1195. if (i < mapped_buf_num) {
  1196. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1197. QDF_DMA_TO_DEVICE,
  1198. curr_nbuf->len);
  1199. i++;
  1200. }
  1201. nbuf = qdf_nbuf_next(nbuf);
  1202. qdf_nbuf_free(curr_nbuf);
  1203. }
  1204. return NULL;
  1205. }
  1206. /**
  1207. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1208. * @soc: DP soc handle
  1209. * @nbuf: Buffer pointer
  1210. *
  1211. * unmap the chain of nbufs that belong to this RAW frame.
  1212. *
  1213. * Return: None
  1214. */
  1215. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1216. qdf_nbuf_t nbuf)
  1217. {
  1218. qdf_nbuf_t cur_nbuf = nbuf;
  1219. do {
  1220. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1221. QDF_DMA_TO_DEVICE,
  1222. cur_nbuf->len);
  1223. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1224. } while (cur_nbuf);
  1225. }
  1226. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1227. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1228. qdf_nbuf_t nbuf)
  1229. {
  1230. qdf_nbuf_t nbuf_local;
  1231. struct dp_vdev *vdev_local = vdev_hdl;
  1232. do {
  1233. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1234. break;
  1235. nbuf_local = nbuf;
  1236. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1237. htt_cmn_pkt_type_raw))
  1238. break;
  1239. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1240. break;
  1241. else if (qdf_nbuf_is_tso((nbuf_local)))
  1242. break;
  1243. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1244. (nbuf_local),
  1245. NULL, 1, 0);
  1246. } while (0);
  1247. }
  1248. #endif
  1249. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1250. /**
  1251. * dp_tx_update_stats() - Update soc level tx stats
  1252. * @soc: DP soc handle
  1253. * @nbuf: packet being transmitted
  1254. *
  1255. * Returns: none
  1256. */
  1257. void dp_tx_update_stats(struct dp_soc *soc,
  1258. qdf_nbuf_t nbuf)
  1259. {
  1260. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1261. }
  1262. int
  1263. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1264. struct dp_tx_desc_s *tx_desc,
  1265. uint8_t tid)
  1266. {
  1267. struct dp_swlm *swlm = &soc->swlm;
  1268. union swlm_data swlm_query_data;
  1269. struct dp_swlm_tcl_data tcl_data;
  1270. QDF_STATUS status;
  1271. int ret;
  1272. if (qdf_unlikely(!swlm->is_enabled))
  1273. return 0;
  1274. tcl_data.nbuf = tx_desc->nbuf;
  1275. tcl_data.tid = tid;
  1276. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1277. swlm_query_data.tcl_data = &tcl_data;
  1278. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1279. if (QDF_IS_STATUS_ERROR(status)) {
  1280. dp_swlm_tcl_reset_session_data(soc);
  1281. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1282. return 0;
  1283. }
  1284. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1285. if (ret) {
  1286. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1287. } else {
  1288. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1289. }
  1290. return ret;
  1291. }
  1292. void
  1293. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1294. int coalesce)
  1295. {
  1296. if (coalesce)
  1297. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1298. else
  1299. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1300. }
  1301. #endif
  1302. #ifdef FEATURE_RUNTIME_PM
  1303. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1304. {
  1305. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1306. }
  1307. /**
  1308. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1309. * @soc: Datapath soc handle
  1310. * @hal_ring_hdl: HAL ring handle
  1311. * @coalesce: Coalesce the current write or not
  1312. *
  1313. * Wrapper for HAL ring access end for data transmission for
  1314. * FEATURE_RUNTIME_PM
  1315. *
  1316. * Returns: none
  1317. */
  1318. void
  1319. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1320. hal_ring_handle_t hal_ring_hdl,
  1321. int coalesce)
  1322. {
  1323. int ret;
  1324. /*
  1325. * Avoid runtime get and put APIs under high throughput scenarios.
  1326. */
  1327. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1328. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1329. return;
  1330. }
  1331. ret = hif_pm_runtime_get(soc->hif_handle,
  1332. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1333. switch (ret) {
  1334. case 0:
  1335. if (hif_system_pm_state_check(soc->hif_handle)) {
  1336. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1337. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1338. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1339. } else {
  1340. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1341. }
  1342. hif_pm_runtime_put(soc->hif_handle,
  1343. RTPM_ID_DW_TX_HW_ENQUEUE);
  1344. break;
  1345. /*
  1346. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1347. * take the dp runtime refcount using dp_runtime_get,
  1348. * check link state,if up, write TX ring HP, else just set flush event.
  1349. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1350. * zero or time out, then flush pending tx.
  1351. */
  1352. case -EBUSY:
  1353. case -EINPROGRESS:
  1354. dp_runtime_get(soc);
  1355. if (hif_pm_get_link_state(soc->hif_handle) ==
  1356. HIF_PM_LINK_STATE_UP) {
  1357. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1358. } else {
  1359. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1360. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1361. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1362. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1363. }
  1364. dp_runtime_put(soc);
  1365. break;
  1366. default:
  1367. dp_runtime_get(soc);
  1368. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1369. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1370. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1371. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1372. dp_runtime_put(soc);
  1373. }
  1374. }
  1375. #else
  1376. #ifdef DP_POWER_SAVE
  1377. void
  1378. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1379. hal_ring_handle_t hal_ring_hdl,
  1380. int coalesce)
  1381. {
  1382. if (hif_system_pm_state_check(soc->hif_handle)) {
  1383. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1384. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1385. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1386. } else {
  1387. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1388. }
  1389. }
  1390. #endif
  1391. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1392. {
  1393. return 0;
  1394. }
  1395. #endif
  1396. /**
  1397. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1398. * @vdev: DP vdev handle
  1399. * @nbuf: skb
  1400. *
  1401. * Extract the DSCP or PCP information from frame and map into TID value.
  1402. *
  1403. * Return: void
  1404. */
  1405. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1406. struct dp_tx_msdu_info_s *msdu_info)
  1407. {
  1408. uint8_t tos = 0, dscp_tid_override = 0;
  1409. uint8_t *hdr_ptr, *L3datap;
  1410. uint8_t is_mcast = 0;
  1411. qdf_ether_header_t *eh = NULL;
  1412. qdf_ethervlan_header_t *evh = NULL;
  1413. uint16_t ether_type;
  1414. qdf_llc_t *llcHdr;
  1415. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1416. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1417. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1418. eh = (qdf_ether_header_t *)nbuf->data;
  1419. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1420. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1421. } else {
  1422. qdf_dot3_qosframe_t *qos_wh =
  1423. (qdf_dot3_qosframe_t *) nbuf->data;
  1424. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1425. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1426. return;
  1427. }
  1428. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1429. ether_type = eh->ether_type;
  1430. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1431. /*
  1432. * Check if packet is dot3 or eth2 type.
  1433. */
  1434. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1435. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1436. sizeof(*llcHdr));
  1437. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1438. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1439. sizeof(*llcHdr);
  1440. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1441. + sizeof(*llcHdr) +
  1442. sizeof(qdf_net_vlanhdr_t));
  1443. } else {
  1444. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1445. sizeof(*llcHdr);
  1446. }
  1447. } else {
  1448. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1449. evh = (qdf_ethervlan_header_t *) eh;
  1450. ether_type = evh->ether_type;
  1451. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1452. }
  1453. }
  1454. /*
  1455. * Find priority from IP TOS DSCP field
  1456. */
  1457. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1458. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1459. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1460. /* Only for unicast frames */
  1461. if (!is_mcast) {
  1462. /* send it on VO queue */
  1463. msdu_info->tid = DP_VO_TID;
  1464. }
  1465. } else {
  1466. /*
  1467. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1468. * from TOS byte.
  1469. */
  1470. tos = ip->ip_tos;
  1471. dscp_tid_override = 1;
  1472. }
  1473. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1474. /* TODO
  1475. * use flowlabel
  1476. *igmpmld cases to be handled in phase 2
  1477. */
  1478. unsigned long ver_pri_flowlabel;
  1479. unsigned long pri;
  1480. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1481. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1482. DP_IPV6_PRIORITY_SHIFT;
  1483. tos = pri;
  1484. dscp_tid_override = 1;
  1485. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1486. msdu_info->tid = DP_VO_TID;
  1487. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1488. /* Only for unicast frames */
  1489. if (!is_mcast) {
  1490. /* send ucast arp on VO queue */
  1491. msdu_info->tid = DP_VO_TID;
  1492. }
  1493. }
  1494. /*
  1495. * Assign all MCAST packets to BE
  1496. */
  1497. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1498. if (is_mcast) {
  1499. tos = 0;
  1500. dscp_tid_override = 1;
  1501. }
  1502. }
  1503. if (dscp_tid_override == 1) {
  1504. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1505. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1506. }
  1507. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1508. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1509. return;
  1510. }
  1511. /**
  1512. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1513. * @vdev: DP vdev handle
  1514. * @nbuf: skb
  1515. *
  1516. * Software based TID classification is required when more than 2 DSCP-TID
  1517. * mapping tables are needed.
  1518. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1519. *
  1520. * Return: void
  1521. */
  1522. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1523. struct dp_tx_msdu_info_s *msdu_info)
  1524. {
  1525. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1526. /*
  1527. * skip_sw_tid_classification flag will set in below cases-
  1528. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1529. * 2. hlos_tid_override enabled for vdev
  1530. * 3. mesh mode enabled for vdev
  1531. */
  1532. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1533. /* Update tid in msdu_info from skb priority */
  1534. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1535. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1536. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1537. if (tid == DP_TX_INVALID_QOS_TAG)
  1538. return;
  1539. msdu_info->tid = tid;
  1540. return;
  1541. }
  1542. return;
  1543. }
  1544. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1545. }
  1546. #ifdef FEATURE_WLAN_TDLS
  1547. /**
  1548. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1549. * @soc: datapath SOC
  1550. * @vdev: datapath vdev
  1551. * @tx_desc: TX descriptor
  1552. *
  1553. * Return: None
  1554. */
  1555. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1556. struct dp_vdev *vdev,
  1557. struct dp_tx_desc_s *tx_desc)
  1558. {
  1559. if (vdev) {
  1560. if (vdev->is_tdls_frame) {
  1561. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1562. vdev->is_tdls_frame = false;
  1563. }
  1564. }
  1565. }
  1566. /**
  1567. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1568. * @soc: dp_soc handle
  1569. * @tx_desc: TX descriptor
  1570. * @vdev: datapath vdev handle
  1571. *
  1572. * Return: None
  1573. */
  1574. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1575. struct dp_tx_desc_s *tx_desc)
  1576. {
  1577. struct hal_tx_completion_status ts = {0};
  1578. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1579. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1580. DP_MOD_ID_TDLS);
  1581. if (qdf_unlikely(!vdev)) {
  1582. dp_err_rl("vdev is null!");
  1583. goto error;
  1584. }
  1585. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1586. if (vdev->tx_non_std_data_callback.func) {
  1587. qdf_nbuf_set_next(nbuf, NULL);
  1588. vdev->tx_non_std_data_callback.func(
  1589. vdev->tx_non_std_data_callback.ctxt,
  1590. nbuf, ts.status);
  1591. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1592. return;
  1593. } else {
  1594. dp_err_rl("callback func is null");
  1595. }
  1596. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1597. error:
  1598. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1599. qdf_nbuf_free(nbuf);
  1600. }
  1601. /**
  1602. * dp_tx_msdu_single_map() - do nbuf map
  1603. * @vdev: DP vdev handle
  1604. * @tx_desc: DP TX descriptor pointer
  1605. * @nbuf: skb pointer
  1606. *
  1607. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1608. * operation done in other component.
  1609. *
  1610. * Return: QDF_STATUS
  1611. */
  1612. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1613. struct dp_tx_desc_s *tx_desc,
  1614. qdf_nbuf_t nbuf)
  1615. {
  1616. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1617. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1618. nbuf,
  1619. QDF_DMA_TO_DEVICE,
  1620. nbuf->len);
  1621. else
  1622. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1623. QDF_DMA_TO_DEVICE);
  1624. }
  1625. #else
  1626. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1627. struct dp_vdev *vdev,
  1628. struct dp_tx_desc_s *tx_desc)
  1629. {
  1630. }
  1631. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1632. struct dp_tx_desc_s *tx_desc)
  1633. {
  1634. }
  1635. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1636. struct dp_tx_desc_s *tx_desc,
  1637. qdf_nbuf_t nbuf)
  1638. {
  1639. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1640. nbuf,
  1641. QDF_DMA_TO_DEVICE,
  1642. nbuf->len);
  1643. }
  1644. #endif
  1645. #ifdef MESH_MODE_SUPPORT
  1646. /**
  1647. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1648. * @soc: datapath SOC
  1649. * @vdev: datapath vdev
  1650. * @tx_desc: TX descriptor
  1651. *
  1652. * Return: None
  1653. */
  1654. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1655. struct dp_vdev *vdev,
  1656. struct dp_tx_desc_s *tx_desc)
  1657. {
  1658. if (qdf_unlikely(vdev->mesh_vdev))
  1659. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1660. }
  1661. /**
  1662. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1663. * @soc: dp_soc handle
  1664. * @tx_desc: TX descriptor
  1665. * @vdev: datapath vdev handle
  1666. *
  1667. * Return: None
  1668. */
  1669. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1670. struct dp_tx_desc_s *tx_desc)
  1671. {
  1672. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1673. struct dp_vdev *vdev = NULL;
  1674. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1675. qdf_nbuf_free(nbuf);
  1676. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1677. } else {
  1678. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1679. DP_MOD_ID_MESH);
  1680. if (vdev && vdev->osif_tx_free_ext)
  1681. vdev->osif_tx_free_ext((nbuf));
  1682. else
  1683. qdf_nbuf_free(nbuf);
  1684. if (vdev)
  1685. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1686. }
  1687. }
  1688. #else
  1689. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1690. struct dp_vdev *vdev,
  1691. struct dp_tx_desc_s *tx_desc)
  1692. {
  1693. }
  1694. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1695. struct dp_tx_desc_s *tx_desc)
  1696. {
  1697. }
  1698. #endif
  1699. /**
  1700. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1701. * @vdev: DP vdev handle
  1702. * @nbuf: skb
  1703. *
  1704. * Return: 1 if frame needs to be dropped else 0
  1705. */
  1706. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1707. {
  1708. struct dp_pdev *pdev = NULL;
  1709. struct dp_ast_entry *src_ast_entry = NULL;
  1710. struct dp_ast_entry *dst_ast_entry = NULL;
  1711. struct dp_soc *soc = NULL;
  1712. qdf_assert(vdev);
  1713. pdev = vdev->pdev;
  1714. qdf_assert(pdev);
  1715. soc = pdev->soc;
  1716. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1717. (soc, dstmac, vdev->pdev->pdev_id);
  1718. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1719. (soc, srcmac, vdev->pdev->pdev_id);
  1720. if (dst_ast_entry && src_ast_entry) {
  1721. if (dst_ast_entry->peer_id ==
  1722. src_ast_entry->peer_id)
  1723. return 1;
  1724. }
  1725. return 0;
  1726. }
  1727. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1728. defined(WLAN_MCAST_MLO)
  1729. /* MLO peer id for reinject*/
  1730. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1731. /* MLO vdev id inc offset */
  1732. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1733. static inline void
  1734. dp_tx_update_mcast_param(uint16_t peer_id,
  1735. uint16_t *htt_tcl_metadata,
  1736. struct dp_vdev *vdev,
  1737. struct dp_tx_msdu_info_s *msdu_info)
  1738. {
  1739. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1740. *htt_tcl_metadata = 0;
  1741. DP_TX_TCL_METADATA_TYPE_SET(
  1742. *htt_tcl_metadata,
  1743. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1744. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1745. msdu_info->gsn);
  1746. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1747. } else {
  1748. msdu_info->vdev_id = vdev->vdev_id;
  1749. }
  1750. }
  1751. #else
  1752. static inline void
  1753. dp_tx_update_mcast_param(uint16_t peer_id,
  1754. uint16_t *htt_tcl_metadata,
  1755. struct dp_vdev *vdev,
  1756. struct dp_tx_msdu_info_s *msdu_info)
  1757. {
  1758. }
  1759. #endif
  1760. /**
  1761. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1762. * @vdev: DP vdev handle
  1763. * @nbuf: skb
  1764. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1765. * @meta_data: Metadata to the fw
  1766. * @tx_q: Tx queue to be used for this Tx frame
  1767. * @peer_id: peer_id of the peer in case of NAWDS frames
  1768. * @tx_exc_metadata: Handle that holds exception path metadata
  1769. *
  1770. * Return: NULL on success,
  1771. * nbuf when it fails to send
  1772. */
  1773. qdf_nbuf_t
  1774. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1775. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1776. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1777. {
  1778. struct dp_pdev *pdev = vdev->pdev;
  1779. struct dp_soc *soc = pdev->soc;
  1780. struct dp_tx_desc_s *tx_desc;
  1781. QDF_STATUS status;
  1782. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1783. uint16_t htt_tcl_metadata = 0;
  1784. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1785. uint8_t tid = msdu_info->tid;
  1786. struct cdp_tid_tx_stats *tid_stats = NULL;
  1787. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1788. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1789. msdu_info, tx_exc_metadata);
  1790. if (!tx_desc) {
  1791. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1792. vdev, tx_q->desc_pool_id);
  1793. drop_code = TX_DESC_ERR;
  1794. goto fail_return;
  1795. }
  1796. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1797. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1798. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1799. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1800. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1801. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1802. DP_TCL_METADATA_TYPE_PEER_BASED);
  1803. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1804. peer_id);
  1805. } else
  1806. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1807. if (msdu_info->exception_fw)
  1808. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1809. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1810. !pdev->enhanced_stats_en);
  1811. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1812. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1813. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1814. /* Handle failure */
  1815. dp_err("qdf_nbuf_map failed");
  1816. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1817. drop_code = TX_DMA_MAP_ERR;
  1818. goto release_desc;
  1819. }
  1820. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1821. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1822. tx_desc->id, DP_TX_DESC_MAP);
  1823. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1824. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1825. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1826. htt_tcl_metadata,
  1827. tx_exc_metadata, msdu_info);
  1828. if (status != QDF_STATUS_SUCCESS) {
  1829. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1830. tx_desc, tx_q->ring_id);
  1831. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1832. tx_desc->id, DP_TX_DESC_UNMAP);
  1833. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1834. QDF_DMA_TO_DEVICE,
  1835. nbuf->len);
  1836. drop_code = TX_HW_ENQUEUE;
  1837. goto release_desc;
  1838. }
  1839. return NULL;
  1840. release_desc:
  1841. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1842. fail_return:
  1843. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1844. tid_stats = &pdev->stats.tid_stats.
  1845. tid_tx_stats[tx_q->ring_id][tid];
  1846. tid_stats->swdrop_cnt[drop_code]++;
  1847. return nbuf;
  1848. }
  1849. /**
  1850. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1851. * @soc: Soc handle
  1852. * @desc: software Tx descriptor to be processed
  1853. *
  1854. * Return: none
  1855. */
  1856. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1857. {
  1858. qdf_nbuf_t nbuf = desc->nbuf;
  1859. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1860. /* nbuf already freed in vdev detach path */
  1861. if (!nbuf)
  1862. return;
  1863. /* If it is TDLS mgmt, don't unmap or free the frame */
  1864. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1865. return dp_non_std_tx_comp_free_buff(soc, desc);
  1866. /* 0 : MSDU buffer, 1 : MLE */
  1867. if (desc->msdu_ext_desc) {
  1868. /* TSO free */
  1869. if (hal_tx_ext_desc_get_tso_enable(
  1870. desc->msdu_ext_desc->vaddr)) {
  1871. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1872. desc->id, DP_TX_COMP_MSDU_EXT);
  1873. dp_tx_tso_seg_history_add(soc,
  1874. desc->msdu_ext_desc->tso_desc,
  1875. desc->nbuf, desc->id, type);
  1876. /* unmap eash TSO seg before free the nbuf */
  1877. dp_tx_tso_unmap_segment(soc,
  1878. desc->msdu_ext_desc->tso_desc,
  1879. desc->msdu_ext_desc->
  1880. tso_num_desc);
  1881. qdf_nbuf_free(nbuf);
  1882. return;
  1883. }
  1884. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  1885. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  1886. qdf_dma_addr_t iova;
  1887. uint32_t frag_len;
  1888. uint32_t i;
  1889. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1890. QDF_DMA_TO_DEVICE,
  1891. qdf_nbuf_headlen(nbuf));
  1892. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  1893. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  1894. &iova,
  1895. &frag_len);
  1896. if (!iova || !frag_len)
  1897. break;
  1898. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  1899. QDF_DMA_TO_DEVICE);
  1900. }
  1901. qdf_nbuf_free(nbuf);
  1902. return;
  1903. }
  1904. }
  1905. /* If it's ME frame, dont unmap the cloned nbuf's */
  1906. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1907. goto nbuf_free;
  1908. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1909. dp_tx_unmap(soc, desc);
  1910. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1911. return dp_mesh_tx_comp_free_buff(soc, desc);
  1912. nbuf_free:
  1913. qdf_nbuf_free(nbuf);
  1914. }
  1915. /**
  1916. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  1917. * @soc: DP soc handle
  1918. * @nbuf: skb
  1919. * @msdu_info: MSDU info
  1920. *
  1921. * Return: None
  1922. */
  1923. static inline void
  1924. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1925. struct dp_tx_msdu_info_s *msdu_info)
  1926. {
  1927. uint32_t cur_idx;
  1928. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  1929. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  1930. qdf_nbuf_headlen(nbuf));
  1931. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  1932. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  1933. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  1934. seg->frags[cur_idx].paddr_hi) << 32),
  1935. seg->frags[cur_idx].len,
  1936. QDF_DMA_TO_DEVICE);
  1937. }
  1938. /**
  1939. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1940. * @vdev: DP vdev handle
  1941. * @nbuf: skb
  1942. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1943. *
  1944. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1945. *
  1946. * Return: NULL on success,
  1947. * nbuf when it fails to send
  1948. */
  1949. #if QDF_LOCK_STATS
  1950. noinline
  1951. #else
  1952. #endif
  1953. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1954. struct dp_tx_msdu_info_s *msdu_info)
  1955. {
  1956. uint32_t i;
  1957. struct dp_pdev *pdev = vdev->pdev;
  1958. struct dp_soc *soc = pdev->soc;
  1959. struct dp_tx_desc_s *tx_desc;
  1960. bool is_cce_classified = false;
  1961. QDF_STATUS status;
  1962. uint16_t htt_tcl_metadata = 0;
  1963. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1964. struct cdp_tid_tx_stats *tid_stats = NULL;
  1965. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1966. if (msdu_info->frm_type == dp_tx_frm_me)
  1967. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1968. i = 0;
  1969. /* Print statement to track i and num_seg */
  1970. /*
  1971. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1972. * descriptors using information in msdu_info
  1973. */
  1974. while (i < msdu_info->num_seg) {
  1975. /*
  1976. * Setup Tx descriptor for an MSDU, and MSDU extension
  1977. * descriptor
  1978. */
  1979. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1980. tx_q->desc_pool_id);
  1981. if (!tx_desc) {
  1982. if (msdu_info->frm_type == dp_tx_frm_me) {
  1983. prep_desc_fail++;
  1984. dp_tx_me_free_buf(pdev,
  1985. (void *)(msdu_info->u.sg_info
  1986. .curr_seg->frags[0].vaddr));
  1987. if (prep_desc_fail == msdu_info->num_seg) {
  1988. /*
  1989. * Unmap is needed only if descriptor
  1990. * preparation failed for all segments.
  1991. */
  1992. qdf_nbuf_unmap(soc->osdev,
  1993. msdu_info->u.sg_info.
  1994. curr_seg->nbuf,
  1995. QDF_DMA_TO_DEVICE);
  1996. }
  1997. /*
  1998. * Free the nbuf for the current segment
  1999. * and make it point to the next in the list.
  2000. * For me, there are as many segments as there
  2001. * are no of clients.
  2002. */
  2003. qdf_nbuf_free(msdu_info->u.sg_info
  2004. .curr_seg->nbuf);
  2005. if (msdu_info->u.sg_info.curr_seg->next) {
  2006. msdu_info->u.sg_info.curr_seg =
  2007. msdu_info->u.sg_info
  2008. .curr_seg->next;
  2009. nbuf = msdu_info->u.sg_info
  2010. .curr_seg->nbuf;
  2011. }
  2012. i++;
  2013. continue;
  2014. }
  2015. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2016. dp_tx_tso_seg_history_add(
  2017. soc,
  2018. msdu_info->u.tso_info.curr_seg,
  2019. nbuf, 0, DP_TX_DESC_UNMAP);
  2020. dp_tx_tso_unmap_segment(soc,
  2021. msdu_info->u.tso_info.
  2022. curr_seg,
  2023. msdu_info->u.tso_info.
  2024. tso_num_seg_list);
  2025. if (msdu_info->u.tso_info.curr_seg->next) {
  2026. msdu_info->u.tso_info.curr_seg =
  2027. msdu_info->u.tso_info.curr_seg->next;
  2028. i++;
  2029. continue;
  2030. }
  2031. }
  2032. if (msdu_info->frm_type == dp_tx_frm_sg)
  2033. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2034. goto done;
  2035. }
  2036. if (msdu_info->frm_type == dp_tx_frm_me) {
  2037. tx_desc->msdu_ext_desc->me_buffer =
  2038. (struct dp_tx_me_buf_t *)msdu_info->
  2039. u.sg_info.curr_seg->frags[0].vaddr;
  2040. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2041. }
  2042. if (is_cce_classified)
  2043. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2044. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2045. if (msdu_info->exception_fw) {
  2046. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2047. }
  2048. /*
  2049. * For frames with multiple segments (TSO, ME), jump to next
  2050. * segment.
  2051. */
  2052. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2053. if (msdu_info->u.tso_info.curr_seg->next) {
  2054. msdu_info->u.tso_info.curr_seg =
  2055. msdu_info->u.tso_info.curr_seg->next;
  2056. /*
  2057. * If this is a jumbo nbuf, then increment the
  2058. * number of nbuf users for each additional
  2059. * segment of the msdu. This will ensure that
  2060. * the skb is freed only after receiving tx
  2061. * completion for all segments of an nbuf
  2062. */
  2063. qdf_nbuf_inc_users(nbuf);
  2064. /* Check with MCL if this is needed */
  2065. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2066. */
  2067. }
  2068. }
  2069. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2070. &htt_tcl_metadata,
  2071. vdev,
  2072. msdu_info);
  2073. /*
  2074. * Enqueue the Tx MSDU descriptor to HW for transmit
  2075. */
  2076. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2077. htt_tcl_metadata,
  2078. NULL, msdu_info);
  2079. if (status != QDF_STATUS_SUCCESS) {
  2080. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2081. tx_desc, tx_q->ring_id);
  2082. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2083. tid_stats = &pdev->stats.tid_stats.
  2084. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2085. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2086. if (msdu_info->frm_type == dp_tx_frm_me) {
  2087. hw_enq_fail++;
  2088. if (hw_enq_fail == msdu_info->num_seg) {
  2089. /*
  2090. * Unmap is needed only if enqueue
  2091. * failed for all segments.
  2092. */
  2093. qdf_nbuf_unmap(soc->osdev,
  2094. msdu_info->u.sg_info.
  2095. curr_seg->nbuf,
  2096. QDF_DMA_TO_DEVICE);
  2097. }
  2098. /*
  2099. * Free the nbuf for the current segment
  2100. * and make it point to the next in the list.
  2101. * For me, there are as many segments as there
  2102. * are no of clients.
  2103. */
  2104. qdf_nbuf_free(msdu_info->u.sg_info
  2105. .curr_seg->nbuf);
  2106. if (msdu_info->u.sg_info.curr_seg->next) {
  2107. msdu_info->u.sg_info.curr_seg =
  2108. msdu_info->u.sg_info
  2109. .curr_seg->next;
  2110. nbuf = msdu_info->u.sg_info
  2111. .curr_seg->nbuf;
  2112. } else
  2113. break;
  2114. i++;
  2115. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2116. continue;
  2117. }
  2118. /*
  2119. * For TSO frames, the nbuf users increment done for
  2120. * the current segment has to be reverted, since the
  2121. * hw enqueue for this segment failed
  2122. */
  2123. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2124. msdu_info->u.tso_info.curr_seg) {
  2125. /*
  2126. * unmap and free current,
  2127. * retransmit remaining segments
  2128. */
  2129. dp_tx_comp_free_buf(soc, tx_desc);
  2130. i++;
  2131. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2132. continue;
  2133. }
  2134. if (msdu_info->frm_type == dp_tx_frm_sg)
  2135. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2136. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2137. goto done;
  2138. }
  2139. /*
  2140. * TODO
  2141. * if tso_info structure can be modified to have curr_seg
  2142. * as first element, following 2 blocks of code (for TSO and SG)
  2143. * can be combined into 1
  2144. */
  2145. /*
  2146. * For Multicast-Unicast converted packets,
  2147. * each converted frame (for a client) is represented as
  2148. * 1 segment
  2149. */
  2150. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2151. (msdu_info->frm_type == dp_tx_frm_me)) {
  2152. if (msdu_info->u.sg_info.curr_seg->next) {
  2153. msdu_info->u.sg_info.curr_seg =
  2154. msdu_info->u.sg_info.curr_seg->next;
  2155. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2156. } else
  2157. break;
  2158. }
  2159. i++;
  2160. }
  2161. nbuf = NULL;
  2162. done:
  2163. return nbuf;
  2164. }
  2165. /**
  2166. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2167. * for SG frames
  2168. * @vdev: DP vdev handle
  2169. * @nbuf: skb
  2170. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2171. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2172. *
  2173. * Return: NULL on success,
  2174. * nbuf when it fails to send
  2175. */
  2176. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2177. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2178. {
  2179. uint32_t cur_frag, nr_frags, i;
  2180. qdf_dma_addr_t paddr;
  2181. struct dp_tx_sg_info_s *sg_info;
  2182. sg_info = &msdu_info->u.sg_info;
  2183. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2184. if (QDF_STATUS_SUCCESS !=
  2185. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2186. QDF_DMA_TO_DEVICE,
  2187. qdf_nbuf_headlen(nbuf))) {
  2188. dp_tx_err("dma map error");
  2189. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2190. qdf_nbuf_free(nbuf);
  2191. return NULL;
  2192. }
  2193. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2194. seg_info->frags[0].paddr_lo = paddr;
  2195. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2196. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2197. seg_info->frags[0].vaddr = (void *) nbuf;
  2198. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2199. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2200. nbuf, 0,
  2201. QDF_DMA_TO_DEVICE,
  2202. cur_frag)) {
  2203. dp_tx_err("frag dma map error");
  2204. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2205. goto map_err;
  2206. }
  2207. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2208. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2209. seg_info->frags[cur_frag + 1].paddr_hi =
  2210. ((uint64_t) paddr) >> 32;
  2211. seg_info->frags[cur_frag + 1].len =
  2212. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2213. }
  2214. seg_info->frag_cnt = (cur_frag + 1);
  2215. seg_info->total_len = qdf_nbuf_len(nbuf);
  2216. seg_info->next = NULL;
  2217. sg_info->curr_seg = seg_info;
  2218. msdu_info->frm_type = dp_tx_frm_sg;
  2219. msdu_info->num_seg = 1;
  2220. return nbuf;
  2221. map_err:
  2222. /* restore paddr into nbuf before calling unmap */
  2223. qdf_nbuf_mapped_paddr_set(nbuf,
  2224. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2225. ((uint64_t)
  2226. seg_info->frags[0].paddr_hi) << 32));
  2227. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2228. QDF_DMA_TO_DEVICE,
  2229. seg_info->frags[0].len);
  2230. for (i = 1; i <= cur_frag; i++) {
  2231. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2232. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2233. seg_info->frags[i].paddr_hi) << 32),
  2234. seg_info->frags[i].len,
  2235. QDF_DMA_TO_DEVICE);
  2236. }
  2237. qdf_nbuf_free(nbuf);
  2238. return NULL;
  2239. }
  2240. /**
  2241. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2242. * @vdev: DP vdev handle
  2243. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2244. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2245. *
  2246. * Return: NULL on failure,
  2247. * nbuf when extracted successfully
  2248. */
  2249. static
  2250. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2251. struct dp_tx_msdu_info_s *msdu_info,
  2252. uint16_t ppdu_cookie)
  2253. {
  2254. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2255. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2256. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2257. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2258. (msdu_info->meta_data[5], 1);
  2259. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2260. (msdu_info->meta_data[5], 1);
  2261. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2262. (msdu_info->meta_data[6], ppdu_cookie);
  2263. msdu_info->exception_fw = 1;
  2264. msdu_info->is_tx_sniffer = 1;
  2265. }
  2266. #ifdef MESH_MODE_SUPPORT
  2267. /**
  2268. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2269. and prepare msdu_info for mesh frames.
  2270. * @vdev: DP vdev handle
  2271. * @nbuf: skb
  2272. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2273. *
  2274. * Return: NULL on failure,
  2275. * nbuf when extracted successfully
  2276. */
  2277. static
  2278. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2279. struct dp_tx_msdu_info_s *msdu_info)
  2280. {
  2281. struct meta_hdr_s *mhdr;
  2282. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2283. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2284. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2285. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2286. msdu_info->exception_fw = 0;
  2287. goto remove_meta_hdr;
  2288. }
  2289. msdu_info->exception_fw = 1;
  2290. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2291. meta_data->host_tx_desc_pool = 1;
  2292. meta_data->update_peer_cache = 1;
  2293. meta_data->learning_frame = 1;
  2294. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2295. meta_data->power = mhdr->power;
  2296. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2297. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2298. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2299. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2300. meta_data->dyn_bw = 1;
  2301. meta_data->valid_pwr = 1;
  2302. meta_data->valid_mcs_mask = 1;
  2303. meta_data->valid_nss_mask = 1;
  2304. meta_data->valid_preamble_type = 1;
  2305. meta_data->valid_retries = 1;
  2306. meta_data->valid_bw_info = 1;
  2307. }
  2308. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2309. meta_data->encrypt_type = 0;
  2310. meta_data->valid_encrypt_type = 1;
  2311. meta_data->learning_frame = 0;
  2312. }
  2313. meta_data->valid_key_flags = 1;
  2314. meta_data->key_flags = (mhdr->keyix & 0x3);
  2315. remove_meta_hdr:
  2316. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2317. dp_tx_err("qdf_nbuf_pull_head failed");
  2318. qdf_nbuf_free(nbuf);
  2319. return NULL;
  2320. }
  2321. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2322. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2323. " tid %d to_fw %d",
  2324. msdu_info->meta_data[0],
  2325. msdu_info->meta_data[1],
  2326. msdu_info->meta_data[2],
  2327. msdu_info->meta_data[3],
  2328. msdu_info->meta_data[4],
  2329. msdu_info->meta_data[5],
  2330. msdu_info->tid, msdu_info->exception_fw);
  2331. return nbuf;
  2332. }
  2333. #else
  2334. static
  2335. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2336. struct dp_tx_msdu_info_s *msdu_info)
  2337. {
  2338. return nbuf;
  2339. }
  2340. #endif
  2341. /**
  2342. * dp_check_exc_metadata() - Checks if parameters are valid
  2343. * @tx_exc - holds all exception path parameters
  2344. *
  2345. * Returns true when all the parameters are valid else false
  2346. *
  2347. */
  2348. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2349. {
  2350. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2351. HTT_INVALID_TID);
  2352. bool invalid_encap_type =
  2353. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2354. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2355. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2356. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2357. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2358. tx_exc->ppdu_cookie == 0);
  2359. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2360. invalid_cookie) {
  2361. return false;
  2362. }
  2363. return true;
  2364. }
  2365. #ifdef ATH_SUPPORT_IQUE
  2366. /**
  2367. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2368. * @vdev: vdev handle
  2369. * @nbuf: skb
  2370. *
  2371. * Return: true on success,
  2372. * false on failure
  2373. */
  2374. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2375. {
  2376. qdf_ether_header_t *eh;
  2377. /* Mcast to Ucast Conversion*/
  2378. if (qdf_likely(!vdev->mcast_enhancement_en))
  2379. return true;
  2380. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2381. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2382. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2383. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2384. qdf_nbuf_set_next(nbuf, NULL);
  2385. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2386. qdf_nbuf_len(nbuf));
  2387. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2388. QDF_STATUS_SUCCESS) {
  2389. return false;
  2390. }
  2391. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2392. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2393. QDF_STATUS_SUCCESS) {
  2394. return false;
  2395. }
  2396. }
  2397. }
  2398. return true;
  2399. }
  2400. #else
  2401. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2402. {
  2403. return true;
  2404. }
  2405. #endif
  2406. /**
  2407. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2408. * @nbuf: qdf_nbuf_t
  2409. * @vdev: struct dp_vdev *
  2410. *
  2411. * Allow packet for processing only if it is for peer client which is
  2412. * connected with same vap. Drop packet if client is connected to
  2413. * different vap.
  2414. *
  2415. * Return: QDF_STATUS
  2416. */
  2417. static inline QDF_STATUS
  2418. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2419. {
  2420. struct dp_ast_entry *dst_ast_entry = NULL;
  2421. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2422. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2423. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2424. return QDF_STATUS_SUCCESS;
  2425. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2426. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2427. eh->ether_dhost,
  2428. vdev->vdev_id);
  2429. /* If there is no ast entry, return failure */
  2430. if (qdf_unlikely(!dst_ast_entry)) {
  2431. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2432. return QDF_STATUS_E_FAILURE;
  2433. }
  2434. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2435. return QDF_STATUS_SUCCESS;
  2436. }
  2437. /**
  2438. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2439. * @soc: DP soc handle
  2440. * @vdev_id: id of DP vdev handle
  2441. * @nbuf: skb
  2442. * @tx_exc_metadata: Handle that holds exception path meta data
  2443. *
  2444. * Entry point for Core Tx layer (DP_TX) invoked from
  2445. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2446. *
  2447. * Return: NULL on success,
  2448. * nbuf when it fails to send
  2449. */
  2450. qdf_nbuf_t
  2451. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2452. qdf_nbuf_t nbuf,
  2453. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2454. {
  2455. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2456. qdf_ether_header_t *eh = NULL;
  2457. struct dp_tx_msdu_info_s msdu_info;
  2458. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2459. DP_MOD_ID_TX_EXCEPTION);
  2460. if (qdf_unlikely(!vdev))
  2461. goto fail;
  2462. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2463. if (!tx_exc_metadata)
  2464. goto fail;
  2465. msdu_info.tid = tx_exc_metadata->tid;
  2466. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2467. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2468. QDF_MAC_ADDR_REF(nbuf->data));
  2469. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2470. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2471. dp_tx_err("Invalid parameters in exception path");
  2472. goto fail;
  2473. }
  2474. /* Basic sanity checks for unsupported packets */
  2475. /* MESH mode */
  2476. if (qdf_unlikely(vdev->mesh_vdev)) {
  2477. dp_tx_err("Mesh mode is not supported in exception path");
  2478. goto fail;
  2479. }
  2480. /*
  2481. * Classify the frame and call corresponding
  2482. * "prepare" function which extracts the segment (TSO)
  2483. * and fragmentation information (for TSO , SG, ME, or Raw)
  2484. * into MSDU_INFO structure which is later used to fill
  2485. * SW and HW descriptors.
  2486. */
  2487. if (qdf_nbuf_is_tso(nbuf)) {
  2488. dp_verbose_debug("TSO frame %pK", vdev);
  2489. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2490. qdf_nbuf_len(nbuf));
  2491. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2492. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2493. qdf_nbuf_len(nbuf));
  2494. goto fail;
  2495. }
  2496. goto send_multiple;
  2497. }
  2498. /* SG */
  2499. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2500. struct dp_tx_seg_info_s seg_info = {0};
  2501. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2502. if (!nbuf)
  2503. goto fail;
  2504. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2505. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2506. qdf_nbuf_len(nbuf));
  2507. goto send_multiple;
  2508. }
  2509. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2510. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2511. qdf_nbuf_len(nbuf));
  2512. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2513. tx_exc_metadata->ppdu_cookie);
  2514. }
  2515. /*
  2516. * Get HW Queue to use for this frame.
  2517. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2518. * dedicated for data and 1 for command.
  2519. * "queue_id" maps to one hardware ring.
  2520. * With each ring, we also associate a unique Tx descriptor pool
  2521. * to minimize lock contention for these resources.
  2522. */
  2523. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2524. /*
  2525. * Check exception descriptors
  2526. */
  2527. if (dp_tx_exception_limit_check(vdev))
  2528. goto fail;
  2529. /* Single linear frame */
  2530. /*
  2531. * If nbuf is a simple linear frame, use send_single function to
  2532. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2533. * SRNG. There is no need to setup a MSDU extension descriptor.
  2534. */
  2535. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2536. tx_exc_metadata->peer_id, tx_exc_metadata);
  2537. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2538. return nbuf;
  2539. send_multiple:
  2540. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2541. fail:
  2542. if (vdev)
  2543. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2544. dp_verbose_debug("pkt send failed");
  2545. return nbuf;
  2546. }
  2547. /**
  2548. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2549. * in exception path in special case to avoid regular exception path chk.
  2550. * @soc: DP soc handle
  2551. * @vdev_id: id of DP vdev handle
  2552. * @nbuf: skb
  2553. * @tx_exc_metadata: Handle that holds exception path meta data
  2554. *
  2555. * Entry point for Core Tx layer (DP_TX) invoked from
  2556. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2557. *
  2558. * Return: NULL on success,
  2559. * nbuf when it fails to send
  2560. */
  2561. qdf_nbuf_t
  2562. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2563. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2564. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2565. {
  2566. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2567. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2568. DP_MOD_ID_TX_EXCEPTION);
  2569. if (qdf_unlikely(!vdev))
  2570. goto fail;
  2571. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2572. == QDF_STATUS_E_FAILURE)) {
  2573. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2574. goto fail;
  2575. }
  2576. /* Unref count as it will agin be taken inside dp_tx_exception */
  2577. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2578. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2579. fail:
  2580. if (vdev)
  2581. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2582. dp_verbose_debug("pkt send failed");
  2583. return nbuf;
  2584. }
  2585. /**
  2586. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2587. * @soc: DP soc handle
  2588. * @vdev_id: DP vdev handle
  2589. * @nbuf: skb
  2590. *
  2591. * Entry point for Core Tx layer (DP_TX) invoked from
  2592. * hard_start_xmit in OSIF/HDD
  2593. *
  2594. * Return: NULL on success,
  2595. * nbuf when it fails to send
  2596. */
  2597. #ifdef MESH_MODE_SUPPORT
  2598. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2599. qdf_nbuf_t nbuf)
  2600. {
  2601. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2602. struct meta_hdr_s *mhdr;
  2603. qdf_nbuf_t nbuf_mesh = NULL;
  2604. qdf_nbuf_t nbuf_clone = NULL;
  2605. struct dp_vdev *vdev;
  2606. uint8_t no_enc_frame = 0;
  2607. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2608. if (!nbuf_mesh) {
  2609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2610. "qdf_nbuf_unshare failed");
  2611. return nbuf;
  2612. }
  2613. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2614. if (!vdev) {
  2615. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2616. "vdev is NULL for vdev_id %d", vdev_id);
  2617. return nbuf;
  2618. }
  2619. nbuf = nbuf_mesh;
  2620. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2621. if ((vdev->sec_type != cdp_sec_type_none) &&
  2622. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2623. no_enc_frame = 1;
  2624. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2625. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2626. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2627. !no_enc_frame) {
  2628. nbuf_clone = qdf_nbuf_clone(nbuf);
  2629. if (!nbuf_clone) {
  2630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2631. "qdf_nbuf_clone failed");
  2632. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2633. return nbuf;
  2634. }
  2635. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2636. }
  2637. if (nbuf_clone) {
  2638. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2639. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2640. } else {
  2641. qdf_nbuf_free(nbuf_clone);
  2642. }
  2643. }
  2644. if (no_enc_frame)
  2645. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2646. else
  2647. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2648. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2649. if ((!nbuf) && no_enc_frame) {
  2650. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2651. }
  2652. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2653. return nbuf;
  2654. }
  2655. #else
  2656. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2657. qdf_nbuf_t nbuf)
  2658. {
  2659. return dp_tx_send(soc, vdev_id, nbuf);
  2660. }
  2661. #endif
  2662. /**
  2663. * dp_tx_nawds_handler() - NAWDS handler
  2664. *
  2665. * @soc: DP soc handle
  2666. * @vdev_id: id of DP vdev handle
  2667. * @msdu_info: msdu_info required to create HTT metadata
  2668. * @nbuf: skb
  2669. *
  2670. * This API transfers the multicast frames with the peer id
  2671. * on NAWDS enabled peer.
  2672. * Return: none
  2673. */
  2674. static inline
  2675. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2676. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2677. {
  2678. struct dp_peer *peer = NULL;
  2679. qdf_nbuf_t nbuf_clone = NULL;
  2680. uint16_t peer_id = DP_INVALID_PEER;
  2681. uint16_t sa_peer_id = DP_INVALID_PEER;
  2682. struct dp_ast_entry *ast_entry = NULL;
  2683. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2684. if (!soc->ast_offload_support) {
  2685. qdf_spin_lock_bh(&soc->ast_lock);
  2686. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2687. (soc,
  2688. (uint8_t *)(eh->ether_shost),
  2689. vdev->pdev->pdev_id);
  2690. if (ast_entry)
  2691. sa_peer_id = ast_entry->peer_id;
  2692. qdf_spin_unlock_bh(&soc->ast_lock);
  2693. } else {
  2694. if ((qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) &&
  2695. qdf_nbuf_get_tx_fctx(nbuf))
  2696. sa_peer_id = *(uint32_t *)qdf_nbuf_get_tx_fctx(nbuf);
  2697. }
  2698. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2699. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2700. if (!peer->bss_peer && peer->nawds_enabled) {
  2701. peer_id = peer->peer_id;
  2702. /* Multicast packets needs to be
  2703. * dropped in case of intra bss forwarding
  2704. */
  2705. if (sa_peer_id == peer->peer_id) {
  2706. dp_tx_debug("multicast packet");
  2707. DP_STATS_INC(peer, tx.nawds_mcast_drop,
  2708. 1);
  2709. continue;
  2710. }
  2711. nbuf_clone = qdf_nbuf_clone(nbuf);
  2712. if (!nbuf_clone) {
  2713. QDF_TRACE(QDF_MODULE_ID_DP,
  2714. QDF_TRACE_LEVEL_ERROR,
  2715. FL("nbuf clone failed"));
  2716. break;
  2717. }
  2718. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2719. msdu_info, peer_id,
  2720. NULL);
  2721. if (nbuf_clone) {
  2722. dp_tx_debug("pkt send failed");
  2723. qdf_nbuf_free(nbuf_clone);
  2724. } else {
  2725. if (peer_id != DP_INVALID_PEER)
  2726. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2727. 1, qdf_nbuf_len(nbuf));
  2728. }
  2729. }
  2730. }
  2731. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2732. }
  2733. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2734. static inline
  2735. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2736. {
  2737. if (nbuf) {
  2738. qdf_prefetch(&nbuf->len);
  2739. qdf_prefetch(&nbuf->data);
  2740. }
  2741. }
  2742. #else
  2743. static inline
  2744. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2745. {
  2746. }
  2747. #endif
  2748. /**
  2749. * dp_tx_send() - Transmit a frame on a given VAP
  2750. * @soc: DP soc handle
  2751. * @vdev_id: id of DP vdev handle
  2752. * @nbuf: skb
  2753. *
  2754. * Entry point for Core Tx layer (DP_TX) invoked from
  2755. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2756. * cases
  2757. *
  2758. * Return: NULL on success,
  2759. * nbuf when it fails to send
  2760. */
  2761. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2762. qdf_nbuf_t nbuf)
  2763. {
  2764. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2765. uint16_t peer_id = HTT_INVALID_PEER;
  2766. /*
  2767. * doing a memzero is causing additional function call overhead
  2768. * so doing static stack clearing
  2769. */
  2770. struct dp_tx_msdu_info_s msdu_info = {0};
  2771. struct dp_vdev *vdev = NULL;
  2772. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2773. return nbuf;
  2774. /*
  2775. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2776. * this in per packet path.
  2777. *
  2778. * As in this path vdev memory is already protected with netdev
  2779. * tx lock
  2780. */
  2781. vdev = soc->vdev_id_map[vdev_id];
  2782. if (qdf_unlikely(!vdev))
  2783. return nbuf;
  2784. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2785. QDF_MAC_ADDR_REF(nbuf->data));
  2786. /*
  2787. * Set Default Host TID value to invalid TID
  2788. * (TID override disabled)
  2789. */
  2790. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2791. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2792. if (qdf_unlikely(vdev->mesh_vdev)) {
  2793. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2794. &msdu_info);
  2795. if (!nbuf_mesh) {
  2796. dp_verbose_debug("Extracting mesh metadata failed");
  2797. return nbuf;
  2798. }
  2799. nbuf = nbuf_mesh;
  2800. }
  2801. /*
  2802. * Get HW Queue to use for this frame.
  2803. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2804. * dedicated for data and 1 for command.
  2805. * "queue_id" maps to one hardware ring.
  2806. * With each ring, we also associate a unique Tx descriptor pool
  2807. * to minimize lock contention for these resources.
  2808. */
  2809. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2810. /*
  2811. * TCL H/W supports 2 DSCP-TID mapping tables.
  2812. * Table 1 - Default DSCP-TID mapping table
  2813. * Table 2 - 1 DSCP-TID override table
  2814. *
  2815. * If we need a different DSCP-TID mapping for this vap,
  2816. * call tid_classify to extract DSCP/ToS from frame and
  2817. * map to a TID and store in msdu_info. This is later used
  2818. * to fill in TCL Input descriptor (per-packet TID override).
  2819. */
  2820. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2821. /*
  2822. * Classify the frame and call corresponding
  2823. * "prepare" function which extracts the segment (TSO)
  2824. * and fragmentation information (for TSO , SG, ME, or Raw)
  2825. * into MSDU_INFO structure which is later used to fill
  2826. * SW and HW descriptors.
  2827. */
  2828. if (qdf_nbuf_is_tso(nbuf)) {
  2829. dp_verbose_debug("TSO frame %pK", vdev);
  2830. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2831. qdf_nbuf_len(nbuf));
  2832. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2833. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2834. qdf_nbuf_len(nbuf));
  2835. return nbuf;
  2836. }
  2837. goto send_multiple;
  2838. }
  2839. /* SG */
  2840. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2841. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  2842. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  2843. return nbuf;
  2844. } else {
  2845. struct dp_tx_seg_info_s seg_info = {0};
  2846. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  2847. &msdu_info);
  2848. if (!nbuf)
  2849. return NULL;
  2850. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2851. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2852. qdf_nbuf_len(nbuf));
  2853. goto send_multiple;
  2854. }
  2855. }
  2856. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2857. return NULL;
  2858. /* RAW */
  2859. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2860. struct dp_tx_seg_info_s seg_info = {0};
  2861. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2862. if (!nbuf)
  2863. return NULL;
  2864. dp_verbose_debug("Raw frame %pK", vdev);
  2865. goto send_multiple;
  2866. }
  2867. if (qdf_unlikely(vdev->nawds_enabled)) {
  2868. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2869. qdf_nbuf_data(nbuf);
  2870. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2871. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2872. peer_id = DP_INVALID_PEER;
  2873. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2874. 1, qdf_nbuf_len(nbuf));
  2875. }
  2876. /* Single linear frame */
  2877. /*
  2878. * If nbuf is a simple linear frame, use send_single function to
  2879. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2880. * SRNG. There is no need to setup a MSDU extension descriptor.
  2881. */
  2882. dp_tx_prefetch_nbuf_data(nbuf);
  2883. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2884. return nbuf;
  2885. send_multiple:
  2886. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2887. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2888. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2889. return nbuf;
  2890. }
  2891. /**
  2892. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2893. * case to vaoid check in perpkt path.
  2894. * @soc: DP soc handle
  2895. * @vdev_id: id of DP vdev handle
  2896. * @nbuf: skb
  2897. *
  2898. * Entry point for Core Tx layer (DP_TX) invoked from
  2899. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2900. * with special condition to avoid per pkt check in dp_tx_send
  2901. *
  2902. * Return: NULL on success,
  2903. * nbuf when it fails to send
  2904. */
  2905. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2906. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2907. {
  2908. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2909. struct dp_vdev *vdev = NULL;
  2910. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2911. return nbuf;
  2912. /*
  2913. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2914. * this in per packet path.
  2915. *
  2916. * As in this path vdev memory is already protected with netdev
  2917. * tx lock
  2918. */
  2919. vdev = soc->vdev_id_map[vdev_id];
  2920. if (qdf_unlikely(!vdev))
  2921. return nbuf;
  2922. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2923. == QDF_STATUS_E_FAILURE)) {
  2924. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2925. return nbuf;
  2926. }
  2927. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2928. }
  2929. #ifdef UMAC_SUPPORT_PROXY_ARP
  2930. /**
  2931. * dp_tx_proxy_arp() - Tx proxy arp handler
  2932. * @vdev: datapath vdev handle
  2933. * @buf: sk buffer
  2934. *
  2935. * Return: status
  2936. */
  2937. static inline
  2938. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2939. {
  2940. if (vdev->osif_proxy_arp)
  2941. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2942. /*
  2943. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2944. * osif_proxy_arp has a valid function pointer assigned
  2945. * to it
  2946. */
  2947. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2948. return QDF_STATUS_NOT_INITIALIZED;
  2949. }
  2950. #else
  2951. /**
  2952. * dp_tx_proxy_arp() - Tx proxy arp handler
  2953. * @vdev: datapath vdev handle
  2954. * @buf: sk buffer
  2955. *
  2956. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2957. * is not defined.
  2958. *
  2959. * Return: status
  2960. */
  2961. static inline
  2962. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2963. {
  2964. return QDF_STATUS_SUCCESS;
  2965. }
  2966. #endif
  2967. /**
  2968. * dp_tx_reinject_handler() - Tx Reinject Handler
  2969. * @soc: datapath soc handle
  2970. * @vdev: datapath vdev handle
  2971. * @tx_desc: software descriptor head pointer
  2972. * @status : Tx completion status from HTT descriptor
  2973. * @reinject_reason : reinject reason from HTT descriptor
  2974. *
  2975. * This function reinjects frames back to Target.
  2976. * Todo - Host queue needs to be added
  2977. *
  2978. * Return: none
  2979. */
  2980. void dp_tx_reinject_handler(struct dp_soc *soc,
  2981. struct dp_vdev *vdev,
  2982. struct dp_tx_desc_s *tx_desc,
  2983. uint8_t *status,
  2984. uint8_t reinject_reason)
  2985. {
  2986. struct dp_peer *peer = NULL;
  2987. uint32_t peer_id = HTT_INVALID_PEER;
  2988. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2989. qdf_nbuf_t nbuf_copy = NULL;
  2990. struct dp_tx_msdu_info_s msdu_info;
  2991. #ifdef WDS_VENDOR_EXTENSION
  2992. int is_mcast = 0, is_ucast = 0;
  2993. int num_peers_3addr = 0;
  2994. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2995. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2996. #endif
  2997. qdf_assert(vdev);
  2998. dp_tx_debug("Tx reinject path");
  2999. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3000. qdf_nbuf_len(tx_desc->nbuf));
  3001. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3002. #ifdef WLAN_MCAST_MLO
  3003. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3004. if (soc->arch_ops.dp_tx_mcast_handler)
  3005. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3006. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3007. return;
  3008. }
  3009. #endif
  3010. #endif
  3011. #ifdef WDS_VENDOR_EXTENSION
  3012. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3013. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3014. } else {
  3015. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3016. }
  3017. is_ucast = !is_mcast;
  3018. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3019. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3020. if (peer->bss_peer)
  3021. continue;
  3022. /* Detect wds peers that use 3-addr framing for mcast.
  3023. * if there are any, the bss_peer is used to send the
  3024. * the mcast frame using 3-addr format. all wds enabled
  3025. * peers that use 4-addr framing for mcast frames will
  3026. * be duplicated and sent as 4-addr frames below.
  3027. */
  3028. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  3029. num_peers_3addr = 1;
  3030. break;
  3031. }
  3032. }
  3033. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3034. #endif
  3035. if (qdf_unlikely(vdev->mesh_vdev)) {
  3036. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3037. } else {
  3038. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3039. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3040. if ((peer->peer_id != HTT_INVALID_PEER) &&
  3041. #ifdef WDS_VENDOR_EXTENSION
  3042. /*
  3043. * . if 3-addr STA, then send on BSS Peer
  3044. * . if Peer WDS enabled and accept 4-addr mcast,
  3045. * send mcast on that peer only
  3046. * . if Peer WDS enabled and accept 4-addr ucast,
  3047. * send ucast on that peer only
  3048. */
  3049. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  3050. (peer->wds_enabled &&
  3051. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  3052. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3053. #else
  3054. (peer->bss_peer &&
  3055. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3056. #endif
  3057. peer_id = DP_INVALID_PEER;
  3058. nbuf_copy = qdf_nbuf_copy(nbuf);
  3059. if (!nbuf_copy) {
  3060. dp_tx_debug("nbuf copy failed");
  3061. break;
  3062. }
  3063. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3064. dp_tx_get_queue(vdev, nbuf,
  3065. &msdu_info.tx_queue);
  3066. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3067. nbuf_copy,
  3068. &msdu_info,
  3069. peer_id,
  3070. NULL);
  3071. if (nbuf_copy) {
  3072. dp_tx_debug("pkt send failed");
  3073. qdf_nbuf_free(nbuf_copy);
  3074. }
  3075. }
  3076. }
  3077. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3078. }
  3079. qdf_nbuf_free(nbuf);
  3080. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3081. }
  3082. /**
  3083. * dp_tx_inspect_handler() - Tx Inspect Handler
  3084. * @soc: datapath soc handle
  3085. * @vdev: datapath vdev handle
  3086. * @tx_desc: software descriptor head pointer
  3087. * @status : Tx completion status from HTT descriptor
  3088. *
  3089. * Handles Tx frames sent back to Host for inspection
  3090. * (ProxyARP)
  3091. *
  3092. * Return: none
  3093. */
  3094. void dp_tx_inspect_handler(struct dp_soc *soc,
  3095. struct dp_vdev *vdev,
  3096. struct dp_tx_desc_s *tx_desc,
  3097. uint8_t *status)
  3098. {
  3099. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3100. "%s Tx inspect path",
  3101. __func__);
  3102. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3103. qdf_nbuf_len(tx_desc->nbuf));
  3104. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3105. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3106. }
  3107. #ifdef MESH_MODE_SUPPORT
  3108. /**
  3109. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3110. * in mesh meta header
  3111. * @tx_desc: software descriptor head pointer
  3112. * @ts: pointer to tx completion stats
  3113. * Return: none
  3114. */
  3115. static
  3116. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3117. struct hal_tx_completion_status *ts)
  3118. {
  3119. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3120. if (!tx_desc->msdu_ext_desc) {
  3121. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3122. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3123. "netbuf %pK offset %d",
  3124. netbuf, tx_desc->pkt_offset);
  3125. return;
  3126. }
  3127. }
  3128. }
  3129. #else
  3130. static
  3131. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3132. struct hal_tx_completion_status *ts)
  3133. {
  3134. }
  3135. #endif
  3136. #ifdef QCA_PEER_EXT_STATS
  3137. /*
  3138. * dp_tx_compute_tid_delay() - Compute per TID delay
  3139. * @stats: Per TID delay stats
  3140. * @tx_desc: Software Tx descriptor
  3141. *
  3142. * Compute the software enqueue and hw enqueue delays and
  3143. * update the respective histograms
  3144. *
  3145. * Return: void
  3146. */
  3147. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3148. struct dp_tx_desc_s *tx_desc)
  3149. {
  3150. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3151. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3152. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3153. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3154. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3155. timestamp_hw_enqueue = tx_desc->timestamp;
  3156. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3157. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3158. timestamp_hw_enqueue);
  3159. /*
  3160. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3161. */
  3162. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3163. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3164. }
  3165. /*
  3166. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3167. * @peer: DP peer context
  3168. * @tx_desc: Tx software descriptor
  3169. * @tid: Transmission ID
  3170. * @ring_id: Rx CPU context ID/CPU_ID
  3171. *
  3172. * Update the peer extended stats. These are enhanced other
  3173. * delay stats per msdu level.
  3174. *
  3175. * Return: void
  3176. */
  3177. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3178. struct dp_tx_desc_s *tx_desc,
  3179. uint8_t tid, uint8_t ring_id)
  3180. {
  3181. struct dp_pdev *pdev = peer->vdev->pdev;
  3182. struct dp_soc *soc = NULL;
  3183. struct cdp_peer_ext_stats *pext_stats = NULL;
  3184. soc = pdev->soc;
  3185. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3186. return;
  3187. pext_stats = peer->pext_stats;
  3188. qdf_assert(pext_stats);
  3189. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3190. /*
  3191. * For non-TID packets use the TID 9
  3192. */
  3193. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3194. tid = CDP_MAX_DATA_TIDS - 1;
  3195. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3196. tx_desc);
  3197. }
  3198. #else
  3199. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3200. struct dp_tx_desc_s *tx_desc,
  3201. uint8_t tid, uint8_t ring_id)
  3202. {
  3203. }
  3204. #endif
  3205. /**
  3206. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3207. * to pass in correct fields
  3208. *
  3209. * @vdev: pdev handle
  3210. * @tx_desc: tx descriptor
  3211. * @tid: tid value
  3212. * @ring_id: TCL or WBM ring number for transmit path
  3213. * Return: none
  3214. */
  3215. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3216. uint8_t tid, uint8_t ring_id)
  3217. {
  3218. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3219. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3220. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3221. return;
  3222. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3223. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3224. timestamp_hw_enqueue = tx_desc->timestamp;
  3225. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3226. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3227. timestamp_hw_enqueue);
  3228. interframe_delay = (uint32_t)(timestamp_ingress -
  3229. vdev->prev_tx_enq_tstamp);
  3230. /*
  3231. * Delay in software enqueue
  3232. */
  3233. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3234. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3235. /*
  3236. * Delay between packet enqueued to HW and Tx completion
  3237. */
  3238. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3239. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3240. /*
  3241. * Update interframe delay stats calculated at hardstart receive point.
  3242. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3243. * interframe delay will not be calculate correctly for 1st frame.
  3244. * On the other side, this will help in avoiding extra per packet check
  3245. * of !vdev->prev_tx_enq_tstamp.
  3246. */
  3247. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3248. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3249. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3250. }
  3251. #ifdef DISABLE_DP_STATS
  3252. static
  3253. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3254. {
  3255. }
  3256. #else
  3257. static
  3258. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3259. {
  3260. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3261. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3262. if (subtype != QDF_PROTO_INVALID)
  3263. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3264. }
  3265. #endif
  3266. /**
  3267. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3268. * per wbm ring
  3269. *
  3270. * @tx_desc: software descriptor head pointer
  3271. * @ts: Tx completion status
  3272. * @peer: peer handle
  3273. * @ring_id: ring number
  3274. *
  3275. * Return: None
  3276. */
  3277. static inline void
  3278. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3279. struct hal_tx_completion_status *ts,
  3280. struct dp_peer *peer, uint8_t ring_id)
  3281. {
  3282. struct dp_pdev *pdev = peer->vdev->pdev;
  3283. struct dp_soc *soc = NULL;
  3284. uint8_t mcs, pkt_type;
  3285. uint8_t tid = ts->tid;
  3286. uint32_t length;
  3287. struct cdp_tid_tx_stats *tid_stats;
  3288. if (!pdev)
  3289. return;
  3290. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3291. tid = CDP_MAX_DATA_TIDS - 1;
  3292. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3293. soc = pdev->soc;
  3294. mcs = ts->mcs;
  3295. pkt_type = ts->pkt_type;
  3296. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3297. dp_err("Release source is not from TQM");
  3298. return;
  3299. }
  3300. length = qdf_nbuf_len(tx_desc->nbuf);
  3301. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3302. if (qdf_unlikely(pdev->delay_stats_flag))
  3303. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3304. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3305. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3306. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3307. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3308. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3309. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3310. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3311. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3312. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3313. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3314. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3315. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3316. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3317. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3318. /*
  3319. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3320. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3321. * are no completions for failed cases. Hence updating tx_failed from
  3322. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3323. * then this has to be removed
  3324. */
  3325. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3326. peer->stats.tx.dropped.fw_rem_notx +
  3327. peer->stats.tx.dropped.fw_rem_tx +
  3328. peer->stats.tx.dropped.age_out +
  3329. peer->stats.tx.dropped.fw_reason1 +
  3330. peer->stats.tx.dropped.fw_reason2 +
  3331. peer->stats.tx.dropped.fw_reason3;
  3332. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3333. tid_stats->tqm_status_cnt[ts->status]++;
  3334. }
  3335. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3336. DP_STATS_INCC(peer, tx.failed_retry_count, 1,
  3337. ts->transmit_cnt > DP_RETRY_COUNT);
  3338. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3339. return;
  3340. }
  3341. DP_STATS_INCC(peer, tx.retry_count, 1, ts->transmit_cnt > 1);
  3342. DP_STATS_INCC(peer, tx.multiple_retry_count, 1, ts->transmit_cnt > 2);
  3343. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3344. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3345. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3346. /*
  3347. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3348. * Return from here if HTT PPDU events are enabled.
  3349. */
  3350. if (!(soc->process_tx_status))
  3351. return;
  3352. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3353. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3354. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3355. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3356. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3357. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3358. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3359. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3360. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3361. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3362. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3363. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3364. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3365. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3366. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3367. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3368. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3369. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3370. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3371. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3372. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3373. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3374. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3375. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3376. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3377. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3378. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3379. if (ts->first_msdu) {
  3380. DP_STATS_INCC(peer, tx.retries_mpdu, 1, ts->transmit_cnt > 1);
  3381. DP_STATS_INCC(peer, tx.mpdu_success_with_retries,
  3382. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3383. ts->transmit_cnt > DP_RETRY_COUNT);
  3384. }
  3385. peer->stats.tx.last_tx_ts = qdf_system_ticks();
  3386. }
  3387. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3388. /**
  3389. * dp_tx_flow_pool_lock() - take flow pool lock
  3390. * @soc: core txrx main context
  3391. * @tx_desc: tx desc
  3392. *
  3393. * Return: None
  3394. */
  3395. static inline
  3396. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3397. struct dp_tx_desc_s *tx_desc)
  3398. {
  3399. struct dp_tx_desc_pool_s *pool;
  3400. uint8_t desc_pool_id;
  3401. desc_pool_id = tx_desc->pool_id;
  3402. pool = &soc->tx_desc[desc_pool_id];
  3403. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3404. }
  3405. /**
  3406. * dp_tx_flow_pool_unlock() - release flow pool lock
  3407. * @soc: core txrx main context
  3408. * @tx_desc: tx desc
  3409. *
  3410. * Return: None
  3411. */
  3412. static inline
  3413. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3414. struct dp_tx_desc_s *tx_desc)
  3415. {
  3416. struct dp_tx_desc_pool_s *pool;
  3417. uint8_t desc_pool_id;
  3418. desc_pool_id = tx_desc->pool_id;
  3419. pool = &soc->tx_desc[desc_pool_id];
  3420. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3421. }
  3422. #else
  3423. static inline
  3424. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3425. {
  3426. }
  3427. static inline
  3428. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3429. {
  3430. }
  3431. #endif
  3432. /**
  3433. * dp_tx_notify_completion() - Notify tx completion for this desc
  3434. * @soc: core txrx main context
  3435. * @vdev: datapath vdev handle
  3436. * @tx_desc: tx desc
  3437. * @netbuf: buffer
  3438. * @status: tx status
  3439. *
  3440. * Return: none
  3441. */
  3442. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3443. struct dp_vdev *vdev,
  3444. struct dp_tx_desc_s *tx_desc,
  3445. qdf_nbuf_t netbuf,
  3446. uint8_t status)
  3447. {
  3448. void *osif_dev;
  3449. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3450. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3451. qdf_assert(tx_desc);
  3452. dp_tx_flow_pool_lock(soc, tx_desc);
  3453. if (!vdev ||
  3454. !vdev->osif_vdev) {
  3455. dp_tx_flow_pool_unlock(soc, tx_desc);
  3456. return;
  3457. }
  3458. osif_dev = vdev->osif_vdev;
  3459. tx_compl_cbk = vdev->tx_comp;
  3460. dp_tx_flow_pool_unlock(soc, tx_desc);
  3461. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3462. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3463. if (tx_compl_cbk)
  3464. tx_compl_cbk(netbuf, osif_dev, flag);
  3465. }
  3466. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3467. * @pdev: pdev handle
  3468. * @tid: tid value
  3469. * @txdesc_ts: timestamp from txdesc
  3470. * @ppdu_id: ppdu id
  3471. *
  3472. * Return: none
  3473. */
  3474. #ifdef FEATURE_PERPKT_INFO
  3475. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3476. struct dp_peer *peer,
  3477. uint8_t tid,
  3478. uint64_t txdesc_ts,
  3479. uint32_t ppdu_id)
  3480. {
  3481. uint64_t delta_ms;
  3482. struct cdp_tx_sojourn_stats *sojourn_stats;
  3483. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3484. return;
  3485. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3486. tid >= CDP_DATA_TID_MAX))
  3487. return;
  3488. if (qdf_unlikely(!pdev->sojourn_buf))
  3489. return;
  3490. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3491. qdf_nbuf_data(pdev->sojourn_buf);
  3492. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3493. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3494. txdesc_ts;
  3495. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3496. delta_ms);
  3497. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3498. sojourn_stats->num_msdus[tid] = 1;
  3499. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3500. peer->avg_sojourn_msdu[tid].internal;
  3501. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3502. pdev->sojourn_buf, HTT_INVALID_PEER,
  3503. WDI_NO_VAL, pdev->pdev_id);
  3504. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3505. sojourn_stats->num_msdus[tid] = 0;
  3506. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3507. }
  3508. #else
  3509. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3510. struct dp_peer *peer,
  3511. uint8_t tid,
  3512. uint64_t txdesc_ts,
  3513. uint32_t ppdu_id)
  3514. {
  3515. }
  3516. #endif
  3517. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3518. /**
  3519. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3520. * @soc: dp_soc handle
  3521. * @desc: Tx Descriptor
  3522. * @ts: HAL Tx completion descriptor contents
  3523. *
  3524. * This function is used to send tx completion to packet capture
  3525. */
  3526. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3527. struct dp_tx_desc_s *desc,
  3528. struct hal_tx_completion_status *ts)
  3529. {
  3530. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3531. desc, ts->peer_id,
  3532. WDI_NO_VAL, desc->pdev->pdev_id);
  3533. }
  3534. #endif
  3535. /**
  3536. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3537. * @soc: DP Soc handle
  3538. * @tx_desc: software Tx descriptor
  3539. * @ts : Tx completion status from HAL/HTT descriptor
  3540. *
  3541. * Return: none
  3542. */
  3543. void
  3544. dp_tx_comp_process_desc(struct dp_soc *soc,
  3545. struct dp_tx_desc_s *desc,
  3546. struct hal_tx_completion_status *ts,
  3547. struct dp_peer *peer)
  3548. {
  3549. uint64_t time_latency = 0;
  3550. /*
  3551. * m_copy/tx_capture modes are not supported for
  3552. * scatter gather packets
  3553. */
  3554. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3555. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3556. desc->timestamp);
  3557. }
  3558. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3559. if (dp_tx_pkt_tracepoints_enabled())
  3560. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3561. desc->msdu_ext_desc ?
  3562. desc->msdu_ext_desc->tso_desc : NULL,
  3563. desc->timestamp);
  3564. if (!(desc->msdu_ext_desc)) {
  3565. dp_tx_enh_unmap(soc, desc);
  3566. if (QDF_STATUS_SUCCESS ==
  3567. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3568. return;
  3569. }
  3570. if (QDF_STATUS_SUCCESS ==
  3571. dp_get_completion_indication_for_stack(soc,
  3572. desc->pdev,
  3573. peer, ts,
  3574. desc->nbuf,
  3575. time_latency)) {
  3576. dp_send_completion_to_stack(soc,
  3577. desc->pdev,
  3578. ts->peer_id,
  3579. ts->ppdu_id,
  3580. desc->nbuf);
  3581. return;
  3582. }
  3583. }
  3584. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3585. dp_tx_comp_free_buf(soc, desc);
  3586. }
  3587. #ifdef DISABLE_DP_STATS
  3588. /**
  3589. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3590. * @soc: core txrx main context
  3591. * @tx_desc: tx desc
  3592. * @status: tx status
  3593. *
  3594. * Return: none
  3595. */
  3596. static inline
  3597. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3598. struct dp_vdev *vdev,
  3599. struct dp_tx_desc_s *tx_desc,
  3600. uint8_t status)
  3601. {
  3602. }
  3603. #else
  3604. static inline
  3605. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3606. struct dp_vdev *vdev,
  3607. struct dp_tx_desc_s *tx_desc,
  3608. uint8_t status)
  3609. {
  3610. void *osif_dev;
  3611. ol_txrx_stats_rx_fp stats_cbk;
  3612. uint8_t pkt_type;
  3613. qdf_assert(tx_desc);
  3614. if (!vdev ||
  3615. !vdev->osif_vdev ||
  3616. !vdev->stats_cb)
  3617. return;
  3618. osif_dev = vdev->osif_vdev;
  3619. stats_cbk = vdev->stats_cb;
  3620. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3621. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3622. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3623. &pkt_type);
  3624. }
  3625. #endif
  3626. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3627. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3628. uint32_t delta_tsf)
  3629. {
  3630. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3631. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3632. DP_MOD_ID_CDP);
  3633. if (!vdev) {
  3634. dp_err_rl("vdev %d does not exist", vdev_id);
  3635. return;
  3636. }
  3637. vdev->delta_tsf = delta_tsf;
  3638. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3639. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3640. }
  3641. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3642. uint8_t vdev_id, bool enable)
  3643. {
  3644. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3645. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3646. DP_MOD_ID_CDP);
  3647. if (!vdev) {
  3648. dp_err_rl("vdev %d does not exist", vdev_id);
  3649. return QDF_STATUS_E_FAILURE;
  3650. }
  3651. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3652. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3653. return QDF_STATUS_SUCCESS;
  3654. }
  3655. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3656. uint32_t *val)
  3657. {
  3658. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3659. struct dp_vdev *vdev;
  3660. uint32_t delay_accum;
  3661. uint32_t pkts_accum;
  3662. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3663. if (!vdev) {
  3664. dp_err_rl("vdev %d does not exist", vdev_id);
  3665. return QDF_STATUS_E_FAILURE;
  3666. }
  3667. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3668. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3669. return QDF_STATUS_E_FAILURE;
  3670. }
  3671. /* Average uplink delay based on current accumulated values */
  3672. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3673. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3674. *val = delay_accum / pkts_accum;
  3675. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3676. delay_accum, pkts_accum);
  3677. /* Reset accumulated values to 0 */
  3678. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3679. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3680. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3681. return QDF_STATUS_SUCCESS;
  3682. }
  3683. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3684. struct hal_tx_completion_status *ts)
  3685. {
  3686. uint32_t buffer_ts;
  3687. uint32_t delta_tsf;
  3688. uint32_t ul_delay;
  3689. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3690. if (!ts->valid)
  3691. return;
  3692. if (qdf_unlikely(!vdev)) {
  3693. dp_info_rl("vdev is null or delete in progrss");
  3694. return;
  3695. }
  3696. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3697. return;
  3698. delta_tsf = vdev->delta_tsf;
  3699. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3700. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3701. * valid up to 29 bits.
  3702. */
  3703. buffer_ts = ts->buffer_timestamp << 10;
  3704. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3705. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3706. if (ul_delay > 0x1000000) {
  3707. dp_info_rl("----------------------\n"
  3708. "Tx completion status:\n"
  3709. "----------------------\n"
  3710. "release_src = %d\n"
  3711. "ppdu_id = 0x%x\n"
  3712. "release_reason = %d\n"
  3713. "tsf = %u (0x%x)\n"
  3714. "buffer_timestamp = %u (0x%x)\n"
  3715. "delta_tsf = %u (0x%x)\n",
  3716. ts->release_src, ts->ppdu_id, ts->status,
  3717. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3718. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3719. return;
  3720. }
  3721. ul_delay /= 1000; /* in unit of ms */
  3722. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3723. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3724. }
  3725. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3726. static inline
  3727. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3728. struct hal_tx_completion_status *ts)
  3729. {
  3730. }
  3731. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3732. /**
  3733. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3734. * @soc: DP soc handle
  3735. * @tx_desc: software descriptor head pointer
  3736. * @ts: Tx completion status
  3737. * @peer: peer handle
  3738. * @ring_id: ring number
  3739. *
  3740. * Return: none
  3741. */
  3742. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3743. struct dp_tx_desc_s *tx_desc,
  3744. struct hal_tx_completion_status *ts,
  3745. struct dp_peer *peer, uint8_t ring_id)
  3746. {
  3747. uint32_t length;
  3748. qdf_ether_header_t *eh;
  3749. struct dp_vdev *vdev = NULL;
  3750. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3751. enum qdf_dp_tx_rx_status dp_status;
  3752. if (!nbuf) {
  3753. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3754. goto out;
  3755. }
  3756. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3757. length = qdf_nbuf_len(nbuf);
  3758. dp_status = dp_tx_hw_to_qdf(ts->status);
  3759. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3760. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3761. QDF_TRACE_DEFAULT_PDEV_ID,
  3762. qdf_nbuf_data_addr(nbuf),
  3763. sizeof(qdf_nbuf_data(nbuf)),
  3764. tx_desc->id, ts->status, dp_status));
  3765. dp_tx_comp_debug("-------------------- \n"
  3766. "Tx Completion Stats: \n"
  3767. "-------------------- \n"
  3768. "ack_frame_rssi = %d \n"
  3769. "first_msdu = %d \n"
  3770. "last_msdu = %d \n"
  3771. "msdu_part_of_amsdu = %d \n"
  3772. "rate_stats valid = %d \n"
  3773. "bw = %d \n"
  3774. "pkt_type = %d \n"
  3775. "stbc = %d \n"
  3776. "ldpc = %d \n"
  3777. "sgi = %d \n"
  3778. "mcs = %d \n"
  3779. "ofdma = %d \n"
  3780. "tones_in_ru = %d \n"
  3781. "tsf = %d \n"
  3782. "ppdu_id = %d \n"
  3783. "transmit_cnt = %d \n"
  3784. "tid = %d \n"
  3785. "peer_id = %d\n",
  3786. ts->ack_frame_rssi, ts->first_msdu,
  3787. ts->last_msdu, ts->msdu_part_of_amsdu,
  3788. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3789. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3790. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3791. ts->transmit_cnt, ts->tid, ts->peer_id);
  3792. /* Update SoC level stats */
  3793. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3794. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3795. if (!peer) {
  3796. dp_info_rl("peer is null or deletion in progress");
  3797. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3798. goto out;
  3799. }
  3800. vdev = peer->vdev;
  3801. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3802. dp_tx_update_uplink_delay(soc, vdev, ts);
  3803. /* Update per-packet stats for mesh mode */
  3804. if (qdf_unlikely(vdev->mesh_vdev) &&
  3805. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3806. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3807. /* Update peer level stats */
  3808. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3809. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3810. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3811. if ((peer->vdev->tx_encap_type ==
  3812. htt_cmn_pkt_type_ethernet) &&
  3813. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3814. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3815. }
  3816. }
  3817. } else {
  3818. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3819. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3820. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3821. if (qdf_unlikely(peer->in_twt)) {
  3822. DP_STATS_INC_PKT(peer,
  3823. tx.tx_success_twt,
  3824. 1, length);
  3825. }
  3826. }
  3827. }
  3828. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3829. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3830. #ifdef QCA_SUPPORT_RDK_STATS
  3831. if (soc->rdkstats_enabled)
  3832. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3833. tx_desc->timestamp,
  3834. ts->ppdu_id);
  3835. #endif
  3836. out:
  3837. return;
  3838. }
  3839. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  3840. defined(QCA_ENHANCED_STATS_SUPPORT)
  3841. /*
  3842. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  3843. * @peer: Datapath peer handle
  3844. * @length: Length of the packet
  3845. * @tx_status: Tx status from TQM/FW
  3846. * @update: enhanced flag value present in dp_pdev
  3847. *
  3848. * Return: none
  3849. */
  3850. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3851. uint8_t tx_status, bool update)
  3852. {
  3853. if ((!peer->hw_txrx_stats_en) || update) {
  3854. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3855. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3856. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3857. }
  3858. }
  3859. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  3860. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3861. uint8_t tx_status, bool update)
  3862. {
  3863. if (!peer->hw_txrx_stats_en) {
  3864. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3865. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3866. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3867. }
  3868. }
  3869. #else
  3870. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3871. uint8_t tx_status, bool update)
  3872. {
  3873. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3874. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3875. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3876. }
  3877. #endif
  3878. /*
  3879. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  3880. * @nbuf: skb buffer
  3881. *
  3882. * Return: none
  3883. */
  3884. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  3885. static inline
  3886. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  3887. {
  3888. qdf_nbuf_t nbuf = NULL;
  3889. if (next)
  3890. nbuf = next->nbuf;
  3891. if (nbuf) {
  3892. /* prefetch skb->next and first few bytes of skb->cb */
  3893. qdf_prefetch(nbuf);
  3894. /* prefetch skb fields present in different cachelines */
  3895. qdf_prefetch(&nbuf->len);
  3896. qdf_prefetch(&nbuf->users);
  3897. }
  3898. }
  3899. #else
  3900. static inline
  3901. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  3902. {
  3903. }
  3904. #endif
  3905. /**
  3906. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3907. * @soc: core txrx main context
  3908. * @comp_head: software descriptor head pointer
  3909. * @ring_id: ring number
  3910. *
  3911. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3912. * and release the software descriptors after processing is complete
  3913. *
  3914. * Return: none
  3915. */
  3916. static void
  3917. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3918. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3919. {
  3920. struct dp_tx_desc_s *desc;
  3921. struct dp_tx_desc_s *next;
  3922. struct hal_tx_completion_status ts;
  3923. struct dp_peer *peer = NULL;
  3924. uint16_t peer_id = DP_INVALID_PEER;
  3925. qdf_nbuf_t netbuf;
  3926. desc = comp_head;
  3927. while (desc) {
  3928. next = desc->next;
  3929. dp_tx_prefetch_next_nbuf_data(next);
  3930. if (peer_id != desc->peer_id) {
  3931. if (peer)
  3932. dp_peer_unref_delete(peer,
  3933. DP_MOD_ID_TX_COMP);
  3934. peer_id = desc->peer_id;
  3935. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3936. DP_MOD_ID_TX_COMP);
  3937. }
  3938. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3939. struct dp_pdev *pdev = desc->pdev;
  3940. if (qdf_likely(peer))
  3941. dp_tx_update_peer_basic_stats(peer,
  3942. desc->length,
  3943. desc->tx_status,
  3944. false);
  3945. qdf_assert(pdev);
  3946. dp_tx_outstanding_dec(pdev);
  3947. /*
  3948. * Calling a QDF WRAPPER here is creating signifcant
  3949. * performance impact so avoided the wrapper call here
  3950. */
  3951. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3952. desc->id, DP_TX_COMP_UNMAP);
  3953. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3954. desc->nbuf,
  3955. desc->dma_addr,
  3956. QDF_DMA_TO_DEVICE,
  3957. desc->length);
  3958. qdf_nbuf_free(desc->nbuf);
  3959. dp_tx_desc_free(soc, desc, desc->pool_id);
  3960. desc = next;
  3961. continue;
  3962. }
  3963. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3964. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3965. netbuf = desc->nbuf;
  3966. /* check tx complete notification */
  3967. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3968. dp_tx_notify_completion(soc, peer->vdev, desc,
  3969. netbuf, ts.status);
  3970. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3971. dp_tx_desc_release(desc, desc->pool_id);
  3972. desc = next;
  3973. }
  3974. if (peer)
  3975. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3976. }
  3977. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3978. static inline
  3979. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3980. int max_reap_limit)
  3981. {
  3982. bool limit_hit = false;
  3983. limit_hit =
  3984. (num_reaped >= max_reap_limit) ? true : false;
  3985. if (limit_hit)
  3986. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3987. return limit_hit;
  3988. }
  3989. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3990. {
  3991. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3992. }
  3993. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3994. {
  3995. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3996. return cfg->tx_comp_loop_pkt_limit;
  3997. }
  3998. #else
  3999. static inline
  4000. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4001. int max_reap_limit)
  4002. {
  4003. return false;
  4004. }
  4005. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4006. {
  4007. return false;
  4008. }
  4009. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4010. {
  4011. return 0;
  4012. }
  4013. #endif
  4014. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4015. static inline int
  4016. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4017. int *max_reap_limit)
  4018. {
  4019. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4020. max_reap_limit);
  4021. }
  4022. #else
  4023. static inline int
  4024. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4025. int *max_reap_limit)
  4026. {
  4027. return 0;
  4028. }
  4029. #endif
  4030. #ifdef DP_TX_TRACKING
  4031. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4032. {
  4033. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4034. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4035. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4036. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4037. }
  4038. }
  4039. #endif
  4040. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4041. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4042. uint32_t quota)
  4043. {
  4044. void *tx_comp_hal_desc;
  4045. void *last_prefetched_hw_desc = NULL;
  4046. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4047. hal_soc_handle_t hal_soc;
  4048. uint8_t buffer_src;
  4049. struct dp_tx_desc_s *tx_desc = NULL;
  4050. struct dp_tx_desc_s *head_desc = NULL;
  4051. struct dp_tx_desc_s *tail_desc = NULL;
  4052. uint32_t num_processed = 0;
  4053. uint32_t count;
  4054. uint32_t num_avail_for_reap = 0;
  4055. bool force_break = false;
  4056. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4057. int max_reap_limit, ring_near_full;
  4058. DP_HIST_INIT();
  4059. more_data:
  4060. hal_soc = soc->hal_soc;
  4061. /* Re-initialize local variables to be re-used */
  4062. head_desc = NULL;
  4063. tail_desc = NULL;
  4064. count = 0;
  4065. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4066. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4067. &max_reap_limit);
  4068. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4069. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4070. return 0;
  4071. }
  4072. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4073. if (num_avail_for_reap >= quota)
  4074. num_avail_for_reap = quota;
  4075. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4076. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4077. num_avail_for_reap);
  4078. /* Find head descriptor from completion ring */
  4079. while (qdf_likely(num_avail_for_reap--)) {
  4080. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4081. if (qdf_unlikely(!tx_comp_hal_desc))
  4082. break;
  4083. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4084. tx_comp_hal_desc);
  4085. /* If this buffer was not released by TQM or FW, then it is not
  4086. * Tx completion indication, assert */
  4087. if (qdf_unlikely(buffer_src !=
  4088. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4089. (qdf_unlikely(buffer_src !=
  4090. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4091. uint8_t wbm_internal_error;
  4092. dp_err_rl(
  4093. "Tx comp release_src != TQM | FW but from %d",
  4094. buffer_src);
  4095. hal_dump_comp_desc(tx_comp_hal_desc);
  4096. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4097. /* When WBM sees NULL buffer_addr_info in any of
  4098. * ingress rings it sends an error indication,
  4099. * with wbm_internal_error=1, to a specific ring.
  4100. * The WBM2SW ring used to indicate these errors is
  4101. * fixed in HW, and that ring is being used as Tx
  4102. * completion ring. These errors are not related to
  4103. * Tx completions, and should just be ignored
  4104. */
  4105. wbm_internal_error = hal_get_wbm_internal_error(
  4106. hal_soc,
  4107. tx_comp_hal_desc);
  4108. if (wbm_internal_error) {
  4109. dp_err_rl("Tx comp wbm_internal_error!!");
  4110. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4111. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4112. buffer_src)
  4113. dp_handle_wbm_internal_error(
  4114. soc,
  4115. tx_comp_hal_desc,
  4116. hal_tx_comp_get_buffer_type(
  4117. tx_comp_hal_desc));
  4118. } else {
  4119. dp_err_rl("Tx comp wbm_internal_error false");
  4120. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4121. }
  4122. continue;
  4123. }
  4124. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4125. tx_comp_hal_desc,
  4126. &tx_desc);
  4127. if (!tx_desc) {
  4128. dp_err("unable to retrieve tx_desc!");
  4129. QDF_BUG(0);
  4130. continue;
  4131. }
  4132. tx_desc->buffer_src = buffer_src;
  4133. /*
  4134. * If the release source is FW, process the HTT status
  4135. */
  4136. if (qdf_unlikely(buffer_src ==
  4137. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4138. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4139. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4140. htt_tx_status);
  4141. soc->arch_ops.dp_tx_process_htt_completion(
  4142. soc,
  4143. tx_desc,
  4144. htt_tx_status,
  4145. ring_id);
  4146. } else {
  4147. tx_desc->tx_status =
  4148. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4149. tx_desc->buffer_src = buffer_src;
  4150. /*
  4151. * If the fast completion mode is enabled extended
  4152. * metadata from descriptor is not copied
  4153. */
  4154. if (qdf_likely(tx_desc->flags &
  4155. DP_TX_DESC_FLAG_SIMPLE))
  4156. goto add_to_pool;
  4157. /*
  4158. * If the descriptor is already freed in vdev_detach,
  4159. * continue to next descriptor
  4160. */
  4161. if (qdf_unlikely
  4162. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4163. !tx_desc->flags)) {
  4164. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4165. tx_desc->id);
  4166. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4167. dp_tx_desc_check_corruption(tx_desc);
  4168. continue;
  4169. }
  4170. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4171. dp_tx_comp_info_rl("pdev in down state %d",
  4172. tx_desc->id);
  4173. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4174. dp_tx_comp_free_buf(soc, tx_desc);
  4175. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4176. goto next_desc;
  4177. }
  4178. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4179. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4180. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4181. tx_desc->flags, tx_desc->id);
  4182. qdf_assert_always(0);
  4183. }
  4184. /* Collect hw completion contents */
  4185. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4186. &tx_desc->comp, 1);
  4187. add_to_pool:
  4188. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4189. /* First ring descriptor on the cycle */
  4190. if (!head_desc) {
  4191. head_desc = tx_desc;
  4192. tail_desc = tx_desc;
  4193. }
  4194. tail_desc->next = tx_desc;
  4195. tx_desc->next = NULL;
  4196. tail_desc = tx_desc;
  4197. }
  4198. next_desc:
  4199. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4200. /*
  4201. * Processed packet count is more than given quota
  4202. * stop to processing
  4203. */
  4204. count++;
  4205. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4206. num_avail_for_reap,
  4207. hal_ring_hdl,
  4208. &last_prefetched_hw_desc,
  4209. &last_prefetched_sw_desc);
  4210. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4211. break;
  4212. }
  4213. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4214. /* Process the reaped descriptors */
  4215. if (head_desc)
  4216. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4217. /*
  4218. * If we are processing in near-full condition, there are 3 scenario
  4219. * 1) Ring entries has reached critical state
  4220. * 2) Ring entries are still near high threshold
  4221. * 3) Ring entries are below the safe level
  4222. *
  4223. * One more loop will move te state to normal processing and yield
  4224. */
  4225. if (ring_near_full)
  4226. goto more_data;
  4227. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4228. if (num_processed >= quota)
  4229. force_break = true;
  4230. if (!force_break &&
  4231. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4232. hal_ring_hdl)) {
  4233. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4234. if (!hif_exec_should_yield(soc->hif_handle,
  4235. int_ctx->dp_intr_id))
  4236. goto more_data;
  4237. }
  4238. }
  4239. DP_TX_HIST_STATS_PER_PDEV();
  4240. return num_processed;
  4241. }
  4242. #ifdef FEATURE_WLAN_TDLS
  4243. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4244. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4245. {
  4246. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4247. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4248. DP_MOD_ID_TDLS);
  4249. if (!vdev) {
  4250. dp_err("vdev handle for id %d is NULL", vdev_id);
  4251. return NULL;
  4252. }
  4253. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4254. vdev->is_tdls_frame = true;
  4255. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4256. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4257. }
  4258. #endif
  4259. /**
  4260. * dp_tx_vdev_attach() - attach vdev to dp tx
  4261. * @vdev: virtual device instance
  4262. *
  4263. * Return: QDF_STATUS_SUCCESS: success
  4264. * QDF_STATUS_E_RESOURCES: Error return
  4265. */
  4266. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4267. {
  4268. int pdev_id;
  4269. /*
  4270. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4271. */
  4272. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4273. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4274. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4275. vdev->vdev_id);
  4276. pdev_id =
  4277. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4278. vdev->pdev->pdev_id);
  4279. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4280. /*
  4281. * Set HTT Extension Valid bit to 0 by default
  4282. */
  4283. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4284. dp_tx_vdev_update_search_flags(vdev);
  4285. return QDF_STATUS_SUCCESS;
  4286. }
  4287. #ifndef FEATURE_WDS
  4288. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4289. {
  4290. return false;
  4291. }
  4292. #endif
  4293. /**
  4294. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4295. * @vdev: virtual device instance
  4296. *
  4297. * Return: void
  4298. *
  4299. */
  4300. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4301. {
  4302. struct dp_soc *soc = vdev->pdev->soc;
  4303. /*
  4304. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4305. * for TDLS link
  4306. *
  4307. * Enable AddrY (SA based search) only for non-WDS STA and
  4308. * ProxySTA VAP (in HKv1) modes.
  4309. *
  4310. * In all other VAP modes, only DA based search should be
  4311. * enabled
  4312. */
  4313. if (vdev->opmode == wlan_op_mode_sta &&
  4314. vdev->tdls_link_connected)
  4315. vdev->hal_desc_addr_search_flags =
  4316. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4317. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4318. !dp_tx_da_search_override(vdev))
  4319. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4320. else
  4321. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4322. if (vdev->opmode == wlan_op_mode_sta)
  4323. vdev->search_type = soc->sta_mode_search_policy;
  4324. else
  4325. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4326. }
  4327. static inline bool
  4328. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4329. struct dp_vdev *vdev,
  4330. struct dp_tx_desc_s *tx_desc)
  4331. {
  4332. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4333. return false;
  4334. /*
  4335. * if vdev is given, then only check whether desc
  4336. * vdev match. if vdev is NULL, then check whether
  4337. * desc pdev match.
  4338. */
  4339. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4340. (tx_desc->pdev == pdev);
  4341. }
  4342. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4343. /**
  4344. * dp_tx_desc_flush() - release resources associated
  4345. * to TX Desc
  4346. *
  4347. * @dp_pdev: Handle to DP pdev structure
  4348. * @vdev: virtual device instance
  4349. * NULL: no specific Vdev is required and check all allcated TX desc
  4350. * on this pdev.
  4351. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4352. *
  4353. * @force_free:
  4354. * true: flush the TX desc.
  4355. * false: only reset the Vdev in each allocated TX desc
  4356. * that associated to current Vdev.
  4357. *
  4358. * This function will go through the TX desc pool to flush
  4359. * the outstanding TX data or reset Vdev to NULL in associated TX
  4360. * Desc.
  4361. */
  4362. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4363. bool force_free)
  4364. {
  4365. uint8_t i;
  4366. uint32_t j;
  4367. uint32_t num_desc, page_id, offset;
  4368. uint16_t num_desc_per_page;
  4369. struct dp_soc *soc = pdev->soc;
  4370. struct dp_tx_desc_s *tx_desc = NULL;
  4371. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4372. if (!vdev && !force_free) {
  4373. dp_err("Reset TX desc vdev, Vdev param is required!");
  4374. return;
  4375. }
  4376. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4377. tx_desc_pool = &soc->tx_desc[i];
  4378. if (!(tx_desc_pool->pool_size) ||
  4379. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4380. !(tx_desc_pool->desc_pages.cacheable_pages))
  4381. continue;
  4382. /*
  4383. * Add flow pool lock protection in case pool is freed
  4384. * due to all tx_desc is recycled when handle TX completion.
  4385. * this is not necessary when do force flush as:
  4386. * a. double lock will happen if dp_tx_desc_release is
  4387. * also trying to acquire it.
  4388. * b. dp interrupt has been disabled before do force TX desc
  4389. * flush in dp_pdev_deinit().
  4390. */
  4391. if (!force_free)
  4392. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4393. num_desc = tx_desc_pool->pool_size;
  4394. num_desc_per_page =
  4395. tx_desc_pool->desc_pages.num_element_per_page;
  4396. for (j = 0; j < num_desc; j++) {
  4397. page_id = j / num_desc_per_page;
  4398. offset = j % num_desc_per_page;
  4399. if (qdf_unlikely(!(tx_desc_pool->
  4400. desc_pages.cacheable_pages)))
  4401. break;
  4402. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4403. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4404. /*
  4405. * Free TX desc if force free is
  4406. * required, otherwise only reset vdev
  4407. * in this TX desc.
  4408. */
  4409. if (force_free) {
  4410. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4411. dp_tx_comp_free_buf(soc, tx_desc);
  4412. dp_tx_desc_release(tx_desc, i);
  4413. } else {
  4414. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4415. }
  4416. }
  4417. }
  4418. if (!force_free)
  4419. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4420. }
  4421. }
  4422. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4423. /**
  4424. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4425. *
  4426. * @soc: Handle to DP soc structure
  4427. * @tx_desc: pointer of one TX desc
  4428. * @desc_pool_id: TX Desc pool id
  4429. */
  4430. static inline void
  4431. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4432. uint8_t desc_pool_id)
  4433. {
  4434. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4435. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4436. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4437. }
  4438. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4439. bool force_free)
  4440. {
  4441. uint8_t i, num_pool;
  4442. uint32_t j;
  4443. uint32_t num_desc, page_id, offset;
  4444. uint16_t num_desc_per_page;
  4445. struct dp_soc *soc = pdev->soc;
  4446. struct dp_tx_desc_s *tx_desc = NULL;
  4447. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4448. if (!vdev && !force_free) {
  4449. dp_err("Reset TX desc vdev, Vdev param is required!");
  4450. return;
  4451. }
  4452. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4453. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4454. for (i = 0; i < num_pool; i++) {
  4455. tx_desc_pool = &soc->tx_desc[i];
  4456. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4457. continue;
  4458. num_desc_per_page =
  4459. tx_desc_pool->desc_pages.num_element_per_page;
  4460. for (j = 0; j < num_desc; j++) {
  4461. page_id = j / num_desc_per_page;
  4462. offset = j % num_desc_per_page;
  4463. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4464. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4465. if (force_free) {
  4466. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4467. dp_tx_comp_free_buf(soc, tx_desc);
  4468. dp_tx_desc_release(tx_desc, i);
  4469. } else {
  4470. dp_tx_desc_reset_vdev(soc, tx_desc,
  4471. i);
  4472. }
  4473. }
  4474. }
  4475. }
  4476. }
  4477. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4478. /**
  4479. * dp_tx_vdev_detach() - detach vdev from dp tx
  4480. * @vdev: virtual device instance
  4481. *
  4482. * Return: QDF_STATUS_SUCCESS: success
  4483. * QDF_STATUS_E_RESOURCES: Error return
  4484. */
  4485. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4486. {
  4487. struct dp_pdev *pdev = vdev->pdev;
  4488. /* Reset TX desc associated to this Vdev as NULL */
  4489. dp_tx_desc_flush(pdev, vdev, false);
  4490. return QDF_STATUS_SUCCESS;
  4491. }
  4492. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4493. /* Pools will be allocated dynamically */
  4494. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4495. int num_desc)
  4496. {
  4497. uint8_t i;
  4498. for (i = 0; i < num_pool; i++) {
  4499. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4500. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4501. }
  4502. return QDF_STATUS_SUCCESS;
  4503. }
  4504. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4505. int num_desc)
  4506. {
  4507. return QDF_STATUS_SUCCESS;
  4508. }
  4509. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4510. {
  4511. }
  4512. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4513. {
  4514. uint8_t i;
  4515. for (i = 0; i < num_pool; i++)
  4516. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4517. }
  4518. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4519. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4520. int num_desc)
  4521. {
  4522. uint8_t i, count;
  4523. /* Allocate software Tx descriptor pools */
  4524. for (i = 0; i < num_pool; i++) {
  4525. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4526. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4527. FL("Tx Desc Pool alloc %d failed %pK"),
  4528. i, soc);
  4529. goto fail;
  4530. }
  4531. }
  4532. return QDF_STATUS_SUCCESS;
  4533. fail:
  4534. for (count = 0; count < i; count++)
  4535. dp_tx_desc_pool_free(soc, count);
  4536. return QDF_STATUS_E_NOMEM;
  4537. }
  4538. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4539. int num_desc)
  4540. {
  4541. uint8_t i;
  4542. for (i = 0; i < num_pool; i++) {
  4543. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4545. FL("Tx Desc Pool init %d failed %pK"),
  4546. i, soc);
  4547. return QDF_STATUS_E_NOMEM;
  4548. }
  4549. }
  4550. return QDF_STATUS_SUCCESS;
  4551. }
  4552. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4553. {
  4554. uint8_t i;
  4555. for (i = 0; i < num_pool; i++)
  4556. dp_tx_desc_pool_deinit(soc, i);
  4557. }
  4558. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4559. {
  4560. uint8_t i;
  4561. for (i = 0; i < num_pool; i++)
  4562. dp_tx_desc_pool_free(soc, i);
  4563. }
  4564. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4565. /**
  4566. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4567. * @soc: core txrx main context
  4568. * @num_pool: number of pools
  4569. *
  4570. */
  4571. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4572. {
  4573. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4574. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4575. }
  4576. /**
  4577. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4578. * @soc: core txrx main context
  4579. * @num_pool: number of pools
  4580. *
  4581. */
  4582. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4583. {
  4584. dp_tx_tso_desc_pool_free(soc, num_pool);
  4585. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4586. }
  4587. /**
  4588. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4589. * @soc: core txrx main context
  4590. *
  4591. * This function frees all tx related descriptors as below
  4592. * 1. Regular TX descriptors (static pools)
  4593. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4594. * 3. TSO descriptors
  4595. *
  4596. */
  4597. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4598. {
  4599. uint8_t num_pool;
  4600. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4601. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4602. dp_tx_ext_desc_pool_free(soc, num_pool);
  4603. dp_tx_delete_static_pools(soc, num_pool);
  4604. }
  4605. /**
  4606. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4607. * @soc: core txrx main context
  4608. *
  4609. * This function de-initializes all tx related descriptors as below
  4610. * 1. Regular TX descriptors (static pools)
  4611. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4612. * 3. TSO descriptors
  4613. *
  4614. */
  4615. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4616. {
  4617. uint8_t num_pool;
  4618. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4619. dp_tx_flow_control_deinit(soc);
  4620. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4621. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4622. dp_tx_deinit_static_pools(soc, num_pool);
  4623. }
  4624. /**
  4625. * dp_tso_attach() - TSO attach handler
  4626. * @txrx_soc: Opaque Dp handle
  4627. *
  4628. * Reserve TSO descriptor buffers
  4629. *
  4630. * Return: QDF_STATUS_E_FAILURE on failure or
  4631. * QDF_STATUS_SUCCESS on success
  4632. */
  4633. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4634. uint8_t num_pool,
  4635. uint16_t num_desc)
  4636. {
  4637. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4638. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4639. return QDF_STATUS_E_FAILURE;
  4640. }
  4641. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4642. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4643. num_pool, soc);
  4644. return QDF_STATUS_E_FAILURE;
  4645. }
  4646. return QDF_STATUS_SUCCESS;
  4647. }
  4648. /**
  4649. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4650. * @soc: DP soc handle
  4651. * @num_pool: Number of pools
  4652. * @num_desc: Number of descriptors
  4653. *
  4654. * Initialize TSO descriptor pools
  4655. *
  4656. * Return: QDF_STATUS_E_FAILURE on failure or
  4657. * QDF_STATUS_SUCCESS on success
  4658. */
  4659. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4660. uint8_t num_pool,
  4661. uint16_t num_desc)
  4662. {
  4663. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4664. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4665. return QDF_STATUS_E_FAILURE;
  4666. }
  4667. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4668. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4669. num_pool, soc);
  4670. return QDF_STATUS_E_FAILURE;
  4671. }
  4672. return QDF_STATUS_SUCCESS;
  4673. }
  4674. /**
  4675. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4676. * @soc: core txrx main context
  4677. *
  4678. * This function allocates memory for following descriptor pools
  4679. * 1. regular sw tx descriptor pools (static pools)
  4680. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4681. * 3. TSO descriptor pools
  4682. *
  4683. * Return: QDF_STATUS_SUCCESS: success
  4684. * QDF_STATUS_E_RESOURCES: Error return
  4685. */
  4686. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4687. {
  4688. uint8_t num_pool;
  4689. uint32_t num_desc;
  4690. uint32_t num_ext_desc;
  4691. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4692. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4693. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4695. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4696. __func__, num_pool, num_desc);
  4697. if ((num_pool > MAX_TXDESC_POOLS) ||
  4698. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4699. goto fail1;
  4700. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4701. goto fail1;
  4702. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4703. goto fail2;
  4704. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4705. return QDF_STATUS_SUCCESS;
  4706. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4707. goto fail3;
  4708. return QDF_STATUS_SUCCESS;
  4709. fail3:
  4710. dp_tx_ext_desc_pool_free(soc, num_pool);
  4711. fail2:
  4712. dp_tx_delete_static_pools(soc, num_pool);
  4713. fail1:
  4714. return QDF_STATUS_E_RESOURCES;
  4715. }
  4716. /**
  4717. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4718. * @soc: core txrx main context
  4719. *
  4720. * This function initializes the following TX descriptor pools
  4721. * 1. regular sw tx descriptor pools (static pools)
  4722. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4723. * 3. TSO descriptor pools
  4724. *
  4725. * Return: QDF_STATUS_SUCCESS: success
  4726. * QDF_STATUS_E_RESOURCES: Error return
  4727. */
  4728. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4729. {
  4730. uint8_t num_pool;
  4731. uint32_t num_desc;
  4732. uint32_t num_ext_desc;
  4733. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4734. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4735. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4736. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4737. goto fail1;
  4738. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4739. goto fail2;
  4740. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4741. return QDF_STATUS_SUCCESS;
  4742. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4743. goto fail3;
  4744. dp_tx_flow_control_init(soc);
  4745. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4746. return QDF_STATUS_SUCCESS;
  4747. fail3:
  4748. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4749. fail2:
  4750. dp_tx_deinit_static_pools(soc, num_pool);
  4751. fail1:
  4752. return QDF_STATUS_E_RESOURCES;
  4753. }
  4754. /**
  4755. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4756. * @txrx_soc: dp soc handle
  4757. *
  4758. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4759. * QDF_STATUS_E_FAILURE
  4760. */
  4761. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4762. {
  4763. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4764. uint8_t num_pool;
  4765. uint32_t num_desc;
  4766. uint32_t num_ext_desc;
  4767. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4768. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4769. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4770. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4771. return QDF_STATUS_E_FAILURE;
  4772. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4773. return QDF_STATUS_E_FAILURE;
  4774. return QDF_STATUS_SUCCESS;
  4775. }
  4776. /**
  4777. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4778. * @txrx_soc: dp soc handle
  4779. *
  4780. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4781. */
  4782. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4783. {
  4784. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4785. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4786. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4787. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4788. return QDF_STATUS_SUCCESS;
  4789. }