bus.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "bus.h"
  7. #include "debug.h"
  8. #include "pci.h"
  9. enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev)
  10. {
  11. if (!dev)
  12. return CNSS_BUS_NONE;
  13. if (!dev->bus)
  14. return CNSS_BUS_NONE;
  15. if (memcmp(dev->bus->name, "pci", 3) == 0)
  16. return CNSS_BUS_PCI;
  17. else
  18. return CNSS_BUS_NONE;
  19. }
  20. enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv)
  21. {
  22. int ret;
  23. struct device *dev;
  24. u32 bus_type_dt = CNSS_BUS_NONE;
  25. if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
  26. dev = &plat_priv->plat_dev->dev;
  27. ret = of_property_read_u32(dev->of_node, "qcom,bus-type",
  28. &bus_type_dt);
  29. if (!ret)
  30. if (bus_type_dt < CNSS_BUS_MAX)
  31. cnss_pr_dbg("Got bus type[%u] from dt\n",
  32. bus_type_dt);
  33. else
  34. bus_type_dt = CNSS_BUS_NONE;
  35. else
  36. cnss_pr_err("No bus type for multi-exchg dt\n");
  37. return bus_type_dt;
  38. }
  39. switch (plat_priv->device_id) {
  40. case QCA6174_DEVICE_ID:
  41. case QCA6290_DEVICE_ID:
  42. case QCA6390_DEVICE_ID:
  43. case QCA6490_DEVICE_ID:
  44. case KIWI_DEVICE_ID:
  45. case MANGO_DEVICE_ID:
  46. case PEACH_DEVICE_ID:
  47. return CNSS_BUS_PCI;
  48. default:
  49. cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id);
  50. return CNSS_BUS_NONE;
  51. }
  52. }
  53. void *cnss_bus_dev_to_bus_priv(struct device *dev)
  54. {
  55. if (!dev)
  56. return NULL;
  57. switch (cnss_get_dev_bus_type(dev)) {
  58. case CNSS_BUS_PCI:
  59. return cnss_get_pci_priv(to_pci_dev(dev));
  60. default:
  61. return NULL;
  62. }
  63. }
  64. struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev)
  65. {
  66. void *bus_priv;
  67. if (!dev)
  68. return cnss_get_plat_priv(NULL);
  69. bus_priv = cnss_bus_dev_to_bus_priv(dev);
  70. if (!bus_priv)
  71. return NULL;
  72. switch (cnss_get_dev_bus_type(dev)) {
  73. case CNSS_BUS_PCI:
  74. return cnss_pci_priv_to_plat_priv(bus_priv);
  75. default:
  76. return NULL;
  77. }
  78. }
  79. int cnss_bus_init(struct cnss_plat_data *plat_priv)
  80. {
  81. if (!plat_priv)
  82. return -ENODEV;
  83. switch (plat_priv->bus_type) {
  84. case CNSS_BUS_PCI:
  85. return cnss_pci_init(plat_priv);
  86. default:
  87. cnss_pr_err("Unsupported bus type: %d\n",
  88. plat_priv->bus_type);
  89. return -EINVAL;
  90. }
  91. }
  92. void cnss_bus_deinit(struct cnss_plat_data *plat_priv)
  93. {
  94. if (!plat_priv)
  95. return;
  96. switch (plat_priv->bus_type) {
  97. case CNSS_BUS_PCI:
  98. return cnss_pci_deinit(plat_priv);
  99. default:
  100. cnss_pr_err("Unsupported bus type: %d\n",
  101. plat_priv->bus_type);
  102. return;
  103. }
  104. }
  105. void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv,
  106. char *prefix_name, char *name)
  107. {
  108. if (!plat_priv)
  109. return;
  110. switch (plat_priv->bus_type) {
  111. case CNSS_BUS_PCI:
  112. return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv,
  113. prefix_name, name);
  114. default:
  115. cnss_pr_err("Unsupported bus type: %d\n",
  116. plat_priv->bus_type);
  117. return;
  118. }
  119. }
  120. int cnss_bus_load_m3(struct cnss_plat_data *plat_priv)
  121. {
  122. if (!plat_priv)
  123. return -ENODEV;
  124. switch (plat_priv->bus_type) {
  125. case CNSS_BUS_PCI:
  126. return cnss_pci_load_m3(plat_priv->bus_priv);
  127. default:
  128. cnss_pr_err("Unsupported bus type: %d\n",
  129. plat_priv->bus_type);
  130. return -EINVAL;
  131. }
  132. }
  133. int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv)
  134. {
  135. if (!plat_priv)
  136. return -ENODEV;
  137. switch (plat_priv->bus_type) {
  138. case CNSS_BUS_PCI:
  139. return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv);
  140. default:
  141. cnss_pr_err("Unsupported bus type: %d\n",
  142. plat_priv->bus_type);
  143. return -EINVAL;
  144. }
  145. }
  146. int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv)
  147. {
  148. if (!plat_priv)
  149. return -ENODEV;
  150. switch (plat_priv->bus_type) {
  151. case CNSS_BUS_PCI:
  152. return cnss_pci_alloc_fw_mem(plat_priv->bus_priv);
  153. default:
  154. cnss_pr_err("Unsupported bus type: %d\n",
  155. plat_priv->bus_type);
  156. return -EINVAL;
  157. }
  158. }
  159. int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv)
  160. {
  161. if (!plat_priv)
  162. return -ENODEV;
  163. switch (plat_priv->bus_type) {
  164. case CNSS_BUS_PCI:
  165. return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv);
  166. default:
  167. cnss_pr_err("Unsupported bus type: %d\n",
  168. plat_priv->bus_type);
  169. return -EINVAL;
  170. }
  171. }
  172. void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv)
  173. {
  174. if (!plat_priv)
  175. return;
  176. switch (plat_priv->bus_type) {
  177. case CNSS_BUS_PCI:
  178. cnss_pci_free_qdss_mem(plat_priv->bus_priv);
  179. return;
  180. default:
  181. cnss_pr_err("Unsupported bus type: %d\n",
  182. plat_priv->bus_type);
  183. return;
  184. }
  185. }
  186. u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv)
  187. {
  188. if (!plat_priv)
  189. return -ENODEV;
  190. switch (plat_priv->bus_type) {
  191. case CNSS_BUS_PCI:
  192. return cnss_pci_get_wake_msi(plat_priv->bus_priv);
  193. default:
  194. cnss_pr_err("Unsupported bus type: %d\n",
  195. plat_priv->bus_type);
  196. return -EINVAL;
  197. }
  198. }
  199. int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
  200. {
  201. if (!plat_priv)
  202. return -ENODEV;
  203. switch (plat_priv->bus_type) {
  204. case CNSS_BUS_PCI:
  205. return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv);
  206. default:
  207. cnss_pr_err("Unsupported bus type: %d\n",
  208. plat_priv->bus_type);
  209. return -EINVAL;
  210. }
  211. }
  212. int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
  213. {
  214. if (!plat_priv)
  215. return -ENODEV;
  216. switch (plat_priv->bus_type) {
  217. case CNSS_BUS_PCI:
  218. return cnss_pci_qmi_send_get(plat_priv->bus_priv);
  219. default:
  220. cnss_pr_err("Unsupported bus type: %d\n",
  221. plat_priv->bus_type);
  222. return -EINVAL;
  223. }
  224. }
  225. int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
  226. {
  227. if (!plat_priv)
  228. return -ENODEV;
  229. switch (plat_priv->bus_type) {
  230. case CNSS_BUS_PCI:
  231. return cnss_pci_qmi_send_put(plat_priv->bus_priv);
  232. default:
  233. cnss_pr_err("Unsupported bus type: %d\n",
  234. plat_priv->bus_type);
  235. return -EINVAL;
  236. }
  237. }
  238. void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
  239. {
  240. struct cnss_plat_data *plat_priv =
  241. from_timer(plat_priv, t, fw_boot_timer);
  242. if (!plat_priv)
  243. return;
  244. switch (plat_priv->bus_type) {
  245. case CNSS_BUS_PCI:
  246. return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv);
  247. default:
  248. cnss_pr_err("Unsupported bus type: %d\n",
  249. plat_priv->bus_type);
  250. return;
  251. }
  252. }
  253. void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic)
  254. {
  255. if (!plat_priv)
  256. return;
  257. switch (plat_priv->bus_type) {
  258. case CNSS_BUS_PCI:
  259. return cnss_pci_collect_dump_info(plat_priv->bus_priv,
  260. in_panic);
  261. default:
  262. cnss_pr_err("Unsupported bus type: %d\n",
  263. plat_priv->bus_type);
  264. return;
  265. }
  266. }
  267. void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv)
  268. {
  269. if (!plat_priv)
  270. return;
  271. switch (plat_priv->bus_type) {
  272. case CNSS_BUS_PCI:
  273. return cnss_pci_device_crashed(plat_priv->bus_priv);
  274. default:
  275. cnss_pr_err("Unsupported bus type: %d\n",
  276. plat_priv->bus_type);
  277. return;
  278. }
  279. }
  280. int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv)
  281. {
  282. if (!plat_priv)
  283. return -ENODEV;
  284. switch (plat_priv->bus_type) {
  285. case CNSS_BUS_PCI:
  286. return cnss_pci_call_driver_probe(plat_priv->bus_priv);
  287. default:
  288. cnss_pr_err("Unsupported bus type: %d\n",
  289. plat_priv->bus_type);
  290. return -EINVAL;
  291. }
  292. }
  293. int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv)
  294. {
  295. if (!plat_priv)
  296. return -ENODEV;
  297. switch (plat_priv->bus_type) {
  298. case CNSS_BUS_PCI:
  299. return cnss_pci_call_driver_remove(plat_priv->bus_priv);
  300. default:
  301. cnss_pr_err("Unsupported bus type: %d\n",
  302. plat_priv->bus_type);
  303. return -EINVAL;
  304. }
  305. }
  306. int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv)
  307. {
  308. if (!plat_priv)
  309. return -ENODEV;
  310. switch (plat_priv->bus_type) {
  311. case CNSS_BUS_PCI:
  312. return cnss_pci_dev_powerup(plat_priv->bus_priv);
  313. default:
  314. cnss_pr_err("Unsupported bus type: %d\n",
  315. plat_priv->bus_type);
  316. return -EINVAL;
  317. }
  318. }
  319. int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv)
  320. {
  321. if (!plat_priv)
  322. return -ENODEV;
  323. switch (plat_priv->bus_type) {
  324. case CNSS_BUS_PCI:
  325. return cnss_pci_dev_shutdown(plat_priv->bus_priv);
  326. default:
  327. cnss_pr_err("Unsupported bus type: %d\n",
  328. plat_priv->bus_type);
  329. return -EINVAL;
  330. }
  331. }
  332. int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv)
  333. {
  334. if (!plat_priv)
  335. return -ENODEV;
  336. switch (plat_priv->bus_type) {
  337. case CNSS_BUS_PCI:
  338. return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv);
  339. default:
  340. cnss_pr_err("Unsupported bus type: %d\n",
  341. plat_priv->bus_type);
  342. return -EINVAL;
  343. }
  344. }
  345. int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv)
  346. {
  347. if (!plat_priv)
  348. return -ENODEV;
  349. switch (plat_priv->bus_type) {
  350. case CNSS_BUS_PCI:
  351. return cnss_pci_dev_ramdump(plat_priv->bus_priv);
  352. default:
  353. cnss_pr_err("Unsupported bus type: %d\n",
  354. plat_priv->bus_type);
  355. return -EINVAL;
  356. }
  357. }
  358. int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data)
  359. {
  360. if (!plat_priv)
  361. return -ENODEV;
  362. switch (plat_priv->bus_type) {
  363. case CNSS_BUS_PCI:
  364. return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data);
  365. default:
  366. cnss_pr_err("Unsupported bus type: %d\n",
  367. plat_priv->bus_type);
  368. return -EINVAL;
  369. }
  370. }
  371. int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv)
  372. {
  373. if (!plat_priv)
  374. return -ENODEV;
  375. switch (plat_priv->bus_type) {
  376. case CNSS_BUS_PCI:
  377. return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv);
  378. default:
  379. cnss_pr_err("Unsupported bus type: %d\n",
  380. plat_priv->bus_type);
  381. return -EINVAL;
  382. }
  383. }
  384. int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
  385. int modem_current_status)
  386. {
  387. if (!plat_priv)
  388. return -ENODEV;
  389. switch (plat_priv->bus_type) {
  390. case CNSS_BUS_PCI:
  391. return cnss_pci_call_driver_modem_status(plat_priv->bus_priv,
  392. modem_current_status);
  393. default:
  394. cnss_pr_err("Unsupported bus type: %d\n",
  395. plat_priv->bus_type);
  396. return -EINVAL;
  397. }
  398. }
  399. int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
  400. enum cnss_driver_status status)
  401. {
  402. if (!plat_priv)
  403. return -ENODEV;
  404. switch (plat_priv->bus_type) {
  405. case CNSS_BUS_PCI:
  406. return cnss_pci_update_status(plat_priv->bus_priv, status);
  407. default:
  408. cnss_pr_err("Unsupported bus type: %d\n",
  409. plat_priv->bus_type);
  410. return -EINVAL;
  411. }
  412. }
  413. int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv,
  414. enum cnss_driver_status status, void *data)
  415. {
  416. if (!plat_priv)
  417. return -ENODEV;
  418. switch (plat_priv->bus_type) {
  419. case CNSS_BUS_PCI:
  420. return cnss_pci_call_driver_uevent(plat_priv->bus_priv,
  421. status, data);
  422. default:
  423. cnss_pr_err("Unsupported bus type: %d\n",
  424. plat_priv->bus_type);
  425. return -EINVAL;
  426. }
  427. }
  428. int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
  429. {
  430. if (!plat_priv)
  431. return -ENODEV;
  432. switch (plat_priv->bus_type) {
  433. case CNSS_BUS_PCI:
  434. return cnss_pcie_is_device_down(plat_priv->bus_priv);
  435. default:
  436. cnss_pr_dbg("Unsupported bus type: %d\n",
  437. plat_priv->bus_type);
  438. return 0;
  439. }
  440. }
  441. int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv)
  442. {
  443. if (!plat_priv)
  444. return -ENODEV;
  445. switch (plat_priv->bus_type) {
  446. case CNSS_BUS_PCI:
  447. return cnss_pci_check_link_status(plat_priv->bus_priv);
  448. default:
  449. cnss_pr_dbg("Unsupported bus type: %d\n",
  450. plat_priv->bus_type);
  451. return 0;
  452. }
  453. }
  454. int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv)
  455. {
  456. if (!plat_priv)
  457. return -ENODEV;
  458. switch (plat_priv->bus_type) {
  459. case CNSS_BUS_PCI:
  460. return cnss_pci_recover_link_down(plat_priv->bus_priv);
  461. default:
  462. cnss_pr_dbg("Unsupported bus type: %d\n",
  463. plat_priv->bus_type);
  464. return -EINVAL;
  465. }
  466. }
  467. int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
  468. u32 *val, bool raw_access)
  469. {
  470. if (!plat_priv)
  471. return -ENODEV;
  472. switch (plat_priv->bus_type) {
  473. case CNSS_BUS_PCI:
  474. return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
  475. val, raw_access);
  476. default:
  477. cnss_pr_dbg("Unsupported bus type: %d\n",
  478. plat_priv->bus_type);
  479. return 0;
  480. }
  481. }
  482. int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
  483. u32 val, bool raw_access)
  484. {
  485. if (!plat_priv)
  486. return -ENODEV;
  487. switch (plat_priv->bus_type) {
  488. case CNSS_BUS_PCI:
  489. return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
  490. val, raw_access);
  491. default:
  492. cnss_pr_dbg("Unsupported bus type: %d\n",
  493. plat_priv->bus_type);
  494. return 0;
  495. }
  496. }
  497. int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size)
  498. {
  499. if (!plat_priv)
  500. return -ENODEV;
  501. switch (plat_priv->bus_type) {
  502. case CNSS_BUS_PCI:
  503. return cnss_pci_get_iova(plat_priv->bus_priv, addr, size);
  504. default:
  505. cnss_pr_err("Unsupported bus type: %d\n",
  506. plat_priv->bus_type);
  507. return -EINVAL;
  508. }
  509. }
  510. int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr,
  511. u64 *size)
  512. {
  513. if (!plat_priv)
  514. return -ENODEV;
  515. switch (plat_priv->bus_type) {
  516. case CNSS_BUS_PCI:
  517. return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size);
  518. default:
  519. cnss_pr_err("Unsupported bus type: %d\n",
  520. plat_priv->bus_type);
  521. return -EINVAL;
  522. }
  523. }
  524. bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv)
  525. {
  526. if (!plat_priv)
  527. return false;
  528. switch (plat_priv->bus_type) {
  529. case CNSS_BUS_PCI:
  530. return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv);
  531. default:
  532. cnss_pr_err("Unsupported bus type: %d\n",
  533. plat_priv->bus_type);
  534. return false;
  535. }
  536. }
  537. int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv,
  538. unsigned int time_sync_period)
  539. {
  540. if (!plat_priv)
  541. return -ENODEV;
  542. switch (plat_priv->bus_type) {
  543. case CNSS_BUS_PCI:
  544. return cnss_pci_update_time_sync_period(plat_priv->bus_priv,
  545. time_sync_period);
  546. default:
  547. cnss_pr_err("Unsupported bus type: %d\n",
  548. plat_priv->bus_type);
  549. return -EINVAL;
  550. }
  551. }
  552. #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
  553. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv)
  554. {
  555. struct cnss_pci_data *pci_priv;
  556. pci_priv = plat_priv->bus_priv;
  557. if (!pci_priv) {
  558. cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n");
  559. return;
  560. }
  561. switch (plat_priv->bus_type) {
  562. case CNSS_BUS_PCI:
  563. /* MHI satellite configuration is only for KIWI V2 and
  564. * that too only in DRV mode.
  565. */
  566. if (plat_priv->device_id == KIWI_DEVICE_ID &&
  567. plat_priv->device_version.major_version == FW_V2_NUMBER) {
  568. cnss_pr_dbg("Remove MHI satellite configuration\n");
  569. return cnss_mhi_controller_set_base(pci_priv, 0);
  570. }
  571. break;
  572. default:
  573. cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n",
  574. plat_priv->bus_type);
  575. return;
  576. }
  577. return;
  578. }
  579. #else
  580. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv)
  581. {
  582. }
  583. #endif