dsi_ctrl.c 106 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_device.h>
  6. #include <linux/err.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/clk.h>
  9. #include <linux/of_irq.h>
  10. #include <video/mipi_display.h>
  11. #include "msm_drv.h"
  12. #include "msm_kms.h"
  13. #include "msm_mmu.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_clk.h"
  17. #include "dsi_pwr.h"
  18. #include "dsi_catalog.h"
  19. #include "dsi_panel.h"
  20. #include "sde_dbg.h"
  21. #define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL"
  22. #define DSI_CTRL_TX_TO_MS 200
  23. #define TO_ON_OFF(x) ((x) ? "ON" : "OFF")
  24. #define CEIL(x, y) (((x) + ((y)-1)) / (y))
  25. #define TICKS_IN_MICRO_SECOND 1000000
  26. #define DSI_CTRL_DEBUG(c, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: %s: "\
  27. fmt, c ? c->name : "inv", ##__VA_ARGS__)
  28. #define DSI_CTRL_ERR(c, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: %s: "\
  29. fmt, c ? c->name : "inv", ##__VA_ARGS__)
  30. #define DSI_CTRL_INFO(c, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: %s: "\
  31. fmt, c->name, ##__VA_ARGS__)
  32. #define DSI_CTRL_WARN(c, fmt, ...) DRM_WARN("[msm-dsi-warn]: %s: " fmt,\
  33. c ? c->name : "inv", ##__VA_ARGS__)
  34. struct dsi_ctrl_list_item {
  35. struct dsi_ctrl *ctrl;
  36. struct list_head list;
  37. };
  38. static LIST_HEAD(dsi_ctrl_list);
  39. static DEFINE_MUTEX(dsi_ctrl_list_lock);
  40. static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;
  41. static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;
  42. static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2;
  43. static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3;
  44. static const enum dsi_ctrl_version dsi_ctrl_v2_4 = DSI_CTRL_VERSION_2_4;
  45. static const enum dsi_ctrl_version dsi_ctrl_v2_5 = DSI_CTRL_VERSION_2_5;
  46. static const enum dsi_ctrl_version dsi_ctrl_v2_6 = DSI_CTRL_VERSION_2_6;
  47. static const struct of_device_id msm_dsi_of_match[] = {
  48. {
  49. .compatible = "qcom,dsi-ctrl-hw-v1.4",
  50. .data = &dsi_ctrl_v1_4,
  51. },
  52. {
  53. .compatible = "qcom,dsi-ctrl-hw-v2.0",
  54. .data = &dsi_ctrl_v2_0,
  55. },
  56. {
  57. .compatible = "qcom,dsi-ctrl-hw-v2.2",
  58. .data = &dsi_ctrl_v2_2,
  59. },
  60. {
  61. .compatible = "qcom,dsi-ctrl-hw-v2.3",
  62. .data = &dsi_ctrl_v2_3,
  63. },
  64. {
  65. .compatible = "qcom,dsi-ctrl-hw-v2.4",
  66. .data = &dsi_ctrl_v2_4,
  67. },
  68. {
  69. .compatible = "qcom,dsi-ctrl-hw-v2.5",
  70. .data = &dsi_ctrl_v2_5,
  71. },
  72. {
  73. .compatible = "qcom,dsi-ctrl-hw-v2.6",
  74. .data = &dsi_ctrl_v2_6,
  75. },
  76. {}
  77. };
  78. #ifdef CONFIG_DEBUG_FS
  79. static ssize_t debugfs_state_info_read(struct file *file,
  80. char __user *buff,
  81. size_t count,
  82. loff_t *ppos)
  83. {
  84. struct dsi_ctrl *dsi_ctrl = file->private_data;
  85. char *buf;
  86. u32 len = 0;
  87. if (!dsi_ctrl)
  88. return -ENODEV;
  89. if (*ppos)
  90. return 0;
  91. buf = kzalloc(SZ_4K, GFP_KERNEL);
  92. if (!buf)
  93. return -ENOMEM;
  94. /* Dump current state */
  95. len += snprintf((buf + len), (SZ_4K - len), "Current State:\n");
  96. len += snprintf((buf + len), (SZ_4K - len),
  97. "\tCTRL_ENGINE = %s\n",
  98. TO_ON_OFF(dsi_ctrl->current_state.controller_state));
  99. len += snprintf((buf + len), (SZ_4K - len),
  100. "\tVIDEO_ENGINE = %s\n\tCOMMAND_ENGINE = %s\n",
  101. TO_ON_OFF(dsi_ctrl->current_state.vid_engine_state),
  102. TO_ON_OFF(dsi_ctrl->current_state.cmd_engine_state));
  103. /* Dump clock information */
  104. len += snprintf((buf + len), (SZ_4K - len), "\nClock Info:\n");
  105. len += snprintf((buf + len), (SZ_4K - len),
  106. "\tBYTE_CLK = %u, PIXEL_CLK = %u, ESC_CLK = %u\n",
  107. dsi_ctrl->clk_freq.byte_clk_rate,
  108. dsi_ctrl->clk_freq.pix_clk_rate,
  109. dsi_ctrl->clk_freq.esc_clk_rate);
  110. if (len > count)
  111. len = count;
  112. len = min_t(size_t, len, SZ_4K);
  113. if (copy_to_user(buff, buf, len)) {
  114. kfree(buf);
  115. return -EFAULT;
  116. }
  117. *ppos += len;
  118. kfree(buf);
  119. return len;
  120. }
  121. static ssize_t debugfs_reg_dump_read(struct file *file,
  122. char __user *buff,
  123. size_t count,
  124. loff_t *ppos)
  125. {
  126. struct dsi_ctrl *dsi_ctrl = file->private_data;
  127. char *buf;
  128. u32 len = 0;
  129. struct dsi_clk_ctrl_info clk_info;
  130. int rc = 0;
  131. if (!dsi_ctrl)
  132. return -ENODEV;
  133. if (*ppos)
  134. return 0;
  135. buf = kzalloc(SZ_4K, GFP_KERNEL);
  136. if (!buf)
  137. return -ENOMEM;
  138. clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
  139. clk_info.clk_type = DSI_CORE_CLK;
  140. clk_info.clk_state = DSI_CLK_ON;
  141. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  142. if (rc) {
  143. DSI_CTRL_ERR(dsi_ctrl, "failed to enable DSI core clocks\n");
  144. kfree(buf);
  145. return rc;
  146. }
  147. if (dsi_ctrl->hw.ops.reg_dump_to_buffer)
  148. len = dsi_ctrl->hw.ops.reg_dump_to_buffer(&dsi_ctrl->hw,
  149. buf, SZ_4K);
  150. clk_info.clk_state = DSI_CLK_OFF;
  151. rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);
  152. if (rc) {
  153. DSI_CTRL_ERR(dsi_ctrl, "failed to disable DSI core clocks\n");
  154. kfree(buf);
  155. return rc;
  156. }
  157. if (len > count)
  158. len = count;
  159. len = min_t(size_t, len, SZ_4K);
  160. if (copy_to_user(buff, buf, len)) {
  161. kfree(buf);
  162. return -EFAULT;
  163. }
  164. *ppos += len;
  165. kfree(buf);
  166. return len;
  167. }
  168. static ssize_t debugfs_line_count_read(struct file *file,
  169. char __user *user_buf,
  170. size_t user_len,
  171. loff_t *ppos)
  172. {
  173. struct dsi_ctrl *dsi_ctrl = file->private_data;
  174. char *buf;
  175. int rc = 0;
  176. u32 len = 0;
  177. size_t max_len = min_t(size_t, user_len, SZ_4K);
  178. if (!dsi_ctrl)
  179. return -ENODEV;
  180. if (*ppos)
  181. return 0;
  182. buf = kzalloc(max_len, GFP_KERNEL);
  183. if (ZERO_OR_NULL_PTR(buf))
  184. return -ENOMEM;
  185. mutex_lock(&dsi_ctrl->ctrl_lock);
  186. len += scnprintf(buf, max_len, "Command triggered at line: %04x\n",
  187. dsi_ctrl->cmd_trigger_line);
  188. len += scnprintf((buf + len), max_len - len,
  189. "Command triggered at frame: %04x\n",
  190. dsi_ctrl->cmd_trigger_frame);
  191. len += scnprintf((buf + len), max_len - len,
  192. "Command successful at line: %04x\n",
  193. dsi_ctrl->cmd_success_line);
  194. len += scnprintf((buf + len), max_len - len,
  195. "Command successful at frame: %04x\n",
  196. dsi_ctrl->cmd_success_frame);
  197. mutex_unlock(&dsi_ctrl->ctrl_lock);
  198. if (len > max_len)
  199. len = max_len;
  200. if (copy_to_user(user_buf, buf, len)) {
  201. rc = -EFAULT;
  202. goto error;
  203. }
  204. *ppos += len;
  205. error:
  206. kfree(buf);
  207. return len;
  208. }
  209. static const struct file_operations state_info_fops = {
  210. .open = simple_open,
  211. .read = debugfs_state_info_read,
  212. };
  213. static const struct file_operations reg_dump_fops = {
  214. .open = simple_open,
  215. .read = debugfs_reg_dump_read,
  216. };
  217. static const struct file_operations cmd_dma_stats_fops = {
  218. .open = simple_open,
  219. .read = debugfs_line_count_read,
  220. };
  221. static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl,
  222. struct dentry *parent)
  223. {
  224. int rc = 0;
  225. struct dentry *dir, *state_file, *reg_dump, *cmd_dma_logs;
  226. char dbg_name[DSI_DEBUG_NAME_LEN];
  227. if (!dsi_ctrl || !parent) {
  228. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  229. return -EINVAL;
  230. }
  231. dir = debugfs_create_dir(dsi_ctrl->name, parent);
  232. if (IS_ERR_OR_NULL(dir)) {
  233. rc = PTR_ERR(dir);
  234. DSI_CTRL_ERR(dsi_ctrl, "debugfs create dir failed, rc=%d\n",
  235. rc);
  236. goto error;
  237. }
  238. state_file = debugfs_create_file("state_info",
  239. 0444,
  240. dir,
  241. dsi_ctrl,
  242. &state_info_fops);
  243. if (IS_ERR_OR_NULL(state_file)) {
  244. rc = PTR_ERR(state_file);
  245. DSI_CTRL_ERR(dsi_ctrl, "state file failed, rc=%d\n", rc);
  246. goto error_remove_dir;
  247. }
  248. reg_dump = debugfs_create_file("reg_dump",
  249. 0444,
  250. dir,
  251. dsi_ctrl,
  252. &reg_dump_fops);
  253. if (IS_ERR_OR_NULL(reg_dump)) {
  254. rc = PTR_ERR(reg_dump);
  255. DSI_CTRL_ERR(dsi_ctrl, "reg dump file failed, rc=%d\n", rc);
  256. goto error_remove_dir;
  257. }
  258. cmd_dma_logs = debugfs_create_bool("enable_cmd_dma_stats",
  259. 0600,
  260. dir,
  261. &dsi_ctrl->enable_cmd_dma_stats);
  262. if (IS_ERR_OR_NULL(cmd_dma_logs)) {
  263. rc = PTR_ERR(cmd_dma_logs);
  264. DSI_CTRL_ERR(dsi_ctrl,
  265. "enable cmd dma stats failed, rc=%d\n",
  266. rc);
  267. goto error_remove_dir;
  268. }
  269. cmd_dma_logs = debugfs_create_file("cmd_dma_stats",
  270. 0444,
  271. dir,
  272. dsi_ctrl,
  273. &cmd_dma_stats_fops);
  274. if (IS_ERR_OR_NULL(cmd_dma_logs)) {
  275. rc = PTR_ERR(cmd_dma_logs);
  276. DSI_CTRL_ERR(dsi_ctrl, "Line count file failed, rc=%d\n",
  277. rc);
  278. goto error_remove_dir;
  279. }
  280. dsi_ctrl->debugfs_root = dir;
  281. snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_ctrl", dsi_ctrl->cell_index);
  282. sde_dbg_reg_register_base(dbg_name, dsi_ctrl->hw.base,
  283. msm_iomap_size(dsi_ctrl->pdev, "dsi_ctrl"), SDE_DBG_DSI);
  284. error_remove_dir:
  285. debugfs_remove(dir);
  286. error:
  287. return rc;
  288. }
  289. static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
  290. {
  291. debugfs_remove(dsi_ctrl->debugfs_root);
  292. return 0;
  293. }
  294. #else
  295. static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl,
  296. struct dentry *parent)
  297. {
  298. char dbg_name[DSI_DEBUG_NAME_LEN];
  299. snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_ctrl", dsi_ctrl->cell_index);
  300. sde_dbg_reg_register_base(dbg_name, dsi_ctrl->hw.base,
  301. msm_iomap_size(dsi_ctrl->pdev, "dsi_ctrl"), SDE_DBG_DSI);
  302. return 0;
  303. }
  304. static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
  305. {
  306. return 0;
  307. }
  308. #endif /* CONFIG_DEBUG_FS */
  309. static inline struct msm_gem_address_space*
  310. dsi_ctrl_get_aspace(struct dsi_ctrl *dsi_ctrl,
  311. int domain)
  312. {
  313. if (!dsi_ctrl || !dsi_ctrl->drm_dev)
  314. return NULL;
  315. return msm_gem_smmu_address_space_get(dsi_ctrl->drm_dev, domain);
  316. }
  317. static void dsi_ctrl_flush_cmd_dma_queue(struct dsi_ctrl *dsi_ctrl)
  318. {
  319. /*
  320. * If a command is triggered right after another command,
  321. * check if the previous command transfer is completed. If
  322. * transfer is done, cancel any work that has been
  323. * queued. Otherwise wait till the work is scheduled and
  324. * completed before triggering the next command by
  325. * flushing the workqueue.
  326. */
  327. if (atomic_read(&dsi_ctrl->dma_irq_trig)) {
  328. cancel_work_sync(&dsi_ctrl->dma_cmd_wait);
  329. } else {
  330. flush_workqueue(dsi_ctrl->dma_cmd_workq);
  331. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2);
  332. }
  333. }
  334. static void dsi_ctrl_dma_cmd_wait_for_done(struct work_struct *work)
  335. {
  336. int ret = 0;
  337. struct dsi_ctrl *dsi_ctrl = NULL;
  338. u32 status;
  339. u32 mask = DSI_CMD_MODE_DMA_DONE;
  340. struct dsi_ctrl_hw_ops dsi_hw_ops;
  341. dsi_ctrl = container_of(work, struct dsi_ctrl, dma_cmd_wait);
  342. dsi_hw_ops = dsi_ctrl->hw.ops;
  343. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY);
  344. /*
  345. * This atomic state will be set if ISR has been triggered,
  346. * so the wait is not needed.
  347. */
  348. if (atomic_read(&dsi_ctrl->dma_irq_trig))
  349. goto done;
  350. ret = wait_for_completion_timeout(
  351. &dsi_ctrl->irq_info.cmd_dma_done,
  352. msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
  353. if (ret == 0 && !atomic_read(&dsi_ctrl->dma_irq_trig)) {
  354. status = dsi_hw_ops.get_interrupt_status(&dsi_ctrl->hw);
  355. if (status & mask) {
  356. status |= (DSI_CMD_MODE_DMA_DONE | DSI_BTA_DONE);
  357. dsi_hw_ops.clear_interrupt_status(&dsi_ctrl->hw,
  358. status);
  359. DSI_CTRL_WARN(dsi_ctrl,
  360. "dma_tx done but irq not triggered\n");
  361. } else {
  362. DSI_CTRL_ERR(dsi_ctrl,
  363. "Command transfer failed\n");
  364. }
  365. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  366. DSI_SINT_CMD_MODE_DMA_DONE);
  367. }
  368. done:
  369. dsi_ctrl->dma_wait_queued = false;
  370. }
  371. static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl,
  372. enum dsi_ctrl_driver_ops op,
  373. u32 op_state)
  374. {
  375. int rc = 0;
  376. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  377. SDE_EVT32(dsi_ctrl->cell_index, op, op_state);
  378. switch (op) {
  379. case DSI_CTRL_OP_POWER_STATE_CHANGE:
  380. if (state->power_state == op_state) {
  381. DSI_CTRL_ERR(dsi_ctrl, "No change in state, pwr_state=%d\n",
  382. op_state);
  383. rc = -EINVAL;
  384. } else if (state->power_state == DSI_CTRL_POWER_VREG_ON) {
  385. if (state->vid_engine_state == DSI_CTRL_ENGINE_ON) {
  386. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  387. op_state,
  388. state->vid_engine_state);
  389. rc = -EINVAL;
  390. }
  391. }
  392. break;
  393. case DSI_CTRL_OP_CMD_ENGINE:
  394. if (state->cmd_engine_state == op_state) {
  395. DSI_CTRL_ERR(dsi_ctrl, "No change in state, cmd_state=%d\n",
  396. op_state);
  397. rc = -EINVAL;
  398. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  399. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  400. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  401. op,
  402. state->power_state,
  403. state->controller_state);
  404. rc = -EINVAL;
  405. }
  406. break;
  407. case DSI_CTRL_OP_VID_ENGINE:
  408. if (state->vid_engine_state == op_state) {
  409. DSI_CTRL_ERR(dsi_ctrl, "No change in state, cmd_state=%d\n",
  410. op_state);
  411. rc = -EINVAL;
  412. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  413. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  414. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  415. op,
  416. state->power_state,
  417. state->controller_state);
  418. rc = -EINVAL;
  419. }
  420. break;
  421. case DSI_CTRL_OP_HOST_ENGINE:
  422. if (state->controller_state == op_state) {
  423. DSI_CTRL_ERR(dsi_ctrl, "No change in state, ctrl_state=%d\n",
  424. op_state);
  425. rc = -EINVAL;
  426. } else if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  427. DSI_CTRL_ERR(dsi_ctrl, "State error (link is off): op=%d:, %d\n",
  428. op_state,
  429. state->power_state);
  430. rc = -EINVAL;
  431. } else if ((op_state == DSI_CTRL_ENGINE_OFF) &&
  432. ((state->cmd_engine_state != DSI_CTRL_ENGINE_OFF) ||
  433. (state->vid_engine_state != DSI_CTRL_ENGINE_OFF))) {
  434. DSI_CTRL_ERR(dsi_ctrl, "State error (eng on): op=%d: %d, %d\n",
  435. op_state,
  436. state->cmd_engine_state,
  437. state->vid_engine_state);
  438. rc = -EINVAL;
  439. }
  440. break;
  441. case DSI_CTRL_OP_CMD_TX:
  442. if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  443. (!state->host_initialized) ||
  444. (state->cmd_engine_state != DSI_CTRL_ENGINE_ON)) {
  445. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d, %d\n",
  446. op,
  447. state->power_state,
  448. state->host_initialized,
  449. state->cmd_engine_state);
  450. rc = -EINVAL;
  451. }
  452. break;
  453. case DSI_CTRL_OP_HOST_INIT:
  454. if (state->host_initialized == op_state) {
  455. DSI_CTRL_ERR(dsi_ctrl, "No change in state, host_init=%d\n",
  456. op_state);
  457. rc = -EINVAL;
  458. } else if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  459. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  460. op, state->power_state);
  461. rc = -EINVAL;
  462. }
  463. break;
  464. case DSI_CTRL_OP_TPG:
  465. if (state->tpg_enabled == op_state) {
  466. DSI_CTRL_ERR(dsi_ctrl, "No change in state, tpg_enabled=%d\n",
  467. op_state);
  468. rc = -EINVAL;
  469. } else if ((state->power_state != DSI_CTRL_POWER_VREG_ON) ||
  470. (state->controller_state != DSI_CTRL_ENGINE_ON)) {
  471. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d, %d\n",
  472. op,
  473. state->power_state,
  474. state->controller_state);
  475. rc = -EINVAL;
  476. }
  477. break;
  478. case DSI_CTRL_OP_PHY_SW_RESET:
  479. if (state->power_state != DSI_CTRL_POWER_VREG_ON) {
  480. DSI_CTRL_ERR(dsi_ctrl, "State error: op=%d: %d\n",
  481. op, state->power_state);
  482. rc = -EINVAL;
  483. }
  484. break;
  485. case DSI_CTRL_OP_ASYNC_TIMING:
  486. if (state->vid_engine_state != op_state) {
  487. DSI_CTRL_ERR(dsi_ctrl, "Unexpected engine state vid_state=%d\n",
  488. op_state);
  489. rc = -EINVAL;
  490. }
  491. break;
  492. default:
  493. rc = -ENOTSUPP;
  494. break;
  495. }
  496. return rc;
  497. }
  498. bool dsi_ctrl_validate_host_state(struct dsi_ctrl *dsi_ctrl)
  499. {
  500. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  501. if (!state) {
  502. DSI_CTRL_ERR(dsi_ctrl, "Invalid host state for DSI controller\n");
  503. return -EINVAL;
  504. }
  505. if (!state->host_initialized)
  506. return false;
  507. return true;
  508. }
  509. static void dsi_ctrl_update_state(struct dsi_ctrl *dsi_ctrl,
  510. enum dsi_ctrl_driver_ops op,
  511. u32 op_state)
  512. {
  513. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  514. switch (op) {
  515. case DSI_CTRL_OP_POWER_STATE_CHANGE:
  516. state->power_state = op_state;
  517. break;
  518. case DSI_CTRL_OP_CMD_ENGINE:
  519. state->cmd_engine_state = op_state;
  520. break;
  521. case DSI_CTRL_OP_VID_ENGINE:
  522. state->vid_engine_state = op_state;
  523. break;
  524. case DSI_CTRL_OP_HOST_ENGINE:
  525. state->controller_state = op_state;
  526. break;
  527. case DSI_CTRL_OP_HOST_INIT:
  528. state->host_initialized = (op_state == 1) ? true : false;
  529. break;
  530. case DSI_CTRL_OP_TPG:
  531. state->tpg_enabled = (op_state == 1) ? true : false;
  532. break;
  533. case DSI_CTRL_OP_CMD_TX:
  534. case DSI_CTRL_OP_PHY_SW_RESET:
  535. default:
  536. break;
  537. }
  538. }
  539. static int dsi_ctrl_init_regmap(struct platform_device *pdev,
  540. struct dsi_ctrl *ctrl)
  541. {
  542. int rc = 0;
  543. void __iomem *ptr;
  544. ptr = msm_ioremap(pdev, "dsi_ctrl", ctrl->name);
  545. if (IS_ERR(ptr)) {
  546. rc = PTR_ERR(ptr);
  547. return rc;
  548. }
  549. ctrl->hw.base = ptr;
  550. DSI_CTRL_DEBUG(ctrl, "map dsi_ctrl registers to %pK\n", ctrl->hw.base);
  551. switch (ctrl->version) {
  552. case DSI_CTRL_VERSION_1_4:
  553. case DSI_CTRL_VERSION_2_0:
  554. ptr = msm_ioremap(pdev, "mmss_misc", ctrl->name);
  555. if (IS_ERR(ptr)) {
  556. DSI_CTRL_ERR(ctrl, "mmss_misc base address not found\n");
  557. rc = PTR_ERR(ptr);
  558. return rc;
  559. }
  560. ctrl->hw.mmss_misc_base = ptr;
  561. ctrl->hw.disp_cc_base = NULL;
  562. ctrl->hw.mdp_intf_base = NULL;
  563. break;
  564. case DSI_CTRL_VERSION_2_2:
  565. case DSI_CTRL_VERSION_2_3:
  566. case DSI_CTRL_VERSION_2_4:
  567. case DSI_CTRL_VERSION_2_5:
  568. case DSI_CTRL_VERSION_2_6:
  569. ptr = msm_ioremap(pdev, "disp_cc_base", ctrl->name);
  570. if (IS_ERR(ptr)) {
  571. DSI_CTRL_ERR(ctrl, "disp_cc base address not found for\n");
  572. rc = PTR_ERR(ptr);
  573. return rc;
  574. }
  575. ctrl->hw.disp_cc_base = ptr;
  576. ctrl->hw.mmss_misc_base = NULL;
  577. ptr = msm_ioremap(pdev, "mdp_intf_base", ctrl->name);
  578. if (!IS_ERR(ptr))
  579. ctrl->hw.mdp_intf_base = ptr;
  580. break;
  581. default:
  582. break;
  583. }
  584. return rc;
  585. }
  586. static int dsi_ctrl_clocks_deinit(struct dsi_ctrl *ctrl)
  587. {
  588. struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
  589. struct dsi_link_lp_clk_info *lp_link = &ctrl->clk_info.lp_link_clks;
  590. struct dsi_link_hs_clk_info *hs_link = &ctrl->clk_info.hs_link_clks;
  591. struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
  592. if (core->mdp_core_clk)
  593. devm_clk_put(&ctrl->pdev->dev, core->mdp_core_clk);
  594. if (core->iface_clk)
  595. devm_clk_put(&ctrl->pdev->dev, core->iface_clk);
  596. if (core->core_mmss_clk)
  597. devm_clk_put(&ctrl->pdev->dev, core->core_mmss_clk);
  598. if (core->bus_clk)
  599. devm_clk_put(&ctrl->pdev->dev, core->bus_clk);
  600. if (core->mnoc_clk)
  601. devm_clk_put(&ctrl->pdev->dev, core->mnoc_clk);
  602. memset(core, 0x0, sizeof(*core));
  603. if (hs_link->byte_clk)
  604. devm_clk_put(&ctrl->pdev->dev, hs_link->byte_clk);
  605. if (hs_link->pixel_clk)
  606. devm_clk_put(&ctrl->pdev->dev, hs_link->pixel_clk);
  607. if (lp_link->esc_clk)
  608. devm_clk_put(&ctrl->pdev->dev, lp_link->esc_clk);
  609. if (hs_link->byte_intf_clk)
  610. devm_clk_put(&ctrl->pdev->dev, hs_link->byte_intf_clk);
  611. memset(hs_link, 0x0, sizeof(*hs_link));
  612. memset(lp_link, 0x0, sizeof(*lp_link));
  613. if (rcg->byte_clk)
  614. devm_clk_put(&ctrl->pdev->dev, rcg->byte_clk);
  615. if (rcg->pixel_clk)
  616. devm_clk_put(&ctrl->pdev->dev, rcg->pixel_clk);
  617. memset(rcg, 0x0, sizeof(*rcg));
  618. return 0;
  619. }
  620. static int dsi_ctrl_clocks_init(struct platform_device *pdev,
  621. struct dsi_ctrl *ctrl)
  622. {
  623. int rc = 0;
  624. struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
  625. struct dsi_link_lp_clk_info *lp_link = &ctrl->clk_info.lp_link_clks;
  626. struct dsi_link_hs_clk_info *hs_link = &ctrl->clk_info.hs_link_clks;
  627. struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
  628. struct dsi_clk_link_set *xo = &ctrl->clk_info.xo_clk;
  629. core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
  630. if (IS_ERR(core->mdp_core_clk)) {
  631. core->mdp_core_clk = NULL;
  632. DSI_CTRL_DEBUG(ctrl, "failed to get mdp_core_clk, rc=%d\n", rc);
  633. }
  634. core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
  635. if (IS_ERR(core->iface_clk)) {
  636. core->iface_clk = NULL;
  637. DSI_CTRL_DEBUG(ctrl, "failed to get iface_clk, rc=%d\n", rc);
  638. }
  639. core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
  640. if (IS_ERR(core->core_mmss_clk)) {
  641. core->core_mmss_clk = NULL;
  642. DSI_CTRL_DEBUG(ctrl, "failed to get core_mmss_clk, rc=%d\n",
  643. rc);
  644. }
  645. core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
  646. if (IS_ERR(core->bus_clk)) {
  647. core->bus_clk = NULL;
  648. DSI_CTRL_DEBUG(ctrl, "failed to get bus_clk, rc=%d\n", rc);
  649. }
  650. core->mnoc_clk = devm_clk_get(&pdev->dev, "mnoc_clk");
  651. if (IS_ERR(core->mnoc_clk)) {
  652. core->mnoc_clk = NULL;
  653. DSI_CTRL_DEBUG(ctrl, "can't get mnoc clock, rc=%d\n", rc);
  654. }
  655. hs_link->byte_clk = devm_clk_get(&pdev->dev, "byte_clk");
  656. if (IS_ERR(hs_link->byte_clk)) {
  657. rc = PTR_ERR(hs_link->byte_clk);
  658. DSI_CTRL_ERR(ctrl, "failed to get byte_clk, rc=%d\n", rc);
  659. goto fail;
  660. }
  661. hs_link->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk");
  662. if (IS_ERR(hs_link->pixel_clk)) {
  663. rc = PTR_ERR(hs_link->pixel_clk);
  664. DSI_CTRL_ERR(ctrl, "failed to get pixel_clk, rc=%d\n", rc);
  665. goto fail;
  666. }
  667. lp_link->esc_clk = devm_clk_get(&pdev->dev, "esc_clk");
  668. if (IS_ERR(lp_link->esc_clk)) {
  669. rc = PTR_ERR(lp_link->esc_clk);
  670. DSI_CTRL_ERR(ctrl, "failed to get esc_clk, rc=%d\n", rc);
  671. goto fail;
  672. }
  673. hs_link->byte_intf_clk = devm_clk_get(&pdev->dev, "byte_intf_clk");
  674. if (IS_ERR(hs_link->byte_intf_clk)) {
  675. hs_link->byte_intf_clk = NULL;
  676. DSI_CTRL_DEBUG(ctrl, "can't find byte intf clk, rc=%d\n", rc);
  677. }
  678. rcg->byte_clk = devm_clk_get(&pdev->dev, "byte_clk_rcg");
  679. if (IS_ERR(rcg->byte_clk)) {
  680. rc = PTR_ERR(rcg->byte_clk);
  681. DSI_CTRL_ERR(ctrl, "failed to get byte_clk_rcg, rc=%d\n", rc);
  682. goto fail;
  683. }
  684. rcg->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk_rcg");
  685. if (IS_ERR(rcg->pixel_clk)) {
  686. rc = PTR_ERR(rcg->pixel_clk);
  687. DSI_CTRL_ERR(ctrl, "failed to get pixel_clk_rcg, rc=%d\n", rc);
  688. goto fail;
  689. }
  690. xo->byte_clk = devm_clk_get(&pdev->dev, "xo");
  691. if (IS_ERR(xo->byte_clk)) {
  692. xo->byte_clk = NULL;
  693. DSI_CTRL_DEBUG(ctrl, "failed to get xo clk, rc=%d\n", rc);
  694. }
  695. xo->pixel_clk = xo->byte_clk;
  696. return 0;
  697. fail:
  698. dsi_ctrl_clocks_deinit(ctrl);
  699. return rc;
  700. }
  701. static int dsi_ctrl_supplies_deinit(struct dsi_ctrl *ctrl)
  702. {
  703. int i = 0;
  704. int rc = 0;
  705. struct dsi_regulator_info *regs;
  706. regs = &ctrl->pwr_info.digital;
  707. for (i = 0; i < regs->count; i++) {
  708. if (!regs->vregs[i].vreg)
  709. DSI_CTRL_ERR(ctrl,
  710. "vreg is NULL, should not reach here\n");
  711. else
  712. devm_regulator_put(regs->vregs[i].vreg);
  713. }
  714. regs = &ctrl->pwr_info.host_pwr;
  715. for (i = 0; i < regs->count; i++) {
  716. if (!regs->vregs[i].vreg)
  717. DSI_CTRL_ERR(ctrl,
  718. "vreg is NULL, should not reach here\n");
  719. else
  720. devm_regulator_put(regs->vregs[i].vreg);
  721. }
  722. if (!ctrl->pwr_info.host_pwr.vregs) {
  723. devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.host_pwr.vregs);
  724. ctrl->pwr_info.host_pwr.vregs = NULL;
  725. ctrl->pwr_info.host_pwr.count = 0;
  726. }
  727. if (!ctrl->pwr_info.digital.vregs) {
  728. devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.digital.vregs);
  729. ctrl->pwr_info.digital.vregs = NULL;
  730. ctrl->pwr_info.digital.count = 0;
  731. }
  732. return rc;
  733. }
  734. static int dsi_ctrl_supplies_init(struct platform_device *pdev,
  735. struct dsi_ctrl *ctrl)
  736. {
  737. int rc = 0;
  738. int i = 0;
  739. struct dsi_regulator_info *regs;
  740. struct regulator *vreg = NULL;
  741. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  742. &ctrl->pwr_info.digital,
  743. "qcom,core-supply-entries");
  744. if (rc)
  745. DSI_CTRL_DEBUG(ctrl,
  746. "failed to get digital supply, rc = %d\n", rc);
  747. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  748. &ctrl->pwr_info.host_pwr,
  749. "qcom,ctrl-supply-entries");
  750. if (rc) {
  751. DSI_CTRL_ERR(ctrl,
  752. "failed to get host power supplies, rc = %d\n", rc);
  753. goto error_digital;
  754. }
  755. regs = &ctrl->pwr_info.digital;
  756. for (i = 0; i < regs->count; i++) {
  757. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  758. if (IS_ERR(vreg)) {
  759. DSI_CTRL_ERR(ctrl, "failed to get %s regulator\n",
  760. regs->vregs[i].vreg_name);
  761. rc = PTR_ERR(vreg);
  762. goto error_host_pwr;
  763. }
  764. regs->vregs[i].vreg = vreg;
  765. }
  766. regs = &ctrl->pwr_info.host_pwr;
  767. for (i = 0; i < regs->count; i++) {
  768. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  769. if (IS_ERR(vreg)) {
  770. DSI_CTRL_ERR(ctrl, "failed to get %s regulator\n",
  771. regs->vregs[i].vreg_name);
  772. for (--i; i >= 0; i--)
  773. devm_regulator_put(regs->vregs[i].vreg);
  774. rc = PTR_ERR(vreg);
  775. goto error_digital_put;
  776. }
  777. regs->vregs[i].vreg = vreg;
  778. }
  779. return rc;
  780. error_digital_put:
  781. regs = &ctrl->pwr_info.digital;
  782. for (i = 0; i < regs->count; i++)
  783. devm_regulator_put(regs->vregs[i].vreg);
  784. error_host_pwr:
  785. devm_kfree(&pdev->dev, ctrl->pwr_info.host_pwr.vregs);
  786. ctrl->pwr_info.host_pwr.vregs = NULL;
  787. ctrl->pwr_info.host_pwr.count = 0;
  788. error_digital:
  789. if (ctrl->pwr_info.digital.vregs)
  790. devm_kfree(&pdev->dev, ctrl->pwr_info.digital.vregs);
  791. ctrl->pwr_info.digital.vregs = NULL;
  792. ctrl->pwr_info.digital.count = 0;
  793. return rc;
  794. }
  795. static int dsi_ctrl_validate_panel_info(struct dsi_ctrl *dsi_ctrl,
  796. struct dsi_host_config *config)
  797. {
  798. int rc = 0;
  799. struct dsi_host_common_cfg *host_cfg = &config->common_config;
  800. if (config->panel_mode >= DSI_OP_MODE_MAX) {
  801. DSI_CTRL_ERR(dsi_ctrl, "Invalid dsi operation mode (%d)\n",
  802. config->panel_mode);
  803. rc = -EINVAL;
  804. goto err;
  805. }
  806. if ((host_cfg->data_lanes & (DSI_CLOCK_LANE - 1)) == 0) {
  807. DSI_CTRL_ERR(dsi_ctrl, "No data lanes are enabled\n");
  808. rc = -EINVAL;
  809. goto err;
  810. }
  811. err:
  812. return rc;
  813. }
  814. /* Function returns number of bits per pxl */
  815. int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format)
  816. {
  817. u32 bpp = 0;
  818. switch (dst_format) {
  819. case DSI_PIXEL_FORMAT_RGB111:
  820. bpp = 3;
  821. break;
  822. case DSI_PIXEL_FORMAT_RGB332:
  823. bpp = 8;
  824. break;
  825. case DSI_PIXEL_FORMAT_RGB444:
  826. bpp = 12;
  827. break;
  828. case DSI_PIXEL_FORMAT_RGB565:
  829. bpp = 16;
  830. break;
  831. case DSI_PIXEL_FORMAT_RGB666:
  832. case DSI_PIXEL_FORMAT_RGB666_LOOSE:
  833. bpp = 18;
  834. break;
  835. case DSI_PIXEL_FORMAT_RGB888:
  836. bpp = 24;
  837. break;
  838. default:
  839. bpp = 24;
  840. break;
  841. }
  842. return bpp;
  843. }
  844. static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
  845. struct dsi_host_config *config, void *clk_handle,
  846. struct dsi_display_mode *mode)
  847. {
  848. int rc = 0;
  849. u32 num_of_lanes = 0;
  850. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  851. u32 bpp, frame_time_us, byte_intf_clk_div;
  852. u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
  853. byte_clk_rate, byte_intf_clk_rate;
  854. struct dsi_host_common_cfg *host_cfg = &config->common_config;
  855. struct dsi_split_link_config *split_link = &host_cfg->split_link;
  856. struct dsi_mode_info *timing = &config->video_timing;
  857. u64 dsi_transfer_time_us = mode->priv_info->dsi_transfer_time_us;
  858. u64 min_dsi_clk_hz = mode->priv_info->min_dsi_clk_hz;
  859. /* Get bits per pxl in destination format */
  860. bpp = dsi_ctrl_pixel_format_to_bpp(host_cfg->dst_format);
  861. frame_time_us = mult_frac(1000, 1000, (timing->refresh_rate));
  862. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  863. num_of_lanes++;
  864. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  865. num_of_lanes++;
  866. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  867. num_of_lanes++;
  868. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  869. num_of_lanes++;
  870. if (split_link->enabled)
  871. num_of_lanes = split_link->lanes_per_sublink;
  872. config->common_config.num_data_lanes = num_of_lanes;
  873. config->common_config.bpp = bpp;
  874. if (config->bit_clk_rate_hz_override != 0) {
  875. bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
  876. if (host_cfg->phy_type == DSI_PHY_TYPE_CPHY) {
  877. bit_rate *= bits_per_symbol;
  878. do_div(bit_rate, num_of_symbols);
  879. }
  880. } else if (config->panel_mode == DSI_OP_CMD_MODE) {
  881. /* Calculate the bit rate needed to match dsi transfer time */
  882. bit_rate = min_dsi_clk_hz * frame_time_us;
  883. do_div(bit_rate, dsi_transfer_time_us);
  884. bit_rate = bit_rate * num_of_lanes;
  885. } else {
  886. h_period = dsi_h_total_dce(timing);
  887. v_period = DSI_V_TOTAL(timing);
  888. bit_rate = h_period * v_period * timing->refresh_rate * bpp;
  889. }
  890. pclk_rate = bit_rate;
  891. do_div(pclk_rate, bpp);
  892. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  893. bit_rate_per_lane = bit_rate;
  894. do_div(bit_rate_per_lane, num_of_lanes);
  895. byte_clk_rate = bit_rate_per_lane;
  896. /**
  897. * Ensure that the byte clock rate is even to avoid failures
  898. * during set rate for byte intf clock. Round up to the nearest
  899. * even number for byte clk.
  900. */
  901. byte_clk_rate = DIV_ROUND_CLOSEST(byte_clk_rate, 8);
  902. byte_clk_rate = ((byte_clk_rate + 1) & ~BIT(0));
  903. byte_intf_clk_rate = byte_clk_rate;
  904. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  905. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  906. config->bit_clk_rate_hz = byte_clk_rate * 8;
  907. } else {
  908. do_div(bit_rate, bits_per_symbol);
  909. bit_rate *= num_of_symbols;
  910. bit_rate_per_lane = bit_rate;
  911. do_div(bit_rate_per_lane, num_of_lanes);
  912. byte_clk_rate = bit_rate_per_lane;
  913. do_div(byte_clk_rate, 7);
  914. /* For CPHY, byte_intf_clk is same as byte_clk */
  915. byte_intf_clk_rate = byte_clk_rate;
  916. config->bit_clk_rate_hz = byte_clk_rate * 7;
  917. }
  918. DSI_CTRL_DEBUG(dsi_ctrl, "bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  919. bit_rate, bit_rate_per_lane);
  920. DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",
  921. byte_clk_rate, byte_intf_clk_rate);
  922. DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);
  923. SDE_EVT32(dsi_ctrl->cell_index, bit_rate, byte_clk_rate, pclk_rate);
  924. dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  925. dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  926. dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
  927. dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
  928. rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
  929. dsi_ctrl->cell_index);
  930. if (rc)
  931. DSI_CTRL_ERR(dsi_ctrl, "Failed to update link frequencies\n");
  932. return rc;
  933. }
  934. static int dsi_ctrl_enable_supplies(struct dsi_ctrl *dsi_ctrl, bool enable)
  935. {
  936. int rc = 0;
  937. if (enable) {
  938. rc = pm_runtime_get_sync(dsi_ctrl->drm_dev->dev);
  939. if (rc < 0) {
  940. DSI_CTRL_ERR(dsi_ctrl,
  941. "Power resource enable failed, rc=%d\n", rc);
  942. goto error;
  943. }
  944. if (!dsi_ctrl->current_state.host_initialized) {
  945. rc = dsi_pwr_enable_regulator(
  946. &dsi_ctrl->pwr_info.host_pwr, true);
  947. if (rc) {
  948. DSI_CTRL_ERR(dsi_ctrl, "failed to enable host power regs\n");
  949. goto error_get_sync;
  950. }
  951. }
  952. rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
  953. true);
  954. if (rc) {
  955. DSI_CTRL_ERR(dsi_ctrl, "failed to enable gdsc, rc=%d\n",
  956. rc);
  957. (void)dsi_pwr_enable_regulator(
  958. &dsi_ctrl->pwr_info.host_pwr,
  959. false
  960. );
  961. goto error_get_sync;
  962. }
  963. return rc;
  964. } else {
  965. rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
  966. false);
  967. if (rc) {
  968. DSI_CTRL_ERR(dsi_ctrl, "failed to disable gdsc, rc=%d\n",
  969. rc);
  970. goto error;
  971. }
  972. if (!dsi_ctrl->current_state.host_initialized) {
  973. rc = dsi_pwr_enable_regulator(
  974. &dsi_ctrl->pwr_info.host_pwr, false);
  975. if (rc) {
  976. DSI_CTRL_ERR(dsi_ctrl, "failed to disable host power regs\n");
  977. goto error;
  978. }
  979. }
  980. pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  981. return rc;
  982. }
  983. error_get_sync:
  984. pm_runtime_put_sync(dsi_ctrl->drm_dev->dev);
  985. error:
  986. return rc;
  987. }
  988. static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl,
  989. const struct mipi_dsi_packet *packet,
  990. u8 **buffer,
  991. u32 *size)
  992. {
  993. int rc = 0;
  994. u8 *buf = NULL;
  995. u32 len, i;
  996. u8 cmd_type = 0;
  997. len = packet->size;
  998. len += 0x3; len &= ~0x03; /* Align to 32 bits */
  999. buf = devm_kzalloc(&dsi_ctrl->pdev->dev, len * sizeof(u8), GFP_KERNEL);
  1000. if (!buf)
  1001. return -ENOMEM;
  1002. for (i = 0; i < len; i++) {
  1003. if (i >= packet->size)
  1004. buf[i] = 0xFF;
  1005. else if (i < sizeof(packet->header))
  1006. buf[i] = packet->header[i];
  1007. else
  1008. buf[i] = packet->payload[i - sizeof(packet->header)];
  1009. }
  1010. if (packet->payload_length > 0)
  1011. buf[3] |= BIT(6);
  1012. /* Swap BYTE order in the command buffer for MSM */
  1013. buf[0] = packet->header[1];
  1014. buf[1] = packet->header[2];
  1015. buf[2] = packet->header[0];
  1016. /* send embedded BTA for read commands */
  1017. cmd_type = buf[2] & 0x3f;
  1018. if ((cmd_type == MIPI_DSI_DCS_READ) ||
  1019. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) ||
  1020. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) ||
  1021. (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM))
  1022. buf[3] |= BIT(5);
  1023. *buffer = buf;
  1024. *size = len;
  1025. return rc;
  1026. }
  1027. int dsi_ctrl_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl *dsi_ctrl)
  1028. {
  1029. int rc = 0;
  1030. if (!dsi_ctrl) {
  1031. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  1032. return -EINVAL;
  1033. }
  1034. if (dsi_ctrl->host_config.panel_mode != DSI_OP_CMD_MODE)
  1035. return -EINVAL;
  1036. mutex_lock(&dsi_ctrl->ctrl_lock);
  1037. rc = dsi_ctrl->hw.ops.wait_for_cmd_mode_mdp_idle(&dsi_ctrl->hw);
  1038. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1039. return rc;
  1040. }
  1041. static void dsi_ctrl_wait_for_video_done(struct dsi_ctrl *dsi_ctrl)
  1042. {
  1043. u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0, ret;
  1044. struct dsi_mode_info *timing;
  1045. /**
  1046. * No need to wait if the panel is not video mode or
  1047. * if DSI controller supports command DMA scheduling or
  1048. * if we are sending init commands.
  1049. */
  1050. if ((dsi_ctrl->host_config.panel_mode != DSI_OP_VIDEO_MODE) ||
  1051. (dsi_ctrl->version >= DSI_CTRL_VERSION_2_2) ||
  1052. (dsi_ctrl->current_state.vid_engine_state !=
  1053. DSI_CTRL_ENGINE_ON))
  1054. return;
  1055. dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
  1056. DSI_VIDEO_MODE_FRAME_DONE);
  1057. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  1058. DSI_SINT_VIDEO_MODE_FRAME_DONE, NULL);
  1059. reinit_completion(&dsi_ctrl->irq_info.vid_frame_done);
  1060. ret = wait_for_completion_timeout(
  1061. &dsi_ctrl->irq_info.vid_frame_done,
  1062. msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
  1063. if (ret <= 0)
  1064. DSI_CTRL_DEBUG(dsi_ctrl, "wait for video done failed\n");
  1065. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  1066. DSI_SINT_VIDEO_MODE_FRAME_DONE);
  1067. timing = &(dsi_ctrl->host_config.video_timing);
  1068. v_total = timing->v_sync_width + timing->v_back_porch +
  1069. timing->v_front_porch + timing->v_active;
  1070. v_blank = timing->v_sync_width + timing->v_back_porch;
  1071. fps = timing->refresh_rate;
  1072. sleep_ms = CEIL((v_blank * 1000), (v_total * fps)) + 1;
  1073. udelay(sleep_ms * 1000);
  1074. }
  1075. int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl,
  1076. u32 cmd_len,
  1077. u32 *flags)
  1078. {
  1079. int rc = 0;
  1080. if (*flags & DSI_CTRL_CMD_FIFO_STORE) {
  1081. /* if command size plus header is greater than fifo size */
  1082. if ((cmd_len + 4) > DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE) {
  1083. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer Cmd in FIFO config\n");
  1084. return -ENOTSUPP;
  1085. }
  1086. if (!dsi_ctrl->hw.ops.kickoff_fifo_command) {
  1087. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer command,ops not defined\n");
  1088. return -ENOTSUPP;
  1089. }
  1090. }
  1091. if (*flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1092. if (*flags & DSI_CTRL_CMD_BROADCAST) {
  1093. DSI_CTRL_ERR(dsi_ctrl, "Non embedded not supported with broadcast\n");
  1094. return -ENOTSUPP;
  1095. }
  1096. if (!dsi_ctrl->hw.ops.kickoff_command_non_embedded_mode) {
  1097. DSI_CTRL_ERR(dsi_ctrl, " Cannot transfer command,ops not defined\n");
  1098. return -ENOTSUPP;
  1099. }
  1100. if ((cmd_len + 4) > SZ_4K) {
  1101. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer,size is greater than 4096\n");
  1102. return -ENOTSUPP;
  1103. }
  1104. }
  1105. if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1106. if ((dsi_ctrl->cmd_len + cmd_len + 4) > SZ_4K) {
  1107. DSI_CTRL_ERR(dsi_ctrl, "Cannot transfer,size is greater than 4096\n");
  1108. return -ENOTSUPP;
  1109. }
  1110. }
  1111. return rc;
  1112. }
  1113. static void dsi_configure_command_scheduling(struct dsi_ctrl *dsi_ctrl,
  1114. struct dsi_ctrl_cmd_dma_info *cmd_mem)
  1115. {
  1116. u32 line_no = 0, window = 0, sched_line_no = 0;
  1117. struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
  1118. struct dsi_mode_info *timing = &(dsi_ctrl->host_config.video_timing);
  1119. line_no = dsi_ctrl->host_config.common_config.dma_sched_line;
  1120. window = dsi_ctrl->host_config.common_config.dma_sched_window;
  1121. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, line_no, window);
  1122. /*
  1123. * In case of command scheduling in video mode, the line at which
  1124. * the command is scheduled can revert to the default value i.e. 1
  1125. * for the following cases:
  1126. * 1) No schedule line defined by the panel.
  1127. * 2) schedule line defined is greater than VFP.
  1128. */
  1129. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  1130. dsi_hw_ops.schedule_dma_cmd &&
  1131. (dsi_ctrl->current_state.vid_engine_state ==
  1132. DSI_CTRL_ENGINE_ON)) {
  1133. sched_line_no = (line_no == 0) ? 1 : line_no;
  1134. if (timing) {
  1135. if (sched_line_no >= timing->v_front_porch)
  1136. sched_line_no = 1;
  1137. sched_line_no += timing->v_back_porch +
  1138. timing->v_sync_width + timing->v_active;
  1139. }
  1140. dsi_hw_ops.schedule_dma_cmd(&dsi_ctrl->hw, sched_line_no);
  1141. }
  1142. /*
  1143. * In case of command scheduling in command mode, set the maximum
  1144. * possible size of the DMA start window in case no schedule line and
  1145. * window size properties are defined by the panel.
  1146. */
  1147. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) &&
  1148. dsi_hw_ops.configure_cmddma_window) {
  1149. sched_line_no = (line_no == 0) ? TEARCHECK_WINDOW_SIZE :
  1150. line_no;
  1151. window = (window == 0) ? timing->v_active : window;
  1152. sched_line_no += timing->v_active;
  1153. dsi_hw_ops.configure_cmddma_window(&dsi_ctrl->hw, cmd_mem,
  1154. sched_line_no, window);
  1155. }
  1156. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_EXIT,
  1157. sched_line_no, window);
  1158. }
  1159. static u32 calculate_schedule_line(struct dsi_ctrl *dsi_ctrl, u32 flags)
  1160. {
  1161. u32 line_no = 0x1;
  1162. struct dsi_mode_info *timing;
  1163. /* check if custom dma scheduling line needed */
  1164. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  1165. (flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED))
  1166. line_no = dsi_ctrl->host_config.common_config.dma_sched_line;
  1167. timing = &(dsi_ctrl->host_config.video_timing);
  1168. if (timing)
  1169. line_no += timing->v_back_porch + timing->v_sync_width +
  1170. timing->v_active;
  1171. return line_no;
  1172. }
  1173. static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
  1174. const struct mipi_dsi_msg *msg,
  1175. struct dsi_ctrl_cmd_dma_fifo_info *cmd,
  1176. struct dsi_ctrl_cmd_dma_info *cmd_mem,
  1177. u32 flags)
  1178. {
  1179. u32 hw_flags = 0;
  1180. struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
  1181. struct dsi_split_link_config *split_link;
  1182. split_link = &(dsi_ctrl->host_config.common_config.split_link);
  1183. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags,
  1184. msg->flags);
  1185. if (dsi_ctrl->hw.reset_trig_ctrl)
  1186. dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
  1187. &dsi_ctrl->host_config.common_config);
  1188. if (dsi_hw_ops.splitlink_cmd_setup && split_link->enabled)
  1189. dsi_hw_ops.splitlink_cmd_setup(&dsi_ctrl->hw,
  1190. &dsi_ctrl->host_config.common_config, flags);
  1191. /*
  1192. * Always enable DMA scheduling for video mode panel.
  1193. *
  1194. * In video mode panel, if the DMA is triggered very close to
  1195. * the beginning of the active window and the DMA transfer
  1196. * happens in the last line of VBP, then the HW state will
  1197. * stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
  1198. * But somewhere in the middle of the active window, if SW
  1199. * disables DSI command mode engine while the HW is still
  1200. * waiting and re-enable after timing engine is OFF. So the
  1201. * HW never ‘sees’ another vblank line and hence it gets
  1202. * stuck in the ‘wait’ state.
  1203. */
  1204. if ((flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED) ||
  1205. (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE))
  1206. dsi_configure_command_scheduling(dsi_ctrl, cmd_mem);
  1207. dsi_ctrl->cmd_mode = (dsi_ctrl->host_config.panel_mode ==
  1208. DSI_OP_CMD_MODE);
  1209. hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ?
  1210. DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0;
  1211. if (flags & DSI_CTRL_CMD_LAST_COMMAND)
  1212. hw_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  1213. if (flags & DSI_CTRL_CMD_DEFER_TRIGGER) {
  1214. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1215. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1216. dsi_hw_ops.kickoff_command_non_embedded_mode(
  1217. &dsi_ctrl->hw,
  1218. cmd_mem,
  1219. hw_flags);
  1220. } else {
  1221. dsi_hw_ops.kickoff_command(
  1222. &dsi_ctrl->hw,
  1223. cmd_mem,
  1224. hw_flags);
  1225. }
  1226. } else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
  1227. dsi_hw_ops.kickoff_fifo_command(&dsi_ctrl->hw,
  1228. cmd,
  1229. hw_flags);
  1230. }
  1231. }
  1232. if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
  1233. dsi_ctrl_wait_for_video_done(dsi_ctrl);
  1234. dsi_ctrl_mask_overflow(dsi_ctrl, true);
  1235. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1236. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  1237. DSI_SINT_CMD_MODE_DMA_DONE, NULL);
  1238. reinit_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  1239. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1240. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1241. dsi_hw_ops.kickoff_command_non_embedded_mode(
  1242. &dsi_ctrl->hw,
  1243. cmd_mem,
  1244. hw_flags);
  1245. } else {
  1246. dsi_hw_ops.kickoff_command(
  1247. &dsi_ctrl->hw,
  1248. cmd_mem,
  1249. hw_flags);
  1250. }
  1251. } else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
  1252. dsi_hw_ops.kickoff_fifo_command(&dsi_ctrl->hw,
  1253. cmd,
  1254. hw_flags);
  1255. }
  1256. if (dsi_ctrl->enable_cmd_dma_stats) {
  1257. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  1258. dsi_ctrl->cmd_mode);
  1259. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  1260. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  1261. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  1262. dsi_ctrl->cmd_trigger_line,
  1263. dsi_ctrl->cmd_trigger_frame);
  1264. }
  1265. if (flags & DSI_CTRL_CMD_ASYNC_WAIT) {
  1266. dsi_ctrl->dma_wait_queued = true;
  1267. queue_work(dsi_ctrl->dma_cmd_workq,
  1268. &dsi_ctrl->dma_cmd_wait);
  1269. } else {
  1270. dsi_ctrl->dma_wait_queued = false;
  1271. dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait);
  1272. }
  1273. dsi_ctrl_mask_overflow(dsi_ctrl, false);
  1274. dsi_hw_ops.reset_cmd_fifo(&dsi_ctrl->hw);
  1275. /*
  1276. * DSI 2.2 needs a soft reset whenever we send non-embedded
  1277. * mode command followed by embedded mode. Otherwise it will
  1278. * result in smmu write faults with DSI as client.
  1279. */
  1280. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1281. if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4)
  1282. dsi_hw_ops.soft_reset(&dsi_ctrl->hw);
  1283. dsi_ctrl->cmd_len = 0;
  1284. }
  1285. }
  1286. }
  1287. static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd_desc)
  1288. {
  1289. int rc = 0;
  1290. struct mipi_dsi_packet packet;
  1291. struct dsi_ctrl_cmd_dma_fifo_info cmd;
  1292. struct dsi_ctrl_cmd_dma_info cmd_mem;
  1293. const struct mipi_dsi_msg *msg;
  1294. u32 length = 0;
  1295. u8 *buffer = NULL;
  1296. u32 cnt = 0;
  1297. u8 *cmdbuf;
  1298. u32 *flags;
  1299. msg = &cmd_desc->msg;
  1300. flags = &cmd_desc->ctrl_flags;
  1301. /* Validate the mode before sending the command */
  1302. rc = dsi_message_validate_tx_mode(dsi_ctrl, msg->tx_len, flags);
  1303. if (rc) {
  1304. DSI_CTRL_ERR(dsi_ctrl,
  1305. "Cmd tx validation failed, cannot transfer cmd\n");
  1306. rc = -ENOTSUPP;
  1307. goto error;
  1308. }
  1309. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags);
  1310. if (dsi_ctrl->dma_wait_queued)
  1311. dsi_ctrl_flush_cmd_dma_queue(dsi_ctrl);
  1312. if (*flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  1313. cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
  1314. cmd_mem.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1315. true : false;
  1316. cmd_mem.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1317. true : false;
  1318. cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1319. true : false;
  1320. cmd_mem.datatype = msg->type;
  1321. cmd_mem.length = msg->tx_len;
  1322. dsi_ctrl->cmd_len = msg->tx_len;
  1323. memcpy(dsi_ctrl->vaddr, msg->tx_buf, msg->tx_len);
  1324. DSI_CTRL_DEBUG(dsi_ctrl,
  1325. "non-embedded mode , size of command =%zd\n",
  1326. msg->tx_len);
  1327. goto kickoff;
  1328. }
  1329. rc = mipi_dsi_create_packet(&packet, msg);
  1330. if (rc) {
  1331. DSI_CTRL_ERR(dsi_ctrl, "Failed to create message packet, rc=%d\n",
  1332. rc);
  1333. goto error;
  1334. }
  1335. rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl,
  1336. &packet,
  1337. &buffer,
  1338. &length);
  1339. if (rc) {
  1340. DSI_CTRL_ERR(dsi_ctrl, "failed to copy message, rc=%d\n", rc);
  1341. goto error;
  1342. }
  1343. /*
  1344. * In case of broadcast CMD length cannot be greater than 512 bytes
  1345. * as specified by HW limitations. Need to overwrite the flags to
  1346. * set the LAST_COMMAND flag to ensure no command transfer failures.
  1347. */
  1348. if ((*flags & DSI_CTRL_CMD_FETCH_MEMORY) &&
  1349. (*flags & DSI_CTRL_CMD_BROADCAST)) {
  1350. if ((dsi_ctrl->cmd_len + length) > 240) {
  1351. dsi_ctrl_mask_overflow(dsi_ctrl, true);
  1352. *flags |= DSI_CTRL_CMD_LAST_COMMAND;
  1353. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  1354. flags);
  1355. }
  1356. }
  1357. if (*flags & DSI_CTRL_CMD_LAST_COMMAND)
  1358. buffer[3] |= BIT(7);//set the last cmd bit in header.
  1359. if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) {
  1360. /* Embedded mode config is selected */
  1361. cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
  1362. cmd_mem.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1363. true : false;
  1364. cmd_mem.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1365. true : false;
  1366. cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1367. true : false;
  1368. cmdbuf = (u8 *)(dsi_ctrl->vaddr);
  1369. msm_gem_sync(dsi_ctrl->tx_cmd_buf);
  1370. for (cnt = 0; cnt < length; cnt++)
  1371. cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt];
  1372. dsi_ctrl->cmd_len += length;
  1373. if (*flags & DSI_CTRL_CMD_LAST_COMMAND) {
  1374. cmd_mem.length = dsi_ctrl->cmd_len;
  1375. dsi_ctrl->cmd_len = 0;
  1376. } else {
  1377. goto error;
  1378. }
  1379. } else if (*flags & DSI_CTRL_CMD_FIFO_STORE) {
  1380. cmd.command = (u32 *)buffer;
  1381. cmd.size = length;
  1382. cmd.en_broadcast = (*flags & DSI_CTRL_CMD_BROADCAST) ?
  1383. true : false;
  1384. cmd.is_master = (*flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
  1385. true : false;
  1386. cmd.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
  1387. true : false;
  1388. }
  1389. kickoff:
  1390. dsi_kickoff_msg_tx(dsi_ctrl, msg, &cmd, &cmd_mem, *flags);
  1391. error:
  1392. if (buffer)
  1393. devm_kfree(&dsi_ctrl->pdev->dev, buffer);
  1394. return rc;
  1395. }
  1396. static int dsi_set_max_return_size(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *rx_cmd, u32 size)
  1397. {
  1398. int rc = 0;
  1399. const struct mipi_dsi_msg *rx_msg = &rx_cmd->msg;
  1400. u8 tx[2] = { (u8)(size & 0xFF), (u8)(size >> 8) };
  1401. u16 dflags = rx_msg->flags;
  1402. struct dsi_cmd_desc cmd= {
  1403. .msg.channel = rx_msg->channel,
  1404. .msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
  1405. .msg.tx_len = 2,
  1406. .msg.tx_buf = tx,
  1407. .msg.flags = rx_msg->flags,
  1408. };
  1409. /* remove last message flag to batch max packet cmd to read command */
  1410. dflags &= ~BIT(3);
  1411. cmd.msg.flags = dflags;
  1412. cmd.ctrl_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  1413. rc = dsi_message_tx(dsi_ctrl, &cmd);
  1414. if (rc)
  1415. DSI_CTRL_ERR(dsi_ctrl, "failed to send max return size packet, rc=%d\n",
  1416. rc);
  1417. return rc;
  1418. }
  1419. /* Helper functions to support DCS read operation */
  1420. static int dsi_parse_short_read1_resp(const struct mipi_dsi_msg *msg,
  1421. unsigned char *buff)
  1422. {
  1423. u8 *data = msg->rx_buf;
  1424. int read_len = 1;
  1425. if (!data)
  1426. return 0;
  1427. /* remove dcs type */
  1428. if (msg->rx_len >= 1)
  1429. data[0] = buff[1];
  1430. else
  1431. read_len = 0;
  1432. return read_len;
  1433. }
  1434. static int dsi_parse_short_read2_resp(const struct mipi_dsi_msg *msg,
  1435. unsigned char *buff)
  1436. {
  1437. u8 *data = msg->rx_buf;
  1438. int read_len = 2;
  1439. if (!data)
  1440. return 0;
  1441. /* remove dcs type */
  1442. if (msg->rx_len >= 2) {
  1443. data[0] = buff[1];
  1444. data[1] = buff[2];
  1445. } else {
  1446. read_len = 0;
  1447. }
  1448. return read_len;
  1449. }
  1450. static int dsi_parse_long_read_resp(const struct mipi_dsi_msg *msg,
  1451. unsigned char *buff)
  1452. {
  1453. if (!msg->rx_buf)
  1454. return 0;
  1455. /* remove dcs type */
  1456. if (msg->rx_buf && msg->rx_len)
  1457. memcpy(msg->rx_buf, buff + 4, msg->rx_len);
  1458. return msg->rx_len;
  1459. }
  1460. static int dsi_message_rx(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd_desc)
  1461. {
  1462. int rc = 0;
  1463. u32 rd_pkt_size, total_read_len, hw_read_cnt;
  1464. u32 current_read_len = 0, total_bytes_read = 0;
  1465. bool short_resp = false;
  1466. bool read_done = false;
  1467. u32 dlen, diff, rlen;
  1468. unsigned char *buff;
  1469. char cmd;
  1470. const struct mipi_dsi_msg *msg;
  1471. if (!cmd_desc) {
  1472. DSI_CTRL_ERR(dsi_ctrl, "Invalid command\n");
  1473. rc = -EINVAL;
  1474. goto error;
  1475. }
  1476. msg = &cmd_desc->msg;
  1477. rlen = msg->rx_len;
  1478. if (msg->rx_len <= 2) {
  1479. short_resp = true;
  1480. rd_pkt_size = msg->rx_len;
  1481. total_read_len = 4;
  1482. } else {
  1483. short_resp = false;
  1484. current_read_len = 10;
  1485. if (msg->rx_len < current_read_len)
  1486. rd_pkt_size = msg->rx_len;
  1487. else
  1488. rd_pkt_size = current_read_len;
  1489. total_read_len = current_read_len + 6;
  1490. }
  1491. buff = msg->rx_buf;
  1492. while (!read_done) {
  1493. rc = dsi_set_max_return_size(dsi_ctrl, cmd_desc, rd_pkt_size);
  1494. if (rc) {
  1495. DSI_CTRL_ERR(dsi_ctrl, "Failed to set max return packet size, rc=%d\n",
  1496. rc);
  1497. goto error;
  1498. }
  1499. /* clear RDBK_DATA registers before proceeding */
  1500. dsi_ctrl->hw.ops.clear_rdbk_register(&dsi_ctrl->hw);
  1501. rc = dsi_message_tx(dsi_ctrl, cmd_desc);
  1502. if (rc) {
  1503. DSI_CTRL_ERR(dsi_ctrl, "Message transmission failed, rc=%d\n",
  1504. rc);
  1505. goto error;
  1506. }
  1507. /*
  1508. * wait before reading rdbk_data register, if any delay is
  1509. * required after sending the read command.
  1510. */
  1511. if (cmd_desc->post_wait_ms)
  1512. usleep_range(cmd_desc->post_wait_ms * 1000,
  1513. ((cmd_desc->post_wait_ms * 1000) + 10));
  1514. dlen = dsi_ctrl->hw.ops.get_cmd_read_data(&dsi_ctrl->hw,
  1515. buff, total_bytes_read,
  1516. total_read_len, rd_pkt_size,
  1517. &hw_read_cnt);
  1518. if (!dlen)
  1519. goto error;
  1520. if (short_resp)
  1521. break;
  1522. if (rlen <= current_read_len) {
  1523. diff = current_read_len - rlen;
  1524. read_done = true;
  1525. } else {
  1526. diff = 0;
  1527. rlen -= current_read_len;
  1528. }
  1529. dlen -= 2; /* 2 bytes of CRC */
  1530. dlen -= diff;
  1531. buff += dlen;
  1532. total_bytes_read += dlen;
  1533. if (!read_done) {
  1534. current_read_len = 14; /* Not first read */
  1535. if (rlen < current_read_len)
  1536. rd_pkt_size += rlen;
  1537. else
  1538. rd_pkt_size += current_read_len;
  1539. }
  1540. }
  1541. if (hw_read_cnt < 16 && !short_resp)
  1542. buff = msg->rx_buf + (16 - hw_read_cnt);
  1543. else
  1544. buff = msg->rx_buf;
  1545. /* parse the data read from panel */
  1546. cmd = buff[0];
  1547. switch (cmd) {
  1548. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  1549. DSI_CTRL_ERR(dsi_ctrl, "Rx ACK_ERROR 0x%x\n", cmd);
  1550. rc = 0;
  1551. break;
  1552. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  1553. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  1554. rc = dsi_parse_short_read1_resp(msg, buff);
  1555. break;
  1556. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  1557. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  1558. rc = dsi_parse_short_read2_resp(msg, buff);
  1559. break;
  1560. case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
  1561. case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
  1562. rc = dsi_parse_long_read_resp(msg, buff);
  1563. break;
  1564. default:
  1565. DSI_CTRL_WARN(dsi_ctrl, "Invalid response: 0x%x\n", cmd);
  1566. rc = 0;
  1567. }
  1568. error:
  1569. return rc;
  1570. }
  1571. static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl)
  1572. {
  1573. int rc = 0;
  1574. u32 lanes = 0;
  1575. u32 ulps_lanes;
  1576. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1577. rc = dsi_ctrl->hw.ops.wait_for_lane_idle(&dsi_ctrl->hw, lanes);
  1578. if (rc) {
  1579. DSI_CTRL_ERR(dsi_ctrl, "lanes not entering idle, skip ULPS\n");
  1580. return rc;
  1581. }
  1582. if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||
  1583. !dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {
  1584. DSI_CTRL_DEBUG(dsi_ctrl, "DSI controller ULPS ops not present\n");
  1585. return 0;
  1586. }
  1587. lanes |= DSI_CLOCK_LANE;
  1588. dsi_ctrl->hw.ops.ulps_ops.ulps_request(&dsi_ctrl->hw, lanes);
  1589. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1590. if ((lanes & ulps_lanes) != lanes) {
  1591. DSI_CTRL_ERR(dsi_ctrl, "Failed to enter ULPS, request=0x%x, actual=0x%x\n",
  1592. lanes, ulps_lanes);
  1593. rc = -EIO;
  1594. }
  1595. return rc;
  1596. }
  1597. static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl)
  1598. {
  1599. int rc = 0;
  1600. u32 ulps_lanes, lanes = 0;
  1601. dsi_ctrl->hw.ops.clear_phy0_ln_err(&dsi_ctrl->hw);
  1602. if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||
  1603. !dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {
  1604. DSI_CTRL_DEBUG(dsi_ctrl, "DSI controller ULPS ops not present\n");
  1605. return 0;
  1606. }
  1607. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1608. lanes |= DSI_CLOCK_LANE;
  1609. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1610. if ((lanes & ulps_lanes) != lanes)
  1611. DSI_CTRL_ERR(dsi_ctrl, "Mismatch between lanes in ULPS\n");
  1612. lanes &= ulps_lanes;
  1613. dsi_ctrl->hw.ops.ulps_ops.ulps_exit(&dsi_ctrl->hw, lanes);
  1614. ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);
  1615. if (ulps_lanes & lanes) {
  1616. DSI_CTRL_ERR(dsi_ctrl, "Lanes (0x%x) stuck in ULPS\n",
  1617. ulps_lanes);
  1618. rc = -EIO;
  1619. }
  1620. return rc;
  1621. }
  1622. static void dsi_ctrl_enable_error_interrupts(struct dsi_ctrl *dsi_ctrl)
  1623. {
  1624. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
  1625. !dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
  1626. !dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
  1627. dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
  1628. 0xFF00A0);
  1629. else
  1630. dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
  1631. 0xFF00E0);
  1632. }
  1633. static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
  1634. {
  1635. int rc = 0;
  1636. bool splash_enabled = false;
  1637. struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
  1638. if (!splash_enabled) {
  1639. state->power_state = DSI_CTRL_POWER_VREG_OFF;
  1640. state->cmd_engine_state = DSI_CTRL_ENGINE_OFF;
  1641. state->vid_engine_state = DSI_CTRL_ENGINE_OFF;
  1642. }
  1643. return rc;
  1644. }
  1645. static int dsi_ctrl_buffer_deinit(struct dsi_ctrl *dsi_ctrl)
  1646. {
  1647. struct msm_gem_address_space *aspace = NULL;
  1648. if (dsi_ctrl->tx_cmd_buf) {
  1649. aspace = dsi_ctrl_get_aspace(dsi_ctrl,
  1650. MSM_SMMU_DOMAIN_UNSECURE);
  1651. if (!aspace) {
  1652. DSI_CTRL_ERR(dsi_ctrl, "failed to get address space\n");
  1653. return -ENOMEM;
  1654. }
  1655. msm_gem_put_iova(dsi_ctrl->tx_cmd_buf, aspace);
  1656. mutex_lock(&dsi_ctrl->drm_dev->struct_mutex);
  1657. msm_gem_free_object(dsi_ctrl->tx_cmd_buf);
  1658. mutex_unlock(&dsi_ctrl->drm_dev->struct_mutex);
  1659. dsi_ctrl->tx_cmd_buf = NULL;
  1660. }
  1661. return 0;
  1662. }
  1663. int dsi_ctrl_buffer_init(struct dsi_ctrl *dsi_ctrl)
  1664. {
  1665. int rc = 0;
  1666. u64 iova = 0;
  1667. struct msm_gem_address_space *aspace = NULL;
  1668. aspace = dsi_ctrl_get_aspace(dsi_ctrl, MSM_SMMU_DOMAIN_UNSECURE);
  1669. if (!aspace) {
  1670. DSI_CTRL_ERR(dsi_ctrl, "failed to get address space\n");
  1671. return -ENOMEM;
  1672. }
  1673. dsi_ctrl->tx_cmd_buf = msm_gem_new(dsi_ctrl->drm_dev,
  1674. SZ_4K,
  1675. MSM_BO_UNCACHED);
  1676. if (IS_ERR(dsi_ctrl->tx_cmd_buf)) {
  1677. rc = PTR_ERR(dsi_ctrl->tx_cmd_buf);
  1678. DSI_CTRL_ERR(dsi_ctrl, "failed to allocate gem, rc=%d\n", rc);
  1679. dsi_ctrl->tx_cmd_buf = NULL;
  1680. goto error;
  1681. }
  1682. dsi_ctrl->cmd_buffer_size = SZ_4K;
  1683. rc = msm_gem_get_iova(dsi_ctrl->tx_cmd_buf, aspace, &iova);
  1684. if (rc) {
  1685. DSI_CTRL_ERR(dsi_ctrl, "failed to get iova, rc=%d\n", rc);
  1686. (void)dsi_ctrl_buffer_deinit(dsi_ctrl);
  1687. goto error;
  1688. }
  1689. if (iova & 0x07) {
  1690. DSI_CTRL_ERR(dsi_ctrl, "Tx command buffer is not 8 byte aligned\n");
  1691. rc = -ENOTSUPP;
  1692. (void)dsi_ctrl_buffer_deinit(dsi_ctrl);
  1693. goto error;
  1694. }
  1695. error:
  1696. return rc;
  1697. }
  1698. static int dsi_enable_io_clamp(struct dsi_ctrl *dsi_ctrl,
  1699. bool enable, bool ulps_enabled)
  1700. {
  1701. u32 lanes = 0;
  1702. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
  1703. lanes = dsi_ctrl->host_config.common_config.data_lanes;
  1704. lanes |= DSI_CLOCK_LANE;
  1705. if (enable)
  1706. dsi_ctrl->hw.ops.clamp_enable(&dsi_ctrl->hw,
  1707. lanes, ulps_enabled);
  1708. else
  1709. dsi_ctrl->hw.ops.clamp_disable(&dsi_ctrl->hw,
  1710. lanes, ulps_enabled);
  1711. return 0;
  1712. }
  1713. static int dsi_ctrl_dts_parse(struct dsi_ctrl *dsi_ctrl,
  1714. struct device_node *of_node)
  1715. {
  1716. u32 index = 0, frame_threshold_time_us = 0;
  1717. int rc = 0;
  1718. if (!dsi_ctrl || !of_node) {
  1719. DSI_CTRL_ERR(dsi_ctrl, "invalid dsi_ctrl:%d or of_node:%d\n",
  1720. dsi_ctrl != NULL, of_node != NULL);
  1721. return -EINVAL;
  1722. }
  1723. rc = of_property_read_u32(of_node, "cell-index", &index);
  1724. if (rc) {
  1725. DSI_CTRL_DEBUG(dsi_ctrl, "cell index not set, default to 0\n");
  1726. index = 0;
  1727. }
  1728. dsi_ctrl->cell_index = index;
  1729. dsi_ctrl->name = of_get_property(of_node, "label", NULL);
  1730. if (!dsi_ctrl->name)
  1731. dsi_ctrl->name = DSI_CTRL_DEFAULT_LABEL;
  1732. dsi_ctrl->phy_isolation_enabled = of_property_read_bool(of_node,
  1733. "qcom,dsi-phy-isolation-enabled");
  1734. dsi_ctrl->null_insertion_enabled = of_property_read_bool(of_node,
  1735. "qcom,null-insertion-enabled");
  1736. dsi_ctrl->split_link_supported = of_property_read_bool(of_node,
  1737. "qcom,split-link-supported");
  1738. rc = of_property_read_u32(of_node, "frame-threshold-time-us",
  1739. &frame_threshold_time_us);
  1740. if (rc) {
  1741. DSI_CTRL_DEBUG(dsi_ctrl,
  1742. "frame-threshold-time not specified, defaulting\n");
  1743. frame_threshold_time_us = 2666;
  1744. }
  1745. dsi_ctrl->frame_threshold_time_us = frame_threshold_time_us;
  1746. return 0;
  1747. }
  1748. static int dsi_ctrl_dev_probe(struct platform_device *pdev)
  1749. {
  1750. struct dsi_ctrl *dsi_ctrl;
  1751. struct dsi_ctrl_list_item *item;
  1752. const struct of_device_id *id;
  1753. enum dsi_ctrl_version version;
  1754. int rc = 0;
  1755. id = of_match_node(msm_dsi_of_match, pdev->dev.of_node);
  1756. if (!id)
  1757. return -ENODEV;
  1758. version = *(enum dsi_ctrl_version *)id->data;
  1759. item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
  1760. if (!item)
  1761. return -ENOMEM;
  1762. dsi_ctrl = devm_kzalloc(&pdev->dev, sizeof(*dsi_ctrl), GFP_KERNEL);
  1763. if (!dsi_ctrl)
  1764. return -ENOMEM;
  1765. dsi_ctrl->version = version;
  1766. dsi_ctrl->irq_info.irq_num = -1;
  1767. dsi_ctrl->irq_info.irq_stat_mask = 0x0;
  1768. INIT_WORK(&dsi_ctrl->dma_cmd_wait, dsi_ctrl_dma_cmd_wait_for_done);
  1769. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1770. spin_lock_init(&dsi_ctrl->irq_info.irq_lock);
  1771. rc = dsi_ctrl_dts_parse(dsi_ctrl, pdev->dev.of_node);
  1772. if (rc) {
  1773. DSI_CTRL_ERR(dsi_ctrl, "dts parse failed, rc = %d\n", rc);
  1774. goto fail;
  1775. }
  1776. rc = dsi_ctrl_init_regmap(pdev, dsi_ctrl);
  1777. if (rc) {
  1778. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse register information, rc = %d\n",
  1779. rc);
  1780. goto fail;
  1781. }
  1782. rc = dsi_ctrl_supplies_init(pdev, dsi_ctrl);
  1783. if (rc) {
  1784. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse voltage supplies, rc = %d\n",
  1785. rc);
  1786. goto fail;
  1787. }
  1788. rc = dsi_ctrl_clocks_init(pdev, dsi_ctrl);
  1789. if (rc) {
  1790. DSI_CTRL_ERR(dsi_ctrl, "Failed to parse clock information, rc = %d\n",
  1791. rc);
  1792. goto fail_supplies;
  1793. }
  1794. rc = dsi_catalog_ctrl_setup(&dsi_ctrl->hw, dsi_ctrl->version,
  1795. dsi_ctrl->cell_index, dsi_ctrl->phy_isolation_enabled,
  1796. dsi_ctrl->null_insertion_enabled);
  1797. if (rc) {
  1798. DSI_CTRL_ERR(dsi_ctrl, "Catalog does not support version (%d)\n",
  1799. dsi_ctrl->version);
  1800. goto fail_clks;
  1801. }
  1802. item->ctrl = dsi_ctrl;
  1803. sde_dbg_dsi_ctrl_register(dsi_ctrl->hw.base, dsi_ctrl->name);
  1804. mutex_lock(&dsi_ctrl_list_lock);
  1805. list_add(&item->list, &dsi_ctrl_list);
  1806. mutex_unlock(&dsi_ctrl_list_lock);
  1807. mutex_init(&dsi_ctrl->ctrl_lock);
  1808. dsi_ctrl->secure_mode = false;
  1809. dsi_ctrl->pdev = pdev;
  1810. platform_set_drvdata(pdev, dsi_ctrl);
  1811. DSI_CTRL_INFO(dsi_ctrl, "Probe successful\n");
  1812. return 0;
  1813. fail_clks:
  1814. (void)dsi_ctrl_clocks_deinit(dsi_ctrl);
  1815. fail_supplies:
  1816. (void)dsi_ctrl_supplies_deinit(dsi_ctrl);
  1817. fail:
  1818. return rc;
  1819. }
  1820. static int dsi_ctrl_dev_remove(struct platform_device *pdev)
  1821. {
  1822. int rc = 0;
  1823. struct dsi_ctrl *dsi_ctrl;
  1824. struct list_head *pos, *tmp;
  1825. dsi_ctrl = platform_get_drvdata(pdev);
  1826. mutex_lock(&dsi_ctrl_list_lock);
  1827. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1828. struct dsi_ctrl_list_item *n = list_entry(pos,
  1829. struct dsi_ctrl_list_item,
  1830. list);
  1831. if (n->ctrl == dsi_ctrl) {
  1832. list_del(&n->list);
  1833. break;
  1834. }
  1835. }
  1836. mutex_unlock(&dsi_ctrl_list_lock);
  1837. mutex_lock(&dsi_ctrl->ctrl_lock);
  1838. dsi_ctrl_isr_configure(dsi_ctrl, false);
  1839. rc = dsi_ctrl_supplies_deinit(dsi_ctrl);
  1840. if (rc)
  1841. DSI_CTRL_ERR(dsi_ctrl,
  1842. "failed to deinitialize voltage supplies, rc=%d\n",
  1843. rc);
  1844. rc = dsi_ctrl_clocks_deinit(dsi_ctrl);
  1845. if (rc)
  1846. DSI_CTRL_ERR(dsi_ctrl,
  1847. "failed to deinitialize clocks, rc=%d\n", rc);
  1848. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  1849. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1850. mutex_destroy(&dsi_ctrl->ctrl_lock);
  1851. devm_kfree(&pdev->dev, dsi_ctrl);
  1852. platform_set_drvdata(pdev, NULL);
  1853. return 0;
  1854. }
  1855. static struct platform_driver dsi_ctrl_driver = {
  1856. .probe = dsi_ctrl_dev_probe,
  1857. .remove = dsi_ctrl_dev_remove,
  1858. .driver = {
  1859. .name = "drm_dsi_ctrl",
  1860. .of_match_table = msm_dsi_of_match,
  1861. .suppress_bind_attrs = true,
  1862. },
  1863. };
  1864. int dsi_ctrl_get_io_resources(struct msm_io_res *io_res)
  1865. {
  1866. int rc = 0;
  1867. struct dsi_ctrl_list_item *dsi_ctrl;
  1868. mutex_lock(&dsi_ctrl_list_lock);
  1869. list_for_each_entry(dsi_ctrl, &dsi_ctrl_list, list) {
  1870. rc = msm_dss_get_io_mem(dsi_ctrl->ctrl->pdev, &io_res->mem);
  1871. if (rc) {
  1872. DSI_CTRL_ERR(dsi_ctrl->ctrl,
  1873. "failed to get io mem, rc = %d\n", rc);
  1874. return rc;
  1875. }
  1876. }
  1877. mutex_unlock(&dsi_ctrl_list_lock);
  1878. return rc;
  1879. }
  1880. /**
  1881. * dsi_ctrl_check_resource() - check if DSI controller is probed
  1882. * @of_node: of_node of the DSI controller.
  1883. *
  1884. * Checks if the DSI controller has been probed and is available.
  1885. *
  1886. * Return: status of DSI controller
  1887. */
  1888. bool dsi_ctrl_check_resource(struct device_node *of_node)
  1889. {
  1890. struct list_head *pos, *tmp;
  1891. struct dsi_ctrl *ctrl = NULL;
  1892. mutex_lock(&dsi_ctrl_list_lock);
  1893. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1894. struct dsi_ctrl_list_item *n;
  1895. n = list_entry(pos, struct dsi_ctrl_list_item, list);
  1896. if (!n->ctrl || !n->ctrl->pdev)
  1897. break;
  1898. if (n->ctrl->pdev->dev.of_node == of_node) {
  1899. ctrl = n->ctrl;
  1900. break;
  1901. }
  1902. }
  1903. mutex_unlock(&dsi_ctrl_list_lock);
  1904. return ctrl ? true : false;
  1905. }
  1906. /**
  1907. * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
  1908. * @of_node: of_node of the DSI controller.
  1909. *
  1910. * Gets the DSI controller handle for the corresponding of_node. The ref count
  1911. * is incremented to one and all subsequent gets will fail until the original
  1912. * clients calls a put.
  1913. *
  1914. * Return: DSI Controller handle.
  1915. */
  1916. struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node)
  1917. {
  1918. struct list_head *pos, *tmp;
  1919. struct dsi_ctrl *ctrl = NULL;
  1920. mutex_lock(&dsi_ctrl_list_lock);
  1921. list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
  1922. struct dsi_ctrl_list_item *n;
  1923. n = list_entry(pos, struct dsi_ctrl_list_item, list);
  1924. if (n->ctrl->pdev->dev.of_node == of_node) {
  1925. ctrl = n->ctrl;
  1926. break;
  1927. }
  1928. }
  1929. mutex_unlock(&dsi_ctrl_list_lock);
  1930. if (!ctrl) {
  1931. DSI_CTRL_ERR(ctrl, "Device with of node not found rc=%d\n",
  1932. -EPROBE_DEFER);
  1933. ctrl = ERR_PTR(-EPROBE_DEFER);
  1934. return ctrl;
  1935. }
  1936. mutex_lock(&ctrl->ctrl_lock);
  1937. if (ctrl->refcount == 1) {
  1938. DSI_CTRL_ERR(ctrl, "Device in use\n");
  1939. mutex_unlock(&ctrl->ctrl_lock);
  1940. ctrl = ERR_PTR(-EBUSY);
  1941. return ctrl;
  1942. }
  1943. ctrl->refcount++;
  1944. mutex_unlock(&ctrl->ctrl_lock);
  1945. return ctrl;
  1946. }
  1947. /**
  1948. * dsi_ctrl_put() - releases a dsi controller handle.
  1949. * @dsi_ctrl: DSI controller handle.
  1950. *
  1951. * Releases the DSI controller. Driver will clean up all resources and puts back
  1952. * the DSI controller into reset state.
  1953. */
  1954. void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl)
  1955. {
  1956. mutex_lock(&dsi_ctrl->ctrl_lock);
  1957. if (dsi_ctrl->refcount == 0)
  1958. DSI_CTRL_ERR(dsi_ctrl, "Unbalanced %s call\n", __func__);
  1959. else
  1960. dsi_ctrl->refcount--;
  1961. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1962. }
  1963. /**
  1964. * dsi_ctrl_drv_init() - initialize dsi controller driver.
  1965. * @dsi_ctrl: DSI controller handle.
  1966. * @parent: Parent directory for debug fs.
  1967. *
  1968. * Initializes DSI controller driver. Driver should be initialized after
  1969. * dsi_ctrl_get() succeeds.
  1970. *
  1971. * Return: error code.
  1972. */
  1973. int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent)
  1974. {
  1975. int rc = 0;
  1976. if (!dsi_ctrl) {
  1977. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  1978. return -EINVAL;
  1979. }
  1980. mutex_lock(&dsi_ctrl->ctrl_lock);
  1981. rc = dsi_ctrl_drv_state_init(dsi_ctrl);
  1982. if (rc) {
  1983. DSI_CTRL_ERR(dsi_ctrl, "Failed to initialize driver state, rc=%d\n",
  1984. rc);
  1985. goto error;
  1986. }
  1987. rc = dsi_ctrl_debugfs_init(dsi_ctrl, parent);
  1988. if (rc) {
  1989. DSI_CTRL_ERR(dsi_ctrl, "failed to init debug fs, rc=%d\n", rc);
  1990. goto error;
  1991. }
  1992. error:
  1993. mutex_unlock(&dsi_ctrl->ctrl_lock);
  1994. return rc;
  1995. }
  1996. /**
  1997. * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
  1998. * @dsi_ctrl: DSI controller handle.
  1999. *
  2000. * Releases all resources acquired by dsi_ctrl_drv_init().
  2001. *
  2002. * Return: error code.
  2003. */
  2004. int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl)
  2005. {
  2006. int rc = 0;
  2007. if (!dsi_ctrl) {
  2008. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2009. return -EINVAL;
  2010. }
  2011. mutex_lock(&dsi_ctrl->ctrl_lock);
  2012. rc = dsi_ctrl_debugfs_deinit(dsi_ctrl);
  2013. if (rc)
  2014. DSI_CTRL_ERR(dsi_ctrl, "failed to release debugfs root, rc=%d\n",
  2015. rc);
  2016. rc = dsi_ctrl_buffer_deinit(dsi_ctrl);
  2017. if (rc)
  2018. DSI_CTRL_ERR(dsi_ctrl, "Failed to free cmd buffers, rc=%d\n",
  2019. rc);
  2020. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2021. return rc;
  2022. }
  2023. int dsi_ctrl_clk_cb_register(struct dsi_ctrl *dsi_ctrl,
  2024. struct clk_ctrl_cb *clk_cb)
  2025. {
  2026. if (!dsi_ctrl || !clk_cb) {
  2027. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2028. return -EINVAL;
  2029. }
  2030. dsi_ctrl->clk_cb.priv = clk_cb->priv;
  2031. dsi_ctrl->clk_cb.dsi_clk_cb = clk_cb->dsi_clk_cb;
  2032. return 0;
  2033. }
  2034. /**
  2035. * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
  2036. * @dsi_ctrl: DSI controller handle.
  2037. *
  2038. * Performs a PHY software reset on the DSI controller. Reset should be done
  2039. * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
  2040. * not enabled.
  2041. *
  2042. * This function will fail if driver is in any other state.
  2043. *
  2044. * Return: error code.
  2045. */
  2046. int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl)
  2047. {
  2048. int rc = 0;
  2049. if (!dsi_ctrl) {
  2050. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2051. return -EINVAL;
  2052. }
  2053. mutex_lock(&dsi_ctrl->ctrl_lock);
  2054. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
  2055. if (rc) {
  2056. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2057. rc);
  2058. goto error;
  2059. }
  2060. dsi_ctrl->hw.ops.phy_sw_reset(&dsi_ctrl->hw);
  2061. DSI_CTRL_DEBUG(dsi_ctrl, "PHY soft reset done\n");
  2062. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
  2063. error:
  2064. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2065. return rc;
  2066. }
  2067. /**
  2068. * dsi_ctrl_seamless_timing_update() - update only controller timing
  2069. * @dsi_ctrl: DSI controller handle.
  2070. * @timing: New DSI timing info
  2071. *
  2072. * Updates host timing values to conduct a seamless transition to new timing
  2073. * For example, to update the porch values in a dynamic fps switch.
  2074. *
  2075. * Return: error code.
  2076. */
  2077. int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
  2078. struct dsi_mode_info *timing)
  2079. {
  2080. struct dsi_mode_info *host_mode;
  2081. int rc = 0;
  2082. if (!dsi_ctrl || !timing) {
  2083. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2084. return -EINVAL;
  2085. }
  2086. mutex_lock(&dsi_ctrl->ctrl_lock);
  2087. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,
  2088. DSI_CTRL_ENGINE_ON);
  2089. if (rc) {
  2090. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2091. rc);
  2092. goto exit;
  2093. }
  2094. host_mode = &dsi_ctrl->host_config.video_timing;
  2095. memcpy(host_mode, timing, sizeof(*host_mode));
  2096. dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, true);
  2097. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw, host_mode);
  2098. exit:
  2099. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2100. return rc;
  2101. }
  2102. /**
  2103. * dsi_ctrl_timing_db_update() - update only controller Timing DB
  2104. * @dsi_ctrl: DSI controller handle.
  2105. * @enable: Enable/disable Timing DB register
  2106. *
  2107. * Update timing db register value during dfps usecases
  2108. *
  2109. * Return: error code.
  2110. */
  2111. int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl,
  2112. bool enable)
  2113. {
  2114. int rc = 0;
  2115. if (!dsi_ctrl) {
  2116. DSI_CTRL_ERR(dsi_ctrl, "Invalid dsi_ctrl\n");
  2117. return -EINVAL;
  2118. }
  2119. mutex_lock(&dsi_ctrl->ctrl_lock);
  2120. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,
  2121. DSI_CTRL_ENGINE_ON);
  2122. if (rc) {
  2123. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2124. rc);
  2125. goto exit;
  2126. }
  2127. /*
  2128. * Add HW recommended delay for dfps feature.
  2129. * When prefetch is enabled, MDSS HW works on 2 vsync
  2130. * boundaries i.e. mdp_vsync and panel_vsync.
  2131. * In the current implementation we are only waiting
  2132. * for mdp_vsync. We need to make sure that interface
  2133. * flush is after panel_vsync. So, added the recommended
  2134. * delays after dfps update.
  2135. */
  2136. usleep_range(2000, 2010);
  2137. dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, enable);
  2138. exit:
  2139. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2140. return rc;
  2141. }
  2142. int dsi_ctrl_timing_setup(struct dsi_ctrl *dsi_ctrl)
  2143. {
  2144. int rc = 0;
  2145. if (!dsi_ctrl) {
  2146. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2147. return -EINVAL;
  2148. }
  2149. mutex_lock(&dsi_ctrl->ctrl_lock);
  2150. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2151. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2152. &dsi_ctrl->host_config.common_config,
  2153. &dsi_ctrl->host_config.u.cmd_engine);
  2154. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2155. &dsi_ctrl->host_config.video_timing,
  2156. &dsi_ctrl->host_config.common_config,
  2157. 0x0,
  2158. &dsi_ctrl->roi);
  2159. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
  2160. } else {
  2161. dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
  2162. &dsi_ctrl->host_config.common_config,
  2163. &dsi_ctrl->host_config.u.video_engine);
  2164. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
  2165. &dsi_ctrl->host_config.video_timing);
  2166. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, true);
  2167. }
  2168. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2169. return rc;
  2170. }
  2171. int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl)
  2172. {
  2173. int rc = 0;
  2174. rc = dsi_ctrl_timing_setup(dsi_ctrl);
  2175. if (rc)
  2176. return -EINVAL;
  2177. mutex_lock(&dsi_ctrl->ctrl_lock);
  2178. dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
  2179. &dsi_ctrl->host_config.lane_map);
  2180. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2181. &dsi_ctrl->host_config.common_config);
  2182. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
  2183. dsi_ctrl_enable_error_interrupts(dsi_ctrl);
  2184. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
  2185. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2186. return rc;
  2187. }
  2188. int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi,
  2189. bool *changed)
  2190. {
  2191. int rc = 0;
  2192. if (!dsi_ctrl || !roi || !changed) {
  2193. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2194. return -EINVAL;
  2195. }
  2196. mutex_lock(&dsi_ctrl->ctrl_lock);
  2197. if ((!dsi_rect_is_equal(&dsi_ctrl->roi, roi)) ||
  2198. dsi_ctrl->modeupdated) {
  2199. *changed = true;
  2200. memcpy(&dsi_ctrl->roi, roi, sizeof(dsi_ctrl->roi));
  2201. dsi_ctrl->modeupdated = false;
  2202. } else
  2203. *changed = false;
  2204. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2205. return rc;
  2206. }
  2207. /**
  2208. * dsi_ctrl_config_clk_gating() - Enable/disable DSI PHY clk gating.
  2209. * @dsi_ctrl: DSI controller handle.
  2210. * @enable: Enable/disable DSI PHY clk gating
  2211. * @clk_selection: clock to enable/disable clock gating
  2212. *
  2213. * Return: error code.
  2214. */
  2215. int dsi_ctrl_config_clk_gating(struct dsi_ctrl *dsi_ctrl, bool enable,
  2216. enum dsi_clk_gate_type clk_selection)
  2217. {
  2218. if (!dsi_ctrl) {
  2219. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2220. return -EINVAL;
  2221. }
  2222. if (dsi_ctrl->hw.ops.config_clk_gating)
  2223. dsi_ctrl->hw.ops.config_clk_gating(&dsi_ctrl->hw, enable,
  2224. clk_selection);
  2225. return 0;
  2226. }
  2227. /**
  2228. * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal
  2229. * to DSI PHY hardware.
  2230. * @dsi_ctrl: DSI controller handle.
  2231. * @enable: Mask/unmask the PHY reset signal.
  2232. *
  2233. * Return: error code.
  2234. */
  2235. int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable)
  2236. {
  2237. if (!dsi_ctrl) {
  2238. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2239. return -EINVAL;
  2240. }
  2241. if (dsi_ctrl->hw.ops.phy_reset_config)
  2242. dsi_ctrl->hw.ops.phy_reset_config(&dsi_ctrl->hw, enable);
  2243. return 0;
  2244. }
  2245. static bool dsi_ctrl_check_for_spurious_error_interrupts(
  2246. struct dsi_ctrl *dsi_ctrl)
  2247. {
  2248. const unsigned long intr_check_interval = msecs_to_jiffies(1000);
  2249. const unsigned int interrupt_threshold = 15;
  2250. unsigned long jiffies_now = jiffies;
  2251. if (!dsi_ctrl) {
  2252. DSI_CTRL_ERR(dsi_ctrl, "Invalid DSI controller structure\n");
  2253. return false;
  2254. }
  2255. if (dsi_ctrl->jiffies_start == 0)
  2256. dsi_ctrl->jiffies_start = jiffies;
  2257. dsi_ctrl->error_interrupt_count++;
  2258. if ((jiffies_now - dsi_ctrl->jiffies_start) < intr_check_interval) {
  2259. if (dsi_ctrl->error_interrupt_count > interrupt_threshold) {
  2260. SDE_EVT32_IRQ(dsi_ctrl->cell_index,
  2261. dsi_ctrl->error_interrupt_count,
  2262. interrupt_threshold);
  2263. return true;
  2264. }
  2265. } else {
  2266. dsi_ctrl->jiffies_start = jiffies;
  2267. dsi_ctrl->error_interrupt_count = 1;
  2268. }
  2269. return false;
  2270. }
  2271. static void dsi_ctrl_handle_error_status(struct dsi_ctrl *dsi_ctrl,
  2272. unsigned long error)
  2273. {
  2274. struct dsi_event_cb_info cb_info;
  2275. cb_info = dsi_ctrl->irq_info.irq_err_cb;
  2276. /* disable error interrupts */
  2277. if (dsi_ctrl->hw.ops.error_intr_ctrl)
  2278. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, false);
  2279. /* clear error interrupts first */
  2280. if (dsi_ctrl->hw.ops.clear_error_status)
  2281. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  2282. error);
  2283. /* DTLN PHY error */
  2284. if (error & 0x3000E00)
  2285. DSI_CTRL_ERR(dsi_ctrl, "dsi PHY contention error: 0x%lx\n",
  2286. error);
  2287. /* ignore TX timeout if blpp_lp11 is disabled */
  2288. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
  2289. !dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
  2290. !dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
  2291. error &= ~DSI_HS_TX_TIMEOUT;
  2292. /* TX timeout error */
  2293. if (error & 0xE0) {
  2294. if (error & 0xA0) {
  2295. if (cb_info.event_cb) {
  2296. cb_info.event_idx = DSI_LP_Rx_TIMEOUT;
  2297. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2298. cb_info.event_idx,
  2299. dsi_ctrl->cell_index,
  2300. 0, 0, 0, 0);
  2301. }
  2302. }
  2303. }
  2304. /* DSI FIFO OVERFLOW error */
  2305. if (error & 0xF0000) {
  2306. u32 mask = 0;
  2307. if (dsi_ctrl->hw.ops.get_error_mask)
  2308. mask = dsi_ctrl->hw.ops.get_error_mask(&dsi_ctrl->hw);
  2309. /* no need to report FIFO overflow if already masked */
  2310. if (cb_info.event_cb && !(mask & 0xf0000)) {
  2311. cb_info.event_idx = DSI_FIFO_OVERFLOW;
  2312. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2313. cb_info.event_idx,
  2314. dsi_ctrl->cell_index,
  2315. 0, 0, 0, 0);
  2316. }
  2317. }
  2318. /* DSI FIFO UNDERFLOW error */
  2319. if (error & 0xF00000) {
  2320. if (cb_info.event_cb) {
  2321. cb_info.event_idx = DSI_FIFO_UNDERFLOW;
  2322. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2323. cb_info.event_idx,
  2324. dsi_ctrl->cell_index,
  2325. 0, 0, 0, 0);
  2326. }
  2327. }
  2328. /* DSI PLL UNLOCK error */
  2329. if (error & BIT(8))
  2330. DSI_CTRL_ERR(dsi_ctrl, "dsi PLL unlock error: 0x%lx\n", error);
  2331. /* ACK error */
  2332. if (error & 0xF)
  2333. DSI_CTRL_ERR(dsi_ctrl, "ack error: 0x%lx\n", error);
  2334. /*
  2335. * DSI Phy can go into bad state during ESD influence. This can
  2336. * manifest as various types of spurious error interrupts on
  2337. * DSI controller. This check will allow us to handle afore mentioned
  2338. * case and prevent us from re enabling interrupts until a full ESD
  2339. * recovery is completed.
  2340. */
  2341. if (dsi_ctrl_check_for_spurious_error_interrupts(dsi_ctrl) &&
  2342. dsi_ctrl->esd_check_underway) {
  2343. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  2344. return;
  2345. }
  2346. /* enable back DSI interrupts */
  2347. if (dsi_ctrl->hw.ops.error_intr_ctrl)
  2348. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, true);
  2349. }
  2350. /**
  2351. * dsi_ctrl_isr - interrupt service routine for DSI CTRL component
  2352. * @irq: Incoming IRQ number
  2353. * @ptr: Pointer to user data structure (struct dsi_ctrl)
  2354. * Returns: IRQ_HANDLED if no further action required
  2355. */
  2356. static irqreturn_t dsi_ctrl_isr(int irq, void *ptr)
  2357. {
  2358. struct dsi_ctrl *dsi_ctrl;
  2359. struct dsi_event_cb_info cb_info;
  2360. unsigned long flags;
  2361. uint32_t status = 0x0, i;
  2362. uint64_t errors = 0x0;
  2363. if (!ptr)
  2364. return IRQ_NONE;
  2365. dsi_ctrl = ptr;
  2366. /* check status interrupts */
  2367. if (dsi_ctrl->hw.ops.get_interrupt_status)
  2368. status = dsi_ctrl->hw.ops.get_interrupt_status(&dsi_ctrl->hw);
  2369. /* check error interrupts */
  2370. if (dsi_ctrl->hw.ops.get_error_status)
  2371. errors = dsi_ctrl->hw.ops.get_error_status(&dsi_ctrl->hw);
  2372. /* clear interrupts */
  2373. if (dsi_ctrl->hw.ops.clear_interrupt_status)
  2374. dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw, 0x0);
  2375. SDE_EVT32_IRQ(dsi_ctrl->cell_index, status, errors);
  2376. /* handle DSI error recovery */
  2377. if (status & DSI_ERROR)
  2378. dsi_ctrl_handle_error_status(dsi_ctrl, errors);
  2379. if (status & DSI_CMD_MODE_DMA_DONE) {
  2380. if (dsi_ctrl->enable_cmd_dma_stats) {
  2381. u32 reg = dsi_ctrl->hw.ops.log_line_count(&dsi_ctrl->hw,
  2382. dsi_ctrl->cmd_mode);
  2383. dsi_ctrl->cmd_success_line = (reg & 0xFFFF);
  2384. dsi_ctrl->cmd_success_frame = ((reg >> 16) & 0xFFFF);
  2385. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  2386. dsi_ctrl->cmd_success_line,
  2387. dsi_ctrl->cmd_success_frame);
  2388. }
  2389. atomic_set(&dsi_ctrl->dma_irq_trig, 1);
  2390. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2391. DSI_SINT_CMD_MODE_DMA_DONE);
  2392. complete_all(&dsi_ctrl->irq_info.cmd_dma_done);
  2393. }
  2394. if (status & DSI_CMD_FRAME_DONE) {
  2395. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2396. DSI_SINT_CMD_FRAME_DONE);
  2397. complete_all(&dsi_ctrl->irq_info.cmd_frame_done);
  2398. }
  2399. if (status & DSI_VIDEO_MODE_FRAME_DONE) {
  2400. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2401. DSI_SINT_VIDEO_MODE_FRAME_DONE);
  2402. complete_all(&dsi_ctrl->irq_info.vid_frame_done);
  2403. }
  2404. if (status & DSI_BTA_DONE) {
  2405. u32 fifo_overflow_mask = (DSI_DLN0_HS_FIFO_OVERFLOW |
  2406. DSI_DLN1_HS_FIFO_OVERFLOW |
  2407. DSI_DLN2_HS_FIFO_OVERFLOW |
  2408. DSI_DLN3_HS_FIFO_OVERFLOW);
  2409. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  2410. DSI_SINT_BTA_DONE);
  2411. complete_all(&dsi_ctrl->irq_info.bta_done);
  2412. if (dsi_ctrl->hw.ops.clear_error_status)
  2413. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  2414. fifo_overflow_mask);
  2415. }
  2416. for (i = 0; status && i < DSI_STATUS_INTERRUPT_COUNT; ++i) {
  2417. if (status & 0x1) {
  2418. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2419. cb_info = dsi_ctrl->irq_info.irq_stat_cb[i];
  2420. spin_unlock_irqrestore(
  2421. &dsi_ctrl->irq_info.irq_lock, flags);
  2422. if (cb_info.event_cb)
  2423. (void)cb_info.event_cb(cb_info.event_usr_ptr,
  2424. cb_info.event_idx,
  2425. dsi_ctrl->cell_index,
  2426. irq, 0, 0, 0);
  2427. }
  2428. status >>= 1;
  2429. }
  2430. return IRQ_HANDLED;
  2431. }
  2432. /**
  2433. * _dsi_ctrl_setup_isr - register ISR handler
  2434. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  2435. * Returns: Zero on success
  2436. */
  2437. static int _dsi_ctrl_setup_isr(struct dsi_ctrl *dsi_ctrl)
  2438. {
  2439. int irq_num, rc;
  2440. if (!dsi_ctrl)
  2441. return -EINVAL;
  2442. if (dsi_ctrl->irq_info.irq_num != -1)
  2443. return 0;
  2444. init_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  2445. init_completion(&dsi_ctrl->irq_info.vid_frame_done);
  2446. init_completion(&dsi_ctrl->irq_info.cmd_frame_done);
  2447. init_completion(&dsi_ctrl->irq_info.bta_done);
  2448. irq_num = platform_get_irq(dsi_ctrl->pdev, 0);
  2449. if (irq_num < 0) {
  2450. DSI_CTRL_ERR(dsi_ctrl, "Failed to get IRQ number, %d\n",
  2451. irq_num);
  2452. rc = irq_num;
  2453. } else {
  2454. rc = devm_request_threaded_irq(&dsi_ctrl->pdev->dev, irq_num,
  2455. dsi_ctrl_isr, NULL, 0, "dsi_ctrl", dsi_ctrl);
  2456. if (rc) {
  2457. DSI_CTRL_ERR(dsi_ctrl, "Failed to request IRQ, %d\n",
  2458. rc);
  2459. } else {
  2460. dsi_ctrl->irq_info.irq_num = irq_num;
  2461. disable_irq_nosync(irq_num);
  2462. DSI_CTRL_INFO(dsi_ctrl, "IRQ %d registered\n", irq_num);
  2463. }
  2464. }
  2465. return rc;
  2466. }
  2467. /**
  2468. * _dsi_ctrl_destroy_isr - unregister ISR handler
  2469. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  2470. */
  2471. static void _dsi_ctrl_destroy_isr(struct dsi_ctrl *dsi_ctrl)
  2472. {
  2473. if (!dsi_ctrl || !dsi_ctrl->pdev || dsi_ctrl->irq_info.irq_num < 0)
  2474. return;
  2475. if (dsi_ctrl->irq_info.irq_num != -1) {
  2476. devm_free_irq(&dsi_ctrl->pdev->dev,
  2477. dsi_ctrl->irq_info.irq_num, dsi_ctrl);
  2478. dsi_ctrl->irq_info.irq_num = -1;
  2479. }
  2480. }
  2481. void dsi_ctrl_enable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
  2482. uint32_t intr_idx, struct dsi_event_cb_info *event_info)
  2483. {
  2484. unsigned long flags;
  2485. if (!dsi_ctrl || dsi_ctrl->irq_info.irq_num == -1 ||
  2486. intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
  2487. return;
  2488. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
  2489. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2490. if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx] == 0) {
  2491. /* enable irq on first request */
  2492. if (dsi_ctrl->irq_info.irq_stat_mask == 0)
  2493. enable_irq(dsi_ctrl->irq_info.irq_num);
  2494. /* update hardware mask */
  2495. dsi_ctrl->irq_info.irq_stat_mask |= BIT(intr_idx);
  2496. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2497. dsi_ctrl->irq_info.irq_stat_mask);
  2498. }
  2499. if (intr_idx == DSI_SINT_CMD_MODE_DMA_DONE)
  2500. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2501. dsi_ctrl->irq_info.irq_stat_mask);
  2502. ++(dsi_ctrl->irq_info.irq_stat_refcount[intr_idx]);
  2503. if (event_info)
  2504. dsi_ctrl->irq_info.irq_stat_cb[intr_idx] = *event_info;
  2505. spin_unlock_irqrestore(&dsi_ctrl->irq_info.irq_lock, flags);
  2506. }
  2507. void dsi_ctrl_disable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
  2508. uint32_t intr_idx)
  2509. {
  2510. unsigned long flags;
  2511. if (!dsi_ctrl || intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
  2512. return;
  2513. SDE_EVT32_IRQ(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
  2514. spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
  2515. if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx])
  2516. if (--(dsi_ctrl->irq_info.irq_stat_refcount[intr_idx]) == 0) {
  2517. dsi_ctrl->irq_info.irq_stat_mask &= ~BIT(intr_idx);
  2518. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw,
  2519. dsi_ctrl->irq_info.irq_stat_mask);
  2520. /* don't need irq if no lines are enabled */
  2521. if (dsi_ctrl->irq_info.irq_stat_mask == 0 &&
  2522. dsi_ctrl->irq_info.irq_num != -1)
  2523. disable_irq_nosync(dsi_ctrl->irq_info.irq_num);
  2524. }
  2525. spin_unlock_irqrestore(&dsi_ctrl->irq_info.irq_lock, flags);
  2526. }
  2527. int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
  2528. {
  2529. if (!dsi_ctrl) {
  2530. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2531. return -EINVAL;
  2532. }
  2533. if (dsi_ctrl->hw.ops.host_setup)
  2534. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2535. &dsi_ctrl->host_config.common_config);
  2536. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2537. if (dsi_ctrl->hw.ops.cmd_engine_setup)
  2538. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2539. &dsi_ctrl->host_config.common_config,
  2540. &dsi_ctrl->host_config.u.cmd_engine);
  2541. if (dsi_ctrl->hw.ops.setup_cmd_stream)
  2542. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2543. &dsi_ctrl->host_config.video_timing,
  2544. &dsi_ctrl->host_config.common_config,
  2545. 0x0, NULL);
  2546. } else {
  2547. DSI_CTRL_ERR(dsi_ctrl, "invalid panel mode for resolution switch\n");
  2548. return -EINVAL;
  2549. }
  2550. return 0;
  2551. }
  2552. /**
  2553. * dsi_ctrl_update_host_state() - Update the host initialization state.
  2554. * @dsi_ctrl: DSI controller handle.
  2555. * @op: ctrl driver ops
  2556. * @enable: boolean signifying host state.
  2557. *
  2558. * Update the host status only while exiting from ulps during suspend state.
  2559. *
  2560. * Return: error code.
  2561. */
  2562. int dsi_ctrl_update_host_state(struct dsi_ctrl *dsi_ctrl,
  2563. enum dsi_ctrl_driver_ops op, bool enable)
  2564. {
  2565. int rc = 0;
  2566. u32 state = enable ? 0x1 : 0x0;
  2567. if (!dsi_ctrl)
  2568. return rc;
  2569. mutex_lock(&dsi_ctrl->ctrl_lock);
  2570. rc = dsi_ctrl_check_state(dsi_ctrl, op, state);
  2571. if (rc) {
  2572. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2573. rc);
  2574. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2575. return rc;
  2576. }
  2577. dsi_ctrl_update_state(dsi_ctrl, op, state);
  2578. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2579. return rc;
  2580. }
  2581. /**
  2582. * dsi_ctrl_host_init() - Initialize DSI host hardware.
  2583. * @dsi_ctrl: DSI controller handle.
  2584. * @skip_op: Boolean to indicate few operations can be skipped.
  2585. * Set during the cont-splash or trusted-vm enable case.
  2586. *
  2587. * Initializes DSI controller hardware with host configuration provided by
  2588. * dsi_ctrl_update_host_config(). Initialization can be performed only during
  2589. * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
  2590. * performed.
  2591. *
  2592. * Return: error code.
  2593. */
  2594. int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool skip_op)
  2595. {
  2596. int rc = 0;
  2597. if (!dsi_ctrl) {
  2598. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2599. return -EINVAL;
  2600. }
  2601. mutex_lock(&dsi_ctrl->ctrl_lock);
  2602. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
  2603. if (rc) {
  2604. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2605. rc);
  2606. goto error;
  2607. }
  2608. /*
  2609. * For continuous splash/trusted vm usecases we omit hw operations
  2610. * as bootloader/primary vm takes care of them respectively
  2611. */
  2612. if (!skip_op) {
  2613. dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
  2614. &dsi_ctrl->host_config.lane_map);
  2615. dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
  2616. &dsi_ctrl->host_config.common_config);
  2617. if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  2618. dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
  2619. &dsi_ctrl->host_config.common_config,
  2620. &dsi_ctrl->host_config.u.cmd_engine);
  2621. dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
  2622. &dsi_ctrl->host_config.video_timing,
  2623. &dsi_ctrl->host_config.common_config,
  2624. 0x0,
  2625. NULL);
  2626. } else {
  2627. dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
  2628. &dsi_ctrl->host_config.common_config,
  2629. &dsi_ctrl->host_config.u.video_engine);
  2630. dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
  2631. &dsi_ctrl->host_config.video_timing);
  2632. }
  2633. }
  2634. dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
  2635. dsi_ctrl_enable_error_interrupts(dsi_ctrl);
  2636. DSI_CTRL_DEBUG(dsi_ctrl, "Host initialization complete, skip op: %d\n",
  2637. skip_op);
  2638. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
  2639. error:
  2640. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2641. return rc;
  2642. }
  2643. /**
  2644. * dsi_ctrl_isr_configure() - API to register/deregister dsi isr
  2645. * @dsi_ctrl: DSI controller handle.
  2646. * @enable: variable to control register/deregister isr
  2647. */
  2648. void dsi_ctrl_isr_configure(struct dsi_ctrl *dsi_ctrl, bool enable)
  2649. {
  2650. if (!dsi_ctrl)
  2651. return;
  2652. mutex_lock(&dsi_ctrl->ctrl_lock);
  2653. if (enable)
  2654. _dsi_ctrl_setup_isr(dsi_ctrl);
  2655. else
  2656. _dsi_ctrl_destroy_isr(dsi_ctrl);
  2657. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2658. }
  2659. void dsi_ctrl_hs_req_sel(struct dsi_ctrl *dsi_ctrl, bool sel_phy)
  2660. {
  2661. if (!dsi_ctrl)
  2662. return;
  2663. mutex_lock(&dsi_ctrl->ctrl_lock);
  2664. dsi_ctrl->hw.ops.hs_req_sel(&dsi_ctrl->hw, sel_phy);
  2665. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2666. }
  2667. void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable)
  2668. {
  2669. if (!dsi_ctrl)
  2670. return;
  2671. mutex_lock(&dsi_ctrl->ctrl_lock);
  2672. dsi_ctrl->hw.ops.set_continuous_clk(&dsi_ctrl->hw, enable);
  2673. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2674. }
  2675. int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl)
  2676. {
  2677. if (!dsi_ctrl)
  2678. return -EINVAL;
  2679. mutex_lock(&dsi_ctrl->ctrl_lock);
  2680. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  2681. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2682. DSI_CTRL_DEBUG(dsi_ctrl, "Soft reset complete\n");
  2683. return 0;
  2684. }
  2685. int dsi_ctrl_reset(struct dsi_ctrl *dsi_ctrl, int mask)
  2686. {
  2687. int rc = 0;
  2688. if (!dsi_ctrl)
  2689. return -EINVAL;
  2690. mutex_lock(&dsi_ctrl->ctrl_lock);
  2691. rc = dsi_ctrl->hw.ops.ctrl_reset(&dsi_ctrl->hw, mask);
  2692. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2693. return rc;
  2694. }
  2695. int dsi_ctrl_get_hw_version(struct dsi_ctrl *dsi_ctrl)
  2696. {
  2697. int rc = 0;
  2698. if (!dsi_ctrl)
  2699. return -EINVAL;
  2700. mutex_lock(&dsi_ctrl->ctrl_lock);
  2701. rc = dsi_ctrl->hw.ops.get_hw_version(&dsi_ctrl->hw);
  2702. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2703. return rc;
  2704. }
  2705. int dsi_ctrl_vid_engine_en(struct dsi_ctrl *dsi_ctrl, bool on)
  2706. {
  2707. int rc = 0;
  2708. if (!dsi_ctrl)
  2709. return -EINVAL;
  2710. mutex_lock(&dsi_ctrl->ctrl_lock);
  2711. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
  2712. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2713. return rc;
  2714. }
  2715. int dsi_ctrl_setup_avr(struct dsi_ctrl *dsi_ctrl, bool enable)
  2716. {
  2717. if (!dsi_ctrl)
  2718. return -EINVAL;
  2719. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
  2720. mutex_lock(&dsi_ctrl->ctrl_lock);
  2721. dsi_ctrl->hw.ops.setup_avr(&dsi_ctrl->hw, enable);
  2722. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2723. }
  2724. return 0;
  2725. }
  2726. /**
  2727. * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
  2728. * @dsi_ctrl: DSI controller handle.
  2729. *
  2730. * De-initializes DSI controller hardware. It can be performed only during
  2731. * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
  2732. *
  2733. * Return: error code.
  2734. */
  2735. int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl)
  2736. {
  2737. int rc = 0;
  2738. if (!dsi_ctrl) {
  2739. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2740. return -EINVAL;
  2741. }
  2742. mutex_lock(&dsi_ctrl->ctrl_lock);
  2743. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
  2744. if (rc) {
  2745. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2746. rc);
  2747. DSI_CTRL_ERR(dsi_ctrl, "driver state check failed, rc=%d\n",
  2748. rc);
  2749. goto error;
  2750. }
  2751. DSI_CTRL_DEBUG(dsi_ctrl, "Host deinitization complete\n");
  2752. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
  2753. error:
  2754. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2755. return rc;
  2756. }
  2757. /**
  2758. * dsi_ctrl_update_host_config() - update dsi host configuration
  2759. * @dsi_ctrl: DSI controller handle.
  2760. * @config: DSI host configuration.
  2761. * @flags: dsi_mode_flags modifying the behavior
  2762. *
  2763. * Updates driver with new Host configuration to use for host initialization.
  2764. * This function call will only update the software context. The stored
  2765. * configuration information will be used when the host is initialized.
  2766. *
  2767. * Return: error code.
  2768. */
  2769. int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
  2770. struct dsi_host_config *config,
  2771. struct dsi_display_mode *mode, int flags,
  2772. void *clk_handle)
  2773. {
  2774. int rc = 0;
  2775. if (!ctrl || !config) {
  2776. DSI_CTRL_ERR(ctrl, "Invalid params\n");
  2777. return -EINVAL;
  2778. }
  2779. mutex_lock(&ctrl->ctrl_lock);
  2780. rc = dsi_ctrl_validate_panel_info(ctrl, config);
  2781. if (rc) {
  2782. DSI_CTRL_ERR(ctrl, "panel validation failed, rc=%d\n", rc);
  2783. goto error;
  2784. }
  2785. if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  2786. DSI_MODE_FLAG_DYN_CLK))) {
  2787. /*
  2788. * for dynamic clk switch case link frequence would
  2789. * be updated dsi_display_dynamic_clk_switch().
  2790. */
  2791. rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle,
  2792. mode);
  2793. if (rc) {
  2794. DSI_CTRL_ERR(ctrl, "failed to update link frequency, rc=%d\n",
  2795. rc);
  2796. goto error;
  2797. }
  2798. }
  2799. DSI_CTRL_DEBUG(ctrl, "Host config updated\n");
  2800. memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config));
  2801. ctrl->mode_bounds.x = ctrl->host_config.video_timing.h_active *
  2802. ctrl->horiz_index;
  2803. ctrl->mode_bounds.y = 0;
  2804. ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active;
  2805. ctrl->mode_bounds.h = ctrl->host_config.video_timing.v_active;
  2806. memcpy(&ctrl->roi, &ctrl->mode_bounds, sizeof(ctrl->mode_bounds));
  2807. ctrl->modeupdated = true;
  2808. ctrl->roi.x = 0;
  2809. error:
  2810. mutex_unlock(&ctrl->ctrl_lock);
  2811. return rc;
  2812. }
  2813. /**
  2814. * dsi_ctrl_validate_timing() - validate a video timing configuration
  2815. * @dsi_ctrl: DSI controller handle.
  2816. * @timing: Pointer to timing data.
  2817. *
  2818. * Driver will validate if the timing configuration is supported on the
  2819. * controller hardware.
  2820. *
  2821. * Return: error code if timing is not supported.
  2822. */
  2823. int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
  2824. struct dsi_mode_info *mode)
  2825. {
  2826. int rc = 0;
  2827. if (!dsi_ctrl || !mode) {
  2828. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2829. return -EINVAL;
  2830. }
  2831. return rc;
  2832. }
  2833. /**
  2834. * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
  2835. * @dsi_ctrl: DSI controller handle.
  2836. * @cmd: Command description to transfer on DSI link.
  2837. *
  2838. * Command transfer can be done only when command engine is enabled. The
  2839. * transfer API will block until either the command transfer finishes or
  2840. * the timeout value is reached. If the trigger is deferred, it will return
  2841. * without triggering the transfer. Command parameters are programmed to
  2842. * hardware.
  2843. *
  2844. * Return: error code.
  2845. */
  2846. int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl, struct dsi_cmd_desc *cmd)
  2847. {
  2848. int rc = 0;
  2849. if (!dsi_ctrl || !cmd) {
  2850. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2851. return -EINVAL;
  2852. }
  2853. mutex_lock(&dsi_ctrl->ctrl_lock);
  2854. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
  2855. if (rc) {
  2856. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  2857. rc);
  2858. goto error;
  2859. }
  2860. if (cmd->ctrl_flags & DSI_CTRL_CMD_READ) {
  2861. rc = dsi_message_rx(dsi_ctrl, cmd);
  2862. if (rc <= 0)
  2863. DSI_CTRL_ERR(dsi_ctrl, "read message failed read length, rc=%d\n",
  2864. rc);
  2865. } else {
  2866. rc = dsi_message_tx(dsi_ctrl, cmd);
  2867. if (rc)
  2868. DSI_CTRL_ERR(dsi_ctrl, "command msg transfer failed, rc = %d\n",
  2869. rc);
  2870. }
  2871. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
  2872. error:
  2873. mutex_unlock(&dsi_ctrl->ctrl_lock);
  2874. return rc;
  2875. }
  2876. /**
  2877. * dsi_ctrl_mask_overflow() - API to mask/unmask overflow error.
  2878. * @dsi_ctrl: DSI controller handle.
  2879. * @enable: variable to control masking/unmasking.
  2880. */
  2881. void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable)
  2882. {
  2883. struct dsi_ctrl_hw_ops dsi_hw_ops;
  2884. dsi_hw_ops = dsi_ctrl->hw.ops;
  2885. if (enable) {
  2886. if (dsi_hw_ops.mask_error_intr)
  2887. dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
  2888. BIT(DSI_FIFO_OVERFLOW), true);
  2889. } else {
  2890. if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway)
  2891. dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
  2892. BIT(DSI_FIFO_OVERFLOW), false);
  2893. }
  2894. }
  2895. /**
  2896. * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
  2897. * @dsi_ctrl: DSI controller handle.
  2898. * @flags: Modifiers.
  2899. *
  2900. * Return: error code.
  2901. */
  2902. int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
  2903. {
  2904. int rc = 0;
  2905. struct dsi_ctrl_hw_ops dsi_hw_ops;
  2906. u32 v_total = 0, fps = 0, cur_line = 0, mem_latency_us = 100;
  2907. u32 line_time = 0, schedule_line = 0x1, latency_by_line = 0;
  2908. struct dsi_mode_info *timing;
  2909. unsigned long flag;
  2910. if (!dsi_ctrl) {
  2911. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  2912. return -EINVAL;
  2913. }
  2914. dsi_hw_ops = dsi_ctrl->hw.ops;
  2915. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags);
  2916. /* Dont trigger the command if this is not the last ocmmand */
  2917. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2918. return rc;
  2919. mutex_lock(&dsi_ctrl->ctrl_lock);
  2920. timing = &(dsi_ctrl->host_config.video_timing);
  2921. if (timing &&
  2922. (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE)) {
  2923. v_total = timing->v_sync_width + timing->v_back_porch +
  2924. timing->v_front_porch + timing->v_active;
  2925. fps = timing->refresh_rate;
  2926. schedule_line = calculate_schedule_line(dsi_ctrl, flags);
  2927. line_time = (1000000 / fps) / v_total;
  2928. latency_by_line = CEIL(mem_latency_us, line_time);
  2929. }
  2930. if (!(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
  2931. dsi_hw_ops.trigger_command_dma(&dsi_ctrl->hw);
  2932. if (dsi_ctrl->enable_cmd_dma_stats) {
  2933. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  2934. dsi_ctrl->cmd_mode);
  2935. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  2936. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  2937. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  2938. dsi_ctrl->cmd_trigger_line,
  2939. dsi_ctrl->cmd_trigger_frame);
  2940. }
  2941. }
  2942. if ((flags & DSI_CTRL_CMD_BROADCAST) &&
  2943. (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
  2944. dsi_ctrl_wait_for_video_done(dsi_ctrl);
  2945. atomic_set(&dsi_ctrl->dma_irq_trig, 0);
  2946. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  2947. DSI_SINT_CMD_MODE_DMA_DONE, NULL);
  2948. reinit_completion(&dsi_ctrl->irq_info.cmd_dma_done);
  2949. /* trigger command */
  2950. if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
  2951. dsi_hw_ops.schedule_dma_cmd &&
  2952. (dsi_ctrl->current_state.vid_engine_state ==
  2953. DSI_CTRL_ENGINE_ON)) {
  2954. /*
  2955. * This change reads the video line count from
  2956. * MDP_INTF_LINE_COUNT register and checks whether
  2957. * DMA trigger happens close to the schedule line.
  2958. * If it is not close to the schedule line, then DMA
  2959. * command transfer is triggered.
  2960. */
  2961. while (1) {
  2962. local_irq_save(flag);
  2963. cur_line =
  2964. dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  2965. dsi_ctrl->cmd_mode);
  2966. if (cur_line <
  2967. (schedule_line - latency_by_line) ||
  2968. cur_line > (schedule_line + 1)) {
  2969. dsi_hw_ops.trigger_command_dma(
  2970. &dsi_ctrl->hw);
  2971. local_irq_restore(flag);
  2972. break;
  2973. }
  2974. local_irq_restore(flag);
  2975. udelay(1000);
  2976. }
  2977. } else
  2978. dsi_hw_ops.trigger_command_dma(&dsi_ctrl->hw);
  2979. if (dsi_ctrl->enable_cmd_dma_stats) {
  2980. u32 reg = dsi_hw_ops.log_line_count(&dsi_ctrl->hw,
  2981. dsi_ctrl->cmd_mode);
  2982. dsi_ctrl->cmd_trigger_line = (reg & 0xFFFF);
  2983. dsi_ctrl->cmd_trigger_frame = ((reg >> 16) & 0xFFFF);
  2984. SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1,
  2985. dsi_ctrl->cmd_trigger_line,
  2986. dsi_ctrl->cmd_trigger_frame);
  2987. }
  2988. if (flags & DSI_CTRL_CMD_ASYNC_WAIT) {
  2989. dsi_ctrl->dma_wait_queued = true;
  2990. queue_work(dsi_ctrl->dma_cmd_workq,
  2991. &dsi_ctrl->dma_cmd_wait);
  2992. } else {
  2993. dsi_ctrl->dma_wait_queued = false;
  2994. dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait);
  2995. }
  2996. if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
  2997. if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4)
  2998. dsi_hw_ops.soft_reset(&dsi_ctrl->hw);
  2999. dsi_ctrl->cmd_len = 0;
  3000. }
  3001. }
  3002. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3003. return rc;
  3004. }
  3005. /**
  3006. * dsi_ctrl_cache_misr - Cache frame MISR value
  3007. * @dsi_ctrl: Pointer to associated dsi_ctrl structure
  3008. */
  3009. void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl)
  3010. {
  3011. u32 misr;
  3012. if (!dsi_ctrl || !dsi_ctrl->hw.ops.collect_misr)
  3013. return;
  3014. misr = dsi_ctrl->hw.ops.collect_misr(&dsi_ctrl->hw,
  3015. dsi_ctrl->host_config.panel_mode);
  3016. if (misr)
  3017. dsi_ctrl->misr_cache = misr;
  3018. DSI_CTRL_DEBUG(dsi_ctrl, "misr_cache = %x\n", dsi_ctrl->misr_cache);
  3019. }
  3020. /**
  3021. * dsi_ctrl_get_host_engine_init_state() - Return host init state
  3022. * @dsi_ctrl: DSI controller handle.
  3023. * @state: Controller initialization state
  3024. *
  3025. * Return: error code.
  3026. */
  3027. int dsi_ctrl_get_host_engine_init_state(struct dsi_ctrl *dsi_ctrl,
  3028. bool *state)
  3029. {
  3030. if (!dsi_ctrl || !state) {
  3031. DSI_CTRL_ERR(dsi_ctrl, "Invalid Params\n");
  3032. return -EINVAL;
  3033. }
  3034. mutex_lock(&dsi_ctrl->ctrl_lock);
  3035. *state = dsi_ctrl->current_state.host_initialized;
  3036. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3037. return 0;
  3038. }
  3039. /**
  3040. * dsi_ctrl_set_power_state() - set power state for dsi controller
  3041. * @dsi_ctrl: DSI controller handle.
  3042. * @state: Power state.
  3043. *
  3044. * Set power state for DSI controller. Power state can be changed only when
  3045. * Controller, Video and Command engines are turned off.
  3046. *
  3047. * Return: error code.
  3048. */
  3049. int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
  3050. enum dsi_power_state state)
  3051. {
  3052. int rc = 0;
  3053. if (!dsi_ctrl || (state >= DSI_CTRL_POWER_MAX)) {
  3054. DSI_CTRL_ERR(dsi_ctrl, "Invalid Params\n");
  3055. return -EINVAL;
  3056. }
  3057. mutex_lock(&dsi_ctrl->ctrl_lock);
  3058. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE,
  3059. state);
  3060. if (rc) {
  3061. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3062. rc);
  3063. goto error;
  3064. }
  3065. if (state == DSI_CTRL_POWER_VREG_ON) {
  3066. rc = dsi_ctrl_enable_supplies(dsi_ctrl, true);
  3067. if (rc) {
  3068. DSI_CTRL_ERR(dsi_ctrl, "failed to enable voltage supplies, rc=%d\n",
  3069. rc);
  3070. goto error;
  3071. }
  3072. } else if (state == DSI_CTRL_POWER_VREG_OFF) {
  3073. rc = dsi_ctrl_enable_supplies(dsi_ctrl, false);
  3074. if (rc) {
  3075. DSI_CTRL_ERR(dsi_ctrl, "failed to disable vreg supplies, rc=%d\n",
  3076. rc);
  3077. goto error;
  3078. }
  3079. }
  3080. DSI_CTRL_DEBUG(dsi_ctrl, "Power state updated to %d\n", state);
  3081. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state);
  3082. error:
  3083. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3084. return rc;
  3085. }
  3086. /**
  3087. * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
  3088. * @dsi_ctrl: DSI controller handle.
  3089. * @on: enable/disable test pattern.
  3090. *
  3091. * Test pattern can be enabled only after Video engine (for video mode panels)
  3092. * or command engine (for cmd mode panels) is enabled.
  3093. *
  3094. * Return: error code.
  3095. */
  3096. int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on)
  3097. {
  3098. int rc = 0;
  3099. if (!dsi_ctrl) {
  3100. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3101. return -EINVAL;
  3102. }
  3103. mutex_lock(&dsi_ctrl->ctrl_lock);
  3104. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
  3105. if (rc) {
  3106. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3107. rc);
  3108. goto error;
  3109. }
  3110. if (on) {
  3111. if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
  3112. dsi_ctrl->hw.ops.video_test_pattern_setup(&dsi_ctrl->hw,
  3113. DSI_TEST_PATTERN_INC,
  3114. 0xFFFF);
  3115. } else {
  3116. dsi_ctrl->hw.ops.cmd_test_pattern_setup(
  3117. &dsi_ctrl->hw,
  3118. DSI_TEST_PATTERN_INC,
  3119. 0xFFFF,
  3120. 0x0);
  3121. }
  3122. }
  3123. dsi_ctrl->hw.ops.test_pattern_enable(&dsi_ctrl->hw, on);
  3124. DSI_CTRL_DEBUG(dsi_ctrl, "Set test pattern state=%d\n", on);
  3125. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
  3126. error:
  3127. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3128. return rc;
  3129. }
  3130. /**
  3131. * dsi_ctrl_set_host_engine_state() - set host engine state
  3132. * @dsi_ctrl: DSI Controller handle.
  3133. * @state: Engine state.
  3134. * @skip_op: Boolean to indicate few operations can be skipped.
  3135. * Set during the cont-splash or trusted-vm enable case.
  3136. *
  3137. * Host engine state can be modified only when DSI controller power state is
  3138. * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
  3139. *
  3140. * Return: error code.
  3141. */
  3142. int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
  3143. enum dsi_engine_state state, bool skip_op)
  3144. {
  3145. int rc = 0;
  3146. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3147. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3148. return -EINVAL;
  3149. }
  3150. mutex_lock(&dsi_ctrl->ctrl_lock);
  3151. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
  3152. if (rc) {
  3153. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3154. rc);
  3155. goto error;
  3156. }
  3157. if (!skip_op) {
  3158. if (state == DSI_CTRL_ENGINE_ON)
  3159. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
  3160. else
  3161. dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, false);
  3162. }
  3163. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3164. DSI_CTRL_DEBUG(dsi_ctrl, "Set host engine state = %d\n", state);
  3165. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
  3166. error:
  3167. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3168. return rc;
  3169. }
  3170. /**
  3171. * dsi_ctrl_set_cmd_engine_state() - set command engine state
  3172. * @dsi_ctrl: DSI Controller handle.
  3173. * @state: Engine state.
  3174. * @skip_op: Boolean to indicate few operations can be skipped.
  3175. * Set during the cont-splash or trusted-vm enable case.
  3176. *
  3177. * Command engine state can be modified only when DSI controller power state is
  3178. * set to DSI_CTRL_POWER_LINK_CLK_ON.
  3179. *
  3180. * Return: error code.
  3181. */
  3182. int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
  3183. enum dsi_engine_state state, bool skip_op)
  3184. {
  3185. int rc = 0;
  3186. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3187. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3188. return -EINVAL;
  3189. }
  3190. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
  3191. if (rc) {
  3192. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3193. rc);
  3194. goto error;
  3195. }
  3196. if (!skip_op) {
  3197. if (state == DSI_CTRL_ENGINE_ON)
  3198. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
  3199. else
  3200. dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, false);
  3201. }
  3202. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3203. DSI_CTRL_DEBUG(dsi_ctrl, "Set cmd engine state:%d, skip_op:%d\n",
  3204. state, skip_op);
  3205. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
  3206. error:
  3207. return rc;
  3208. }
  3209. /**
  3210. * dsi_ctrl_set_vid_engine_state() - set video engine state
  3211. * @dsi_ctrl: DSI Controller handle.
  3212. * @state: Engine state.
  3213. * @skip_op: Boolean to indicate few operations can be skipped.
  3214. * Set during the cont-splash or trusted-vm enable case.
  3215. *
  3216. * Video engine state can be modified only when DSI controller power state is
  3217. * set to DSI_CTRL_POWER_LINK_CLK_ON.
  3218. *
  3219. * Return: error code.
  3220. */
  3221. int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
  3222. enum dsi_engine_state state, bool skip_op)
  3223. {
  3224. int rc = 0;
  3225. bool on;
  3226. bool vid_eng_busy;
  3227. if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
  3228. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3229. return -EINVAL;
  3230. }
  3231. mutex_lock(&dsi_ctrl->ctrl_lock);
  3232. rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
  3233. if (rc) {
  3234. DSI_CTRL_ERR(dsi_ctrl, "Controller state check failed, rc=%d\n",
  3235. rc);
  3236. goto error;
  3237. }
  3238. if (!skip_op) {
  3239. on = (state == DSI_CTRL_ENGINE_ON) ? true : false;
  3240. dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
  3241. vid_eng_busy = dsi_ctrl->hw.ops.vid_engine_busy(&dsi_ctrl->hw);
  3242. /*
  3243. * During ESD check failure, DSI video engine can get stuck
  3244. * sending data from display engine. In use cases where GDSC
  3245. * toggle does not happen like DP MST connected or secure video
  3246. * playback, display does not recover back after ESD failure.
  3247. * Perform a reset if video engine is stuck.
  3248. */
  3249. if (!on && (dsi_ctrl->version < DSI_CTRL_VERSION_1_3 ||
  3250. vid_eng_busy))
  3251. dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
  3252. }
  3253. SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
  3254. DSI_CTRL_DEBUG(dsi_ctrl, "Set video engine state:%d, skip_op:%d\n",
  3255. state, skip_op);
  3256. dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
  3257. error:
  3258. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3259. return rc;
  3260. }
  3261. /**
  3262. * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
  3263. * @dsi_ctrl: DSI controller handle.
  3264. * @enable: enable/disable ULPS.
  3265. *
  3266. * ULPS can be enabled/disabled after DSI host engine is turned on.
  3267. *
  3268. * Return: error code.
  3269. */
  3270. int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable)
  3271. {
  3272. int rc = 0;
  3273. if (!dsi_ctrl) {
  3274. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3275. return -EINVAL;
  3276. }
  3277. mutex_lock(&dsi_ctrl->ctrl_lock);
  3278. if (enable)
  3279. rc = dsi_enable_ulps(dsi_ctrl);
  3280. else
  3281. rc = dsi_disable_ulps(dsi_ctrl);
  3282. if (rc) {
  3283. DSI_CTRL_ERR(dsi_ctrl, "Ulps state change(%d) failed, rc=%d\n",
  3284. enable, rc);
  3285. goto error;
  3286. }
  3287. DSI_CTRL_DEBUG(dsi_ctrl, "ULPS state = %d\n", enable);
  3288. error:
  3289. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3290. return rc;
  3291. }
  3292. /**
  3293. * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
  3294. * @dsi_ctrl: DSI controller handle.
  3295. * @enable: enable/disable clamping.
  3296. *
  3297. * Clamps can be enabled/disabled while DSI controller is still turned on.
  3298. *
  3299. * Return: error code.
  3300. */
  3301. int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_ctrl,
  3302. bool enable, bool ulps_enabled)
  3303. {
  3304. int rc = 0;
  3305. if (!dsi_ctrl) {
  3306. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3307. return -EINVAL;
  3308. }
  3309. if (!dsi_ctrl->hw.ops.clamp_enable ||
  3310. !dsi_ctrl->hw.ops.clamp_disable) {
  3311. DSI_CTRL_DEBUG(dsi_ctrl, "No clamp control for DSI controller\n");
  3312. return 0;
  3313. }
  3314. mutex_lock(&dsi_ctrl->ctrl_lock);
  3315. rc = dsi_enable_io_clamp(dsi_ctrl, enable, ulps_enabled);
  3316. if (rc) {
  3317. DSI_CTRL_ERR(dsi_ctrl, "Failed to enable IO clamp\n");
  3318. goto error;
  3319. }
  3320. DSI_CTRL_DEBUG(dsi_ctrl, "Clamp state = %d\n", enable);
  3321. error:
  3322. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3323. return rc;
  3324. }
  3325. /**
  3326. * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
  3327. * @dsi_ctrl: DSI controller handle.
  3328. * @source_clks: Source clocks for DSI link clocks.
  3329. *
  3330. * Clock source should be changed while link clocks are disabled.
  3331. *
  3332. * Return: error code.
  3333. */
  3334. int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
  3335. struct dsi_clk_link_set *source_clks)
  3336. {
  3337. int rc = 0;
  3338. if (!dsi_ctrl || !source_clks) {
  3339. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3340. return -EINVAL;
  3341. }
  3342. mutex_lock(&dsi_ctrl->ctrl_lock);
  3343. rc = dsi_clk_update_parent(source_clks, &dsi_ctrl->clk_info.rcg_clks);
  3344. if (rc) {
  3345. DSI_CTRL_ERR(dsi_ctrl, "Failed to update link clk parent, rc=%d\n",
  3346. rc);
  3347. (void)dsi_clk_update_parent(&dsi_ctrl->clk_info.pll_op_clks,
  3348. &dsi_ctrl->clk_info.rcg_clks);
  3349. goto error;
  3350. }
  3351. dsi_ctrl->clk_info.pll_op_clks.byte_clk = source_clks->byte_clk;
  3352. dsi_ctrl->clk_info.pll_op_clks.pixel_clk = source_clks->pixel_clk;
  3353. DSI_CTRL_DEBUG(dsi_ctrl, "Source clocks are updated\n");
  3354. error:
  3355. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3356. return rc;
  3357. }
  3358. /**
  3359. * dsi_ctrl_setup_misr() - Setup frame MISR
  3360. * @dsi_ctrl: DSI controller handle.
  3361. * @enable: enable/disable MISR.
  3362. * @frame_count: Number of frames to accumulate MISR.
  3363. *
  3364. * Return: error code.
  3365. */
  3366. int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl,
  3367. bool enable,
  3368. u32 frame_count)
  3369. {
  3370. if (!dsi_ctrl) {
  3371. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3372. return -EINVAL;
  3373. }
  3374. if (!dsi_ctrl->hw.ops.setup_misr)
  3375. return 0;
  3376. mutex_lock(&dsi_ctrl->ctrl_lock);
  3377. dsi_ctrl->misr_enable = enable;
  3378. dsi_ctrl->hw.ops.setup_misr(&dsi_ctrl->hw,
  3379. dsi_ctrl->host_config.panel_mode,
  3380. enable, frame_count);
  3381. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3382. return 0;
  3383. }
  3384. /**
  3385. * dsi_ctrl_collect_misr() - Read frame MISR
  3386. * @dsi_ctrl: DSI controller handle.
  3387. *
  3388. * Return: MISR value.
  3389. */
  3390. u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl)
  3391. {
  3392. u32 misr;
  3393. if (!dsi_ctrl || !dsi_ctrl->hw.ops.collect_misr)
  3394. return 0;
  3395. misr = dsi_ctrl->hw.ops.collect_misr(&dsi_ctrl->hw,
  3396. dsi_ctrl->host_config.panel_mode);
  3397. if (!misr)
  3398. misr = dsi_ctrl->misr_cache;
  3399. DSI_CTRL_DEBUG(dsi_ctrl, "cached misr = %x, final = %x\n",
  3400. dsi_ctrl->misr_cache, misr);
  3401. return misr;
  3402. }
  3403. void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl, u32 idx,
  3404. bool mask_enable)
  3405. {
  3406. if (!dsi_ctrl || !dsi_ctrl->hw.ops.error_intr_ctrl
  3407. || !dsi_ctrl->hw.ops.clear_error_status) {
  3408. DSI_CTRL_ERR(dsi_ctrl, "Invalid params\n");
  3409. return;
  3410. }
  3411. /*
  3412. * Mask DSI error status interrupts and clear error status
  3413. * register
  3414. */
  3415. mutex_lock(&dsi_ctrl->ctrl_lock);
  3416. if (idx & BIT(DSI_ERR_INTR_ALL)) {
  3417. /*
  3418. * The behavior of mask_enable is different in ctrl register
  3419. * and mask register and hence mask_enable is manipulated for
  3420. * selective error interrupt masking vs total error interrupt
  3421. * masking.
  3422. */
  3423. dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, !mask_enable);
  3424. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  3425. DSI_ERROR_INTERRUPT_COUNT);
  3426. } else {
  3427. dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw, idx,
  3428. mask_enable);
  3429. dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
  3430. DSI_ERROR_INTERRUPT_COUNT);
  3431. }
  3432. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3433. }
  3434. /**
  3435. * dsi_ctrl_irq_update() - Put a irq vote to process DSI error
  3436. * interrupts at any time.
  3437. * @dsi_ctrl: DSI controller handle.
  3438. * @enable: variable to enable/disable irq
  3439. */
  3440. void dsi_ctrl_irq_update(struct dsi_ctrl *dsi_ctrl, bool enable)
  3441. {
  3442. if (!dsi_ctrl)
  3443. return;
  3444. mutex_lock(&dsi_ctrl->ctrl_lock);
  3445. if (enable)
  3446. dsi_ctrl_enable_status_interrupt(dsi_ctrl,
  3447. DSI_SINT_ERROR, NULL);
  3448. else
  3449. dsi_ctrl_disable_status_interrupt(dsi_ctrl,
  3450. DSI_SINT_ERROR);
  3451. mutex_unlock(&dsi_ctrl->ctrl_lock);
  3452. }
  3453. /**
  3454. * dsi_ctrl_wait4dynamic_refresh_done() - Poll for dynamci refresh
  3455. * done interrupt.
  3456. * @dsi_ctrl: DSI controller handle.
  3457. */
  3458. int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl)
  3459. {
  3460. int rc = 0;
  3461. if (!ctrl)
  3462. return 0;
  3463. mutex_lock(&ctrl->ctrl_lock);
  3464. if (ctrl->hw.ops.wait4dynamic_refresh_done)
  3465. rc = ctrl->hw.ops.wait4dynamic_refresh_done(&ctrl->hw);
  3466. mutex_unlock(&ctrl->ctrl_lock);
  3467. return rc;
  3468. }
  3469. /**
  3470. * dsi_ctrl_drv_register() - register platform driver for dsi controller
  3471. */
  3472. void dsi_ctrl_drv_register(void)
  3473. {
  3474. platform_driver_register(&dsi_ctrl_driver);
  3475. }
  3476. /**
  3477. * dsi_ctrl_drv_unregister() - unregister platform driver
  3478. */
  3479. void dsi_ctrl_drv_unregister(void)
  3480. {
  3481. platform_driver_unregister(&dsi_ctrl_driver);
  3482. }