msm_vidc_internal.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_VIDC_INTERNAL_H_
  6. #define _MSM_VIDC_INTERNAL_H_
  7. #include <linux/version.h>
  8. #include <linux/bits.h>
  9. #include <linux/workqueue.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/sync_file.h>
  12. #include <linux/dma-fence.h>
  13. #include <media/v4l2-dev.h>
  14. #include <media/v4l2-device.h>
  15. #include <media/v4l2-ioctl.h>
  16. #include <media/v4l2-event.h>
  17. #include <media/v4l2-ctrls.h>
  18. #include <media/v4l2-mem2mem.h>
  19. #include <media/videobuf2-core.h>
  20. #include <media/videobuf2-v4l2.h>
  21. #define MAX_NAME_LENGTH 128
  22. #define VENUS_VERSION_LENGTH 128
  23. #define MAX_MATRIX_COEFFS 9
  24. #define MAX_BIAS_COEFFS 3
  25. #define MAX_LIMIT_COEFFS 6
  26. #define MAX_DEBUGFS_NAME 50
  27. #define DEFAULT_HEIGHT 240
  28. #define DEFAULT_WIDTH 320
  29. #define DEFAULT_FPS 30
  30. #define MAXIMUM_VP9_FPS 60
  31. #define NRT_PRIORITY_OFFSET 2
  32. #define RT_DEC_DOWN_PRORITY_OFFSET 1
  33. #define MAX_SUPPORTED_INSTANCES 16
  34. #define DEFAULT_BSE_VPP_DELAY 2
  35. #define MAX_CAP_PARENTS 20
  36. #define MAX_CAP_CHILDREN 20
  37. #define DEFAULT_MAX_HOST_BUF_COUNT 64
  38. #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256
  39. #define BIT_DEPTH_8 (8 << 16 | 8)
  40. #define BIT_DEPTH_10 (10 << 16 | 10)
  41. #define CODED_FRAMES_PROGRESSIVE 0x0
  42. #define CODED_FRAMES_INTERLACE 0x1
  43. #define MAX_VP9D_INST_COUNT 6
  44. /* TODO: move below macros to waipio.c */
  45. #define MAX_ENH_LAYER_HB 3
  46. #define MAX_HEVC_ENH_LAYER_SLIDING_WINDOW 5
  47. #define MAX_AVC_ENH_LAYER_SLIDING_WINDOW 3
  48. #define MAX_AVC_ENH_LAYER_HYBRID_HP 5
  49. #define INVALID_DEFAULT_MARK_OR_USE_LTR -1
  50. #define MAX_SLICES_PER_FRAME 10
  51. #define MAX_SLICES_FRAME_RATE 60
  52. #define MAX_MB_SLICE_WIDTH 4096
  53. #define MAX_MB_SLICE_HEIGHT 2160
  54. #define MAX_BYTES_SLICE_WIDTH 1920
  55. #define MAX_BYTES_SLICE_HEIGHT 1088
  56. #define MIN_HEVC_SLICE_WIDTH 384
  57. #define MIN_AVC_SLICE_WIDTH 192
  58. #define MIN_SLICE_HEIGHT 128
  59. #define MAX_BITRATE_BOOST 25
  60. #define MAX_SUPPORTED_MIN_QUALITY 70
  61. #define MIN_CHROMA_QP_OFFSET -12
  62. #define MAX_CHROMA_QP_OFFSET 0
  63. #define INVALID_FD -1
  64. #define DCVS_WINDOW 16
  65. #define ENC_FPS_WINDOW 3
  66. #define DEC_FPS_WINDOW 10
  67. #define INPUT_TIMER_LIST_SIZE 30
  68. #define DEFAULT_COMPLEXITY 50
  69. #define INPUT_MPLANE V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
  70. #define OUTPUT_MPLANE V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
  71. #define INPUT_META_PLANE V4L2_BUF_TYPE_META_OUTPUT
  72. #define OUTPUT_META_PLANE V4L2_BUF_TYPE_META_CAPTURE
  73. #define VIDC_IFACEQ_MAX_PKT_SIZE 1024
  74. #define VIDC_IFACEQ_MED_PKT_SIZE 768
  75. #define VIDC_IFACEQ_MIN_PKT_SIZE 8
  76. #define VIDC_IFACEQ_VAR_SMALL_PKT_SIZE 100
  77. #define VIDC_IFACEQ_VAR_LARGE_PKT_SIZE 512
  78. #define VIDC_IFACEQ_VAR_HUGE_PKT_SIZE (1024*12)
  79. #define NUM_MBS_PER_SEC(__height, __width, __fps) \
  80. (NUM_MBS_PER_FRAME(__height, __width) * __fps)
  81. #define NUM_MBS_PER_FRAME(__height, __width) \
  82. ((ALIGN(__height, 16) / 16) * (ALIGN(__width, 16) / 16))
  83. #ifdef V4L2_CTRL_CLASS_CODEC
  84. #define IS_PRIV_CTRL(idx) ( \
  85. (V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_CODEC) && \
  86. V4L2_CTRL_DRIVER_PRIV(idx))
  87. #else
  88. #define IS_PRIV_CTRL(idx) ( \
  89. (V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_MPEG) && \
  90. V4L2_CTRL_DRIVER_PRIV(idx))
  91. #endif
  92. #define BUFFER_ALIGNMENT_SIZE(x) x
  93. #define NUM_MBS_360P (((480 + 15) >> 4) * ((360 + 15) >> 4))
  94. #define NUM_MBS_720P (((1280 + 15) >> 4) * ((720 + 15) >> 4))
  95. #define NUM_MBS_4k (((4096 + 15) >> 4) * ((2304 + 15) >> 4))
  96. #define MB_SIZE_IN_PIXEL (16 * 16)
  97. #define DB_H264_DISABLE_SLICE_BOUNDARY \
  98. V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
  99. #define DB_HEVC_DISABLE_SLICE_BOUNDARY \
  100. V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
  101. /*
  102. * Convert Q16 number into Integer and Fractional part upto 2 places.
  103. * Ex : 105752 / 65536 = 1.61; 1.61 in Q16 = 105752;
  104. * Integer part = 105752 / 65536 = 1;
  105. * Reminder = 105752 * 0xFFFF = 40216; Last 16 bits.
  106. * Fractional part = 40216 * 100 / 65536 = 61;
  107. * Now convert to FP(1, 61, 100).
  108. */
  109. #define Q16_INT(q) ((q) >> 16)
  110. #define Q16_FRAC(q) ((((q) & 0xFFFF) * 100) >> 16)
  111. /* define timeout values */
  112. #define HW_RESPONSE_TIMEOUT_VALUE (1000)
  113. #define SW_PC_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500)
  114. #define FW_UNLOAD_DELAY_VALUE (SW_PC_DELAY_VALUE + 1500)
  115. #define MAX_MAP_OUTPUT_COUNT 64
  116. #define MAX_DPB_COUNT 32
  117. /*
  118. * max dpb count in firmware = 16
  119. * each dpb: 4 words - <base_address, addr_offset, data_offset>
  120. * dpb list array size = 16 * 4
  121. * dpb payload size = 16 * 4 * 4
  122. */
  123. #define MAX_DPB_LIST_ARRAY_SIZE (16 * 4)
  124. #define MAX_DPB_LIST_PAYLOAD_SIZE (16 * 4 * 4)
  125. enum msm_vidc_domain_type {
  126. MSM_VIDC_ENCODER = BIT(0),
  127. MSM_VIDC_DECODER = BIT(1),
  128. };
  129. enum msm_vidc_codec_type {
  130. MSM_VIDC_H264 = BIT(0),
  131. MSM_VIDC_HEVC = BIT(1),
  132. MSM_VIDC_VP9 = BIT(2),
  133. MSM_VIDC_HEIC = BIT(3),
  134. MSM_VIDC_AV1 = BIT(4),
  135. };
  136. enum msm_vidc_colorformat_type {
  137. MSM_VIDC_FMT_NONE = 0,
  138. MSM_VIDC_FMT_NV12C = BIT(0),
  139. MSM_VIDC_FMT_NV12 = BIT(1),
  140. MSM_VIDC_FMT_NV21 = BIT(2),
  141. MSM_VIDC_FMT_TP10C = BIT(3),
  142. MSM_VIDC_FMT_P010 = BIT(4),
  143. MSM_VIDC_FMT_RGBA8888C = BIT(5),
  144. MSM_VIDC_FMT_RGBA8888 = BIT(6),
  145. };
  146. enum msm_vidc_buffer_type {
  147. MSM_VIDC_BUF_INPUT = 1,
  148. MSM_VIDC_BUF_OUTPUT = 2,
  149. MSM_VIDC_BUF_INPUT_META = 3,
  150. MSM_VIDC_BUF_OUTPUT_META = 4,
  151. MSM_VIDC_BUF_READ_ONLY = 5,
  152. MSM_VIDC_BUF_QUEUE = 6,
  153. MSM_VIDC_BUF_BIN = 7,
  154. MSM_VIDC_BUF_ARP = 8,
  155. MSM_VIDC_BUF_COMV = 9,
  156. MSM_VIDC_BUF_NON_COMV = 10,
  157. MSM_VIDC_BUF_LINE = 11,
  158. MSM_VIDC_BUF_DPB = 12,
  159. MSM_VIDC_BUF_PERSIST = 13,
  160. MSM_VIDC_BUF_VPSS = 14,
  161. MSM_VIDC_BUF_PARTIAL_DATA = 15,
  162. };
  163. /* always match with v4l2 flags V4L2_BUF_FLAG_* */
  164. enum msm_vidc_buffer_flags {
  165. MSM_VIDC_BUF_FLAG_KEYFRAME = 0x00000008,
  166. MSM_VIDC_BUF_FLAG_PFRAME = 0x00000010,
  167. MSM_VIDC_BUF_FLAG_BFRAME = 0x00000020,
  168. MSM_VIDC_BUF_FLAG_ERROR = 0x00000040,
  169. MSM_VIDC_BUF_FLAG_LAST = 0x00100000,
  170. MSM_VIDC_BUF_FLAG_CODECCONFIG = 0x01000000,
  171. MSM_VIDC_BUF_FLAG_SUBFRAME = 0x02000000,
  172. };
  173. enum msm_vidc_buffer_attributes {
  174. MSM_VIDC_ATTR_DEFERRED = BIT(0),
  175. MSM_VIDC_ATTR_READ_ONLY = BIT(1),
  176. MSM_VIDC_ATTR_PENDING_RELEASE = BIT(2),
  177. MSM_VIDC_ATTR_QUEUED = BIT(3),
  178. MSM_VIDC_ATTR_DEQUEUED = BIT(4),
  179. MSM_VIDC_ATTR_BUFFER_DONE = BIT(5),
  180. };
  181. enum msm_vidc_buffer_region {
  182. MSM_VIDC_REGION_NONE = 0,
  183. MSM_VIDC_NON_SECURE,
  184. MSM_VIDC_NON_SECURE_PIXEL,
  185. MSM_VIDC_SECURE_PIXEL,
  186. MSM_VIDC_SECURE_NONPIXEL,
  187. MSM_VIDC_SECURE_BITSTREAM,
  188. };
  189. enum msm_vidc_port_type {
  190. INPUT_PORT = 0,
  191. OUTPUT_PORT,
  192. INPUT_META_PORT,
  193. OUTPUT_META_PORT,
  194. PORT_NONE,
  195. MAX_PORT,
  196. };
  197. enum msm_vidc_stage_type {
  198. MSM_VIDC_STAGE_NONE = 0,
  199. MSM_VIDC_STAGE_1 = 1,
  200. MSM_VIDC_STAGE_2 = 2,
  201. };
  202. enum msm_vidc_pipe_type {
  203. MSM_VIDC_PIPE_NONE = 0,
  204. MSM_VIDC_PIPE_1 = 1,
  205. MSM_VIDC_PIPE_2 = 2,
  206. MSM_VIDC_PIPE_4 = 4,
  207. };
  208. enum msm_vidc_quality_mode {
  209. MSM_VIDC_MAX_QUALITY_MODE = 0x1,
  210. MSM_VIDC_POWER_SAVE_MODE = 0x2,
  211. };
  212. enum msm_vidc_color_primaries {
  213. MSM_VIDC_PRIMARIES_RESERVED = 0,
  214. MSM_VIDC_PRIMARIES_BT709 = 1,
  215. MSM_VIDC_PRIMARIES_UNSPECIFIED = 2,
  216. MSM_VIDC_PRIMARIES_BT470_SYSTEM_M = 4,
  217. MSM_VIDC_PRIMARIES_BT470_SYSTEM_BG = 5,
  218. MSM_VIDC_PRIMARIES_BT601_525 = 6,
  219. MSM_VIDC_PRIMARIES_SMPTE_ST240M = 7,
  220. MSM_VIDC_PRIMARIES_GENERIC_FILM = 8,
  221. MSM_VIDC_PRIMARIES_BT2020 = 9,
  222. MSM_VIDC_PRIMARIES_SMPTE_ST428_1 = 10,
  223. MSM_VIDC_PRIMARIES_SMPTE_RP431_2 = 11,
  224. MSM_VIDC_PRIMARIES_SMPTE_EG431_1 = 12,
  225. MSM_VIDC_PRIMARIES_SMPTE_EBU_TECH = 22,
  226. };
  227. enum msm_vidc_transfer_characteristics {
  228. MSM_VIDC_TRANSFER_RESERVED = 0,
  229. MSM_VIDC_TRANSFER_BT709 = 1,
  230. MSM_VIDC_TRANSFER_UNSPECIFIED = 2,
  231. MSM_VIDC_TRANSFER_BT470_SYSTEM_M = 4,
  232. MSM_VIDC_TRANSFER_BT470_SYSTEM_BG = 5,
  233. MSM_VIDC_TRANSFER_BT601_525_OR_625 = 6,
  234. MSM_VIDC_TRANSFER_SMPTE_ST240M = 7,
  235. MSM_VIDC_TRANSFER_LINEAR = 8,
  236. MSM_VIDC_TRANSFER_LOG_100_1 = 9,
  237. MSM_VIDC_TRANSFER_LOG_SQRT = 10,
  238. MSM_VIDC_TRANSFER_XVYCC = 11,
  239. MSM_VIDC_TRANSFER_BT1361_0 = 12,
  240. MSM_VIDC_TRANSFER_SRGB_SYCC = 13,
  241. MSM_VIDC_TRANSFER_BT2020_14 = 14,
  242. MSM_VIDC_TRANSFER_BT2020_15 = 15,
  243. MSM_VIDC_TRANSFER_SMPTE_ST2084_PQ = 16,
  244. MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17,
  245. MSM_VIDC_TRANSFER_BT2100_2_HLG = 18,
  246. };
  247. enum msm_vidc_matrix_coefficients {
  248. MSM_VIDC_MATRIX_COEFF_SRGB_SMPTE_ST428_1 = 0,
  249. MSM_VIDC_MATRIX_COEFF_BT709 = 1,
  250. MSM_VIDC_MATRIX_COEFF_UNSPECIFIED = 2,
  251. MSM_VIDC_MATRIX_COEFF_RESERVED = 3,
  252. MSM_VIDC_MATRIX_COEFF_FCC_TITLE_47 = 4,
  253. MSM_VIDC_MATRIX_COEFF_BT470_SYS_BG_OR_BT601_625 = 5,
  254. MSM_VIDC_MATRIX_COEFF_BT601_525_BT1358_525_OR_625 = 6,
  255. MSM_VIDC_MATRIX_COEFF_SMPTE_ST240 = 7,
  256. MSM_VIDC_MATRIX_COEFF_YCGCO = 8,
  257. MSM_VIDC_MATRIX_COEFF_BT2020_NON_CONSTANT = 9,
  258. MSM_VIDC_MATRIX_COEFF_BT2020_CONSTANT = 10,
  259. MSM_VIDC_MATRIX_COEFF_SMPTE_ST2085 = 11,
  260. MSM_VIDC_MATRIX_COEFF_SMPTE_CHROM_DERV_NON_CONSTANT = 12,
  261. MSM_VIDC_MATRIX_COEFF_SMPTE_CHROM_DERV_CONSTANT = 13,
  262. MSM_VIDC_MATRIX_COEFF_BT2100 = 14,
  263. };
  264. enum msm_vidc_preprocess_type {
  265. MSM_VIDC_PREPROCESS_NONE = BIT(0),
  266. MSM_VIDC_PREPROCESS_TYPE0 = BIT(1),
  267. };
  268. enum msm_vidc_core_capability_type {
  269. CORE_CAP_NONE = 0,
  270. ENC_CODECS,
  271. DEC_CODECS,
  272. MAX_SESSION_COUNT,
  273. MAX_NUM_720P_SESSIONS,
  274. MAX_NUM_1080P_SESSIONS,
  275. MAX_NUM_4K_SESSIONS,
  276. MAX_NUM_8K_SESSIONS,
  277. MAX_SECURE_SESSION_COUNT,
  278. MAX_LOAD,
  279. MAX_RT_MBPF,
  280. MAX_MBPF,
  281. MAX_MBPS,
  282. MAX_IMAGE_MBPF,
  283. MAX_MBPF_HQ,
  284. MAX_MBPS_HQ,
  285. MAX_MBPF_B_FRAME,
  286. MAX_MBPS_B_FRAME,
  287. MAX_MBPS_ALL_INTRA,
  288. MAX_ENH_LAYER_COUNT,
  289. NUM_VPP_PIPE,
  290. SW_PC,
  291. SW_PC_DELAY,
  292. FW_UNLOAD,
  293. FW_UNLOAD_DELAY,
  294. HW_RESPONSE_TIMEOUT,
  295. PREFIX_BUF_COUNT_PIX,
  296. PREFIX_BUF_SIZE_PIX,
  297. PREFIX_BUF_COUNT_NON_PIX,
  298. PREFIX_BUF_SIZE_NON_PIX,
  299. PAGEFAULT_NON_FATAL,
  300. PAGETABLE_CACHING,
  301. DCVS,
  302. DECODE_BATCH,
  303. DECODE_BATCH_TIMEOUT,
  304. STATS_TIMEOUT_MS,
  305. AV_SYNC_WINDOW_SIZE,
  306. CLK_FREQ_THRESHOLD,
  307. NON_FATAL_FAULTS,
  308. ENC_AUTO_FRAMERATE,
  309. MMRM,
  310. CORE_CAP_MAX,
  311. };
  312. /**
  313. * msm_vidc_prepare_dependency_list() api will prepare caps_list by looping over
  314. * enums(msm_vidc_inst_capability_type) from 0 to INST_CAP_MAX and arranges the
  315. * node in such a way that parents willbe at the front and dependent children
  316. * in the back.
  317. *
  318. * caps_list preparation may become CPU intensive task, so to save CPU cycles,
  319. * organize enum in proper order(root caps at the beginning and dependent caps
  320. * at back), so that during caps_list preparation num CPU cycles spent will reduce.
  321. *
  322. * Note: It will work, if enum kept at different places, but not efficient.
  323. */
  324. enum msm_vidc_inst_capability_type {
  325. INST_CAP_NONE = 0,
  326. /* place all metadata after this line
  327. * (Between INST_CAP_NONE and META_CAP_MAX)
  328. */
  329. META_SEQ_HDR_NAL,
  330. META_BITSTREAM_RESOLUTION,
  331. META_CROP_OFFSETS,
  332. META_DPB_MISR,
  333. META_OPB_MISR,
  334. META_INTERLACE,
  335. META_OUTBUF_FENCE,
  336. META_LTR_MARK_USE,
  337. META_TIMESTAMP,
  338. META_CONCEALED_MB_CNT,
  339. META_HIST_INFO,
  340. META_PICTURE_TYPE,
  341. META_SEI_MASTERING_DISP,
  342. META_SEI_CLL,
  343. META_HDR10PLUS,
  344. META_BUF_TAG,
  345. META_DPB_TAG_LIST,
  346. META_SUBFRAME_OUTPUT,
  347. META_ENC_QP_METADATA,
  348. META_DEC_QP_METADATA,
  349. META_MAX_NUM_REORDER_FRAMES,
  350. META_EVA_STATS,
  351. META_ROI_INFO,
  352. META_SALIENCY_INFO,
  353. META_TRANSCODING_STAT_INFO,
  354. META_CAP_MAX,
  355. /* end of metadata caps */
  356. FRAME_WIDTH,
  357. LOSSLESS_FRAME_WIDTH,
  358. SECURE_FRAME_WIDTH,
  359. FRAME_HEIGHT,
  360. LOSSLESS_FRAME_HEIGHT,
  361. SECURE_FRAME_HEIGHT,
  362. PIX_FMTS,
  363. MIN_BUFFERS_INPUT,
  364. MIN_BUFFERS_OUTPUT,
  365. MBPF,
  366. BATCH_MBPF,
  367. BATCH_FPS,
  368. LOSSLESS_MBPF,
  369. SECURE_MBPF,
  370. MBPS,
  371. POWER_SAVE_MBPS,
  372. CHECK_MBPS,
  373. FRAME_RATE,
  374. OPERATING_RATE,
  375. INPUT_RATE,
  376. TIMESTAMP_RATE,
  377. SCALE_FACTOR,
  378. MB_CYCLES_VSP,
  379. MB_CYCLES_VPP,
  380. MB_CYCLES_LP,
  381. MB_CYCLES_FW,
  382. MB_CYCLES_FW_VPP,
  383. SECURE_MODE,
  384. FENCE_ID,
  385. FENCE_FD,
  386. TS_REORDER,
  387. SLICE_INTERFACE,
  388. HFLIP,
  389. VFLIP,
  390. ROTATION,
  391. SUPER_FRAME,
  392. HEADER_MODE,
  393. PREPEND_SPSPPS_TO_IDR,
  394. WITHOUT_STARTCODE,
  395. NAL_LENGTH_FIELD,
  396. REQUEST_I_FRAME,
  397. BITRATE_MODE,
  398. LOSSLESS,
  399. FRAME_SKIP_MODE,
  400. FRAME_RC_ENABLE,
  401. GOP_CLOSURE,
  402. CSC,
  403. CSC_CUSTOM_MATRIX,
  404. USE_LTR,
  405. MARK_LTR,
  406. BASELAYER_PRIORITY,
  407. IR_TYPE,
  408. AU_DELIMITER,
  409. GRID,
  410. I_FRAME_MIN_QP,
  411. P_FRAME_MIN_QP,
  412. B_FRAME_MIN_QP,
  413. I_FRAME_MAX_QP,
  414. P_FRAME_MAX_QP,
  415. B_FRAME_MAX_QP,
  416. LAYER_TYPE,
  417. LAYER_ENABLE,
  418. L0_BR,
  419. L1_BR,
  420. L2_BR,
  421. L3_BR,
  422. L4_BR,
  423. L5_BR,
  424. LEVEL,
  425. HEVC_TIER,
  426. AV1_TIER,
  427. DISPLAY_DELAY_ENABLE,
  428. DISPLAY_DELAY,
  429. CONCEAL_COLOR_8BIT,
  430. CONCEAL_COLOR_10BIT,
  431. LF_MODE,
  432. LF_ALPHA,
  433. LF_BETA,
  434. SLICE_MAX_BYTES,
  435. SLICE_MAX_MB,
  436. MB_RC,
  437. CHROMA_QP_INDEX_OFFSET,
  438. PIPE,
  439. POC,
  440. CODED_FRAMES,
  441. BIT_DEPTH,
  442. CODEC_CONFIG,
  443. BITSTREAM_SIZE_OVERWRITE,
  444. THUMBNAIL_MODE,
  445. DEFAULT_HEADER,
  446. RAP_FRAME,
  447. SEQ_CHANGE_AT_SYNC_FRAME,
  448. QUALITY_MODE,
  449. PRIORITY,
  450. FIRMWARE_PRIORITY_OFFSET,
  451. CRITICAL_PRIORITY,
  452. RESERVE_DURATION,
  453. DPB_LIST,
  454. FILM_GRAIN,
  455. SUPER_BLOCK,
  456. DRAP,
  457. INPUT_METADATA_FD,
  458. INPUT_META_VIA_REQUEST,
  459. ENC_IP_CR,
  460. COMPLEXITY,
  461. /* place all root(no parent) enums before this line */
  462. PROFILE,
  463. ENH_LAYER_COUNT,
  464. BIT_RATE,
  465. LOWLATENCY_MODE,
  466. GOP_SIZE,
  467. B_FRAME,
  468. ALL_INTRA,
  469. MIN_QUALITY,
  470. CONTENT_ADAPTIVE_CODING,
  471. BLUR_TYPES,
  472. REQUEST_PREPROCESS,
  473. SLICE_MODE,
  474. /* place all intermittent(having both parent and child) enums before this line */
  475. MIN_FRAME_QP,
  476. MAX_FRAME_QP,
  477. I_FRAME_QP,
  478. P_FRAME_QP,
  479. B_FRAME_QP,
  480. TIME_DELTA_BASED_RC,
  481. CONSTANT_QUALITY,
  482. VBV_DELAY,
  483. PEAK_BITRATE,
  484. ENTROPY_MODE,
  485. TRANSFORM_8X8,
  486. STAGE,
  487. LTR_COUNT,
  488. IR_PERIOD,
  489. BITRATE_BOOST,
  490. BLUR_RESOLUTION,
  491. OUTPUT_ORDER,
  492. INPUT_BUF_HOST_MAX_COUNT,
  493. OUTPUT_BUF_HOST_MAX_COUNT,
  494. DELIVERY_MODE,
  495. /* place all leaf(no child) enums before this line */
  496. INST_CAP_MAX,
  497. };
  498. enum msm_vidc_inst_capability_flags {
  499. CAP_FLAG_NONE = 0,
  500. CAP_FLAG_DYNAMIC_ALLOWED = BIT(0),
  501. CAP_FLAG_MENU = BIT(1),
  502. CAP_FLAG_INPUT_PORT = BIT(2),
  503. CAP_FLAG_OUTPUT_PORT = BIT(3),
  504. CAP_FLAG_CLIENT_SET = BIT(4),
  505. CAP_FLAG_BITMASK = BIT(5),
  506. };
  507. struct msm_vidc_inst_cap {
  508. enum msm_vidc_inst_capability_type cap_id;
  509. s32 min;
  510. s32 max;
  511. u32 step_or_mask;
  512. s32 value;
  513. u32 v4l2_id;
  514. u32 hfi_id;
  515. enum msm_vidc_inst_capability_flags flags;
  516. enum msm_vidc_inst_capability_type parents[MAX_CAP_PARENTS];
  517. enum msm_vidc_inst_capability_type children[MAX_CAP_CHILDREN];
  518. int (*adjust)(void *inst,
  519. struct v4l2_ctrl *ctrl);
  520. int (*set)(void *inst,
  521. enum msm_vidc_inst_capability_type cap_id);
  522. };
  523. struct msm_vidc_inst_capability {
  524. enum msm_vidc_domain_type domain;
  525. enum msm_vidc_codec_type codec;
  526. struct msm_vidc_inst_cap cap[INST_CAP_MAX+1];
  527. };
  528. struct msm_vidc_core_capability {
  529. enum msm_vidc_core_capability_type type;
  530. u32 value;
  531. };
  532. struct msm_vidc_inst_cap_entry {
  533. /* list of struct msm_vidc_inst_cap_entry */
  534. struct list_head list;
  535. enum msm_vidc_inst_capability_type cap_id;
  536. };
  537. struct debug_buf_count {
  538. u64 etb;
  539. u64 ftb;
  540. u64 fbd;
  541. u64 ebd;
  542. };
  543. struct msm_vidc_statistics {
  544. struct debug_buf_count count;
  545. u64 data_size;
  546. u64 time_ms;
  547. };
  548. enum efuse_purpose {
  549. SKU_VERSION = 0,
  550. };
  551. enum sku_version {
  552. SKU_VERSION_0 = 0,
  553. SKU_VERSION_1,
  554. SKU_VERSION_2,
  555. };
  556. enum msm_vidc_ssr_trigger_type {
  557. SSR_ERR_FATAL = 1,
  558. SSR_SW_DIV_BY_ZERO,
  559. SSR_HW_WDOG_IRQ,
  560. };
  561. enum msm_vidc_stability_trigger_type {
  562. STABILITY_VCODEC_HUNG = 1,
  563. STABILITY_ENC_BUFFER_FULL,
  564. };
  565. enum msm_vidc_cache_op {
  566. MSM_VIDC_CACHE_CLEAN,
  567. MSM_VIDC_CACHE_INVALIDATE,
  568. MSM_VIDC_CACHE_CLEAN_INVALIDATE,
  569. };
  570. enum msm_vidc_dcvs_flags {
  571. MSM_VIDC_DCVS_INCR = BIT(0),
  572. MSM_VIDC_DCVS_DECR = BIT(1),
  573. };
  574. enum msm_vidc_clock_properties {
  575. CLOCK_PROP_HAS_SCALING = BIT(0),
  576. CLOCK_PROP_HAS_MEM_RETENTION = BIT(1),
  577. };
  578. enum profiling_points {
  579. FRAME_PROCESSING = 0,
  580. MAX_PROFILING_POINTS,
  581. };
  582. enum signal_session_response {
  583. SIGNAL_CMD_STOP_INPUT = 0,
  584. SIGNAL_CMD_STOP_OUTPUT,
  585. SIGNAL_CMD_CLOSE,
  586. MAX_SIGNAL,
  587. };
  588. #define HFI_MASK_QHDR_TX_TYPE 0xFF000000
  589. #define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
  590. #define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
  591. #define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
  592. #define HFI_Q_ID_HOST_TO_CTRL_CMD_Q 0x00
  593. #define HFI_Q_ID_CTRL_TO_HOST_MSG_Q 0x01
  594. #define HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q 0x02
  595. #define HFI_MASK_QHDR_STATUS 0x000000FF
  596. #define VIDC_IFACEQ_NUMQ 3
  597. #define VIDC_IFACEQ_CMDQ_IDX 0
  598. #define VIDC_IFACEQ_MSGQ_IDX 1
  599. #define VIDC_IFACEQ_DBGQ_IDX 2
  600. #define VIDC_IFACEQ_MAX_BUF_COUNT 50
  601. #define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
  602. #define VIDC_IFACEQ_DFLT_QHDR 0x01010000
  603. struct hfi_queue_table_header {
  604. u32 qtbl_version;
  605. u32 qtbl_size;
  606. u32 qtbl_qhdr0_offset;
  607. u32 qtbl_qhdr_size;
  608. u32 qtbl_num_q;
  609. u32 qtbl_num_active_q;
  610. void *device_addr;
  611. char name[256];
  612. };
  613. struct hfi_queue_header {
  614. u32 qhdr_status;
  615. u32 qhdr_start_addr;
  616. u32 qhdr_type;
  617. u32 qhdr_q_size;
  618. u32 qhdr_pkt_size;
  619. u32 qhdr_pkt_drop_cnt;
  620. u32 qhdr_rx_wm;
  621. u32 qhdr_tx_wm;
  622. u32 qhdr_rx_req;
  623. u32 qhdr_tx_req;
  624. u32 qhdr_rx_irq_status;
  625. u32 qhdr_tx_irq_status;
  626. u32 qhdr_read_idx;
  627. u32 qhdr_write_idx;
  628. };
  629. #define VIDC_IFACEQ_TABLE_SIZE (sizeof(struct hfi_queue_table_header) \
  630. + sizeof(struct hfi_queue_header) * VIDC_IFACEQ_NUMQ)
  631. #define VIDC_IFACEQ_QUEUE_SIZE (VIDC_IFACEQ_MAX_PKT_SIZE * \
  632. VIDC_IFACEQ_MAX_BUF_COUNT * VIDC_IFACE_MAX_PARALLEL_CLNTS)
  633. #define VIDC_IFACEQ_GET_QHDR_START_ADDR(ptr, i) \
  634. (void *)((ptr + sizeof(struct hfi_queue_table_header)) + \
  635. (i * sizeof(struct hfi_queue_header)))
  636. #define QDSS_SIZE 4096
  637. #define SFR_SIZE 4096
  638. #define QUEUE_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
  639. (VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ))
  640. #define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)
  641. #define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)
  642. #define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
  643. #define SHARED_QSIZE ALIGN(ALIGNED_SFR_SIZE + ALIGNED_QUEUE_SIZE + \
  644. ALIGNED_QDSS_SIZE, SZ_1M)
  645. #define TOTAL_QSIZE (SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE)
  646. struct profile_data {
  647. u64 start;
  648. u64 stop;
  649. u64 cumulative;
  650. char name[64];
  651. u32 sampling;
  652. u64 average;
  653. };
  654. struct msm_vidc_debug {
  655. struct profile_data pdata[MAX_PROFILING_POINTS];
  656. u32 profile;
  657. u32 samples;
  658. };
  659. struct msm_vidc_input_cr_data {
  660. struct list_head list;
  661. u32 index;
  662. u32 input_cr;
  663. };
  664. struct msm_vidc_session_idle {
  665. bool idle;
  666. u64 last_activity_time_ns;
  667. };
  668. struct msm_vidc_color_info {
  669. u32 colorspace;
  670. u32 ycbcr_enc;
  671. u32 xfer_func;
  672. u32 quantization;
  673. };
  674. struct msm_vidc_rectangle {
  675. u32 left;
  676. u32 top;
  677. u32 width;
  678. u32 height;
  679. };
  680. struct msm_vidc_subscription_params {
  681. u32 bitstream_resolution;
  682. u32 crop_offsets[2];
  683. u32 bit_depth;
  684. u32 coded_frames;
  685. u32 fw_min_count;
  686. u32 pic_order_cnt;
  687. u32 color_info;
  688. u32 profile;
  689. u32 level;
  690. u32 tier;
  691. u32 av1_film_grain_present;
  692. u32 av1_super_block_enabled;
  693. };
  694. struct msm_vidc_hfi_frame_info {
  695. u32 picture_type;
  696. u32 no_output;
  697. u32 cr;
  698. u32 cf;
  699. u32 data_corrupt;
  700. u32 overflow;
  701. u32 fence_id;
  702. };
  703. struct msm_vidc_decode_vpp_delay {
  704. bool enable;
  705. u32 size;
  706. };
  707. struct msm_vidc_decode_batch {
  708. bool enable;
  709. u32 size;
  710. struct delayed_work work;
  711. };
  712. enum msm_vidc_power_mode {
  713. VIDC_POWER_NORMAL = 0,
  714. VIDC_POWER_LOW,
  715. VIDC_POWER_TURBO,
  716. };
  717. struct vidc_bus_vote_data {
  718. enum msm_vidc_domain_type domain;
  719. enum msm_vidc_codec_type codec;
  720. enum msm_vidc_power_mode power_mode;
  721. u32 color_formats[2];
  722. int num_formats; /* 1 = DPB-OPB unified; 2 = split */
  723. int input_height, input_width, bitrate;
  724. int output_height, output_width;
  725. int rotation;
  726. int compression_ratio;
  727. int complexity_factor;
  728. int input_cr;
  729. u32 lcu_size;
  730. u32 fps;
  731. u32 work_mode;
  732. bool use_sys_cache;
  733. bool b_frames_enabled;
  734. u64 calc_bw_ddr;
  735. u64 calc_bw_llcc;
  736. u32 num_vpp_pipes;
  737. bool vpss_preprocessing_enabled;
  738. };
  739. struct msm_vidc_power {
  740. enum msm_vidc_power_mode power_mode;
  741. u32 buffer_counter;
  742. u32 min_threshold;
  743. u32 nom_threshold;
  744. u32 max_threshold;
  745. bool dcvs_mode;
  746. u32 dcvs_window;
  747. u64 min_freq;
  748. u64 curr_freq;
  749. u32 ddr_bw;
  750. u32 sys_cache_bw;
  751. u32 dcvs_flags;
  752. u32 fw_cr;
  753. u32 fw_cf;
  754. };
  755. struct msm_vidc_fence_context {
  756. char name[MAX_NAME_LENGTH];
  757. u64 ctx_num;
  758. u64 seq_num;
  759. };
  760. struct msm_vidc_fence {
  761. struct list_head list;
  762. struct dma_fence dma_fence;
  763. char name[MAX_NAME_LENGTH];
  764. spinlock_t lock;
  765. struct sync_file *sync_file;
  766. int fd;
  767. };
  768. struct msm_vidc_alloc {
  769. struct list_head list;
  770. enum msm_vidc_buffer_type type;
  771. enum msm_vidc_buffer_region region;
  772. u32 size;
  773. u8 secure:1;
  774. u8 map_kernel:1;
  775. struct dma_buf *dmabuf;
  776. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0))
  777. struct dma_buf_map dmabuf_map;
  778. #endif
  779. void *kvaddr;
  780. };
  781. struct msm_vidc_allocations {
  782. struct list_head list; // list of "struct msm_vidc_alloc"
  783. };
  784. struct msm_vidc_map {
  785. struct list_head list;
  786. enum msm_vidc_buffer_type type;
  787. enum msm_vidc_buffer_region region;
  788. struct dma_buf *dmabuf;
  789. u32 refcount;
  790. u64 device_addr;
  791. struct sg_table *table;
  792. struct dma_buf_attachment *attach;
  793. u32 skip_delayed_unmap:1;
  794. };
  795. struct msm_vidc_mappings {
  796. struct list_head list; // list of "struct msm_vidc_map"
  797. };
  798. struct msm_vidc_buffer {
  799. struct list_head list;
  800. enum msm_vidc_buffer_type type;
  801. u32 index;
  802. int fd;
  803. u32 buffer_size;
  804. u32 data_offset;
  805. u32 data_size;
  806. u64 device_addr;
  807. void *dmabuf;
  808. u32 flags;
  809. u64 timestamp;
  810. enum msm_vidc_buffer_attributes attr;
  811. u64 fence_id;
  812. };
  813. struct msm_vidc_buffers {
  814. struct list_head list; // list of "struct msm_vidc_buffer"
  815. u32 min_count;
  816. u32 extra_count;
  817. u32 actual_count;
  818. u32 size;
  819. bool reuse;
  820. };
  821. struct msm_vidc_sort {
  822. struct list_head list;
  823. s64 val;
  824. };
  825. struct msm_vidc_timestamp {
  826. struct msm_vidc_sort sort;
  827. u64 rank;
  828. };
  829. struct msm_vidc_timestamps {
  830. struct list_head list;
  831. u32 count;
  832. u64 rank;
  833. };
  834. struct msm_vidc_input_timer {
  835. struct list_head list;
  836. u64 time_us;
  837. };
  838. enum msm_vidc_allow {
  839. MSM_VIDC_DISALLOW = 0,
  840. MSM_VIDC_ALLOW,
  841. MSM_VIDC_DEFER,
  842. MSM_VIDC_DISCARD,
  843. MSM_VIDC_IGNORE,
  844. };
  845. enum response_work_type {
  846. RESP_WORK_INPUT_PSC = 1,
  847. RESP_WORK_OUTPUT_PSC,
  848. RESP_WORK_LAST_FLAG,
  849. };
  850. struct response_work {
  851. struct list_head list;
  852. enum response_work_type type;
  853. void *data;
  854. u32 data_size;
  855. };
  856. struct msm_vidc_ssr {
  857. bool trigger;
  858. enum msm_vidc_ssr_trigger_type ssr_type;
  859. u32 sub_client_id;
  860. u32 test_addr;
  861. };
  862. struct msm_vidc_stability {
  863. enum msm_vidc_stability_trigger_type stability_type;
  864. u32 sub_client_id;
  865. u32 value;
  866. };
  867. struct msm_vidc_sfr {
  868. u32 bufSize;
  869. u8 rg_data[1];
  870. };
  871. #define call_mem_op(c, op, ...) \
  872. (((c) && (c)->mem_ops && (c)->mem_ops->op) ? \
  873. ((c)->mem_ops->op(__VA_ARGS__)) : 0)
  874. struct msm_vidc_memory_ops {
  875. int (*allocate)(void *inst, struct msm_vidc_buffer *mbuf);
  876. int (*dma_map)(void *inst, struct msm_vidc_buffer *mbuf);
  877. int (*dma_unmap)(void *inst, struct msm_vidc_buffer *mbuf);
  878. int (*free)(void *inst, struct msm_vidc_buffer *mbuf);
  879. int (*cache_op)(void *inst, struct msm_vidc_buffer *mbuf,
  880. enum msm_vidc_cache_op cache_op);
  881. };
  882. #endif // _MSM_VIDC_INTERNAL_H_