dp_tx.c 112 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. }
  199. /* Add the tso segment into the free list*/
  200. dp_tx_tso_desc_free(soc,
  201. tx_desc->pool_id, tx_desc->tso_desc);
  202. tx_desc->tso_desc = NULL;
  203. }
  204. }
  205. #else
  206. static void dp_tx_tso_unmap_segment(
  207. struct dp_soc *soc,
  208. struct qdf_tso_seg_elem_t *seg_desc,
  209. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  210. {
  211. }
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. }
  216. #endif
  217. /**
  218. * dp_tx_desc_release() - Release Tx Descriptor
  219. * @tx_desc : Tx Descriptor
  220. * @desc_pool_id: Descriptor Pool ID
  221. *
  222. * Deallocate all resources attached to Tx descriptor and free the Tx
  223. * descriptor.
  224. *
  225. * Return:
  226. */
  227. static void
  228. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  229. {
  230. struct dp_pdev *pdev = tx_desc->pdev;
  231. struct dp_soc *soc;
  232. uint8_t comp_status = 0;
  233. qdf_assert(pdev);
  234. soc = pdev->soc;
  235. if (tx_desc->frm_type == dp_tx_frm_tso)
  236. dp_tx_tso_desc_release(soc, tx_desc);
  237. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  238. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  239. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  240. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  241. dp_tx_outstanding_dec(pdev);
  242. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  243. qdf_atomic_dec(&pdev->num_tx_exception);
  244. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  245. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  246. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  247. soc->hal_soc);
  248. else
  249. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  251. "Tx Completion Release desc %d status %d outstanding %d",
  252. tx_desc->id, comp_status,
  253. qdf_atomic_read(&pdev->num_tx_outstanding));
  254. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  255. return;
  256. }
  257. /**
  258. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  259. * @vdev: DP vdev Handle
  260. * @nbuf: skb
  261. * @msdu_info: msdu_info required to create HTT metadata
  262. *
  263. * Prepares and fills HTT metadata in the frame pre-header for special frames
  264. * that should be transmitted using varying transmit parameters.
  265. * There are 2 VDEV modes that currently needs this special metadata -
  266. * 1) Mesh Mode
  267. * 2) DSRC Mode
  268. *
  269. * Return: HTT metadata size
  270. *
  271. */
  272. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  273. struct dp_tx_msdu_info_s *msdu_info)
  274. {
  275. uint32_t *meta_data = msdu_info->meta_data;
  276. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  277. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  278. uint8_t htt_desc_size;
  279. /* Size rounded of multiple of 8 bytes */
  280. uint8_t htt_desc_size_aligned;
  281. uint8_t *hdr = NULL;
  282. /*
  283. * Metadata - HTT MSDU Extension header
  284. */
  285. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  286. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  287. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  288. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  289. meta_data[0])) {
  290. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  291. htt_desc_size_aligned)) {
  292. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  293. htt_desc_size_aligned);
  294. if (!nbuf) {
  295. /*
  296. * qdf_nbuf_realloc_headroom won't do skb_clone
  297. * as skb_realloc_headroom does. so, no free is
  298. * needed here.
  299. */
  300. DP_STATS_INC(vdev,
  301. tx_i.dropped.headroom_insufficient,
  302. 1);
  303. qdf_print(" %s[%d] skb_realloc_headroom failed",
  304. __func__, __LINE__);
  305. return 0;
  306. }
  307. }
  308. /* Fill and add HTT metaheader */
  309. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  310. if (!hdr) {
  311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  312. "Error in filling HTT metadata");
  313. return 0;
  314. }
  315. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  316. } else if (vdev->opmode == wlan_op_mode_ocb) {
  317. /* Todo - Add support for DSRC */
  318. }
  319. return htt_desc_size_aligned;
  320. }
  321. /**
  322. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  323. * @tso_seg: TSO segment to process
  324. * @ext_desc: Pointer to MSDU extension descriptor
  325. *
  326. * Return: void
  327. */
  328. #if defined(FEATURE_TSO)
  329. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  330. void *ext_desc)
  331. {
  332. uint8_t num_frag;
  333. uint32_t tso_flags;
  334. /*
  335. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  336. * tcp_flag_mask
  337. *
  338. * Checksum enable flags are set in TCL descriptor and not in Extension
  339. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  340. */
  341. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  342. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  343. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  344. tso_seg->tso_flags.ip_len);
  345. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  346. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  347. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  348. uint32_t lo = 0;
  349. uint32_t hi = 0;
  350. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  351. (tso_seg->tso_frags[num_frag].length));
  352. qdf_dmaaddr_to_32s(
  353. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  354. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  355. tso_seg->tso_frags[num_frag].length);
  356. }
  357. return;
  358. }
  359. #else
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. return;
  364. }
  365. #endif
  366. #if defined(FEATURE_TSO)
  367. /**
  368. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  369. * allocated and free them
  370. *
  371. * @soc: soc handle
  372. * @free_seg: list of tso segments
  373. * @msdu_info: msdu descriptor
  374. *
  375. * Return - void
  376. */
  377. static void dp_tx_free_tso_seg_list(
  378. struct dp_soc *soc,
  379. struct qdf_tso_seg_elem_t *free_seg,
  380. struct dp_tx_msdu_info_s *msdu_info)
  381. {
  382. struct qdf_tso_seg_elem_t *next_seg;
  383. while (free_seg) {
  384. next_seg = free_seg->next;
  385. dp_tx_tso_desc_free(soc,
  386. msdu_info->tx_queue.desc_pool_id,
  387. free_seg);
  388. free_seg = next_seg;
  389. }
  390. }
  391. /**
  392. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  393. * allocated and free them
  394. *
  395. * @soc: soc handle
  396. * @free_num_seg: list of tso number segments
  397. * @msdu_info: msdu descriptor
  398. * Return - void
  399. */
  400. static void dp_tx_free_tso_num_seg_list(
  401. struct dp_soc *soc,
  402. struct qdf_tso_num_seg_elem_t *free_num_seg,
  403. struct dp_tx_msdu_info_s *msdu_info)
  404. {
  405. struct qdf_tso_num_seg_elem_t *next_num_seg;
  406. while (free_num_seg) {
  407. next_num_seg = free_num_seg->next;
  408. dp_tso_num_seg_free(soc,
  409. msdu_info->tx_queue.desc_pool_id,
  410. free_num_seg);
  411. free_num_seg = next_num_seg;
  412. }
  413. }
  414. /**
  415. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  416. * do dma unmap for each segment
  417. *
  418. * @soc: soc handle
  419. * @free_seg: list of tso segments
  420. * @num_seg_desc: tso number segment descriptor
  421. *
  422. * Return - void
  423. */
  424. static void dp_tx_unmap_tso_seg_list(
  425. struct dp_soc *soc,
  426. struct qdf_tso_seg_elem_t *free_seg,
  427. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  428. {
  429. struct qdf_tso_seg_elem_t *next_seg;
  430. if (qdf_unlikely(!num_seg_desc)) {
  431. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  432. return;
  433. }
  434. while (free_seg) {
  435. next_seg = free_seg->next;
  436. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  437. free_seg = next_seg;
  438. }
  439. }
  440. /**
  441. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  442. * free the tso segments descriptor and
  443. * tso num segments descriptor
  444. *
  445. * @soc: soc handle
  446. * @msdu_info: msdu descriptor
  447. * @tso_seg_unmap: flag to show if dma unmap is necessary
  448. *
  449. * Return - void
  450. */
  451. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  452. struct dp_tx_msdu_info_s *msdu_info,
  453. bool tso_seg_unmap)
  454. {
  455. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  456. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  457. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  458. tso_info->tso_num_seg_list;
  459. /* do dma unmap for each segment */
  460. if (tso_seg_unmap)
  461. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  462. /* free all tso number segment descriptor though looks only have 1 */
  463. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  464. /* free all tso segment descriptor */
  465. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  466. }
  467. /**
  468. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  469. * @vdev: virtual device handle
  470. * @msdu: network buffer
  471. * @msdu_info: meta data associated with the msdu
  472. *
  473. * Return: QDF_STATUS_SUCCESS success
  474. */
  475. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  476. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  477. {
  478. struct qdf_tso_seg_elem_t *tso_seg;
  479. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  480. struct dp_soc *soc = vdev->pdev->soc;
  481. struct qdf_tso_info_t *tso_info;
  482. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  483. tso_info = &msdu_info->u.tso_info;
  484. tso_info->curr_seg = NULL;
  485. tso_info->tso_seg_list = NULL;
  486. tso_info->num_segs = num_seg;
  487. msdu_info->frm_type = dp_tx_frm_tso;
  488. tso_info->tso_num_seg_list = NULL;
  489. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  490. while (num_seg) {
  491. tso_seg = dp_tx_tso_desc_alloc(
  492. soc, msdu_info->tx_queue.desc_pool_id);
  493. if (tso_seg) {
  494. tso_seg->next = tso_info->tso_seg_list;
  495. tso_info->tso_seg_list = tso_seg;
  496. num_seg--;
  497. } else {
  498. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  499. __func__);
  500. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  501. return QDF_STATUS_E_NOMEM;
  502. }
  503. }
  504. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  505. tso_num_seg = dp_tso_num_seg_alloc(soc,
  506. msdu_info->tx_queue.desc_pool_id);
  507. if (tso_num_seg) {
  508. tso_num_seg->next = tso_info->tso_num_seg_list;
  509. tso_info->tso_num_seg_list = tso_num_seg;
  510. } else {
  511. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  512. __func__);
  513. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  514. return QDF_STATUS_E_NOMEM;
  515. }
  516. msdu_info->num_seg =
  517. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  518. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  519. msdu_info->num_seg);
  520. if (!(msdu_info->num_seg)) {
  521. /*
  522. * Free allocated TSO seg desc and number seg desc,
  523. * do unmap for segments if dma map has done.
  524. */
  525. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  526. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  527. return QDF_STATUS_E_INVAL;
  528. }
  529. tso_info->curr_seg = tso_info->tso_seg_list;
  530. return QDF_STATUS_SUCCESS;
  531. }
  532. #else
  533. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  534. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  535. {
  536. return QDF_STATUS_E_NOMEM;
  537. }
  538. #endif
  539. /**
  540. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  541. * @vdev: DP Vdev handle
  542. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  543. * @desc_pool_id: Descriptor Pool ID
  544. *
  545. * Return:
  546. */
  547. static
  548. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  549. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  550. {
  551. uint8_t i;
  552. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  553. struct dp_tx_seg_info_s *seg_info;
  554. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  555. struct dp_soc *soc = vdev->pdev->soc;
  556. /* Allocate an extension descriptor */
  557. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  558. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  559. if (!msdu_ext_desc) {
  560. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  561. return NULL;
  562. }
  563. if (msdu_info->exception_fw &&
  564. qdf_unlikely(vdev->mesh_vdev)) {
  565. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  566. &msdu_info->meta_data[0],
  567. sizeof(struct htt_tx_msdu_desc_ext2_t));
  568. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  569. }
  570. switch (msdu_info->frm_type) {
  571. case dp_tx_frm_sg:
  572. case dp_tx_frm_me:
  573. case dp_tx_frm_raw:
  574. seg_info = msdu_info->u.sg_info.curr_seg;
  575. /* Update the buffer pointers in MSDU Extension Descriptor */
  576. for (i = 0; i < seg_info->frag_cnt; i++) {
  577. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  578. seg_info->frags[i].paddr_lo,
  579. seg_info->frags[i].paddr_hi,
  580. seg_info->frags[i].len);
  581. }
  582. break;
  583. case dp_tx_frm_tso:
  584. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  585. &cached_ext_desc[0]);
  586. break;
  587. default:
  588. break;
  589. }
  590. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  591. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  592. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  593. msdu_ext_desc->vaddr);
  594. return msdu_ext_desc;
  595. }
  596. /**
  597. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  598. *
  599. * @skb: skb to be traced
  600. * @msdu_id: msdu_id of the packet
  601. * @vdev_id: vdev_id of the packet
  602. *
  603. * Return: None
  604. */
  605. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  606. uint8_t vdev_id)
  607. {
  608. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  609. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  610. DPTRACE(qdf_dp_trace_ptr(skb,
  611. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  612. QDF_TRACE_DEFAULT_PDEV_ID,
  613. qdf_nbuf_data_addr(skb),
  614. sizeof(qdf_nbuf_data(skb)),
  615. msdu_id, vdev_id));
  616. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  617. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  618. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  619. msdu_id, QDF_TX));
  620. }
  621. /**
  622. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  623. * @vdev: DP vdev handle
  624. * @nbuf: skb
  625. * @desc_pool_id: Descriptor pool ID
  626. * @meta_data: Metadata to the fw
  627. * @tx_exc_metadata: Handle that holds exception path metadata
  628. * Allocate and prepare Tx descriptor with msdu information.
  629. *
  630. * Return: Pointer to Tx Descriptor on success,
  631. * NULL on failure
  632. */
  633. static
  634. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  635. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  636. struct dp_tx_msdu_info_s *msdu_info,
  637. struct cdp_tx_exception_metadata *tx_exc_metadata)
  638. {
  639. uint8_t align_pad;
  640. uint8_t is_exception = 0;
  641. uint8_t htt_hdr_size;
  642. qdf_ether_header_t *eh;
  643. struct dp_tx_desc_s *tx_desc;
  644. struct dp_pdev *pdev = vdev->pdev;
  645. struct dp_soc *soc = pdev->soc;
  646. if (dp_tx_limit_check(vdev))
  647. return NULL;
  648. /* Allocate software Tx descriptor */
  649. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  650. if (qdf_unlikely(!tx_desc)) {
  651. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  652. return NULL;
  653. }
  654. dp_tx_outstanding_inc(pdev);
  655. /* Initialize the SW tx descriptor */
  656. tx_desc->nbuf = nbuf;
  657. tx_desc->frm_type = dp_tx_frm_std;
  658. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  659. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  660. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  661. tx_desc->vdev = vdev;
  662. tx_desc->pdev = pdev;
  663. tx_desc->msdu_ext_desc = NULL;
  664. tx_desc->pkt_offset = 0;
  665. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  666. if (qdf_unlikely(vdev->multipass_en)) {
  667. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  668. goto failure;
  669. }
  670. /*
  671. * For special modes (vdev_type == ocb or mesh), data frames should be
  672. * transmitted using varying transmit parameters (tx spec) which include
  673. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  674. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  675. * These frames are sent as exception packets to firmware.
  676. *
  677. * HW requirement is that metadata should always point to a
  678. * 8-byte aligned address. So we add alignment pad to start of buffer.
  679. * HTT Metadata should be ensured to be multiple of 8-bytes,
  680. * to get 8-byte aligned start address along with align_pad added
  681. *
  682. * |-----------------------------|
  683. * | |
  684. * |-----------------------------| <-----Buffer Pointer Address given
  685. * | | ^ in HW descriptor (aligned)
  686. * | HTT Metadata | |
  687. * | | |
  688. * | | | Packet Offset given in descriptor
  689. * | | |
  690. * |-----------------------------| |
  691. * | Alignment Pad | v
  692. * |-----------------------------| <----- Actual buffer start address
  693. * | SKB Data | (Unaligned)
  694. * | |
  695. * | |
  696. * | |
  697. * | |
  698. * | |
  699. * |-----------------------------|
  700. */
  701. if (qdf_unlikely((msdu_info->exception_fw)) ||
  702. (vdev->opmode == wlan_op_mode_ocb) ||
  703. (tx_exc_metadata &&
  704. tx_exc_metadata->is_tx_sniffer)) {
  705. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  706. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  707. DP_STATS_INC(vdev,
  708. tx_i.dropped.headroom_insufficient, 1);
  709. goto failure;
  710. }
  711. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  713. "qdf_nbuf_push_head failed");
  714. goto failure;
  715. }
  716. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  717. msdu_info);
  718. if (htt_hdr_size == 0)
  719. goto failure;
  720. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  721. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  722. is_exception = 1;
  723. }
  724. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  725. qdf_nbuf_map(soc->osdev, nbuf,
  726. QDF_DMA_TO_DEVICE))) {
  727. /* Handle failure */
  728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  729. "qdf_nbuf_map failed");
  730. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  731. goto failure;
  732. }
  733. if (qdf_unlikely(vdev->nawds_enabled)) {
  734. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  735. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  736. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  737. is_exception = 1;
  738. }
  739. }
  740. #if !TQM_BYPASS_WAR
  741. if (is_exception || tx_exc_metadata)
  742. #endif
  743. {
  744. /* Temporary WAR due to TQM VP issues */
  745. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  746. qdf_atomic_inc(&pdev->num_tx_exception);
  747. }
  748. return tx_desc;
  749. failure:
  750. dp_tx_desc_release(tx_desc, desc_pool_id);
  751. return NULL;
  752. }
  753. /**
  754. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  755. * @vdev: DP vdev handle
  756. * @nbuf: skb
  757. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  758. * @desc_pool_id : Descriptor Pool ID
  759. *
  760. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  761. * information. For frames wth fragments, allocate and prepare
  762. * an MSDU extension descriptor
  763. *
  764. * Return: Pointer to Tx Descriptor on success,
  765. * NULL on failure
  766. */
  767. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  768. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  769. uint8_t desc_pool_id)
  770. {
  771. struct dp_tx_desc_s *tx_desc;
  772. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  773. struct dp_pdev *pdev = vdev->pdev;
  774. struct dp_soc *soc = pdev->soc;
  775. if (dp_tx_limit_check(vdev))
  776. return NULL;
  777. /* Allocate software Tx descriptor */
  778. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  779. if (!tx_desc) {
  780. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  781. return NULL;
  782. }
  783. dp_tx_outstanding_inc(pdev);
  784. /* Initialize the SW tx descriptor */
  785. tx_desc->nbuf = nbuf;
  786. tx_desc->frm_type = msdu_info->frm_type;
  787. tx_desc->tx_encap_type = vdev->tx_encap_type;
  788. tx_desc->vdev = vdev;
  789. tx_desc->pdev = pdev;
  790. tx_desc->pkt_offset = 0;
  791. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  792. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  793. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  794. /* Handle scattered frames - TSO/SG/ME */
  795. /* Allocate and prepare an extension descriptor for scattered frames */
  796. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  797. if (!msdu_ext_desc) {
  798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  799. "%s Tx Extension Descriptor Alloc Fail",
  800. __func__);
  801. goto failure;
  802. }
  803. #if TQM_BYPASS_WAR
  804. /* Temporary WAR due to TQM VP issues */
  805. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  806. qdf_atomic_inc(&pdev->num_tx_exception);
  807. #endif
  808. if (qdf_unlikely(msdu_info->exception_fw))
  809. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  810. tx_desc->msdu_ext_desc = msdu_ext_desc;
  811. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  812. return tx_desc;
  813. failure:
  814. dp_tx_desc_release(tx_desc, desc_pool_id);
  815. return NULL;
  816. }
  817. /**
  818. * dp_tx_prepare_raw() - Prepare RAW packet TX
  819. * @vdev: DP vdev handle
  820. * @nbuf: buffer pointer
  821. * @seg_info: Pointer to Segment info Descriptor to be prepared
  822. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  823. * descriptor
  824. *
  825. * Return:
  826. */
  827. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  828. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  829. {
  830. qdf_nbuf_t curr_nbuf = NULL;
  831. uint16_t total_len = 0;
  832. qdf_dma_addr_t paddr;
  833. int32_t i;
  834. int32_t mapped_buf_num = 0;
  835. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  836. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  837. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  838. /* Continue only if frames are of DATA type */
  839. if (!DP_FRAME_IS_DATA(qos_wh)) {
  840. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  842. "Pkt. recd is of not data type");
  843. goto error;
  844. }
  845. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  846. if (vdev->raw_mode_war &&
  847. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  848. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  849. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  850. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  851. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  852. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  853. QDF_DMA_TO_DEVICE)) {
  854. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  855. "%s dma map error ", __func__);
  856. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  857. mapped_buf_num = i;
  858. goto error;
  859. }
  860. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  861. seg_info->frags[i].paddr_lo = paddr;
  862. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  863. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  864. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  865. total_len += qdf_nbuf_len(curr_nbuf);
  866. }
  867. seg_info->frag_cnt = i;
  868. seg_info->total_len = total_len;
  869. seg_info->next = NULL;
  870. sg_info->curr_seg = seg_info;
  871. msdu_info->frm_type = dp_tx_frm_raw;
  872. msdu_info->num_seg = 1;
  873. return nbuf;
  874. error:
  875. i = 0;
  876. while (nbuf) {
  877. curr_nbuf = nbuf;
  878. if (i < mapped_buf_num) {
  879. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  880. i++;
  881. }
  882. nbuf = qdf_nbuf_next(nbuf);
  883. qdf_nbuf_free(curr_nbuf);
  884. }
  885. return NULL;
  886. }
  887. /**
  888. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  889. * @soc: DP soc handle
  890. * @nbuf: Buffer pointer
  891. *
  892. * unmap the chain of nbufs that belong to this RAW frame.
  893. *
  894. * Return: None
  895. */
  896. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  897. qdf_nbuf_t nbuf)
  898. {
  899. qdf_nbuf_t cur_nbuf = nbuf;
  900. do {
  901. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  902. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  903. } while (cur_nbuf);
  904. }
  905. /**
  906. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  907. * @soc: DP Soc Handle
  908. * @vdev: DP vdev handle
  909. * @tx_desc: Tx Descriptor Handle
  910. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  911. * @fw_metadata: Metadata to send to Target Firmware along with frame
  912. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  913. * @tx_exc_metadata: Handle that holds exception path meta data
  914. *
  915. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  916. * from software Tx descriptor
  917. *
  918. * Return:
  919. */
  920. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  921. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  922. uint16_t fw_metadata, uint8_t ring_id,
  923. struct cdp_tx_exception_metadata
  924. *tx_exc_metadata)
  925. {
  926. uint8_t type;
  927. uint16_t length;
  928. void *hal_tx_desc, *hal_tx_desc_cached;
  929. qdf_dma_addr_t dma_addr;
  930. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  931. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  932. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  933. tx_exc_metadata->sec_type : vdev->sec_type);
  934. /* Return Buffer Manager ID */
  935. uint8_t bm_id = ring_id;
  936. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  937. hal_tx_desc_cached = (void *) cached_desc;
  938. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  939. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  940. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  941. type = HAL_TX_BUF_TYPE_EXT_DESC;
  942. dma_addr = tx_desc->msdu_ext_desc->paddr;
  943. } else {
  944. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  945. type = HAL_TX_BUF_TYPE_BUFFER;
  946. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  947. }
  948. qdf_assert_always(dma_addr);
  949. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  950. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  951. dma_addr, bm_id, tx_desc->id,
  952. type, soc->hal_soc);
  953. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  954. return QDF_STATUS_E_RESOURCES;
  955. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  956. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  957. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  958. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  959. vdev->pdev->lmac_id);
  960. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  961. vdev->search_type);
  962. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  963. vdev->bss_ast_idx);
  964. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  965. vdev->dscp_tid_map_id);
  966. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  967. sec_type_map[sec_type]);
  968. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  969. (vdev->bss_ast_hash & 0xF));
  970. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  971. length, type, (uint64_t)dma_addr,
  972. tx_desc->pkt_offset, tx_desc->id);
  973. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  974. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  975. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  976. vdev->hal_desc_addr_search_flags);
  977. /* verify checksum offload configuration*/
  978. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  979. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  980. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  981. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  982. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  983. }
  984. if (tid != HTT_TX_EXT_TID_INVALID)
  985. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  986. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  987. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  988. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  989. /* Sync cached descriptor with HW */
  990. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  991. if (!hal_tx_desc) {
  992. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  993. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  994. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  995. return QDF_STATUS_E_RESOURCES;
  996. }
  997. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  998. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  999. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1000. return QDF_STATUS_SUCCESS;
  1001. }
  1002. /**
  1003. * dp_cce_classify() - Classify the frame based on CCE rules
  1004. * @vdev: DP vdev handle
  1005. * @nbuf: skb
  1006. *
  1007. * Classify frames based on CCE rules
  1008. * Return: bool( true if classified,
  1009. * else false)
  1010. */
  1011. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1012. {
  1013. qdf_ether_header_t *eh = NULL;
  1014. uint16_t ether_type;
  1015. qdf_llc_t *llcHdr;
  1016. qdf_nbuf_t nbuf_clone = NULL;
  1017. qdf_dot3_qosframe_t *qos_wh = NULL;
  1018. /* for mesh packets don't do any classification */
  1019. if (qdf_unlikely(vdev->mesh_vdev))
  1020. return false;
  1021. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1022. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1023. ether_type = eh->ether_type;
  1024. llcHdr = (qdf_llc_t *)(nbuf->data +
  1025. sizeof(qdf_ether_header_t));
  1026. } else {
  1027. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1028. /* For encrypted packets don't do any classification */
  1029. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1030. return false;
  1031. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1032. if (qdf_unlikely(
  1033. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1034. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1035. ether_type = *(uint16_t *)(nbuf->data
  1036. + QDF_IEEE80211_4ADDR_HDR_LEN
  1037. + sizeof(qdf_llc_t)
  1038. - sizeof(ether_type));
  1039. llcHdr = (qdf_llc_t *)(nbuf->data +
  1040. QDF_IEEE80211_4ADDR_HDR_LEN);
  1041. } else {
  1042. ether_type = *(uint16_t *)(nbuf->data
  1043. + QDF_IEEE80211_3ADDR_HDR_LEN
  1044. + sizeof(qdf_llc_t)
  1045. - sizeof(ether_type));
  1046. llcHdr = (qdf_llc_t *)(nbuf->data +
  1047. QDF_IEEE80211_3ADDR_HDR_LEN);
  1048. }
  1049. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1050. && (ether_type ==
  1051. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1052. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1053. return true;
  1054. }
  1055. }
  1056. return false;
  1057. }
  1058. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1059. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1060. sizeof(*llcHdr));
  1061. nbuf_clone = qdf_nbuf_clone(nbuf);
  1062. if (qdf_unlikely(nbuf_clone)) {
  1063. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1064. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1065. qdf_nbuf_pull_head(nbuf_clone,
  1066. sizeof(qdf_net_vlanhdr_t));
  1067. }
  1068. }
  1069. } else {
  1070. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1071. nbuf_clone = qdf_nbuf_clone(nbuf);
  1072. if (qdf_unlikely(nbuf_clone)) {
  1073. qdf_nbuf_pull_head(nbuf_clone,
  1074. sizeof(qdf_net_vlanhdr_t));
  1075. }
  1076. }
  1077. }
  1078. if (qdf_unlikely(nbuf_clone))
  1079. nbuf = nbuf_clone;
  1080. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1081. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1082. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1083. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1084. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1085. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1086. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1087. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1088. if (qdf_unlikely(nbuf_clone))
  1089. qdf_nbuf_free(nbuf_clone);
  1090. return true;
  1091. }
  1092. if (qdf_unlikely(nbuf_clone))
  1093. qdf_nbuf_free(nbuf_clone);
  1094. return false;
  1095. }
  1096. /**
  1097. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1098. * @vdev: DP vdev handle
  1099. * @nbuf: skb
  1100. *
  1101. * Extract the DSCP or PCP information from frame and map into TID value.
  1102. *
  1103. * Return: void
  1104. */
  1105. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1106. struct dp_tx_msdu_info_s *msdu_info)
  1107. {
  1108. uint8_t tos = 0, dscp_tid_override = 0;
  1109. uint8_t *hdr_ptr, *L3datap;
  1110. uint8_t is_mcast = 0;
  1111. qdf_ether_header_t *eh = NULL;
  1112. qdf_ethervlan_header_t *evh = NULL;
  1113. uint16_t ether_type;
  1114. qdf_llc_t *llcHdr;
  1115. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1116. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1117. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1118. eh = (qdf_ether_header_t *)nbuf->data;
  1119. hdr_ptr = eh->ether_dhost;
  1120. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1121. } else {
  1122. qdf_dot3_qosframe_t *qos_wh =
  1123. (qdf_dot3_qosframe_t *) nbuf->data;
  1124. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1125. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1126. return;
  1127. }
  1128. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1129. ether_type = eh->ether_type;
  1130. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1131. /*
  1132. * Check if packet is dot3 or eth2 type.
  1133. */
  1134. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1135. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1136. sizeof(*llcHdr));
  1137. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1138. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1139. sizeof(*llcHdr);
  1140. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1141. + sizeof(*llcHdr) +
  1142. sizeof(qdf_net_vlanhdr_t));
  1143. } else {
  1144. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1145. sizeof(*llcHdr);
  1146. }
  1147. } else {
  1148. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1149. evh = (qdf_ethervlan_header_t *) eh;
  1150. ether_type = evh->ether_type;
  1151. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1152. }
  1153. }
  1154. /*
  1155. * Find priority from IP TOS DSCP field
  1156. */
  1157. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1158. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1159. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1160. /* Only for unicast frames */
  1161. if (!is_mcast) {
  1162. /* send it on VO queue */
  1163. msdu_info->tid = DP_VO_TID;
  1164. }
  1165. } else {
  1166. /*
  1167. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1168. * from TOS byte.
  1169. */
  1170. tos = ip->ip_tos;
  1171. dscp_tid_override = 1;
  1172. }
  1173. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1174. /* TODO
  1175. * use flowlabel
  1176. *igmpmld cases to be handled in phase 2
  1177. */
  1178. unsigned long ver_pri_flowlabel;
  1179. unsigned long pri;
  1180. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1181. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1182. DP_IPV6_PRIORITY_SHIFT;
  1183. tos = pri;
  1184. dscp_tid_override = 1;
  1185. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1186. msdu_info->tid = DP_VO_TID;
  1187. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1188. /* Only for unicast frames */
  1189. if (!is_mcast) {
  1190. /* send ucast arp on VO queue */
  1191. msdu_info->tid = DP_VO_TID;
  1192. }
  1193. }
  1194. /*
  1195. * Assign all MCAST packets to BE
  1196. */
  1197. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1198. if (is_mcast) {
  1199. tos = 0;
  1200. dscp_tid_override = 1;
  1201. }
  1202. }
  1203. if (dscp_tid_override == 1) {
  1204. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1205. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1206. }
  1207. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1208. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1209. return;
  1210. }
  1211. /**
  1212. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1213. * @vdev: DP vdev handle
  1214. * @nbuf: skb
  1215. *
  1216. * Software based TID classification is required when more than 2 DSCP-TID
  1217. * mapping tables are needed.
  1218. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1219. *
  1220. * Return: void
  1221. */
  1222. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1223. struct dp_tx_msdu_info_s *msdu_info)
  1224. {
  1225. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1226. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1227. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1228. return;
  1229. /* for mesh packets don't do any classification */
  1230. if (qdf_unlikely(vdev->mesh_vdev))
  1231. return;
  1232. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1233. }
  1234. #ifdef FEATURE_WLAN_TDLS
  1235. /**
  1236. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1237. * @tx_desc: TX descriptor
  1238. *
  1239. * Return: None
  1240. */
  1241. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1242. {
  1243. if (tx_desc->vdev) {
  1244. if (tx_desc->vdev->is_tdls_frame) {
  1245. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1246. tx_desc->vdev->is_tdls_frame = false;
  1247. }
  1248. }
  1249. }
  1250. /**
  1251. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1252. * @tx_desc: TX descriptor
  1253. * @vdev: datapath vdev handle
  1254. *
  1255. * Return: None
  1256. */
  1257. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1258. struct dp_vdev *vdev)
  1259. {
  1260. struct hal_tx_completion_status ts = {0};
  1261. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1262. if (qdf_unlikely(!vdev)) {
  1263. dp_err("vdev is null!");
  1264. return;
  1265. }
  1266. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1267. if (vdev->tx_non_std_data_callback.func) {
  1268. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1269. vdev->tx_non_std_data_callback.func(
  1270. vdev->tx_non_std_data_callback.ctxt,
  1271. nbuf, ts.status);
  1272. return;
  1273. }
  1274. }
  1275. #else
  1276. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1277. {
  1278. }
  1279. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1280. struct dp_vdev *vdev)
  1281. {
  1282. }
  1283. #endif
  1284. /**
  1285. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1286. * @vdev: DP vdev handle
  1287. * @nbuf: skb
  1288. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1289. * @meta_data: Metadata to the fw
  1290. * @tx_q: Tx queue to be used for this Tx frame
  1291. * @peer_id: peer_id of the peer in case of NAWDS frames
  1292. * @tx_exc_metadata: Handle that holds exception path metadata
  1293. *
  1294. * Return: NULL on success,
  1295. * nbuf when it fails to send
  1296. */
  1297. qdf_nbuf_t
  1298. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1299. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1300. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1301. {
  1302. struct dp_pdev *pdev = vdev->pdev;
  1303. struct dp_soc *soc = pdev->soc;
  1304. struct dp_tx_desc_s *tx_desc;
  1305. QDF_STATUS status;
  1306. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1307. hal_ring_handle_t hal_ring_hdl =
  1308. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1309. uint16_t htt_tcl_metadata = 0;
  1310. uint8_t tid = msdu_info->tid;
  1311. struct cdp_tid_tx_stats *tid_stats = NULL;
  1312. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1313. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1314. msdu_info, tx_exc_metadata);
  1315. if (!tx_desc) {
  1316. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1317. vdev, tx_q->desc_pool_id);
  1318. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1319. tid_stats = &pdev->stats.tid_stats.
  1320. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1321. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1322. return nbuf;
  1323. }
  1324. if (qdf_unlikely(soc->cce_disable)) {
  1325. if (dp_cce_classify(vdev, nbuf) == true) {
  1326. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1327. tid = DP_VO_TID;
  1328. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1329. }
  1330. }
  1331. dp_tx_update_tdls_flags(tx_desc);
  1332. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1333. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1334. "%s %d : HAL RING Access Failed -- %pK",
  1335. __func__, __LINE__, hal_ring_hdl);
  1336. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1337. tid_stats = &pdev->stats.tid_stats.
  1338. tid_tx_stats[tx_q->ring_id][tid];
  1339. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1340. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1341. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1342. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1343. goto fail_return;
  1344. }
  1345. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1346. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1347. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1348. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1349. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1350. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1351. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1352. peer_id);
  1353. } else
  1354. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1355. if (msdu_info->exception_fw) {
  1356. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1357. }
  1358. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1359. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1360. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1361. if (status != QDF_STATUS_SUCCESS) {
  1362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1363. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1364. __func__, tx_desc, tx_q->ring_id);
  1365. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1366. tid_stats = &pdev->stats.tid_stats.
  1367. tid_tx_stats[tx_q->ring_id][tid];
  1368. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1369. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1370. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1371. goto fail_return;
  1372. }
  1373. nbuf = NULL;
  1374. fail_return:
  1375. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1376. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1377. hif_pm_runtime_put(soc->hif_handle);
  1378. } else {
  1379. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1380. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1381. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1382. }
  1383. return nbuf;
  1384. }
  1385. /**
  1386. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1387. * @vdev: DP vdev handle
  1388. * @nbuf: skb
  1389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1390. *
  1391. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1392. *
  1393. * Return: NULL on success,
  1394. * nbuf when it fails to send
  1395. */
  1396. #if QDF_LOCK_STATS
  1397. noinline
  1398. #else
  1399. #endif
  1400. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1401. struct dp_tx_msdu_info_s *msdu_info)
  1402. {
  1403. uint8_t i;
  1404. struct dp_pdev *pdev = vdev->pdev;
  1405. struct dp_soc *soc = pdev->soc;
  1406. struct dp_tx_desc_s *tx_desc;
  1407. bool is_cce_classified = false;
  1408. QDF_STATUS status;
  1409. uint16_t htt_tcl_metadata = 0;
  1410. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1411. hal_ring_handle_t hal_ring_hdl =
  1412. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1413. struct cdp_tid_tx_stats *tid_stats = NULL;
  1414. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1415. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1416. "%s %d : HAL RING Access Failed -- %pK",
  1417. __func__, __LINE__, hal_ring_hdl);
  1418. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1419. tid_stats = &pdev->stats.tid_stats.
  1420. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1421. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1422. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1423. return nbuf;
  1424. }
  1425. if (qdf_unlikely(soc->cce_disable)) {
  1426. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1427. if (is_cce_classified) {
  1428. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1429. msdu_info->tid = DP_VO_TID;
  1430. }
  1431. }
  1432. if (msdu_info->frm_type == dp_tx_frm_me)
  1433. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1434. i = 0;
  1435. /* Print statement to track i and num_seg */
  1436. /*
  1437. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1438. * descriptors using information in msdu_info
  1439. */
  1440. while (i < msdu_info->num_seg) {
  1441. /*
  1442. * Setup Tx descriptor for an MSDU, and MSDU extension
  1443. * descriptor
  1444. */
  1445. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1446. tx_q->desc_pool_id);
  1447. if (!tx_desc) {
  1448. if (msdu_info->frm_type == dp_tx_frm_me) {
  1449. dp_tx_me_free_buf(pdev,
  1450. (void *)(msdu_info->u.sg_info
  1451. .curr_seg->frags[0].vaddr));
  1452. }
  1453. goto done;
  1454. }
  1455. if (msdu_info->frm_type == dp_tx_frm_me) {
  1456. tx_desc->me_buffer =
  1457. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1458. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1459. }
  1460. if (is_cce_classified)
  1461. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1462. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1463. if (msdu_info->exception_fw) {
  1464. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1465. }
  1466. /*
  1467. * Enqueue the Tx MSDU descriptor to HW for transmit
  1468. */
  1469. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1470. htt_tcl_metadata, tx_q->ring_id, NULL);
  1471. if (status != QDF_STATUS_SUCCESS) {
  1472. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1473. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1474. __func__, tx_desc, tx_q->ring_id);
  1475. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1476. tid_stats = &pdev->stats.tid_stats.
  1477. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1478. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1479. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1480. goto done;
  1481. }
  1482. /*
  1483. * TODO
  1484. * if tso_info structure can be modified to have curr_seg
  1485. * as first element, following 2 blocks of code (for TSO and SG)
  1486. * can be combined into 1
  1487. */
  1488. /*
  1489. * For frames with multiple segments (TSO, ME), jump to next
  1490. * segment.
  1491. */
  1492. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1493. if (msdu_info->u.tso_info.curr_seg->next) {
  1494. msdu_info->u.tso_info.curr_seg =
  1495. msdu_info->u.tso_info.curr_seg->next;
  1496. /*
  1497. * If this is a jumbo nbuf, then increment the number of
  1498. * nbuf users for each additional segment of the msdu.
  1499. * This will ensure that the skb is freed only after
  1500. * receiving tx completion for all segments of an nbuf
  1501. */
  1502. qdf_nbuf_inc_users(nbuf);
  1503. /* Check with MCL if this is needed */
  1504. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1505. }
  1506. }
  1507. /*
  1508. * For Multicast-Unicast converted packets,
  1509. * each converted frame (for a client) is represented as
  1510. * 1 segment
  1511. */
  1512. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1513. (msdu_info->frm_type == dp_tx_frm_me)) {
  1514. if (msdu_info->u.sg_info.curr_seg->next) {
  1515. msdu_info->u.sg_info.curr_seg =
  1516. msdu_info->u.sg_info.curr_seg->next;
  1517. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1518. }
  1519. }
  1520. i++;
  1521. }
  1522. nbuf = NULL;
  1523. done:
  1524. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1525. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1526. hif_pm_runtime_put(soc->hif_handle);
  1527. } else {
  1528. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1529. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1530. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1531. }
  1532. return nbuf;
  1533. }
  1534. /**
  1535. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1536. * for SG frames
  1537. * @vdev: DP vdev handle
  1538. * @nbuf: skb
  1539. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1540. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1541. *
  1542. * Return: NULL on success,
  1543. * nbuf when it fails to send
  1544. */
  1545. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1546. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1547. {
  1548. uint32_t cur_frag, nr_frags;
  1549. qdf_dma_addr_t paddr;
  1550. struct dp_tx_sg_info_s *sg_info;
  1551. sg_info = &msdu_info->u.sg_info;
  1552. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1553. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1554. QDF_DMA_TO_DEVICE)) {
  1555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1556. "dma map error");
  1557. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1558. qdf_nbuf_free(nbuf);
  1559. return NULL;
  1560. }
  1561. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1562. seg_info->frags[0].paddr_lo = paddr;
  1563. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1564. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1565. seg_info->frags[0].vaddr = (void *) nbuf;
  1566. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1567. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1568. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1570. "frag dma map error");
  1571. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1572. qdf_nbuf_free(nbuf);
  1573. return NULL;
  1574. }
  1575. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1576. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1577. seg_info->frags[cur_frag + 1].paddr_hi =
  1578. ((uint64_t) paddr) >> 32;
  1579. seg_info->frags[cur_frag + 1].len =
  1580. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1581. }
  1582. seg_info->frag_cnt = (cur_frag + 1);
  1583. seg_info->total_len = qdf_nbuf_len(nbuf);
  1584. seg_info->next = NULL;
  1585. sg_info->curr_seg = seg_info;
  1586. msdu_info->frm_type = dp_tx_frm_sg;
  1587. msdu_info->num_seg = 1;
  1588. return nbuf;
  1589. }
  1590. /**
  1591. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1592. * @vdev: DP vdev handle
  1593. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1594. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1595. *
  1596. * Return: NULL on failure,
  1597. * nbuf when extracted successfully
  1598. */
  1599. static
  1600. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1601. struct dp_tx_msdu_info_s *msdu_info,
  1602. uint16_t ppdu_cookie)
  1603. {
  1604. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1605. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1606. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1607. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1608. (msdu_info->meta_data[5], 1);
  1609. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1610. (msdu_info->meta_data[5], 1);
  1611. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1612. (msdu_info->meta_data[6], ppdu_cookie);
  1613. msdu_info->exception_fw = 1;
  1614. msdu_info->is_tx_sniffer = 1;
  1615. }
  1616. #ifdef MESH_MODE_SUPPORT
  1617. /**
  1618. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1619. and prepare msdu_info for mesh frames.
  1620. * @vdev: DP vdev handle
  1621. * @nbuf: skb
  1622. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1623. *
  1624. * Return: NULL on failure,
  1625. * nbuf when extracted successfully
  1626. */
  1627. static
  1628. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1629. struct dp_tx_msdu_info_s *msdu_info)
  1630. {
  1631. struct meta_hdr_s *mhdr;
  1632. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1633. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1634. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1635. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1636. msdu_info->exception_fw = 0;
  1637. goto remove_meta_hdr;
  1638. }
  1639. msdu_info->exception_fw = 1;
  1640. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1641. meta_data->host_tx_desc_pool = 1;
  1642. meta_data->update_peer_cache = 1;
  1643. meta_data->learning_frame = 1;
  1644. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1645. meta_data->power = mhdr->power;
  1646. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1647. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1648. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1649. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1650. meta_data->dyn_bw = 1;
  1651. meta_data->valid_pwr = 1;
  1652. meta_data->valid_mcs_mask = 1;
  1653. meta_data->valid_nss_mask = 1;
  1654. meta_data->valid_preamble_type = 1;
  1655. meta_data->valid_retries = 1;
  1656. meta_data->valid_bw_info = 1;
  1657. }
  1658. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1659. meta_data->encrypt_type = 0;
  1660. meta_data->valid_encrypt_type = 1;
  1661. meta_data->learning_frame = 0;
  1662. }
  1663. meta_data->valid_key_flags = 1;
  1664. meta_data->key_flags = (mhdr->keyix & 0x3);
  1665. remove_meta_hdr:
  1666. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1668. "qdf_nbuf_pull_head failed");
  1669. qdf_nbuf_free(nbuf);
  1670. return NULL;
  1671. }
  1672. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1673. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1674. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1675. " tid %d to_fw %d",
  1676. __func__, msdu_info->meta_data[0],
  1677. msdu_info->meta_data[1],
  1678. msdu_info->meta_data[2],
  1679. msdu_info->meta_data[3],
  1680. msdu_info->meta_data[4],
  1681. msdu_info->meta_data[5],
  1682. msdu_info->tid, msdu_info->exception_fw);
  1683. return nbuf;
  1684. }
  1685. #else
  1686. static
  1687. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1688. struct dp_tx_msdu_info_s *msdu_info)
  1689. {
  1690. return nbuf;
  1691. }
  1692. #endif
  1693. /**
  1694. * dp_check_exc_metadata() - Checks if parameters are valid
  1695. * @tx_exc - holds all exception path parameters
  1696. *
  1697. * Returns true when all the parameters are valid else false
  1698. *
  1699. */
  1700. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1701. {
  1702. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1703. HTT_INVALID_TID);
  1704. bool invalid_encap_type =
  1705. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1706. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1707. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1708. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1709. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1710. tx_exc->ppdu_cookie == 0);
  1711. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1712. invalid_cookie) {
  1713. return false;
  1714. }
  1715. return true;
  1716. }
  1717. /**
  1718. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1719. * @vap_dev: DP vdev handle
  1720. * @nbuf: skb
  1721. * @tx_exc_metadata: Handle that holds exception path meta data
  1722. *
  1723. * Entry point for Core Tx layer (DP_TX) invoked from
  1724. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1725. *
  1726. * Return: NULL on success,
  1727. * nbuf when it fails to send
  1728. */
  1729. qdf_nbuf_t
  1730. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1731. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1732. {
  1733. qdf_ether_header_t *eh = NULL;
  1734. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1735. struct dp_tx_msdu_info_s msdu_info;
  1736. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1737. if (!tx_exc_metadata)
  1738. goto fail;
  1739. msdu_info.tid = tx_exc_metadata->tid;
  1740. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1741. dp_verbose_debug("skb %pM", nbuf->data);
  1742. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1743. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1744. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1745. "Invalid parameters in exception path");
  1746. goto fail;
  1747. }
  1748. /* Basic sanity checks for unsupported packets */
  1749. /* MESH mode */
  1750. if (qdf_unlikely(vdev->mesh_vdev)) {
  1751. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1752. "Mesh mode is not supported in exception path");
  1753. goto fail;
  1754. }
  1755. /* TSO or SG */
  1756. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1757. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1758. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1759. "TSO and SG are not supported in exception path");
  1760. goto fail;
  1761. }
  1762. /* RAW */
  1763. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1764. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1765. "Raw frame is not supported in exception path");
  1766. goto fail;
  1767. }
  1768. /* Mcast enhancement*/
  1769. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1770. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1771. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1772. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1773. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1774. }
  1775. }
  1776. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1777. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1778. qdf_nbuf_len(nbuf));
  1779. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1780. tx_exc_metadata->ppdu_cookie);
  1781. }
  1782. /*
  1783. * Get HW Queue to use for this frame.
  1784. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1785. * dedicated for data and 1 for command.
  1786. * "queue_id" maps to one hardware ring.
  1787. * With each ring, we also associate a unique Tx descriptor pool
  1788. * to minimize lock contention for these resources.
  1789. */
  1790. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1791. /* Single linear frame */
  1792. /*
  1793. * If nbuf is a simple linear frame, use send_single function to
  1794. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1795. * SRNG. There is no need to setup a MSDU extension descriptor.
  1796. */
  1797. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1798. tx_exc_metadata->peer_id, tx_exc_metadata);
  1799. return nbuf;
  1800. fail:
  1801. dp_verbose_debug("pkt send failed");
  1802. return nbuf;
  1803. }
  1804. /**
  1805. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1806. * @vap_dev: DP vdev handle
  1807. * @nbuf: skb
  1808. *
  1809. * Entry point for Core Tx layer (DP_TX) invoked from
  1810. * hard_start_xmit in OSIF/HDD
  1811. *
  1812. * Return: NULL on success,
  1813. * nbuf when it fails to send
  1814. */
  1815. #ifdef MESH_MODE_SUPPORT
  1816. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1817. {
  1818. struct meta_hdr_s *mhdr;
  1819. qdf_nbuf_t nbuf_mesh = NULL;
  1820. qdf_nbuf_t nbuf_clone = NULL;
  1821. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1822. uint8_t no_enc_frame = 0;
  1823. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1824. if (!nbuf_mesh) {
  1825. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1826. "qdf_nbuf_unshare failed");
  1827. return nbuf;
  1828. }
  1829. nbuf = nbuf_mesh;
  1830. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1831. if ((vdev->sec_type != cdp_sec_type_none) &&
  1832. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1833. no_enc_frame = 1;
  1834. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1835. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1836. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1837. !no_enc_frame) {
  1838. nbuf_clone = qdf_nbuf_clone(nbuf);
  1839. if (!nbuf_clone) {
  1840. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1841. "qdf_nbuf_clone failed");
  1842. return nbuf;
  1843. }
  1844. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1845. }
  1846. if (nbuf_clone) {
  1847. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1848. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1849. } else {
  1850. qdf_nbuf_free(nbuf_clone);
  1851. }
  1852. }
  1853. if (no_enc_frame)
  1854. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1855. else
  1856. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1857. nbuf = dp_tx_send(vap_dev, nbuf);
  1858. if ((!nbuf) && no_enc_frame) {
  1859. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1860. }
  1861. return nbuf;
  1862. }
  1863. #else
  1864. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1865. {
  1866. return dp_tx_send(vap_dev, nbuf);
  1867. }
  1868. #endif
  1869. /**
  1870. * dp_tx_send() - Transmit a frame on a given VAP
  1871. * @vap_dev: DP vdev handle
  1872. * @nbuf: skb
  1873. *
  1874. * Entry point for Core Tx layer (DP_TX) invoked from
  1875. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1876. * cases
  1877. *
  1878. * Return: NULL on success,
  1879. * nbuf when it fails to send
  1880. */
  1881. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1882. {
  1883. qdf_ether_header_t *eh = NULL;
  1884. struct dp_tx_msdu_info_s msdu_info;
  1885. struct dp_tx_seg_info_s seg_info;
  1886. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1887. uint16_t peer_id = HTT_INVALID_PEER;
  1888. qdf_nbuf_t nbuf_mesh = NULL;
  1889. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1890. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1891. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1892. dp_verbose_debug("skb %pM", nbuf->data);
  1893. /*
  1894. * Set Default Host TID value to invalid TID
  1895. * (TID override disabled)
  1896. */
  1897. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1898. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1899. if (qdf_unlikely(vdev->mesh_vdev)) {
  1900. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1901. &msdu_info);
  1902. if (!nbuf_mesh) {
  1903. dp_verbose_debug("Extracting mesh metadata failed");
  1904. return nbuf;
  1905. }
  1906. nbuf = nbuf_mesh;
  1907. }
  1908. /*
  1909. * Get HW Queue to use for this frame.
  1910. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1911. * dedicated for data and 1 for command.
  1912. * "queue_id" maps to one hardware ring.
  1913. * With each ring, we also associate a unique Tx descriptor pool
  1914. * to minimize lock contention for these resources.
  1915. */
  1916. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1917. /*
  1918. * TCL H/W supports 2 DSCP-TID mapping tables.
  1919. * Table 1 - Default DSCP-TID mapping table
  1920. * Table 2 - 1 DSCP-TID override table
  1921. *
  1922. * If we need a different DSCP-TID mapping for this vap,
  1923. * call tid_classify to extract DSCP/ToS from frame and
  1924. * map to a TID and store in msdu_info. This is later used
  1925. * to fill in TCL Input descriptor (per-packet TID override).
  1926. */
  1927. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1928. /*
  1929. * Classify the frame and call corresponding
  1930. * "prepare" function which extracts the segment (TSO)
  1931. * and fragmentation information (for TSO , SG, ME, or Raw)
  1932. * into MSDU_INFO structure which is later used to fill
  1933. * SW and HW descriptors.
  1934. */
  1935. if (qdf_nbuf_is_tso(nbuf)) {
  1936. dp_verbose_debug("TSO frame %pK", vdev);
  1937. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1938. qdf_nbuf_len(nbuf));
  1939. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1940. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1941. qdf_nbuf_len(nbuf));
  1942. return nbuf;
  1943. }
  1944. goto send_multiple;
  1945. }
  1946. /* SG */
  1947. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1948. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1949. if (!nbuf)
  1950. return NULL;
  1951. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1952. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1953. qdf_nbuf_len(nbuf));
  1954. goto send_multiple;
  1955. }
  1956. #ifdef ATH_SUPPORT_IQUE
  1957. /* Mcast to Ucast Conversion*/
  1958. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1959. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1960. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1961. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1962. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1963. DP_STATS_INC_PKT(vdev,
  1964. tx_i.mcast_en.mcast_pkt, 1,
  1965. qdf_nbuf_len(nbuf));
  1966. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1967. QDF_STATUS_SUCCESS) {
  1968. return NULL;
  1969. }
  1970. }
  1971. }
  1972. #endif
  1973. /* RAW */
  1974. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1975. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1976. if (!nbuf)
  1977. return NULL;
  1978. dp_verbose_debug("Raw frame %pK", vdev);
  1979. goto send_multiple;
  1980. }
  1981. /* Single linear frame */
  1982. /*
  1983. * If nbuf is a simple linear frame, use send_single function to
  1984. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1985. * SRNG. There is no need to setup a MSDU extension descriptor.
  1986. */
  1987. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1988. return nbuf;
  1989. send_multiple:
  1990. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1991. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1992. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1993. return nbuf;
  1994. }
  1995. /**
  1996. * dp_tx_reinject_handler() - Tx Reinject Handler
  1997. * @tx_desc: software descriptor head pointer
  1998. * @status : Tx completion status from HTT descriptor
  1999. *
  2000. * This function reinjects frames back to Target.
  2001. * Todo - Host queue needs to be added
  2002. *
  2003. * Return: none
  2004. */
  2005. static
  2006. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2007. {
  2008. struct dp_vdev *vdev;
  2009. struct dp_peer *peer = NULL;
  2010. uint32_t peer_id = HTT_INVALID_PEER;
  2011. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2012. qdf_nbuf_t nbuf_copy = NULL;
  2013. struct dp_tx_msdu_info_s msdu_info;
  2014. struct dp_peer *sa_peer = NULL;
  2015. struct dp_ast_entry *ast_entry = NULL;
  2016. struct dp_soc *soc = NULL;
  2017. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2018. #ifdef WDS_VENDOR_EXTENSION
  2019. int is_mcast = 0, is_ucast = 0;
  2020. int num_peers_3addr = 0;
  2021. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2022. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2023. #endif
  2024. vdev = tx_desc->vdev;
  2025. soc = vdev->pdev->soc;
  2026. qdf_assert(vdev);
  2027. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2028. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2030. "%s Tx reinject path", __func__);
  2031. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2032. qdf_nbuf_len(tx_desc->nbuf));
  2033. qdf_spin_lock_bh(&(soc->ast_lock));
  2034. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2035. (soc,
  2036. (uint8_t *)(eh->ether_shost),
  2037. vdev->pdev->pdev_id);
  2038. if (ast_entry)
  2039. sa_peer = ast_entry->peer;
  2040. qdf_spin_unlock_bh(&(soc->ast_lock));
  2041. #ifdef WDS_VENDOR_EXTENSION
  2042. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2043. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2044. } else {
  2045. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2046. }
  2047. is_ucast = !is_mcast;
  2048. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2049. if (peer->bss_peer)
  2050. continue;
  2051. /* Detect wds peers that use 3-addr framing for mcast.
  2052. * if there are any, the bss_peer is used to send the
  2053. * the mcast frame using 3-addr format. all wds enabled
  2054. * peers that use 4-addr framing for mcast frames will
  2055. * be duplicated and sent as 4-addr frames below.
  2056. */
  2057. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2058. num_peers_3addr = 1;
  2059. break;
  2060. }
  2061. }
  2062. #endif
  2063. if (qdf_unlikely(vdev->mesh_vdev)) {
  2064. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2065. } else {
  2066. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2067. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2068. #ifdef WDS_VENDOR_EXTENSION
  2069. /*
  2070. * . if 3-addr STA, then send on BSS Peer
  2071. * . if Peer WDS enabled and accept 4-addr mcast,
  2072. * send mcast on that peer only
  2073. * . if Peer WDS enabled and accept 4-addr ucast,
  2074. * send ucast on that peer only
  2075. */
  2076. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2077. (peer->wds_enabled &&
  2078. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2079. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2080. #else
  2081. ((peer->bss_peer &&
  2082. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2083. peer->nawds_enabled)) {
  2084. #endif
  2085. peer_id = DP_INVALID_PEER;
  2086. if (peer->nawds_enabled) {
  2087. peer_id = peer->peer_ids[0];
  2088. if (sa_peer == peer) {
  2089. QDF_TRACE(
  2090. QDF_MODULE_ID_DP,
  2091. QDF_TRACE_LEVEL_DEBUG,
  2092. " %s: multicast packet",
  2093. __func__);
  2094. DP_STATS_INC(peer,
  2095. tx.nawds_mcast_drop, 1);
  2096. continue;
  2097. }
  2098. }
  2099. nbuf_copy = qdf_nbuf_copy(nbuf);
  2100. if (!nbuf_copy) {
  2101. QDF_TRACE(QDF_MODULE_ID_DP,
  2102. QDF_TRACE_LEVEL_DEBUG,
  2103. FL("nbuf copy failed"));
  2104. break;
  2105. }
  2106. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2107. nbuf_copy,
  2108. &msdu_info,
  2109. peer_id,
  2110. NULL);
  2111. if (nbuf_copy) {
  2112. QDF_TRACE(QDF_MODULE_ID_DP,
  2113. QDF_TRACE_LEVEL_DEBUG,
  2114. FL("pkt send failed"));
  2115. qdf_nbuf_free(nbuf_copy);
  2116. } else {
  2117. if (peer_id != DP_INVALID_PEER)
  2118. DP_STATS_INC_PKT(peer,
  2119. tx.nawds_mcast,
  2120. 1, qdf_nbuf_len(nbuf));
  2121. }
  2122. }
  2123. }
  2124. }
  2125. if (vdev->nawds_enabled) {
  2126. peer_id = DP_INVALID_PEER;
  2127. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2128. 1, qdf_nbuf_len(nbuf));
  2129. nbuf = dp_tx_send_msdu_single(vdev,
  2130. nbuf,
  2131. &msdu_info,
  2132. peer_id, NULL);
  2133. if (nbuf) {
  2134. QDF_TRACE(QDF_MODULE_ID_DP,
  2135. QDF_TRACE_LEVEL_DEBUG,
  2136. FL("pkt send failed"));
  2137. qdf_nbuf_free(nbuf);
  2138. }
  2139. } else
  2140. qdf_nbuf_free(nbuf);
  2141. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2142. }
  2143. /**
  2144. * dp_tx_inspect_handler() - Tx Inspect Handler
  2145. * @tx_desc: software descriptor head pointer
  2146. * @status : Tx completion status from HTT descriptor
  2147. *
  2148. * Handles Tx frames sent back to Host for inspection
  2149. * (ProxyARP)
  2150. *
  2151. * Return: none
  2152. */
  2153. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2154. {
  2155. struct dp_soc *soc;
  2156. struct dp_pdev *pdev = tx_desc->pdev;
  2157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2158. "%s Tx inspect path",
  2159. __func__);
  2160. qdf_assert(pdev);
  2161. soc = pdev->soc;
  2162. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2163. qdf_nbuf_len(tx_desc->nbuf));
  2164. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2165. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2166. }
  2167. #ifdef FEATURE_PERPKT_INFO
  2168. /**
  2169. * dp_get_completion_indication_for_stack() - send completion to stack
  2170. * @soc : dp_soc handle
  2171. * @pdev: dp_pdev handle
  2172. * @peer: dp peer handle
  2173. * @ts: transmit completion status structure
  2174. * @netbuf: Buffer pointer for free
  2175. *
  2176. * This function is used for indication whether buffer needs to be
  2177. * sent to stack for freeing or not
  2178. */
  2179. QDF_STATUS
  2180. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2181. struct dp_pdev *pdev,
  2182. struct dp_peer *peer,
  2183. struct hal_tx_completion_status *ts,
  2184. qdf_nbuf_t netbuf,
  2185. uint64_t time_latency)
  2186. {
  2187. struct tx_capture_hdr *ppdu_hdr;
  2188. uint16_t peer_id = ts->peer_id;
  2189. uint32_t ppdu_id = ts->ppdu_id;
  2190. uint8_t first_msdu = ts->first_msdu;
  2191. uint8_t last_msdu = ts->last_msdu;
  2192. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2193. !pdev->latency_capture_enable))
  2194. return QDF_STATUS_E_NOSUPPORT;
  2195. if (!peer) {
  2196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2197. FL("Peer Invalid"));
  2198. return QDF_STATUS_E_INVAL;
  2199. }
  2200. if (pdev->mcopy_mode) {
  2201. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2202. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2203. return QDF_STATUS_E_INVAL;
  2204. }
  2205. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2206. pdev->m_copy_id.tx_peer_id = peer_id;
  2207. }
  2208. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2210. FL("No headroom"));
  2211. return QDF_STATUS_E_NOMEM;
  2212. }
  2213. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2214. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2215. QDF_MAC_ADDR_SIZE);
  2216. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2217. QDF_MAC_ADDR_SIZE);
  2218. ppdu_hdr->ppdu_id = ppdu_id;
  2219. ppdu_hdr->peer_id = peer_id;
  2220. ppdu_hdr->first_msdu = first_msdu;
  2221. ppdu_hdr->last_msdu = last_msdu;
  2222. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2223. ppdu_hdr->tsf = ts->tsf;
  2224. ppdu_hdr->time_latency = time_latency;
  2225. }
  2226. return QDF_STATUS_SUCCESS;
  2227. }
  2228. /**
  2229. * dp_send_completion_to_stack() - send completion to stack
  2230. * @soc : dp_soc handle
  2231. * @pdev: dp_pdev handle
  2232. * @peer_id: peer_id of the peer for which completion came
  2233. * @ppdu_id: ppdu_id
  2234. * @netbuf: Buffer pointer for free
  2235. *
  2236. * This function is used to send completion to stack
  2237. * to free buffer
  2238. */
  2239. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2240. uint16_t peer_id, uint32_t ppdu_id,
  2241. qdf_nbuf_t netbuf)
  2242. {
  2243. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2244. netbuf, peer_id,
  2245. WDI_NO_VAL, pdev->pdev_id);
  2246. }
  2247. #else
  2248. static QDF_STATUS
  2249. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2250. struct dp_pdev *pdev,
  2251. struct dp_peer *peer,
  2252. struct hal_tx_completion_status *ts,
  2253. qdf_nbuf_t netbuf,
  2254. uint64_t time_latency)
  2255. {
  2256. return QDF_STATUS_E_NOSUPPORT;
  2257. }
  2258. static void
  2259. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2260. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2261. {
  2262. }
  2263. #endif
  2264. /**
  2265. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2266. * @soc: Soc handle
  2267. * @desc: software Tx descriptor to be processed
  2268. *
  2269. * Return: none
  2270. */
  2271. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2272. struct dp_tx_desc_s *desc)
  2273. {
  2274. struct dp_vdev *vdev = desc->vdev;
  2275. qdf_nbuf_t nbuf = desc->nbuf;
  2276. /* nbuf already freed in vdev detach path */
  2277. if (!nbuf)
  2278. return;
  2279. /* If it is TDLS mgmt, don't unmap or free the frame */
  2280. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2281. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2282. /* 0 : MSDU buffer, 1 : MLE */
  2283. if (desc->msdu_ext_desc) {
  2284. /* TSO free */
  2285. if (hal_tx_ext_desc_get_tso_enable(
  2286. desc->msdu_ext_desc->vaddr)) {
  2287. /* unmap eash TSO seg before free the nbuf */
  2288. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2289. desc->tso_num_desc);
  2290. qdf_nbuf_free(nbuf);
  2291. return;
  2292. }
  2293. }
  2294. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2295. if (qdf_unlikely(!vdev)) {
  2296. qdf_nbuf_free(nbuf);
  2297. return;
  2298. }
  2299. if (qdf_likely(!vdev->mesh_vdev))
  2300. qdf_nbuf_free(nbuf);
  2301. else {
  2302. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2303. qdf_nbuf_free(nbuf);
  2304. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2305. } else
  2306. vdev->osif_tx_free_ext((nbuf));
  2307. }
  2308. }
  2309. #ifdef MESH_MODE_SUPPORT
  2310. /**
  2311. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2312. * in mesh meta header
  2313. * @tx_desc: software descriptor head pointer
  2314. * @ts: pointer to tx completion stats
  2315. * Return: none
  2316. */
  2317. static
  2318. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2319. struct hal_tx_completion_status *ts)
  2320. {
  2321. struct meta_hdr_s *mhdr;
  2322. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2323. if (!tx_desc->msdu_ext_desc) {
  2324. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2325. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2326. "netbuf %pK offset %d",
  2327. netbuf, tx_desc->pkt_offset);
  2328. return;
  2329. }
  2330. }
  2331. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2332. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2333. "netbuf %pK offset %lu", netbuf,
  2334. sizeof(struct meta_hdr_s));
  2335. return;
  2336. }
  2337. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2338. mhdr->rssi = ts->ack_frame_rssi;
  2339. mhdr->channel = tx_desc->pdev->operating_channel;
  2340. }
  2341. #else
  2342. static
  2343. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2344. struct hal_tx_completion_status *ts)
  2345. {
  2346. }
  2347. #endif
  2348. /**
  2349. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2350. * to pass in correct fields
  2351. *
  2352. * @vdev: pdev handle
  2353. * @tx_desc: tx descriptor
  2354. * @tid: tid value
  2355. * @ring_id: TCL or WBM ring number for transmit path
  2356. * Return: none
  2357. */
  2358. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2359. struct dp_tx_desc_s *tx_desc,
  2360. uint8_t tid, uint8_t ring_id)
  2361. {
  2362. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2363. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2364. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2365. return;
  2366. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2367. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2368. timestamp_hw_enqueue = tx_desc->timestamp;
  2369. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2370. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2371. timestamp_hw_enqueue);
  2372. interframe_delay = (uint32_t)(timestamp_ingress -
  2373. vdev->prev_tx_enq_tstamp);
  2374. /*
  2375. * Delay in software enqueue
  2376. */
  2377. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2378. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2379. /*
  2380. * Delay between packet enqueued to HW and Tx completion
  2381. */
  2382. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2383. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2384. /*
  2385. * Update interframe delay stats calculated at hardstart receive point.
  2386. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2387. * interframe delay will not be calculate correctly for 1st frame.
  2388. * On the other side, this will help in avoiding extra per packet check
  2389. * of !vdev->prev_tx_enq_tstamp.
  2390. */
  2391. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2392. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2393. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2394. }
  2395. /**
  2396. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2397. * per wbm ring
  2398. *
  2399. * @tx_desc: software descriptor head pointer
  2400. * @ts: Tx completion status
  2401. * @peer: peer handle
  2402. * @ring_id: ring number
  2403. *
  2404. * Return: None
  2405. */
  2406. static inline void
  2407. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2408. struct hal_tx_completion_status *ts,
  2409. struct dp_peer *peer, uint8_t ring_id)
  2410. {
  2411. struct dp_pdev *pdev = peer->vdev->pdev;
  2412. struct dp_soc *soc = NULL;
  2413. uint8_t mcs, pkt_type;
  2414. uint8_t tid = ts->tid;
  2415. uint32_t length;
  2416. struct cdp_tid_tx_stats *tid_stats;
  2417. if (!pdev)
  2418. return;
  2419. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2420. tid = CDP_MAX_DATA_TIDS - 1;
  2421. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2422. soc = pdev->soc;
  2423. mcs = ts->mcs;
  2424. pkt_type = ts->pkt_type;
  2425. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2426. dp_err("Release source is not from TQM");
  2427. return;
  2428. }
  2429. length = qdf_nbuf_len(tx_desc->nbuf);
  2430. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2431. if (qdf_unlikely(pdev->delay_stats_flag))
  2432. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2433. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2434. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2435. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2436. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2437. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2438. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2439. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2440. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2441. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2442. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2443. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2444. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2445. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2446. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2447. /*
  2448. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2449. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2450. * are no completions for failed cases. Hence updating tx_failed from
  2451. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2452. * then this has to be removed
  2453. */
  2454. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2455. peer->stats.tx.dropped.fw_rem_notx +
  2456. peer->stats.tx.dropped.fw_rem_tx +
  2457. peer->stats.tx.dropped.age_out +
  2458. peer->stats.tx.dropped.fw_reason1 +
  2459. peer->stats.tx.dropped.fw_reason2 +
  2460. peer->stats.tx.dropped.fw_reason3;
  2461. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2462. tid_stats->tqm_status_cnt[ts->status]++;
  2463. }
  2464. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2465. return;
  2466. }
  2467. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2468. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2469. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2470. /*
  2471. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2472. * Return from here if HTT PPDU events are enabled.
  2473. */
  2474. if (!(soc->process_tx_status))
  2475. return;
  2476. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2477. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2478. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2479. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2480. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2481. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2482. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2483. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2484. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2485. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2486. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2487. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2488. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2489. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2490. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2491. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2492. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2493. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2494. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2495. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2496. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2497. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2498. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2499. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2500. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2501. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2502. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2503. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2504. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2505. &peer->stats, ts->peer_id,
  2506. UPDATE_PEER_STATS, pdev->pdev_id);
  2507. #endif
  2508. }
  2509. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2510. /**
  2511. * dp_tx_flow_pool_lock() - take flow pool lock
  2512. * @soc: core txrx main context
  2513. * @tx_desc: tx desc
  2514. *
  2515. * Return: None
  2516. */
  2517. static inline
  2518. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2519. struct dp_tx_desc_s *tx_desc)
  2520. {
  2521. struct dp_tx_desc_pool_s *pool;
  2522. uint8_t desc_pool_id;
  2523. desc_pool_id = tx_desc->pool_id;
  2524. pool = &soc->tx_desc[desc_pool_id];
  2525. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2526. }
  2527. /**
  2528. * dp_tx_flow_pool_unlock() - release flow pool lock
  2529. * @soc: core txrx main context
  2530. * @tx_desc: tx desc
  2531. *
  2532. * Return: None
  2533. */
  2534. static inline
  2535. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2536. struct dp_tx_desc_s *tx_desc)
  2537. {
  2538. struct dp_tx_desc_pool_s *pool;
  2539. uint8_t desc_pool_id;
  2540. desc_pool_id = tx_desc->pool_id;
  2541. pool = &soc->tx_desc[desc_pool_id];
  2542. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2543. }
  2544. #else
  2545. static inline
  2546. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2547. {
  2548. }
  2549. static inline
  2550. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2551. {
  2552. }
  2553. #endif
  2554. /**
  2555. * dp_tx_notify_completion() - Notify tx completion for this desc
  2556. * @soc: core txrx main context
  2557. * @tx_desc: tx desc
  2558. * @netbuf: buffer
  2559. *
  2560. * Return: none
  2561. */
  2562. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2563. struct dp_tx_desc_s *tx_desc,
  2564. qdf_nbuf_t netbuf)
  2565. {
  2566. void *osif_dev;
  2567. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2568. qdf_assert(tx_desc);
  2569. dp_tx_flow_pool_lock(soc, tx_desc);
  2570. if (!tx_desc->vdev ||
  2571. !tx_desc->vdev->osif_vdev) {
  2572. dp_tx_flow_pool_unlock(soc, tx_desc);
  2573. return;
  2574. }
  2575. osif_dev = tx_desc->vdev->osif_vdev;
  2576. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2577. dp_tx_flow_pool_unlock(soc, tx_desc);
  2578. if (tx_compl_cbk)
  2579. tx_compl_cbk(netbuf, osif_dev);
  2580. }
  2581. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2582. * @pdev: pdev handle
  2583. * @tid: tid value
  2584. * @txdesc_ts: timestamp from txdesc
  2585. * @ppdu_id: ppdu id
  2586. *
  2587. * Return: none
  2588. */
  2589. #ifdef FEATURE_PERPKT_INFO
  2590. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2591. struct dp_peer *peer,
  2592. uint8_t tid,
  2593. uint64_t txdesc_ts,
  2594. uint32_t ppdu_id)
  2595. {
  2596. uint64_t delta_ms;
  2597. struct cdp_tx_sojourn_stats *sojourn_stats;
  2598. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2599. return;
  2600. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2601. tid >= CDP_DATA_TID_MAX))
  2602. return;
  2603. if (qdf_unlikely(!pdev->sojourn_buf))
  2604. return;
  2605. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2606. qdf_nbuf_data(pdev->sojourn_buf);
  2607. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2608. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2609. txdesc_ts;
  2610. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2611. delta_ms);
  2612. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2613. sojourn_stats->num_msdus[tid] = 1;
  2614. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2615. peer->avg_sojourn_msdu[tid].internal;
  2616. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2617. pdev->sojourn_buf, HTT_INVALID_PEER,
  2618. WDI_NO_VAL, pdev->pdev_id);
  2619. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2620. sojourn_stats->num_msdus[tid] = 0;
  2621. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2622. }
  2623. #else
  2624. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2625. uint8_t tid,
  2626. uint64_t txdesc_ts,
  2627. uint32_t ppdu_id)
  2628. {
  2629. }
  2630. #endif
  2631. /**
  2632. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2633. * @soc: DP Soc handle
  2634. * @tx_desc: software Tx descriptor
  2635. * @ts : Tx completion status from HAL/HTT descriptor
  2636. *
  2637. * Return: none
  2638. */
  2639. static inline void
  2640. dp_tx_comp_process_desc(struct dp_soc *soc,
  2641. struct dp_tx_desc_s *desc,
  2642. struct hal_tx_completion_status *ts,
  2643. struct dp_peer *peer)
  2644. {
  2645. uint64_t time_latency = 0;
  2646. /*
  2647. * m_copy/tx_capture modes are not supported for
  2648. * scatter gather packets
  2649. */
  2650. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2651. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2652. desc->timestamp);
  2653. }
  2654. if (!(desc->msdu_ext_desc)) {
  2655. if (QDF_STATUS_SUCCESS ==
  2656. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2657. return;
  2658. }
  2659. if (QDF_STATUS_SUCCESS ==
  2660. dp_get_completion_indication_for_stack(soc,
  2661. desc->pdev,
  2662. peer, ts,
  2663. desc->nbuf,
  2664. time_latency)) {
  2665. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2666. QDF_DMA_TO_DEVICE);
  2667. dp_send_completion_to_stack(soc,
  2668. desc->pdev,
  2669. ts->peer_id,
  2670. ts->ppdu_id,
  2671. desc->nbuf);
  2672. return;
  2673. }
  2674. }
  2675. dp_tx_comp_free_buf(soc, desc);
  2676. }
  2677. /**
  2678. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2679. * @tx_desc: software descriptor head pointer
  2680. * @ts: Tx completion status
  2681. * @peer: peer handle
  2682. * @ring_id: ring number
  2683. *
  2684. * Return: none
  2685. */
  2686. static inline
  2687. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2688. struct hal_tx_completion_status *ts,
  2689. struct dp_peer *peer, uint8_t ring_id)
  2690. {
  2691. uint32_t length;
  2692. qdf_ether_header_t *eh;
  2693. struct dp_soc *soc = NULL;
  2694. struct dp_vdev *vdev = tx_desc->vdev;
  2695. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2696. if (!vdev || !nbuf) {
  2697. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2698. "invalid tx descriptor. vdev or nbuf NULL");
  2699. goto out;
  2700. }
  2701. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2702. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2703. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2704. QDF_TRACE_DEFAULT_PDEV_ID,
  2705. qdf_nbuf_data_addr(nbuf),
  2706. sizeof(qdf_nbuf_data(nbuf)),
  2707. tx_desc->id,
  2708. ts->status));
  2709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2710. "-------------------- \n"
  2711. "Tx Completion Stats: \n"
  2712. "-------------------- \n"
  2713. "ack_frame_rssi = %d \n"
  2714. "first_msdu = %d \n"
  2715. "last_msdu = %d \n"
  2716. "msdu_part_of_amsdu = %d \n"
  2717. "rate_stats valid = %d \n"
  2718. "bw = %d \n"
  2719. "pkt_type = %d \n"
  2720. "stbc = %d \n"
  2721. "ldpc = %d \n"
  2722. "sgi = %d \n"
  2723. "mcs = %d \n"
  2724. "ofdma = %d \n"
  2725. "tones_in_ru = %d \n"
  2726. "tsf = %d \n"
  2727. "ppdu_id = %d \n"
  2728. "transmit_cnt = %d \n"
  2729. "tid = %d \n"
  2730. "peer_id = %d\n",
  2731. ts->ack_frame_rssi, ts->first_msdu,
  2732. ts->last_msdu, ts->msdu_part_of_amsdu,
  2733. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2734. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2735. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2736. ts->transmit_cnt, ts->tid, ts->peer_id);
  2737. soc = vdev->pdev->soc;
  2738. /* Update SoC level stats */
  2739. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2740. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2741. /* Update per-packet stats for mesh mode */
  2742. if (qdf_unlikely(vdev->mesh_vdev) &&
  2743. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2744. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2745. length = qdf_nbuf_len(nbuf);
  2746. /* Update peer level stats */
  2747. if (!peer) {
  2748. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2749. "peer is null or deletion in progress");
  2750. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2751. goto out;
  2752. }
  2753. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2754. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2755. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2756. if ((peer->vdev->tx_encap_type ==
  2757. htt_cmn_pkt_type_ethernet) &&
  2758. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2759. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2760. }
  2761. }
  2762. } else {
  2763. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2764. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2765. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2766. }
  2767. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2768. #ifdef QCA_SUPPORT_RDK_STATS
  2769. if (soc->wlanstats_enabled)
  2770. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2771. tx_desc->timestamp,
  2772. ts->ppdu_id);
  2773. #endif
  2774. out:
  2775. return;
  2776. }
  2777. /**
  2778. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2779. * @soc: core txrx main context
  2780. * @comp_head: software descriptor head pointer
  2781. * @ring_id: ring number
  2782. *
  2783. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2784. * and release the software descriptors after processing is complete
  2785. *
  2786. * Return: none
  2787. */
  2788. static void
  2789. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2790. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2791. {
  2792. struct dp_tx_desc_s *desc;
  2793. struct dp_tx_desc_s *next;
  2794. struct hal_tx_completion_status ts = {0};
  2795. struct dp_peer *peer;
  2796. qdf_nbuf_t netbuf;
  2797. desc = comp_head;
  2798. while (desc) {
  2799. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2800. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2801. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2802. netbuf = desc->nbuf;
  2803. /* check tx complete notification */
  2804. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2805. dp_tx_notify_completion(soc, desc, netbuf);
  2806. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2807. if (peer)
  2808. dp_peer_unref_del_find_by_id(peer);
  2809. next = desc->next;
  2810. dp_tx_desc_release(desc, desc->pool_id);
  2811. desc = next;
  2812. }
  2813. }
  2814. /**
  2815. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2816. * @tx_desc: software descriptor head pointer
  2817. * @status : Tx completion status from HTT descriptor
  2818. * @ring_id: ring number
  2819. *
  2820. * This function will process HTT Tx indication messages from Target
  2821. *
  2822. * Return: none
  2823. */
  2824. static
  2825. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2826. uint8_t ring_id)
  2827. {
  2828. uint8_t tx_status;
  2829. struct dp_pdev *pdev;
  2830. struct dp_vdev *vdev;
  2831. struct dp_soc *soc;
  2832. struct hal_tx_completion_status ts = {0};
  2833. uint32_t *htt_desc = (uint32_t *)status;
  2834. struct dp_peer *peer;
  2835. struct cdp_tid_tx_stats *tid_stats = NULL;
  2836. struct htt_soc *htt_handle;
  2837. qdf_assert(tx_desc->pdev);
  2838. pdev = tx_desc->pdev;
  2839. vdev = tx_desc->vdev;
  2840. soc = pdev->soc;
  2841. if (!vdev)
  2842. return;
  2843. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2844. htt_handle = (struct htt_soc *)soc->htt_handle;
  2845. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2846. switch (tx_status) {
  2847. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2848. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2849. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2850. {
  2851. uint8_t tid;
  2852. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2853. ts.peer_id =
  2854. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2855. htt_desc[2]);
  2856. ts.tid =
  2857. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2858. htt_desc[2]);
  2859. } else {
  2860. ts.peer_id = HTT_INVALID_PEER;
  2861. ts.tid = HTT_INVALID_TID;
  2862. }
  2863. ts.ppdu_id =
  2864. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2865. htt_desc[1]);
  2866. ts.ack_frame_rssi =
  2867. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2868. htt_desc[1]);
  2869. ts.first_msdu = 1;
  2870. ts.last_msdu = 1;
  2871. tid = ts.tid;
  2872. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2873. tid = CDP_MAX_DATA_TIDS - 1;
  2874. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2875. if (qdf_unlikely(pdev->delay_stats_flag))
  2876. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2877. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2878. tid_stats->htt_status_cnt[tx_status]++;
  2879. }
  2880. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2881. if (qdf_likely(peer))
  2882. dp_peer_unref_del_find_by_id(peer);
  2883. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2884. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2885. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2886. break;
  2887. }
  2888. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2889. {
  2890. dp_tx_reinject_handler(tx_desc, status);
  2891. break;
  2892. }
  2893. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2894. {
  2895. dp_tx_inspect_handler(tx_desc, status);
  2896. break;
  2897. }
  2898. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2899. {
  2900. dp_tx_mec_handler(vdev, status);
  2901. break;
  2902. }
  2903. default:
  2904. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2905. "%s Invalid HTT tx_status %d\n",
  2906. __func__, tx_status);
  2907. break;
  2908. }
  2909. }
  2910. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2911. static inline
  2912. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2913. {
  2914. bool limit_hit = false;
  2915. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2916. limit_hit =
  2917. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2918. if (limit_hit)
  2919. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2920. return limit_hit;
  2921. }
  2922. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2923. {
  2924. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2925. }
  2926. #else
  2927. static inline
  2928. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2929. {
  2930. return false;
  2931. }
  2932. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2933. {
  2934. return false;
  2935. }
  2936. #endif
  2937. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2938. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2939. uint32_t quota)
  2940. {
  2941. void *tx_comp_hal_desc;
  2942. uint8_t buffer_src;
  2943. uint8_t pool_id;
  2944. uint32_t tx_desc_id;
  2945. struct dp_tx_desc_s *tx_desc = NULL;
  2946. struct dp_tx_desc_s *head_desc = NULL;
  2947. struct dp_tx_desc_s *tail_desc = NULL;
  2948. uint32_t num_processed = 0;
  2949. uint32_t count = 0;
  2950. bool force_break = false;
  2951. DP_HIST_INIT();
  2952. more_data:
  2953. /* Re-initialize local variables to be re-used */
  2954. head_desc = NULL;
  2955. tail_desc = NULL;
  2956. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2957. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2958. "%s %d : HAL RING Access Failed -- %pK",
  2959. __func__, __LINE__, hal_ring_hdl);
  2960. return 0;
  2961. }
  2962. /* Find head descriptor from completion ring */
  2963. while (qdf_likely(tx_comp_hal_desc =
  2964. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2965. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2966. /* If this buffer was not released by TQM or FW, then it is not
  2967. * Tx completion indication, assert */
  2968. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2969. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2970. uint8_t wbm_internal_error;
  2971. QDF_TRACE(QDF_MODULE_ID_DP,
  2972. QDF_TRACE_LEVEL_FATAL,
  2973. "Tx comp release_src != TQM | FW but from %d",
  2974. buffer_src);
  2975. hal_dump_comp_desc(tx_comp_hal_desc);
  2976. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2977. /* When WBM sees NULL buffer_addr_info in any of
  2978. * ingress rings it sends an error indication,
  2979. * with wbm_internal_error=1, to a specific ring.
  2980. * The WBM2SW ring used to indicate these errors is
  2981. * fixed in HW, and that ring is being used as Tx
  2982. * completion ring. These errors are not related to
  2983. * Tx completions, and should just be ignored
  2984. */
  2985. wbm_internal_error =
  2986. hal_get_wbm_internal_error(tx_comp_hal_desc);
  2987. if (wbm_internal_error) {
  2988. QDF_TRACE(QDF_MODULE_ID_DP,
  2989. QDF_TRACE_LEVEL_ERROR,
  2990. "Tx comp wbm_internal_error!!!\n");
  2991. DP_STATS_INC(soc, tx.wbm_internal_error, 1);
  2992. continue;
  2993. } else {
  2994. qdf_assert_always(0);
  2995. }
  2996. }
  2997. /* Get descriptor id */
  2998. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2999. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3000. DP_TX_DESC_ID_POOL_OS;
  3001. /* Find Tx descriptor */
  3002. tx_desc = dp_tx_desc_find(soc, pool_id,
  3003. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3004. DP_TX_DESC_ID_PAGE_OS,
  3005. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3006. DP_TX_DESC_ID_OFFSET_OS);
  3007. /*
  3008. * If the descriptor is already freed in vdev_detach,
  3009. * continue to next descriptor
  3010. */
  3011. if (!tx_desc->vdev && !tx_desc->flags) {
  3012. QDF_TRACE(QDF_MODULE_ID_DP,
  3013. QDF_TRACE_LEVEL_INFO,
  3014. "Descriptor freed in vdev_detach %d",
  3015. tx_desc_id);
  3016. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3017. count++;
  3018. continue;
  3019. }
  3020. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3021. QDF_TRACE(QDF_MODULE_ID_DP,
  3022. QDF_TRACE_LEVEL_INFO,
  3023. "pdev in down state %d",
  3024. tx_desc_id);
  3025. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3026. count++;
  3027. dp_tx_comp_free_buf(soc, tx_desc);
  3028. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3029. continue;
  3030. }
  3031. /*
  3032. * If the release source is FW, process the HTT status
  3033. */
  3034. if (qdf_unlikely(buffer_src ==
  3035. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3036. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3037. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3038. htt_tx_status);
  3039. dp_tx_process_htt_completion(tx_desc,
  3040. htt_tx_status, ring_id);
  3041. } else {
  3042. /* Pool id is not matching. Error */
  3043. if (tx_desc->pool_id != pool_id) {
  3044. QDF_TRACE(QDF_MODULE_ID_DP,
  3045. QDF_TRACE_LEVEL_FATAL,
  3046. "Tx Comp pool id %d not matched %d",
  3047. pool_id, tx_desc->pool_id);
  3048. qdf_assert_always(0);
  3049. }
  3050. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3051. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3052. QDF_TRACE(QDF_MODULE_ID_DP,
  3053. QDF_TRACE_LEVEL_FATAL,
  3054. "Txdesc invalid, flgs = %x,id = %d",
  3055. tx_desc->flags, tx_desc_id);
  3056. qdf_assert_always(0);
  3057. }
  3058. /* First ring descriptor on the cycle */
  3059. if (!head_desc) {
  3060. head_desc = tx_desc;
  3061. tail_desc = tx_desc;
  3062. }
  3063. tail_desc->next = tx_desc;
  3064. tx_desc->next = NULL;
  3065. tail_desc = tx_desc;
  3066. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3067. /* Collect hw completion contents */
  3068. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3069. &tx_desc->comp, 1);
  3070. }
  3071. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3072. /*
  3073. * Processed packet count is more than given quota
  3074. * stop to processing
  3075. */
  3076. if (num_processed >= quota) {
  3077. force_break = true;
  3078. break;
  3079. }
  3080. count++;
  3081. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3082. break;
  3083. }
  3084. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3085. /* Process the reaped descriptors */
  3086. if (head_desc)
  3087. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3088. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3089. if (!force_break &&
  3090. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3091. hal_ring_hdl)) {
  3092. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3093. if (!hif_exec_should_yield(soc->hif_handle,
  3094. int_ctx->dp_intr_id))
  3095. goto more_data;
  3096. }
  3097. }
  3098. DP_TX_HIST_STATS_PER_PDEV();
  3099. return num_processed;
  3100. }
  3101. #ifdef FEATURE_WLAN_TDLS
  3102. /**
  3103. * dp_tx_non_std() - Allow the control-path SW to send data frames
  3104. *
  3105. * @data_vdev - which vdev should transmit the tx data frames
  3106. * @tx_spec - what non-standard handling to apply to the tx data frames
  3107. * @msdu_list - NULL-terminated list of tx MSDUs
  3108. *
  3109. * Return: NULL on success,
  3110. * nbuf when it fails to send
  3111. */
  3112. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3113. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3114. {
  3115. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3116. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3117. vdev->is_tdls_frame = true;
  3118. return dp_tx_send(vdev_handle, msdu_list);
  3119. }
  3120. #endif
  3121. /**
  3122. * dp_tx_vdev_attach() - attach vdev to dp tx
  3123. * @vdev: virtual device instance
  3124. *
  3125. * Return: QDF_STATUS_SUCCESS: success
  3126. * QDF_STATUS_E_RESOURCES: Error return
  3127. */
  3128. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3129. {
  3130. /*
  3131. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3132. */
  3133. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3134. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3135. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3136. vdev->vdev_id);
  3137. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3138. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3139. /*
  3140. * Set HTT Extension Valid bit to 0 by default
  3141. */
  3142. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3143. dp_tx_vdev_update_search_flags(vdev);
  3144. return QDF_STATUS_SUCCESS;
  3145. }
  3146. #ifndef FEATURE_WDS
  3147. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3148. {
  3149. return false;
  3150. }
  3151. #endif
  3152. /**
  3153. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3154. * @vdev: virtual device instance
  3155. *
  3156. * Return: void
  3157. *
  3158. */
  3159. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3160. {
  3161. struct dp_soc *soc = vdev->pdev->soc;
  3162. /*
  3163. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3164. * for TDLS link
  3165. *
  3166. * Enable AddrY (SA based search) only for non-WDS STA and
  3167. * ProxySTA VAP (in HKv1) modes.
  3168. *
  3169. * In all other VAP modes, only DA based search should be
  3170. * enabled
  3171. */
  3172. if (vdev->opmode == wlan_op_mode_sta &&
  3173. vdev->tdls_link_connected)
  3174. vdev->hal_desc_addr_search_flags =
  3175. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3176. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3177. !dp_tx_da_search_override(vdev))
  3178. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3179. else
  3180. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3181. /* Set search type only when peer map v2 messaging is enabled
  3182. * as we will have the search index (AST hash) only when v2 is
  3183. * enabled
  3184. */
  3185. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3186. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3187. else
  3188. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3189. }
  3190. static inline bool
  3191. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3192. struct dp_vdev *vdev,
  3193. struct dp_tx_desc_s *tx_desc)
  3194. {
  3195. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3196. return false;
  3197. /*
  3198. * if vdev is given, then only check whether desc
  3199. * vdev match. if vdev is NULL, then check whether
  3200. * desc pdev match.
  3201. */
  3202. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3203. }
  3204. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3205. /**
  3206. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3207. *
  3208. * @soc: Handle to DP SoC structure
  3209. * @tx_desc: pointer of one TX desc
  3210. * @desc_pool_id: TX Desc pool id
  3211. */
  3212. static inline void
  3213. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3214. uint8_t desc_pool_id)
  3215. {
  3216. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3217. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3218. tx_desc->vdev = NULL;
  3219. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3220. }
  3221. /**
  3222. * dp_tx_desc_flush() - release resources associated
  3223. * to TX Desc
  3224. *
  3225. * @dp_pdev: Handle to DP pdev structure
  3226. * @vdev: virtual device instance
  3227. * NULL: no specific Vdev is required and check all allcated TX desc
  3228. * on this pdev.
  3229. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3230. *
  3231. * @force_free:
  3232. * true: flush the TX desc.
  3233. * false: only reset the Vdev in each allocated TX desc
  3234. * that associated to current Vdev.
  3235. *
  3236. * This function will go through the TX desc pool to flush
  3237. * the outstanding TX data or reset Vdev to NULL in associated TX
  3238. * Desc.
  3239. */
  3240. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3241. struct dp_vdev *vdev,
  3242. bool force_free)
  3243. {
  3244. uint8_t i;
  3245. uint32_t j;
  3246. uint32_t num_desc, page_id, offset;
  3247. uint16_t num_desc_per_page;
  3248. struct dp_soc *soc = pdev->soc;
  3249. struct dp_tx_desc_s *tx_desc = NULL;
  3250. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3251. if (!vdev && !force_free) {
  3252. dp_err("Reset TX desc vdev, Vdev param is required!");
  3253. return;
  3254. }
  3255. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3256. tx_desc_pool = &soc->tx_desc[i];
  3257. if (!(tx_desc_pool->pool_size) ||
  3258. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3259. !(tx_desc_pool->desc_pages.cacheable_pages))
  3260. continue;
  3261. num_desc = tx_desc_pool->pool_size;
  3262. num_desc_per_page =
  3263. tx_desc_pool->desc_pages.num_element_per_page;
  3264. for (j = 0; j < num_desc; j++) {
  3265. page_id = j / num_desc_per_page;
  3266. offset = j % num_desc_per_page;
  3267. if (qdf_unlikely(!(tx_desc_pool->
  3268. desc_pages.cacheable_pages)))
  3269. break;
  3270. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3271. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3272. /*
  3273. * Free TX desc if force free is
  3274. * required, otherwise only reset vdev
  3275. * in this TX desc.
  3276. */
  3277. if (force_free) {
  3278. dp_tx_comp_free_buf(soc, tx_desc);
  3279. dp_tx_desc_release(tx_desc, i);
  3280. } else {
  3281. dp_tx_desc_reset_vdev(soc, tx_desc,
  3282. i);
  3283. }
  3284. }
  3285. }
  3286. }
  3287. }
  3288. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3289. static inline void
  3290. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3291. uint8_t desc_pool_id)
  3292. {
  3293. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3294. tx_desc->vdev = NULL;
  3295. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3296. }
  3297. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3298. struct dp_vdev *vdev,
  3299. bool force_free)
  3300. {
  3301. uint8_t i, num_pool;
  3302. uint32_t j;
  3303. uint32_t num_desc, page_id, offset;
  3304. uint16_t num_desc_per_page;
  3305. struct dp_soc *soc = pdev->soc;
  3306. struct dp_tx_desc_s *tx_desc = NULL;
  3307. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3308. if (!vdev && !force_free) {
  3309. dp_err("Reset TX desc vdev, Vdev param is required!");
  3310. return;
  3311. }
  3312. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3313. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3314. for (i = 0; i < num_pool; i++) {
  3315. tx_desc_pool = &soc->tx_desc[i];
  3316. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3317. continue;
  3318. num_desc_per_page =
  3319. tx_desc_pool->desc_pages.num_element_per_page;
  3320. for (j = 0; j < num_desc; j++) {
  3321. page_id = j / num_desc_per_page;
  3322. offset = j % num_desc_per_page;
  3323. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3324. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3325. if (force_free) {
  3326. dp_tx_comp_free_buf(soc, tx_desc);
  3327. dp_tx_desc_release(tx_desc, i);
  3328. } else {
  3329. dp_tx_desc_reset_vdev(soc, tx_desc,
  3330. i);
  3331. }
  3332. }
  3333. }
  3334. }
  3335. }
  3336. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3337. /**
  3338. * dp_tx_vdev_detach() - detach vdev from dp tx
  3339. * @vdev: virtual device instance
  3340. *
  3341. * Return: QDF_STATUS_SUCCESS: success
  3342. * QDF_STATUS_E_RESOURCES: Error return
  3343. */
  3344. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3345. {
  3346. struct dp_pdev *pdev = vdev->pdev;
  3347. /* Reset TX desc associated to this Vdev as NULL */
  3348. dp_tx_desc_flush(pdev, vdev, false);
  3349. dp_tx_vdev_multipass_deinit(vdev);
  3350. return QDF_STATUS_SUCCESS;
  3351. }
  3352. /**
  3353. * dp_tx_pdev_attach() - attach pdev to dp tx
  3354. * @pdev: physical device instance
  3355. *
  3356. * Return: QDF_STATUS_SUCCESS: success
  3357. * QDF_STATUS_E_RESOURCES: Error return
  3358. */
  3359. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3360. {
  3361. struct dp_soc *soc = pdev->soc;
  3362. /* Initialize Flow control counters */
  3363. qdf_atomic_init(&pdev->num_tx_exception);
  3364. qdf_atomic_init(&pdev->num_tx_outstanding);
  3365. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3366. /* Initialize descriptors in TCL Ring */
  3367. hal_tx_init_data_ring(soc->hal_soc,
  3368. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3369. }
  3370. return QDF_STATUS_SUCCESS;
  3371. }
  3372. /**
  3373. * dp_tx_pdev_detach() - detach pdev from dp tx
  3374. * @pdev: physical device instance
  3375. *
  3376. * Return: QDF_STATUS_SUCCESS: success
  3377. * QDF_STATUS_E_RESOURCES: Error return
  3378. */
  3379. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3380. {
  3381. /* flush TX outstanding data per pdev */
  3382. dp_tx_desc_flush(pdev, NULL, true);
  3383. dp_tx_me_exit(pdev);
  3384. return QDF_STATUS_SUCCESS;
  3385. }
  3386. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3387. /* Pools will be allocated dynamically */
  3388. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3389. int num_desc)
  3390. {
  3391. uint8_t i;
  3392. for (i = 0; i < num_pool; i++) {
  3393. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3394. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3395. }
  3396. return 0;
  3397. }
  3398. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3399. {
  3400. uint8_t i;
  3401. for (i = 0; i < num_pool; i++)
  3402. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3403. }
  3404. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3405. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3406. int num_desc)
  3407. {
  3408. uint8_t i;
  3409. /* Allocate software Tx descriptor pools */
  3410. for (i = 0; i < num_pool; i++) {
  3411. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3412. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3413. "%s Tx Desc Pool alloc %d failed %pK",
  3414. __func__, i, soc);
  3415. return ENOMEM;
  3416. }
  3417. }
  3418. return 0;
  3419. }
  3420. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3421. {
  3422. uint8_t i;
  3423. for (i = 0; i < num_pool; i++) {
  3424. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3425. if (dp_tx_desc_pool_free(soc, i)) {
  3426. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3427. "%s Tx Desc Pool Free failed", __func__);
  3428. }
  3429. }
  3430. }
  3431. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3432. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3433. /**
  3434. * dp_tso_attach_wifi3() - TSO attach handler
  3435. * @txrx_soc: Opaque Dp handle
  3436. *
  3437. * Reserve TSO descriptor buffers
  3438. *
  3439. * Return: QDF_STATUS_E_FAILURE on failure or
  3440. * QDF_STATUS_SUCCESS on success
  3441. */
  3442. static
  3443. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3444. {
  3445. return dp_tso_soc_attach(txrx_soc);
  3446. }
  3447. /**
  3448. * dp_tso_detach_wifi3() - TSO Detach handler
  3449. * @txrx_soc: Opaque Dp handle
  3450. *
  3451. * Deallocate TSO descriptor buffers
  3452. *
  3453. * Return: QDF_STATUS_E_FAILURE on failure or
  3454. * QDF_STATUS_SUCCESS on success
  3455. */
  3456. static
  3457. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3458. {
  3459. return dp_tso_soc_detach(txrx_soc);
  3460. }
  3461. #else
  3462. static
  3463. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3464. {
  3465. return QDF_STATUS_SUCCESS;
  3466. }
  3467. static
  3468. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3469. {
  3470. return QDF_STATUS_SUCCESS;
  3471. }
  3472. #endif
  3473. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3474. {
  3475. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3476. uint8_t i;
  3477. uint8_t num_pool;
  3478. uint32_t num_desc;
  3479. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3480. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3481. for (i = 0; i < num_pool; i++)
  3482. dp_tx_tso_desc_pool_free(soc, i);
  3483. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3484. __func__, num_pool, num_desc);
  3485. for (i = 0; i < num_pool; i++)
  3486. dp_tx_tso_num_seg_pool_free(soc, i);
  3487. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3488. __func__, num_pool, num_desc);
  3489. return QDF_STATUS_SUCCESS;
  3490. }
  3491. /**
  3492. * dp_tso_attach() - TSO attach handler
  3493. * @txrx_soc: Opaque Dp handle
  3494. *
  3495. * Reserve TSO descriptor buffers
  3496. *
  3497. * Return: QDF_STATUS_E_FAILURE on failure or
  3498. * QDF_STATUS_SUCCESS on success
  3499. */
  3500. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3501. {
  3502. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3503. uint8_t i;
  3504. uint8_t num_pool;
  3505. uint32_t num_desc;
  3506. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3507. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3508. for (i = 0; i < num_pool; i++) {
  3509. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3510. dp_err("TSO Desc Pool alloc %d failed %pK",
  3511. i, soc);
  3512. return QDF_STATUS_E_FAILURE;
  3513. }
  3514. }
  3515. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3516. __func__, num_pool, num_desc);
  3517. for (i = 0; i < num_pool; i++) {
  3518. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3519. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3520. i, soc);
  3521. return QDF_STATUS_E_FAILURE;
  3522. }
  3523. }
  3524. return QDF_STATUS_SUCCESS;
  3525. }
  3526. /**
  3527. * dp_tx_soc_detach() - detach soc from dp tx
  3528. * @soc: core txrx main context
  3529. *
  3530. * This function will detach dp tx into main device context
  3531. * will free dp tx resource and initialize resources
  3532. *
  3533. * Return: QDF_STATUS_SUCCESS: success
  3534. * QDF_STATUS_E_RESOURCES: Error return
  3535. */
  3536. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3537. {
  3538. uint8_t num_pool;
  3539. uint16_t num_desc;
  3540. uint16_t num_ext_desc;
  3541. uint8_t i;
  3542. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3543. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3544. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3545. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3546. dp_tx_flow_control_deinit(soc);
  3547. dp_tx_delete_static_pools(soc, num_pool);
  3548. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3549. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3550. __func__, num_pool, num_desc);
  3551. for (i = 0; i < num_pool; i++) {
  3552. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3553. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3554. "%s Tx Ext Desc Pool Free failed",
  3555. __func__);
  3556. return QDF_STATUS_E_RESOURCES;
  3557. }
  3558. }
  3559. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3560. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3561. __func__, num_pool, num_ext_desc);
  3562. status = dp_tso_detach_wifi3(soc);
  3563. if (status != QDF_STATUS_SUCCESS)
  3564. return status;
  3565. return QDF_STATUS_SUCCESS;
  3566. }
  3567. /**
  3568. * dp_tx_soc_attach() - attach soc to dp tx
  3569. * @soc: core txrx main context
  3570. *
  3571. * This function will attach dp tx into main device context
  3572. * will allocate dp tx resource and initialize resources
  3573. *
  3574. * Return: QDF_STATUS_SUCCESS: success
  3575. * QDF_STATUS_E_RESOURCES: Error return
  3576. */
  3577. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3578. {
  3579. uint8_t i;
  3580. uint8_t num_pool;
  3581. uint32_t num_desc;
  3582. uint32_t num_ext_desc;
  3583. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3584. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3585. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3586. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3587. if (num_pool > MAX_TXDESC_POOLS)
  3588. goto fail;
  3589. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3590. goto fail;
  3591. dp_tx_flow_control_init(soc);
  3592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3593. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3594. __func__, num_pool, num_desc);
  3595. /* Allocate extension tx descriptor pools */
  3596. for (i = 0; i < num_pool; i++) {
  3597. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3599. "MSDU Ext Desc Pool alloc %d failed %pK",
  3600. i, soc);
  3601. goto fail;
  3602. }
  3603. }
  3604. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3605. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3606. __func__, num_pool, num_ext_desc);
  3607. status = dp_tso_attach_wifi3((void *)soc);
  3608. if (status != QDF_STATUS_SUCCESS)
  3609. goto fail;
  3610. /* Initialize descriptors in TCL Rings */
  3611. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3612. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3613. hal_tx_init_data_ring(soc->hal_soc,
  3614. soc->tcl_data_ring[i].hal_srng);
  3615. }
  3616. }
  3617. /*
  3618. * todo - Add a runtime config option to enable this.
  3619. */
  3620. /*
  3621. * Due to multiple issues on NPR EMU, enable it selectively
  3622. * only for NPR EMU, should be removed, once NPR platforms
  3623. * are stable.
  3624. */
  3625. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3627. "%s HAL Tx init Success", __func__);
  3628. return QDF_STATUS_SUCCESS;
  3629. fail:
  3630. /* Detach will take care of freeing only allocated resources */
  3631. dp_tx_soc_detach(soc);
  3632. return QDF_STATUS_E_RESOURCES;
  3633. }