sdm660-common.c 96 KB

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  1. /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/input.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_device.h>
  17. #include <sound/pcm_params.h>
  18. #include <dsp/q6afe-v2.h>
  19. #include <dsp/audio_notifier.h>
  20. #include "msm-pcm-routing-v2.h"
  21. #include "sdm660-common.h"
  22. #include "sdm660-internal.h"
  23. #include "sdm660-external.h"
  24. #include "codecs/msm-cdc-pinctrl.h"
  25. #include "codecs/sdm660_cdc/msm-analog-cdc.h"
  26. #include "codecs/wsa881x.h"
  27. #define __CHIPSET__ "SDM660 "
  28. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  29. #define DRV_NAME "sdm660-asoc-snd"
  30. #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
  31. #define PMIC_INT_ANALOG_CODEC "analog-codec"
  32. #define DEV_NAME_STR_LEN 32
  33. #define DEFAULT_MCLK_RATE 9600000
  34. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  35. struct dev_config {
  36. u32 sample_rate;
  37. u32 bit_format;
  38. u32 channels;
  39. };
  40. enum {
  41. DP_RX_IDX,
  42. EXT_DISP_RX_IDX_MAX,
  43. };
  44. bool codec_reg_done;
  45. /* TDM default config */
  46. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  47. { /* PRI TDM */
  48. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  49. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  50. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  51. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  52. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  53. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  54. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  55. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  56. },
  57. { /* SEC TDM */
  58. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  59. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  60. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  61. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  62. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  63. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  64. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  65. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  66. },
  67. { /* TERT TDM */
  68. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  69. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  70. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  71. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  72. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  73. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  74. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  75. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  76. },
  77. { /* QUAT TDM */
  78. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  79. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  80. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  81. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  82. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  83. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  84. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  85. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  86. },
  87. { /* QUIN TDM */
  88. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  89. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  90. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  91. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  92. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  93. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  94. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  95. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  96. }
  97. };
  98. /* TDM default config */
  99. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  100. { /* PRI TDM */
  101. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  102. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  103. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  104. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  105. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  106. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  107. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  108. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  109. },
  110. { /* SEC TDM */
  111. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  112. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  113. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  114. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  115. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  116. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  117. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  118. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  119. },
  120. { /* TERT TDM */
  121. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  122. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  123. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  124. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  125. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  126. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  127. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  128. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  129. },
  130. { /* QUAT TDM */
  131. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  132. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  133. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  134. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  135. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  136. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  137. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  138. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  139. },
  140. { /* QUIN TDM */
  141. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  142. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  143. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  144. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  145. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  146. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  147. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  148. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  149. }
  150. };
  151. /* Default configuration of external display BE */
  152. static struct dev_config ext_disp_rx_cfg[] = {
  153. [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  154. };
  155. static struct dev_config usb_rx_cfg = {
  156. .sample_rate = SAMPLING_RATE_48KHZ,
  157. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  158. .channels = 2,
  159. };
  160. static struct dev_config usb_tx_cfg = {
  161. .sample_rate = SAMPLING_RATE_48KHZ,
  162. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  163. .channels = 1,
  164. };
  165. enum {
  166. PRIM_AUX_PCM = 0,
  167. SEC_AUX_PCM,
  168. TERT_AUX_PCM,
  169. QUAT_AUX_PCM,
  170. QUIN_AUX_PCM,
  171. AUX_PCM_MAX,
  172. };
  173. enum {
  174. PCM_I2S_SEL_PRIM = 0,
  175. PCM_I2S_SEL_SEC,
  176. PCM_I2S_SEL_TERT,
  177. PCM_I2S_SEL_QUAT,
  178. PCM_I2S_SEL_QUIN,
  179. PCM_I2S_SEL_MAX,
  180. };
  181. struct mi2s_conf {
  182. struct mutex lock;
  183. u32 ref_cnt;
  184. u32 msm_is_mi2s_master;
  185. u32 msm_is_ext_mclk;
  186. };
  187. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  188. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  189. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  190. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  191. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  192. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  193. };
  194. struct msm_wsa881x_dev_info {
  195. struct device_node *of_node;
  196. u32 index;
  197. };
  198. static struct snd_soc_aux_dev *msm_aux_dev;
  199. static struct snd_soc_codec_conf *msm_codec_conf;
  200. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
  201. static struct wcd_mbhc_config mbhc_cfg = {
  202. .read_fw_bin = false,
  203. .calibration = NULL,
  204. .detect_extn_cable = true,
  205. .mono_stero_detection = false,
  206. .swap_gnd_mic = NULL,
  207. .hs_ext_micbias = true,
  208. .key_code[0] = KEY_MEDIA,
  209. .key_code[1] = KEY_VOICECOMMAND,
  210. .key_code[2] = KEY_VOLUMEUP,
  211. .key_code[3] = KEY_VOLUMEDOWN,
  212. .key_code[4] = 0,
  213. .key_code[5] = 0,
  214. .key_code[6] = 0,
  215. .key_code[7] = 0,
  216. .linein_th = 5000,
  217. .moisture_en = false,
  218. .mbhc_micbias = 0,
  219. .anc_micbias = 0,
  220. .enable_anc_mic_detect = false,
  221. };
  222. static struct dev_config proxy_rx_cfg = {
  223. .sample_rate = SAMPLING_RATE_48KHZ,
  224. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  225. .channels = 2,
  226. };
  227. /* Default configuration of MI2S channels */
  228. static struct dev_config mi2s_rx_cfg[] = {
  229. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  230. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  231. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  232. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  233. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  234. };
  235. static struct dev_config mi2s_tx_cfg[] = {
  236. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  237. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  238. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  239. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  240. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  241. };
  242. static struct dev_config aux_pcm_rx_cfg[] = {
  243. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  244. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  245. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  246. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  247. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  248. };
  249. static struct dev_config aux_pcm_tx_cfg[] = {
  250. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  251. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  252. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  253. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  254. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  255. };
  256. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  257. "Six", "Seven", "Eight"};
  258. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  259. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
  260. "KHZ_32", "KHZ_44P1", "KHZ_48",
  261. "KHZ_96", "KHZ_192"};
  262. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  263. "Five", "Six", "Seven",
  264. "Eight"};
  265. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  266. "S32_LE"};
  267. static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  268. "S32_LE"};
  269. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  270. "Five", "Six", "Seven", "Eight"};
  271. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  272. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  273. "KHZ_44P1", "KHZ_48", "KHZ_96",
  274. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  275. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  276. "Five", "Six", "Seven",
  277. "Eight"};
  278. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  279. "KHZ_16", "KHZ_22P05",
  280. "KHZ_32", "KHZ_44P1", "KHZ_48",
  281. "KHZ_96", "KHZ_192", "KHZ_384"};
  282. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
  283. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  284. "KHZ_192"};
  285. static const char *const qos_text[] = {"Disable", "Enable"};
  286. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  287. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  288. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  289. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  290. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  291. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  292. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  293. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  294. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  295. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  296. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  297. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  298. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  299. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  300. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  301. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  302. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  303. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  304. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  305. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  306. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  307. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  308. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
  309. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
  310. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
  311. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
  312. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
  313. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
  314. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
  315. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
  316. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
  317. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
  318. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  319. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  320. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  321. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  322. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  323. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  324. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  325. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  326. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  328. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  329. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  330. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  331. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  332. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  333. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  334. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  335. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  336. ext_disp_sample_rate_text);
  337. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  338. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  339. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  340. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  341. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  342. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  343. static SOC_ENUM_SINGLE_EXT_DECL(qos_vote, qos_text);
  344. static int qos_vote_status;
  345. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  346. {
  347. AFE_API_VERSION_I2S_CONFIG,
  348. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  349. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  350. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  351. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  352. 0,
  353. },
  354. {
  355. AFE_API_VERSION_I2S_CONFIG,
  356. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  357. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  358. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  359. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  360. 0,
  361. },
  362. {
  363. AFE_API_VERSION_I2S_CONFIG,
  364. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  365. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  366. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  367. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  368. 0,
  369. },
  370. {
  371. AFE_API_VERSION_I2S_CONFIG,
  372. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  373. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  374. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  375. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  376. 0,
  377. },
  378. {
  379. AFE_API_VERSION_I2S_CONFIG,
  380. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  381. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  382. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  383. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  384. 0,
  385. }
  386. };
  387. static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
  388. {
  389. AFE_API_VERSION_I2S_CONFIG,
  390. Q6AFE_LPASS_CLK_ID_MCLK_3,
  391. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  392. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  393. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  394. 0,
  395. },
  396. {
  397. AFE_API_VERSION_I2S_CONFIG,
  398. Q6AFE_LPASS_CLK_ID_MCLK_2,
  399. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  400. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  401. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  402. 0,
  403. },
  404. {
  405. AFE_API_VERSION_I2S_CONFIG,
  406. Q6AFE_LPASS_CLK_ID_MCLK_1,
  407. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  408. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  409. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  410. 0,
  411. },
  412. {
  413. AFE_API_VERSION_I2S_CONFIG,
  414. Q6AFE_LPASS_CLK_ID_MCLK_1,
  415. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  416. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  417. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  418. 0,
  419. },
  420. {
  421. AFE_API_VERSION_I2S_CONFIG,
  422. Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
  423. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  424. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  425. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  426. 0,
  427. }
  428. };
  429. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  430. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  431. struct snd_ctl_elem_value *ucontrol)
  432. {
  433. pr_debug("%s: proxy_rx channels = %d\n",
  434. __func__, proxy_rx_cfg.channels);
  435. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  436. return 0;
  437. }
  438. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  439. struct snd_ctl_elem_value *ucontrol)
  440. {
  441. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  442. pr_debug("%s: proxy_rx channels = %d\n",
  443. __func__, proxy_rx_cfg.channels);
  444. return 1;
  445. }
  446. static int tdm_get_sample_rate(int value)
  447. {
  448. int sample_rate = 0;
  449. switch (value) {
  450. case 0:
  451. sample_rate = SAMPLING_RATE_8KHZ;
  452. break;
  453. case 1:
  454. sample_rate = SAMPLING_RATE_16KHZ;
  455. break;
  456. case 2:
  457. sample_rate = SAMPLING_RATE_32KHZ;
  458. break;
  459. case 3:
  460. sample_rate = SAMPLING_RATE_44P1KHZ;
  461. break;
  462. case 4:
  463. sample_rate = SAMPLING_RATE_48KHZ;
  464. break;
  465. case 5:
  466. sample_rate = SAMPLING_RATE_96KHZ;
  467. break;
  468. case 6:
  469. sample_rate = SAMPLING_RATE_192KHZ;
  470. break;
  471. case 7:
  472. sample_rate = SAMPLING_RATE_352P8KHZ;
  473. break;
  474. case 8:
  475. sample_rate = SAMPLING_RATE_384KHZ;
  476. break;
  477. default:
  478. sample_rate = SAMPLING_RATE_48KHZ;
  479. break;
  480. }
  481. return sample_rate;
  482. }
  483. static int tdm_get_sample_rate_val(int sample_rate)
  484. {
  485. int sample_rate_val = 0;
  486. switch (sample_rate) {
  487. case SAMPLING_RATE_8KHZ:
  488. sample_rate_val = 0;
  489. break;
  490. case SAMPLING_RATE_16KHZ:
  491. sample_rate_val = 1;
  492. break;
  493. case SAMPLING_RATE_32KHZ:
  494. sample_rate_val = 2;
  495. break;
  496. case SAMPLING_RATE_44P1KHZ:
  497. sample_rate_val = 3;
  498. break;
  499. case SAMPLING_RATE_48KHZ:
  500. sample_rate_val = 4;
  501. break;
  502. case SAMPLING_RATE_96KHZ:
  503. sample_rate_val = 5;
  504. break;
  505. case SAMPLING_RATE_192KHZ:
  506. sample_rate_val = 6;
  507. break;
  508. case SAMPLING_RATE_352P8KHZ:
  509. sample_rate_val = 7;
  510. break;
  511. case SAMPLING_RATE_384KHZ:
  512. sample_rate_val = 8;
  513. break;
  514. default:
  515. sample_rate_val = 4;
  516. break;
  517. }
  518. return sample_rate_val;
  519. }
  520. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  521. struct tdm_port *port)
  522. {
  523. if (port) {
  524. if (strnstr(kcontrol->id.name, "PRI",
  525. sizeof(kcontrol->id.name))) {
  526. port->mode = TDM_PRI;
  527. } else if (strnstr(kcontrol->id.name, "SEC",
  528. sizeof(kcontrol->id.name))) {
  529. port->mode = TDM_SEC;
  530. } else if (strnstr(kcontrol->id.name, "TERT",
  531. sizeof(kcontrol->id.name))) {
  532. port->mode = TDM_TERT;
  533. } else if (strnstr(kcontrol->id.name, "QUAT",
  534. sizeof(kcontrol->id.name))) {
  535. port->mode = TDM_QUAT;
  536. } else if (strnstr(kcontrol->id.name, "QUIN",
  537. sizeof(kcontrol->id.name))) {
  538. port->mode = TDM_QUIN;
  539. } else {
  540. pr_err("%s: unsupported mode in: %s",
  541. __func__, kcontrol->id.name);
  542. return -EINVAL;
  543. }
  544. if (strnstr(kcontrol->id.name, "RX_0",
  545. sizeof(kcontrol->id.name)) ||
  546. strnstr(kcontrol->id.name, "TX_0",
  547. sizeof(kcontrol->id.name))) {
  548. port->channel = TDM_0;
  549. } else if (strnstr(kcontrol->id.name, "RX_1",
  550. sizeof(kcontrol->id.name)) ||
  551. strnstr(kcontrol->id.name, "TX_1",
  552. sizeof(kcontrol->id.name))) {
  553. port->channel = TDM_1;
  554. } else if (strnstr(kcontrol->id.name, "RX_2",
  555. sizeof(kcontrol->id.name)) ||
  556. strnstr(kcontrol->id.name, "TX_2",
  557. sizeof(kcontrol->id.name))) {
  558. port->channel = TDM_2;
  559. } else if (strnstr(kcontrol->id.name, "RX_3",
  560. sizeof(kcontrol->id.name)) ||
  561. strnstr(kcontrol->id.name, "TX_3",
  562. sizeof(kcontrol->id.name))) {
  563. port->channel = TDM_3;
  564. } else if (strnstr(kcontrol->id.name, "RX_4",
  565. sizeof(kcontrol->id.name)) ||
  566. strnstr(kcontrol->id.name, "TX_4",
  567. sizeof(kcontrol->id.name))) {
  568. port->channel = TDM_4;
  569. } else if (strnstr(kcontrol->id.name, "RX_5",
  570. sizeof(kcontrol->id.name)) ||
  571. strnstr(kcontrol->id.name, "TX_5",
  572. sizeof(kcontrol->id.name))) {
  573. port->channel = TDM_5;
  574. } else if (strnstr(kcontrol->id.name, "RX_6",
  575. sizeof(kcontrol->id.name)) ||
  576. strnstr(kcontrol->id.name, "TX_6",
  577. sizeof(kcontrol->id.name))) {
  578. port->channel = TDM_6;
  579. } else if (strnstr(kcontrol->id.name, "RX_7",
  580. sizeof(kcontrol->id.name)) ||
  581. strnstr(kcontrol->id.name, "TX_7",
  582. sizeof(kcontrol->id.name))) {
  583. port->channel = TDM_7;
  584. } else {
  585. pr_err("%s: unsupported channel in: %s",
  586. __func__, kcontrol->id.name);
  587. return -EINVAL;
  588. }
  589. } else
  590. return -EINVAL;
  591. return 0;
  592. }
  593. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  594. struct snd_ctl_elem_value *ucontrol)
  595. {
  596. struct tdm_port port;
  597. int ret = tdm_get_port_idx(kcontrol, &port);
  598. if (ret) {
  599. pr_err("%s: unsupported control: %s",
  600. __func__, kcontrol->id.name);
  601. } else {
  602. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  603. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  604. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  605. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  606. ucontrol->value.enumerated.item[0]);
  607. }
  608. return ret;
  609. }
  610. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  611. struct snd_ctl_elem_value *ucontrol)
  612. {
  613. struct tdm_port port;
  614. int ret = tdm_get_port_idx(kcontrol, &port);
  615. if (ret) {
  616. pr_err("%s: unsupported control: %s",
  617. __func__, kcontrol->id.name);
  618. } else {
  619. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  620. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  621. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  622. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  623. ucontrol->value.enumerated.item[0]);
  624. }
  625. return ret;
  626. }
  627. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  628. struct snd_ctl_elem_value *ucontrol)
  629. {
  630. struct tdm_port port;
  631. int ret = tdm_get_port_idx(kcontrol, &port);
  632. if (ret) {
  633. pr_err("%s: unsupported control: %s",
  634. __func__, kcontrol->id.name);
  635. } else {
  636. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  637. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  638. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  639. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  640. ucontrol->value.enumerated.item[0]);
  641. }
  642. return ret;
  643. }
  644. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  645. struct snd_ctl_elem_value *ucontrol)
  646. {
  647. struct tdm_port port;
  648. int ret = tdm_get_port_idx(kcontrol, &port);
  649. if (ret) {
  650. pr_err("%s: unsupported control: %s",
  651. __func__, kcontrol->id.name);
  652. } else {
  653. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  654. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  655. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  656. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  657. ucontrol->value.enumerated.item[0]);
  658. }
  659. return ret;
  660. }
  661. static int tdm_get_format(int value)
  662. {
  663. int format = 0;
  664. switch (value) {
  665. case 0:
  666. format = SNDRV_PCM_FORMAT_S16_LE;
  667. break;
  668. case 1:
  669. format = SNDRV_PCM_FORMAT_S24_LE;
  670. break;
  671. case 2:
  672. format = SNDRV_PCM_FORMAT_S32_LE;
  673. break;
  674. default:
  675. format = SNDRV_PCM_FORMAT_S16_LE;
  676. break;
  677. }
  678. return format;
  679. }
  680. static int tdm_get_format_val(int format)
  681. {
  682. int value = 0;
  683. switch (format) {
  684. case SNDRV_PCM_FORMAT_S16_LE:
  685. value = 0;
  686. break;
  687. case SNDRV_PCM_FORMAT_S24_LE:
  688. value = 1;
  689. break;
  690. case SNDRV_PCM_FORMAT_S32_LE:
  691. value = 2;
  692. break;
  693. default:
  694. value = 0;
  695. break;
  696. }
  697. return value;
  698. }
  699. static int mi2s_get_format(int value)
  700. {
  701. int format = 0;
  702. switch (value) {
  703. case 0:
  704. format = SNDRV_PCM_FORMAT_S16_LE;
  705. break;
  706. case 1:
  707. format = SNDRV_PCM_FORMAT_S24_LE;
  708. break;
  709. case 2:
  710. format = SNDRV_PCM_FORMAT_S24_3LE;
  711. break;
  712. case 3:
  713. format = SNDRV_PCM_FORMAT_S32_LE;
  714. break;
  715. default:
  716. format = SNDRV_PCM_FORMAT_S16_LE;
  717. break;
  718. }
  719. return format;
  720. }
  721. static int mi2s_get_format_value(int format)
  722. {
  723. int value = 0;
  724. switch (format) {
  725. case SNDRV_PCM_FORMAT_S16_LE:
  726. value = 0;
  727. break;
  728. case SNDRV_PCM_FORMAT_S24_LE:
  729. value = 1;
  730. break;
  731. case SNDRV_PCM_FORMAT_S24_3LE:
  732. value = 2;
  733. break;
  734. case SNDRV_PCM_FORMAT_S32_LE:
  735. value = 3;
  736. break;
  737. default:
  738. value = 0;
  739. break;
  740. }
  741. return value;
  742. }
  743. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  744. struct snd_ctl_elem_value *ucontrol)
  745. {
  746. struct tdm_port port;
  747. int ret = tdm_get_port_idx(kcontrol, &port);
  748. if (ret) {
  749. pr_err("%s: unsupported control: %s",
  750. __func__, kcontrol->id.name);
  751. } else {
  752. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  753. tdm_rx_cfg[port.mode][port.channel].bit_format);
  754. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  755. tdm_rx_cfg[port.mode][port.channel].bit_format,
  756. ucontrol->value.enumerated.item[0]);
  757. }
  758. return ret;
  759. }
  760. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  761. struct snd_ctl_elem_value *ucontrol)
  762. {
  763. struct tdm_port port;
  764. int ret = tdm_get_port_idx(kcontrol, &port);
  765. if (ret) {
  766. pr_err("%s: unsupported control: %s",
  767. __func__, kcontrol->id.name);
  768. } else {
  769. tdm_rx_cfg[port.mode][port.channel].bit_format =
  770. tdm_get_format(ucontrol->value.enumerated.item[0]);
  771. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  772. tdm_rx_cfg[port.mode][port.channel].bit_format,
  773. ucontrol->value.enumerated.item[0]);
  774. }
  775. return ret;
  776. }
  777. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  778. struct snd_ctl_elem_value *ucontrol)
  779. {
  780. struct tdm_port port;
  781. int ret = tdm_get_port_idx(kcontrol, &port);
  782. if (ret) {
  783. pr_err("%s: unsupported control: %s",
  784. __func__, kcontrol->id.name);
  785. } else {
  786. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  787. tdm_tx_cfg[port.mode][port.channel].bit_format);
  788. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  789. tdm_tx_cfg[port.mode][port.channel].bit_format,
  790. ucontrol->value.enumerated.item[0]);
  791. }
  792. return ret;
  793. }
  794. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. struct tdm_port port;
  798. int ret = tdm_get_port_idx(kcontrol, &port);
  799. if (ret) {
  800. pr_err("%s: unsupported control: %s",
  801. __func__, kcontrol->id.name);
  802. } else {
  803. tdm_tx_cfg[port.mode][port.channel].bit_format =
  804. tdm_get_format(ucontrol->value.enumerated.item[0]);
  805. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  806. tdm_tx_cfg[port.mode][port.channel].bit_format,
  807. ucontrol->value.enumerated.item[0]);
  808. }
  809. return ret;
  810. }
  811. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  812. struct snd_ctl_elem_value *ucontrol)
  813. {
  814. struct tdm_port port;
  815. int ret = tdm_get_port_idx(kcontrol, &port);
  816. if (ret) {
  817. pr_err("%s: unsupported control: %s",
  818. __func__, kcontrol->id.name);
  819. } else {
  820. ucontrol->value.enumerated.item[0] =
  821. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  822. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  823. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  824. ucontrol->value.enumerated.item[0]);
  825. }
  826. return ret;
  827. }
  828. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. struct tdm_port port;
  832. int ret = tdm_get_port_idx(kcontrol, &port);
  833. if (ret) {
  834. pr_err("%s: unsupported control: %s",
  835. __func__, kcontrol->id.name);
  836. } else {
  837. tdm_rx_cfg[port.mode][port.channel].channels =
  838. ucontrol->value.enumerated.item[0] + 1;
  839. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  840. tdm_rx_cfg[port.mode][port.channel].channels,
  841. ucontrol->value.enumerated.item[0] + 1);
  842. }
  843. return ret;
  844. }
  845. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. struct tdm_port port;
  849. int ret = tdm_get_port_idx(kcontrol, &port);
  850. if (ret) {
  851. pr_err("%s: unsupported control: %s",
  852. __func__, kcontrol->id.name);
  853. } else {
  854. ucontrol->value.enumerated.item[0] =
  855. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  856. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  857. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  858. ucontrol->value.enumerated.item[0]);
  859. }
  860. return ret;
  861. }
  862. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  863. struct snd_ctl_elem_value *ucontrol)
  864. {
  865. struct tdm_port port;
  866. int ret = tdm_get_port_idx(kcontrol, &port);
  867. if (ret) {
  868. pr_err("%s: unsupported control: %s",
  869. __func__, kcontrol->id.name);
  870. } else {
  871. tdm_tx_cfg[port.mode][port.channel].channels =
  872. ucontrol->value.enumerated.item[0] + 1;
  873. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  874. tdm_tx_cfg[port.mode][port.channel].channels,
  875. ucontrol->value.enumerated.item[0] + 1);
  876. }
  877. return ret;
  878. }
  879. static int aux_pcm_get_sample_rate(int value)
  880. {
  881. int sample_rate;
  882. switch (value) {
  883. case 1:
  884. sample_rate = SAMPLING_RATE_16KHZ;
  885. break;
  886. case 0:
  887. default:
  888. sample_rate = SAMPLING_RATE_8KHZ;
  889. break;
  890. }
  891. return sample_rate;
  892. }
  893. static int aux_pcm_get_sample_rate_val(int sample_rate)
  894. {
  895. int sample_rate_val;
  896. switch (sample_rate) {
  897. case SAMPLING_RATE_16KHZ:
  898. sample_rate_val = 1;
  899. break;
  900. case SAMPLING_RATE_8KHZ:
  901. default:
  902. sample_rate_val = 0;
  903. break;
  904. }
  905. return sample_rate_val;
  906. }
  907. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  908. {
  909. int idx;
  910. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  911. sizeof("PRIM_AUX_PCM")))
  912. idx = PRIM_AUX_PCM;
  913. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  914. sizeof("SEC_AUX_PCM")))
  915. idx = SEC_AUX_PCM;
  916. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  917. sizeof("TERT_AUX_PCM")))
  918. idx = TERT_AUX_PCM;
  919. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  920. sizeof("QUAT_AUX_PCM")))
  921. idx = QUAT_AUX_PCM;
  922. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  923. sizeof("QUIN_AUX_PCM")))
  924. idx = QUIN_AUX_PCM;
  925. else {
  926. pr_err("%s: unsupported port: %s",
  927. __func__, kcontrol->id.name);
  928. idx = -EINVAL;
  929. }
  930. return idx;
  931. }
  932. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. int idx = aux_pcm_get_port_idx(kcontrol);
  936. if (idx < 0)
  937. return idx;
  938. aux_pcm_rx_cfg[idx].sample_rate =
  939. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  940. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  941. idx, aux_pcm_rx_cfg[idx].sample_rate,
  942. ucontrol->value.enumerated.item[0]);
  943. return 0;
  944. }
  945. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  946. struct snd_ctl_elem_value *ucontrol)
  947. {
  948. int idx = aux_pcm_get_port_idx(kcontrol);
  949. if (idx < 0)
  950. return idx;
  951. ucontrol->value.enumerated.item[0] =
  952. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  953. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  954. idx, aux_pcm_rx_cfg[idx].sample_rate,
  955. ucontrol->value.enumerated.item[0]);
  956. return 0;
  957. }
  958. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. int idx = aux_pcm_get_port_idx(kcontrol);
  962. if (idx < 0)
  963. return idx;
  964. aux_pcm_tx_cfg[idx].sample_rate =
  965. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  966. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  967. idx, aux_pcm_tx_cfg[idx].sample_rate,
  968. ucontrol->value.enumerated.item[0]);
  969. return 0;
  970. }
  971. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  972. struct snd_ctl_elem_value *ucontrol)
  973. {
  974. int idx = aux_pcm_get_port_idx(kcontrol);
  975. if (idx < 0)
  976. return idx;
  977. ucontrol->value.enumerated.item[0] =
  978. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  979. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  980. idx, aux_pcm_tx_cfg[idx].sample_rate,
  981. ucontrol->value.enumerated.item[0]);
  982. return 0;
  983. }
  984. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  985. {
  986. int idx;
  987. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  988. sizeof("PRIM_MI2S_RX")))
  989. idx = PRIM_MI2S;
  990. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  991. sizeof("SEC_MI2S_RX")))
  992. idx = SEC_MI2S;
  993. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  994. sizeof("TERT_MI2S_RX")))
  995. idx = TERT_MI2S;
  996. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  997. sizeof("QUAT_MI2S_RX")))
  998. idx = QUAT_MI2S;
  999. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1000. sizeof("QUIN_MI2S_RX")))
  1001. idx = QUIN_MI2S;
  1002. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1003. sizeof("PRIM_MI2S_TX")))
  1004. idx = PRIM_MI2S;
  1005. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1006. sizeof("SEC_MI2S_TX")))
  1007. idx = SEC_MI2S;
  1008. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1009. sizeof("TERT_MI2S_TX")))
  1010. idx = TERT_MI2S;
  1011. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1012. sizeof("QUAT_MI2S_TX")))
  1013. idx = QUAT_MI2S;
  1014. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1015. sizeof("QUIN_MI2S_TX")))
  1016. idx = QUIN_MI2S;
  1017. else {
  1018. pr_err("%s: unsupported channel: %s",
  1019. __func__, kcontrol->id.name);
  1020. idx = -EINVAL;
  1021. }
  1022. return idx;
  1023. }
  1024. static int mi2s_get_sample_rate_val(int sample_rate)
  1025. {
  1026. int sample_rate_val;
  1027. switch (sample_rate) {
  1028. case SAMPLING_RATE_8KHZ:
  1029. sample_rate_val = 0;
  1030. break;
  1031. case SAMPLING_RATE_16KHZ:
  1032. sample_rate_val = 1;
  1033. break;
  1034. case SAMPLING_RATE_32KHZ:
  1035. sample_rate_val = 2;
  1036. break;
  1037. case SAMPLING_RATE_44P1KHZ:
  1038. sample_rate_val = 3;
  1039. break;
  1040. case SAMPLING_RATE_48KHZ:
  1041. sample_rate_val = 4;
  1042. break;
  1043. case SAMPLING_RATE_96KHZ:
  1044. sample_rate_val = 5;
  1045. break;
  1046. case SAMPLING_RATE_192KHZ:
  1047. sample_rate_val = 6;
  1048. break;
  1049. default:
  1050. sample_rate_val = 4;
  1051. break;
  1052. }
  1053. return sample_rate_val;
  1054. }
  1055. static int mi2s_get_sample_rate(int value)
  1056. {
  1057. int sample_rate;
  1058. switch (value) {
  1059. case 0:
  1060. sample_rate = SAMPLING_RATE_8KHZ;
  1061. break;
  1062. case 1:
  1063. sample_rate = SAMPLING_RATE_16KHZ;
  1064. break;
  1065. case 2:
  1066. sample_rate = SAMPLING_RATE_32KHZ;
  1067. break;
  1068. case 3:
  1069. sample_rate = SAMPLING_RATE_44P1KHZ;
  1070. break;
  1071. case 4:
  1072. sample_rate = SAMPLING_RATE_48KHZ;
  1073. break;
  1074. case 5:
  1075. sample_rate = SAMPLING_RATE_96KHZ;
  1076. break;
  1077. case 6:
  1078. sample_rate = SAMPLING_RATE_192KHZ;
  1079. break;
  1080. default:
  1081. sample_rate = SAMPLING_RATE_48KHZ;
  1082. break;
  1083. }
  1084. return sample_rate;
  1085. }
  1086. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1087. struct snd_ctl_elem_value *ucontrol)
  1088. {
  1089. int idx = mi2s_get_port_idx(kcontrol);
  1090. if (idx < 0)
  1091. return idx;
  1092. mi2s_rx_cfg[idx].sample_rate =
  1093. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1094. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1095. idx, mi2s_rx_cfg[idx].sample_rate,
  1096. ucontrol->value.enumerated.item[0]);
  1097. return 0;
  1098. }
  1099. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1100. struct snd_ctl_elem_value *ucontrol)
  1101. {
  1102. int idx = mi2s_get_port_idx(kcontrol);
  1103. if (idx < 0)
  1104. return idx;
  1105. ucontrol->value.enumerated.item[0] =
  1106. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1107. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1108. idx, mi2s_rx_cfg[idx].sample_rate,
  1109. ucontrol->value.enumerated.item[0]);
  1110. return 0;
  1111. }
  1112. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1113. struct snd_ctl_elem_value *ucontrol)
  1114. {
  1115. int idx = mi2s_get_port_idx(kcontrol);
  1116. if (idx < 0)
  1117. return idx;
  1118. mi2s_tx_cfg[idx].sample_rate =
  1119. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1120. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1121. idx, mi2s_tx_cfg[idx].sample_rate,
  1122. ucontrol->value.enumerated.item[0]);
  1123. return 0;
  1124. }
  1125. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1126. struct snd_ctl_elem_value *ucontrol)
  1127. {
  1128. int idx = mi2s_get_port_idx(kcontrol);
  1129. if (idx < 0)
  1130. return idx;
  1131. ucontrol->value.enumerated.item[0] =
  1132. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1133. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1134. idx, mi2s_tx_cfg[idx].sample_rate,
  1135. ucontrol->value.enumerated.item[0]);
  1136. return 0;
  1137. }
  1138. static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1139. struct snd_ctl_elem_value *ucontrol)
  1140. {
  1141. int idx = mi2s_get_port_idx(kcontrol);
  1142. if (idx < 0)
  1143. return idx;
  1144. mi2s_tx_cfg[idx].bit_format =
  1145. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1146. pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
  1147. idx, mi2s_tx_cfg[idx].bit_format,
  1148. ucontrol->value.enumerated.item[0]);
  1149. return 0;
  1150. }
  1151. static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1152. struct snd_ctl_elem_value *ucontrol)
  1153. {
  1154. int idx = mi2s_get_port_idx(kcontrol);
  1155. if (idx < 0)
  1156. return idx;
  1157. ucontrol->value.enumerated.item[0] =
  1158. mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1159. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1160. idx, mi2s_tx_cfg[idx].bit_format,
  1161. ucontrol->value.enumerated.item[0]);
  1162. return 0;
  1163. }
  1164. static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1165. struct snd_ctl_elem_value *ucontrol)
  1166. {
  1167. int idx = mi2s_get_port_idx(kcontrol);
  1168. if (idx < 0)
  1169. return idx;
  1170. mi2s_rx_cfg[idx].bit_format =
  1171. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1172. pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
  1173. idx, mi2s_rx_cfg[idx].bit_format,
  1174. ucontrol->value.enumerated.item[0]);
  1175. return 0;
  1176. }
  1177. static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1178. struct snd_ctl_elem_value *ucontrol)
  1179. {
  1180. int idx = mi2s_get_port_idx(kcontrol);
  1181. if (idx < 0)
  1182. return idx;
  1183. ucontrol->value.enumerated.item[0] =
  1184. mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1185. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1186. idx, mi2s_rx_cfg[idx].bit_format,
  1187. ucontrol->value.enumerated.item[0]);
  1188. return 0;
  1189. }
  1190. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1191. struct snd_ctl_elem_value *ucontrol)
  1192. {
  1193. int idx = mi2s_get_port_idx(kcontrol);
  1194. if (idx < 0)
  1195. return idx;
  1196. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1197. idx, mi2s_rx_cfg[idx].channels);
  1198. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1199. return 0;
  1200. }
  1201. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1202. struct snd_ctl_elem_value *ucontrol)
  1203. {
  1204. int idx = mi2s_get_port_idx(kcontrol);
  1205. if (idx < 0)
  1206. return idx;
  1207. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1208. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1209. idx, mi2s_rx_cfg[idx].channels);
  1210. return 1;
  1211. }
  1212. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1213. struct snd_ctl_elem_value *ucontrol)
  1214. {
  1215. int idx = mi2s_get_port_idx(kcontrol);
  1216. if (idx < 0)
  1217. return idx;
  1218. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1219. idx, mi2s_tx_cfg[idx].channels);
  1220. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1221. return 0;
  1222. }
  1223. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1224. struct snd_ctl_elem_value *ucontrol)
  1225. {
  1226. int idx = mi2s_get_port_idx(kcontrol);
  1227. if (idx < 0)
  1228. return idx;
  1229. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1230. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1231. idx, mi2s_tx_cfg[idx].channels);
  1232. return 1;
  1233. }
  1234. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1235. struct snd_ctl_elem_value *ucontrol)
  1236. {
  1237. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1238. usb_rx_cfg.channels);
  1239. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1240. return 0;
  1241. }
  1242. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1243. struct snd_ctl_elem_value *ucontrol)
  1244. {
  1245. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1246. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1247. return 1;
  1248. }
  1249. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1250. struct snd_ctl_elem_value *ucontrol)
  1251. {
  1252. int sample_rate_val;
  1253. switch (usb_rx_cfg.sample_rate) {
  1254. case SAMPLING_RATE_384KHZ:
  1255. sample_rate_val = 9;
  1256. break;
  1257. case SAMPLING_RATE_192KHZ:
  1258. sample_rate_val = 8;
  1259. break;
  1260. case SAMPLING_RATE_96KHZ:
  1261. sample_rate_val = 7;
  1262. break;
  1263. case SAMPLING_RATE_48KHZ:
  1264. sample_rate_val = 6;
  1265. break;
  1266. case SAMPLING_RATE_44P1KHZ:
  1267. sample_rate_val = 5;
  1268. break;
  1269. case SAMPLING_RATE_32KHZ:
  1270. sample_rate_val = 4;
  1271. break;
  1272. case SAMPLING_RATE_22P05KHZ:
  1273. sample_rate_val = 3;
  1274. break;
  1275. case SAMPLING_RATE_16KHZ:
  1276. sample_rate_val = 2;
  1277. break;
  1278. case SAMPLING_RATE_11P025KHZ:
  1279. sample_rate_val = 1;
  1280. break;
  1281. case SAMPLING_RATE_8KHZ:
  1282. default:
  1283. sample_rate_val = 0;
  1284. break;
  1285. }
  1286. ucontrol->value.integer.value[0] = sample_rate_val;
  1287. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1288. usb_rx_cfg.sample_rate);
  1289. return 0;
  1290. }
  1291. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1292. struct snd_ctl_elem_value *ucontrol)
  1293. {
  1294. switch (ucontrol->value.integer.value[0]) {
  1295. case 9:
  1296. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1297. break;
  1298. case 8:
  1299. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1300. break;
  1301. case 7:
  1302. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1303. break;
  1304. case 6:
  1305. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1306. break;
  1307. case 5:
  1308. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1309. break;
  1310. case 4:
  1311. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1312. break;
  1313. case 3:
  1314. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1315. break;
  1316. case 2:
  1317. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1318. break;
  1319. case 1:
  1320. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1321. break;
  1322. case 0:
  1323. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1324. break;
  1325. default:
  1326. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1327. break;
  1328. }
  1329. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1330. __func__, ucontrol->value.integer.value[0],
  1331. usb_rx_cfg.sample_rate);
  1332. return 0;
  1333. }
  1334. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1335. struct snd_ctl_elem_value *ucontrol)
  1336. {
  1337. switch (usb_rx_cfg.bit_format) {
  1338. case SNDRV_PCM_FORMAT_S32_LE:
  1339. ucontrol->value.integer.value[0] = 3;
  1340. break;
  1341. case SNDRV_PCM_FORMAT_S24_3LE:
  1342. ucontrol->value.integer.value[0] = 2;
  1343. break;
  1344. case SNDRV_PCM_FORMAT_S24_LE:
  1345. ucontrol->value.integer.value[0] = 1;
  1346. break;
  1347. case SNDRV_PCM_FORMAT_S16_LE:
  1348. default:
  1349. ucontrol->value.integer.value[0] = 0;
  1350. break;
  1351. }
  1352. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1353. __func__, usb_rx_cfg.bit_format,
  1354. ucontrol->value.integer.value[0]);
  1355. return 0;
  1356. }
  1357. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1358. struct snd_ctl_elem_value *ucontrol)
  1359. {
  1360. int rc = 0;
  1361. switch (ucontrol->value.integer.value[0]) {
  1362. case 3:
  1363. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1364. break;
  1365. case 2:
  1366. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1367. break;
  1368. case 1:
  1369. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1370. break;
  1371. case 0:
  1372. default:
  1373. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1374. break;
  1375. }
  1376. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1377. __func__, usb_rx_cfg.bit_format,
  1378. ucontrol->value.integer.value[0]);
  1379. return rc;
  1380. }
  1381. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1382. struct snd_ctl_elem_value *ucontrol)
  1383. {
  1384. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1385. usb_tx_cfg.channels);
  1386. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1387. return 0;
  1388. }
  1389. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1390. struct snd_ctl_elem_value *ucontrol)
  1391. {
  1392. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1393. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1394. return 1;
  1395. }
  1396. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1397. struct snd_ctl_elem_value *ucontrol)
  1398. {
  1399. int sample_rate_val;
  1400. switch (usb_tx_cfg.sample_rate) {
  1401. case SAMPLING_RATE_384KHZ:
  1402. sample_rate_val = 9;
  1403. break;
  1404. case SAMPLING_RATE_192KHZ:
  1405. sample_rate_val = 8;
  1406. break;
  1407. case SAMPLING_RATE_96KHZ:
  1408. sample_rate_val = 7;
  1409. break;
  1410. case SAMPLING_RATE_48KHZ:
  1411. sample_rate_val = 6;
  1412. break;
  1413. case SAMPLING_RATE_44P1KHZ:
  1414. sample_rate_val = 5;
  1415. break;
  1416. case SAMPLING_RATE_32KHZ:
  1417. sample_rate_val = 4;
  1418. break;
  1419. case SAMPLING_RATE_22P05KHZ:
  1420. sample_rate_val = 3;
  1421. break;
  1422. case SAMPLING_RATE_16KHZ:
  1423. sample_rate_val = 2;
  1424. break;
  1425. case SAMPLING_RATE_11P025KHZ:
  1426. sample_rate_val = 1;
  1427. break;
  1428. case SAMPLING_RATE_8KHZ:
  1429. sample_rate_val = 0;
  1430. break;
  1431. default:
  1432. sample_rate_val = 6;
  1433. break;
  1434. }
  1435. ucontrol->value.integer.value[0] = sample_rate_val;
  1436. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1437. usb_tx_cfg.sample_rate);
  1438. return 0;
  1439. }
  1440. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1441. struct snd_ctl_elem_value *ucontrol)
  1442. {
  1443. switch (ucontrol->value.integer.value[0]) {
  1444. case 9:
  1445. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1446. break;
  1447. case 8:
  1448. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1449. break;
  1450. case 7:
  1451. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1452. break;
  1453. case 6:
  1454. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1455. break;
  1456. case 5:
  1457. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1458. break;
  1459. case 4:
  1460. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1461. break;
  1462. case 3:
  1463. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1464. break;
  1465. case 2:
  1466. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1467. break;
  1468. case 1:
  1469. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1470. break;
  1471. case 0:
  1472. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1473. break;
  1474. default:
  1475. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1476. break;
  1477. }
  1478. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1479. __func__, ucontrol->value.integer.value[0],
  1480. usb_tx_cfg.sample_rate);
  1481. return 0;
  1482. }
  1483. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1484. struct snd_ctl_elem_value *ucontrol)
  1485. {
  1486. switch (usb_tx_cfg.bit_format) {
  1487. case SNDRV_PCM_FORMAT_S32_LE:
  1488. ucontrol->value.integer.value[0] = 3;
  1489. break;
  1490. case SNDRV_PCM_FORMAT_S24_3LE:
  1491. ucontrol->value.integer.value[0] = 2;
  1492. break;
  1493. case SNDRV_PCM_FORMAT_S24_LE:
  1494. ucontrol->value.integer.value[0] = 1;
  1495. break;
  1496. case SNDRV_PCM_FORMAT_S16_LE:
  1497. default:
  1498. ucontrol->value.integer.value[0] = 0;
  1499. break;
  1500. }
  1501. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1502. __func__, usb_tx_cfg.bit_format,
  1503. ucontrol->value.integer.value[0]);
  1504. return 0;
  1505. }
  1506. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1507. struct snd_ctl_elem_value *ucontrol)
  1508. {
  1509. int rc = 0;
  1510. switch (ucontrol->value.integer.value[0]) {
  1511. case 3:
  1512. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1513. break;
  1514. case 2:
  1515. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1516. break;
  1517. case 1:
  1518. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1519. break;
  1520. case 0:
  1521. default:
  1522. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1523. break;
  1524. }
  1525. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1526. __func__, usb_tx_cfg.bit_format,
  1527. ucontrol->value.integer.value[0]);
  1528. return rc;
  1529. }
  1530. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1531. {
  1532. int idx;
  1533. if (strnstr(kcontrol->id.name, "Display Port RX",
  1534. sizeof("Display Port RX")))
  1535. idx = DP_RX_IDX;
  1536. else {
  1537. pr_err("%s: unsupported BE: %s",
  1538. __func__, kcontrol->id.name);
  1539. idx = -EINVAL;
  1540. }
  1541. return idx;
  1542. }
  1543. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. int idx = ext_disp_get_port_idx(kcontrol);
  1547. if (idx < 0)
  1548. return idx;
  1549. switch (ext_disp_rx_cfg[idx].bit_format) {
  1550. case SNDRV_PCM_FORMAT_S24_LE:
  1551. ucontrol->value.integer.value[0] = 1;
  1552. break;
  1553. case SNDRV_PCM_FORMAT_S16_LE:
  1554. default:
  1555. ucontrol->value.integer.value[0] = 0;
  1556. break;
  1557. }
  1558. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1559. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1560. ucontrol->value.integer.value[0]);
  1561. return 0;
  1562. }
  1563. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1564. struct snd_ctl_elem_value *ucontrol)
  1565. {
  1566. int idx = ext_disp_get_port_idx(kcontrol);
  1567. if (idx < 0)
  1568. return idx;
  1569. switch (ucontrol->value.integer.value[0]) {
  1570. case 1:
  1571. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1572. break;
  1573. case 0:
  1574. default:
  1575. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1576. break;
  1577. }
  1578. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1579. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1580. ucontrol->value.integer.value[0]);
  1581. return 0;
  1582. }
  1583. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. int idx = ext_disp_get_port_idx(kcontrol);
  1587. if (idx < 0)
  1588. return idx;
  1589. ucontrol->value.integer.value[0] =
  1590. ext_disp_rx_cfg[idx].channels - 2;
  1591. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1592. idx, ext_disp_rx_cfg[idx].channels);
  1593. return 0;
  1594. }
  1595. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_value *ucontrol)
  1597. {
  1598. int idx = ext_disp_get_port_idx(kcontrol);
  1599. if (idx < 0)
  1600. return idx;
  1601. ext_disp_rx_cfg[idx].channels =
  1602. ucontrol->value.integer.value[0] + 2;
  1603. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1604. idx, ext_disp_rx_cfg[idx].channels);
  1605. return 1;
  1606. }
  1607. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1608. struct snd_ctl_elem_value *ucontrol)
  1609. {
  1610. int sample_rate_val;
  1611. int idx = ext_disp_get_port_idx(kcontrol);
  1612. if (idx < 0)
  1613. return idx;
  1614. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1615. case SAMPLING_RATE_192KHZ:
  1616. sample_rate_val = 2;
  1617. break;
  1618. case SAMPLING_RATE_96KHZ:
  1619. sample_rate_val = 1;
  1620. break;
  1621. case SAMPLING_RATE_48KHZ:
  1622. default:
  1623. sample_rate_val = 0;
  1624. break;
  1625. }
  1626. ucontrol->value.integer.value[0] = sample_rate_val;
  1627. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1628. idx, ext_disp_rx_cfg[idx].sample_rate);
  1629. return 0;
  1630. }
  1631. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1632. struct snd_ctl_elem_value *ucontrol)
  1633. {
  1634. int idx = ext_disp_get_port_idx(kcontrol);
  1635. if (idx < 0)
  1636. return idx;
  1637. switch (ucontrol->value.integer.value[0]) {
  1638. case 2:
  1639. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1640. break;
  1641. case 1:
  1642. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1643. break;
  1644. case 0:
  1645. default:
  1646. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1647. break;
  1648. }
  1649. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1650. __func__, ucontrol->value.integer.value[0], idx,
  1651. ext_disp_rx_cfg[idx].sample_rate);
  1652. return 0;
  1653. }
  1654. static int msm_qos_ctl_get(struct snd_kcontrol *kcontrol,
  1655. struct snd_ctl_elem_value *ucontrol)
  1656. {
  1657. ucontrol->value.enumerated.item[0] = qos_vote_status;
  1658. return 0;
  1659. }
  1660. static int msm_qos_ctl_put(struct snd_kcontrol *kcontrol,
  1661. struct snd_ctl_elem_value *ucontrol)
  1662. {
  1663. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  1664. struct snd_soc_card *card = codec->component.card;
  1665. const char *fe_name = MSM_DAILINK_NAME(LowLatency);
  1666. struct snd_soc_pcm_runtime *rtd;
  1667. struct snd_pcm_substream *substream;
  1668. s32 usecs;
  1669. rtd = snd_soc_get_pcm_runtime(card, fe_name);
  1670. if (!rtd) {
  1671. pr_err("%s: fail to get pcm runtime for %s\n",
  1672. __func__, fe_name);
  1673. return -EINVAL;
  1674. }
  1675. substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1676. if (!substream) {
  1677. pr_err("%s: substream is null\n", __func__);
  1678. return -EINVAL;
  1679. }
  1680. qos_vote_status = ucontrol->value.enumerated.item[0];
  1681. if (qos_vote_status) {
  1682. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  1683. pm_qos_remove_request(&substream->latency_pm_qos_req);
  1684. if (!substream->runtime) {
  1685. pr_err("%s: runtime is null\n", __func__);
  1686. return -EINVAL;
  1687. }
  1688. usecs = MSM_LL_QOS_VALUE;
  1689. if (usecs >= 0)
  1690. pm_qos_add_request(&substream->latency_pm_qos_req,
  1691. PM_QOS_CPU_DMA_LATENCY, usecs);
  1692. } else {
  1693. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  1694. pm_qos_remove_request(&substream->latency_pm_qos_req);
  1695. }
  1696. return 0;
  1697. }
  1698. const struct snd_kcontrol_new msm_common_snd_controls[] = {
  1699. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  1700. proxy_rx_ch_get, proxy_rx_ch_put),
  1701. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  1702. aux_pcm_rx_sample_rate_get,
  1703. aux_pcm_rx_sample_rate_put),
  1704. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  1705. aux_pcm_rx_sample_rate_get,
  1706. aux_pcm_rx_sample_rate_put),
  1707. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  1708. aux_pcm_rx_sample_rate_get,
  1709. aux_pcm_rx_sample_rate_put),
  1710. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  1711. aux_pcm_rx_sample_rate_get,
  1712. aux_pcm_rx_sample_rate_put),
  1713. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  1714. aux_pcm_rx_sample_rate_get,
  1715. aux_pcm_rx_sample_rate_put),
  1716. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  1717. aux_pcm_tx_sample_rate_get,
  1718. aux_pcm_tx_sample_rate_put),
  1719. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  1720. aux_pcm_tx_sample_rate_get,
  1721. aux_pcm_tx_sample_rate_put),
  1722. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  1723. aux_pcm_tx_sample_rate_get,
  1724. aux_pcm_tx_sample_rate_put),
  1725. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  1726. aux_pcm_tx_sample_rate_get,
  1727. aux_pcm_tx_sample_rate_put),
  1728. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  1729. aux_pcm_tx_sample_rate_get,
  1730. aux_pcm_tx_sample_rate_put),
  1731. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  1732. mi2s_rx_sample_rate_get,
  1733. mi2s_rx_sample_rate_put),
  1734. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  1735. mi2s_rx_sample_rate_get,
  1736. mi2s_rx_sample_rate_put),
  1737. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  1738. mi2s_rx_sample_rate_get,
  1739. mi2s_rx_sample_rate_put),
  1740. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  1741. mi2s_rx_sample_rate_get,
  1742. mi2s_rx_sample_rate_put),
  1743. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  1744. mi2s_rx_sample_rate_get,
  1745. mi2s_rx_sample_rate_put),
  1746. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  1747. mi2s_tx_sample_rate_get,
  1748. mi2s_tx_sample_rate_put),
  1749. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  1750. mi2s_tx_sample_rate_get,
  1751. mi2s_tx_sample_rate_put),
  1752. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  1753. mi2s_tx_sample_rate_get,
  1754. mi2s_tx_sample_rate_put),
  1755. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  1756. mi2s_tx_sample_rate_get,
  1757. mi2s_tx_sample_rate_put),
  1758. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  1759. mi2s_tx_sample_rate_get,
  1760. mi2s_tx_sample_rate_put),
  1761. SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
  1762. mi2s_rx_format_get,
  1763. mi2s_rx_format_put),
  1764. SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
  1765. mi2s_rx_format_get,
  1766. mi2s_rx_format_put),
  1767. SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
  1768. mi2s_rx_format_get,
  1769. mi2s_rx_format_put),
  1770. SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
  1771. mi2s_rx_format_get,
  1772. mi2s_rx_format_put),
  1773. SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
  1774. mi2s_rx_format_get,
  1775. mi2s_rx_format_put),
  1776. SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
  1777. mi2s_tx_format_get,
  1778. mi2s_tx_format_put),
  1779. SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
  1780. mi2s_tx_format_get,
  1781. mi2s_tx_format_put),
  1782. SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
  1783. mi2s_tx_format_get,
  1784. mi2s_tx_format_put),
  1785. SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
  1786. mi2s_tx_format_get,
  1787. mi2s_tx_format_put),
  1788. SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
  1789. mi2s_tx_format_get,
  1790. mi2s_tx_format_put),
  1791. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  1792. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1793. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  1794. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1795. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  1796. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1797. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  1798. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1799. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  1800. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1801. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  1802. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1803. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  1804. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1805. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  1806. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1807. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  1808. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1809. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  1810. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1811. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  1812. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  1813. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  1814. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  1815. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  1816. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  1817. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  1818. usb_audio_rx_format_get, usb_audio_rx_format_put),
  1819. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  1820. usb_audio_tx_format_get, usb_audio_tx_format_put),
  1821. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  1822. ext_disp_rx_format_get, ext_disp_rx_format_put),
  1823. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  1824. usb_audio_rx_sample_rate_get,
  1825. usb_audio_rx_sample_rate_put),
  1826. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  1827. usb_audio_tx_sample_rate_get,
  1828. usb_audio_tx_sample_rate_put),
  1829. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  1830. ext_disp_rx_sample_rate_get,
  1831. ext_disp_rx_sample_rate_put),
  1832. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1833. tdm_rx_sample_rate_get,
  1834. tdm_rx_sample_rate_put),
  1835. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1836. tdm_tx_sample_rate_get,
  1837. tdm_tx_sample_rate_put),
  1838. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  1839. tdm_rx_format_get,
  1840. tdm_rx_format_put),
  1841. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  1842. tdm_tx_format_get,
  1843. tdm_tx_format_put),
  1844. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  1845. tdm_rx_ch_get,
  1846. tdm_rx_ch_put),
  1847. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  1848. tdm_tx_ch_get,
  1849. tdm_tx_ch_put),
  1850. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1851. tdm_rx_sample_rate_get,
  1852. tdm_rx_sample_rate_put),
  1853. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1854. tdm_tx_sample_rate_get,
  1855. tdm_tx_sample_rate_put),
  1856. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  1857. tdm_rx_format_get,
  1858. tdm_rx_format_put),
  1859. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  1860. tdm_tx_format_get,
  1861. tdm_tx_format_put),
  1862. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  1863. tdm_rx_ch_get,
  1864. tdm_rx_ch_put),
  1865. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  1866. tdm_tx_ch_get,
  1867. tdm_tx_ch_put),
  1868. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1869. tdm_rx_sample_rate_get,
  1870. tdm_rx_sample_rate_put),
  1871. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1872. tdm_tx_sample_rate_get,
  1873. tdm_tx_sample_rate_put),
  1874. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  1875. tdm_rx_format_get,
  1876. tdm_rx_format_put),
  1877. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  1878. tdm_tx_format_get,
  1879. tdm_tx_format_put),
  1880. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  1881. tdm_rx_ch_get,
  1882. tdm_rx_ch_put),
  1883. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  1884. tdm_tx_ch_get,
  1885. tdm_tx_ch_put),
  1886. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1887. tdm_rx_sample_rate_get,
  1888. tdm_rx_sample_rate_put),
  1889. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1890. tdm_tx_sample_rate_get,
  1891. tdm_tx_sample_rate_put),
  1892. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  1893. tdm_rx_format_get,
  1894. tdm_rx_format_put),
  1895. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  1896. tdm_tx_format_get,
  1897. tdm_tx_format_put),
  1898. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  1899. tdm_rx_ch_get,
  1900. tdm_rx_ch_put),
  1901. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  1902. tdm_tx_ch_get,
  1903. tdm_tx_ch_put),
  1904. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1905. tdm_rx_sample_rate_get,
  1906. tdm_rx_sample_rate_put),
  1907. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1908. tdm_tx_sample_rate_get,
  1909. tdm_tx_sample_rate_put),
  1910. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  1911. tdm_rx_format_get,
  1912. tdm_rx_format_put),
  1913. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  1914. tdm_tx_format_get,
  1915. tdm_tx_format_put),
  1916. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  1917. tdm_rx_ch_get,
  1918. tdm_rx_ch_put),
  1919. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  1920. tdm_tx_ch_get,
  1921. tdm_tx_ch_put),
  1922. SOC_ENUM_EXT("MultiMedia5_RX QOS Vote", qos_vote, msm_qos_ctl_get,
  1923. msm_qos_ctl_put),
  1924. };
  1925. /**
  1926. * msm_common_snd_controls_size - to return controls size
  1927. *
  1928. * Return: returns size of common controls array
  1929. */
  1930. int msm_common_snd_controls_size(void)
  1931. {
  1932. return ARRAY_SIZE(msm_common_snd_controls);
  1933. }
  1934. EXPORT_SYMBOL(msm_common_snd_controls_size);
  1935. void msm_set_codec_reg_done(bool done)
  1936. {
  1937. codec_reg_done = done;
  1938. }
  1939. EXPORT_SYMBOL(msm_set_codec_reg_done);
  1940. static inline int param_is_mask(int p)
  1941. {
  1942. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  1943. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  1944. }
  1945. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  1946. int n)
  1947. {
  1948. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  1949. }
  1950. static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
  1951. {
  1952. if (bit >= SNDRV_MASK_MAX)
  1953. return;
  1954. if (param_is_mask(n)) {
  1955. struct snd_mask *m = param_to_mask(p, n);
  1956. m->bits[0] = 0;
  1957. m->bits[1] = 0;
  1958. m->bits[bit >> 5] |= (1 << (bit & 31));
  1959. }
  1960. }
  1961. static int msm_ext_disp_get_idx_from_beid(int32_t id)
  1962. {
  1963. int idx;
  1964. switch (id) {
  1965. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1966. idx = DP_RX_IDX;
  1967. break;
  1968. default:
  1969. pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
  1970. idx = -EINVAL;
  1971. break;
  1972. }
  1973. return idx;
  1974. }
  1975. /**
  1976. * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
  1977. *
  1978. * @rtd: runtime dailink instance
  1979. * @params: HW params of associated backend dailink.
  1980. *
  1981. * Returns 0.
  1982. */
  1983. int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  1984. struct snd_pcm_hw_params *params)
  1985. {
  1986. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  1987. struct snd_interval *rate = hw_param_interval(params,
  1988. SNDRV_PCM_HW_PARAM_RATE);
  1989. struct snd_interval *channels = hw_param_interval(params,
  1990. SNDRV_PCM_HW_PARAM_CHANNELS);
  1991. int rc = 0;
  1992. int idx;
  1993. pr_debug("%s: format = %d, rate = %d\n",
  1994. __func__, params_format(params), params_rate(params));
  1995. switch (dai_link->id) {
  1996. case MSM_BACKEND_DAI_USB_RX:
  1997. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1998. usb_rx_cfg.bit_format);
  1999. rate->min = rate->max = usb_rx_cfg.sample_rate;
  2000. channels->min = channels->max = usb_rx_cfg.channels;
  2001. break;
  2002. case MSM_BACKEND_DAI_USB_TX:
  2003. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2004. usb_tx_cfg.bit_format);
  2005. rate->min = rate->max = usb_tx_cfg.sample_rate;
  2006. channels->min = channels->max = usb_tx_cfg.channels;
  2007. break;
  2008. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  2009. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  2010. if (idx < 0) {
  2011. pr_err("%s: Incorrect ext disp idx %d\n",
  2012. __func__, idx);
  2013. rc = idx;
  2014. break;
  2015. }
  2016. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2017. ext_disp_rx_cfg[idx].bit_format);
  2018. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  2019. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  2020. break;
  2021. case MSM_BACKEND_DAI_AFE_PCM_RX:
  2022. channels->min = channels->max = proxy_rx_cfg.channels;
  2023. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2024. break;
  2025. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  2026. channels->min = channels->max =
  2027. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  2028. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2029. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  2030. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  2031. break;
  2032. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  2033. channels->min = channels->max =
  2034. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  2035. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2036. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  2037. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  2038. break;
  2039. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  2040. channels->min = channels->max =
  2041. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  2042. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2043. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  2044. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  2045. break;
  2046. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  2047. channels->min = channels->max =
  2048. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  2049. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2050. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  2051. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  2052. break;
  2053. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2054. channels->min = channels->max =
  2055. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2056. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2057. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2058. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2059. break;
  2060. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2061. channels->min = channels->max =
  2062. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2063. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2064. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2065. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2066. break;
  2067. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2068. channels->min = channels->max =
  2069. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2070. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2071. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2072. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2073. break;
  2074. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2075. channels->min = channels->max =
  2076. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2077. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2078. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2079. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2080. break;
  2081. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  2082. channels->min = channels->max =
  2083. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  2084. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2085. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  2086. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2087. break;
  2088. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  2089. channels->min = channels->max =
  2090. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  2091. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2092. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  2093. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2094. break;
  2095. case MSM_BACKEND_DAI_AUXPCM_RX:
  2096. rate->min = rate->max =
  2097. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2098. channels->min = channels->max =
  2099. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2100. break;
  2101. case MSM_BACKEND_DAI_AUXPCM_TX:
  2102. rate->min = rate->max =
  2103. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2104. channels->min = channels->max =
  2105. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2106. break;
  2107. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2108. rate->min = rate->max =
  2109. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2110. channels->min = channels->max =
  2111. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2112. break;
  2113. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2114. rate->min = rate->max =
  2115. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2116. channels->min = channels->max =
  2117. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2118. break;
  2119. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2120. rate->min = rate->max =
  2121. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2122. channels->min = channels->max =
  2123. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2124. break;
  2125. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2126. rate->min = rate->max =
  2127. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2128. channels->min = channels->max =
  2129. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  2130. break;
  2131. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  2132. rate->min = rate->max =
  2133. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  2134. channels->min = channels->max =
  2135. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  2136. break;
  2137. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  2138. rate->min = rate->max =
  2139. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  2140. channels->min = channels->max =
  2141. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  2142. break;
  2143. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  2144. rate->min = rate->max =
  2145. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  2146. channels->min = channels->max =
  2147. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  2148. break;
  2149. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  2150. rate->min = rate->max =
  2151. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  2152. channels->min = channels->max =
  2153. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  2154. break;
  2155. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2156. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  2157. channels->min = channels->max =
  2158. mi2s_rx_cfg[PRIM_MI2S].channels;
  2159. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2160. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  2161. break;
  2162. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2163. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  2164. channels->min = channels->max =
  2165. mi2s_tx_cfg[PRIM_MI2S].channels;
  2166. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2167. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  2168. break;
  2169. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2170. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  2171. channels->min = channels->max =
  2172. mi2s_rx_cfg[SEC_MI2S].channels;
  2173. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2174. mi2s_rx_cfg[SEC_MI2S].bit_format);
  2175. break;
  2176. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2177. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  2178. channels->min = channels->max =
  2179. mi2s_tx_cfg[SEC_MI2S].channels;
  2180. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2181. mi2s_tx_cfg[SEC_MI2S].bit_format);
  2182. break;
  2183. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2184. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  2185. channels->min = channels->max =
  2186. mi2s_rx_cfg[TERT_MI2S].channels;
  2187. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2188. mi2s_rx_cfg[TERT_MI2S].bit_format);
  2189. break;
  2190. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2191. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  2192. channels->min = channels->max =
  2193. mi2s_tx_cfg[TERT_MI2S].channels;
  2194. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2195. mi2s_tx_cfg[TERT_MI2S].bit_format);
  2196. break;
  2197. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2198. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  2199. channels->min = channels->max =
  2200. mi2s_rx_cfg[QUAT_MI2S].channels;
  2201. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2202. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  2203. break;
  2204. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2205. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  2206. channels->min = channels->max =
  2207. mi2s_tx_cfg[QUAT_MI2S].channels;
  2208. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2209. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  2210. break;
  2211. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2212. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  2213. channels->min = channels->max =
  2214. mi2s_rx_cfg[QUIN_MI2S].channels;
  2215. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2216. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  2217. break;
  2218. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2219. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  2220. channels->min = channels->max =
  2221. mi2s_tx_cfg[QUIN_MI2S].channels;
  2222. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2223. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  2224. break;
  2225. default:
  2226. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2227. break;
  2228. }
  2229. return rc;
  2230. }
  2231. EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
  2232. /**
  2233. * msm_aux_pcm_snd_startup - startup ops of auxpcm.
  2234. *
  2235. * @substream: PCM stream pointer of associated backend dailink
  2236. *
  2237. * Returns 0 on success or -EINVAL on error.
  2238. */
  2239. int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
  2240. {
  2241. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2242. dev_dbg(rtd->card->dev,
  2243. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2244. __func__, substream->name, substream->stream,
  2245. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2246. return 0;
  2247. }
  2248. EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
  2249. /**
  2250. * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
  2251. *
  2252. * @substream: PCM stream pointer of associated backend dailink
  2253. */
  2254. void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
  2255. {
  2256. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2257. dev_dbg(rtd->card->dev,
  2258. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2259. __func__,
  2260. substream->name, substream->stream,
  2261. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2262. }
  2263. EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
  2264. static int msm_get_port_id(int id)
  2265. {
  2266. int afe_port_id;
  2267. switch (id) {
  2268. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2269. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2270. break;
  2271. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2272. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2273. break;
  2274. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2275. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2276. break;
  2277. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2278. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2279. break;
  2280. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2281. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2282. break;
  2283. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2284. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2285. break;
  2286. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2287. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2288. break;
  2289. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2290. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2291. break;
  2292. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2293. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2294. break;
  2295. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2296. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2297. break;
  2298. default:
  2299. pr_err("%s: Invalid id: %d\n", __func__, id);
  2300. afe_port_id = -EINVAL;
  2301. }
  2302. return afe_port_id;
  2303. }
  2304. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2305. {
  2306. u32 bit_per_sample;
  2307. switch (bit_format) {
  2308. case SNDRV_PCM_FORMAT_S32_LE:
  2309. case SNDRV_PCM_FORMAT_S24_3LE:
  2310. case SNDRV_PCM_FORMAT_S24_LE:
  2311. bit_per_sample = 32;
  2312. break;
  2313. case SNDRV_PCM_FORMAT_S16_LE:
  2314. default:
  2315. bit_per_sample = 16;
  2316. break;
  2317. }
  2318. return bit_per_sample;
  2319. }
  2320. static void update_mi2s_clk_val(int dai_id, int stream)
  2321. {
  2322. u32 bit_per_sample;
  2323. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2324. bit_per_sample =
  2325. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2326. mi2s_clk[dai_id].clk_freq_in_hz =
  2327. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2328. } else {
  2329. bit_per_sample =
  2330. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2331. mi2s_clk[dai_id].clk_freq_in_hz =
  2332. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2333. }
  2334. }
  2335. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2336. {
  2337. int ret = 0;
  2338. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2339. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2340. int port_id = 0;
  2341. int index = cpu_dai->id;
  2342. port_id = msm_get_port_id(rtd->dai_link->id);
  2343. if (port_id < 0) {
  2344. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2345. ret = port_id;
  2346. goto done;
  2347. }
  2348. if (enable) {
  2349. update_mi2s_clk_val(index, substream->stream);
  2350. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2351. mi2s_clk[index].clk_freq_in_hz);
  2352. }
  2353. mi2s_clk[index].enable = enable;
  2354. ret = afe_set_lpass_clock_v2(port_id,
  2355. &mi2s_clk[index]);
  2356. if (ret < 0) {
  2357. dev_err(rtd->card->dev,
  2358. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2359. __func__, port_id, ret);
  2360. goto done;
  2361. }
  2362. done:
  2363. return ret;
  2364. }
  2365. /**
  2366. * msm_mi2s_snd_startup - startup ops of mi2s.
  2367. *
  2368. * @substream: PCM stream pointer of associated backend dailink
  2369. *
  2370. * Returns 0 on success or -EINVAL on error.
  2371. */
  2372. int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  2373. {
  2374. int ret = 0;
  2375. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2376. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2377. int port_id = msm_get_port_id(rtd->dai_link->id);
  2378. int index = cpu_dai->id;
  2379. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  2380. struct msm_asoc_mach_data *pdata =
  2381. snd_soc_card_get_drvdata(rtd->card);
  2382. dev_dbg(rtd->card->dev,
  2383. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2384. __func__, substream->name, substream->stream,
  2385. cpu_dai->name, cpu_dai->id);
  2386. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2387. ret = -EINVAL;
  2388. dev_err(rtd->card->dev,
  2389. "%s: CPU DAI id (%d) out of range\n",
  2390. __func__, cpu_dai->id);
  2391. goto done;
  2392. }
  2393. /*
  2394. * Muxtex protection in case the same MI2S
  2395. * interface using for both TX and RX so
  2396. * that the same clock won't be enable twice.
  2397. */
  2398. mutex_lock(&mi2s_intf_conf[index].lock);
  2399. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  2400. /* Check if msm needs to provide the clock to the interface */
  2401. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  2402. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  2403. fmt = SND_SOC_DAIFMT_CBM_CFM;
  2404. }
  2405. ret = msm_mi2s_set_sclk(substream, true);
  2406. if (ret < 0) {
  2407. dev_err(rtd->card->dev,
  2408. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  2409. __func__, ret);
  2410. goto clean_up;
  2411. }
  2412. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  2413. if (ret < 0) {
  2414. dev_err(rtd->card->dev,
  2415. "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  2416. __func__, index, ret);
  2417. goto clk_off;
  2418. }
  2419. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2420. mi2s_mclk[index].enable = 1;
  2421. pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
  2422. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2423. ret = afe_set_lpass_clock_v2(port_id,
  2424. &mi2s_mclk[index]);
  2425. if (ret < 0) {
  2426. pr_err("%s: afe lpass mclk failed, err:%d\n",
  2427. __func__, ret);
  2428. goto clk_off;
  2429. }
  2430. }
  2431. if (pdata->mi2s_gpio_p[index])
  2432. msm_cdc_pinctrl_select_active_state(
  2433. pdata->mi2s_gpio_p[index]);
  2434. }
  2435. mutex_unlock(&mi2s_intf_conf[index].lock);
  2436. return 0;
  2437. clk_off:
  2438. if (ret < 0)
  2439. msm_mi2s_set_sclk(substream, false);
  2440. clean_up:
  2441. if (ret < 0)
  2442. mi2s_intf_conf[index].ref_cnt--;
  2443. mutex_unlock(&mi2s_intf_conf[index].lock);
  2444. done:
  2445. return ret;
  2446. }
  2447. EXPORT_SYMBOL(msm_mi2s_snd_startup);
  2448. /**
  2449. * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
  2450. *
  2451. * @substream: PCM stream pointer of associated backend dailink
  2452. */
  2453. void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  2454. {
  2455. int ret;
  2456. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2457. int port_id = msm_get_port_id(rtd->dai_link->id);
  2458. int index = rtd->cpu_dai->id;
  2459. struct msm_asoc_mach_data *pdata =
  2460. snd_soc_card_get_drvdata(rtd->card);
  2461. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  2462. substream->name, substream->stream);
  2463. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2464. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  2465. return;
  2466. }
  2467. mutex_lock(&mi2s_intf_conf[index].lock);
  2468. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  2469. if (pdata->mi2s_gpio_p[index])
  2470. msm_cdc_pinctrl_select_sleep_state(
  2471. pdata->mi2s_gpio_p[index]);
  2472. ret = msm_mi2s_set_sclk(substream, false);
  2473. if (ret < 0)
  2474. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  2475. __func__, index, ret);
  2476. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2477. mi2s_mclk[index].enable = 0;
  2478. pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
  2479. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2480. ret = afe_set_lpass_clock_v2(port_id,
  2481. &mi2s_mclk[index]);
  2482. if (ret < 0) {
  2483. pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
  2484. __func__, index, ret);
  2485. }
  2486. }
  2487. }
  2488. mutex_unlock(&mi2s_intf_conf[index].lock);
  2489. }
  2490. EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
  2491. /* Validate whether US EU switch is present or not */
  2492. static int msm_prepare_us_euro(struct snd_soc_card *card)
  2493. {
  2494. struct msm_asoc_mach_data *pdata =
  2495. snd_soc_card_get_drvdata(card);
  2496. int ret = 0;
  2497. if (pdata->us_euro_gpio >= 0) {
  2498. dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
  2499. pdata->us_euro_gpio);
  2500. ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
  2501. if (ret) {
  2502. dev_err(card->dev,
  2503. "%s: Failed to request codec US/EURO gpio %d error %d\n",
  2504. __func__, pdata->us_euro_gpio, ret);
  2505. }
  2506. }
  2507. return ret;
  2508. }
  2509. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
  2510. {
  2511. struct snd_soc_card *card = codec->component.card;
  2512. struct msm_asoc_mach_data *pdata =
  2513. snd_soc_card_get_drvdata(card);
  2514. int value = 0;
  2515. if (pdata->us_euro_gpio_p) {
  2516. value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p);
  2517. if (value)
  2518. msm_cdc_pinctrl_select_sleep_state(
  2519. pdata->us_euro_gpio_p);
  2520. else
  2521. msm_cdc_pinctrl_select_active_state(
  2522. pdata->us_euro_gpio_p);
  2523. } else if (pdata->us_euro_gpio >= 0) {
  2524. value = gpio_get_value_cansleep(pdata->us_euro_gpio);
  2525. gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
  2526. }
  2527. pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value);
  2528. return true;
  2529. }
  2530. static int msm_populate_dai_link_component_of_node(
  2531. struct msm_asoc_mach_data *pdata,
  2532. struct snd_soc_card *card)
  2533. {
  2534. int i, index, ret = 0;
  2535. struct device *cdev = card->dev;
  2536. struct snd_soc_dai_link *dai_link = card->dai_link;
  2537. struct device_node *phandle;
  2538. if (!cdev) {
  2539. pr_err("%s: Sound card device memory NULL\n", __func__);
  2540. return -ENODEV;
  2541. }
  2542. for (i = 0; i < card->num_links; i++) {
  2543. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  2544. continue;
  2545. /* populate platform_of_node for snd card dai links */
  2546. if (dai_link[i].platform_name &&
  2547. !dai_link[i].platform_of_node) {
  2548. index = of_property_match_string(cdev->of_node,
  2549. "asoc-platform-names",
  2550. dai_link[i].platform_name);
  2551. if (index < 0) {
  2552. pr_err("%s: No match found for platform name: %s\n",
  2553. __func__, dai_link[i].platform_name);
  2554. ret = index;
  2555. goto cpu_dai;
  2556. }
  2557. phandle = of_parse_phandle(cdev->of_node,
  2558. "asoc-platform",
  2559. index);
  2560. if (!phandle) {
  2561. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  2562. __func__, dai_link[i].platform_name,
  2563. index);
  2564. ret = -ENODEV;
  2565. goto err;
  2566. }
  2567. dai_link[i].platform_of_node = phandle;
  2568. dai_link[i].platform_name = NULL;
  2569. }
  2570. cpu_dai:
  2571. /* populate cpu_of_node for snd card dai links */
  2572. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  2573. index = of_property_match_string(cdev->of_node,
  2574. "asoc-cpu-names",
  2575. dai_link[i].cpu_dai_name);
  2576. if (index < 0)
  2577. goto codec_dai;
  2578. phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
  2579. index);
  2580. if (!phandle) {
  2581. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  2582. __func__, dai_link[i].cpu_dai_name);
  2583. ret = -ENODEV;
  2584. goto err;
  2585. }
  2586. dai_link[i].cpu_of_node = phandle;
  2587. dai_link[i].cpu_dai_name = NULL;
  2588. }
  2589. codec_dai:
  2590. /* populate codec_of_node for snd card dai links */
  2591. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  2592. index = of_property_match_string(cdev->of_node,
  2593. "asoc-codec-names",
  2594. dai_link[i].codec_name);
  2595. if (index < 0)
  2596. continue;
  2597. phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
  2598. index);
  2599. if (!phandle) {
  2600. pr_err("%s: retrieving phandle for codec dai %s failed\n",
  2601. __func__, dai_link[i].codec_name);
  2602. ret = -ENODEV;
  2603. goto err;
  2604. }
  2605. dai_link[i].codec_of_node = phandle;
  2606. dai_link[i].codec_name = NULL;
  2607. }
  2608. if (pdata->snd_card_val == INT_SND_CARD) {
  2609. if ((dai_link[i].id ==
  2610. MSM_BACKEND_DAI_INT0_MI2S_RX) ||
  2611. (dai_link[i].id ==
  2612. MSM_BACKEND_DAI_INT1_MI2S_RX) ||
  2613. (dai_link[i].id ==
  2614. MSM_BACKEND_DAI_INT2_MI2S_TX) ||
  2615. (dai_link[i].id ==
  2616. MSM_BACKEND_DAI_INT3_MI2S_TX)) {
  2617. index = of_property_match_string(cdev->of_node,
  2618. "asoc-codec-names",
  2619. MSM_INT_DIGITAL_CODEC);
  2620. phandle = of_parse_phandle(cdev->of_node,
  2621. "asoc-codec",
  2622. index);
  2623. dai_link[i].codecs[DIG_CDC].of_node = phandle;
  2624. index = of_property_match_string(cdev->of_node,
  2625. "asoc-codec-names",
  2626. PMIC_INT_ANALOG_CODEC);
  2627. phandle = of_parse_phandle(cdev->of_node,
  2628. "asoc-codec",
  2629. index);
  2630. dai_link[i].codecs[ANA_CDC].of_node = phandle;
  2631. }
  2632. }
  2633. }
  2634. err:
  2635. return ret;
  2636. }
  2637. static int msm_wsa881x_init(struct snd_soc_component *component)
  2638. {
  2639. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  2640. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  2641. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  2642. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  2643. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  2644. struct msm_asoc_mach_data *pdata;
  2645. struct snd_soc_dapm_context *dapm =
  2646. snd_soc_codec_get_dapm(codec);
  2647. if (!codec) {
  2648. pr_err("%s codec is NULL\n", __func__);
  2649. return -EINVAL;
  2650. }
  2651. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  2652. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  2653. __func__, codec->component.name);
  2654. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  2655. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2656. &ch_rate[0]);
  2657. if (dapm->component) {
  2658. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  2659. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  2660. }
  2661. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  2662. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  2663. __func__, codec->component.name);
  2664. wsa881x_set_channel_map(codec, &spkright_ports[0],
  2665. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2666. &ch_rate[0]);
  2667. if (dapm->component) {
  2668. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  2669. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  2670. }
  2671. } else {
  2672. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  2673. codec->component.name);
  2674. return -EINVAL;
  2675. }
  2676. pdata = snd_soc_card_get_drvdata(component->card);
  2677. if (pdata && pdata->codec_root)
  2678. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  2679. codec);
  2680. return 0;
  2681. }
  2682. static int msm_init_wsa_dev(struct platform_device *pdev,
  2683. struct snd_soc_card *card)
  2684. {
  2685. struct device_node *wsa_of_node;
  2686. u32 wsa_max_devs;
  2687. u32 wsa_dev_cnt;
  2688. char *dev_name_str = NULL;
  2689. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  2690. const char *wsa_auxdev_name_prefix[1];
  2691. int found = 0;
  2692. int i;
  2693. int ret;
  2694. /* Get maximum WSA device count for this platform */
  2695. ret = of_property_read_u32(pdev->dev.of_node,
  2696. "qcom,wsa-max-devs", &wsa_max_devs);
  2697. if (ret) {
  2698. dev_dbg(&pdev->dev,
  2699. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  2700. __func__, pdev->dev.of_node->full_name, ret);
  2701. goto err_dt;
  2702. }
  2703. if (wsa_max_devs == 0) {
  2704. dev_warn(&pdev->dev,
  2705. "%s: Max WSA devices is 0 for this target?\n",
  2706. __func__);
  2707. goto err_dt;
  2708. }
  2709. /* Get count of WSA device phandles for this platform */
  2710. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  2711. "qcom,wsa-devs", NULL);
  2712. if (wsa_dev_cnt == -ENOENT) {
  2713. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  2714. __func__);
  2715. goto err_dt;
  2716. } else if (wsa_dev_cnt <= 0) {
  2717. dev_err(&pdev->dev,
  2718. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  2719. __func__, wsa_dev_cnt);
  2720. ret = -EINVAL;
  2721. goto err_dt;
  2722. }
  2723. /*
  2724. * Expect total phandles count to be NOT less than maximum possible
  2725. * WSA count. However, if it is less, then assign same value to
  2726. * max count as well.
  2727. */
  2728. if (wsa_dev_cnt < wsa_max_devs) {
  2729. dev_dbg(&pdev->dev,
  2730. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  2731. __func__, wsa_max_devs, wsa_dev_cnt);
  2732. wsa_max_devs = wsa_dev_cnt;
  2733. }
  2734. /* Make sure prefix string passed for each WSA device */
  2735. ret = of_property_count_strings(pdev->dev.of_node,
  2736. "qcom,wsa-aux-dev-prefix");
  2737. if (ret != wsa_dev_cnt) {
  2738. dev_err(&pdev->dev,
  2739. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  2740. __func__, wsa_dev_cnt, ret);
  2741. ret = -EINVAL;
  2742. goto err_dt;
  2743. }
  2744. /*
  2745. * Alloc mem to store phandle and index info of WSA device, if already
  2746. * registered with ALSA core
  2747. */
  2748. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  2749. sizeof(struct msm_wsa881x_dev_info),
  2750. GFP_KERNEL);
  2751. if (!wsa881x_dev_info) {
  2752. ret = -ENOMEM;
  2753. goto err_mem;
  2754. }
  2755. /*
  2756. * search and check whether all WSA devices are already
  2757. * registered with ALSA core or not. If found a node, store
  2758. * the node and the index in a local array of struct for later
  2759. * use.
  2760. */
  2761. for (i = 0; i < wsa_dev_cnt; i++) {
  2762. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  2763. "qcom,wsa-devs", i);
  2764. if (unlikely(!wsa_of_node)) {
  2765. /* we should not be here */
  2766. dev_err(&pdev->dev,
  2767. "%s: wsa dev node is not present\n",
  2768. __func__);
  2769. ret = -EINVAL;
  2770. goto err_dev_node;
  2771. }
  2772. if (soc_find_component(wsa_of_node, NULL)) {
  2773. /* WSA device registered with ALSA core */
  2774. wsa881x_dev_info[found].of_node = wsa_of_node;
  2775. wsa881x_dev_info[found].index = i;
  2776. found++;
  2777. if (found == wsa_max_devs)
  2778. break;
  2779. }
  2780. }
  2781. if (found < wsa_max_devs) {
  2782. dev_dbg(&pdev->dev,
  2783. "%s: failed to find %d components. Found only %d\n",
  2784. __func__, wsa_max_devs, found);
  2785. return -EPROBE_DEFER;
  2786. }
  2787. dev_info(&pdev->dev,
  2788. "%s: found %d wsa881x devices registered with ALSA core\n",
  2789. __func__, found);
  2790. card->num_aux_devs = wsa_max_devs;
  2791. card->num_configs = wsa_max_devs;
  2792. /* Alloc array of AUX devs struct */
  2793. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2794. sizeof(struct snd_soc_aux_dev),
  2795. GFP_KERNEL);
  2796. if (!msm_aux_dev) {
  2797. ret = -ENOMEM;
  2798. goto err_auxdev_mem;
  2799. }
  2800. /* Alloc array of codec conf struct */
  2801. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2802. sizeof(struct snd_soc_codec_conf),
  2803. GFP_KERNEL);
  2804. if (!msm_codec_conf) {
  2805. ret = -ENOMEM;
  2806. goto err_codec_conf;
  2807. }
  2808. for (i = 0; i < card->num_aux_devs; i++) {
  2809. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  2810. GFP_KERNEL);
  2811. if (!dev_name_str) {
  2812. ret = -ENOMEM;
  2813. goto err_dev_str;
  2814. }
  2815. ret = of_property_read_string_index(pdev->dev.of_node,
  2816. "qcom,wsa-aux-dev-prefix",
  2817. wsa881x_dev_info[i].index,
  2818. wsa_auxdev_name_prefix);
  2819. if (ret) {
  2820. dev_err(&pdev->dev,
  2821. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  2822. __func__, ret);
  2823. ret = -EINVAL;
  2824. goto err_dt_prop;
  2825. }
  2826. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  2827. msm_aux_dev[i].name = dev_name_str;
  2828. msm_aux_dev[i].codec_name = NULL;
  2829. msm_aux_dev[i].codec_of_node =
  2830. wsa881x_dev_info[i].of_node;
  2831. msm_aux_dev[i].init = msm_wsa881x_init;
  2832. msm_codec_conf[i].dev_name = NULL;
  2833. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  2834. msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
  2835. }
  2836. card->codec_conf = msm_codec_conf;
  2837. card->aux_dev = msm_aux_dev;
  2838. return 0;
  2839. err_dt_prop:
  2840. devm_kfree(&pdev->dev, dev_name_str);
  2841. err_dev_str:
  2842. devm_kfree(&pdev->dev, msm_codec_conf);
  2843. err_codec_conf:
  2844. devm_kfree(&pdev->dev, msm_aux_dev);
  2845. err_auxdev_mem:
  2846. err_dev_node:
  2847. devm_kfree(&pdev->dev, wsa881x_dev_info);
  2848. err_mem:
  2849. err_dt:
  2850. return ret;
  2851. }
  2852. static void i2s_auxpcm_init(struct platform_device *pdev)
  2853. {
  2854. int count;
  2855. u32 mi2s_master_slave[MI2S_MAX];
  2856. u32 mi2s_ext_mclk[MI2S_MAX];
  2857. int ret;
  2858. for (count = 0; count < MI2S_MAX; count++) {
  2859. mutex_init(&mi2s_intf_conf[count].lock);
  2860. mi2s_intf_conf[count].ref_cnt = 0;
  2861. }
  2862. ret = of_property_read_u32_array(pdev->dev.of_node,
  2863. "qcom,msm-mi2s-master",
  2864. mi2s_master_slave, MI2S_MAX);
  2865. if (ret) {
  2866. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  2867. __func__);
  2868. } else {
  2869. for (count = 0; count < MI2S_MAX; count++) {
  2870. mi2s_intf_conf[count].msm_is_mi2s_master =
  2871. mi2s_master_slave[count];
  2872. }
  2873. }
  2874. ret = of_property_read_u32_array(pdev->dev.of_node,
  2875. "qcom,msm-mi2s-ext-mclk",
  2876. mi2s_ext_mclk, MI2S_MAX);
  2877. if (ret) {
  2878. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
  2879. __func__);
  2880. } else {
  2881. for (count = 0; count < MI2S_MAX; count++)
  2882. mi2s_intf_conf[count].msm_is_ext_mclk =
  2883. mi2s_ext_mclk[count];
  2884. }
  2885. }
  2886. static const struct of_device_id sdm660_asoc_machine_of_match[] = {
  2887. { .compatible = "qcom,sdm660-asoc-snd",
  2888. .data = "internal_codec"},
  2889. { .compatible = "qcom,sdm660-asoc-snd-tasha",
  2890. .data = "tasha_codec"},
  2891. { .compatible = "qcom,sdm660-asoc-snd-tavil",
  2892. .data = "tavil_codec"},
  2893. { .compatible = "qcom,sdm670-asoc-snd",
  2894. .data = "internal_codec"},
  2895. { .compatible = "qcom,sdm670-asoc-snd-tasha",
  2896. .data = "tasha_codec"},
  2897. { .compatible = "qcom,sdm670-asoc-snd-tavil",
  2898. .data = "tavil_codec"},
  2899. {},
  2900. };
  2901. static int msm_asoc_machine_probe(struct platform_device *pdev)
  2902. {
  2903. struct snd_soc_card *card = NULL;
  2904. struct msm_asoc_mach_data *pdata = NULL;
  2905. const char *mclk = "qcom,msm-mclk-freq";
  2906. int ret = -EINVAL, id;
  2907. const struct of_device_id *match;
  2908. pdata = devm_kzalloc(&pdev->dev,
  2909. sizeof(struct msm_asoc_mach_data),
  2910. GFP_KERNEL);
  2911. if (!pdata)
  2912. return -ENOMEM;
  2913. msm_set_codec_reg_done(false);
  2914. match = of_match_node(sdm660_asoc_machine_of_match,
  2915. pdev->dev.of_node);
  2916. if (!match)
  2917. goto err;
  2918. ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
  2919. if (ret) {
  2920. dev_err(&pdev->dev,
  2921. "%s: missing %s in dt node\n", __func__, mclk);
  2922. id = DEFAULT_MCLK_RATE;
  2923. }
  2924. pdata->mclk_freq = id;
  2925. if (!strcmp(match->data, "tasha_codec") ||
  2926. !strcmp(match->data, "tavil_codec")) {
  2927. if (!strcmp(match->data, "tasha_codec"))
  2928. pdata->snd_card_val = EXT_SND_CARD_TASHA;
  2929. else
  2930. pdata->snd_card_val = EXT_SND_CARD_TAVIL;
  2931. ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2932. if (ret)
  2933. goto err;
  2934. } else if (!strcmp(match->data, "internal_codec")) {
  2935. pdata->snd_card_val = INT_SND_CARD;
  2936. ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2937. if (ret)
  2938. goto err;
  2939. } else {
  2940. dev_err(&pdev->dev,
  2941. "%s: Not a matching DT sound node\n", __func__);
  2942. goto err;
  2943. }
  2944. if (!card)
  2945. goto err;
  2946. if (pdata->snd_card_val == INT_SND_CARD) {
  2947. /*reading the gpio configurations from dtsi file*/
  2948. pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2949. "qcom,cdc-pdm-gpios", 0);
  2950. pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2951. "qcom,cdc-comp-gpios", 0);
  2952. pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2953. "qcom,cdc-dmic-gpios", 0);
  2954. pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2955. "qcom,cdc-ext-spk-gpios", 0);
  2956. }
  2957. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2958. "qcom,pri-mi2s-gpios", 0);
  2959. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2960. "qcom,sec-mi2s-gpios", 0);
  2961. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2962. "qcom,tert-mi2s-gpios", 0);
  2963. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2964. "qcom,quat-mi2s-gpios", 0);
  2965. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2966. "qcom,quin-mi2s-gpios", 0);
  2967. /*
  2968. * Parse US-Euro gpio info from DT. Report no error if us-euro
  2969. * entry is not found in DT file as some targets do not support
  2970. * US-Euro detection
  2971. */
  2972. pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
  2973. "qcom,us-euro-gpios", 0);
  2974. if (!gpio_is_valid(pdata->us_euro_gpio))
  2975. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2976. "qcom,us-euro-gpios", 0);
  2977. if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
  2978. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  2979. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  2980. } else {
  2981. dev_dbg(&pdev->dev, "%s detected",
  2982. "qcom,us-euro-gpios");
  2983. mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  2984. }
  2985. ret = msm_prepare_us_euro(card);
  2986. if (ret)
  2987. dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
  2988. ret);
  2989. i2s_auxpcm_init(pdev);
  2990. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  2991. if (ret)
  2992. goto err;
  2993. ret = msm_populate_dai_link_component_of_node(pdata, card);
  2994. if (ret) {
  2995. ret = -EPROBE_DEFER;
  2996. goto err;
  2997. }
  2998. if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
  2999. ret = msm_init_wsa_dev(pdev, card);
  3000. if (ret)
  3001. goto err;
  3002. }
  3003. ret = devm_snd_soc_register_card(&pdev->dev, card);
  3004. if (ret == -EPROBE_DEFER) {
  3005. if (codec_reg_done) {
  3006. /*
  3007. * return failure as EINVAL since other codec
  3008. * registered sound card successfully.
  3009. * This avoids any further probe calls.
  3010. */
  3011. ret = -EINVAL;
  3012. }
  3013. goto err;
  3014. } else if (ret) {
  3015. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  3016. ret);
  3017. goto err;
  3018. }
  3019. if (pdata->snd_card_val != INT_SND_CARD)
  3020. msm_ext_register_audio_notifier(pdev);
  3021. return 0;
  3022. err:
  3023. if (pdata->us_euro_gpio > 0) {
  3024. dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
  3025. __func__, pdata->us_euro_gpio);
  3026. pdata->us_euro_gpio = 0;
  3027. }
  3028. if (pdata->hph_en1_gpio > 0) {
  3029. dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
  3030. __func__, pdata->hph_en1_gpio);
  3031. gpio_free(pdata->hph_en1_gpio);
  3032. pdata->hph_en1_gpio = 0;
  3033. }
  3034. if (pdata->hph_en0_gpio > 0) {
  3035. dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
  3036. __func__, pdata->hph_en0_gpio);
  3037. gpio_free(pdata->hph_en0_gpio);
  3038. pdata->hph_en0_gpio = 0;
  3039. }
  3040. devm_kfree(&pdev->dev, pdata);
  3041. return ret;
  3042. }
  3043. static int msm_asoc_machine_remove(struct platform_device *pdev)
  3044. {
  3045. struct snd_soc_card *card = platform_get_drvdata(pdev);
  3046. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3047. if (pdata->snd_card_val == INT_SND_CARD)
  3048. mutex_destroy(&pdata->cdc_int_mclk0_mutex);
  3049. if (gpio_is_valid(pdata->us_euro_gpio)) {
  3050. gpio_free(pdata->us_euro_gpio);
  3051. pdata->us_euro_gpio = 0;
  3052. }
  3053. if (gpio_is_valid(pdata->hph_en1_gpio)) {
  3054. gpio_free(pdata->hph_en1_gpio);
  3055. pdata->hph_en1_gpio = 0;
  3056. }
  3057. if (gpio_is_valid(pdata->hph_en0_gpio)) {
  3058. gpio_free(pdata->hph_en0_gpio);
  3059. pdata->hph_en0_gpio = 0;
  3060. }
  3061. if (pdata->snd_card_val != INT_SND_CARD)
  3062. audio_notifier_deregister("sdm660");
  3063. snd_soc_unregister_card(card);
  3064. return 0;
  3065. }
  3066. static struct platform_driver sdm660_asoc_machine_driver = {
  3067. .driver = {
  3068. .name = DRV_NAME,
  3069. .owner = THIS_MODULE,
  3070. .pm = &snd_soc_pm_ops,
  3071. .of_match_table = sdm660_asoc_machine_of_match,
  3072. },
  3073. .probe = msm_asoc_machine_probe,
  3074. .remove = msm_asoc_machine_remove,
  3075. };
  3076. module_platform_driver(sdm660_asoc_machine_driver);
  3077. MODULE_DESCRIPTION("ALSA SoC msm");
  3078. MODULE_LICENSE("GPL v2");
  3079. MODULE_ALIAS("platform:" DRV_NAME);
  3080. MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);