wcd938x.c 127 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  43. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  44. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  45. SNDRV_PCM_RATE_384000)
  46. /* Fractional Rates */
  47. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  48. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  49. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  50. SNDRV_PCM_FMTBIT_S24_LE |\
  51. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  52. enum {
  53. CODEC_TX = 0,
  54. CODEC_RX,
  55. };
  56. enum {
  57. WCD_ADC1 = 0,
  58. WCD_ADC2,
  59. WCD_ADC3,
  60. WCD_ADC4,
  61. ALLOW_BUCK_DISABLE,
  62. HPH_COMP_DELAY,
  63. HPH_PA_DELAY,
  64. AMIC2_BCS_ENABLE,
  65. WCD_SUPPLIES_LPM_MODE,
  66. WCD_ADC1_MODE,
  67. WCD_ADC2_MODE,
  68. WCD_ADC3_MODE,
  69. WCD_ADC4_MODE,
  70. };
  71. enum {
  72. ADC_MODE_INVALID = 0,
  73. ADC_MODE_HIFI,
  74. ADC_MODE_LO_HIF,
  75. ADC_MODE_NORMAL,
  76. ADC_MODE_LP,
  77. ADC_MODE_ULP1,
  78. ADC_MODE_ULP2,
  79. };
  80. static u8 tx_mode_bit[] = {
  81. [ADC_MODE_INVALID] = 0x00,
  82. [ADC_MODE_HIFI] = 0x01,
  83. [ADC_MODE_LO_HIF] = 0x02,
  84. [ADC_MODE_NORMAL] = 0x04,
  85. [ADC_MODE_LP] = 0x08,
  86. [ADC_MODE_ULP1] = 0x10,
  87. [ADC_MODE_ULP2] = 0x20,
  88. };
  89. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  90. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  91. static int wcd938x_handle_post_irq(void *data);
  92. static int wcd938x_reset(struct device *dev);
  93. static int wcd938x_reset_low(struct device *dev);
  94. static int wcd938x_get_adc_mode(int val);
  95. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  96. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  116. };
  117. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  118. .name = "wcd938x",
  119. .irqs = wcd938x_irqs,
  120. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  121. .num_regs = 3,
  122. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  123. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  124. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  125. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  126. .use_ack = 1,
  127. .runtime_pm = false,
  128. .handle_post_irq = wcd938x_handle_post_irq,
  129. .irq_drv_data = NULL,
  130. };
  131. static int wcd938x_handle_post_irq(void *data)
  132. {
  133. struct wcd938x_priv *wcd938x = data;
  134. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  135. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  136. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  137. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  138. wcd938x->tx_swr_dev->slave_irq_pending =
  139. ((sts1 || sts2 || sts3) ? true : false);
  140. return IRQ_HANDLED;
  141. }
  142. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  143. {
  144. int ret = 0;
  145. int bank = 0;
  146. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  147. if (ret)
  148. return -EINVAL;
  149. return ((bank & 0x40) ? 1: 0);
  150. }
  151. static int wcd938x_get_clk_rate(int mode)
  152. {
  153. int rate;
  154. switch (mode) {
  155. case ADC_MODE_ULP2:
  156. rate = SWR_CLK_RATE_0P6MHZ;
  157. break;
  158. case ADC_MODE_ULP1:
  159. rate = SWR_CLK_RATE_1P2MHZ;
  160. break;
  161. case ADC_MODE_LP:
  162. rate = SWR_CLK_RATE_4P8MHZ;
  163. break;
  164. case ADC_MODE_NORMAL:
  165. case ADC_MODE_LO_HIF:
  166. case ADC_MODE_HIFI:
  167. case ADC_MODE_INVALID:
  168. default:
  169. rate = SWR_CLK_RATE_9P6MHZ;
  170. break;
  171. }
  172. return rate;
  173. }
  174. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  175. int rate, int bank)
  176. {
  177. u8 mask = (bank ? 0xF0 : 0x0F);
  178. u8 val = 0;
  179. switch (rate) {
  180. case SWR_CLK_RATE_0P6MHZ:
  181. val = (bank ? 0x60 : 0x06);
  182. break;
  183. case SWR_CLK_RATE_1P2MHZ:
  184. val = (bank ? 0x50 : 0x05);
  185. break;
  186. case SWR_CLK_RATE_2P4MHZ:
  187. val = (bank ? 0x30 : 0x03);
  188. break;
  189. case SWR_CLK_RATE_4P8MHZ:
  190. val = (bank ? 0x10 : 0x01);
  191. break;
  192. case SWR_CLK_RATE_9P6MHZ:
  193. default:
  194. val = 0x00;
  195. break;
  196. }
  197. snd_soc_component_update_bits(component,
  198. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  199. mask, val);
  200. return 0;
  201. }
  202. static int wcd938x_init_reg(struct snd_soc_component *component)
  203. {
  204. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  205. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  206. /* 1 msec delay as per HW requirement */
  207. usleep_range(1000, 1010);
  208. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  209. /* 1 msec delay as per HW requirement */
  210. usleep_range(1000, 1010);
  211. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  212. 0x10, 0x00);
  213. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  214. 0xF0, 0x80);
  215. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  216. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  217. /* 10 msec delay as per HW requirement */
  218. usleep_range(10000, 10010);
  219. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  220. snd_soc_component_update_bits(component,
  221. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  222. 0xF0, 0x00);
  223. snd_soc_component_update_bits(component,
  224. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  225. 0x1F, 0x15);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  228. 0x1F, 0x15);
  229. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  230. 0xC0, 0x80);
  231. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  232. 0x02, 0x02);
  233. snd_soc_component_update_bits(component,
  234. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  235. 0xFF, 0x14);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  238. 0x1F, 0x08);
  239. snd_soc_component_update_bits(component,
  240. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  257. snd_soc_component_update_bits(component,
  258. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  259. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  260. ((snd_soc_component_read32(component,
  261. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  262. snd_soc_component_update_bits(component,
  263. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  264. return 0;
  265. }
  266. static int wcd938x_set_port_params(struct snd_soc_component *component,
  267. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  268. u8 *ch_mask, u32 *ch_rate,
  269. u8 *port_type, u8 path)
  270. {
  271. int i, j;
  272. u8 num_ports = 0;
  273. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  274. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  275. switch (path) {
  276. case CODEC_RX:
  277. map = &wcd938x->rx_port_mapping;
  278. num_ports = wcd938x->num_rx_ports;
  279. break;
  280. case CODEC_TX:
  281. map = &wcd938x->tx_port_mapping;
  282. num_ports = wcd938x->num_tx_ports;
  283. break;
  284. default:
  285. dev_err(component->dev, "%s Invalid path selected %u\n",
  286. __func__, path);
  287. return -EINVAL;
  288. }
  289. for (i = 0; i <= num_ports; i++) {
  290. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  291. if ((*map)[i][j].slave_port_type == slv_prt_type)
  292. goto found;
  293. }
  294. }
  295. found:
  296. if (i > num_ports || j == MAX_CH_PER_PORT) {
  297. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  298. __func__, slv_prt_type);
  299. return -EINVAL;
  300. }
  301. *port_id = i;
  302. *num_ch = (*map)[i][j].num_ch;
  303. *ch_mask = (*map)[i][j].ch_mask;
  304. *ch_rate = (*map)[i][j].ch_rate;
  305. *port_type = (*map)[i][j].master_port_type;
  306. return 0;
  307. }
  308. static int wcd938x_parse_port_mapping(struct device *dev,
  309. char *prop, u8 path)
  310. {
  311. u32 *dt_array, map_size, map_length;
  312. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  313. u32 slave_port_type, master_port_type;
  314. u32 i, ch_iter = 0;
  315. int ret = 0;
  316. u8 *num_ports = NULL;
  317. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  318. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  319. switch (path) {
  320. case CODEC_RX:
  321. map = &wcd938x->rx_port_mapping;
  322. num_ports = &wcd938x->num_rx_ports;
  323. break;
  324. case CODEC_TX:
  325. map = &wcd938x->tx_port_mapping;
  326. num_ports = &wcd938x->num_tx_ports;
  327. break;
  328. default:
  329. dev_err(dev, "%s Invalid path selected %u\n",
  330. __func__, path);
  331. return -EINVAL;
  332. }
  333. if (!of_find_property(dev->of_node, prop,
  334. &map_size)) {
  335. dev_err(dev, "missing port mapping prop %s\n", prop);
  336. ret = -EINVAL;
  337. goto err_port_map;
  338. }
  339. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  340. dt_array = kzalloc(map_size, GFP_KERNEL);
  341. if (!dt_array) {
  342. ret = -ENOMEM;
  343. goto err_alloc;
  344. }
  345. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  346. NUM_SWRS_DT_PARAMS * map_length);
  347. if (ret) {
  348. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  349. __func__, prop);
  350. goto err_pdata_fail;
  351. }
  352. for (i = 0; i < map_length; i++) {
  353. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  354. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  355. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  356. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  357. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  358. if (port_num != old_port_num)
  359. ch_iter = 0;
  360. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  361. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  362. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  363. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  364. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  365. old_port_num = port_num;
  366. }
  367. *num_ports = port_num;
  368. kfree(dt_array);
  369. return 0;
  370. err_pdata_fail:
  371. kfree(dt_array);
  372. err_alloc:
  373. err_port_map:
  374. return ret;
  375. }
  376. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  377. u8 slv_port_type, int clk_rate,
  378. u8 enable)
  379. {
  380. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  381. u8 port_id, num_ch, ch_mask;
  382. u8 ch_type = 0;
  383. u32 ch_rate;
  384. int slave_ch_idx;
  385. u8 num_port = 1;
  386. int ret = 0;
  387. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  388. &num_ch, &ch_mask, &ch_rate,
  389. &ch_type, CODEC_TX);
  390. if (ret)
  391. return ret;
  392. if (clk_rate)
  393. ch_rate = clk_rate;
  394. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  395. if (slave_ch_idx != -EINVAL)
  396. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  397. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  398. __func__, slave_ch_idx, ch_type);
  399. if (enable)
  400. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  401. num_port, &ch_mask, &ch_rate,
  402. &num_ch, &ch_type);
  403. else
  404. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  405. num_port, &ch_mask, &ch_type);
  406. return ret;
  407. }
  408. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  409. u8 slv_port_type, u8 enable)
  410. {
  411. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  412. u8 port_id, num_ch, ch_mask, port_type;
  413. u32 ch_rate;
  414. u8 num_port = 1;
  415. int ret = 0;
  416. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  417. &num_ch, &ch_mask, &ch_rate,
  418. &port_type, CODEC_RX);
  419. if (ret)
  420. return ret;
  421. if (enable)
  422. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  423. num_port, &ch_mask, &ch_rate,
  424. &num_ch, &port_type);
  425. else
  426. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  427. num_port, &ch_mask, &port_type);
  428. return ret;
  429. }
  430. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  431. {
  432. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  433. if (wcd938x->rx_clk_cnt == 0) {
  434. snd_soc_component_update_bits(component,
  435. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  436. snd_soc_component_update_bits(component,
  437. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  440. snd_soc_component_update_bits(component,
  441. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  442. snd_soc_component_update_bits(component,
  443. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  444. snd_soc_component_update_bits(component,
  445. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  446. snd_soc_component_update_bits(component,
  447. WCD938X_AUX_AUXPA, 0x10, 0x10);
  448. }
  449. wcd938x->rx_clk_cnt++;
  450. return 0;
  451. }
  452. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  453. {
  454. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  455. wcd938x->rx_clk_cnt--;
  456. if (wcd938x->rx_clk_cnt == 0) {
  457. snd_soc_component_update_bits(component,
  458. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  459. snd_soc_component_update_bits(component,
  460. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  461. snd_soc_component_update_bits(component,
  462. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  463. snd_soc_component_update_bits(component,
  464. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  465. snd_soc_component_update_bits(component,
  466. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  467. }
  468. return 0;
  469. }
  470. /*
  471. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  472. * @component: handle to snd_soc_component *
  473. *
  474. * return wcd938x_mbhc handle or error code in case of failure
  475. */
  476. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  477. {
  478. struct wcd938x_priv *wcd938x;
  479. if (!component) {
  480. pr_err("%s: Invalid params, NULL component\n", __func__);
  481. return NULL;
  482. }
  483. wcd938x = snd_soc_component_get_drvdata(component);
  484. if (!wcd938x) {
  485. pr_err("%s: wcd938x is NULL\n", __func__);
  486. return NULL;
  487. }
  488. return wcd938x->mbhc;
  489. }
  490. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  491. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  492. struct snd_kcontrol *kcontrol,
  493. int event)
  494. {
  495. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  496. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  497. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  498. w->name, event);
  499. switch (event) {
  500. case SND_SOC_DAPM_PRE_PMU:
  501. wcd938x_rx_clk_enable(component);
  502. snd_soc_component_update_bits(component,
  503. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  506. snd_soc_component_update_bits(component,
  507. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  508. break;
  509. case SND_SOC_DAPM_POST_PMU:
  510. snd_soc_component_update_bits(component,
  511. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  512. if (wcd938x->comp1_enable) {
  513. snd_soc_component_update_bits(component,
  514. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  515. /* 5msec compander delay as per HW requirement */
  516. if (!wcd938x->comp2_enable ||
  517. (snd_soc_component_read32(component,
  518. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  519. usleep_range(5000, 5010);
  520. snd_soc_component_update_bits(component,
  521. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  522. } else {
  523. snd_soc_component_update_bits(component,
  524. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  525. 0x02, 0x00);
  526. snd_soc_component_update_bits(component,
  527. WCD938X_HPH_L_EN, 0x20, 0x20);
  528. }
  529. break;
  530. case SND_SOC_DAPM_POST_PMD:
  531. snd_soc_component_update_bits(component,
  532. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  533. 0x0F, 0x01);
  534. break;
  535. }
  536. return 0;
  537. }
  538. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  539. struct snd_kcontrol *kcontrol,
  540. int event)
  541. {
  542. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  543. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  544. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  545. w->name, event);
  546. switch (event) {
  547. case SND_SOC_DAPM_PRE_PMU:
  548. wcd938x_rx_clk_enable(component);
  549. snd_soc_component_update_bits(component,
  550. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  551. snd_soc_component_update_bits(component,
  552. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  553. snd_soc_component_update_bits(component,
  554. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  555. break;
  556. case SND_SOC_DAPM_POST_PMU:
  557. snd_soc_component_update_bits(component,
  558. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  559. if (wcd938x->comp2_enable) {
  560. snd_soc_component_update_bits(component,
  561. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  562. /* 5msec compander delay as per HW requirement */
  563. if (!wcd938x->comp1_enable ||
  564. (snd_soc_component_read32(component,
  565. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  566. usleep_range(5000, 5010);
  567. snd_soc_component_update_bits(component,
  568. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  569. } else {
  570. snd_soc_component_update_bits(component,
  571. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  572. 0x01, 0x00);
  573. snd_soc_component_update_bits(component,
  574. WCD938X_HPH_R_EN, 0x20, 0x20);
  575. }
  576. break;
  577. case SND_SOC_DAPM_POST_PMD:
  578. snd_soc_component_update_bits(component,
  579. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  580. 0x0F, 0x01);
  581. break;
  582. }
  583. return 0;
  584. }
  585. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  586. struct snd_kcontrol *kcontrol,
  587. int event)
  588. {
  589. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  590. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  591. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  592. w->name, event);
  593. switch (event) {
  594. case SND_SOC_DAPM_PRE_PMU:
  595. wcd938x_rx_clk_enable(component);
  596. wcd938x->ear_rx_path =
  597. snd_soc_component_read32(
  598. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  599. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  600. snd_soc_component_update_bits(component,
  601. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  602. snd_soc_component_update_bits(component,
  603. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  604. snd_soc_component_update_bits(component,
  605. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  606. snd_soc_component_update_bits(component,
  607. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  608. } else {
  609. snd_soc_component_update_bits(component,
  610. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  611. snd_soc_component_update_bits(component,
  612. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  613. if (wcd938x->comp1_enable)
  614. snd_soc_component_update_bits(component,
  615. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  616. 0x02, 0x02);
  617. }
  618. /* 5 msec delay as per HW requirement */
  619. usleep_range(5000, 5010);
  620. if (wcd938x->flyback_cur_det_disable == 0)
  621. snd_soc_component_update_bits(component,
  622. WCD938X_FLYBACK_EN,
  623. 0x04, 0x00);
  624. wcd938x->flyback_cur_det_disable++;
  625. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  626. WCD_CLSH_EVENT_PRE_DAC,
  627. WCD_CLSH_STATE_EAR,
  628. wcd938x->hph_mode);
  629. break;
  630. case SND_SOC_DAPM_POST_PMD:
  631. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  632. snd_soc_component_update_bits(component,
  633. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  634. snd_soc_component_update_bits(component,
  635. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  636. } else {
  637. snd_soc_component_update_bits(component,
  638. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  639. snd_soc_component_update_bits(component,
  640. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  641. if (wcd938x->comp1_enable)
  642. snd_soc_component_update_bits(component,
  643. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  644. 0x02, 0x00);
  645. }
  646. snd_soc_component_update_bits(component,
  647. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  648. snd_soc_component_update_bits(component,
  649. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  650. break;
  651. };
  652. return 0;
  653. }
  654. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  655. struct snd_kcontrol *kcontrol,
  656. int event)
  657. {
  658. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  659. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  660. int ret = 0;
  661. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  662. w->name, event);
  663. switch (event) {
  664. case SND_SOC_DAPM_PRE_PMU:
  665. wcd938x_rx_clk_enable(component);
  666. snd_soc_component_update_bits(component,
  667. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  668. snd_soc_component_update_bits(component,
  669. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  670. snd_soc_component_update_bits(component,
  671. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  672. if (wcd938x->flyback_cur_det_disable == 0)
  673. snd_soc_component_update_bits(component,
  674. WCD938X_FLYBACK_EN,
  675. 0x04, 0x00);
  676. wcd938x->flyback_cur_det_disable++;
  677. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  678. WCD_CLSH_EVENT_PRE_DAC,
  679. WCD_CLSH_STATE_AUX,
  680. wcd938x->hph_mode);
  681. break;
  682. case SND_SOC_DAPM_POST_PMD:
  683. snd_soc_component_update_bits(component,
  684. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  685. break;
  686. };
  687. return ret;
  688. }
  689. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  690. struct snd_kcontrol *kcontrol,
  691. int event)
  692. {
  693. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  694. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  695. int ret = 0;
  696. int hph_mode = wcd938x->hph_mode;
  697. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  698. w->name, event);
  699. switch (event) {
  700. case SND_SOC_DAPM_PRE_PMU:
  701. if (wcd938x->ldoh)
  702. snd_soc_component_update_bits(component,
  703. WCD938X_LDOH_MODE,
  704. 0x80, 0x80);
  705. if (wcd938x->update_wcd_event)
  706. wcd938x->update_wcd_event(wcd938x->handle,
  707. SLV_BOLERO_EVT_RX_MUTE,
  708. (WCD_RX2 << 0x10 | 0x1));
  709. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  710. wcd938x->rx_swr_dev->dev_num,
  711. true);
  712. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  713. WCD_CLSH_EVENT_PRE_DAC,
  714. WCD_CLSH_STATE_HPHR,
  715. hph_mode);
  716. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  717. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  718. hph_mode == CLS_H_ULP) {
  719. snd_soc_component_update_bits(component,
  720. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  721. }
  722. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  723. 0x10, 0x10);
  724. wcd_clsh_set_hph_mode(component, hph_mode);
  725. /* 100 usec delay as per HW requirement */
  726. usleep_range(100, 110);
  727. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  728. snd_soc_component_update_bits(component,
  729. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  730. break;
  731. case SND_SOC_DAPM_POST_PMU:
  732. /*
  733. * 7ms sleep is required if compander is enabled as per
  734. * HW requirement. If compander is disabled, then
  735. * 20ms delay is required.
  736. */
  737. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  738. if (!wcd938x->comp2_enable)
  739. usleep_range(20000, 20100);
  740. else
  741. usleep_range(7000, 7100);
  742. if (hph_mode == CLS_H_LP ||
  743. hph_mode == CLS_H_LOHIFI ||
  744. hph_mode == CLS_H_ULP)
  745. snd_soc_component_update_bits(component,
  746. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  747. 0x00);
  748. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  749. }
  750. snd_soc_component_update_bits(component,
  751. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  752. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  753. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  754. snd_soc_component_update_bits(component,
  755. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  756. if (wcd938x->update_wcd_event)
  757. wcd938x->update_wcd_event(wcd938x->handle,
  758. SLV_BOLERO_EVT_RX_MUTE,
  759. (WCD_RX2 << 0x10));
  760. wcd_enable_irq(&wcd938x->irq_info,
  761. WCD938X_IRQ_HPHR_PDM_WD_INT);
  762. break;
  763. case SND_SOC_DAPM_PRE_PMD:
  764. if (wcd938x->update_wcd_event)
  765. wcd938x->update_wcd_event(wcd938x->handle,
  766. SLV_BOLERO_EVT_RX_MUTE,
  767. (WCD_RX2 << 0x10 | 0x1));
  768. wcd_disable_irq(&wcd938x->irq_info,
  769. WCD938X_IRQ_HPHR_PDM_WD_INT);
  770. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  771. wcd938x->update_wcd_event(wcd938x->handle,
  772. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  773. (WCD_RX2 << 0x10));
  774. /*
  775. * 7ms sleep is required if compander is enabled as per
  776. * HW requirement. If compander is disabled, then
  777. * 20ms delay is required.
  778. */
  779. if (!wcd938x->comp2_enable)
  780. usleep_range(20000, 20100);
  781. else
  782. usleep_range(7000, 7100);
  783. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  784. 0x40, 0x00);
  785. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  786. WCD_EVENT_PRE_HPHR_PA_OFF,
  787. &wcd938x->mbhc->wcd_mbhc);
  788. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  789. break;
  790. case SND_SOC_DAPM_POST_PMD:
  791. /*
  792. * 7ms sleep is required if compander is enabled as per
  793. * HW requirement. If compander is disabled, then
  794. * 20ms delay is required.
  795. */
  796. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  797. if (!wcd938x->comp2_enable)
  798. usleep_range(20000, 20100);
  799. else
  800. usleep_range(7000, 7100);
  801. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  802. }
  803. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  804. WCD_EVENT_POST_HPHR_PA_OFF,
  805. &wcd938x->mbhc->wcd_mbhc);
  806. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  807. 0x10, 0x00);
  808. snd_soc_component_update_bits(component,
  809. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  810. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  811. WCD_CLSH_EVENT_POST_PA,
  812. WCD_CLSH_STATE_HPHR,
  813. hph_mode);
  814. if (wcd938x->ldoh)
  815. snd_soc_component_update_bits(component,
  816. WCD938X_LDOH_MODE,
  817. 0x80, 0x00);
  818. break;
  819. };
  820. return ret;
  821. }
  822. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  823. struct snd_kcontrol *kcontrol,
  824. int event)
  825. {
  826. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  827. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  828. int ret = 0;
  829. int hph_mode = wcd938x->hph_mode;
  830. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  831. w->name, event);
  832. switch (event) {
  833. case SND_SOC_DAPM_PRE_PMU:
  834. if (wcd938x->ldoh)
  835. snd_soc_component_update_bits(component,
  836. WCD938X_LDOH_MODE,
  837. 0x80, 0x80);
  838. if (wcd938x->update_wcd_event)
  839. wcd938x->update_wcd_event(wcd938x->handle,
  840. SLV_BOLERO_EVT_RX_MUTE,
  841. (WCD_RX1 << 0x10 | 0x01));
  842. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  843. wcd938x->rx_swr_dev->dev_num,
  844. true);
  845. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  846. WCD_CLSH_EVENT_PRE_DAC,
  847. WCD_CLSH_STATE_HPHL,
  848. hph_mode);
  849. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  850. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  851. hph_mode == CLS_H_ULP) {
  852. snd_soc_component_update_bits(component,
  853. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  854. }
  855. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  856. 0x20, 0x20);
  857. wcd_clsh_set_hph_mode(component, hph_mode);
  858. /* 100 usec delay as per HW requirement */
  859. usleep_range(100, 110);
  860. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  861. snd_soc_component_update_bits(component,
  862. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  863. break;
  864. case SND_SOC_DAPM_POST_PMU:
  865. /*
  866. * 7ms sleep is required if compander is enabled as per
  867. * HW requirement. If compander is disabled, then
  868. * 20ms delay is required.
  869. */
  870. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  871. if (!wcd938x->comp1_enable)
  872. usleep_range(20000, 20100);
  873. else
  874. usleep_range(7000, 7100);
  875. if (hph_mode == CLS_H_LP ||
  876. hph_mode == CLS_H_LOHIFI ||
  877. hph_mode == CLS_H_ULP)
  878. snd_soc_component_update_bits(component,
  879. WCD938X_HPH_REFBUFF_LP_CTL,
  880. 0x01, 0x00);
  881. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  882. }
  883. snd_soc_component_update_bits(component,
  884. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  885. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  886. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  887. snd_soc_component_update_bits(component,
  888. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  889. if (wcd938x->update_wcd_event)
  890. wcd938x->update_wcd_event(wcd938x->handle,
  891. SLV_BOLERO_EVT_RX_MUTE,
  892. (WCD_RX1 << 0x10));
  893. wcd_enable_irq(&wcd938x->irq_info,
  894. WCD938X_IRQ_HPHL_PDM_WD_INT);
  895. break;
  896. case SND_SOC_DAPM_PRE_PMD:
  897. if (wcd938x->update_wcd_event)
  898. wcd938x->update_wcd_event(wcd938x->handle,
  899. SLV_BOLERO_EVT_RX_MUTE,
  900. (WCD_RX1 << 0x10 | 0x1));
  901. wcd_disable_irq(&wcd938x->irq_info,
  902. WCD938X_IRQ_HPHL_PDM_WD_INT);
  903. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  904. wcd938x->update_wcd_event(wcd938x->handle,
  905. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  906. (WCD_RX1 << 0x10));
  907. /*
  908. * 7ms sleep is required if compander is enabled as per
  909. * HW requirement. If compander is disabled, then
  910. * 20ms delay is required.
  911. */
  912. if (!wcd938x->comp1_enable)
  913. usleep_range(20000, 20100);
  914. else
  915. usleep_range(7000, 7100);
  916. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  917. 0x80, 0x00);
  918. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  919. WCD_EVENT_PRE_HPHL_PA_OFF,
  920. &wcd938x->mbhc->wcd_mbhc);
  921. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  922. break;
  923. case SND_SOC_DAPM_POST_PMD:
  924. /*
  925. * 7ms sleep is required if compander is enabled as per
  926. * HW requirement. If compander is disabled, then
  927. * 20ms delay is required.
  928. */
  929. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  930. if (!wcd938x->comp1_enable)
  931. usleep_range(21000, 21100);
  932. else
  933. usleep_range(7000, 7100);
  934. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  935. }
  936. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  937. WCD_EVENT_POST_HPHL_PA_OFF,
  938. &wcd938x->mbhc->wcd_mbhc);
  939. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  940. 0x20, 0x00);
  941. snd_soc_component_update_bits(component,
  942. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  943. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  944. WCD_CLSH_EVENT_POST_PA,
  945. WCD_CLSH_STATE_HPHL,
  946. hph_mode);
  947. if (wcd938x->ldoh)
  948. snd_soc_component_update_bits(component,
  949. WCD938X_LDOH_MODE,
  950. 0x80, 0x00);
  951. break;
  952. };
  953. return ret;
  954. }
  955. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  956. struct snd_kcontrol *kcontrol,
  957. int event)
  958. {
  959. struct snd_soc_component *component =
  960. snd_soc_dapm_to_component(w->dapm);
  961. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  962. int hph_mode = wcd938x->hph_mode;
  963. int ret = 0;
  964. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  965. w->name, event);
  966. switch (event) {
  967. case SND_SOC_DAPM_PRE_PMU:
  968. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  969. wcd938x->rx_swr_dev->dev_num,
  970. true);
  971. snd_soc_component_update_bits(component,
  972. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  973. break;
  974. case SND_SOC_DAPM_POST_PMU:
  975. /* 1 msec delay as per HW requirement */
  976. usleep_range(1000, 1010);
  977. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  978. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  979. snd_soc_component_update_bits(component,
  980. WCD938X_ANA_RX_SUPPLIES,
  981. 0x02, 0x02);
  982. if (wcd938x->update_wcd_event)
  983. wcd938x->update_wcd_event(wcd938x->handle,
  984. SLV_BOLERO_EVT_RX_MUTE,
  985. (WCD_RX3 << 0x10));
  986. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  987. break;
  988. case SND_SOC_DAPM_PRE_PMD:
  989. wcd_disable_irq(&wcd938x->irq_info,
  990. WCD938X_IRQ_AUX_PDM_WD_INT);
  991. if (wcd938x->update_wcd_event)
  992. wcd938x->update_wcd_event(wcd938x->handle,
  993. SLV_BOLERO_EVT_RX_MUTE,
  994. (WCD_RX3 << 0x10 | 0x1));
  995. break;
  996. case SND_SOC_DAPM_POST_PMD:
  997. /* 1 msec delay as per HW requirement */
  998. usleep_range(1000, 1010);
  999. snd_soc_component_update_bits(component,
  1000. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1001. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1002. WCD_CLSH_EVENT_POST_PA,
  1003. WCD_CLSH_STATE_AUX,
  1004. hph_mode);
  1005. wcd938x->flyback_cur_det_disable--;
  1006. if (wcd938x->flyback_cur_det_disable == 0)
  1007. snd_soc_component_update_bits(component,
  1008. WCD938X_FLYBACK_EN,
  1009. 0x04, 0x04);
  1010. break;
  1011. };
  1012. return ret;
  1013. }
  1014. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1015. struct snd_kcontrol *kcontrol,
  1016. int event)
  1017. {
  1018. struct snd_soc_component *component =
  1019. snd_soc_dapm_to_component(w->dapm);
  1020. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1021. int hph_mode = wcd938x->hph_mode;
  1022. int ret = 0;
  1023. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1024. w->name, event);
  1025. switch (event) {
  1026. case SND_SOC_DAPM_PRE_PMU:
  1027. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1028. wcd938x->rx_swr_dev->dev_num,
  1029. true);
  1030. /*
  1031. * Enable watchdog interrupt for HPHL or AUX
  1032. * depending on mux value
  1033. */
  1034. wcd938x->ear_rx_path =
  1035. snd_soc_component_read32(
  1036. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1037. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1038. snd_soc_component_update_bits(component,
  1039. WCD938X_DIGITAL_PDM_WD_CTL2,
  1040. 0x01, 0x01);
  1041. else
  1042. snd_soc_component_update_bits(component,
  1043. WCD938X_DIGITAL_PDM_WD_CTL0,
  1044. 0x07, 0x03);
  1045. if (!wcd938x->comp1_enable)
  1046. snd_soc_component_update_bits(component,
  1047. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1048. break;
  1049. case SND_SOC_DAPM_POST_PMU:
  1050. /* 6 msec delay as per HW requirement */
  1051. usleep_range(6000, 6010);
  1052. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1053. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1054. snd_soc_component_update_bits(component,
  1055. WCD938X_ANA_RX_SUPPLIES,
  1056. 0x02, 0x02);
  1057. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1058. if (wcd938x->update_wcd_event)
  1059. wcd938x->update_wcd_event(wcd938x->handle,
  1060. SLV_BOLERO_EVT_RX_MUTE,
  1061. (WCD_RX3 << 0x10));
  1062. wcd_enable_irq(&wcd938x->irq_info,
  1063. WCD938X_IRQ_AUX_PDM_WD_INT);
  1064. } else {
  1065. if (wcd938x->update_wcd_event)
  1066. wcd938x->update_wcd_event(wcd938x->handle,
  1067. SLV_BOLERO_EVT_RX_MUTE,
  1068. (WCD_RX1 << 0x10));
  1069. wcd_enable_irq(&wcd938x->irq_info,
  1070. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1071. }
  1072. break;
  1073. case SND_SOC_DAPM_PRE_PMD:
  1074. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1075. wcd_disable_irq(&wcd938x->irq_info,
  1076. WCD938X_IRQ_AUX_PDM_WD_INT);
  1077. if (wcd938x->update_wcd_event)
  1078. wcd938x->update_wcd_event(wcd938x->handle,
  1079. SLV_BOLERO_EVT_RX_MUTE,
  1080. (WCD_RX3 << 0x10 | 0x1));
  1081. } else {
  1082. wcd_disable_irq(&wcd938x->irq_info,
  1083. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1084. if (wcd938x->update_wcd_event)
  1085. wcd938x->update_wcd_event(wcd938x->handle,
  1086. SLV_BOLERO_EVT_RX_MUTE,
  1087. (WCD_RX1 << 0x10 | 0x1));
  1088. }
  1089. break;
  1090. case SND_SOC_DAPM_POST_PMD:
  1091. if (!wcd938x->comp1_enable)
  1092. snd_soc_component_update_bits(component,
  1093. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1094. /* 7 msec delay as per HW requirement */
  1095. usleep_range(7000, 7010);
  1096. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1097. snd_soc_component_update_bits(component,
  1098. WCD938X_DIGITAL_PDM_WD_CTL2,
  1099. 0x01, 0x00);
  1100. else
  1101. snd_soc_component_update_bits(component,
  1102. WCD938X_DIGITAL_PDM_WD_CTL0,
  1103. 0x07, 0x00);
  1104. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1105. WCD_CLSH_EVENT_POST_PA,
  1106. WCD_CLSH_STATE_EAR,
  1107. hph_mode);
  1108. wcd938x->flyback_cur_det_disable--;
  1109. if (wcd938x->flyback_cur_det_disable == 0)
  1110. snd_soc_component_update_bits(component,
  1111. WCD938X_FLYBACK_EN,
  1112. 0x04, 0x04);
  1113. break;
  1114. };
  1115. return ret;
  1116. }
  1117. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1118. struct snd_kcontrol *kcontrol,
  1119. int event)
  1120. {
  1121. struct snd_soc_component *component =
  1122. snd_soc_dapm_to_component(w->dapm);
  1123. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1124. int mode = wcd938x->hph_mode;
  1125. int ret = 0;
  1126. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1127. w->name, event);
  1128. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1129. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1130. wcd938x_rx_connect_port(component, CLSH,
  1131. SND_SOC_DAPM_EVENT_ON(event));
  1132. }
  1133. if (SND_SOC_DAPM_EVENT_OFF(event))
  1134. ret = swr_slvdev_datapath_control(
  1135. wcd938x->rx_swr_dev,
  1136. wcd938x->rx_swr_dev->dev_num,
  1137. false);
  1138. return ret;
  1139. }
  1140. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1141. struct snd_kcontrol *kcontrol,
  1142. int event)
  1143. {
  1144. struct snd_soc_component *component =
  1145. snd_soc_dapm_to_component(w->dapm);
  1146. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1147. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1148. w->name, event);
  1149. switch (event) {
  1150. case SND_SOC_DAPM_PRE_PMU:
  1151. wcd938x_rx_connect_port(component, HPH_L, true);
  1152. if (wcd938x->comp1_enable)
  1153. wcd938x_rx_connect_port(component, COMP_L, true);
  1154. break;
  1155. case SND_SOC_DAPM_POST_PMD:
  1156. wcd938x_rx_connect_port(component, HPH_L, false);
  1157. if (wcd938x->comp1_enable)
  1158. wcd938x_rx_connect_port(component, COMP_L, false);
  1159. wcd938x_rx_clk_disable(component);
  1160. snd_soc_component_update_bits(component,
  1161. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1162. 0x01, 0x00);
  1163. break;
  1164. };
  1165. return 0;
  1166. }
  1167. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1168. struct snd_kcontrol *kcontrol, int event)
  1169. {
  1170. struct snd_soc_component *component =
  1171. snd_soc_dapm_to_component(w->dapm);
  1172. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1173. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1174. w->name, event);
  1175. switch (event) {
  1176. case SND_SOC_DAPM_PRE_PMU:
  1177. wcd938x_rx_connect_port(component, HPH_R, true);
  1178. if (wcd938x->comp2_enable)
  1179. wcd938x_rx_connect_port(component, COMP_R, true);
  1180. break;
  1181. case SND_SOC_DAPM_POST_PMD:
  1182. wcd938x_rx_connect_port(component, HPH_R, false);
  1183. if (wcd938x->comp2_enable)
  1184. wcd938x_rx_connect_port(component, COMP_R, false);
  1185. wcd938x_rx_clk_disable(component);
  1186. snd_soc_component_update_bits(component,
  1187. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1188. 0x02, 0x00);
  1189. break;
  1190. };
  1191. return 0;
  1192. }
  1193. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1194. struct snd_kcontrol *kcontrol,
  1195. int event)
  1196. {
  1197. struct snd_soc_component *component =
  1198. snd_soc_dapm_to_component(w->dapm);
  1199. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1200. w->name, event);
  1201. switch (event) {
  1202. case SND_SOC_DAPM_PRE_PMU:
  1203. wcd938x_rx_connect_port(component, LO, true);
  1204. break;
  1205. case SND_SOC_DAPM_POST_PMD:
  1206. wcd938x_rx_connect_port(component, LO, false);
  1207. /* 6 msec delay as per HW requirement */
  1208. usleep_range(6000, 6010);
  1209. wcd938x_rx_clk_disable(component);
  1210. snd_soc_component_update_bits(component,
  1211. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1212. break;
  1213. }
  1214. return 0;
  1215. }
  1216. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1217. struct snd_kcontrol *kcontrol,
  1218. int event)
  1219. {
  1220. struct snd_soc_component *component =
  1221. snd_soc_dapm_to_component(w->dapm);
  1222. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1223. u16 dmic_clk_reg, dmic_clk_en_reg;
  1224. s32 *dmic_clk_cnt;
  1225. u8 dmic_ctl_shift = 0;
  1226. u8 dmic_clk_shift = 0;
  1227. u8 dmic_clk_mask = 0;
  1228. u16 dmic2_left_en = 0;
  1229. int ret = 0;
  1230. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1231. w->name, event);
  1232. switch (w->shift) {
  1233. case 0:
  1234. case 1:
  1235. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1236. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1237. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1238. dmic_clk_mask = 0x0F;
  1239. dmic_clk_shift = 0x00;
  1240. dmic_ctl_shift = 0x00;
  1241. break;
  1242. case 2:
  1243. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1244. case 3:
  1245. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1246. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1247. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1248. dmic_clk_mask = 0xF0;
  1249. dmic_clk_shift = 0x04;
  1250. dmic_ctl_shift = 0x01;
  1251. break;
  1252. case 4:
  1253. case 5:
  1254. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1255. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1256. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1257. dmic_clk_mask = 0x0F;
  1258. dmic_clk_shift = 0x00;
  1259. dmic_ctl_shift = 0x02;
  1260. break;
  1261. case 6:
  1262. case 7:
  1263. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1264. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1265. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1266. dmic_clk_mask = 0xF0;
  1267. dmic_clk_shift = 0x04;
  1268. dmic_ctl_shift = 0x03;
  1269. break;
  1270. default:
  1271. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1272. __func__);
  1273. return -EINVAL;
  1274. };
  1275. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1276. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1277. switch (event) {
  1278. case SND_SOC_DAPM_PRE_PMU:
  1279. snd_soc_component_update_bits(component,
  1280. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1281. (0x01 << dmic_ctl_shift), 0x00);
  1282. /* 250us sleep as per HW requirement */
  1283. usleep_range(250, 260);
  1284. if (dmic2_left_en)
  1285. snd_soc_component_update_bits(component,
  1286. dmic2_left_en, 0x80, 0x80);
  1287. /* Setting DMIC clock rate to 2.4MHz */
  1288. snd_soc_component_update_bits(component,
  1289. dmic_clk_reg, dmic_clk_mask,
  1290. (0x03 << dmic_clk_shift));
  1291. snd_soc_component_update_bits(component,
  1292. dmic_clk_en_reg, 0x08, 0x08);
  1293. /* enable clock scaling */
  1294. snd_soc_component_update_bits(component,
  1295. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1296. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1297. wcd938x->tx_swr_dev->dev_num,
  1298. true);
  1299. break;
  1300. case SND_SOC_DAPM_POST_PMD:
  1301. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1302. false);
  1303. snd_soc_component_update_bits(component,
  1304. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1305. (0x01 << dmic_ctl_shift),
  1306. (0x01 << dmic_ctl_shift));
  1307. if (dmic2_left_en)
  1308. snd_soc_component_update_bits(component,
  1309. dmic2_left_en, 0x80, 0x00);
  1310. snd_soc_component_update_bits(component,
  1311. dmic_clk_en_reg, 0x08, 0x00);
  1312. break;
  1313. };
  1314. return ret;
  1315. }
  1316. /*
  1317. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1318. * @micb_mv: micbias in mv
  1319. *
  1320. * return register value converted
  1321. */
  1322. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1323. {
  1324. /* min micbias voltage is 1V and maximum is 2.85V */
  1325. if (micb_mv < 1000 || micb_mv > 2850) {
  1326. pr_err("%s: unsupported micbias voltage\n", __func__);
  1327. return -EINVAL;
  1328. }
  1329. return (micb_mv - 1000) / 50;
  1330. }
  1331. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1332. /*
  1333. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1334. * @component: handle to snd_soc_component *
  1335. * @req_volt: micbias voltage to be set
  1336. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1337. *
  1338. * return 0 if adjustment is success or error code in case of failure
  1339. */
  1340. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1341. int req_volt, int micb_num)
  1342. {
  1343. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1344. int cur_vout_ctl, req_vout_ctl;
  1345. int micb_reg, micb_val, micb_en;
  1346. int ret = 0;
  1347. switch (micb_num) {
  1348. case MIC_BIAS_1:
  1349. micb_reg = WCD938X_ANA_MICB1;
  1350. break;
  1351. case MIC_BIAS_2:
  1352. micb_reg = WCD938X_ANA_MICB2;
  1353. break;
  1354. case MIC_BIAS_3:
  1355. micb_reg = WCD938X_ANA_MICB3;
  1356. break;
  1357. case MIC_BIAS_4:
  1358. micb_reg = WCD938X_ANA_MICB4;
  1359. break;
  1360. default:
  1361. return -EINVAL;
  1362. }
  1363. mutex_lock(&wcd938x->micb_lock);
  1364. /*
  1365. * If requested micbias voltage is same as current micbias
  1366. * voltage, then just return. Otherwise, adjust voltage as
  1367. * per requested value. If micbias is already enabled, then
  1368. * to avoid slow micbias ramp-up or down enable pull-up
  1369. * momentarily, change the micbias value and then re-enable
  1370. * micbias.
  1371. */
  1372. micb_val = snd_soc_component_read32(component, micb_reg);
  1373. micb_en = (micb_val & 0xC0) >> 6;
  1374. cur_vout_ctl = micb_val & 0x3F;
  1375. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1376. if (req_vout_ctl < 0) {
  1377. ret = -EINVAL;
  1378. goto exit;
  1379. }
  1380. if (cur_vout_ctl == req_vout_ctl) {
  1381. ret = 0;
  1382. goto exit;
  1383. }
  1384. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1385. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1386. req_volt, micb_en);
  1387. if (micb_en == 0x1)
  1388. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1389. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1390. if (micb_en == 0x1) {
  1391. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1392. /*
  1393. * Add 2ms delay as per HW requirement after enabling
  1394. * micbias
  1395. */
  1396. usleep_range(2000, 2100);
  1397. }
  1398. exit:
  1399. mutex_unlock(&wcd938x->micb_lock);
  1400. return ret;
  1401. }
  1402. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1403. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1404. struct snd_kcontrol *kcontrol,
  1405. int event)
  1406. {
  1407. struct snd_soc_component *component =
  1408. snd_soc_dapm_to_component(w->dapm);
  1409. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1410. int ret = 0;
  1411. int bank = 0;
  1412. u8 mode = 0;
  1413. int i = 0;
  1414. int rate = 0;
  1415. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1416. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1417. /* power mode is applicable only to analog mics */
  1418. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1419. /* Get channel rate */
  1420. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1421. }
  1422. switch (event) {
  1423. case SND_SOC_DAPM_PRE_PMU:
  1424. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1425. if (w->shift == ADC2 && !(snd_soc_component_read32(component,
  1426. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1427. if (!wcd938x->bcs_dis)
  1428. wcd938x_tx_connect_port(component, MBHC,
  1429. SWR_CLK_RATE_4P8MHZ, true);
  1430. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1431. }
  1432. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1433. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1434. wcd938x_tx_connect_port(component, w->shift, rate,
  1435. true);
  1436. } else {
  1437. wcd938x_tx_connect_port(component, w->shift,
  1438. SWR_CLK_RATE_2P4MHZ, true);
  1439. }
  1440. break;
  1441. case SND_SOC_DAPM_POST_PMD:
  1442. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1443. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1444. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1445. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1446. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1447. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1448. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1449. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1450. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1451. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1452. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1453. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1454. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1455. }
  1456. }
  1457. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1458. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1459. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1460. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1461. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1462. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1463. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1464. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1465. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1466. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1467. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1468. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1469. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1470. if (mode != 0) {
  1471. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1472. if (mode & (1 << i)) {
  1473. i++;
  1474. break;
  1475. }
  1476. }
  1477. }
  1478. rate = wcd938x_get_clk_rate(i);
  1479. if (wcd938x->adc_count) {
  1480. rate = (wcd938x->adc_count * rate);
  1481. if (rate > SWR_CLK_RATE_9P6MHZ)
  1482. rate = SWR_CLK_RATE_9P6MHZ;
  1483. }
  1484. wcd938x_set_swr_clk_rate(component, rate, bank);
  1485. }
  1486. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1487. wcd938x->tx_swr_dev->dev_num,
  1488. false);
  1489. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1490. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1491. break;
  1492. };
  1493. return ret;
  1494. }
  1495. static int wcd938x_get_adc_mode(int val)
  1496. {
  1497. int ret = 0;
  1498. switch (val) {
  1499. case ADC_MODE_INVALID:
  1500. ret = ADC_MODE_VAL_NORMAL;
  1501. break;
  1502. case ADC_MODE_HIFI:
  1503. ret = ADC_MODE_VAL_HIFI;
  1504. break;
  1505. case ADC_MODE_LO_HIF:
  1506. ret = ADC_MODE_VAL_LO_HIF;
  1507. break;
  1508. case ADC_MODE_NORMAL:
  1509. ret = ADC_MODE_VAL_NORMAL;
  1510. break;
  1511. case ADC_MODE_LP:
  1512. ret = ADC_MODE_VAL_LP;
  1513. break;
  1514. case ADC_MODE_ULP1:
  1515. ret = ADC_MODE_VAL_ULP1;
  1516. break;
  1517. case ADC_MODE_ULP2:
  1518. ret = ADC_MODE_VAL_ULP2;
  1519. break;
  1520. default:
  1521. ret = -EINVAL;
  1522. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1523. break;
  1524. }
  1525. return ret;
  1526. }
  1527. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1528. int channel, int mode)
  1529. {
  1530. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1531. int ret = 0;
  1532. switch (channel) {
  1533. case 0:
  1534. reg = WCD938X_ANA_TX_CH2;
  1535. mask = 0x40;
  1536. break;
  1537. case 1:
  1538. reg = WCD938X_ANA_TX_CH2;
  1539. mask = 0x20;
  1540. break;
  1541. case 2:
  1542. reg = WCD938X_ANA_TX_CH4;
  1543. mask = 0x40;
  1544. break;
  1545. case 3:
  1546. reg = WCD938X_ANA_TX_CH4;
  1547. mask = 0x20;
  1548. break;
  1549. default:
  1550. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1551. ret = -EINVAL;
  1552. break;
  1553. }
  1554. if (!mode)
  1555. val = 0x00;
  1556. else
  1557. val = mask;
  1558. if (!ret)
  1559. snd_soc_component_update_bits(component, reg, mask, val);
  1560. return ret;
  1561. }
  1562. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1563. struct snd_kcontrol *kcontrol,
  1564. int event){
  1565. struct snd_soc_component *component =
  1566. snd_soc_dapm_to_component(w->dapm);
  1567. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1568. int clk_rate = 0, ret = 0;
  1569. int mode = 0, i = 0, bank = 0;
  1570. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1571. w->name, event);
  1572. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1573. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1574. switch (event) {
  1575. case SND_SOC_DAPM_PRE_PMU:
  1576. wcd938x->adc_count++;
  1577. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1578. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1579. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1580. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1581. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1582. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1583. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1584. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1585. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1586. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1587. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1588. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1589. if (mode != 0) {
  1590. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1591. if (mode & (1 << i)) {
  1592. i++;
  1593. break;
  1594. }
  1595. }
  1596. }
  1597. clk_rate = wcd938x_get_clk_rate(i);
  1598. /* clk_rate depends on number of paths getting enabled */
  1599. clk_rate = (wcd938x->adc_count * clk_rate);
  1600. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1601. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1602. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1603. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1604. wcd938x->tx_swr_dev->dev_num,
  1605. true);
  1606. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1607. break;
  1608. case SND_SOC_DAPM_POST_PMD:
  1609. wcd938x->adc_count--;
  1610. if (wcd938x->adc_count < 0)
  1611. wcd938x->adc_count = 0;
  1612. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1613. if (w->shift + ADC1 == ADC2 &&
  1614. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1615. if (!wcd938x->bcs_dis)
  1616. wcd938x_tx_connect_port(component, MBHC, 0,
  1617. false);
  1618. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1619. }
  1620. break;
  1621. };
  1622. return ret;
  1623. }
  1624. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1625. bool bcs_disable)
  1626. {
  1627. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1628. if (wcd938x->update_wcd_event) {
  1629. if (bcs_disable)
  1630. wcd938x->update_wcd_event(wcd938x->handle,
  1631. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1632. else
  1633. wcd938x->update_wcd_event(wcd938x->handle,
  1634. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1635. }
  1636. }
  1637. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1638. struct snd_kcontrol *kcontrol, int event)
  1639. {
  1640. struct snd_soc_component *component =
  1641. snd_soc_dapm_to_component(w->dapm);
  1642. struct wcd938x_priv *wcd938x =
  1643. snd_soc_component_get_drvdata(component);
  1644. int ret = 0;
  1645. u8 mode = 0;
  1646. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1647. w->name, event);
  1648. switch (event) {
  1649. case SND_SOC_DAPM_PRE_PMU:
  1650. snd_soc_component_update_bits(component,
  1651. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1652. snd_soc_component_update_bits(component,
  1653. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1654. snd_soc_component_update_bits(component,
  1655. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1656. snd_soc_component_update_bits(component,
  1657. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1658. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1659. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1660. if (mode < 0) {
  1661. dev_info(component->dev,
  1662. "%s: invalid mode, setting to normal mode\n",
  1663. __func__);
  1664. mode = ADC_MODE_VAL_NORMAL;
  1665. }
  1666. switch (w->shift) {
  1667. case 0:
  1668. snd_soc_component_update_bits(component,
  1669. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1670. mode);
  1671. snd_soc_component_update_bits(component,
  1672. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1673. break;
  1674. case 1:
  1675. snd_soc_component_update_bits(component,
  1676. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1677. mode << 4);
  1678. snd_soc_component_update_bits(component,
  1679. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1680. break;
  1681. case 2:
  1682. snd_soc_component_update_bits(component,
  1683. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1684. mode);
  1685. snd_soc_component_update_bits(component,
  1686. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1687. break;
  1688. case 3:
  1689. snd_soc_component_update_bits(component,
  1690. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1691. mode << 4);
  1692. snd_soc_component_update_bits(component,
  1693. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1694. break;
  1695. default:
  1696. break;
  1697. }
  1698. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1699. break;
  1700. case SND_SOC_DAPM_POST_PMD:
  1701. switch (w->shift) {
  1702. case 0:
  1703. snd_soc_component_update_bits(component,
  1704. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1705. 0x00);
  1706. snd_soc_component_update_bits(component,
  1707. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1708. break;
  1709. case 1:
  1710. snd_soc_component_update_bits(component,
  1711. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1712. 0x00);
  1713. snd_soc_component_update_bits(component,
  1714. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1715. break;
  1716. case 2:
  1717. snd_soc_component_update_bits(component,
  1718. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1719. 0x00);
  1720. snd_soc_component_update_bits(component,
  1721. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1722. break;
  1723. case 3:
  1724. snd_soc_component_update_bits(component,
  1725. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1726. 0x00);
  1727. snd_soc_component_update_bits(component,
  1728. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1729. break;
  1730. default:
  1731. break;
  1732. }
  1733. if (wcd938x->adc_count == 0)
  1734. snd_soc_component_update_bits(component,
  1735. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1736. break;
  1737. };
  1738. return ret;
  1739. }
  1740. int wcd938x_micbias_control(struct snd_soc_component *component,
  1741. int micb_num, int req, bool is_dapm)
  1742. {
  1743. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1744. int micb_index = micb_num - 1;
  1745. u16 micb_reg;
  1746. int pre_off_event = 0, post_off_event = 0;
  1747. int post_on_event = 0, post_dapm_off = 0;
  1748. int post_dapm_on = 0;
  1749. int ret = 0;
  1750. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1751. dev_err(component->dev,
  1752. "%s: Invalid micbias index, micb_ind:%d\n",
  1753. __func__, micb_index);
  1754. return -EINVAL;
  1755. }
  1756. if (NULL == wcd938x) {
  1757. dev_err(component->dev,
  1758. "%s: wcd938x private data is NULL\n", __func__);
  1759. return -EINVAL;
  1760. }
  1761. switch (micb_num) {
  1762. case MIC_BIAS_1:
  1763. micb_reg = WCD938X_ANA_MICB1;
  1764. break;
  1765. case MIC_BIAS_2:
  1766. micb_reg = WCD938X_ANA_MICB2;
  1767. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1768. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1769. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1770. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1771. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1772. break;
  1773. case MIC_BIAS_3:
  1774. micb_reg = WCD938X_ANA_MICB3;
  1775. break;
  1776. case MIC_BIAS_4:
  1777. micb_reg = WCD938X_ANA_MICB4;
  1778. break;
  1779. default:
  1780. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1781. __func__, micb_num);
  1782. return -EINVAL;
  1783. };
  1784. mutex_lock(&wcd938x->micb_lock);
  1785. switch (req) {
  1786. case MICB_PULLUP_ENABLE:
  1787. if (!wcd938x->dev_up) {
  1788. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1789. __func__, req);
  1790. ret = -ENODEV;
  1791. goto done;
  1792. }
  1793. wcd938x->pullup_ref[micb_index]++;
  1794. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1795. (wcd938x->micb_ref[micb_index] == 0))
  1796. snd_soc_component_update_bits(component, micb_reg,
  1797. 0xC0, 0x80);
  1798. break;
  1799. case MICB_PULLUP_DISABLE:
  1800. if (wcd938x->pullup_ref[micb_index] > 0)
  1801. wcd938x->pullup_ref[micb_index]--;
  1802. if (!wcd938x->dev_up) {
  1803. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1804. __func__, req);
  1805. ret = -ENODEV;
  1806. goto done;
  1807. }
  1808. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1809. (wcd938x->micb_ref[micb_index] == 0))
  1810. snd_soc_component_update_bits(component, micb_reg,
  1811. 0xC0, 0x00);
  1812. break;
  1813. case MICB_ENABLE:
  1814. if (!wcd938x->dev_up) {
  1815. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1816. __func__, req);
  1817. ret = -ENODEV;
  1818. goto done;
  1819. }
  1820. wcd938x->micb_ref[micb_index]++;
  1821. if (wcd938x->micb_ref[micb_index] == 1) {
  1822. snd_soc_component_update_bits(component,
  1823. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1824. snd_soc_component_update_bits(component,
  1825. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1826. snd_soc_component_update_bits(component,
  1827. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1828. snd_soc_component_update_bits(component,
  1829. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1830. snd_soc_component_update_bits(component,
  1831. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1832. snd_soc_component_update_bits(component,
  1833. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1834. snd_soc_component_update_bits(component,
  1835. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1836. snd_soc_component_update_bits(component,
  1837. micb_reg, 0xC0, 0x40);
  1838. if (post_on_event)
  1839. blocking_notifier_call_chain(
  1840. &wcd938x->mbhc->notifier,
  1841. post_on_event,
  1842. &wcd938x->mbhc->wcd_mbhc);
  1843. }
  1844. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1845. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1846. post_dapm_on,
  1847. &wcd938x->mbhc->wcd_mbhc);
  1848. break;
  1849. case MICB_DISABLE:
  1850. if (wcd938x->micb_ref[micb_index] > 0)
  1851. wcd938x->micb_ref[micb_index]--;
  1852. if (!wcd938x->dev_up) {
  1853. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1854. __func__, req);
  1855. ret = -ENODEV;
  1856. goto done;
  1857. }
  1858. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1859. (wcd938x->pullup_ref[micb_index] > 0))
  1860. snd_soc_component_update_bits(component, micb_reg,
  1861. 0xC0, 0x80);
  1862. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1863. (wcd938x->pullup_ref[micb_index] == 0)) {
  1864. if (pre_off_event && wcd938x->mbhc)
  1865. blocking_notifier_call_chain(
  1866. &wcd938x->mbhc->notifier,
  1867. pre_off_event,
  1868. &wcd938x->mbhc->wcd_mbhc);
  1869. snd_soc_component_update_bits(component, micb_reg,
  1870. 0xC0, 0x00);
  1871. if (post_off_event && wcd938x->mbhc)
  1872. blocking_notifier_call_chain(
  1873. &wcd938x->mbhc->notifier,
  1874. post_off_event,
  1875. &wcd938x->mbhc->wcd_mbhc);
  1876. }
  1877. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1878. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1879. post_dapm_off,
  1880. &wcd938x->mbhc->wcd_mbhc);
  1881. break;
  1882. };
  1883. dev_dbg(component->dev,
  1884. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1885. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1886. wcd938x->pullup_ref[micb_index]);
  1887. done:
  1888. mutex_unlock(&wcd938x->micb_lock);
  1889. return ret;
  1890. }
  1891. EXPORT_SYMBOL(wcd938x_micbias_control);
  1892. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1893. {
  1894. int ret = 0;
  1895. uint8_t devnum = 0;
  1896. int num_retry = NUM_ATTEMPTS;
  1897. do {
  1898. /* retry after 1ms */
  1899. usleep_range(1000, 1010);
  1900. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1901. } while (ret && --num_retry);
  1902. if (ret)
  1903. dev_err(&swr_dev->dev,
  1904. "%s get devnum %d for dev addr %llx failed\n",
  1905. __func__, devnum, swr_dev->addr);
  1906. swr_dev->dev_num = devnum;
  1907. return 0;
  1908. }
  1909. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1910. struct wcd_mbhc_config *mbhc_cfg)
  1911. {
  1912. if (mbhc_cfg->enable_usbc_analog) {
  1913. if (!(snd_soc_component_read32(component, WCD938X_ANA_MBHC_MECH)
  1914. & 0x20))
  1915. return true;
  1916. }
  1917. return false;
  1918. }
  1919. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1920. struct notifier_block *nblock,
  1921. bool enable)
  1922. {
  1923. struct wcd938x_priv *wcd938x_priv;
  1924. if(NULL == component) {
  1925. pr_err("%s: wcd938x component is NULL\n", __func__);
  1926. return -EINVAL;
  1927. }
  1928. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1929. wcd938x_priv->notify_swr_dmic = enable;
  1930. if (enable)
  1931. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  1932. nblock);
  1933. else
  1934. return blocking_notifier_chain_unregister(
  1935. &wcd938x_priv->notifier, nblock);
  1936. }
  1937. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  1938. static int wcd938x_event_notify(struct notifier_block *block,
  1939. unsigned long val,
  1940. void *data)
  1941. {
  1942. u16 event = (val & 0xffff);
  1943. int ret = 0;
  1944. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1945. struct snd_soc_component *component = wcd938x->component;
  1946. struct wcd_mbhc *mbhc;
  1947. switch (event) {
  1948. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1949. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1950. snd_soc_component_update_bits(component,
  1951. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1952. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1953. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1954. }
  1955. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1956. snd_soc_component_update_bits(component,
  1957. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1958. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1959. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1960. }
  1961. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1962. snd_soc_component_update_bits(component,
  1963. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1964. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1965. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1966. }
  1967. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1968. snd_soc_component_update_bits(component,
  1969. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1970. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1971. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1972. }
  1973. break;
  1974. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1975. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1976. 0xC0, 0x00);
  1977. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1978. 0x80, 0x00);
  1979. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1980. 0x80, 0x00);
  1981. break;
  1982. case BOLERO_SLV_EVT_SSR_DOWN:
  1983. wcd938x->dev_up = false;
  1984. if(wcd938x->notify_swr_dmic)
  1985. blocking_notifier_call_chain(&wcd938x->notifier,
  1986. WCD938X_EVT_SSR_DOWN,
  1987. NULL);
  1988. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1989. wcd938x->mbhc->wcd_mbhc.plug_before_ssr =
  1990. wcd938x->mbhc->wcd_mbhc.current_plug;
  1991. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1992. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  1993. mbhc->mbhc_cfg);
  1994. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1995. wcd938x_reset_low(wcd938x->dev);
  1996. break;
  1997. case BOLERO_SLV_EVT_SSR_UP:
  1998. wcd938x_reset(wcd938x->dev);
  1999. /* allow reset to take effect */
  2000. usleep_range(10000, 10010);
  2001. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2002. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2003. wcd938x_init_reg(component);
  2004. regcache_mark_dirty(wcd938x->regmap);
  2005. regcache_sync(wcd938x->regmap);
  2006. /* Initialize MBHC module */
  2007. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2008. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2009. if (ret) {
  2010. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2011. __func__);
  2012. } else {
  2013. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2014. if (wcd938x->usbc_hs_status)
  2015. mdelay(500);
  2016. }
  2017. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2018. wcd938x->dev_up = true;
  2019. if(wcd938x->notify_swr_dmic)
  2020. blocking_notifier_call_chain(&wcd938x->notifier,
  2021. WCD938X_EVT_SSR_UP,
  2022. NULL);
  2023. break;
  2024. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2025. snd_soc_component_update_bits(component,
  2026. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2027. ((val >> 0x10) << 0x01));
  2028. break;
  2029. default:
  2030. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2031. break;
  2032. }
  2033. return 0;
  2034. }
  2035. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2036. int event)
  2037. {
  2038. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2039. int micb_num;
  2040. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2041. __func__, w->name, event);
  2042. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2043. micb_num = MIC_BIAS_1;
  2044. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2045. micb_num = MIC_BIAS_2;
  2046. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2047. micb_num = MIC_BIAS_3;
  2048. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2049. micb_num = MIC_BIAS_4;
  2050. else
  2051. return -EINVAL;
  2052. switch (event) {
  2053. case SND_SOC_DAPM_PRE_PMU:
  2054. wcd938x_micbias_control(component, micb_num,
  2055. MICB_ENABLE, true);
  2056. break;
  2057. case SND_SOC_DAPM_POST_PMU:
  2058. /* 1 msec delay as per HW requirement */
  2059. usleep_range(1000, 1100);
  2060. break;
  2061. case SND_SOC_DAPM_POST_PMD:
  2062. wcd938x_micbias_control(component, micb_num,
  2063. MICB_DISABLE, true);
  2064. break;
  2065. };
  2066. return 0;
  2067. }
  2068. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2069. struct snd_kcontrol *kcontrol,
  2070. int event)
  2071. {
  2072. return __wcd938x_codec_enable_micbias(w, event);
  2073. }
  2074. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2075. int event)
  2076. {
  2077. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2078. int micb_num;
  2079. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2080. __func__, w->name, event);
  2081. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2082. micb_num = MIC_BIAS_1;
  2083. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2084. micb_num = MIC_BIAS_2;
  2085. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2086. micb_num = MIC_BIAS_3;
  2087. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2088. micb_num = MIC_BIAS_4;
  2089. else
  2090. return -EINVAL;
  2091. switch (event) {
  2092. case SND_SOC_DAPM_PRE_PMU:
  2093. wcd938x_micbias_control(component, micb_num,
  2094. MICB_PULLUP_ENABLE, true);
  2095. break;
  2096. case SND_SOC_DAPM_POST_PMU:
  2097. /* 1 msec delay as per HW requirement */
  2098. usleep_range(1000, 1100);
  2099. break;
  2100. case SND_SOC_DAPM_POST_PMD:
  2101. wcd938x_micbias_control(component, micb_num,
  2102. MICB_PULLUP_DISABLE, true);
  2103. break;
  2104. };
  2105. return 0;
  2106. }
  2107. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2108. struct snd_kcontrol *kcontrol,
  2109. int event)
  2110. {
  2111. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2112. }
  2113. static int wcd938x_wakeup(void *handle, bool enable)
  2114. {
  2115. struct wcd938x_priv *priv;
  2116. int ret = 0;
  2117. if (!handle) {
  2118. pr_err("%s: NULL handle\n", __func__);
  2119. return -EINVAL;
  2120. }
  2121. priv = (struct wcd938x_priv *)handle;
  2122. if (!priv->tx_swr_dev) {
  2123. pr_err("%s: tx swr dev is NULL\n", __func__);
  2124. return -EINVAL;
  2125. }
  2126. mutex_lock(&priv->wakeup_lock);
  2127. if (enable)
  2128. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2129. else
  2130. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2131. mutex_unlock(&priv->wakeup_lock);
  2132. return ret;
  2133. }
  2134. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2135. struct snd_kcontrol *kcontrol,
  2136. int event)
  2137. {
  2138. int ret = 0;
  2139. struct snd_soc_component *component =
  2140. snd_soc_dapm_to_component(w->dapm);
  2141. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2142. switch (event) {
  2143. case SND_SOC_DAPM_PRE_PMU:
  2144. wcd938x_wakeup(wcd938x, true);
  2145. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2146. wcd938x_wakeup(wcd938x, false);
  2147. break;
  2148. case SND_SOC_DAPM_POST_PMD:
  2149. wcd938x_wakeup(wcd938x, true);
  2150. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2151. wcd938x_wakeup(wcd938x, false);
  2152. break;
  2153. }
  2154. return ret;
  2155. }
  2156. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2157. int micb_num, int req)
  2158. {
  2159. int micb_index = micb_num - 1;
  2160. u16 micb_reg;
  2161. if (NULL == wcd938x) {
  2162. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2163. return -EINVAL;
  2164. }
  2165. switch (micb_num) {
  2166. case MIC_BIAS_1:
  2167. micb_reg = WCD938X_ANA_MICB1;
  2168. break;
  2169. case MIC_BIAS_2:
  2170. micb_reg = WCD938X_ANA_MICB2;
  2171. break;
  2172. case MIC_BIAS_3:
  2173. micb_reg = WCD938X_ANA_MICB3;
  2174. break;
  2175. case MIC_BIAS_4:
  2176. micb_reg = WCD938X_ANA_MICB4;
  2177. break;
  2178. default:
  2179. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2180. return -EINVAL;
  2181. };
  2182. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2183. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2184. wcd938x->pullup_ref[micb_index]);
  2185. mutex_lock(&wcd938x->micb_lock);
  2186. switch (req) {
  2187. case MICB_ENABLE:
  2188. wcd938x->micb_ref[micb_index]++;
  2189. if (wcd938x->micb_ref[micb_index] == 1) {
  2190. regmap_update_bits(wcd938x->regmap,
  2191. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2192. regmap_update_bits(wcd938x->regmap,
  2193. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2194. regmap_update_bits(wcd938x->regmap,
  2195. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2196. regmap_update_bits(wcd938x->regmap,
  2197. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2198. regmap_update_bits(wcd938x->regmap,
  2199. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2200. regmap_update_bits(wcd938x->regmap,
  2201. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2202. regmap_update_bits(wcd938x->regmap,
  2203. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2204. regmap_update_bits(wcd938x->regmap,
  2205. micb_reg, 0xC0, 0x40);
  2206. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2207. }
  2208. break;
  2209. case MICB_PULLUP_ENABLE:
  2210. wcd938x->pullup_ref[micb_index]++;
  2211. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2212. (wcd938x->micb_ref[micb_index] == 0))
  2213. regmap_update_bits(wcd938x->regmap, micb_reg,
  2214. 0xC0, 0x80);
  2215. break;
  2216. case MICB_PULLUP_DISABLE:
  2217. if (wcd938x->pullup_ref[micb_index] > 0)
  2218. wcd938x->pullup_ref[micb_index]--;
  2219. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2220. (wcd938x->micb_ref[micb_index] == 0))
  2221. regmap_update_bits(wcd938x->regmap, micb_reg,
  2222. 0xC0, 0x00);
  2223. break;
  2224. case MICB_DISABLE:
  2225. if (wcd938x->micb_ref[micb_index] > 0)
  2226. wcd938x->micb_ref[micb_index]--;
  2227. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2228. (wcd938x->pullup_ref[micb_index] > 0))
  2229. regmap_update_bits(wcd938x->regmap, micb_reg,
  2230. 0xC0, 0x80);
  2231. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2232. (wcd938x->pullup_ref[micb_index] == 0))
  2233. regmap_update_bits(wcd938x->regmap, micb_reg,
  2234. 0xC0, 0x00);
  2235. break;
  2236. };
  2237. mutex_unlock(&wcd938x->micb_lock);
  2238. return 0;
  2239. }
  2240. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2241. int event, int micb_num)
  2242. {
  2243. struct wcd938x_priv *wcd938x_priv = NULL;
  2244. int ret = 0;
  2245. int micb_index = micb_num - 1;
  2246. if(NULL == component) {
  2247. pr_err("%s: wcd938x component is NULL\n", __func__);
  2248. return -EINVAL;
  2249. }
  2250. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2251. pr_err("%s: invalid event: %d\n", __func__, event);
  2252. return -EINVAL;
  2253. }
  2254. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2255. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2256. return -EINVAL;
  2257. }
  2258. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2259. if (!wcd938x_priv->dev_up) {
  2260. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2261. (event == SND_SOC_DAPM_POST_PMD)) {
  2262. wcd938x_priv->pullup_ref[micb_index]--;
  2263. ret = -ENODEV;
  2264. goto done;
  2265. }
  2266. }
  2267. switch (event) {
  2268. case SND_SOC_DAPM_PRE_PMU:
  2269. wcd938x_wakeup(wcd938x_priv, true);
  2270. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2271. wcd938x_wakeup(wcd938x_priv, false);
  2272. break;
  2273. case SND_SOC_DAPM_POST_PMD:
  2274. wcd938x_wakeup(wcd938x_priv, true);
  2275. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2276. wcd938x_wakeup(wcd938x_priv, false);
  2277. break;
  2278. }
  2279. done:
  2280. return ret;
  2281. }
  2282. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2283. static inline int wcd938x_tx_path_get(const char *wname,
  2284. unsigned int *path_num)
  2285. {
  2286. int ret = 0;
  2287. char *widget_name = NULL;
  2288. char *w_name = NULL;
  2289. char *path_num_char = NULL;
  2290. char *path_name = NULL;
  2291. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2292. if (!widget_name)
  2293. return -EINVAL;
  2294. w_name = widget_name;
  2295. path_name = strsep(&widget_name, " ");
  2296. if (!path_name) {
  2297. pr_err("%s: Invalid widget name = %s\n",
  2298. __func__, widget_name);
  2299. ret = -EINVAL;
  2300. goto err;
  2301. }
  2302. path_num_char = strpbrk(path_name, "0123");
  2303. if (!path_num_char) {
  2304. pr_err("%s: tx path index not found\n",
  2305. __func__);
  2306. ret = -EINVAL;
  2307. goto err;
  2308. }
  2309. ret = kstrtouint(path_num_char, 10, path_num);
  2310. if (ret < 0)
  2311. pr_err("%s: Invalid tx path = %s\n",
  2312. __func__, w_name);
  2313. err:
  2314. kfree(w_name);
  2315. return ret;
  2316. }
  2317. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2318. struct snd_ctl_elem_value *ucontrol)
  2319. {
  2320. struct snd_soc_component *component =
  2321. snd_soc_kcontrol_component(kcontrol);
  2322. struct wcd938x_priv *wcd938x = NULL;
  2323. int ret = 0;
  2324. unsigned int path = 0;
  2325. if (!component)
  2326. return -EINVAL;
  2327. wcd938x = snd_soc_component_get_drvdata(component);
  2328. if (!wcd938x)
  2329. return -EINVAL;
  2330. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2331. if (ret < 0)
  2332. return ret;
  2333. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2334. return 0;
  2335. }
  2336. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2337. struct snd_ctl_elem_value *ucontrol)
  2338. {
  2339. struct snd_soc_component *component =
  2340. snd_soc_kcontrol_component(kcontrol);
  2341. struct wcd938x_priv *wcd938x = NULL;
  2342. u32 mode_val;
  2343. unsigned int path = 0;
  2344. int ret = 0;
  2345. if (!component)
  2346. return -EINVAL;
  2347. wcd938x = snd_soc_component_get_drvdata(component);
  2348. if (!wcd938x)
  2349. return -EINVAL;
  2350. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2351. if (ret)
  2352. return ret;
  2353. mode_val = ucontrol->value.enumerated.item[0];
  2354. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2355. wcd938x->tx_mode[path] = mode_val;
  2356. return 0;
  2357. }
  2358. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2359. struct snd_ctl_elem_value *ucontrol)
  2360. {
  2361. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2362. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2363. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2364. return 0;
  2365. }
  2366. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2367. struct snd_ctl_elem_value *ucontrol)
  2368. {
  2369. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2370. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2371. u32 mode_val;
  2372. mode_val = ucontrol->value.enumerated.item[0];
  2373. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2374. if (wcd938x->variant == WCD9380) {
  2375. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2376. dev_info(component->dev,
  2377. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2378. __func__);
  2379. mode_val = CLS_H_ULP;
  2380. }
  2381. }
  2382. if (mode_val == CLS_H_NORMAL) {
  2383. dev_info(component->dev,
  2384. "%s:Invalid HPH Mode, default to class_AB\n",
  2385. __func__);
  2386. mode_val = CLS_H_ULP;
  2387. }
  2388. wcd938x->hph_mode = mode_val;
  2389. return 0;
  2390. }
  2391. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2392. struct snd_ctl_elem_value *ucontrol)
  2393. {
  2394. u8 ear_pa_gain = 0;
  2395. struct snd_soc_component *component =
  2396. snd_soc_kcontrol_component(kcontrol);
  2397. ear_pa_gain = snd_soc_component_read32(component,
  2398. WCD938X_ANA_EAR_COMPANDER_CTL);
  2399. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2400. ucontrol->value.integer.value[0] = ear_pa_gain;
  2401. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2402. ear_pa_gain);
  2403. return 0;
  2404. }
  2405. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2406. struct snd_ctl_elem_value *ucontrol)
  2407. {
  2408. u8 ear_pa_gain = 0;
  2409. struct snd_soc_component *component =
  2410. snd_soc_kcontrol_component(kcontrol);
  2411. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2412. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2413. __func__, ucontrol->value.integer.value[0]);
  2414. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2415. if (!wcd938x->comp1_enable) {
  2416. snd_soc_component_update_bits(component,
  2417. WCD938X_ANA_EAR_COMPANDER_CTL,
  2418. 0x7C, ear_pa_gain);
  2419. }
  2420. return 0;
  2421. }
  2422. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2423. struct snd_ctl_elem_value *ucontrol)
  2424. {
  2425. struct snd_soc_component *component =
  2426. snd_soc_kcontrol_component(kcontrol);
  2427. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2428. bool hphr;
  2429. struct soc_multi_mixer_control *mc;
  2430. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2431. hphr = mc->shift;
  2432. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2433. wcd938x->comp1_enable;
  2434. return 0;
  2435. }
  2436. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2437. struct snd_ctl_elem_value *ucontrol)
  2438. {
  2439. struct snd_soc_component *component =
  2440. snd_soc_kcontrol_component(kcontrol);
  2441. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2442. int value = ucontrol->value.integer.value[0];
  2443. bool hphr;
  2444. struct soc_multi_mixer_control *mc;
  2445. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2446. hphr = mc->shift;
  2447. if (hphr)
  2448. wcd938x->comp2_enable = value;
  2449. else
  2450. wcd938x->comp1_enable = value;
  2451. return 0;
  2452. }
  2453. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2454. struct snd_kcontrol *kcontrol,
  2455. int event)
  2456. {
  2457. struct snd_soc_component *component =
  2458. snd_soc_dapm_to_component(w->dapm);
  2459. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2460. struct wcd938x_pdata *pdata = NULL;
  2461. int ret = 0;
  2462. pdata = dev_get_platdata(wcd938x->dev);
  2463. if (!pdata) {
  2464. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2465. return -EINVAL;
  2466. }
  2467. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2468. wcd938x->supplies,
  2469. pdata->regulator,
  2470. pdata->num_supplies,
  2471. "cdc-vdd-buck"))
  2472. return 0;
  2473. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2474. w->name, event);
  2475. switch (event) {
  2476. case SND_SOC_DAPM_PRE_PMU:
  2477. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2478. dev_dbg(component->dev,
  2479. "%s: buck already in enabled state\n",
  2480. __func__);
  2481. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2482. return 0;
  2483. }
  2484. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2485. wcd938x->supplies,
  2486. pdata->regulator,
  2487. pdata->num_supplies,
  2488. "cdc-vdd-buck");
  2489. if (ret == -EINVAL) {
  2490. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2491. __func__);
  2492. return ret;
  2493. }
  2494. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2495. /*
  2496. * 200us sleep is required after LDO is enabled as per
  2497. * HW requirement
  2498. */
  2499. usleep_range(200, 250);
  2500. break;
  2501. case SND_SOC_DAPM_POST_PMD:
  2502. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2503. break;
  2504. }
  2505. return 0;
  2506. }
  2507. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2508. struct snd_ctl_elem_value *ucontrol)
  2509. {
  2510. struct snd_soc_component *component =
  2511. snd_soc_kcontrol_component(kcontrol);
  2512. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2513. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2514. return 0;
  2515. }
  2516. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. struct snd_soc_component *component =
  2520. snd_soc_kcontrol_component(kcontrol);
  2521. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2522. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2523. return 0;
  2524. }
  2525. const char * const tx_master_ch_text[] = {
  2526. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2527. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2528. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2529. "SWRM_PCM_IN",
  2530. };
  2531. const struct soc_enum tx_master_ch_enum =
  2532. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2533. tx_master_ch_text);
  2534. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2535. {
  2536. u8 ch_type = 0;
  2537. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2538. ch_type = ADC1;
  2539. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2540. ch_type = ADC2;
  2541. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2542. ch_type = ADC3;
  2543. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2544. ch_type = ADC4;
  2545. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2546. ch_type = DMIC0;
  2547. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2548. ch_type = DMIC1;
  2549. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2550. ch_type = MBHC;
  2551. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2552. ch_type = DMIC2;
  2553. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2554. ch_type = DMIC3;
  2555. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2556. ch_type = DMIC4;
  2557. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2558. ch_type = DMIC5;
  2559. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2560. ch_type = DMIC6;
  2561. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2562. ch_type = DMIC7;
  2563. else
  2564. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2565. if (ch_type)
  2566. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2567. else
  2568. *ch_idx = -EINVAL;
  2569. }
  2570. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2571. struct snd_ctl_elem_value *ucontrol)
  2572. {
  2573. struct snd_soc_component *component =
  2574. snd_soc_kcontrol_component(kcontrol);
  2575. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2576. int slave_ch_idx;
  2577. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2578. if (slave_ch_idx != -EINVAL)
  2579. ucontrol->value.integer.value[0] =
  2580. wcd938x_slave_get_master_ch_val(
  2581. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2582. return 0;
  2583. }
  2584. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2585. struct snd_ctl_elem_value *ucontrol)
  2586. {
  2587. struct snd_soc_component *component =
  2588. snd_soc_kcontrol_component(kcontrol);
  2589. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2590. int slave_ch_idx;
  2591. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2592. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2593. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2594. __func__, ucontrol->value.enumerated.item[0]);
  2595. if (slave_ch_idx != -EINVAL)
  2596. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2597. wcd938x_slave_get_master_ch(
  2598. ucontrol->value.enumerated.item[0]);
  2599. return 0;
  2600. }
  2601. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2602. struct snd_ctl_elem_value *ucontrol)
  2603. {
  2604. struct snd_soc_component *component =
  2605. snd_soc_kcontrol_component(kcontrol);
  2606. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2607. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2608. return 0;
  2609. }
  2610. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2611. struct snd_ctl_elem_value *ucontrol)
  2612. {
  2613. struct snd_soc_component *component =
  2614. snd_soc_kcontrol_component(kcontrol);
  2615. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2616. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2617. return 0;
  2618. }
  2619. static const char * const tx_mode_mux_text_wcd9380[] = {
  2620. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2621. };
  2622. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2623. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2624. tx_mode_mux_text_wcd9380);
  2625. static const char * const tx_mode_mux_text[] = {
  2626. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2627. "ADC_ULP1", "ADC_ULP2",
  2628. };
  2629. static const struct soc_enum tx_mode_mux_enum =
  2630. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2631. tx_mode_mux_text);
  2632. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2633. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2634. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2635. "CLS_AB_LOHIFI",
  2636. };
  2637. static const char * const wcd938x_ear_pa_gain_text[] = {
  2638. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2639. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2640. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2641. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2642. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2643. };
  2644. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2645. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2646. rx_hph_mode_mux_text_wcd9380);
  2647. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2648. wcd938x_ear_pa_gain_text);
  2649. static const char * const rx_hph_mode_mux_text[] = {
  2650. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2651. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2652. };
  2653. static const struct soc_enum rx_hph_mode_mux_enum =
  2654. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2655. rx_hph_mode_mux_text);
  2656. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2657. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2658. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2659. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2660. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2661. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2662. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2663. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2664. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2665. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2666. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2667. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2668. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2669. };
  2670. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2671. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2672. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2673. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2674. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2675. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2676. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2677. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2678. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2679. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2680. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2681. };
  2682. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2683. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2684. wcd938x_get_compander, wcd938x_set_compander),
  2685. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2686. wcd938x_get_compander, wcd938x_set_compander),
  2687. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2688. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2689. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2690. wcd938x_bcs_get, wcd938x_bcs_put),
  2691. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2692. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2693. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2694. analog_gain),
  2695. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2696. analog_gain),
  2697. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2698. analog_gain),
  2699. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2700. analog_gain),
  2701. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2702. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2703. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2704. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2705. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2706. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2707. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2708. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2709. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2710. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2711. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2712. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2713. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2714. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2715. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2716. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2717. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2718. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2719. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2720. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2721. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2722. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2723. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2724. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2725. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2726. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2727. };
  2728. static const struct snd_kcontrol_new adc1_switch[] = {
  2729. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2730. };
  2731. static const struct snd_kcontrol_new adc2_switch[] = {
  2732. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2733. };
  2734. static const struct snd_kcontrol_new adc3_switch[] = {
  2735. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2736. };
  2737. static const struct snd_kcontrol_new adc4_switch[] = {
  2738. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2739. };
  2740. static const struct snd_kcontrol_new dmic1_switch[] = {
  2741. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2742. };
  2743. static const struct snd_kcontrol_new dmic2_switch[] = {
  2744. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2745. };
  2746. static const struct snd_kcontrol_new dmic3_switch[] = {
  2747. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2748. };
  2749. static const struct snd_kcontrol_new dmic4_switch[] = {
  2750. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2751. };
  2752. static const struct snd_kcontrol_new dmic5_switch[] = {
  2753. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2754. };
  2755. static const struct snd_kcontrol_new dmic6_switch[] = {
  2756. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2757. };
  2758. static const struct snd_kcontrol_new dmic7_switch[] = {
  2759. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2760. };
  2761. static const struct snd_kcontrol_new dmic8_switch[] = {
  2762. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2763. };
  2764. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2765. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2766. };
  2767. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2768. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2769. };
  2770. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2771. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2772. };
  2773. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2774. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2775. };
  2776. static const char * const adc2_mux_text[] = {
  2777. "INP2", "INP3"
  2778. };
  2779. static const struct soc_enum adc2_enum =
  2780. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2781. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2782. static const struct snd_kcontrol_new tx_adc2_mux =
  2783. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2784. static const char * const adc3_mux_text[] = {
  2785. "INP4", "INP6"
  2786. };
  2787. static const struct soc_enum adc3_enum =
  2788. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2789. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2790. static const struct snd_kcontrol_new tx_adc3_mux =
  2791. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2792. static const char * const adc4_mux_text[] = {
  2793. "INP5", "INP7"
  2794. };
  2795. static const struct soc_enum adc4_enum =
  2796. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2797. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2798. static const struct snd_kcontrol_new tx_adc4_mux =
  2799. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2800. static const char * const rdac3_mux_text[] = {
  2801. "RX1", "RX3"
  2802. };
  2803. static const char * const hdr12_mux_text[] = {
  2804. "NO_HDR12", "HDR12"
  2805. };
  2806. static const struct soc_enum hdr12_enum =
  2807. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2808. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2809. static const struct snd_kcontrol_new tx_hdr12_mux =
  2810. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2811. static const char * const hdr34_mux_text[] = {
  2812. "NO_HDR34", "HDR34"
  2813. };
  2814. static const struct soc_enum hdr34_enum =
  2815. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2816. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2817. static const struct snd_kcontrol_new tx_hdr34_mux =
  2818. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2819. static const struct soc_enum rdac3_enum =
  2820. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2821. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2822. static const struct snd_kcontrol_new rx_rdac3_mux =
  2823. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2824. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2825. /*input widgets*/
  2826. SND_SOC_DAPM_INPUT("AMIC1"),
  2827. SND_SOC_DAPM_INPUT("AMIC2"),
  2828. SND_SOC_DAPM_INPUT("AMIC3"),
  2829. SND_SOC_DAPM_INPUT("AMIC4"),
  2830. SND_SOC_DAPM_INPUT("AMIC5"),
  2831. SND_SOC_DAPM_INPUT("AMIC6"),
  2832. SND_SOC_DAPM_INPUT("AMIC7"),
  2833. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2834. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2835. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2836. /*
  2837. * These dummy widgets are null connected to WCD938x dapm input and
  2838. * output widgets which are not actual path endpoints. This ensures
  2839. * dapm doesnt set these dapm input and output widgets as endpoints.
  2840. */
  2841. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2842. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2843. /*tx widgets*/
  2844. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2845. wcd938x_codec_enable_adc,
  2846. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2847. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2848. wcd938x_codec_enable_adc,
  2849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2850. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2851. wcd938x_codec_enable_adc,
  2852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2853. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2854. wcd938x_codec_enable_adc,
  2855. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2856. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2857. wcd938x_codec_enable_dmic,
  2858. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2859. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2860. wcd938x_codec_enable_dmic,
  2861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2862. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2863. wcd938x_codec_enable_dmic,
  2864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2865. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2866. wcd938x_codec_enable_dmic,
  2867. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2868. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2869. wcd938x_codec_enable_dmic,
  2870. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2871. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2872. wcd938x_codec_enable_dmic,
  2873. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2874. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2875. wcd938x_codec_enable_dmic,
  2876. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2877. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2878. wcd938x_codec_enable_dmic,
  2879. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2880. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2881. NULL, 0, wcd938x_enable_req,
  2882. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2883. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2884. NULL, 0, wcd938x_enable_req,
  2885. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2886. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2887. NULL, 0, wcd938x_enable_req,
  2888. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2889. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2890. NULL, 0, wcd938x_enable_req,
  2891. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2892. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2893. &tx_adc2_mux),
  2894. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2895. &tx_adc3_mux),
  2896. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2897. &tx_adc4_mux),
  2898. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2899. &tx_hdr12_mux),
  2900. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2901. &tx_hdr34_mux),
  2902. /*tx mixers*/
  2903. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  2904. adc1_switch, ARRAY_SIZE(adc1_switch),
  2905. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2906. SND_SOC_DAPM_POST_PMD),
  2907. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  2908. adc2_switch, ARRAY_SIZE(adc2_switch),
  2909. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2910. SND_SOC_DAPM_POST_PMD),
  2911. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  2912. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2913. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2914. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  2915. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2916. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2917. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2918. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2919. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2920. SND_SOC_DAPM_POST_PMD),
  2921. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2922. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2923. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2924. SND_SOC_DAPM_POST_PMD),
  2925. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2926. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2927. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2928. SND_SOC_DAPM_POST_PMD),
  2929. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2930. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2931. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2932. SND_SOC_DAPM_POST_PMD),
  2933. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2934. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2935. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2936. SND_SOC_DAPM_POST_PMD),
  2937. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2938. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2939. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2940. SND_SOC_DAPM_POST_PMD),
  2941. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  2942. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2943. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2944. SND_SOC_DAPM_POST_PMD),
  2945. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  2946. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2947. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2948. SND_SOC_DAPM_POST_PMD),
  2949. /* micbias widgets*/
  2950. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2951. wcd938x_codec_enable_micbias,
  2952. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2953. SND_SOC_DAPM_POST_PMD),
  2954. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2955. wcd938x_codec_enable_micbias,
  2956. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2957. SND_SOC_DAPM_POST_PMD),
  2958. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2959. wcd938x_codec_enable_micbias,
  2960. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2961. SND_SOC_DAPM_POST_PMD),
  2962. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2963. wcd938x_codec_enable_micbias,
  2964. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2965. SND_SOC_DAPM_POST_PMD),
  2966. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2967. wcd938x_codec_force_enable_micbias,
  2968. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2969. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2970. wcd938x_codec_force_enable_micbias,
  2971. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2972. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2973. wcd938x_codec_force_enable_micbias,
  2974. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2975. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2976. wcd938x_codec_force_enable_micbias,
  2977. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2978. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2979. wcd938x_codec_enable_vdd_buck,
  2980. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2981. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2982. wcd938x_enable_clsh,
  2983. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2984. /*rx widgets*/
  2985. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2986. wcd938x_codec_enable_ear_pa,
  2987. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2988. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2989. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2990. wcd938x_codec_enable_aux_pa,
  2991. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2992. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2993. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2994. wcd938x_codec_enable_hphl_pa,
  2995. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2996. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2997. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2998. wcd938x_codec_enable_hphr_pa,
  2999. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3000. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3001. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3002. wcd938x_codec_hphl_dac_event,
  3003. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3004. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3005. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3006. wcd938x_codec_hphr_dac_event,
  3007. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3008. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3009. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3010. wcd938x_codec_ear_dac_event,
  3011. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3012. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3013. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3014. wcd938x_codec_aux_dac_event,
  3015. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3016. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3017. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3018. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3019. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3020. SND_SOC_DAPM_POST_PMD),
  3021. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3022. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3023. SND_SOC_DAPM_POST_PMD),
  3024. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3025. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3026. SND_SOC_DAPM_POST_PMD),
  3027. /* rx mixer widgets*/
  3028. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3029. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3030. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3031. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3032. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3033. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3034. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3035. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3036. /*output widgets tx*/
  3037. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3038. /*output widgets rx*/
  3039. SND_SOC_DAPM_OUTPUT("EAR"),
  3040. SND_SOC_DAPM_OUTPUT("AUX"),
  3041. SND_SOC_DAPM_OUTPUT("HPHL"),
  3042. SND_SOC_DAPM_OUTPUT("HPHR"),
  3043. /* micbias pull up widgets*/
  3044. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3045. wcd938x_codec_enable_micbias_pullup,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3047. SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3049. wcd938x_codec_enable_micbias_pullup,
  3050. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3051. SND_SOC_DAPM_POST_PMD),
  3052. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3053. wcd938x_codec_enable_micbias_pullup,
  3054. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3055. SND_SOC_DAPM_POST_PMD),
  3056. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3057. wcd938x_codec_enable_micbias_pullup,
  3058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3059. SND_SOC_DAPM_POST_PMD),
  3060. };
  3061. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3062. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3063. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3064. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3065. {"ADC1 REQ", NULL, "ADC1"},
  3066. {"ADC1", NULL, "AMIC1"},
  3067. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3068. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3069. {"ADC2 REQ", NULL, "ADC2"},
  3070. {"ADC2", NULL, "HDR12 MUX"},
  3071. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3072. {"HDR12 MUX", "HDR12", "AMIC1"},
  3073. {"ADC2 MUX", "INP3", "AMIC3"},
  3074. {"ADC2 MUX", "INP2", "AMIC2"},
  3075. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3076. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3077. {"ADC3 REQ", NULL, "ADC3"},
  3078. {"ADC3", NULL, "HDR34 MUX"},
  3079. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3080. {"HDR34 MUX", "HDR34", "AMIC5"},
  3081. {"ADC3 MUX", "INP4", "AMIC4"},
  3082. {"ADC3 MUX", "INP6", "AMIC6"},
  3083. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3084. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3085. {"ADC4 REQ", NULL, "ADC4"},
  3086. {"ADC4", NULL, "ADC4 MUX"},
  3087. {"ADC4 MUX", "INP5", "AMIC5"},
  3088. {"ADC4 MUX", "INP7", "AMIC7"},
  3089. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3090. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3091. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3092. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3093. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3094. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3095. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3096. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3097. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3098. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3099. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3100. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3101. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3102. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3103. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3104. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3105. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3106. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3107. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3108. {"RX1", NULL, "IN1_HPHL"},
  3109. {"RDAC1", NULL, "RX1"},
  3110. {"HPHL_RDAC", "Switch", "RDAC1"},
  3111. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3112. {"HPHL", NULL, "HPHL PGA"},
  3113. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3114. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3115. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3116. {"RX2", NULL, "IN2_HPHR"},
  3117. {"RDAC2", NULL, "RX2"},
  3118. {"HPHR_RDAC", "Switch", "RDAC2"},
  3119. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3120. {"HPHR", NULL, "HPHR PGA"},
  3121. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3122. {"IN3_AUX", NULL, "VDD_BUCK"},
  3123. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3124. {"RX3", NULL, "IN3_AUX"},
  3125. {"RDAC4", NULL, "RX3"},
  3126. {"AUX_RDAC", "Switch", "RDAC4"},
  3127. {"AUX PGA", NULL, "AUX_RDAC"},
  3128. {"AUX", NULL, "AUX PGA"},
  3129. {"RDAC3_MUX", "RX3", "RX3"},
  3130. {"RDAC3_MUX", "RX1", "RX1"},
  3131. {"RDAC3", NULL, "RDAC3_MUX"},
  3132. {"EAR_RDAC", "Switch", "RDAC3"},
  3133. {"EAR PGA", NULL, "EAR_RDAC"},
  3134. {"EAR", NULL, "EAR PGA"},
  3135. };
  3136. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3137. void *file_private_data,
  3138. struct file *file,
  3139. char __user *buf, size_t count,
  3140. loff_t pos)
  3141. {
  3142. struct wcd938x_priv *priv;
  3143. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3144. int len = 0;
  3145. priv = (struct wcd938x_priv *) entry->private_data;
  3146. if (!priv) {
  3147. pr_err("%s: wcd938x priv is null\n", __func__);
  3148. return -EINVAL;
  3149. }
  3150. switch (priv->version) {
  3151. case WCD938X_VERSION_1_0:
  3152. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3153. break;
  3154. default:
  3155. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3156. }
  3157. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3158. }
  3159. static struct snd_info_entry_ops wcd938x_info_ops = {
  3160. .read = wcd938x_version_read,
  3161. };
  3162. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3163. void *file_private_data,
  3164. struct file *file,
  3165. char __user *buf, size_t count,
  3166. loff_t pos)
  3167. {
  3168. struct wcd938x_priv *priv;
  3169. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3170. int len = 0;
  3171. priv = (struct wcd938x_priv *) entry->private_data;
  3172. if (!priv) {
  3173. pr_err("%s: wcd938x priv is null\n", __func__);
  3174. return -EINVAL;
  3175. }
  3176. switch (priv->variant) {
  3177. case WCD9380:
  3178. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3179. break;
  3180. case WCD9385:
  3181. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3182. break;
  3183. default:
  3184. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3185. }
  3186. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3187. }
  3188. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3189. .read = wcd938x_variant_read,
  3190. };
  3191. /*
  3192. * wcd938x_get_codec_variant
  3193. * @component: component instance
  3194. *
  3195. * Return: codec variant or -EINVAL in error.
  3196. */
  3197. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3198. {
  3199. struct wcd938x_priv *priv = NULL;
  3200. if (!component)
  3201. return -EINVAL;
  3202. priv = snd_soc_component_get_drvdata(component);
  3203. if (!priv) {
  3204. dev_err(component->dev,
  3205. "%s:wcd938x not probed\n", __func__);
  3206. return 0;
  3207. }
  3208. return priv->variant;
  3209. }
  3210. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3211. /*
  3212. * wcd938x_info_create_codec_entry - creates wcd938x module
  3213. * @codec_root: The parent directory
  3214. * @component: component instance
  3215. *
  3216. * Creates wcd938x module, variant and version entry under the given
  3217. * parent directory.
  3218. *
  3219. * Return: 0 on success or negative error code on failure.
  3220. */
  3221. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3222. struct snd_soc_component *component)
  3223. {
  3224. struct snd_info_entry *version_entry;
  3225. struct snd_info_entry *variant_entry;
  3226. struct wcd938x_priv *priv;
  3227. struct snd_soc_card *card;
  3228. if (!codec_root || !component)
  3229. return -EINVAL;
  3230. priv = snd_soc_component_get_drvdata(component);
  3231. if (priv->entry) {
  3232. dev_dbg(priv->dev,
  3233. "%s:wcd938x module already created\n", __func__);
  3234. return 0;
  3235. }
  3236. card = component->card;
  3237. priv->entry = snd_info_create_module_entry(codec_root->module,
  3238. "wcd938x", codec_root);
  3239. if (!priv->entry) {
  3240. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3241. __func__);
  3242. return -ENOMEM;
  3243. }
  3244. priv->entry->mode = S_IFDIR | 0555;
  3245. if (snd_info_register(priv->entry) < 0) {
  3246. snd_info_free_entry(priv->entry);
  3247. return -ENOMEM;
  3248. }
  3249. version_entry = snd_info_create_card_entry(card->snd_card,
  3250. "version",
  3251. priv->entry);
  3252. if (!version_entry) {
  3253. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3254. __func__);
  3255. snd_info_free_entry(priv->entry);
  3256. return -ENOMEM;
  3257. }
  3258. version_entry->private_data = priv;
  3259. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3260. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3261. version_entry->c.ops = &wcd938x_info_ops;
  3262. if (snd_info_register(version_entry) < 0) {
  3263. snd_info_free_entry(version_entry);
  3264. snd_info_free_entry(priv->entry);
  3265. return -ENOMEM;
  3266. }
  3267. priv->version_entry = version_entry;
  3268. variant_entry = snd_info_create_card_entry(card->snd_card,
  3269. "variant",
  3270. priv->entry);
  3271. if (!variant_entry) {
  3272. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3273. __func__);
  3274. snd_info_free_entry(version_entry);
  3275. snd_info_free_entry(priv->entry);
  3276. return -ENOMEM;
  3277. }
  3278. variant_entry->private_data = priv;
  3279. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3280. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3281. variant_entry->c.ops = &wcd938x_variant_ops;
  3282. if (snd_info_register(variant_entry) < 0) {
  3283. snd_info_free_entry(variant_entry);
  3284. snd_info_free_entry(version_entry);
  3285. snd_info_free_entry(priv->entry);
  3286. return -ENOMEM;
  3287. }
  3288. priv->variant_entry = variant_entry;
  3289. return 0;
  3290. }
  3291. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3292. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3293. struct wcd938x_pdata *pdata)
  3294. {
  3295. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3296. int rc = 0;
  3297. if (!pdata) {
  3298. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3299. return -ENODEV;
  3300. }
  3301. /* set micbias voltage */
  3302. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3303. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3304. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3305. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3306. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3307. vout_ctl_4 < 0) {
  3308. rc = -EINVAL;
  3309. goto done;
  3310. }
  3311. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3312. vout_ctl_1);
  3313. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3314. vout_ctl_2);
  3315. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3316. vout_ctl_3);
  3317. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3318. vout_ctl_4);
  3319. done:
  3320. return rc;
  3321. }
  3322. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3323. {
  3324. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3325. struct snd_soc_dapm_context *dapm =
  3326. snd_soc_component_get_dapm(component);
  3327. int variant;
  3328. int ret = -EINVAL;
  3329. dev_info(component->dev, "%s()\n", __func__);
  3330. wcd938x = snd_soc_component_get_drvdata(component);
  3331. if (!wcd938x)
  3332. return -EINVAL;
  3333. wcd938x->component = component;
  3334. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3335. variant = (snd_soc_component_read32(component,
  3336. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3337. wcd938x->variant = variant;
  3338. wcd938x->fw_data = devm_kzalloc(component->dev,
  3339. sizeof(*(wcd938x->fw_data)),
  3340. GFP_KERNEL);
  3341. if (!wcd938x->fw_data) {
  3342. dev_err(component->dev, "Failed to allocate fw_data\n");
  3343. ret = -ENOMEM;
  3344. goto err;
  3345. }
  3346. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3347. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3348. WCD9XXX_CODEC_HWDEP_NODE, component);
  3349. if (ret < 0) {
  3350. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3351. goto err_hwdep;
  3352. }
  3353. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3354. if (ret) {
  3355. pr_err("%s: mbhc initialization failed\n", __func__);
  3356. goto err_hwdep;
  3357. }
  3358. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3359. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3360. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3361. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3362. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3363. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3364. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3365. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3366. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3367. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3368. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3369. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3370. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3371. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3372. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3373. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3374. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3375. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3376. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3377. snd_soc_dapm_sync(dapm);
  3378. wcd_cls_h_init(&wcd938x->clsh_info);
  3379. wcd938x_init_reg(component);
  3380. if (wcd938x->variant == WCD9380) {
  3381. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3382. ARRAY_SIZE(wcd9380_snd_controls));
  3383. if (ret < 0) {
  3384. dev_err(component->dev,
  3385. "%s: Failed to add snd ctrls for variant: %d\n",
  3386. __func__, wcd938x->variant);
  3387. goto err_hwdep;
  3388. }
  3389. }
  3390. if (wcd938x->variant == WCD9385) {
  3391. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3392. ARRAY_SIZE(wcd9385_snd_controls));
  3393. if (ret < 0) {
  3394. dev_err(component->dev,
  3395. "%s: Failed to add snd ctrls for variant: %d\n",
  3396. __func__, wcd938x->variant);
  3397. goto err_hwdep;
  3398. }
  3399. }
  3400. wcd938x->version = WCD938X_VERSION_1_0;
  3401. /* Register event notifier */
  3402. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3403. if (wcd938x->register_notifier) {
  3404. ret = wcd938x->register_notifier(wcd938x->handle,
  3405. &wcd938x->nblock,
  3406. true);
  3407. if (ret) {
  3408. dev_err(component->dev,
  3409. "%s: Failed to register notifier %d\n",
  3410. __func__, ret);
  3411. return ret;
  3412. }
  3413. }
  3414. return ret;
  3415. err_hwdep:
  3416. wcd938x->fw_data = NULL;
  3417. err:
  3418. return ret;
  3419. }
  3420. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3421. {
  3422. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3423. if (!wcd938x) {
  3424. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3425. __func__);
  3426. return;
  3427. }
  3428. if (wcd938x->register_notifier)
  3429. wcd938x->register_notifier(wcd938x->handle,
  3430. &wcd938x->nblock,
  3431. false);
  3432. }
  3433. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3434. {
  3435. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3436. if (!wcd938x)
  3437. return 0;
  3438. wcd938x->dapm_bias_off = true;
  3439. return 0;
  3440. }
  3441. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3442. {
  3443. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3444. if (!wcd938x)
  3445. return 0;
  3446. wcd938x->dapm_bias_off = false;
  3447. return 0;
  3448. }
  3449. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3450. .name = WCD938X_DRV_NAME,
  3451. .probe = wcd938x_soc_codec_probe,
  3452. .remove = wcd938x_soc_codec_remove,
  3453. .controls = wcd938x_snd_controls,
  3454. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3455. .dapm_widgets = wcd938x_dapm_widgets,
  3456. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3457. .dapm_routes = wcd938x_audio_map,
  3458. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3459. .suspend = wcd938x_soc_codec_suspend,
  3460. .resume = wcd938x_soc_codec_resume,
  3461. };
  3462. static int wcd938x_reset(struct device *dev)
  3463. {
  3464. struct wcd938x_priv *wcd938x = NULL;
  3465. int rc = 0;
  3466. int value = 0;
  3467. if (!dev)
  3468. return -ENODEV;
  3469. wcd938x = dev_get_drvdata(dev);
  3470. if (!wcd938x)
  3471. return -EINVAL;
  3472. if (!wcd938x->rst_np) {
  3473. dev_err(dev, "%s: reset gpio device node not specified\n",
  3474. __func__);
  3475. return -EINVAL;
  3476. }
  3477. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3478. if (value > 0)
  3479. return 0;
  3480. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3481. if (rc) {
  3482. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3483. __func__);
  3484. return rc;
  3485. }
  3486. /* 20us sleep required after pulling the reset gpio to LOW */
  3487. usleep_range(20, 30);
  3488. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3489. if (rc) {
  3490. dev_err(dev, "%s: wcd active state request fail!\n",
  3491. __func__);
  3492. return rc;
  3493. }
  3494. /* 20us sleep required after pulling the reset gpio to HIGH */
  3495. usleep_range(20, 30);
  3496. return rc;
  3497. }
  3498. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3499. u32 *val)
  3500. {
  3501. int rc = 0;
  3502. rc = of_property_read_u32(dev->of_node, name, val);
  3503. if (rc)
  3504. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3505. __func__, name, dev->of_node->full_name);
  3506. return rc;
  3507. }
  3508. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3509. struct wcd938x_micbias_setting *mb)
  3510. {
  3511. u32 prop_val = 0;
  3512. int rc = 0;
  3513. /* MB1 */
  3514. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3515. NULL)) {
  3516. rc = wcd938x_read_of_property_u32(dev,
  3517. "qcom,cdc-micbias1-mv",
  3518. &prop_val);
  3519. if (!rc)
  3520. mb->micb1_mv = prop_val;
  3521. } else {
  3522. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3523. __func__);
  3524. }
  3525. /* MB2 */
  3526. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3527. NULL)) {
  3528. rc = wcd938x_read_of_property_u32(dev,
  3529. "qcom,cdc-micbias2-mv",
  3530. &prop_val);
  3531. if (!rc)
  3532. mb->micb2_mv = prop_val;
  3533. } else {
  3534. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3535. __func__);
  3536. }
  3537. /* MB3 */
  3538. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3539. NULL)) {
  3540. rc = wcd938x_read_of_property_u32(dev,
  3541. "qcom,cdc-micbias3-mv",
  3542. &prop_val);
  3543. if (!rc)
  3544. mb->micb3_mv = prop_val;
  3545. } else {
  3546. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3547. __func__);
  3548. }
  3549. /* MB4 */
  3550. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3551. NULL)) {
  3552. rc = wcd938x_read_of_property_u32(dev,
  3553. "qcom,cdc-micbias4-mv",
  3554. &prop_val);
  3555. if (!rc)
  3556. mb->micb4_mv = prop_val;
  3557. } else {
  3558. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3559. __func__);
  3560. }
  3561. }
  3562. static int wcd938x_reset_low(struct device *dev)
  3563. {
  3564. struct wcd938x_priv *wcd938x = NULL;
  3565. int rc = 0;
  3566. if (!dev)
  3567. return -ENODEV;
  3568. wcd938x = dev_get_drvdata(dev);
  3569. if (!wcd938x)
  3570. return -EINVAL;
  3571. if (!wcd938x->rst_np) {
  3572. dev_err(dev, "%s: reset gpio device node not specified\n",
  3573. __func__);
  3574. return -EINVAL;
  3575. }
  3576. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3577. if (rc) {
  3578. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3579. __func__);
  3580. return rc;
  3581. }
  3582. /* 20us sleep required after pulling the reset gpio to LOW */
  3583. usleep_range(20, 30);
  3584. return rc;
  3585. }
  3586. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3587. {
  3588. struct wcd938x_pdata *pdata = NULL;
  3589. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3590. GFP_KERNEL);
  3591. if (!pdata)
  3592. return NULL;
  3593. pdata->rst_np = of_parse_phandle(dev->of_node,
  3594. "qcom,wcd-rst-gpio-node", 0);
  3595. if (!pdata->rst_np) {
  3596. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3597. __func__, "qcom,wcd-rst-gpio-node",
  3598. dev->of_node->full_name);
  3599. return NULL;
  3600. }
  3601. /* Parse power supplies */
  3602. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3603. &pdata->num_supplies);
  3604. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3605. dev_err(dev, "%s: no power supplies defined for codec\n",
  3606. __func__);
  3607. return NULL;
  3608. }
  3609. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3610. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3611. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3612. return pdata;
  3613. }
  3614. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3615. {
  3616. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3617. __func__, irq);
  3618. return IRQ_HANDLED;
  3619. }
  3620. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3621. {
  3622. .name = "wcd938x_cdc",
  3623. .playback = {
  3624. .stream_name = "WCD938X_AIF Playback",
  3625. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3626. .formats = WCD938X_FORMATS,
  3627. .rate_max = 384000,
  3628. .rate_min = 8000,
  3629. .channels_min = 1,
  3630. .channels_max = 4,
  3631. },
  3632. .capture = {
  3633. .stream_name = "WCD938X_AIF Capture",
  3634. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3635. .formats = WCD938X_FORMATS,
  3636. .rate_max = 384000,
  3637. .rate_min = 8000,
  3638. .channels_min = 1,
  3639. .channels_max = 4,
  3640. },
  3641. },
  3642. };
  3643. static int wcd938x_bind(struct device *dev)
  3644. {
  3645. int ret = 0, i = 0;
  3646. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3647. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3648. /*
  3649. * Add 5msec delay to provide sufficient time for
  3650. * soundwire auto enumeration of slave devices as
  3651. * as per HW requirement.
  3652. */
  3653. usleep_range(5000, 5010);
  3654. ret = component_bind_all(dev, wcd938x);
  3655. if (ret) {
  3656. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3657. __func__, ret);
  3658. return ret;
  3659. }
  3660. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3661. if (!wcd938x->rx_swr_dev) {
  3662. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3663. __func__);
  3664. ret = -ENODEV;
  3665. goto err;
  3666. }
  3667. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3668. if (!wcd938x->tx_swr_dev) {
  3669. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3670. __func__);
  3671. ret = -ENODEV;
  3672. goto err;
  3673. }
  3674. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3675. &wcd938x_regmap_config);
  3676. if (!wcd938x->regmap) {
  3677. dev_err(dev, "%s: Regmap init failed\n",
  3678. __func__);
  3679. goto err;
  3680. }
  3681. /* Set all interupts as edge triggered */
  3682. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3683. regmap_write(wcd938x->regmap,
  3684. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3685. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3686. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3687. wcd938x->irq_info.codec_name = "WCD938X";
  3688. wcd938x->irq_info.regmap = wcd938x->regmap;
  3689. wcd938x->irq_info.dev = dev;
  3690. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3691. if (ret) {
  3692. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3693. __func__, ret);
  3694. goto err;
  3695. }
  3696. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3697. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3698. if (ret < 0) {
  3699. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3700. goto err_irq;
  3701. }
  3702. /* Request for watchdog interrupt */
  3703. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3704. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3705. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3706. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3707. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3708. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3709. /* Disable watchdog interrupt for HPH and AUX */
  3710. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3711. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3712. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3713. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3714. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3715. if (ret) {
  3716. dev_err(dev, "%s: Codec registration failed\n",
  3717. __func__);
  3718. goto err_irq;
  3719. }
  3720. wcd938x->dev_up = true;
  3721. return ret;
  3722. err_irq:
  3723. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3724. err:
  3725. component_unbind_all(dev, wcd938x);
  3726. return ret;
  3727. }
  3728. static void wcd938x_unbind(struct device *dev)
  3729. {
  3730. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3731. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3732. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3733. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3734. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3735. snd_soc_unregister_component(dev);
  3736. component_unbind_all(dev, wcd938x);
  3737. }
  3738. static const struct of_device_id wcd938x_dt_match[] = {
  3739. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3740. {}
  3741. };
  3742. static const struct component_master_ops wcd938x_comp_ops = {
  3743. .bind = wcd938x_bind,
  3744. .unbind = wcd938x_unbind,
  3745. };
  3746. static int wcd938x_compare_of(struct device *dev, void *data)
  3747. {
  3748. return dev->of_node == data;
  3749. }
  3750. static void wcd938x_release_of(struct device *dev, void *data)
  3751. {
  3752. of_node_put(data);
  3753. }
  3754. static int wcd938x_add_slave_components(struct device *dev,
  3755. struct component_match **matchptr)
  3756. {
  3757. struct device_node *np, *rx_node, *tx_node;
  3758. np = dev->of_node;
  3759. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3760. if (!rx_node) {
  3761. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3762. return -ENODEV;
  3763. }
  3764. of_node_get(rx_node);
  3765. component_match_add_release(dev, matchptr,
  3766. wcd938x_release_of,
  3767. wcd938x_compare_of,
  3768. rx_node);
  3769. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3770. if (!tx_node) {
  3771. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3772. return -ENODEV;
  3773. }
  3774. of_node_get(tx_node);
  3775. component_match_add_release(dev, matchptr,
  3776. wcd938x_release_of,
  3777. wcd938x_compare_of,
  3778. tx_node);
  3779. return 0;
  3780. }
  3781. static int wcd938x_probe(struct platform_device *pdev)
  3782. {
  3783. struct component_match *match = NULL;
  3784. struct wcd938x_priv *wcd938x = NULL;
  3785. struct wcd938x_pdata *pdata = NULL;
  3786. struct wcd_ctrl_platform_data *plat_data = NULL;
  3787. struct device *dev = &pdev->dev;
  3788. int ret;
  3789. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3790. GFP_KERNEL);
  3791. if (!wcd938x)
  3792. return -ENOMEM;
  3793. dev_set_drvdata(dev, wcd938x);
  3794. wcd938x->dev = dev;
  3795. pdata = wcd938x_populate_dt_data(dev);
  3796. if (!pdata) {
  3797. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3798. return -EINVAL;
  3799. }
  3800. dev->platform_data = pdata;
  3801. wcd938x->rst_np = pdata->rst_np;
  3802. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3803. pdata->regulator, pdata->num_supplies);
  3804. if (!wcd938x->supplies) {
  3805. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3806. __func__);
  3807. return ret;
  3808. }
  3809. plat_data = dev_get_platdata(dev->parent);
  3810. if (!plat_data) {
  3811. dev_err(dev, "%s: platform data from parent is NULL\n",
  3812. __func__);
  3813. return -EINVAL;
  3814. }
  3815. wcd938x->handle = (void *)plat_data->handle;
  3816. if (!wcd938x->handle) {
  3817. dev_err(dev, "%s: handle is NULL\n", __func__);
  3818. return -EINVAL;
  3819. }
  3820. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3821. if (!wcd938x->update_wcd_event) {
  3822. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3823. __func__);
  3824. return -EINVAL;
  3825. }
  3826. wcd938x->register_notifier = plat_data->register_notifier;
  3827. if (!wcd938x->register_notifier) {
  3828. dev_err(dev, "%s: register_notifier api is null!\n",
  3829. __func__);
  3830. return -EINVAL;
  3831. }
  3832. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3833. pdata->regulator,
  3834. pdata->num_supplies);
  3835. if (ret) {
  3836. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3837. __func__);
  3838. return ret;
  3839. }
  3840. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3841. CODEC_RX);
  3842. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3843. CODEC_TX);
  3844. if (ret) {
  3845. dev_err(dev, "Failed to read port mapping\n");
  3846. goto err;
  3847. }
  3848. mutex_init(&wcd938x->wakeup_lock);
  3849. mutex_init(&wcd938x->micb_lock);
  3850. ret = wcd938x_add_slave_components(dev, &match);
  3851. if (ret)
  3852. goto err_lock_init;
  3853. wcd938x_reset(dev);
  3854. wcd938x->wakeup = wcd938x_wakeup;
  3855. return component_master_add_with_match(dev,
  3856. &wcd938x_comp_ops, match);
  3857. err_lock_init:
  3858. mutex_destroy(&wcd938x->micb_lock);
  3859. mutex_destroy(&wcd938x->wakeup_lock);
  3860. err:
  3861. return ret;
  3862. }
  3863. static int wcd938x_remove(struct platform_device *pdev)
  3864. {
  3865. struct wcd938x_priv *wcd938x = NULL;
  3866. wcd938x = platform_get_drvdata(pdev);
  3867. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3868. mutex_destroy(&wcd938x->micb_lock);
  3869. mutex_destroy(&wcd938x->wakeup_lock);
  3870. dev_set_drvdata(&pdev->dev, NULL);
  3871. return 0;
  3872. }
  3873. #ifdef CONFIG_PM_SLEEP
  3874. static int wcd938x_suspend(struct device *dev)
  3875. {
  3876. struct wcd938x_priv *wcd938x = NULL;
  3877. int ret = 0;
  3878. struct wcd938x_pdata *pdata = NULL;
  3879. if (!dev)
  3880. return -ENODEV;
  3881. wcd938x = dev_get_drvdata(dev);
  3882. if (!wcd938x)
  3883. return -EINVAL;
  3884. pdata = dev_get_platdata(wcd938x->dev);
  3885. if (!pdata) {
  3886. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3887. return -EINVAL;
  3888. }
  3889. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  3890. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  3891. wcd938x->supplies,
  3892. pdata->regulator,
  3893. pdata->num_supplies,
  3894. "cdc-vdd-buck");
  3895. if (ret == -EINVAL) {
  3896. dev_err(dev, "%s: vdd buck is not disabled\n",
  3897. __func__);
  3898. return 0;
  3899. }
  3900. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  3901. }
  3902. if (wcd938x->dapm_bias_off) {
  3903. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3904. wcd938x->supplies,
  3905. pdata->regulator,
  3906. pdata->num_supplies,
  3907. true);
  3908. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3909. }
  3910. return 0;
  3911. }
  3912. static int wcd938x_resume(struct device *dev)
  3913. {
  3914. struct wcd938x_priv *wcd938x = NULL;
  3915. struct wcd938x_pdata *pdata = NULL;
  3916. if (!dev)
  3917. return -ENODEV;
  3918. wcd938x = dev_get_drvdata(dev);
  3919. if (!wcd938x)
  3920. return -EINVAL;
  3921. pdata = dev_get_platdata(wcd938x->dev);
  3922. if (!pdata) {
  3923. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3924. return -EINVAL;
  3925. }
  3926. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  3927. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3928. wcd938x->supplies,
  3929. pdata->regulator,
  3930. pdata->num_supplies,
  3931. false);
  3932. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3933. }
  3934. return 0;
  3935. }
  3936. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3937. .suspend_late = wcd938x_suspend,
  3938. .resume_early = wcd938x_resume,
  3939. };
  3940. #endif
  3941. static struct platform_driver wcd938x_codec_driver = {
  3942. .probe = wcd938x_probe,
  3943. .remove = wcd938x_remove,
  3944. .driver = {
  3945. .name = "wcd938x_codec",
  3946. .owner = THIS_MODULE,
  3947. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3948. #ifdef CONFIG_PM_SLEEP
  3949. .pm = &wcd938x_dev_pm_ops,
  3950. #endif
  3951. .suppress_bind_attrs = true,
  3952. },
  3953. };
  3954. module_platform_driver(wcd938x_codec_driver);
  3955. MODULE_DESCRIPTION("WCD938X Codec driver");
  3956. MODULE_LICENSE("GPL v2");