lpass-cdc-wsa2-macro.c 130 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/io.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/clk.h>
  10. #include <linux/thermal.h>
  11. #include <linux/pm_runtime.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dapm.h>
  14. #include <sound/pcm_params.h>
  15. #include <sound/tlv.h>
  16. #include <soc/swr-common.h>
  17. #include <soc/swr-wcd.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include "lpass-cdc.h"
  20. #include "lpass-cdc-comp.h"
  21. #include "lpass-cdc-registers.h"
  22. #include "lpass-cdc-wsa2-macro.h"
  23. #include "lpass-cdc-clk-rsc.h"
  24. #define AUTO_SUSPEND_DELAY 50 /* delay in msec */
  25. #define LPASS_CDC_WSA2_MACRO_MAX_OFFSET 0x1000
  26. #define LPASS_CDC_WSA2_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  27. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  28. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  29. #define LPASS_CDC_WSA2_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
  30. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  31. #define LPASS_CDC_WSA2_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  32. SNDRV_PCM_FMTBIT_S24_LE |\
  33. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  34. #define LPASS_CDC_WSA2_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  35. SNDRV_PCM_RATE_48000)
  36. #define LPASS_CDC_WSA2_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  37. SNDRV_PCM_FMTBIT_S24_LE |\
  38. SNDRV_PCM_FMTBIT_S24_3LE)
  39. #define LPASS_CDC_WSA2_MACRO_CPS_RATES (SNDRV_PCM_RATE_48000)
  40. #define LPASS_CDC_WSA2_MACRO_CPS_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
  41. #define NUM_INTERPOLATORS 2
  42. #define LPASS_CDC_WSA2_MACRO_MUX_INP_SHFT 0x3
  43. #define LPASS_CDC_WSA2_MACRO_MUX_INP_MASK1 0x07
  44. #define LPASS_CDC_WSA2_MACRO_MUX_INP_MASK2 0x38
  45. #define LPASS_CDC_WSA2_MACRO_MUX_CFG_OFFSET 0x8
  46. #define LPASS_CDC_WSA2_MACRO_MUX_CFG1_OFFSET 0x4
  47. #define LPASS_CDC_WSA2_MACRO_RX_COMP_OFFSET \
  48. (LPASS_CDC_WSA2_COMPANDER1_CTL0 - LPASS_CDC_WSA2_COMPANDER0_CTL0)
  49. #define LPASS_CDC_WSA2_MACRO_RX_SOFTCLIP_OFFSET \
  50. (LPASS_CDC_WSA2_SOFTCLIP1_CRC - LPASS_CDC_WSA2_SOFTCLIP0_CRC)
  51. #define LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET \
  52. (LPASS_CDC_WSA2_RX1_RX_PATH_CTL - LPASS_CDC_WSA2_RX0_RX_PATH_CTL)
  53. #define LPASS_CDC_WSA2_MACRO_RX_PATH_CFG3_OFFSET 0x10
  54. #define LPASS_CDC_WSA2_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
  55. #define LPASS_CDC_WSA2_MACRO_FS_RATE_MASK 0x0F
  56. #define LPASS_CDC_WSA2_MACRO_EC_MIX_TX0_MASK 0x03
  57. #define LPASS_CDC_WSA2_MACRO_EC_MIX_TX1_MASK 0x18
  58. #define LPASS_CDC_WSA2_MACRO_MAX_DMA_CH_PER_PORT 0x2
  59. #define LPASS_CDC_WSA2_MACRO_THERMAL_MAX_STATE 11
  60. enum {
  61. LPASS_CDC_WSA2_MACRO_RX0 = 0,
  62. LPASS_CDC_WSA2_MACRO_RX1,
  63. LPASS_CDC_WSA2_MACRO_RX_MIX,
  64. LPASS_CDC_WSA2_MACRO_RX_MIX0 = LPASS_CDC_WSA2_MACRO_RX_MIX,
  65. LPASS_CDC_WSA2_MACRO_RX_MIX1,
  66. LPASS_CDC_WSA2_MACRO_RX4,
  67. LPASS_CDC_WSA2_MACRO_RX5,
  68. LPASS_CDC_WSA2_MACRO_RX6,
  69. LPASS_CDC_WSA2_MACRO_RX7,
  70. LPASS_CDC_WSA2_MACRO_RX8,
  71. LPASS_CDC_WSA2_MACRO_RX_MAX,
  72. };
  73. enum {
  74. LPASS_CDC_WSA2_MACRO_TX0 = 0,
  75. LPASS_CDC_WSA2_MACRO_TX1,
  76. LPASS_CDC_WSA2_MACRO_TX_MAX,
  77. };
  78. enum {
  79. LPASS_CDC_WSA2_MACRO_EC0_MUX = 0,
  80. LPASS_CDC_WSA2_MACRO_EC1_MUX,
  81. LPASS_CDC_WSA2_MACRO_EC_MUX_MAX,
  82. };
  83. enum {
  84. LPASS_CDC_WSA2_MACRO_COMP1, /* SPK_L */
  85. LPASS_CDC_WSA2_MACRO_COMP2, /* SPK_R */
  86. LPASS_CDC_WSA2_MACRO_COMP_MAX
  87. };
  88. enum {
  89. LPASS_CDC_WSA2_MACRO_SOFTCLIP0, /* RX0 */
  90. LPASS_CDC_WSA2_MACRO_SOFTCLIP1, /* RX1 */
  91. LPASS_CDC_WSA2_MACRO_SOFTCLIP_MAX
  92. };
  93. enum {
  94. INTn_1_INP_SEL_ZERO = 0,
  95. INTn_1_INP_SEL_RX0,
  96. INTn_1_INP_SEL_RX1,
  97. INTn_1_INP_SEL_RX2,
  98. INTn_1_INP_SEL_RX3,
  99. INTn_1_INP_SEL_RX4,
  100. INTn_1_INP_SEL_RX5,
  101. INTn_1_INP_SEL_RX6,
  102. INTn_1_INP_SEL_RX7,
  103. INTn_1_INP_SEL_RX8,
  104. INTn_1_INP_SEL_DEC0,
  105. INTn_1_INP_SEL_DEC1,
  106. };
  107. enum {
  108. INTn_2_INP_SEL_ZERO = 0,
  109. INTn_2_INP_SEL_RX0,
  110. INTn_2_INP_SEL_RX1,
  111. INTn_2_INP_SEL_RX2,
  112. INTn_2_INP_SEL_RX3,
  113. INTn_2_INP_SEL_RX4,
  114. INTn_2_INP_SEL_RX5,
  115. INTn_2_INP_SEL_RX6,
  116. INTn_2_INP_SEL_RX7,
  117. INTn_2_INP_SEL_RX8,
  118. };
  119. enum {
  120. IDLE_DETECT,
  121. NG1,
  122. NG2,
  123. NG3,
  124. };
  125. static struct lpass_cdc_comp_setting comp_setting_table[G_MAX_DB] = {
  126. {42, 0, 42},
  127. {39, 0, 42},
  128. {36, 0, 42},
  129. {33, 0, 42},
  130. {30, 0, 42},
  131. {27, 0, 42},
  132. {24, 0, 42},
  133. {21, 0, 42},
  134. {18, 0, 42},
  135. };
  136. struct interp_sample_rate {
  137. int sample_rate;
  138. int rate_val;
  139. };
  140. /*
  141. * Structure used to update codec
  142. * register defaults after reset
  143. */
  144. struct lpass_cdc_wsa2_macro_reg_mask_val {
  145. u16 reg;
  146. u8 mask;
  147. u8 val;
  148. };
  149. static struct interp_sample_rate int_prim_sample_rate_val[] = {
  150. {8000, 0x0}, /* 8K */
  151. {16000, 0x1}, /* 16K */
  152. {24000, -EINVAL},/* 24K */
  153. {32000, 0x3}, /* 32K */
  154. {48000, 0x4}, /* 48K */
  155. {96000, 0x5}, /* 96K */
  156. {192000, 0x6}, /* 192K */
  157. {384000, 0x7}, /* 384K */
  158. {44100, 0x8}, /* 44.1K */
  159. };
  160. static struct interp_sample_rate int_mix_sample_rate_val[] = {
  161. {48000, 0x4}, /* 48K */
  162. {96000, 0x5}, /* 96K */
  163. {192000, 0x6}, /* 192K */
  164. };
  165. #define LPASS_CDC_WSA2_MACRO_SWR_STRING_LEN 80
  166. static int lpass_cdc_wsa2_macro_core_vote(void *handle, bool enable);
  167. static int lpass_cdc_wsa2_macro_hw_params(struct snd_pcm_substream *substream,
  168. struct snd_pcm_hw_params *params,
  169. struct snd_soc_dai *dai);
  170. static int lpass_cdc_wsa2_macro_get_channel_map(struct snd_soc_dai *dai,
  171. unsigned int *tx_num, unsigned int *tx_slot,
  172. unsigned int *rx_num, unsigned int *rx_slot);
  173. static int lpass_cdc_wsa2_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream);
  174. #define LPASS_CDC_WSA2_MACRO_VTH_TO_REG(vth) ((vth) == 0 ? 255 : (vth))
  175. /* Hold instance to soundwire platform device */
  176. struct lpass_cdc_wsa2_macro_swr_ctrl_data {
  177. struct platform_device *wsa2_swr_pdev;
  178. };
  179. static int lpass_cdc_wsa2_macro_enable_vi_decimator(struct snd_soc_component *component);
  180. #define LPASS_CDC_WSA2_MACRO_SET_VOLUME_TLV(xname, xreg, xmin, xmax, tlv_array) \
  181. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  182. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
  183. SNDRV_CTL_ELEM_ACCESS_READWRITE, \
  184. .tlv.p = (tlv_array), \
  185. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  186. .put = lpass_cdc_wsa2_macro_set_digital_volume, \
  187. .private_value = (unsigned long)&(struct soc_mixer_control) \
  188. {.reg = xreg, .rreg = xreg, \
  189. .min = xmin, .max = xmax, \
  190. .sign_bit = 7,} }
  191. struct lpass_cdc_wsa2_macro_swr_ctrl_platform_data {
  192. void *handle; /* holds codec private data */
  193. int (*read)(void *handle, int reg);
  194. int (*write)(void *handle, int reg, int val);
  195. int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
  196. int (*clk)(void *handle, bool enable);
  197. int (*core_vote)(void *handle, bool enable);
  198. int (*handle_irq)(void *handle,
  199. irqreturn_t (*swrm_irq_handler)(int irq,
  200. void *data),
  201. void *swrm_handle,
  202. int action);
  203. };
  204. enum {
  205. LPASS_CDC_WSA2_MACRO_AIF_INVALID = 0,
  206. LPASS_CDC_WSA2_MACRO_AIF1_PB,
  207. LPASS_CDC_WSA2_MACRO_AIF_MIX1_PB,
  208. LPASS_CDC_WSA2_MACRO_AIF_VI,
  209. LPASS_CDC_WSA2_MACRO_AIF_ECHO,
  210. LPASS_CDC_WSA2_MACRO_AIF_CPS,
  211. LPASS_CDC_WSA2_MACRO_MAX_DAIS,
  212. };
  213. #define LPASS_CDC_WSA2_MACRO_CHILD_DEVICES_MAX 3
  214. /*
  215. * @dev: wsa2 macro device pointer
  216. * @comp_enabled: compander enable mixer value set
  217. * @ec_hq: echo HQ enable mixer value set
  218. * @prim_int_users: Users of interpolator
  219. * @wsa2_mclk_users: WSA2 MCLK users count
  220. * @swr_clk_users: SWR clk users count
  221. * @vi_feed_value: VI sense mask
  222. * @mclk_lock: to lock mclk operations
  223. * @swr_clk_lock: to lock swr master clock operations
  224. * @swr_ctrl_data: SoundWire data structure
  225. * @swr_plat_data: Soundwire platform data
  226. * @lpass_cdc_wsa2_macro_add_child_devices_work: work for adding child devices
  227. * @wsa2_swr_gpio_p: used by pinctrl API
  228. * @component: codec handle
  229. * @rx_0_count: RX0 interpolation users
  230. * @rx_1_count: RX1 interpolation users
  231. * @active_ch_mask: channel mask for all AIF DAIs
  232. * @active_ch_cnt: channel count of all AIF DAIs
  233. * @rx_port_value: mixer ctl value of WSA2 RX MUXes
  234. * @wsa2_io_base: Base address of WSA2 macro addr space
  235. * @wsa2_sys_gain System gain value, see wsa2 driver
  236. * @wsa2_bat_cfg Battery Configuration value, see wsa2 driver
  237. * @wsa2_rload Resistor load value for WSA2 Speaker, see wsa2 driver
  238. */
  239. struct lpass_cdc_wsa2_macro_priv {
  240. struct device *dev;
  241. int comp_enabled[LPASS_CDC_WSA2_MACRO_COMP_MAX];
  242. int comp_mode[LPASS_CDC_WSA2_MACRO_COMP_MAX];
  243. int ec_hq[LPASS_CDC_WSA2_MACRO_RX1 + 1];
  244. u16 prim_int_users[LPASS_CDC_WSA2_MACRO_RX1 + 1];
  245. u16 wsa2_mclk_users;
  246. u16 swr_clk_users;
  247. bool dapm_mclk_enable;
  248. bool reset_swr;
  249. unsigned int vi_feed_value;
  250. struct mutex mclk_lock;
  251. struct mutex swr_clk_lock;
  252. struct lpass_cdc_wsa2_macro_swr_ctrl_data *swr_ctrl_data;
  253. struct lpass_cdc_wsa2_macro_swr_ctrl_platform_data swr_plat_data;
  254. struct work_struct lpass_cdc_wsa2_macro_add_child_devices_work;
  255. struct device_node *wsa2_swr_gpio_p;
  256. struct snd_soc_component *component;
  257. int rx_0_count;
  258. int rx_1_count;
  259. unsigned long active_ch_mask[LPASS_CDC_WSA2_MACRO_MAX_DAIS];
  260. unsigned long active_ch_cnt[LPASS_CDC_WSA2_MACRO_MAX_DAIS];
  261. u16 bit_width[LPASS_CDC_WSA2_MACRO_MAX_DAIS];
  262. int rx_port_value[LPASS_CDC_WSA2_MACRO_RX_MAX];
  263. char __iomem *wsa2_io_base;
  264. struct platform_device *pdev_child_devices
  265. [LPASS_CDC_WSA2_MACRO_CHILD_DEVICES_MAX];
  266. int child_count;
  267. int wsa2_spkrrecv;
  268. int spkr_gain_offset;
  269. int spkr_mode;
  270. int is_softclip_on[LPASS_CDC_WSA2_MACRO_SOFTCLIP_MAX];
  271. int softclip_clk_users[LPASS_CDC_WSA2_MACRO_SOFTCLIP_MAX];
  272. char __iomem *mclk_mode_muxsel;
  273. u16 default_clk_id;
  274. u32 pcm_rate_vi;
  275. int wsa2_digital_mute_status[LPASS_CDC_WSA2_MACRO_RX_MAX];
  276. u8 rx0_origin_gain;
  277. u8 rx1_origin_gain;
  278. struct thermal_cooling_device *tcdev;
  279. uint32_t thermal_cur_state;
  280. uint32_t thermal_max_state;
  281. struct work_struct lpass_cdc_wsa2_macro_cooling_work;
  282. bool pbr_enable;
  283. u32 wsa2_sys_gain[2 * (LPASS_CDC_WSA2_MACRO_RX1 + 1)];
  284. u32 wsa2_bat_cfg[LPASS_CDC_WSA2_MACRO_RX1 + 1];
  285. u32 wsa2_rload[LPASS_CDC_WSA2_MACRO_RX1 + 1];
  286. u32 wsa2_fs_ctl_reg;
  287. u8 idle_detect_en;
  288. int noise_gate_mode;
  289. bool pre_dev_up;
  290. int pbr_clk_users;
  291. char __iomem *wsa2_fs_reg_base;
  292. bool wsa2_2ch_dma_enable;
  293. };
  294. static struct snd_soc_dai_driver lpass_cdc_wsa2_macro_dai[];
  295. static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
  296. static const char *const rx_text[] = {
  297. "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4",
  298. "RX5", "RX6", "RX7", "RX8", "DEC0", "DEC1"
  299. };
  300. static const char *const rx_mix_text[] = {
  301. "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8"
  302. };
  303. static const char *const rx_mix_ec_text[] = {
  304. "ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
  305. };
  306. static const char *const rx_mux_text[] = {
  307. "ZERO", "AIF1_PB", "AIF_MIX1_PB"
  308. };
  309. static const char *const rx_sidetone_mix_text[] = {
  310. "ZERO", "SRC0"
  311. };
  312. static const char * const lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_text[] = {
  313. "OFF", "ON"
  314. };
  315. static const char * const lpass_cdc_wsa2_macro_comp_mode_text[] = {
  316. "G_21_DB", "G_19P5_DB", "G_18_DB", "G_16P5_DB", "G_15_DB",
  317. "G_13P5_DB", "G_12_DB", "G_10P5_DB", "G_9_DB"
  318. };
  319. static const struct snd_kcontrol_new wsa2_int0_vbat_mix_switch[] = {
  320. SOC_DAPM_SINGLE("WSA2 RX0 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
  321. };
  322. static const struct snd_kcontrol_new wsa2_int1_vbat_mix_switch[] = {
  323. SOC_DAPM_SINGLE("WSA2 RX1 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
  324. };
  325. static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_enum,
  326. lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa2_macro_comp_mode_enum,
  328. lpass_cdc_wsa2_macro_comp_mode_text);
  329. /* RX INT0 */
  330. static const struct soc_enum rx0_prim_inp0_chain_enum =
  331. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0,
  332. 0, 12, rx_text);
  333. static const struct soc_enum rx0_prim_inp1_chain_enum =
  334. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0,
  335. 3, 12, rx_text);
  336. static const struct soc_enum rx0_prim_inp2_chain_enum =
  337. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1,
  338. 3, 12, rx_text);
  339. static const struct soc_enum rx0_mix_chain_enum =
  340. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1,
  341. 0, 10, rx_mix_text);
  342. static const struct soc_enum rx0_sidetone_mix_enum =
  343. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
  344. static const struct snd_kcontrol_new rx0_prim_inp0_mux =
  345. SOC_DAPM_ENUM("WSA2_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
  346. static const struct snd_kcontrol_new rx0_prim_inp1_mux =
  347. SOC_DAPM_ENUM("WSA2_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
  348. static const struct snd_kcontrol_new rx0_prim_inp2_mux =
  349. SOC_DAPM_ENUM("WSA2_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
  350. static const struct snd_kcontrol_new rx0_mix_mux =
  351. SOC_DAPM_ENUM("WSA2_RX0 MIX Mux", rx0_mix_chain_enum);
  352. static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
  353. SOC_DAPM_ENUM("WSA2_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
  354. /* RX INT1 */
  355. static const struct soc_enum rx1_prim_inp0_chain_enum =
  356. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0,
  357. 0, 12, rx_text);
  358. static const struct soc_enum rx1_prim_inp1_chain_enum =
  359. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0,
  360. 3, 12, rx_text);
  361. static const struct soc_enum rx1_prim_inp2_chain_enum =
  362. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1,
  363. 3, 12, rx_text);
  364. static const struct soc_enum rx1_mix_chain_enum =
  365. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1,
  366. 0, 10, rx_mix_text);
  367. static const struct snd_kcontrol_new rx1_prim_inp0_mux =
  368. SOC_DAPM_ENUM("WSA2_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);
  369. static const struct snd_kcontrol_new rx1_prim_inp1_mux =
  370. SOC_DAPM_ENUM("WSA2_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);
  371. static const struct snd_kcontrol_new rx1_prim_inp2_mux =
  372. SOC_DAPM_ENUM("WSA2_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);
  373. static const struct snd_kcontrol_new rx1_mix_mux =
  374. SOC_DAPM_ENUM("WSA2_RX1 MIX Mux", rx1_mix_chain_enum);
  375. static const struct soc_enum rx_mix_ec0_enum =
  376. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0,
  377. 0, 3, rx_mix_ec_text);
  378. static const struct soc_enum rx_mix_ec1_enum =
  379. SOC_ENUM_SINGLE(LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0,
  380. 3, 3, rx_mix_ec_text);
  381. static const struct snd_kcontrol_new rx_mix_ec0_mux =
  382. SOC_DAPM_ENUM("WSA2 RX_MIX EC0_Mux", rx_mix_ec0_enum);
  383. static const struct snd_kcontrol_new rx_mix_ec1_mux =
  384. SOC_DAPM_ENUM("WSA2 RX_MIX EC1_Mux", rx_mix_ec1_enum);
  385. static struct snd_soc_dai_ops lpass_cdc_wsa2_macro_dai_ops = {
  386. .hw_params = lpass_cdc_wsa2_macro_hw_params,
  387. .get_channel_map = lpass_cdc_wsa2_macro_get_channel_map,
  388. .mute_stream = lpass_cdc_wsa2_macro_mute_stream,
  389. };
  390. static struct snd_soc_dai_driver lpass_cdc_wsa2_macro_dai[] = {
  391. {
  392. .name = "wsa2_macro_rx1",
  393. .id = LPASS_CDC_WSA2_MACRO_AIF1_PB,
  394. .playback = {
  395. .stream_name = "WSA2_AIF1 Playback",
  396. .rates = LPASS_CDC_WSA2_MACRO_RX_RATES,
  397. .formats = LPASS_CDC_WSA2_MACRO_RX_FORMATS,
  398. .rate_max = 384000,
  399. .rate_min = 8000,
  400. .channels_min = 1,
  401. .channels_max = 2,
  402. },
  403. .ops = &lpass_cdc_wsa2_macro_dai_ops,
  404. },
  405. {
  406. .name = "wsa2_macro_rx_mix",
  407. .id = LPASS_CDC_WSA2_MACRO_AIF_MIX1_PB,
  408. .playback = {
  409. .stream_name = "WSA2_AIF_MIX1 Playback",
  410. .rates = LPASS_CDC_WSA2_MACRO_RX_MIX_RATES,
  411. .formats = LPASS_CDC_WSA2_MACRO_RX_FORMATS,
  412. .rate_max = 192000,
  413. .rate_min = 48000,
  414. .channels_min = 1,
  415. .channels_max = 2,
  416. },
  417. .ops = &lpass_cdc_wsa2_macro_dai_ops,
  418. },
  419. {
  420. .name = "wsa2_macro_vifeedback",
  421. .id = LPASS_CDC_WSA2_MACRO_AIF_VI,
  422. .capture = {
  423. .stream_name = "WSA2_AIF_VI Capture",
  424. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
  425. .formats = LPASS_CDC_WSA2_MACRO_RX_FORMATS,
  426. .rate_max = 48000,
  427. .rate_min = 8000,
  428. .channels_min = 1,
  429. .channels_max = 4,
  430. },
  431. .ops = &lpass_cdc_wsa2_macro_dai_ops,
  432. },
  433. {
  434. .name = "wsa2_macro_echo",
  435. .id = LPASS_CDC_WSA2_MACRO_AIF_ECHO,
  436. .capture = {
  437. .stream_name = "WSA2_AIF_ECHO Capture",
  438. .rates = LPASS_CDC_WSA2_MACRO_ECHO_RATES,
  439. .formats = LPASS_CDC_WSA2_MACRO_ECHO_FORMATS,
  440. .rate_max = 48000,
  441. .rate_min = 8000,
  442. .channels_min = 1,
  443. .channels_max = 2,
  444. },
  445. .ops = &lpass_cdc_wsa2_macro_dai_ops,
  446. },
  447. {
  448. .name = "wsa2_macro_cpsfeedback",
  449. .id = LPASS_CDC_WSA2_MACRO_AIF_CPS,
  450. .capture = {
  451. .stream_name = "WSA2_AIF_CPS Capture",
  452. .rates = LPASS_CDC_WSA2_MACRO_CPS_RATES,
  453. .formats = LPASS_CDC_WSA2_MACRO_CPS_FORMATS,
  454. .rate_max = 48000,
  455. .rate_min = 48000,
  456. .channels_min = 1,
  457. .channels_max = 2,
  458. },
  459. .ops = &lpass_cdc_wsa2_macro_dai_ops,
  460. },
  461. };
  462. static bool lpass_cdc_wsa2_macro_get_data(struct snd_soc_component *component,
  463. struct device **wsa2_dev,
  464. struct lpass_cdc_wsa2_macro_priv **wsa2_priv,
  465. const char *func_name)
  466. {
  467. *wsa2_dev = lpass_cdc_get_device_ptr(component->dev,
  468. WSA2_MACRO);
  469. if (!(*wsa2_dev)) {
  470. dev_err_ratelimited(component->dev,
  471. "%s: null device for macro!\n", func_name);
  472. return false;
  473. }
  474. *wsa2_priv = dev_get_drvdata((*wsa2_dev));
  475. if (!(*wsa2_priv) || !(*wsa2_priv)->component) {
  476. dev_err_ratelimited(component->dev,
  477. "%s: priv is null for macro!\n", func_name);
  478. return false;
  479. }
  480. return true;
  481. }
  482. static int lpass_cdc_wsa2_macro_set_port_map(struct snd_soc_component *component,
  483. u32 usecase, u32 size, void *data)
  484. {
  485. struct device *wsa2_dev = NULL;
  486. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  487. struct swrm_port_config port_cfg;
  488. int ret = 0;
  489. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  490. return -EINVAL;
  491. memset(&port_cfg, 0, sizeof(port_cfg));
  492. port_cfg.uc = usecase;
  493. port_cfg.size = size;
  494. port_cfg.params = data;
  495. if (wsa2_priv->swr_ctrl_data)
  496. ret = swrm_wcd_notify(
  497. wsa2_priv->swr_ctrl_data[0].wsa2_swr_pdev,
  498. SWR_SET_PORT_MAP, &port_cfg);
  499. return ret;
  500. }
  501. static int lpass_cdc_wsa2_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
  502. u8 int_prim_fs_rate_reg_val,
  503. u32 sample_rate)
  504. {
  505. u8 int_1_mix1_inp;
  506. u32 j, port;
  507. u16 int_mux_cfg0, int_mux_cfg1;
  508. u16 int_fs_reg;
  509. u8 int_mux_cfg0_val, int_mux_cfg1_val;
  510. u8 inp0_sel, inp1_sel, inp2_sel;
  511. struct snd_soc_component *component = dai->component;
  512. struct device *wsa2_dev = NULL;
  513. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  514. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  515. return -EINVAL;
  516. for_each_set_bit(port, &wsa2_priv->active_ch_mask[dai->id],
  517. LPASS_CDC_WSA2_MACRO_RX_MAX) {
  518. int_1_mix1_inp = port;
  519. if ((int_1_mix1_inp < LPASS_CDC_WSA2_MACRO_RX0) ||
  520. (int_1_mix1_inp >= LPASS_CDC_WSA2_MACRO_RX_MAX)) {
  521. dev_err_ratelimited(wsa2_dev,
  522. "%s: Invalid RX port, Dai ID is %d\n",
  523. __func__, dai->id);
  524. return -EINVAL;
  525. }
  526. int_mux_cfg0 = LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0;
  527. /*
  528. * Loop through all interpolator MUX inputs and find out
  529. * to which interpolator input, the cdc_dma rx port
  530. * is connected
  531. */
  532. for (j = 0; j < NUM_INTERPOLATORS; j++) {
  533. int_mux_cfg1 = int_mux_cfg0 + LPASS_CDC_WSA2_MACRO_MUX_CFG1_OFFSET;
  534. int_mux_cfg0_val = snd_soc_component_read(component,
  535. int_mux_cfg0);
  536. int_mux_cfg1_val = snd_soc_component_read(component,
  537. int_mux_cfg1);
  538. inp0_sel = int_mux_cfg0_val & LPASS_CDC_WSA2_MACRO_MUX_INP_MASK1;
  539. inp1_sel = (int_mux_cfg0_val >>
  540. LPASS_CDC_WSA2_MACRO_MUX_INP_SHFT) &
  541. LPASS_CDC_WSA2_MACRO_MUX_INP_MASK1;
  542. inp2_sel = (int_mux_cfg1_val >>
  543. LPASS_CDC_WSA2_MACRO_MUX_INP_SHFT) &
  544. LPASS_CDC_WSA2_MACRO_MUX_INP_MASK1;
  545. if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
  546. (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
  547. (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
  548. int_fs_reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL +
  549. LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET * j;
  550. dev_dbg(wsa2_dev,
  551. "%s: AIF_PB DAI(%d) connected to INT%u_1\n",
  552. __func__, dai->id, j);
  553. dev_dbg(wsa2_dev,
  554. "%s: set INT%u_1 sample rate to %u\n",
  555. __func__, j, sample_rate);
  556. /* sample_rate is in Hz */
  557. snd_soc_component_update_bits(component,
  558. int_fs_reg,
  559. LPASS_CDC_WSA2_MACRO_FS_RATE_MASK,
  560. int_prim_fs_rate_reg_val);
  561. }
  562. int_mux_cfg0 += LPASS_CDC_WSA2_MACRO_MUX_CFG_OFFSET;
  563. }
  564. }
  565. return 0;
  566. }
  567. static int lpass_cdc_wsa2_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
  568. u8 int_mix_fs_rate_reg_val,
  569. u32 sample_rate)
  570. {
  571. u8 int_2_inp;
  572. u32 j, port;
  573. u16 int_mux_cfg1, int_fs_reg;
  574. u8 int_mux_cfg1_val;
  575. struct snd_soc_component *component = dai->component;
  576. struct device *wsa2_dev = NULL;
  577. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  578. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  579. return -EINVAL;
  580. for_each_set_bit(port, &wsa2_priv->active_ch_mask[dai->id],
  581. LPASS_CDC_WSA2_MACRO_RX_MAX) {
  582. int_2_inp = port;
  583. if ((int_2_inp < LPASS_CDC_WSA2_MACRO_RX0) ||
  584. (int_2_inp > LPASS_CDC_WSA2_MACRO_RX_MIX1)) {
  585. dev_err_ratelimited(wsa2_dev,
  586. "%s: Invalid RX port, Dai ID is %d\n",
  587. __func__, dai->id);
  588. return -EINVAL;
  589. }
  590. int_mux_cfg1 = LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1;
  591. for (j = 0; j < NUM_INTERPOLATORS; j++) {
  592. int_mux_cfg1_val = snd_soc_component_read(component,
  593. int_mux_cfg1) &
  594. LPASS_CDC_WSA2_MACRO_MUX_INP_MASK1;
  595. if (int_mux_cfg1_val == int_2_inp +
  596. INTn_2_INP_SEL_RX0) {
  597. int_fs_reg =
  598. LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL +
  599. LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET * j;
  600. dev_dbg(wsa2_dev,
  601. "%s: AIF_PB DAI(%d) connected to INT%u_2\n",
  602. __func__, dai->id, j);
  603. dev_dbg(wsa2_dev,
  604. "%s: set INT%u_2 sample rate to %u\n",
  605. __func__, j, sample_rate);
  606. snd_soc_component_update_bits(component,
  607. int_fs_reg,
  608. LPASS_CDC_WSA2_MACRO_FS_RATE_MASK,
  609. int_mix_fs_rate_reg_val);
  610. }
  611. int_mux_cfg1 += LPASS_CDC_WSA2_MACRO_MUX_CFG_OFFSET;
  612. }
  613. }
  614. return 0;
  615. }
  616. static int lpass_cdc_wsa2_macro_set_interpolator_rate(struct snd_soc_dai *dai,
  617. u32 sample_rate)
  618. {
  619. int rate_val = 0;
  620. int i, ret;
  621. /* set mixing path rate */
  622. for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
  623. if (sample_rate ==
  624. int_mix_sample_rate_val[i].sample_rate) {
  625. rate_val =
  626. int_mix_sample_rate_val[i].rate_val;
  627. break;
  628. }
  629. }
  630. if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) ||
  631. (rate_val < 0))
  632. goto prim_rate;
  633. ret = lpass_cdc_wsa2_macro_set_mix_interpolator_rate(dai,
  634. (u8) rate_val, sample_rate);
  635. prim_rate:
  636. /* set primary path sample rate */
  637. for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
  638. if (sample_rate ==
  639. int_prim_sample_rate_val[i].sample_rate) {
  640. rate_val =
  641. int_prim_sample_rate_val[i].rate_val;
  642. break;
  643. }
  644. }
  645. if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) ||
  646. (rate_val < 0))
  647. return -EINVAL;
  648. ret = lpass_cdc_wsa2_macro_set_prim_interpolator_rate(dai,
  649. (u8) rate_val, sample_rate);
  650. return ret;
  651. }
  652. static int lpass_cdc_wsa2_macro_hw_params(struct snd_pcm_substream *substream,
  653. struct snd_pcm_hw_params *params,
  654. struct snd_soc_dai *dai)
  655. {
  656. struct snd_soc_component *component = dai->component;
  657. int ret;
  658. struct device *wsa2_dev = NULL;
  659. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  660. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  661. return -EINVAL;
  662. wsa2_priv = dev_get_drvdata(wsa2_dev);
  663. if (!wsa2_priv)
  664. return -EINVAL;
  665. dev_dbg(component->dev,
  666. "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
  667. dai->name, dai->id, params_rate(params),
  668. params_channels(params));
  669. switch (substream->stream) {
  670. case SNDRV_PCM_STREAM_PLAYBACK:
  671. ret = lpass_cdc_wsa2_macro_set_interpolator_rate(dai, params_rate(params));
  672. if (ret) {
  673. dev_err_ratelimited(component->dev,
  674. "%s: cannot set sample rate: %u\n",
  675. __func__, params_rate(params));
  676. return ret;
  677. }
  678. switch (params_width(params)) {
  679. case 16:
  680. wsa2_priv->bit_width[dai->id] = 16;
  681. break;
  682. case 24:
  683. wsa2_priv->bit_width[dai->id] = 24;
  684. break;
  685. case 32:
  686. wsa2_priv->bit_width[dai->id] = 32;
  687. break;
  688. default:
  689. dev_err_ratelimited(component->dev, "%s: Invalid format 0x%x\n",
  690. __func__, params_width(params));
  691. return -EINVAL;
  692. }
  693. break;
  694. case SNDRV_PCM_STREAM_CAPTURE:
  695. if (dai->id == LPASS_CDC_WSA2_MACRO_AIF_VI)
  696. wsa2_priv->pcm_rate_vi = params_rate(params);
  697. switch (params_width(params)) {
  698. case 16:
  699. wsa2_priv->bit_width[dai->id] = 16;
  700. break;
  701. case 24:
  702. wsa2_priv->bit_width[dai->id] = 24;
  703. break;
  704. case 32:
  705. wsa2_priv->bit_width[dai->id] = 32;
  706. break;
  707. default:
  708. dev_err_ratelimited(component->dev, "%s: Invalid format 0x%x\n",
  709. __func__, params_width(params));
  710. return -EINVAL;
  711. }
  712. break;
  713. default:
  714. break;
  715. }
  716. return 0;
  717. }
  718. static int lpass_cdc_wsa2_macro_get_channel_map(struct snd_soc_dai *dai,
  719. unsigned int *tx_num, unsigned int *tx_slot,
  720. unsigned int *rx_num, unsigned int *rx_slot)
  721. {
  722. struct snd_soc_component *component = dai->component;
  723. struct device *wsa2_dev = NULL;
  724. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  725. u16 val = 0, mask = 0, cnt = 0, temp = 0;
  726. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  727. return -EINVAL;
  728. wsa2_priv = dev_get_drvdata(wsa2_dev);
  729. if (!wsa2_priv)
  730. return -EINVAL;
  731. switch (dai->id) {
  732. case LPASS_CDC_WSA2_MACRO_AIF_VI:
  733. for_each_set_bit(temp, &wsa2_priv->active_ch_mask[dai->id],
  734. LPASS_CDC_WSA2_MACRO_TX_MAX) {
  735. mask |= (1 << temp);
  736. if (++cnt == LPASS_CDC_WSA2_MACRO_MAX_DMA_CH_PER_PORT)
  737. break;
  738. }
  739. /* consider WSA2 Backend is used when 2ch_dma is enabled
  740. * and doesn't require channel mask shift
  741. */
  742. if (!wsa2_priv->wsa2_2ch_dma_enable) {
  743. if (mask & 0x03)
  744. mask = mask << 0x2;
  745. }
  746. *tx_slot = mask;
  747. *tx_num = cnt;
  748. break;
  749. case LPASS_CDC_WSA2_MACRO_AIF_CPS:
  750. *tx_slot = wsa2_priv->active_ch_mask[dai->id];
  751. *tx_num = wsa2_priv->active_ch_cnt[dai->id];
  752. break;
  753. case LPASS_CDC_WSA2_MACRO_AIF1_PB:
  754. case LPASS_CDC_WSA2_MACRO_AIF_MIX1_PB:
  755. for_each_set_bit(temp, &wsa2_priv->active_ch_mask[dai->id],
  756. LPASS_CDC_WSA2_MACRO_RX_MAX) {
  757. mask |= (1 << temp);
  758. if (++cnt == LPASS_CDC_WSA2_MACRO_MAX_DMA_CH_PER_PORT)
  759. break;
  760. }
  761. if (mask & 0x30)
  762. mask = mask >> 0x4;
  763. else
  764. mask = mask << 0x2;
  765. *rx_slot = mask;
  766. *rx_num = cnt;
  767. break;
  768. case LPASS_CDC_WSA2_MACRO_AIF_ECHO:
  769. val = snd_soc_component_read(component,
  770. LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0);
  771. if (val & LPASS_CDC_WSA2_MACRO_EC_MIX_TX1_MASK) {
  772. mask |= 0x2;
  773. cnt++;
  774. }
  775. if (val & LPASS_CDC_WSA2_MACRO_EC_MIX_TX0_MASK) {
  776. mask |= 0x1;
  777. cnt++;
  778. }
  779. *tx_slot = mask;
  780. *tx_num = cnt;
  781. break;
  782. default:
  783. dev_err(wsa2_dev, "%s: Invalid AIF\n", __func__);
  784. break;
  785. }
  786. return 0;
  787. }
  788. static void lpass_cdc_wsa2_unmute_interpolator(struct snd_soc_dai *dai)
  789. {
  790. struct snd_soc_component *component = dai->component;
  791. uint16_t j = 0, reg = 0, mix_reg = 0;
  792. switch (dai->id) {
  793. case LPASS_CDC_WSA2_MACRO_AIF1_PB:
  794. case LPASS_CDC_WSA2_MACRO_AIF_MIX1_PB:
  795. for (j = 0; j < NUM_INTERPOLATORS; ++j) {
  796. reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL +
  797. (j * LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET);
  798. mix_reg = LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL +
  799. (j * LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET);
  800. snd_soc_component_update_bits(component, reg, 0x10, 0x00);
  801. snd_soc_component_update_bits(component, mix_reg, 0x10, 0x00);
  802. }
  803. }
  804. }
  805. static int lpass_cdc_wsa2_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
  806. {
  807. struct snd_soc_component *component = dai->component;
  808. struct device *wsa2_dev = NULL;
  809. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  810. uint32_t temp;
  811. bool adie_lb = false;
  812. if (mute)
  813. return 0;
  814. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  815. return -EINVAL;
  816. switch (dai->id) {
  817. case LPASS_CDC_WSA2_MACRO_AIF1_PB:
  818. case LPASS_CDC_WSA2_MACRO_AIF_MIX1_PB:
  819. lpass_cdc_wsa_pa_on(wsa2_dev, adie_lb);
  820. lpass_cdc_wsa2_unmute_interpolator(dai);
  821. lpass_cdc_wsa2_macro_enable_vi_decimator(component);
  822. break;
  823. default:
  824. break;
  825. }
  826. if ((test_bit(LPASS_CDC_WSA2_MACRO_RX4,
  827. &wsa2_priv->active_ch_mask[dai->id]) ||
  828. test_bit(LPASS_CDC_WSA2_MACRO_RX5,
  829. &wsa2_priv->active_ch_mask[dai->id])) &&
  830. wsa2_priv->wsa2_fs_reg_base) {
  831. temp = ioread32(wsa2_priv->wsa2_fs_reg_base);
  832. if (temp != 1) {
  833. temp = 1;
  834. iowrite32(temp, wsa2_priv->wsa2_fs_reg_base);
  835. }
  836. dev_dbg(wsa2_dev, "%s: LPASS_WSA_FS_CTL : %d", __func__, temp);
  837. }
  838. return 0;
  839. }
  840. static int lpass_cdc_wsa2_macro_mclk_enable(
  841. struct lpass_cdc_wsa2_macro_priv *wsa2_priv,
  842. bool mclk_enable, bool dapm)
  843. {
  844. struct regmap *regmap = dev_get_regmap(wsa2_priv->dev->parent, NULL);
  845. int ret = 0;
  846. if (regmap == NULL) {
  847. dev_err_ratelimited(wsa2_priv->dev, "%s: regmap is NULL\n", __func__);
  848. return -EINVAL;
  849. }
  850. dev_dbg(wsa2_priv->dev, "%s: mclk_enable = %u, dapm = %d clk_users= %d\n",
  851. __func__, mclk_enable, dapm, wsa2_priv->wsa2_mclk_users);
  852. mutex_lock(&wsa2_priv->mclk_lock);
  853. if (mclk_enable) {
  854. if (wsa2_priv->wsa2_mclk_users == 0) {
  855. ret = lpass_cdc_clk_rsc_request_clock(wsa2_priv->dev,
  856. wsa2_priv->default_clk_id,
  857. wsa2_priv->default_clk_id,
  858. true);
  859. if (ret < 0) {
  860. dev_err_ratelimited(wsa2_priv->dev,
  861. "%s: wsa2 request clock enable failed\n",
  862. __func__);
  863. goto exit;
  864. }
  865. lpass_cdc_clk_rsc_fs_gen_request(wsa2_priv->dev,
  866. true);
  867. regcache_mark_dirty(regmap);
  868. regcache_sync_region(regmap,
  869. WSA2_START_OFFSET,
  870. WSA2_MAX_OFFSET);
  871. /* 9.6MHz MCLK, set value 0x00 if other frequency */
  872. regmap_update_bits(regmap,
  873. LPASS_CDC_WSA2_TOP_FREQ_MCLK, 0x01, 0x01);
  874. regmap_update_bits(regmap,
  875. LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL,
  876. 0x01, 0x01);
  877. /* Toggle fs_cntr_clr bit*/
  878. regmap_update_bits(regmap,
  879. LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
  880. 0x02, 0x02);
  881. regmap_update_bits(regmap,
  882. LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
  883. 0x02, 0x0);
  884. regmap_update_bits(regmap,
  885. LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL,
  886. 0x01, 0x01);
  887. }
  888. wsa2_priv->wsa2_mclk_users++;
  889. } else {
  890. if (wsa2_priv->wsa2_mclk_users <= 0) {
  891. dev_err_ratelimited(wsa2_priv->dev, "%s: clock already disabled\n",
  892. __func__);
  893. wsa2_priv->wsa2_mclk_users = 0;
  894. goto exit;
  895. }
  896. wsa2_priv->wsa2_mclk_users--;
  897. if (wsa2_priv->wsa2_mclk_users == 0) {
  898. regmap_update_bits(regmap,
  899. LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL,
  900. 0x01, 0x00);
  901. regmap_update_bits(regmap,
  902. LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL,
  903. 0x01, 0x00);
  904. lpass_cdc_clk_rsc_fs_gen_request(wsa2_priv->dev,
  905. false);
  906. lpass_cdc_clk_rsc_request_clock(wsa2_priv->dev,
  907. wsa2_priv->default_clk_id,
  908. wsa2_priv->default_clk_id,
  909. false);
  910. }
  911. }
  912. exit:
  913. mutex_unlock(&wsa2_priv->mclk_lock);
  914. return ret;
  915. }
  916. static int lpass_cdc_wsa2_macro_mclk_event(struct snd_soc_dapm_widget *w,
  917. struct snd_kcontrol *kcontrol, int event)
  918. {
  919. struct snd_soc_component *component =
  920. snd_soc_dapm_to_component(w->dapm);
  921. int ret = 0;
  922. struct device *wsa2_dev = NULL;
  923. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  924. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  925. return -EINVAL;
  926. dev_dbg(wsa2_dev, "%s: event = %d\n", __func__, event);
  927. switch (event) {
  928. case SND_SOC_DAPM_PRE_PMU:
  929. ret = lpass_cdc_wsa2_macro_mclk_enable(wsa2_priv, 1, true);
  930. if (ret)
  931. wsa2_priv->dapm_mclk_enable = false;
  932. else
  933. wsa2_priv->dapm_mclk_enable = true;
  934. break;
  935. case SND_SOC_DAPM_POST_PMD:
  936. if (wsa2_priv->dapm_mclk_enable) {
  937. lpass_cdc_wsa2_macro_mclk_enable(wsa2_priv, 0, true);
  938. wsa2_priv->dapm_mclk_enable = false;
  939. }
  940. break;
  941. default:
  942. dev_err_ratelimited(wsa2_priv->dev,
  943. "%s: invalid DAPM event %d\n", __func__, event);
  944. ret = -EINVAL;
  945. }
  946. return ret;
  947. }
  948. static int lpass_cdc_wsa2_macro_event_handler(struct snd_soc_component *component,
  949. u16 event, u32 data)
  950. {
  951. struct device *wsa2_dev = NULL;
  952. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  953. int ret = 0;
  954. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  955. return -EINVAL;
  956. switch (event) {
  957. case LPASS_CDC_MACRO_EVT_SSR_DOWN:
  958. wsa2_priv->pre_dev_up = false;
  959. if (wsa2_priv->swr_ctrl_data) {
  960. swrm_wcd_notify(
  961. wsa2_priv->swr_ctrl_data[0].wsa2_swr_pdev,
  962. SWR_DEVICE_SSR_DOWN, NULL);
  963. }
  964. if ((!pm_runtime_enabled(wsa2_dev) ||
  965. !pm_runtime_suspended(wsa2_dev))) {
  966. ret = lpass_cdc_runtime_suspend(wsa2_dev);
  967. if (!ret) {
  968. pm_runtime_disable(wsa2_dev);
  969. pm_runtime_set_suspended(wsa2_dev);
  970. pm_runtime_enable(wsa2_dev);
  971. }
  972. }
  973. break;
  974. case LPASS_CDC_MACRO_EVT_PRE_SSR_UP:
  975. break;
  976. case LPASS_CDC_MACRO_EVT_SSR_UP:
  977. wsa2_priv->pre_dev_up = true;
  978. /* reset swr after ssr/pdr */
  979. wsa2_priv->reset_swr = true;
  980. if (wsa2_priv->swr_ctrl_data)
  981. swrm_wcd_notify(
  982. wsa2_priv->swr_ctrl_data[0].wsa2_swr_pdev,
  983. SWR_DEVICE_SSR_UP, NULL);
  984. break;
  985. case LPASS_CDC_MACRO_EVT_CLK_RESET:
  986. lpass_cdc_rsc_clk_reset(wsa2_dev, WSA2_CORE_CLK);
  987. lpass_cdc_rsc_clk_reset(wsa2_dev, WSA2_TX_CORE_CLK);
  988. break;
  989. }
  990. return 0;
  991. }
  992. static int lpass_cdc_wsa2_macro_enable_vi_decimator(struct snd_soc_component *component)
  993. {
  994. struct device *wsa2_dev = NULL;
  995. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  996. u8 val = 0x0;
  997. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  998. return -EINVAL;
  999. usleep_range(5000, 5500);
  1000. dev_dbg(wsa2_dev, "%s: wsa2_priv->pcm_rate_vi %d\n", __func__, wsa2_priv->pcm_rate_vi);
  1001. switch (wsa2_priv->pcm_rate_vi) {
  1002. case 48000:
  1003. val = 0x04;
  1004. break;
  1005. case 24000:
  1006. val = 0x02;
  1007. break;
  1008. case 8000:
  1009. default:
  1010. val = 0x00;
  1011. break;
  1012. }
  1013. if (test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  1014. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  1015. dev_dbg(wsa2_dev, "%s: spkr1 enabled\n", __func__);
  1016. /* Enable V&I sensing */
  1017. snd_soc_component_update_bits(component,
  1018. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1019. 0x20, 0x20);
  1020. snd_soc_component_update_bits(component,
  1021. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1022. 0x20, 0x20);
  1023. snd_soc_component_update_bits(component,
  1024. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1025. 0x0F, val);
  1026. snd_soc_component_update_bits(component,
  1027. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1028. 0x0F, val);
  1029. snd_soc_component_update_bits(component,
  1030. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1031. 0x10, 0x10);
  1032. snd_soc_component_update_bits(component,
  1033. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1034. 0x10, 0x10);
  1035. snd_soc_component_update_bits(component,
  1036. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1037. 0x20, 0x00);
  1038. snd_soc_component_update_bits(component,
  1039. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1040. 0x20, 0x00);
  1041. }
  1042. if (test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  1043. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  1044. dev_dbg(wsa2_dev, "%s: spkr2 enabled\n", __func__);
  1045. /* Enable V&I sensing */
  1046. snd_soc_component_update_bits(component,
  1047. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1048. 0x20, 0x20);
  1049. snd_soc_component_update_bits(component,
  1050. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1051. 0x20, 0x20);
  1052. snd_soc_component_update_bits(component,
  1053. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1054. 0x0F, val);
  1055. snd_soc_component_update_bits(component,
  1056. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1057. 0x0F, val);
  1058. snd_soc_component_update_bits(component,
  1059. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1060. 0x10, 0x10);
  1061. snd_soc_component_update_bits(component,
  1062. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1063. 0x10, 0x10);
  1064. snd_soc_component_update_bits(component,
  1065. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1066. 0x20, 0x00);
  1067. snd_soc_component_update_bits(component,
  1068. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1069. 0x20, 0x00);
  1070. }
  1071. return 0;
  1072. }
  1073. static int lpass_cdc_wsa2_macro_disable_vi_feedback(struct snd_soc_dapm_widget *w,
  1074. struct snd_kcontrol *kcontrol,
  1075. int event)
  1076. {
  1077. struct snd_soc_component *component =
  1078. snd_soc_dapm_to_component(w->dapm);
  1079. struct device *wsa2_dev = NULL;
  1080. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1081. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1082. return -EINVAL;
  1083. switch (event) {
  1084. case SND_SOC_DAPM_POST_PMD:
  1085. if (test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  1086. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  1087. /* Disable V&I sensing */
  1088. snd_soc_component_update_bits(component,
  1089. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1090. 0x20, 0x20);
  1091. snd_soc_component_update_bits(component,
  1092. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1093. 0x20, 0x20);
  1094. dev_dbg(wsa2_dev, "%s: spkr1 disabled\n", __func__);
  1095. snd_soc_component_update_bits(component,
  1096. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1097. 0x10, 0x00);
  1098. snd_soc_component_update_bits(component,
  1099. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1100. 0x10, 0x00);
  1101. snd_soc_component_update_bits(component,
  1102. LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL,
  1103. 0x20, 0x00);
  1104. snd_soc_component_update_bits(component,
  1105. LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL,
  1106. 0x20, 0x00);
  1107. }
  1108. if (test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  1109. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  1110. /* Disable V&I sensing */
  1111. dev_dbg(wsa2_dev, "%s: spkr2 disabled\n", __func__);
  1112. snd_soc_component_update_bits(component,
  1113. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1114. 0x20, 0x20);
  1115. snd_soc_component_update_bits(component,
  1116. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1117. 0x20, 0x20);
  1118. snd_soc_component_update_bits(component,
  1119. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1120. 0x10, 0x00);
  1121. snd_soc_component_update_bits(component,
  1122. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1123. 0x10, 0x00);
  1124. snd_soc_component_update_bits(component,
  1125. LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL,
  1126. 0x20, 0x00);
  1127. snd_soc_component_update_bits(component,
  1128. LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL,
  1129. 0x20, 0x00);
  1130. }
  1131. break;
  1132. }
  1133. return 0;
  1134. }
  1135. static void lpass_cdc_wsa2_macro_hd2_control(struct snd_soc_component *component,
  1136. u16 reg, int event)
  1137. {
  1138. u16 hd2_scale_reg;
  1139. u16 hd2_enable_reg = 0;
  1140. if (reg == LPASS_CDC_WSA2_RX0_RX_PATH_CTL) {
  1141. hd2_scale_reg = LPASS_CDC_WSA2_RX0_RX_PATH_SEC3;
  1142. hd2_enable_reg = LPASS_CDC_WSA2_RX0_RX_PATH_CFG0;
  1143. }
  1144. if (reg == LPASS_CDC_WSA2_RX1_RX_PATH_CTL) {
  1145. hd2_scale_reg = LPASS_CDC_WSA2_RX1_RX_PATH_SEC3;
  1146. hd2_enable_reg = LPASS_CDC_WSA2_RX1_RX_PATH_CFG0;
  1147. }
  1148. if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
  1149. snd_soc_component_update_bits(component, hd2_scale_reg,
  1150. 0x3C, 0x10);
  1151. snd_soc_component_update_bits(component, hd2_scale_reg,
  1152. 0x03, 0x01);
  1153. snd_soc_component_update_bits(component, hd2_enable_reg,
  1154. 0x04, 0x04);
  1155. }
  1156. if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
  1157. snd_soc_component_update_bits(component, hd2_enable_reg,
  1158. 0x04, 0x00);
  1159. snd_soc_component_update_bits(component, hd2_scale_reg,
  1160. 0x03, 0x00);
  1161. snd_soc_component_update_bits(component, hd2_scale_reg,
  1162. 0x3C, 0x00);
  1163. }
  1164. }
  1165. static int lpass_cdc_wsa2_macro_enable_swr(struct snd_soc_dapm_widget *w,
  1166. struct snd_kcontrol *kcontrol, int event)
  1167. {
  1168. struct snd_soc_component *component =
  1169. snd_soc_dapm_to_component(w->dapm);
  1170. int ch_cnt;
  1171. struct device *wsa2_dev = NULL;
  1172. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1173. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1174. return -EINVAL;
  1175. switch (event) {
  1176. case SND_SOC_DAPM_PRE_PMU:
  1177. if (!(strnstr(w->name, "RX0", sizeof("WSA2_RX0"))) &&
  1178. !wsa2_priv->rx_0_count)
  1179. wsa2_priv->rx_0_count++;
  1180. if (!(strnstr(w->name, "RX1", sizeof("WSA2_RX1"))) &&
  1181. !wsa2_priv->rx_1_count)
  1182. wsa2_priv->rx_1_count++;
  1183. ch_cnt = wsa2_priv->rx_0_count + wsa2_priv->rx_1_count;
  1184. if (wsa2_priv->swr_ctrl_data) {
  1185. swrm_wcd_notify(
  1186. wsa2_priv->swr_ctrl_data[0].wsa2_swr_pdev,
  1187. SWR_DEVICE_UP, NULL);
  1188. }
  1189. break;
  1190. case SND_SOC_DAPM_POST_PMD:
  1191. if (!(strnstr(w->name, "RX0", sizeof("WSA2_RX0"))) &&
  1192. wsa2_priv->rx_0_count)
  1193. wsa2_priv->rx_0_count--;
  1194. if (!(strnstr(w->name, "RX1", sizeof("WSA2_RX1"))) &&
  1195. wsa2_priv->rx_1_count)
  1196. wsa2_priv->rx_1_count--;
  1197. ch_cnt = wsa2_priv->rx_0_count + wsa2_priv->rx_1_count;
  1198. break;
  1199. }
  1200. dev_dbg(wsa2_priv->dev, "%s: current swr ch cnt: %d\n",
  1201. __func__, wsa2_priv->rx_0_count + wsa2_priv->rx_1_count);
  1202. return 0;
  1203. }
  1204. static int lpass_cdc_wsa2_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
  1205. struct snd_kcontrol *kcontrol, int event)
  1206. {
  1207. struct snd_soc_component *component =
  1208. snd_soc_dapm_to_component(w->dapm);
  1209. u16 gain_reg;
  1210. int offset_val = 0;
  1211. int val = 0;
  1212. uint16_t mix_reg = 0;
  1213. uint16_t reg = 0;
  1214. dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name);
  1215. if (!(strcmp(w->name, "WSA2_RX0 MIX INP"))) {
  1216. gain_reg = LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL;
  1217. } else if (!(strcmp(w->name, "WSA2_RX1 MIX INP"))) {
  1218. gain_reg = LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL;
  1219. } else {
  1220. dev_err_ratelimited(component->dev, "%s: No gain register avail for %s\n",
  1221. __func__, w->name);
  1222. return 0;
  1223. }
  1224. reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL +
  1225. LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET * w->shift;
  1226. mix_reg = LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL +
  1227. LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET * w->shift;
  1228. switch (event) {
  1229. case SND_SOC_DAPM_PRE_PMU:
  1230. snd_soc_component_update_bits(component, mix_reg, 0x40, 0x40);
  1231. usleep_range(500, 510);
  1232. snd_soc_component_update_bits(component, mix_reg, 0x40, 0x00);
  1233. snd_soc_component_update_bits(component, reg, 0x20, 0x20);
  1234. snd_soc_component_update_bits(component,
  1235. mix_reg, 0x20, 0x20);
  1236. lpass_cdc_wsa2_macro_enable_swr(w, kcontrol, event);
  1237. val = snd_soc_component_read(component, gain_reg);
  1238. val += offset_val;
  1239. snd_soc_component_write(component, gain_reg, val);
  1240. break;
  1241. case SND_SOC_DAPM_POST_PMD:
  1242. snd_soc_component_update_bits(component,
  1243. w->reg, 0x20, 0x00);
  1244. lpass_cdc_wsa2_macro_enable_swr(w, kcontrol, event);
  1245. break;
  1246. }
  1247. return 0;
  1248. }
  1249. static int lpass_cdc_wsa2_macro_config_compander(struct snd_soc_component *component,
  1250. int comp, int event)
  1251. {
  1252. u16 comp_ctl0_reg, comp_ctl8_reg, rx_path_cfg0_reg;
  1253. struct device *wsa2_dev = NULL;
  1254. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1255. struct lpass_cdc_comp_setting *comp_settings = NULL;
  1256. u16 mode = 0;
  1257. u16 index = 0;
  1258. int sys_gain, bat_cfg, sys_gain_int, upper_gain, lower_gain;
  1259. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1260. return -EINVAL;
  1261. dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n",
  1262. __func__, event, comp + 1, wsa2_priv->comp_enabled[comp]);
  1263. if (comp >= LPASS_CDC_WSA2_MACRO_COMP_MAX || comp < 0) {
  1264. dev_err(component->dev, "%s: Invalid compander value: %d\n",
  1265. __func__, comp);
  1266. return -EINVAL;
  1267. }
  1268. if (!wsa2_priv->comp_enabled[comp])
  1269. return 0;
  1270. mode = wsa2_priv->comp_mode[comp];
  1271. if (mode >= G_MAX_DB || mode < 0)
  1272. mode = 0;
  1273. comp_ctl0_reg = LPASS_CDC_WSA2_COMPANDER0_CTL0 +
  1274. (comp * LPASS_CDC_WSA2_MACRO_RX_COMP_OFFSET);
  1275. comp_ctl8_reg = LPASS_CDC_WSA2_COMPANDER0_CTL8 +
  1276. (comp * LPASS_CDC_WSA2_MACRO_RX_COMP_OFFSET);
  1277. rx_path_cfg0_reg = LPASS_CDC_WSA2_RX0_RX_PATH_CFG0 +
  1278. (comp * LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET);
  1279. comp_settings = &comp_setting_table[mode];
  1280. /* If System has battery configuration */
  1281. if (wsa2_priv->wsa2_bat_cfg[comp]) {
  1282. index = (comp * 2) + wsa2_priv->wsa2_spkrrecv;
  1283. if (index >= (2 * (LPASS_CDC_WSA2_MACRO_RX1 + 1))) {
  1284. dev_err(component->dev, "%s: Invalid index: %d\n",
  1285. __func__, index);
  1286. return -EINVAL;
  1287. }
  1288. sys_gain = wsa2_priv->wsa2_sys_gain[index];
  1289. bat_cfg = wsa2_priv->wsa2_bat_cfg[comp];
  1290. /* Convert enum to value and
  1291. * multiply all values by 10 to avoid float
  1292. */
  1293. sys_gain_int = -15 * sys_gain + 210;
  1294. switch (bat_cfg) {
  1295. case CONFIG_1S:
  1296. case EXT_1S:
  1297. if (sys_gain > G_13P5_DB) {
  1298. upper_gain = sys_gain_int + 60;
  1299. lower_gain = 0;
  1300. } else {
  1301. upper_gain = 210;
  1302. lower_gain = 0;
  1303. }
  1304. break;
  1305. case CONFIG_3S:
  1306. case EXT_3S:
  1307. upper_gain = sys_gain_int;
  1308. lower_gain = 75;
  1309. break;
  1310. case EXT_ABOVE_3S:
  1311. upper_gain = sys_gain_int;
  1312. lower_gain = 120;
  1313. break;
  1314. default:
  1315. upper_gain = sys_gain_int;
  1316. lower_gain = 0;
  1317. break;
  1318. }
  1319. /* Truncate after calculation */
  1320. comp_settings->lower_gain_int = (lower_gain * 2) / 10;
  1321. comp_settings->upper_gain_int = (upper_gain * 2) / 10;
  1322. }
  1323. if (SND_SOC_DAPM_EVENT_ON(event)) {
  1324. lpass_cdc_update_compander_setting(component,
  1325. comp_ctl8_reg,
  1326. comp_settings);
  1327. /* Enable Compander Clock */
  1328. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1329. 0x01, 0x01);
  1330. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1331. 0x02, 0x02);
  1332. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1333. 0x02, 0x00);
  1334. snd_soc_component_update_bits(component, rx_path_cfg0_reg,
  1335. 0x02, 0x02);
  1336. }
  1337. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  1338. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1339. 0x04, 0x04);
  1340. snd_soc_component_update_bits(component, rx_path_cfg0_reg,
  1341. 0x02, 0x00);
  1342. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1343. 0x02, 0x02);
  1344. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1345. 0x02, 0x00);
  1346. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1347. 0x01, 0x00);
  1348. snd_soc_component_update_bits(component, comp_ctl0_reg,
  1349. 0x04, 0x00);
  1350. }
  1351. return 0;
  1352. }
  1353. static void lpass_cdc_wsa2_macro_enable_softclip_clk(struct snd_soc_component *component,
  1354. struct lpass_cdc_wsa2_macro_priv *wsa2_priv,
  1355. int path,
  1356. bool enable)
  1357. {
  1358. u16 softclip_clk_reg = LPASS_CDC_WSA2_SOFTCLIP0_CRC +
  1359. (path * LPASS_CDC_WSA2_MACRO_RX_SOFTCLIP_OFFSET);
  1360. u8 softclip_mux_mask = (1 << path);
  1361. u8 softclip_mux_value = (1 << path);
  1362. dev_dbg(component->dev, "%s: path %d, enable %d\n",
  1363. __func__, path, enable);
  1364. if (enable) {
  1365. if (wsa2_priv->softclip_clk_users[path] == 0) {
  1366. snd_soc_component_update_bits(component,
  1367. softclip_clk_reg, 0x01, 0x01);
  1368. snd_soc_component_update_bits(component,
  1369. LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0,
  1370. softclip_mux_mask, softclip_mux_value);
  1371. }
  1372. wsa2_priv->softclip_clk_users[path]++;
  1373. } else {
  1374. wsa2_priv->softclip_clk_users[path]--;
  1375. if (wsa2_priv->softclip_clk_users[path] == 0) {
  1376. snd_soc_component_update_bits(component,
  1377. softclip_clk_reg, 0x01, 0x00);
  1378. snd_soc_component_update_bits(component,
  1379. LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0,
  1380. softclip_mux_mask, 0x00);
  1381. }
  1382. }
  1383. }
  1384. static int lpass_cdc_wsa2_macro_config_softclip(struct snd_soc_component *component,
  1385. int path, int event)
  1386. {
  1387. u16 softclip_ctrl_reg = 0;
  1388. struct device *wsa2_dev = NULL;
  1389. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1390. int softclip_path = 0;
  1391. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1392. return -EINVAL;
  1393. if (path == LPASS_CDC_WSA2_MACRO_COMP1)
  1394. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP0;
  1395. else if (path == LPASS_CDC_WSA2_MACRO_COMP2)
  1396. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP1;
  1397. dev_dbg(component->dev, "%s: event %d path %d, enabled %d\n",
  1398. __func__, event, softclip_path,
  1399. wsa2_priv->is_softclip_on[softclip_path]);
  1400. if (!wsa2_priv->is_softclip_on[softclip_path])
  1401. return 0;
  1402. softclip_ctrl_reg = LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL +
  1403. (softclip_path * LPASS_CDC_WSA2_MACRO_RX_SOFTCLIP_OFFSET);
  1404. if (SND_SOC_DAPM_EVENT_ON(event)) {
  1405. /* Enable Softclip clock and mux */
  1406. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1407. softclip_path, true);
  1408. /* Enable Softclip control */
  1409. snd_soc_component_update_bits(component, softclip_ctrl_reg,
  1410. 0x01, 0x01);
  1411. }
  1412. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  1413. snd_soc_component_update_bits(component, softclip_ctrl_reg,
  1414. 0x01, 0x00);
  1415. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1416. softclip_path, false);
  1417. }
  1418. return 0;
  1419. }
  1420. static int lpass_cdc_was_macro_config_pbr(struct snd_soc_component *component,
  1421. int path, int event)
  1422. {
  1423. struct device *wsa2_dev = NULL;
  1424. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1425. u16 reg1 = 0, reg2 = 0, reg3 = 0;
  1426. int softclip_path = 0;
  1427. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1428. return -EINVAL;
  1429. if (path == LPASS_CDC_WSA2_MACRO_COMP1) {
  1430. reg1 = LPASS_CDC_WSA2_COMPANDER0_CTL0;
  1431. reg2 = LPASS_CDC_WSA2_RX0_RX_PATH_CFG3;
  1432. reg3 = LPASS_CDC_WSA2_RX0_RX_PATH_CFG1;
  1433. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP0;
  1434. } else if (path == LPASS_CDC_WSA2_MACRO_COMP2) {
  1435. reg1 = LPASS_CDC_WSA2_COMPANDER1_CTL0;
  1436. reg2 = LPASS_CDC_WSA2_RX1_RX_PATH_CFG3;
  1437. reg3 = LPASS_CDC_WSA2_RX1_RX_PATH_CFG1;
  1438. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP1;
  1439. }
  1440. if (!wsa2_priv->pbr_enable || wsa2_priv->wsa2_bat_cfg[path] >= EXT_1S ||
  1441. wsa2_priv->wsa2_sys_gain[path * 2] > G_12_DB ||
  1442. wsa2_priv->wsa2_spkrrecv || !reg1 || !reg2 || !reg3)
  1443. return 0;
  1444. if (SND_SOC_DAPM_EVENT_ON(event)) {
  1445. snd_soc_component_update_bits(component,
  1446. reg1, 0x08, 0x08);
  1447. snd_soc_component_update_bits(component,
  1448. reg2, 0x40, 0x40);
  1449. snd_soc_component_update_bits(component,
  1450. reg3, 0x80, 0x80);
  1451. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1452. softclip_path, true);
  1453. if (wsa2_priv->pbr_clk_users == 0)
  1454. snd_soc_component_update_bits(component,
  1455. LPASS_CDC_WSA2_PBR_PATH_CTL,
  1456. 0x01, 0x01);
  1457. ++wsa2_priv->pbr_clk_users;
  1458. }
  1459. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  1460. if (wsa2_priv->pbr_clk_users)
  1461. snd_soc_component_update_bits(component,
  1462. LPASS_CDC_WSA2_PBR_PATH_CTL,
  1463. 0x01, 0x00);
  1464. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1465. softclip_path, false);
  1466. snd_soc_component_update_bits(component,
  1467. reg1, 0x08, 0x00);
  1468. snd_soc_component_update_bits(component,
  1469. reg2, 0x40, 0x00);
  1470. snd_soc_component_update_bits(component,
  1471. reg3, 0x80, 0x00);
  1472. --wsa2_priv->pbr_clk_users;
  1473. if (wsa2_priv->pbr_clk_users < 0)
  1474. wsa2_priv->pbr_clk_users = 0;
  1475. }
  1476. return 0;
  1477. }
  1478. static bool lpass_cdc_wsa2_macro_adie_lb(struct snd_soc_component *component,
  1479. int interp_idx)
  1480. {
  1481. u16 int_mux_cfg0 = 0, int_mux_cfg1 = 0;
  1482. u8 int_mux_cfg0_val = 0, int_mux_cfg1_val = 0;
  1483. u8 int_n_inp0 = 0, int_n_inp1 = 0, int_n_inp2 = 0;
  1484. int_mux_cfg0 = LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
  1485. int_mux_cfg1 = int_mux_cfg0 + 4;
  1486. int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
  1487. int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
  1488. int_n_inp0 = int_mux_cfg0_val & 0x0F;
  1489. if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
  1490. int_n_inp0 == INTn_1_INP_SEL_DEC1)
  1491. return true;
  1492. int_n_inp1 = int_mux_cfg0_val >> 4;
  1493. if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
  1494. int_n_inp1 == INTn_1_INP_SEL_DEC1)
  1495. return true;
  1496. int_n_inp2 = int_mux_cfg1_val >> 4;
  1497. if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
  1498. int_n_inp2 == INTn_1_INP_SEL_DEC1)
  1499. return true;
  1500. return false;
  1501. }
  1502. static int lpass_cdc_wsa2_macro_enable_main_path(struct snd_soc_dapm_widget *w,
  1503. struct snd_kcontrol *kcontrol,
  1504. int event)
  1505. {
  1506. struct snd_soc_component *component =
  1507. snd_soc_dapm_to_component(w->dapm);
  1508. u16 reg = 0;
  1509. struct device *wsa2_dev = NULL;
  1510. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1511. bool adie_lb = false;
  1512. dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name);
  1513. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1514. return -EINVAL;
  1515. reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL +
  1516. LPASS_CDC_WSA2_MACRO_RX_PATH_OFFSET * w->shift;
  1517. switch (event) {
  1518. case SND_SOC_DAPM_PRE_PMU:
  1519. snd_soc_component_update_bits(component, reg, 0x40, 0x40);
  1520. usleep_range(500, 510);
  1521. snd_soc_component_update_bits(component, reg, 0x40, 0x00);
  1522. snd_soc_component_update_bits(component,
  1523. reg, 0x20, 0x20);
  1524. if (lpass_cdc_wsa2_macro_adie_lb(component, w->shift)) {
  1525. adie_lb = true;
  1526. lpass_cdc_wsa_pa_on(wsa2_dev, adie_lb);
  1527. snd_soc_component_update_bits(component,
  1528. reg, 0x10, 0x00);
  1529. }
  1530. break;
  1531. default:
  1532. break;
  1533. }
  1534. return 0;
  1535. }
  1536. static int lpass_cdc_wsa2_macro_interp_get_primary_reg(u16 reg, u16 *ind)
  1537. {
  1538. u16 prim_int_reg = 0;
  1539. switch (reg) {
  1540. case LPASS_CDC_WSA2_RX0_RX_PATH_CTL:
  1541. case LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL:
  1542. prim_int_reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL;
  1543. *ind = 0;
  1544. break;
  1545. case LPASS_CDC_WSA2_RX1_RX_PATH_CTL:
  1546. case LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL:
  1547. prim_int_reg = LPASS_CDC_WSA2_RX1_RX_PATH_CTL;
  1548. *ind = 1;
  1549. break;
  1550. }
  1551. return prim_int_reg;
  1552. }
  1553. static int lpass_cdc_wsa2_macro_enable_prim_interpolator(
  1554. struct snd_soc_component *component,
  1555. u16 reg, int event)
  1556. {
  1557. u16 prim_int_reg;
  1558. u16 ind = 0;
  1559. struct device *wsa2_dev = NULL;
  1560. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1561. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1562. return -EINVAL;
  1563. prim_int_reg = lpass_cdc_wsa2_macro_interp_get_primary_reg(reg, &ind);
  1564. switch (event) {
  1565. case SND_SOC_DAPM_PRE_PMU:
  1566. wsa2_priv->prim_int_users[ind]++;
  1567. if (wsa2_priv->prim_int_users[ind] == 1) {
  1568. snd_soc_component_update_bits(component,
  1569. prim_int_reg + LPASS_CDC_WSA2_MACRO_RX_PATH_CFG3_OFFSET,
  1570. 0x03, 0x03);
  1571. snd_soc_component_update_bits(component, prim_int_reg,
  1572. 0x10, 0x10);
  1573. lpass_cdc_wsa2_macro_hd2_control(component, prim_int_reg, event);
  1574. snd_soc_component_update_bits(component,
  1575. prim_int_reg + LPASS_CDC_WSA2_MACRO_RX_PATH_DSMDEM_OFFSET,
  1576. 0x1, 0x1);
  1577. }
  1578. if ((reg != prim_int_reg) &&
  1579. ((snd_soc_component_read(
  1580. component, prim_int_reg)) & 0x10))
  1581. snd_soc_component_update_bits(component, reg,
  1582. 0x10, 0x10);
  1583. break;
  1584. case SND_SOC_DAPM_POST_PMD:
  1585. wsa2_priv->prim_int_users[ind]--;
  1586. if (wsa2_priv->prim_int_users[ind] == 0) {
  1587. snd_soc_component_update_bits(component, prim_int_reg,
  1588. 1 << 0x5, 0 << 0x5);
  1589. snd_soc_component_update_bits(component,
  1590. prim_int_reg + LPASS_CDC_WSA2_MACRO_RX_PATH_DSMDEM_OFFSET,
  1591. 0x1, 0x0);
  1592. snd_soc_component_update_bits(component, prim_int_reg,
  1593. 0x40, 0x40);
  1594. snd_soc_component_update_bits(component, prim_int_reg,
  1595. 0x40, 0x00);
  1596. lpass_cdc_wsa2_macro_hd2_control(component, prim_int_reg, event);
  1597. }
  1598. break;
  1599. }
  1600. dev_dbg(component->dev, "%s: primary interpolator: INT%d, users: %d\n",
  1601. __func__, ind, wsa2_priv->prim_int_users[ind]);
  1602. return 0;
  1603. }
  1604. static void lpass_cdc_macro_idle_detect_control(struct snd_soc_component *component,
  1605. struct lpass_cdc_wsa2_macro_priv *wsa2_priv,
  1606. int interp, int event)
  1607. {
  1608. int reg = 0, mask = 0, val = 0, source_reg = 0;
  1609. u16 mode = 0;
  1610. dev_dbg(component->dev, "%s: Idle_detect_en value: %d\n", __func__,
  1611. wsa2_priv->idle_detect_en);
  1612. if (!wsa2_priv->idle_detect_en)
  1613. return;
  1614. if (interp == LPASS_CDC_WSA2_MACRO_COMP1) {
  1615. source_reg = LPASS_CDC_WSA2_RX0_RX_PATH_CFG3;
  1616. reg = LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL;
  1617. mask = 0x01;
  1618. val = 0x01;
  1619. }
  1620. if (interp == LPASS_CDC_WSA2_MACRO_COMP2) {
  1621. source_reg = LPASS_CDC_WSA2_RX1_RX_PATH_CFG3;
  1622. reg = LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL;
  1623. mask = 0x02;
  1624. val = 0x02;
  1625. }
  1626. mode = wsa2_priv->comp_mode[interp];
  1627. if ((wsa2_priv->noise_gate_mode == NG2 && mode >= G_13P5_DB) ||
  1628. wsa2_priv->noise_gate_mode == IDLE_DETECT || !wsa2_priv->pbr_enable ||
  1629. wsa2_priv->wsa2_spkrrecv) {
  1630. snd_soc_component_update_bits(component, source_reg, 0x80, 0x00);
  1631. dev_dbg(component->dev, "%s: Idle detect source: Legacy\n", __func__);
  1632. } else {
  1633. snd_soc_component_update_bits(component, source_reg, 0x80, 0x80);
  1634. dev_dbg(component->dev, "%s: Idle detect source: PRE-LA\n", __func__);
  1635. }
  1636. if (reg && SND_SOC_DAPM_EVENT_ON(event)) {
  1637. snd_soc_component_update_bits(component, reg, mask, val);
  1638. dev_dbg(component->dev, "%s: Idle detect clks ON\n", __func__);
  1639. }
  1640. if (reg && SND_SOC_DAPM_EVENT_OFF(event)) {
  1641. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1642. snd_soc_component_write(component,
  1643. LPASS_CDC_WSA2_IDLE_DETECT_CFG3, 0x0);
  1644. dev_dbg(component->dev, "%s: Idle detect clks OFF\n", __func__);
  1645. }
  1646. }
  1647. static int lpass_cdc_wsa2_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
  1648. struct snd_kcontrol *kcontrol,
  1649. int event)
  1650. {
  1651. struct snd_soc_component *component =
  1652. snd_soc_dapm_to_component(w->dapm);
  1653. struct device *wsa2_dev = NULL;
  1654. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1655. u8 gain = 0;
  1656. u16 reg = 0;
  1657. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1658. return -EINVAL;
  1659. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1660. return -EINVAL;
  1661. dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name);
  1662. if (!(strcmp(w->name, "WSA2_RX INT0 INTERP"))) {
  1663. reg = LPASS_CDC_WSA2_RX0_RX_PATH_CTL;
  1664. } else if (!(strcmp(w->name, "WSA2_RX INT1 INTERP"))) {
  1665. reg = LPASS_CDC_WSA2_RX1_RX_PATH_CTL;
  1666. } else {
  1667. dev_err_ratelimited(component->dev, "%s: Interpolator reg not found\n",
  1668. __func__);
  1669. return -EINVAL;
  1670. }
  1671. switch (event) {
  1672. case SND_SOC_DAPM_PRE_PMU:
  1673. /* Reset if needed */
  1674. lpass_cdc_wsa2_macro_enable_prim_interpolator(component, reg, event);
  1675. break;
  1676. case SND_SOC_DAPM_POST_PMU:
  1677. if (!strcmp(w->name, "WSA2_RX INT0 INTERP")) {
  1678. gain = (u8)(wsa2_priv->rx0_origin_gain -
  1679. wsa2_priv->thermal_cur_state);
  1680. if (snd_soc_component_read(wsa2_priv->component,
  1681. LPASS_CDC_WSA2_RX0_RX_VOL_CTL) != gain) {
  1682. snd_soc_component_update_bits(wsa2_priv->component,
  1683. LPASS_CDC_WSA2_RX0_RX_VOL_CTL, 0xFF, gain);
  1684. dev_dbg(wsa2_priv->dev,
  1685. "%s: RX0 current thermal state: %d, "
  1686. "adjusted gain: %#x\n",
  1687. __func__, wsa2_priv->thermal_cur_state, gain);
  1688. }
  1689. }
  1690. if (!strcmp(w->name, "WSA2_RX INT1 INTERP")) {
  1691. gain = (u8)(wsa2_priv->rx1_origin_gain -
  1692. wsa2_priv->thermal_cur_state);
  1693. if (snd_soc_component_read(wsa2_priv->component,
  1694. LPASS_CDC_WSA2_RX1_RX_VOL_CTL) != gain) {
  1695. snd_soc_component_update_bits(wsa2_priv->component,
  1696. LPASS_CDC_WSA2_RX1_RX_VOL_CTL, 0xFF, gain);
  1697. dev_dbg(wsa2_priv->dev,
  1698. "%s: RX1 current thermal state: %d, "
  1699. "adjusted gain: %#x\n",
  1700. __func__, wsa2_priv->thermal_cur_state, gain);
  1701. }
  1702. }
  1703. lpass_cdc_wsa2_macro_config_compander(component, w->shift, event);
  1704. lpass_cdc_macro_idle_detect_control(component, wsa2_priv,
  1705. w->shift, event);
  1706. lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event);
  1707. lpass_cdc_was_macro_config_pbr(component, w->shift, event);
  1708. if (wsa2_priv->wsa2_spkrrecv)
  1709. snd_soc_component_update_bits(component,
  1710. LPASS_CDC_WSA2_RX0_RX_PATH_CFG1,
  1711. 0x08, 0x00);
  1712. break;
  1713. case SND_SOC_DAPM_POST_PMD:
  1714. snd_soc_component_update_bits(component,
  1715. LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x08, 0x08);
  1716. lpass_cdc_wsa2_macro_config_compander(component, w->shift, event);
  1717. lpass_cdc_macro_idle_detect_control(component, wsa2_priv,
  1718. w->shift, event);
  1719. lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event);
  1720. lpass_cdc_was_macro_config_pbr(component, w->shift, event);
  1721. lpass_cdc_wsa2_macro_enable_prim_interpolator(component, reg, event);
  1722. break;
  1723. }
  1724. return 0;
  1725. }
  1726. static int lpass_cdc_wsa2_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
  1727. struct snd_kcontrol *kcontrol,
  1728. int event)
  1729. {
  1730. struct snd_soc_component *component =
  1731. snd_soc_dapm_to_component(w->dapm);
  1732. u16 boost_path_ctl, boost_path_cfg1;
  1733. dev_dbg(component->dev, "%s %s %d\n", __func__, w->name, event);
  1734. if (!strcmp(w->name, "WSA2_RX INT0 CHAIN")) {
  1735. boost_path_ctl = LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL;
  1736. boost_path_cfg1 = LPASS_CDC_WSA2_RX0_RX_PATH_CFG1;
  1737. } else if (!strcmp(w->name, "WSA2_RX INT1 CHAIN")) {
  1738. boost_path_ctl = LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL;
  1739. boost_path_cfg1 = LPASS_CDC_WSA2_RX1_RX_PATH_CFG1;
  1740. } else {
  1741. dev_err_ratelimited(component->dev, "%s: unknown widget: %s\n",
  1742. __func__, w->name);
  1743. return -EINVAL;
  1744. }
  1745. switch (event) {
  1746. case SND_SOC_DAPM_PRE_PMU:
  1747. snd_soc_component_update_bits(component, boost_path_cfg1,
  1748. 0x01, 0x01);
  1749. snd_soc_component_update_bits(component, boost_path_ctl,
  1750. 0x10, 0x10);
  1751. break;
  1752. case SND_SOC_DAPM_POST_PMU:
  1753. break;
  1754. case SND_SOC_DAPM_POST_PMD:
  1755. snd_soc_component_update_bits(component, boost_path_ctl,
  1756. 0x10, 0x00);
  1757. snd_soc_component_update_bits(component, boost_path_cfg1,
  1758. 0x01, 0x00);
  1759. break;
  1760. }
  1761. return 0;
  1762. }
  1763. static int lpass_cdc_wsa2_macro_enable_vbat(struct snd_soc_dapm_widget *w,
  1764. struct snd_kcontrol *kcontrol,
  1765. int event)
  1766. {
  1767. struct snd_soc_component *component =
  1768. snd_soc_dapm_to_component(w->dapm);
  1769. struct device *wsa2_dev = NULL;
  1770. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1771. u16 vbat_path_cfg = 0;
  1772. int softclip_path = 0;
  1773. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1774. return -EINVAL;
  1775. dev_dbg(component->dev, "%s %s %d\n", __func__, w->name, event);
  1776. if (!strcmp(w->name, "WSA2_RX INT0 VBAT")) {
  1777. vbat_path_cfg = LPASS_CDC_WSA2_RX0_RX_PATH_CFG1;
  1778. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP0;
  1779. } else if (!strcmp(w->name, "WSA2_RX INT1 VBAT")) {
  1780. vbat_path_cfg = LPASS_CDC_WSA2_RX1_RX_PATH_CFG1;
  1781. softclip_path = LPASS_CDC_WSA2_MACRO_SOFTCLIP1;
  1782. }
  1783. switch (event) {
  1784. case SND_SOC_DAPM_PRE_PMU:
  1785. /* Enable clock for VBAT block */
  1786. snd_soc_component_update_bits(component,
  1787. LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL, 0x10, 0x10);
  1788. /* Enable VBAT block */
  1789. snd_soc_component_update_bits(component,
  1790. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x01, 0x01);
  1791. /* Update interpolator with 384K path */
  1792. snd_soc_component_update_bits(component, vbat_path_cfg,
  1793. 0x80, 0x80);
  1794. /* Use attenuation mode */
  1795. snd_soc_component_update_bits(component,
  1796. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x02, 0x00);
  1797. /*
  1798. * BCL block needs softclip clock and mux config to be enabled
  1799. */
  1800. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1801. softclip_path, true);
  1802. /* Enable VBAT at channel level */
  1803. snd_soc_component_update_bits(component, vbat_path_cfg,
  1804. 0x02, 0x02);
  1805. /* Set the ATTK1 gain */
  1806. snd_soc_component_update_bits(component,
  1807. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1,
  1808. 0xFF, 0xFF);
  1809. snd_soc_component_update_bits(component,
  1810. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2,
  1811. 0xFF, 0x03);
  1812. snd_soc_component_update_bits(component,
  1813. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3,
  1814. 0xFF, 0x00);
  1815. /* Set the ATTK2 gain */
  1816. snd_soc_component_update_bits(component,
  1817. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4,
  1818. 0xFF, 0xFF);
  1819. snd_soc_component_update_bits(component,
  1820. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5,
  1821. 0xFF, 0x03);
  1822. snd_soc_component_update_bits(component,
  1823. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6,
  1824. 0xFF, 0x00);
  1825. /* Set the ATTK3 gain */
  1826. snd_soc_component_update_bits(component,
  1827. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7,
  1828. 0xFF, 0xFF);
  1829. snd_soc_component_update_bits(component,
  1830. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8,
  1831. 0xFF, 0x03);
  1832. snd_soc_component_update_bits(component,
  1833. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9,
  1834. 0xFF, 0x00);
  1835. /* Enable CB decode block clock */
  1836. snd_soc_component_update_bits(component,
  1837. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x01);
  1838. /* Enable BCL path */
  1839. snd_soc_component_update_bits(component,
  1840. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2, 0x01, 0x01);
  1841. /* Request for BCL data */
  1842. snd_soc_component_update_bits(component,
  1843. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x01);
  1844. break;
  1845. case SND_SOC_DAPM_POST_PMD:
  1846. snd_soc_component_update_bits(component,
  1847. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x00);
  1848. snd_soc_component_update_bits(component,
  1849. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2, 0x01, 0x00);
  1850. snd_soc_component_update_bits(component,
  1851. LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x00);
  1852. snd_soc_component_update_bits(component, vbat_path_cfg,
  1853. 0x80, 0x00);
  1854. snd_soc_component_update_bits(component,
  1855. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG,
  1856. 0x02, 0x02);
  1857. snd_soc_component_update_bits(component, vbat_path_cfg,
  1858. 0x02, 0x00);
  1859. snd_soc_component_update_bits(component,
  1860. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1,
  1861. 0xFF, 0x00);
  1862. snd_soc_component_update_bits(component,
  1863. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2,
  1864. 0xFF, 0x00);
  1865. snd_soc_component_update_bits(component,
  1866. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3,
  1867. 0xFF, 0x00);
  1868. snd_soc_component_update_bits(component,
  1869. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4,
  1870. 0xFF, 0x00);
  1871. snd_soc_component_update_bits(component,
  1872. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5,
  1873. 0xFF, 0x00);
  1874. snd_soc_component_update_bits(component,
  1875. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6,
  1876. 0xFF, 0x00);
  1877. snd_soc_component_update_bits(component,
  1878. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7,
  1879. 0xFF, 0x00);
  1880. snd_soc_component_update_bits(component,
  1881. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8,
  1882. 0xFF, 0x00);
  1883. snd_soc_component_update_bits(component,
  1884. LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9,
  1885. 0xFF, 0x00);
  1886. lpass_cdc_wsa2_macro_enable_softclip_clk(component, wsa2_priv,
  1887. softclip_path, false);
  1888. snd_soc_component_update_bits(component,
  1889. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x01, 0x00);
  1890. snd_soc_component_update_bits(component,
  1891. LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL, 0x10, 0x00);
  1892. break;
  1893. default:
  1894. dev_err_ratelimited(wsa2_dev, "%s: Invalid event %d\n", __func__, event);
  1895. break;
  1896. }
  1897. return 0;
  1898. }
  1899. static int lpass_cdc_wsa2_macro_enable_echo(struct snd_soc_dapm_widget *w,
  1900. struct snd_kcontrol *kcontrol,
  1901. int event)
  1902. {
  1903. struct snd_soc_component *component =
  1904. snd_soc_dapm_to_component(w->dapm);
  1905. struct device *wsa2_dev = NULL;
  1906. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1907. u16 val, ec_tx = 0, ec_hq_reg;
  1908. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1909. return -EINVAL;
  1910. dev_dbg(wsa2_dev, "%s %d %s\n", __func__, event, w->name);
  1911. val = snd_soc_component_read(component,
  1912. LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0);
  1913. if (!(strcmp(w->name, "WSA2 RX_MIX EC0_MUX")))
  1914. ec_tx = (val & 0x07) - 1;
  1915. else
  1916. ec_tx = ((val & 0x38) >> 0x3) - 1;
  1917. if (ec_tx < 0 || ec_tx >= (LPASS_CDC_WSA2_MACRO_RX1 + 1)) {
  1918. dev_err_ratelimited(wsa2_dev, "%s: EC mix control not set correctly\n",
  1919. __func__);
  1920. return -EINVAL;
  1921. }
  1922. if (wsa2_priv->ec_hq[ec_tx]) {
  1923. snd_soc_component_update_bits(component,
  1924. LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0,
  1925. 0x1 << ec_tx, 0x1 << ec_tx);
  1926. ec_hq_reg = LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL +
  1927. 0x40 * ec_tx;
  1928. snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
  1929. ec_hq_reg = LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0 +
  1930. 0x40 * ec_tx;
  1931. /* default set to 48k */
  1932. snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
  1933. }
  1934. return 0;
  1935. }
  1936. static int lpass_cdc_wsa2_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
  1937. struct snd_ctl_elem_value *ucontrol)
  1938. {
  1939. struct snd_soc_component *component =
  1940. snd_soc_kcontrol_component(kcontrol);
  1941. int ec_tx = ((struct soc_multi_mixer_control *)
  1942. kcontrol->private_value)->shift;
  1943. struct device *wsa2_dev = NULL;
  1944. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1945. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1946. return -EINVAL;
  1947. ucontrol->value.integer.value[0] = wsa2_priv->ec_hq[ec_tx];
  1948. return 0;
  1949. }
  1950. static int lpass_cdc_wsa2_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
  1951. struct snd_ctl_elem_value *ucontrol)
  1952. {
  1953. struct snd_soc_component *component =
  1954. snd_soc_kcontrol_component(kcontrol);
  1955. int ec_tx = ((struct soc_multi_mixer_control *)
  1956. kcontrol->private_value)->shift;
  1957. int value = ucontrol->value.integer.value[0];
  1958. struct device *wsa2_dev = NULL;
  1959. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1960. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1961. return -EINVAL;
  1962. dev_dbg(wsa2_dev, "%s: enable current %d, new %d\n",
  1963. __func__, wsa2_priv->ec_hq[ec_tx], value);
  1964. wsa2_priv->ec_hq[ec_tx] = value;
  1965. return 0;
  1966. }
  1967. static int lpass_cdc_wsa2_macro_get_rx_mute_status(struct snd_kcontrol *kcontrol,
  1968. struct snd_ctl_elem_value *ucontrol)
  1969. {
  1970. struct snd_soc_component *component =
  1971. snd_soc_kcontrol_component(kcontrol);
  1972. struct device *wsa2_dev = NULL;
  1973. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1974. int wsa2_rx_shift = ((struct soc_multi_mixer_control *)
  1975. kcontrol->private_value)->shift;
  1976. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1977. return -EINVAL;
  1978. ucontrol->value.integer.value[0] =
  1979. wsa2_priv->wsa2_digital_mute_status[wsa2_rx_shift];
  1980. return 0;
  1981. }
  1982. static int lpass_cdc_wsa2_macro_set_rx_mute_status(struct snd_kcontrol *kcontrol,
  1983. struct snd_ctl_elem_value *ucontrol)
  1984. {
  1985. struct snd_soc_component *component =
  1986. snd_soc_kcontrol_component(kcontrol);
  1987. struct device *wsa2_dev = NULL;
  1988. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  1989. int value = ucontrol->value.integer.value[0];
  1990. int wsa2_rx_shift = ((struct soc_multi_mixer_control *)
  1991. kcontrol->private_value)->shift;
  1992. int ret = 0;
  1993. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  1994. return -EINVAL;
  1995. pm_runtime_get_sync(wsa2_priv->dev);
  1996. switch (wsa2_rx_shift) {
  1997. case 0:
  1998. snd_soc_component_update_bits(component,
  1999. LPASS_CDC_WSA2_RX0_RX_PATH_CTL,
  2000. 0x10, value << 4);
  2001. break;
  2002. case 1:
  2003. snd_soc_component_update_bits(component,
  2004. LPASS_CDC_WSA2_RX1_RX_PATH_CTL,
  2005. 0x10, value << 4);
  2006. break;
  2007. case 2:
  2008. snd_soc_component_update_bits(component,
  2009. LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL,
  2010. 0x10, value << 4);
  2011. break;
  2012. case 3:
  2013. snd_soc_component_update_bits(component,
  2014. LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL,
  2015. 0x10, value << 4);
  2016. break;
  2017. default:
  2018. pr_err_ratelimited("%s: invalid argument rx_shift = %d\n", __func__,
  2019. wsa2_rx_shift);
  2020. ret = -EINVAL;
  2021. }
  2022. pm_runtime_mark_last_busy(wsa2_priv->dev);
  2023. pm_runtime_put_autosuspend(wsa2_priv->dev);
  2024. dev_dbg(component->dev, "%s: WSA2 Digital Mute RX %d Enable %d\n",
  2025. __func__, wsa2_rx_shift, value);
  2026. wsa2_priv->wsa2_digital_mute_status[wsa2_rx_shift] = value;
  2027. return ret;
  2028. }
  2029. static int lpass_cdc_wsa2_macro_set_digital_volume(struct snd_kcontrol *kcontrol,
  2030. struct snd_ctl_elem_value *ucontrol)
  2031. {
  2032. struct snd_soc_component *component =
  2033. snd_soc_kcontrol_component(kcontrol);
  2034. struct device *wsa2_dev = NULL;
  2035. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2036. struct soc_mixer_control *mc =
  2037. (struct soc_mixer_control *)kcontrol->private_value;
  2038. u8 gain = 0;
  2039. int ret = 0;
  2040. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2041. return -EINVAL;
  2042. if (!wsa2_priv) {
  2043. pr_err_ratelimited("%s: priv is null for macro!\n",
  2044. __func__);
  2045. return -EINVAL;
  2046. }
  2047. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  2048. if (mc->reg == LPASS_CDC_WSA2_RX0_RX_VOL_CTL) {
  2049. wsa2_priv->rx0_origin_gain =
  2050. (u8)snd_soc_component_read(wsa2_priv->component,
  2051. mc->reg);
  2052. gain = (u8)(wsa2_priv->rx0_origin_gain -
  2053. wsa2_priv->thermal_cur_state);
  2054. } else if (mc->reg == LPASS_CDC_WSA2_RX1_RX_VOL_CTL) {
  2055. wsa2_priv->rx1_origin_gain =
  2056. (u8)snd_soc_component_read(wsa2_priv->component,
  2057. mc->reg);
  2058. gain = (u8)(wsa2_priv->rx1_origin_gain -
  2059. wsa2_priv->thermal_cur_state);
  2060. } else {
  2061. dev_err_ratelimited(wsa2_priv->dev,
  2062. "%s: Incorrect RX Path selected\n", __func__);
  2063. return -EINVAL;
  2064. }
  2065. /* only adjust gain if thermal state is positive */
  2066. if (wsa2_priv->dapm_mclk_enable &&
  2067. wsa2_priv->thermal_cur_state > 0) {
  2068. snd_soc_component_update_bits(wsa2_priv->component,
  2069. mc->reg, 0xFF, gain);
  2070. dev_dbg(wsa2_priv->dev,
  2071. "%s: Current thermal state: %d, adjusted gain: %x\n",
  2072. __func__, wsa2_priv->thermal_cur_state, gain);
  2073. }
  2074. return ret;
  2075. }
  2076. static int lpass_cdc_wsa2_macro_get_compander(struct snd_kcontrol *kcontrol,
  2077. struct snd_ctl_elem_value *ucontrol)
  2078. {
  2079. struct snd_soc_component *component =
  2080. snd_soc_kcontrol_component(kcontrol);
  2081. int comp = ((struct soc_multi_mixer_control *)
  2082. kcontrol->private_value)->shift;
  2083. struct device *wsa2_dev = NULL;
  2084. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2085. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2086. return -EINVAL;
  2087. ucontrol->value.integer.value[0] = wsa2_priv->comp_enabled[comp];
  2088. return 0;
  2089. }
  2090. static int lpass_cdc_wsa2_macro_set_compander(struct snd_kcontrol *kcontrol,
  2091. struct snd_ctl_elem_value *ucontrol)
  2092. {
  2093. struct snd_soc_component *component =
  2094. snd_soc_kcontrol_component(kcontrol);
  2095. int comp = ((struct soc_multi_mixer_control *)
  2096. kcontrol->private_value)->shift;
  2097. int value = ucontrol->value.integer.value[0];
  2098. struct device *wsa2_dev = NULL;
  2099. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2100. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2101. return -EINVAL;
  2102. dev_dbg(component->dev, "%s: Compander %d enable current %d, new %d\n",
  2103. __func__, comp + 1, wsa2_priv->comp_enabled[comp], value);
  2104. wsa2_priv->comp_enabled[comp] = value;
  2105. return 0;
  2106. }
  2107. static int lpass_cdc_wsa2_macro_ear_spkrrecv_get(struct snd_kcontrol *kcontrol,
  2108. struct snd_ctl_elem_value *ucontrol)
  2109. {
  2110. struct snd_soc_component *component =
  2111. snd_soc_kcontrol_component(kcontrol);
  2112. struct device *wsa2_dev = NULL;
  2113. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2114. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2115. return -EINVAL;
  2116. ucontrol->value.integer.value[0] = wsa2_priv->wsa2_spkrrecv;
  2117. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2118. __func__, ucontrol->value.integer.value[0]);
  2119. return 0;
  2120. }
  2121. static int lpass_cdc_wsa2_macro_ear_spkrrecv_put(struct snd_kcontrol *kcontrol,
  2122. struct snd_ctl_elem_value *ucontrol)
  2123. {
  2124. struct snd_soc_component *component =
  2125. snd_soc_kcontrol_component(kcontrol);
  2126. struct device *wsa2_dev = NULL;
  2127. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2128. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2129. return -EINVAL;
  2130. wsa2_priv->wsa2_spkrrecv = ucontrol->value.integer.value[0];
  2131. dev_dbg(component->dev, "%s:spkrrecv status = %d\n",
  2132. __func__, wsa2_priv->wsa2_spkrrecv);
  2133. return 0;
  2134. }
  2135. static int lpass_cdc_wsa2_macro_idle_detect_get(struct snd_kcontrol *kcontrol,
  2136. struct snd_ctl_elem_value *ucontrol)
  2137. {
  2138. struct snd_soc_component *component =
  2139. snd_soc_kcontrol_component(kcontrol);
  2140. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2141. struct device *wsa2_dev = NULL;
  2142. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2143. return -EINVAL;
  2144. ucontrol->value.integer.value[0] = wsa2_priv->idle_detect_en;
  2145. return 0;
  2146. }
  2147. static int lpass_cdc_wsa2_macro_idle_detect_put(struct snd_kcontrol *kcontrol,
  2148. struct snd_ctl_elem_value *ucontrol)
  2149. {
  2150. struct snd_soc_component *component =
  2151. snd_soc_kcontrol_component(kcontrol);
  2152. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2153. struct device *wsa2_dev = NULL;
  2154. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2155. return -EINVAL;
  2156. wsa2_priv->idle_detect_en = ucontrol->value.integer.value[0];
  2157. return 0;
  2158. }
  2159. static int lpass_cdc_wsa2_macro_comp_mode_get(struct snd_kcontrol *kcontrol,
  2160. struct snd_ctl_elem_value *ucontrol)
  2161. {
  2162. struct snd_soc_component *component =
  2163. snd_soc_kcontrol_component(kcontrol);
  2164. struct device *wsa2_dev = NULL;
  2165. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2166. u16 idx = 0;
  2167. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2168. return -EINVAL;
  2169. if (strnstr(kcontrol->id.name, "RX0", sizeof("WSA2_RX0")))
  2170. idx = LPASS_CDC_WSA2_MACRO_COMP1;
  2171. if (strnstr(kcontrol->id.name, "RX1", sizeof("WSA2_RX1")))
  2172. idx = LPASS_CDC_WSA2_MACRO_COMP2;
  2173. ucontrol->value.integer.value[0] = wsa2_priv->comp_mode[idx];
  2174. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2175. __func__, ucontrol->value.integer.value[0]);
  2176. return 0;
  2177. }
  2178. static int lpass_cdc_wsa2_macro_comp_mode_put(struct snd_kcontrol *kcontrol,
  2179. struct snd_ctl_elem_value *ucontrol)
  2180. {
  2181. struct snd_soc_component *component =
  2182. snd_soc_kcontrol_component(kcontrol);
  2183. struct device *wsa2_dev = NULL;
  2184. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2185. u16 idx = 0;
  2186. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2187. return -EINVAL;
  2188. if (strnstr(kcontrol->id.name, "RX0", sizeof("WSA2_RX0")))
  2189. idx = LPASS_CDC_WSA2_MACRO_COMP1;
  2190. if (strnstr(kcontrol->id.name, "RX1", sizeof("WSA2_RX1")))
  2191. idx = LPASS_CDC_WSA2_MACRO_COMP2;
  2192. if (ucontrol->value.integer.value[0] < G_MAX_DB &&
  2193. ucontrol->value.integer.value[0] >= 0)
  2194. wsa2_priv->comp_mode[idx] = ucontrol->value.integer.value[0];
  2195. else
  2196. return 0;
  2197. dev_dbg(component->dev, "%s: comp_mode = %d\n", __func__,
  2198. wsa2_priv->comp_mode[idx]);
  2199. return 0;
  2200. }
  2201. static int lpass_cdc_wsa2_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
  2202. struct snd_ctl_elem_value *ucontrol)
  2203. {
  2204. struct snd_soc_dapm_widget *widget =
  2205. snd_soc_dapm_kcontrol_widget(kcontrol);
  2206. struct snd_soc_component *component =
  2207. snd_soc_dapm_to_component(widget->dapm);
  2208. struct device *wsa2_dev = NULL;
  2209. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2210. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2211. return -EINVAL;
  2212. ucontrol->value.integer.value[0] =
  2213. wsa2_priv->rx_port_value[widget->shift];
  2214. return 0;
  2215. }
  2216. static int lpass_cdc_wsa2_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
  2217. struct snd_ctl_elem_value *ucontrol)
  2218. {
  2219. struct snd_soc_dapm_widget *widget =
  2220. snd_soc_dapm_kcontrol_widget(kcontrol);
  2221. struct snd_soc_component *component =
  2222. snd_soc_dapm_to_component(widget->dapm);
  2223. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  2224. struct snd_soc_dapm_update *update = NULL;
  2225. u32 rx_port_value = ucontrol->value.integer.value[0];
  2226. u32 bit_input = 0;
  2227. u32 aif_rst;
  2228. struct device *wsa2_dev = NULL;
  2229. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2230. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2231. return -EINVAL;
  2232. aif_rst = wsa2_priv->rx_port_value[widget->shift];
  2233. if (!rx_port_value) {
  2234. if (aif_rst == 0) {
  2235. dev_err_ratelimited(wsa2_dev, "%s: AIF reset already\n", __func__);
  2236. return 0;
  2237. }
  2238. if (aif_rst >= LPASS_CDC_WSA2_MACRO_MAX_DAIS) {
  2239. dev_err_ratelimited(wsa2_dev, "%s: Invalid AIF reset\n", __func__);
  2240. return 0;
  2241. }
  2242. }
  2243. wsa2_priv->rx_port_value[widget->shift] = rx_port_value;
  2244. bit_input = widget->shift;
  2245. dev_dbg(wsa2_dev,
  2246. "%s: mux input: %d, mux output: %d, bit: %d\n",
  2247. __func__, rx_port_value, widget->shift, bit_input);
  2248. switch (rx_port_value) {
  2249. case 0:
  2250. if (wsa2_priv->active_ch_cnt[aif_rst]) {
  2251. clear_bit(bit_input,
  2252. &wsa2_priv->active_ch_mask[aif_rst]);
  2253. wsa2_priv->active_ch_cnt[aif_rst]--;
  2254. }
  2255. break;
  2256. case 1:
  2257. case 2:
  2258. set_bit(bit_input,
  2259. &wsa2_priv->active_ch_mask[rx_port_value]);
  2260. wsa2_priv->active_ch_cnt[rx_port_value]++;
  2261. break;
  2262. default:
  2263. dev_err_ratelimited(wsa2_dev,
  2264. "%s: Invalid AIF_ID for WSA2 RX MUX %d\n",
  2265. __func__, rx_port_value);
  2266. return -EINVAL;
  2267. }
  2268. snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
  2269. rx_port_value, e, update);
  2270. return 0;
  2271. }
  2272. static int lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_get(struct snd_kcontrol *kcontrol,
  2273. struct snd_ctl_elem_value *ucontrol)
  2274. {
  2275. struct snd_soc_component *component =
  2276. snd_soc_kcontrol_component(kcontrol);
  2277. ucontrol->value.integer.value[0] =
  2278. ((snd_soc_component_read(
  2279. component, LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG) & 0x04) ?
  2280. 1 : 0);
  2281. dev_dbg(component->dev, "%s: value: %lu\n", __func__,
  2282. ucontrol->value.integer.value[0]);
  2283. return 0;
  2284. }
  2285. static int lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_put(struct snd_kcontrol *kcontrol,
  2286. struct snd_ctl_elem_value *ucontrol)
  2287. {
  2288. struct snd_soc_component *component =
  2289. snd_soc_kcontrol_component(kcontrol);
  2290. dev_dbg(component->dev, "%s: value: %lu\n", __func__,
  2291. ucontrol->value.integer.value[0]);
  2292. /* Set Vbat register configuration for GSM mode bit based on value */
  2293. if (ucontrol->value.integer.value[0])
  2294. snd_soc_component_update_bits(component,
  2295. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG,
  2296. 0x04, 0x04);
  2297. else
  2298. snd_soc_component_update_bits(component,
  2299. LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG,
  2300. 0x04, 0x00);
  2301. return 0;
  2302. }
  2303. static int lpass_cdc_wsa2_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
  2304. struct snd_ctl_elem_value *ucontrol)
  2305. {
  2306. struct snd_soc_component *component =
  2307. snd_soc_kcontrol_component(kcontrol);
  2308. struct device *wsa2_dev = NULL;
  2309. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2310. int path = ((struct soc_multi_mixer_control *)
  2311. kcontrol->private_value)->shift;
  2312. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2313. return -EINVAL;
  2314. ucontrol->value.integer.value[0] = wsa2_priv->is_softclip_on[path];
  2315. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2316. __func__, ucontrol->value.integer.value[0]);
  2317. return 0;
  2318. }
  2319. static int lpass_cdc_wsa2_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
  2320. struct snd_ctl_elem_value *ucontrol)
  2321. {
  2322. struct snd_soc_component *component =
  2323. snd_soc_kcontrol_component(kcontrol);
  2324. struct device *wsa2_dev = NULL;
  2325. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2326. int path = ((struct soc_multi_mixer_control *)
  2327. kcontrol->private_value)->shift;
  2328. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2329. return -EINVAL;
  2330. wsa2_priv->is_softclip_on[path] = ucontrol->value.integer.value[0];
  2331. dev_dbg(component->dev, "%s: soft clip enable for %d: %d\n", __func__,
  2332. path, wsa2_priv->is_softclip_on[path]);
  2333. return 0;
  2334. }
  2335. static int lpass_cdc_wsa2_macro_pbr_enable_get(struct snd_kcontrol *kcontrol,
  2336. struct snd_ctl_elem_value *ucontrol)
  2337. {
  2338. struct snd_soc_component *component =
  2339. snd_soc_kcontrol_component(kcontrol);
  2340. struct device *wsa2_dev = NULL;
  2341. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2342. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2343. return -EINVAL;
  2344. ucontrol->value.integer.value[0] = wsa2_priv->pbr_enable;
  2345. return 0;
  2346. }
  2347. static int lpass_cdc_wsa2_macro_pbr_enable_put(struct snd_kcontrol *kcontrol,
  2348. struct snd_ctl_elem_value *ucontrol)
  2349. {
  2350. struct snd_soc_component *component =
  2351. snd_soc_kcontrol_component(kcontrol);
  2352. struct device *wsa2_dev = NULL;
  2353. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2354. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2355. return -EINVAL;
  2356. wsa2_priv->pbr_enable = ucontrol->value.integer.value[0];
  2357. return 0;
  2358. }
  2359. static int lpass_cdc_wsa2_macro_2ch_dma_enable_get(struct snd_kcontrol *kcontrol,
  2360. struct snd_ctl_elem_value *ucontrol)
  2361. {
  2362. struct snd_soc_component *component =
  2363. snd_soc_kcontrol_component(kcontrol);
  2364. struct device *wsa2_dev = NULL;
  2365. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2366. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2367. return -EINVAL;
  2368. ucontrol->value.integer.value[0] = wsa2_priv->wsa2_2ch_dma_enable;
  2369. return 0;
  2370. }
  2371. static int lpass_cdc_wsa2_macro_2ch_dma_enable_put(struct snd_kcontrol *kcontrol,
  2372. struct snd_ctl_elem_value *ucontrol)
  2373. {
  2374. struct snd_soc_component *component =
  2375. snd_soc_kcontrol_component(kcontrol);
  2376. struct device *wsa2_dev = NULL;
  2377. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2378. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2379. return -EINVAL;
  2380. wsa2_priv->wsa2_2ch_dma_enable = ucontrol->value.integer.value[0];
  2381. return 0;
  2382. }
  2383. static const struct snd_kcontrol_new lpass_cdc_wsa2_macro_snd_controls[] = {
  2384. SOC_ENUM_EXT("WSA2_GSM mode Enable", lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_enum,
  2385. lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_get,
  2386. lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_put),
  2387. SOC_ENUM_EXT("WSA2_RX0 comp_mode", lpass_cdc_wsa2_macro_comp_mode_enum,
  2388. lpass_cdc_wsa2_macro_comp_mode_get,
  2389. lpass_cdc_wsa2_macro_comp_mode_put),
  2390. SOC_ENUM_EXT("WSA2_RX1 comp_mode", lpass_cdc_wsa2_macro_comp_mode_enum,
  2391. lpass_cdc_wsa2_macro_comp_mode_get,
  2392. lpass_cdc_wsa2_macro_comp_mode_put),
  2393. SOC_SINGLE_EXT("WSA2 SPKRRECV", SND_SOC_NOPM, 0, 1, 0,
  2394. lpass_cdc_wsa2_macro_ear_spkrrecv_get,
  2395. lpass_cdc_wsa2_macro_ear_spkrrecv_put),
  2396. SOC_SINGLE_EXT("WSA2 Idle Detect", SND_SOC_NOPM, 0, 1,
  2397. 0, lpass_cdc_wsa2_macro_idle_detect_get,
  2398. lpass_cdc_wsa2_macro_idle_detect_put),
  2399. SOC_SINGLE_EXT("WSA2_Softclip0 Enable", SND_SOC_NOPM,
  2400. LPASS_CDC_WSA2_MACRO_SOFTCLIP0, 1, 0,
  2401. lpass_cdc_wsa2_macro_soft_clip_enable_get,
  2402. lpass_cdc_wsa2_macro_soft_clip_enable_put),
  2403. SOC_SINGLE_EXT("WSA2_Softclip1 Enable", SND_SOC_NOPM,
  2404. LPASS_CDC_WSA2_MACRO_SOFTCLIP1, 1, 0,
  2405. lpass_cdc_wsa2_macro_soft_clip_enable_get,
  2406. lpass_cdc_wsa2_macro_soft_clip_enable_put),
  2407. LPASS_CDC_WSA2_MACRO_SET_VOLUME_TLV("WSA2_RX0 Digital Volume",
  2408. LPASS_CDC_WSA2_RX0_RX_VOL_CTL,
  2409. -84, 40, digital_gain),
  2410. LPASS_CDC_WSA2_MACRO_SET_VOLUME_TLV("WSA2_RX1 Digital Volume",
  2411. LPASS_CDC_WSA2_RX1_RX_VOL_CTL,
  2412. -84, 40, digital_gain),
  2413. SOC_SINGLE_EXT("WSA2_RX0 Digital Mute", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX0, 1,
  2414. 0, lpass_cdc_wsa2_macro_get_rx_mute_status,
  2415. lpass_cdc_wsa2_macro_set_rx_mute_status),
  2416. SOC_SINGLE_EXT("WSA2_RX1 Digital Mute", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX1, 1,
  2417. 0, lpass_cdc_wsa2_macro_get_rx_mute_status,
  2418. lpass_cdc_wsa2_macro_set_rx_mute_status),
  2419. SOC_SINGLE_EXT("WSA2_RX0_MIX Digital Mute", SND_SOC_NOPM,
  2420. LPASS_CDC_WSA2_MACRO_RX_MIX0, 1, 0, lpass_cdc_wsa2_macro_get_rx_mute_status,
  2421. lpass_cdc_wsa2_macro_set_rx_mute_status),
  2422. SOC_SINGLE_EXT("WSA2_RX1_MIX Digital Mute", SND_SOC_NOPM,
  2423. LPASS_CDC_WSA2_MACRO_RX_MIX1, 1, 0, lpass_cdc_wsa2_macro_get_rx_mute_status,
  2424. lpass_cdc_wsa2_macro_set_rx_mute_status),
  2425. SOC_SINGLE_EXT("WSA2_COMP1 Switch", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_COMP1, 1, 0,
  2426. lpass_cdc_wsa2_macro_get_compander, lpass_cdc_wsa2_macro_set_compander),
  2427. SOC_SINGLE_EXT("WSA2_COMP2 Switch", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_COMP2, 1, 0,
  2428. lpass_cdc_wsa2_macro_get_compander, lpass_cdc_wsa2_macro_set_compander),
  2429. SOC_SINGLE_EXT("WSA2_RX0 EC_HQ Switch", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX0,
  2430. 1, 0, lpass_cdc_wsa2_macro_get_ec_hq, lpass_cdc_wsa2_macro_set_ec_hq),
  2431. SOC_SINGLE_EXT("WSA2_RX1 EC_HQ Switch", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX1,
  2432. 1, 0, lpass_cdc_wsa2_macro_get_ec_hq, lpass_cdc_wsa2_macro_set_ec_hq),
  2433. SOC_SINGLE_EXT("WSA2 PBR Enable", SND_SOC_NOPM, 0, 1,
  2434. 0, lpass_cdc_wsa2_macro_pbr_enable_get,
  2435. lpass_cdc_wsa2_macro_pbr_enable_put),
  2436. SOC_SINGLE_EXT("WSA2 2CH_DMA ENABLE", SND_SOC_NOPM, 0, 1,
  2437. 0, lpass_cdc_wsa2_macro_2ch_dma_enable_get,
  2438. lpass_cdc_wsa2_macro_2ch_dma_enable_put),
  2439. };
  2440. static const struct soc_enum rx_mux_enum =
  2441. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
  2442. static const struct snd_kcontrol_new rx_mux[LPASS_CDC_WSA2_MACRO_RX_MAX] = {
  2443. SOC_DAPM_ENUM_EXT("WSA2 RX0 Mux", rx_mux_enum,
  2444. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2445. SOC_DAPM_ENUM_EXT("WSA2 RX1 Mux", rx_mux_enum,
  2446. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2447. SOC_DAPM_ENUM_EXT("WSA2 RX_MIX0 Mux", rx_mux_enum,
  2448. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2449. SOC_DAPM_ENUM_EXT("WSA2 RX_MIX1 Mux", rx_mux_enum,
  2450. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2451. SOC_DAPM_ENUM_EXT("WSA2 RX4 Mux", rx_mux_enum,
  2452. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2453. SOC_DAPM_ENUM_EXT("WSA2 RX5 Mux", rx_mux_enum,
  2454. lpass_cdc_wsa2_macro_rx_mux_get, lpass_cdc_wsa2_macro_rx_mux_put),
  2455. };
  2456. static int lpass_cdc_wsa2_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
  2457. struct snd_ctl_elem_value *ucontrol)
  2458. {
  2459. struct snd_soc_dapm_widget *widget =
  2460. snd_soc_dapm_kcontrol_widget(kcontrol);
  2461. struct snd_soc_component *component =
  2462. snd_soc_dapm_to_component(widget->dapm);
  2463. struct soc_multi_mixer_control *mixer =
  2464. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  2465. u32 dai_id = widget->shift;
  2466. u32 spk_tx_id = mixer->shift;
  2467. struct device *wsa2_dev = NULL;
  2468. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2469. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2470. return -EINVAL;
  2471. if (test_bit(spk_tx_id, &wsa2_priv->active_ch_mask[dai_id]))
  2472. ucontrol->value.integer.value[0] = 1;
  2473. else
  2474. ucontrol->value.integer.value[0] = 0;
  2475. return 0;
  2476. }
  2477. static int lpass_cdc_wsa2_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
  2478. struct snd_ctl_elem_value *ucontrol)
  2479. {
  2480. struct snd_soc_dapm_widget *widget =
  2481. snd_soc_dapm_kcontrol_widget(kcontrol);
  2482. struct snd_soc_component *component =
  2483. snd_soc_dapm_to_component(widget->dapm);
  2484. struct soc_multi_mixer_control *mixer =
  2485. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  2486. u32 spk_tx_id = mixer->shift;
  2487. u32 enable = ucontrol->value.integer.value[0];
  2488. struct device *wsa2_dev = NULL;
  2489. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2490. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2491. return -EINVAL;
  2492. wsa2_priv->vi_feed_value = ucontrol->value.integer.value[0];
  2493. if (enable) {
  2494. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX0 &&
  2495. !test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2496. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  2497. set_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2498. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI]);
  2499. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_VI]++;
  2500. }
  2501. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX1 &&
  2502. !test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2503. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  2504. set_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2505. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI]);
  2506. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_VI]++;
  2507. }
  2508. } else {
  2509. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX0 &&
  2510. test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2511. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  2512. clear_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2513. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI]);
  2514. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_VI]--;
  2515. }
  2516. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX1 &&
  2517. test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2518. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI])) {
  2519. clear_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2520. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_VI]);
  2521. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_VI]--;
  2522. }
  2523. }
  2524. snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
  2525. return 0;
  2526. }
  2527. static const struct snd_kcontrol_new aif_vi_mixer[] = {
  2528. SOC_SINGLE_EXT("WSA2_SPKR_VI_1", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_TX0, 1, 0,
  2529. lpass_cdc_wsa2_macro_vi_feed_mixer_get,
  2530. lpass_cdc_wsa2_macro_vi_feed_mixer_put),
  2531. SOC_SINGLE_EXT("WSA2_SPKR_VI_2", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_TX1, 1, 0,
  2532. lpass_cdc_wsa2_macro_vi_feed_mixer_get,
  2533. lpass_cdc_wsa2_macro_vi_feed_mixer_put),
  2534. };
  2535. static int lpass_cdc_wsa2_macro_cps_feed_mixer_get(struct snd_kcontrol *kcontrol,
  2536. struct snd_ctl_elem_value *ucontrol)
  2537. {
  2538. struct snd_soc_dapm_widget *widget =
  2539. snd_soc_dapm_kcontrol_widget(kcontrol);
  2540. struct snd_soc_component *component =
  2541. snd_soc_dapm_to_component(widget->dapm);
  2542. struct soc_multi_mixer_control *mixer =
  2543. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  2544. u32 dai_id = widget->shift;
  2545. u32 spk_tx_id = mixer->shift;
  2546. struct device *wsa2_dev = NULL;
  2547. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2548. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2549. return -EINVAL;
  2550. if (test_bit(spk_tx_id, &wsa2_priv->active_ch_mask[dai_id]))
  2551. ucontrol->value.integer.value[0] = 1;
  2552. else
  2553. ucontrol->value.integer.value[0] = 0;
  2554. return 0;
  2555. }
  2556. static int lpass_cdc_wsa2_macro_cps_feed_mixer_put(struct snd_kcontrol *kcontrol,
  2557. struct snd_ctl_elem_value *ucontrol)
  2558. {
  2559. struct snd_soc_dapm_widget *widget =
  2560. snd_soc_dapm_kcontrol_widget(kcontrol);
  2561. struct snd_soc_component *component =
  2562. snd_soc_dapm_to_component(widget->dapm);
  2563. struct soc_multi_mixer_control *mixer =
  2564. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  2565. u32 spk_tx_id = mixer->shift;
  2566. u32 enable = ucontrol->value.integer.value[0];
  2567. struct device *wsa2_dev = NULL;
  2568. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2569. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2570. return -EINVAL;
  2571. if (enable) {
  2572. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX0 &&
  2573. !test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2574. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS])) {
  2575. set_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2576. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS]);
  2577. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_CPS]++;
  2578. }
  2579. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX1 &&
  2580. !test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2581. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS])) {
  2582. set_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2583. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS]);
  2584. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_CPS]++;
  2585. }
  2586. } else {
  2587. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX0 &&
  2588. test_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2589. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS])) {
  2590. clear_bit(LPASS_CDC_WSA2_MACRO_TX0,
  2591. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS]);
  2592. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_CPS]--;
  2593. }
  2594. if (spk_tx_id == LPASS_CDC_WSA2_MACRO_TX1 &&
  2595. test_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2596. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS])) {
  2597. clear_bit(LPASS_CDC_WSA2_MACRO_TX1,
  2598. &wsa2_priv->active_ch_mask[LPASS_CDC_WSA2_MACRO_AIF_CPS]);
  2599. wsa2_priv->active_ch_cnt[LPASS_CDC_WSA2_MACRO_AIF_CPS]--;
  2600. }
  2601. }
  2602. snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
  2603. return 0;
  2604. }
  2605. static const struct snd_kcontrol_new aif_cps_mixer[] = {
  2606. SOC_SINGLE_EXT("WSA2_SPKR_CPS_1", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_TX0, 1, 0,
  2607. lpass_cdc_wsa2_macro_cps_feed_mixer_get,
  2608. lpass_cdc_wsa2_macro_cps_feed_mixer_put),
  2609. SOC_SINGLE_EXT("WSA2_SPKR_CPS_2", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_TX1, 1, 0,
  2610. lpass_cdc_wsa2_macro_cps_feed_mixer_get,
  2611. lpass_cdc_wsa2_macro_cps_feed_mixer_put),
  2612. };
  2613. static const struct snd_soc_dapm_widget lpass_cdc_wsa2_macro_dapm_widgets[] = {
  2614. SND_SOC_DAPM_AIF_IN("WSA2 AIF1 PB", "WSA2_AIF1 Playback", 0,
  2615. SND_SOC_NOPM, 0, 0),
  2616. SND_SOC_DAPM_AIF_IN("WSA2 AIF_MIX1 PB", "WSA2_AIF_MIX1 Playback", 0,
  2617. SND_SOC_NOPM, 0, 0),
  2618. SND_SOC_DAPM_AIF_OUT_E("WSA2 AIF_VI", "WSA2_AIF_VI Capture", 0,
  2619. SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_AIF_VI, 0,
  2620. lpass_cdc_wsa2_macro_disable_vi_feedback,
  2621. SND_SOC_DAPM_POST_PMD),
  2622. SND_SOC_DAPM_AIF_OUT("WSA2 AIF_ECHO", "WSA2_AIF_ECHO Capture", 0,
  2623. SND_SOC_NOPM, 0, 0),
  2624. SND_SOC_DAPM_AIF_OUT("WSA2 AIF_CPS", "WSA2_AIF_CPS Capture", 0,
  2625. SND_SOC_NOPM, 0, 0),
  2626. SND_SOC_DAPM_MIXER("WSA2_AIF_VI Mixer", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_AIF_VI,
  2627. 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
  2628. SND_SOC_DAPM_MIXER("WSA2_AIF_CPS Mixer", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_AIF_CPS,
  2629. 0, aif_cps_mixer, ARRAY_SIZE(aif_cps_mixer)),
  2630. SND_SOC_DAPM_MUX_E("WSA2 RX_MIX EC0_MUX", SND_SOC_NOPM,
  2631. LPASS_CDC_WSA2_MACRO_EC0_MUX, 0,
  2632. &rx_mix_ec0_mux, lpass_cdc_wsa2_macro_enable_echo,
  2633. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2634. SND_SOC_DAPM_MUX_E("WSA2 RX_MIX EC1_MUX", SND_SOC_NOPM,
  2635. LPASS_CDC_WSA2_MACRO_EC1_MUX, 0,
  2636. &rx_mix_ec1_mux, lpass_cdc_wsa2_macro_enable_echo,
  2637. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2638. SND_SOC_DAPM_MUX("WSA2 RX0 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX0, 0,
  2639. &rx_mux[LPASS_CDC_WSA2_MACRO_RX0]),
  2640. SND_SOC_DAPM_MUX("WSA2 RX1 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX1, 0,
  2641. &rx_mux[LPASS_CDC_WSA2_MACRO_RX1]),
  2642. SND_SOC_DAPM_MUX("WSA2 RX_MIX0 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX_MIX0, 0,
  2643. &rx_mux[LPASS_CDC_WSA2_MACRO_RX_MIX0]),
  2644. SND_SOC_DAPM_MUX("WSA2 RX_MIX1 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX_MIX1, 0,
  2645. &rx_mux[LPASS_CDC_WSA2_MACRO_RX_MIX1]),
  2646. SND_SOC_DAPM_MUX("WSA2 RX4 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX4, 0,
  2647. &rx_mux[LPASS_CDC_WSA2_MACRO_RX4]),
  2648. SND_SOC_DAPM_MUX("WSA2 RX5 MUX", SND_SOC_NOPM, LPASS_CDC_WSA2_MACRO_RX5, 0,
  2649. &rx_mux[LPASS_CDC_WSA2_MACRO_RX5]),
  2650. SND_SOC_DAPM_MIXER("WSA2 RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
  2651. SND_SOC_DAPM_MIXER("WSA2 RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2652. SND_SOC_DAPM_MIXER("WSA2 RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
  2653. SND_SOC_DAPM_MIXER("WSA2 RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2654. SND_SOC_DAPM_MIXER("WSA2 RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2655. SND_SOC_DAPM_MIXER("WSA2 RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
  2656. SND_SOC_DAPM_MUX_E("WSA2_RX0 INP0", SND_SOC_NOPM, 0, 0,
  2657. &rx0_prim_inp0_mux, lpass_cdc_wsa2_macro_enable_swr,
  2658. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2659. SND_SOC_DAPM_MUX_E("WSA2_RX0 INP1", SND_SOC_NOPM, 0, 0,
  2660. &rx0_prim_inp1_mux, lpass_cdc_wsa2_macro_enable_swr,
  2661. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2662. SND_SOC_DAPM_MUX_E("WSA2_RX0 INP2", SND_SOC_NOPM, 0, 0,
  2663. &rx0_prim_inp2_mux, lpass_cdc_wsa2_macro_enable_swr,
  2664. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2665. SND_SOC_DAPM_MUX_E("WSA2_RX0 MIX INP", SND_SOC_NOPM,
  2666. 0, 0, &rx0_mix_mux, lpass_cdc_wsa2_macro_enable_mix_path,
  2667. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2668. SND_SOC_DAPM_MUX_E("WSA2_RX1 INP0", SND_SOC_NOPM, 0, 0,
  2669. &rx1_prim_inp0_mux, lpass_cdc_wsa2_macro_enable_swr,
  2670. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2671. SND_SOC_DAPM_MUX_E("WSA2_RX1 INP1", SND_SOC_NOPM, 0, 0,
  2672. &rx1_prim_inp1_mux, lpass_cdc_wsa2_macro_enable_swr,
  2673. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2674. SND_SOC_DAPM_MUX_E("WSA2_RX1 INP2", SND_SOC_NOPM, 0, 0,
  2675. &rx1_prim_inp2_mux, lpass_cdc_wsa2_macro_enable_swr,
  2676. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2677. SND_SOC_DAPM_MUX_E("WSA2_RX1 MIX INP", SND_SOC_NOPM,
  2678. 0, 0, &rx1_mix_mux, lpass_cdc_wsa2_macro_enable_mix_path,
  2679. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2680. SND_SOC_DAPM_PGA_E("WSA2_RX INT0 MIX", SND_SOC_NOPM,
  2681. 0, 0, NULL, 0, lpass_cdc_wsa2_macro_enable_main_path,
  2682. SND_SOC_DAPM_PRE_PMU),
  2683. SND_SOC_DAPM_PGA_E("WSA2_RX INT1 MIX", SND_SOC_NOPM,
  2684. 1, 0, NULL, 0, lpass_cdc_wsa2_macro_enable_main_path,
  2685. SND_SOC_DAPM_PRE_PMU),
  2686. SND_SOC_DAPM_MIXER("WSA2_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2687. SND_SOC_DAPM_MIXER("WSA2_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2688. SND_SOC_DAPM_MUX_E("WSA2_RX0 INT0 SIDETONE MIX",
  2689. LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 4, 0,
  2690. &rx0_sidetone_mix_mux, lpass_cdc_wsa2_macro_enable_swr,
  2691. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2692. SND_SOC_DAPM_INPUT("WSA2 SRC0_INP"),
  2693. SND_SOC_DAPM_INPUT("WSA2_TX DEC0_INP"),
  2694. SND_SOC_DAPM_INPUT("WSA2_TX DEC1_INP"),
  2695. SND_SOC_DAPM_MIXER_E("WSA2_RX INT0 INTERP", SND_SOC_NOPM,
  2696. LPASS_CDC_WSA2_MACRO_COMP1, 0, NULL, 0, lpass_cdc_wsa2_macro_enable_interpolator,
  2697. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2698. SND_SOC_DAPM_POST_PMD),
  2699. SND_SOC_DAPM_MIXER_E("WSA2_RX INT1 INTERP", SND_SOC_NOPM,
  2700. LPASS_CDC_WSA2_MACRO_COMP2, 0, NULL, 0, lpass_cdc_wsa2_macro_enable_interpolator,
  2701. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2702. SND_SOC_DAPM_POST_PMD),
  2703. SND_SOC_DAPM_MIXER_E("WSA2_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
  2704. NULL, 0, lpass_cdc_wsa2_macro_spk_boost_event,
  2705. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2706. SND_SOC_DAPM_POST_PMD),
  2707. SND_SOC_DAPM_MIXER_E("WSA2_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
  2708. NULL, 0, lpass_cdc_wsa2_macro_spk_boost_event,
  2709. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2710. SND_SOC_DAPM_POST_PMD),
  2711. SND_SOC_DAPM_MIXER_E("WSA2_RX INT0 VBAT", SND_SOC_NOPM,
  2712. 0, 0, wsa2_int0_vbat_mix_switch,
  2713. ARRAY_SIZE(wsa2_int0_vbat_mix_switch),
  2714. lpass_cdc_wsa2_macro_enable_vbat,
  2715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2716. SND_SOC_DAPM_MIXER_E("WSA2_RX INT1 VBAT", SND_SOC_NOPM,
  2717. 0, 0, wsa2_int1_vbat_mix_switch,
  2718. ARRAY_SIZE(wsa2_int1_vbat_mix_switch),
  2719. lpass_cdc_wsa2_macro_enable_vbat,
  2720. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2721. SND_SOC_DAPM_INPUT("VIINPUT_WSA2"),
  2722. SND_SOC_DAPM_INPUT("CPSINPUT_WSA2"),
  2723. SND_SOC_DAPM_OUTPUT("WSA2_SPK1 OUT"),
  2724. SND_SOC_DAPM_OUTPUT("WSA2_SPK2 OUT"),
  2725. SND_SOC_DAPM_SUPPLY_S("WSA2_MCLK", 0, SND_SOC_NOPM, 0, 0,
  2726. lpass_cdc_wsa2_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2727. };
  2728. static const struct snd_soc_dapm_route wsa2_audio_map[] = {
  2729. /* VI Feedback */
  2730. {"WSA2_AIF_VI Mixer", "WSA2_SPKR_VI_1", "VIINPUT_WSA2"},
  2731. {"WSA2_AIF_VI Mixer", "WSA2_SPKR_VI_2", "VIINPUT_WSA2"},
  2732. {"WSA2 AIF_VI", NULL, "WSA2_AIF_VI Mixer"},
  2733. {"WSA2 AIF_VI", NULL, "WSA2_MCLK"},
  2734. /* VI Feedback */
  2735. {"WSA2_AIF_CPS Mixer", "WSA2_SPKR_CPS_1", "CPSINPUT_WSA2"},
  2736. {"WSA2_AIF_CPS Mixer", "WSA2_SPKR_CPS_2", "CPSINPUT_WSA2"},
  2737. {"WSA2 AIF_CPS", NULL, "WSA2_AIF_CPS Mixer"},
  2738. {"WSA2 AIF_CPS", NULL, "WSA2_MCLK"},
  2739. {"WSA2 RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA2_RX INT0 SEC MIX"},
  2740. {"WSA2 RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA2_RX INT0 SEC MIX"},
  2741. {"WSA2 RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA2_RX INT1 SEC MIX"},
  2742. {"WSA2 RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA2_RX INT1 SEC MIX"},
  2743. {"WSA2 AIF_ECHO", NULL, "WSA2 RX_MIX EC0_MUX"},
  2744. {"WSA2 AIF_ECHO", NULL, "WSA2 RX_MIX EC1_MUX"},
  2745. {"WSA2 AIF_ECHO", NULL, "WSA2_MCLK"},
  2746. {"WSA2 AIF1 PB", NULL, "WSA2_MCLK"},
  2747. {"WSA2 AIF_MIX1 PB", NULL, "WSA2_MCLK"},
  2748. {"WSA2 RX0 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2749. {"WSA2 RX1 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2750. {"WSA2 RX_MIX0 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2751. {"WSA2 RX_MIX1 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2752. {"WSA2 RX4 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2753. {"WSA2 RX5 MUX", "AIF1_PB", "WSA2 AIF1 PB"},
  2754. {"WSA2 RX0 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2755. {"WSA2 RX1 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2756. {"WSA2 RX_MIX0 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2757. {"WSA2 RX_MIX1 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2758. {"WSA2 RX4 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2759. {"WSA2 RX5 MUX", "AIF_MIX1_PB", "WSA2 AIF_MIX1 PB"},
  2760. {"WSA2 RX0", NULL, "WSA2 RX0 MUX"},
  2761. {"WSA2 RX1", NULL, "WSA2 RX1 MUX"},
  2762. {"WSA2 RX_MIX0", NULL, "WSA2 RX_MIX0 MUX"},
  2763. {"WSA2 RX_MIX1", NULL, "WSA2 RX_MIX1 MUX"},
  2764. {"WSA2 RX4", NULL, "WSA2 RX4 MUX"},
  2765. {"WSA2 RX5", NULL, "WSA2 RX5 MUX"},
  2766. {"WSA2_RX0 INP0", "RX0", "WSA2 RX0"},
  2767. {"WSA2_RX0 INP0", "RX1", "WSA2 RX1"},
  2768. {"WSA2_RX0 INP0", "RX_MIX0", "WSA2 RX_MIX0"},
  2769. {"WSA2_RX0 INP0", "RX_MIX1", "WSA2 RX_MIX1"},
  2770. {"WSA2_RX0 INP0", "RX4", "WSA2 RX4"},
  2771. {"WSA2_RX0 INP0", "RX5", "WSA2 RX5"},
  2772. {"WSA2_RX0 INP0", "DEC0", "WSA2_TX DEC0_INP"},
  2773. {"WSA2_RX0 INP0", "DEC1", "WSA2_TX DEC1_INP"},
  2774. {"WSA2_RX INT0 MIX", NULL, "WSA2_RX0 INP0"},
  2775. {"WSA2_RX0 INP1", "RX0", "WSA2 RX0"},
  2776. {"WSA2_RX0 INP1", "RX1", "WSA2 RX1"},
  2777. {"WSA2_RX0 INP1", "RX_MIX0", "WSA2 RX_MIX0"},
  2778. {"WSA2_RX0 INP1", "RX_MIX1", "WSA2 RX_MIX1"},
  2779. {"WSA2_RX0 INP1", "RX4", "WSA2 RX4"},
  2780. {"WSA2_RX0 INP1", "RX5", "WSA2 RX5"},
  2781. {"WSA2_RX0 INP1", "DEC0", "WSA2_TX DEC0_INP"},
  2782. {"WSA2_RX0 INP1", "DEC1", "WSA2_TX DEC1_INP"},
  2783. {"WSA2_RX INT0 MIX", NULL, "WSA2_RX0 INP1"},
  2784. {"WSA2_RX0 INP2", "RX0", "WSA2 RX0"},
  2785. {"WSA2_RX0 INP2", "RX1", "WSA2 RX1"},
  2786. {"WSA2_RX0 INP2", "RX_MIX0", "WSA2 RX_MIX0"},
  2787. {"WSA2_RX0 INP2", "RX_MIX1", "WSA2 RX_MIX1"},
  2788. {"WSA2_RX0 INP2", "RX4", "WSA2 RX4"},
  2789. {"WSA2_RX0 INP2", "RX5", "WSA2 RX5"},
  2790. {"WSA2_RX0 INP2", "DEC0", "WSA2_TX DEC0_INP"},
  2791. {"WSA2_RX0 INP2", "DEC1", "WSA2_TX DEC1_INP"},
  2792. {"WSA2_RX INT0 MIX", NULL, "WSA2_RX0 INP2"},
  2793. {"WSA2_RX0 MIX INP", "RX0", "WSA2 RX0"},
  2794. {"WSA2_RX0 MIX INP", "RX1", "WSA2 RX1"},
  2795. {"WSA2_RX0 MIX INP", "RX_MIX0", "WSA2 RX_MIX0"},
  2796. {"WSA2_RX0 MIX INP", "RX_MIX1", "WSA2 RX_MIX1"},
  2797. {"WSA2_RX0 MIX INP", "RX4", "WSA2 RX4"},
  2798. {"WSA2_RX0 MIX INP", "RX5", "WSA2 RX5"},
  2799. {"WSA2_RX INT0 SEC MIX", NULL, "WSA2_RX0 MIX INP"},
  2800. {"WSA2_RX INT0 SEC MIX", NULL, "WSA2_RX INT0 MIX"},
  2801. {"WSA2_RX INT0 INTERP", NULL, "WSA2_RX INT0 SEC MIX"},
  2802. {"WSA2_RX0 INT0 SIDETONE MIX", "SRC0", "WSA2 SRC0_INP"},
  2803. {"WSA2_RX INT0 INTERP", NULL, "WSA2_RX0 INT0 SIDETONE MIX"},
  2804. {"WSA2_RX INT0 CHAIN", NULL, "WSA2_RX INT0 INTERP"},
  2805. {"WSA2_RX INT0 VBAT", "WSA2 RX0 VBAT Enable", "WSA2_RX INT0 INTERP"},
  2806. {"WSA2_RX INT0 CHAIN", NULL, "WSA2_RX INT0 VBAT"},
  2807. {"WSA2_SPK1 OUT", NULL, "WSA2_RX INT0 CHAIN"},
  2808. {"WSA2_SPK1 OUT", NULL, "WSA2_MCLK"},
  2809. {"WSA2_RX1 INP0", "RX0", "WSA2 RX0"},
  2810. {"WSA2_RX1 INP0", "RX1", "WSA2 RX1"},
  2811. {"WSA2_RX1 INP0", "RX_MIX0", "WSA2 RX_MIX0"},
  2812. {"WSA2_RX1 INP0", "RX_MIX1", "WSA2 RX_MIX1"},
  2813. {"WSA2_RX1 INP0", "RX4", "WSA2 RX4"},
  2814. {"WSA2_RX1 INP0", "RX5", "WSA2 RX5"},
  2815. {"WSA2_RX1 INP0", "DEC0", "WSA2_TX DEC0_INP"},
  2816. {"WSA2_RX1 INP0", "DEC1", "WSA2_TX DEC1_INP"},
  2817. {"WSA2_RX INT1 MIX", NULL, "WSA2_RX1 INP0"},
  2818. {"WSA2_RX1 INP1", "RX0", "WSA2 RX0"},
  2819. {"WSA2_RX1 INP1", "RX1", "WSA2 RX1"},
  2820. {"WSA2_RX1 INP1", "RX_MIX0", "WSA2 RX_MIX0"},
  2821. {"WSA2_RX1 INP1", "RX_MIX1", "WSA2 RX_MIX1"},
  2822. {"WSA2_RX1 INP1", "RX4", "WSA2 RX4"},
  2823. {"WSA2_RX1 INP1", "RX5", "WSA2 RX5"},
  2824. {"WSA2_RX1 INP1", "DEC0", "WSA2_TX DEC0_INP"},
  2825. {"WSA2_RX1 INP1", "DEC1", "WSA2_TX DEC1_INP"},
  2826. {"WSA2_RX INT1 MIX", NULL, "WSA2_RX1 INP1"},
  2827. {"WSA2_RX1 INP2", "RX0", "WSA2 RX0"},
  2828. {"WSA2_RX1 INP2", "RX1", "WSA2 RX1"},
  2829. {"WSA2_RX1 INP2", "RX_MIX0", "WSA2 RX_MIX0"},
  2830. {"WSA2_RX1 INP2", "RX_MIX1", "WSA2 RX_MIX1"},
  2831. {"WSA2_RX1 INP2", "RX4", "WSA2 RX4"},
  2832. {"WSA2_RX1 INP2", "RX5", "WSA2 RX5"},
  2833. {"WSA2_RX1 INP2", "DEC0", "WSA2_TX DEC0_INP"},
  2834. {"WSA2_RX1 INP2", "DEC1", "WSA2_TX DEC1_INP"},
  2835. {"WSA2_RX INT1 MIX", NULL, "WSA2_RX1 INP2"},
  2836. {"WSA2_RX1 MIX INP", "RX0", "WSA2 RX0"},
  2837. {"WSA2_RX1 MIX INP", "RX1", "WSA2 RX1"},
  2838. {"WSA2_RX1 MIX INP", "RX_MIX0", "WSA2 RX_MIX0"},
  2839. {"WSA2_RX1 MIX INP", "RX_MIX1", "WSA2 RX_MIX1"},
  2840. {"WSA2_RX1 MIX INP", "RX4", "WSA2 RX4"},
  2841. {"WSA2_RX1 MIX INP", "RX5", "WSA2 RX5"},
  2842. {"WSA2_RX INT1 SEC MIX", NULL, "WSA2_RX1 MIX INP"},
  2843. {"WSA2_RX INT1 SEC MIX", NULL, "WSA2_RX INT1 MIX"},
  2844. {"WSA2_RX INT1 INTERP", NULL, "WSA2_RX INT1 SEC MIX"},
  2845. {"WSA2_RX INT1 VBAT", "WSA2 RX1 VBAT Enable", "WSA2_RX INT1 INTERP"},
  2846. {"WSA2_RX INT1 CHAIN", NULL, "WSA2_RX INT1 VBAT"},
  2847. {"WSA2_RX INT1 CHAIN", NULL, "WSA2_RX INT1 INTERP"},
  2848. {"WSA2_SPK2 OUT", NULL, "WSA2_RX INT1 CHAIN"},
  2849. {"WSA2_SPK2 OUT", NULL, "WSA2_MCLK"},
  2850. };
  2851. static void lpass_cdc_wsa2_macro_init_pbr(struct snd_soc_component *component)
  2852. {
  2853. int sys_gain, bat_cfg, rload;
  2854. int vth1, vth2, vth3, vth4, vth5, vth6, vth7, vth8, vth9;
  2855. int vth10, vth11, vth12, vth13, vth14, vth15;
  2856. struct device *wsa2_dev = NULL;
  2857. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  2858. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  2859. return;
  2860. /* RX0 */
  2861. sys_gain = wsa2_priv->wsa2_sys_gain[0];
  2862. bat_cfg = wsa2_priv->wsa2_bat_cfg[0];
  2863. rload = wsa2_priv->wsa2_rload[0];
  2864. /* ILIM */
  2865. switch (rload) {
  2866. case WSA_4_OHMS:
  2867. snd_soc_component_update_bits(component,
  2868. LPASS_CDC_WSA2_ILIM_CFG0, 0xE0, 0x40);
  2869. break;
  2870. case WSA_6_OHMS:
  2871. snd_soc_component_update_bits(component,
  2872. LPASS_CDC_WSA2_ILIM_CFG0, 0xE0, 0x80);
  2873. break;
  2874. case WSA_8_OHMS:
  2875. snd_soc_component_update_bits(component,
  2876. LPASS_CDC_WSA2_ILIM_CFG0, 0xE0, 0xC0);
  2877. break;
  2878. case WSA_32_OHMS:
  2879. snd_soc_component_update_bits(component,
  2880. LPASS_CDC_WSA2_ILIM_CFG0, 0xE0, 0xE0);
  2881. break;
  2882. default:
  2883. break;
  2884. }
  2885. snd_soc_component_update_bits(component,
  2886. LPASS_CDC_WSA2_ILIM_CFG1, 0x0F, sys_gain);
  2887. snd_soc_component_update_bits(component,
  2888. LPASS_CDC_WSA2_ILIM_CFG9, 0xC0, (bat_cfg - 1) << 0x6);
  2889. /* Thesh */
  2890. vth1 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth1_data[sys_gain][bat_cfg][rload]);
  2891. vth2 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth2_data[sys_gain][bat_cfg][rload]);
  2892. vth3 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth3_data[sys_gain][bat_cfg][rload]);
  2893. vth4 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth4_data[sys_gain][bat_cfg][rload]);
  2894. vth5 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth5_data[sys_gain][bat_cfg][rload]);
  2895. vth6 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth6_data[sys_gain][bat_cfg][rload]);
  2896. vth7 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth7_data[sys_gain][bat_cfg][rload]);
  2897. vth8 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth8_data[sys_gain][bat_cfg][rload]);
  2898. vth9 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth9_data[sys_gain][bat_cfg][rload]);
  2899. vth10 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth10_data[sys_gain][bat_cfg][rload]);
  2900. vth11 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth11_data[sys_gain][bat_cfg][rload]);
  2901. vth12 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth12_data[sys_gain][bat_cfg][rload]);
  2902. vth13 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth13_data[sys_gain][bat_cfg][rload]);
  2903. vth14 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth14_data[sys_gain][bat_cfg][rload]);
  2904. vth15 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth15_data[sys_gain][bat_cfg][rload]);
  2905. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG1, vth1);
  2906. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG2, vth2);
  2907. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG3, vth3);
  2908. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG4, vth4);
  2909. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG5, vth5);
  2910. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG6, vth6);
  2911. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG7, vth7);
  2912. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG8, vth8);
  2913. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG9, vth9);
  2914. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG10, vth10);
  2915. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG11, vth11);
  2916. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG12, vth12);
  2917. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG13, vth13);
  2918. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG14, vth14);
  2919. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG15, vth15);
  2920. /* RX1 */
  2921. sys_gain = wsa2_priv->wsa2_sys_gain[2];
  2922. bat_cfg = wsa2_priv->wsa2_bat_cfg[1];
  2923. rload = wsa2_priv->wsa2_rload[1];
  2924. /* ILIM */
  2925. switch (rload) {
  2926. case WSA_4_OHMS:
  2927. snd_soc_component_update_bits(component,
  2928. LPASS_CDC_WSA2_ILIM_CFG0_1, 0xE0, 0x40);
  2929. break;
  2930. case WSA_6_OHMS:
  2931. snd_soc_component_update_bits(component,
  2932. LPASS_CDC_WSA2_ILIM_CFG0_1, 0xE0, 0x80);
  2933. break;
  2934. case WSA_8_OHMS:
  2935. snd_soc_component_update_bits(component,
  2936. LPASS_CDC_WSA2_ILIM_CFG0_1, 0xE0, 0xC0);
  2937. break;
  2938. case WSA_32_OHMS:
  2939. snd_soc_component_update_bits(component,
  2940. LPASS_CDC_WSA2_ILIM_CFG0_1, 0xE0, 0xE0);
  2941. break;
  2942. default:
  2943. break;
  2944. }
  2945. snd_soc_component_update_bits(component,
  2946. LPASS_CDC_WSA2_ILIM_CFG1_1, 0x0F, sys_gain);
  2947. snd_soc_component_update_bits(component,
  2948. LPASS_CDC_WSA2_ILIM_CFG9, 0x30, (bat_cfg - 1) << 0x4);
  2949. /* Thesh */
  2950. vth1 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth1_data[sys_gain][bat_cfg][rload]);
  2951. vth2 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth2_data[sys_gain][bat_cfg][rload]);
  2952. vth3 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth3_data[sys_gain][bat_cfg][rload]);
  2953. vth4 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth4_data[sys_gain][bat_cfg][rload]);
  2954. vth5 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth5_data[sys_gain][bat_cfg][rload]);
  2955. vth6 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth6_data[sys_gain][bat_cfg][rload]);
  2956. vth7 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth7_data[sys_gain][bat_cfg][rload]);
  2957. vth8 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth8_data[sys_gain][bat_cfg][rload]);
  2958. vth9 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth9_data[sys_gain][bat_cfg][rload]);
  2959. vth10 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth10_data[sys_gain][bat_cfg][rload]);
  2960. vth11 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth11_data[sys_gain][bat_cfg][rload]);
  2961. vth12 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth12_data[sys_gain][bat_cfg][rload]);
  2962. vth13 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth13_data[sys_gain][bat_cfg][rload]);
  2963. vth14 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth14_data[sys_gain][bat_cfg][rload]);
  2964. vth15 = LPASS_CDC_WSA2_MACRO_VTH_TO_REG(pbr_vth15_data[sys_gain][bat_cfg][rload]);
  2965. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG1_1, vth1);
  2966. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG2_1, vth2);
  2967. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG3_1, vth3);
  2968. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG4_1, vth4);
  2969. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG5_1, vth5);
  2970. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG6_1, vth6);
  2971. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG7_1, vth7);
  2972. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG8_1, vth8);
  2973. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG9_1, vth9);
  2974. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG10_1, vth10);
  2975. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG11_1, vth11);
  2976. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG12_1, vth12);
  2977. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG13_1, vth13);
  2978. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG14_1, vth14);
  2979. snd_soc_component_write(component, LPASS_CDC_WSA2_PBR_CFG15_1, vth15);
  2980. }
  2981. static const struct lpass_cdc_wsa2_macro_reg_mask_val
  2982. lpass_cdc_wsa2_macro_reg_init[] = {
  2983. {LPASS_CDC_WSA2_BOOST0_BOOST_CFG1, 0x3F, 0x12},
  2984. {LPASS_CDC_WSA2_BOOST0_BOOST_CFG2, 0x1C, 0x08},
  2985. {LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x3E, 0x2e},
  2986. {LPASS_CDC_WSA2_BOOST1_BOOST_CFG1, 0x3F, 0x12},
  2987. {LPASS_CDC_WSA2_BOOST1_BOOST_CFG2, 0x1C, 0x08},
  2988. {LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x3E, 0x2e},
  2989. {LPASS_CDC_WSA2_BOOST0_BOOST_CTL, 0x70, 0x58},
  2990. {LPASS_CDC_WSA2_BOOST1_BOOST_CTL, 0x70, 0x58},
  2991. {LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x08, 0x08},
  2992. {LPASS_CDC_WSA2_RX1_RX_PATH_CFG1, 0x08, 0x08},
  2993. {LPASS_CDC_WSA2_TOP_TOP_CFG1, 0x02, 0x02},
  2994. {LPASS_CDC_WSA2_TOP_TOP_CFG1, 0x01, 0x01},
  2995. {LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  2996. {LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  2997. {LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  2998. {LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  2999. {LPASS_CDC_WSA2_RX0_RX_PATH_CFG0, 0x01, 0x01},
  3000. {LPASS_CDC_WSA2_RX1_RX_PATH_CFG0, 0x01, 0x01},
  3001. {LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
  3002. {LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
  3003. {LPASS_CDC_WSA2_LA_CFG, 0x3F, 0xF},
  3004. {LPASS_CDC_WSA2_PBR_CFG16, 0xFF, 0x42},
  3005. {LPASS_CDC_WSA2_PBR_CFG19, 0xFF, 0xFC},
  3006. {LPASS_CDC_WSA2_PBR_CFG20, 0xF0, 0x60},
  3007. {LPASS_CDC_WSA2_ILIM_CFG1, 0x70, 0x40},
  3008. {LPASS_CDC_WSA2_ILIM_CFG0, 0x03, 0x01},
  3009. {LPASS_CDC_WSA2_ILIM_CFG3, 0x1F, 0x15},
  3010. {LPASS_CDC_WSA2_LA_CFG_1, 0x3F, 0x0F},
  3011. {LPASS_CDC_WSA2_PBR_CFG16_1, 0xFF, 0x42},
  3012. {LPASS_CDC_WSA2_PBR_CFG21, 0xFF, 0xFC},
  3013. {LPASS_CDC_WSA2_PBR_CFG22, 0xF0, 0x60},
  3014. {LPASS_CDC_WSA2_ILIM_CFG1_1, 0x70, 0x40},
  3015. {LPASS_CDC_WSA2_ILIM_CFG0_1, 0x03, 0x01},
  3016. {LPASS_CDC_WSA2_ILIM_CFG4, 0x1F, 0x15},
  3017. {LPASS_CDC_WSA2_ILIM_CFG2_1, 0xFF, 0x2A},
  3018. {LPASS_CDC_WSA2_ILIM_CFG2, 0x3F, 0x1B},
  3019. {LPASS_CDC_WSA2_ILIM_CFG9, 0x0F, 0x05},
  3020. {LPASS_CDC_WSA2_IDLE_DETECT_CFG1, 0xFF, 0x1D},
  3021. };
  3022. static void lpass_cdc_wsa2_macro_init_reg(struct snd_soc_component *component)
  3023. {
  3024. int i;
  3025. for (i = 0; i < ARRAY_SIZE(lpass_cdc_wsa2_macro_reg_init); i++)
  3026. snd_soc_component_update_bits(component,
  3027. lpass_cdc_wsa2_macro_reg_init[i].reg,
  3028. lpass_cdc_wsa2_macro_reg_init[i].mask,
  3029. lpass_cdc_wsa2_macro_reg_init[i].val);
  3030. lpass_cdc_wsa2_macro_init_pbr(component);
  3031. }
  3032. static int lpass_cdc_wsa2_macro_core_vote(void *handle, bool enable)
  3033. {
  3034. int rc = 0;
  3035. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = (struct lpass_cdc_wsa2_macro_priv *) handle;
  3036. if (wsa2_priv == NULL) {
  3037. pr_err_ratelimited("%s: wsa2 priv data is NULL\n", __func__);
  3038. return -EINVAL;
  3039. }
  3040. if (!wsa2_priv->pre_dev_up && enable) {
  3041. pr_debug("%s: adsp is not up\n", __func__);
  3042. return -EINVAL;
  3043. }
  3044. if (enable) {
  3045. pm_runtime_get_sync(wsa2_priv->dev);
  3046. if (lpass_cdc_check_core_votes(wsa2_priv->dev))
  3047. rc = 0;
  3048. else
  3049. rc = -ENOTSYNC;
  3050. } else {
  3051. pm_runtime_put_autosuspend(wsa2_priv->dev);
  3052. pm_runtime_mark_last_busy(wsa2_priv->dev);
  3053. }
  3054. return rc;
  3055. }
  3056. static int wsa2_swrm_clock(void *handle, bool enable)
  3057. {
  3058. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = (struct lpass_cdc_wsa2_macro_priv *) handle;
  3059. struct regmap *regmap = dev_get_regmap(wsa2_priv->dev->parent, NULL);
  3060. int ret = 0;
  3061. if (regmap == NULL) {
  3062. dev_err_ratelimited(wsa2_priv->dev, "%s: regmap is NULL\n", __func__);
  3063. return -EINVAL;
  3064. }
  3065. mutex_lock(&wsa2_priv->swr_clk_lock);
  3066. dev_dbg(wsa2_priv->dev, "%s: swrm clock %s\n",
  3067. __func__, (enable ? "enable" : "disable"));
  3068. if (enable) {
  3069. pm_runtime_get_sync(wsa2_priv->dev);
  3070. if (wsa2_priv->swr_clk_users == 0) {
  3071. ret = msm_cdc_pinctrl_select_active_state(
  3072. wsa2_priv->wsa2_swr_gpio_p);
  3073. if (ret < 0) {
  3074. dev_err_ratelimited(wsa2_priv->dev,
  3075. "%s: wsa2 swr pinctrl enable failed\n",
  3076. __func__);
  3077. pm_runtime_mark_last_busy(wsa2_priv->dev);
  3078. pm_runtime_put_autosuspend(wsa2_priv->dev);
  3079. goto exit;
  3080. }
  3081. ret = lpass_cdc_wsa2_macro_mclk_enable(wsa2_priv, 1, true);
  3082. if (ret < 0) {
  3083. msm_cdc_pinctrl_select_sleep_state(
  3084. wsa2_priv->wsa2_swr_gpio_p);
  3085. dev_err_ratelimited(wsa2_priv->dev,
  3086. "%s: wsa2 request clock enable failed\n",
  3087. __func__);
  3088. pm_runtime_mark_last_busy(wsa2_priv->dev);
  3089. pm_runtime_put_autosuspend(wsa2_priv->dev);
  3090. goto exit;
  3091. }
  3092. if (wsa2_priv->reset_swr)
  3093. regmap_update_bits(regmap,
  3094. LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL,
  3095. 0x02, 0x02);
  3096. regmap_update_bits(regmap,
  3097. LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL,
  3098. 0x01, 0x01);
  3099. if (wsa2_priv->reset_swr)
  3100. regmap_update_bits(regmap,
  3101. LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL,
  3102. 0x02, 0x00);
  3103. regmap_update_bits(regmap,
  3104. LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL,
  3105. 0x1C, 0x0C);
  3106. wsa2_priv->reset_swr = false;
  3107. }
  3108. wsa2_priv->swr_clk_users++;
  3109. pm_runtime_mark_last_busy(wsa2_priv->dev);
  3110. pm_runtime_put_autosuspend(wsa2_priv->dev);
  3111. } else {
  3112. if (wsa2_priv->swr_clk_users <= 0) {
  3113. dev_err_ratelimited(wsa2_priv->dev, "%s: clock already disabled\n",
  3114. __func__);
  3115. wsa2_priv->swr_clk_users = 0;
  3116. goto exit;
  3117. }
  3118. wsa2_priv->swr_clk_users--;
  3119. if (wsa2_priv->swr_clk_users == 0) {
  3120. regmap_update_bits(regmap,
  3121. LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL,
  3122. 0x01, 0x00);
  3123. lpass_cdc_wsa2_macro_mclk_enable(wsa2_priv, 0, true);
  3124. ret = msm_cdc_pinctrl_select_sleep_state(
  3125. wsa2_priv->wsa2_swr_gpio_p);
  3126. if (ret < 0) {
  3127. dev_err_ratelimited(wsa2_priv->dev,
  3128. "%s: wsa2 swr pinctrl disable failed\n",
  3129. __func__);
  3130. goto exit;
  3131. }
  3132. }
  3133. }
  3134. dev_dbg(wsa2_priv->dev, "%s: swrm clock users %d\n",
  3135. __func__, wsa2_priv->swr_clk_users);
  3136. exit:
  3137. mutex_unlock(&wsa2_priv->swr_clk_lock);
  3138. return ret;
  3139. }
  3140. /* Thermal Functions */
  3141. static int lpass_cdc_wsa2_macro_get_max_state(
  3142. struct thermal_cooling_device *cdev,
  3143. unsigned long *state)
  3144. {
  3145. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = cdev->devdata;
  3146. if (!wsa2_priv) {
  3147. pr_err_ratelimited("%s: cdev->devdata is NULL\n", __func__);
  3148. return -EINVAL;
  3149. }
  3150. *state = wsa2_priv->thermal_max_state;
  3151. return 0;
  3152. }
  3153. static int lpass_cdc_wsa2_macro_get_cur_state(
  3154. struct thermal_cooling_device *cdev,
  3155. unsigned long *state)
  3156. {
  3157. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = cdev->devdata;
  3158. if (!wsa2_priv) {
  3159. pr_err_ratelimited("%s: cdev->devdata is NULL\n", __func__);
  3160. return -EINVAL;
  3161. }
  3162. *state = wsa2_priv->thermal_cur_state;
  3163. pr_debug("%s: thermal current state:%lu\n", __func__, *state);
  3164. return 0;
  3165. }
  3166. static int lpass_cdc_wsa2_macro_set_cur_state(
  3167. struct thermal_cooling_device *cdev,
  3168. unsigned long state)
  3169. {
  3170. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = cdev->devdata;
  3171. if (!wsa2_priv || !wsa2_priv->dev) {
  3172. pr_err_ratelimited("%s: cdev->devdata is NULL\n", __func__);
  3173. return -EINVAL;
  3174. }
  3175. if (state <= wsa2_priv->thermal_max_state) {
  3176. wsa2_priv->thermal_cur_state = state;
  3177. } else {
  3178. dev_err_ratelimited(wsa2_priv->dev,
  3179. "%s: incorrect requested state:%d\n",
  3180. __func__, state);
  3181. return -EINVAL;
  3182. }
  3183. dev_dbg(wsa2_priv->dev,
  3184. "%s: set the thermal current state to %d\n",
  3185. __func__, wsa2_priv->thermal_cur_state);
  3186. schedule_work(&wsa2_priv->lpass_cdc_wsa2_macro_cooling_work);
  3187. return 0;
  3188. }
  3189. static struct thermal_cooling_device_ops wsa2_cooling_ops = {
  3190. .get_max_state = lpass_cdc_wsa2_macro_get_max_state,
  3191. .get_cur_state = lpass_cdc_wsa2_macro_get_cur_state,
  3192. .set_cur_state = lpass_cdc_wsa2_macro_set_cur_state,
  3193. };
  3194. static int lpass_cdc_wsa2_macro_init(struct snd_soc_component *component)
  3195. {
  3196. struct snd_soc_dapm_context *dapm =
  3197. snd_soc_component_get_dapm(component);
  3198. int ret;
  3199. struct device *wsa2_dev = NULL;
  3200. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  3201. wsa2_dev = lpass_cdc_get_device_ptr(component->dev, WSA2_MACRO);
  3202. if (!wsa2_dev) {
  3203. dev_err(component->dev,
  3204. "%s: null device for macro!\n", __func__);
  3205. return -EINVAL;
  3206. }
  3207. wsa2_priv = dev_get_drvdata(wsa2_dev);
  3208. if (!wsa2_priv) {
  3209. dev_err(component->dev,
  3210. "%s: priv is null for macro!\n", __func__);
  3211. return -EINVAL;
  3212. }
  3213. ret = snd_soc_dapm_new_controls(dapm, lpass_cdc_wsa2_macro_dapm_widgets,
  3214. ARRAY_SIZE(lpass_cdc_wsa2_macro_dapm_widgets));
  3215. if (ret < 0) {
  3216. dev_err(wsa2_dev, "%s: Failed to add controls\n", __func__);
  3217. return ret;
  3218. }
  3219. ret = snd_soc_dapm_add_routes(dapm, wsa2_audio_map,
  3220. ARRAY_SIZE(wsa2_audio_map));
  3221. if (ret < 0) {
  3222. dev_err(wsa2_dev, "%s: Failed to add routes\n", __func__);
  3223. return ret;
  3224. }
  3225. ret = snd_soc_dapm_new_widgets(dapm->card);
  3226. if (ret < 0) {
  3227. dev_err(wsa2_dev, "%s: Failed to add widgets\n", __func__);
  3228. return ret;
  3229. }
  3230. ret = snd_soc_add_component_controls(component, lpass_cdc_wsa2_macro_snd_controls,
  3231. ARRAY_SIZE(lpass_cdc_wsa2_macro_snd_controls));
  3232. if (ret < 0) {
  3233. dev_err(wsa2_dev, "%s: Failed to add snd_ctls\n", __func__);
  3234. return ret;
  3235. }
  3236. snd_soc_dapm_ignore_suspend(dapm, "WSA2_AIF1 Playback");
  3237. snd_soc_dapm_ignore_suspend(dapm, "WSA2_AIF_MIX1 Playback");
  3238. snd_soc_dapm_ignore_suspend(dapm, "WSA2_AIF_VI Capture");
  3239. snd_soc_dapm_ignore_suspend(dapm, "WSA2_AIF_ECHO Capture");
  3240. snd_soc_dapm_ignore_suspend(dapm, "WSA2_SPK1 OUT");
  3241. snd_soc_dapm_ignore_suspend(dapm, "WSA2_SPK2 OUT");
  3242. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA2");
  3243. snd_soc_dapm_ignore_suspend(dapm, "WSA2 SRC0_INP");
  3244. snd_soc_dapm_ignore_suspend(dapm, "WSA2_TX DEC0_INP");
  3245. snd_soc_dapm_ignore_suspend(dapm, "WSA2_TX DEC1_INP");
  3246. snd_soc_dapm_sync(dapm);
  3247. wsa2_priv->component = component;
  3248. wsa2_priv->spkr_gain_offset = LPASS_CDC_WSA2_MACRO_GAIN_OFFSET_0_DB;
  3249. lpass_cdc_wsa2_macro_init_reg(component);
  3250. return 0;
  3251. }
  3252. static int lpass_cdc_wsa2_macro_deinit(struct snd_soc_component *component)
  3253. {
  3254. struct device *wsa2_dev = NULL;
  3255. struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
  3256. if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
  3257. return -EINVAL;
  3258. wsa2_priv->component = NULL;
  3259. return 0;
  3260. }
  3261. static void lpass_cdc_wsa2_macro_add_child_devices(struct work_struct *work)
  3262. {
  3263. struct lpass_cdc_wsa2_macro_priv *wsa2_priv;
  3264. struct platform_device *pdev;
  3265. struct device_node *node;
  3266. struct lpass_cdc_wsa2_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp;
  3267. int ret;
  3268. u16 count = 0, ctrl_num = 0;
  3269. struct lpass_cdc_wsa2_macro_swr_ctrl_platform_data *platdata;
  3270. char plat_dev_name[LPASS_CDC_WSA2_MACRO_SWR_STRING_LEN];
  3271. wsa2_priv = container_of(work, struct lpass_cdc_wsa2_macro_priv,
  3272. lpass_cdc_wsa2_macro_add_child_devices_work);
  3273. if (!wsa2_priv) {
  3274. pr_err("%s: Memory for wsa2_priv does not exist\n",
  3275. __func__);
  3276. return;
  3277. }
  3278. if (!wsa2_priv->dev || !wsa2_priv->dev->of_node) {
  3279. dev_err(wsa2_priv->dev,
  3280. "%s: DT node for wsa2_priv does not exist\n", __func__);
  3281. return;
  3282. }
  3283. platdata = &wsa2_priv->swr_plat_data;
  3284. wsa2_priv->child_count = 0;
  3285. for_each_available_child_of_node(wsa2_priv->dev->of_node, node) {
  3286. if (strnstr(node->name, "wsa2_swr_master",
  3287. strlen("wsa2_swr_master")) != NULL)
  3288. strlcpy(plat_dev_name, "wsa2_swr_ctrl",
  3289. (LPASS_CDC_WSA2_MACRO_SWR_STRING_LEN - 1));
  3290. else if (strnstr(node->name, "msm_cdc_pinctrl",
  3291. strlen("msm_cdc_pinctrl")) != NULL)
  3292. strlcpy(plat_dev_name, node->name,
  3293. (LPASS_CDC_WSA2_MACRO_SWR_STRING_LEN - 1));
  3294. else
  3295. continue;
  3296. pdev = platform_device_alloc(plat_dev_name, -1);
  3297. if (!pdev) {
  3298. dev_err(wsa2_priv->dev, "%s: pdev memory alloc failed\n",
  3299. __func__);
  3300. ret = -ENOMEM;
  3301. goto err;
  3302. }
  3303. pdev->dev.parent = wsa2_priv->dev;
  3304. pdev->dev.of_node = node;
  3305. if (strnstr(node->name, "wsa2_swr_master",
  3306. strlen("wsa2_swr_master")) != NULL) {
  3307. ret = platform_device_add_data(pdev, platdata,
  3308. sizeof(*platdata));
  3309. if (ret) {
  3310. dev_err(&pdev->dev,
  3311. "%s: cannot add plat data ctrl:%d\n",
  3312. __func__, ctrl_num);
  3313. goto fail_pdev_add;
  3314. }
  3315. temp = krealloc(swr_ctrl_data,
  3316. (ctrl_num + 1) * sizeof(
  3317. struct lpass_cdc_wsa2_macro_swr_ctrl_data),
  3318. GFP_KERNEL);
  3319. if (!temp) {
  3320. dev_err(&pdev->dev, "out of memory\n");
  3321. ret = -ENOMEM;
  3322. goto fail_pdev_add;
  3323. }
  3324. swr_ctrl_data = temp;
  3325. swr_ctrl_data[ctrl_num].wsa2_swr_pdev = pdev;
  3326. ctrl_num++;
  3327. dev_dbg(&pdev->dev,
  3328. "%s: Adding soundwire ctrl device(s)\n",
  3329. __func__);
  3330. wsa2_priv->swr_ctrl_data = swr_ctrl_data;
  3331. }
  3332. ret = platform_device_add(pdev);
  3333. if (ret) {
  3334. dev_err(&pdev->dev,
  3335. "%s: Cannot add platform device\n",
  3336. __func__);
  3337. goto fail_pdev_add;
  3338. }
  3339. if (wsa2_priv->child_count < LPASS_CDC_WSA2_MACRO_CHILD_DEVICES_MAX)
  3340. wsa2_priv->pdev_child_devices[
  3341. wsa2_priv->child_count++] = pdev;
  3342. else
  3343. goto err;
  3344. }
  3345. return;
  3346. fail_pdev_add:
  3347. for (count = 0; count < wsa2_priv->child_count; count++)
  3348. platform_device_put(wsa2_priv->pdev_child_devices[count]);
  3349. err:
  3350. return;
  3351. }
  3352. static void lpass_cdc_wsa2_macro_cooling_adjust_gain(struct work_struct *work)
  3353. {
  3354. struct lpass_cdc_wsa2_macro_priv *wsa2_priv;
  3355. u8 gain = 0;
  3356. wsa2_priv = container_of(work, struct lpass_cdc_wsa2_macro_priv,
  3357. lpass_cdc_wsa2_macro_cooling_work);
  3358. if (!wsa2_priv) {
  3359. pr_err("%s: priv is null for macro!\n",
  3360. __func__);
  3361. return;
  3362. }
  3363. if (!wsa2_priv->dev || !wsa2_priv->dev->of_node) {
  3364. dev_err(wsa2_priv->dev,
  3365. "%s: DT node for wsa2_priv does not exist\n", __func__);
  3366. return;
  3367. }
  3368. /* Only adjust the volume when WSA2 clock is enabled */
  3369. if (wsa2_priv->dapm_mclk_enable) {
  3370. gain = (u8)(wsa2_priv->rx0_origin_gain -
  3371. wsa2_priv->thermal_cur_state);
  3372. snd_soc_component_update_bits(wsa2_priv->component,
  3373. LPASS_CDC_WSA2_RX0_RX_VOL_CTL, 0xFF, gain);
  3374. dev_dbg(wsa2_priv->dev,
  3375. "%s: RX0 current thermal state: %d, "
  3376. "adjusted gain: %#x\n",
  3377. __func__, wsa2_priv->thermal_cur_state, gain);
  3378. gain = (u8)(wsa2_priv->rx1_origin_gain -
  3379. wsa2_priv->thermal_cur_state);
  3380. snd_soc_component_update_bits(wsa2_priv->component,
  3381. LPASS_CDC_WSA2_RX1_RX_VOL_CTL, 0xFF, gain);
  3382. dev_dbg(wsa2_priv->dev,
  3383. "%s: RX1 current thermal state: %d, "
  3384. "adjusted gain: %#x\n",
  3385. __func__, wsa2_priv->thermal_cur_state, gain);
  3386. }
  3387. return;
  3388. }
  3389. static int lpass_cdc_wsa2_macro_read_array(struct platform_device *pdev,
  3390. const char *name, int num_values,
  3391. u32 *output)
  3392. {
  3393. u32 len, ret, size;
  3394. if (!of_find_property(pdev->dev.of_node, name, &size)) {
  3395. dev_info(&pdev->dev, "%s: missing %s\n", __func__, name);
  3396. return 0;
  3397. }
  3398. len = size / sizeof(u32);
  3399. if (len != num_values) {
  3400. dev_info(&pdev->dev, "%s: invalid number of %s\n", __func__, name);
  3401. return -EINVAL;
  3402. }
  3403. ret = of_property_read_u32_array(pdev->dev.of_node, name, output, len);
  3404. if (ret)
  3405. dev_info(&pdev->dev, "%s: Failed to read %s\n", __func__, name);
  3406. return 0;
  3407. }
  3408. static void lpass_cdc_wsa2_macro_init_ops(struct macro_ops *ops,
  3409. char __iomem *wsa2_io_base)
  3410. {
  3411. memset(ops, 0, sizeof(struct macro_ops));
  3412. ops->init = lpass_cdc_wsa2_macro_init;
  3413. ops->exit = lpass_cdc_wsa2_macro_deinit;
  3414. ops->io_base = wsa2_io_base;
  3415. ops->dai_ptr = lpass_cdc_wsa2_macro_dai;
  3416. ops->num_dais = ARRAY_SIZE(lpass_cdc_wsa2_macro_dai);
  3417. ops->event_handler = lpass_cdc_wsa2_macro_event_handler;
  3418. ops->set_port_map = lpass_cdc_wsa2_macro_set_port_map;
  3419. }
  3420. static int lpass_cdc_wsa2_macro_probe(struct platform_device *pdev)
  3421. {
  3422. struct macro_ops ops;
  3423. struct lpass_cdc_wsa2_macro_priv *wsa2_priv;
  3424. u32 wsa2_base_addr, default_clk_id, thermal_max_state;
  3425. char __iomem *wsa2_io_base;
  3426. int ret = 0;
  3427. u32 is_used_wsa2_swr_gpio = 1;
  3428. u32 noise_gate_mode;
  3429. const char *is_used_wsa2_swr_gpio_dt = "qcom,is-used-swr-gpio";
  3430. if (!lpass_cdc_is_va_macro_registered(&pdev->dev)) {
  3431. dev_err(&pdev->dev,
  3432. "%s: va-macro not registered yet, defer\n", __func__);
  3433. return -EPROBE_DEFER;
  3434. }
  3435. wsa2_priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_wsa2_macro_priv),
  3436. GFP_KERNEL);
  3437. if (!wsa2_priv)
  3438. return -ENOMEM;
  3439. wsa2_priv->pre_dev_up = true;
  3440. wsa2_priv->dev = &pdev->dev;
  3441. ret = of_property_read_u32(pdev->dev.of_node, "reg",
  3442. &wsa2_base_addr);
  3443. if (ret) {
  3444. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  3445. __func__, "reg");
  3446. return ret;
  3447. }
  3448. ret = of_property_read_u32(pdev->dev.of_node, "wsa_data_fs_ctl_reg",
  3449. &wsa2_priv->wsa2_fs_ctl_reg);
  3450. if (ret) {
  3451. dev_dbg(&pdev->dev, "%s: error finding %s entry in dt\n",
  3452. __func__, "wsa_data_fs_ctl_reg");
  3453. }
  3454. if (!wsa2_priv->wsa2_fs_reg_base && wsa2_priv->wsa2_fs_ctl_reg)
  3455. wsa2_priv->wsa2_fs_reg_base = devm_ioremap(&pdev->dev,
  3456. wsa2_priv->wsa2_fs_ctl_reg, LPASS_CDC_WSA2_MACRO_MAX_OFFSET);
  3457. if (of_find_property(pdev->dev.of_node, is_used_wsa2_swr_gpio_dt,
  3458. NULL)) {
  3459. ret = of_property_read_u32(pdev->dev.of_node,
  3460. is_used_wsa2_swr_gpio_dt,
  3461. &is_used_wsa2_swr_gpio);
  3462. if (ret) {
  3463. dev_err(&pdev->dev, "%s: error reading %s in dt\n",
  3464. __func__, is_used_wsa2_swr_gpio_dt);
  3465. is_used_wsa2_swr_gpio = 1;
  3466. }
  3467. }
  3468. wsa2_priv->wsa2_swr_gpio_p = of_parse_phandle(pdev->dev.of_node,
  3469. "qcom,wsa2-swr-gpios", 0);
  3470. if (!wsa2_priv->wsa2_swr_gpio_p && is_used_wsa2_swr_gpio) {
  3471. dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n",
  3472. __func__);
  3473. return -EINVAL;
  3474. }
  3475. if (msm_cdc_pinctrl_get_state(wsa2_priv->wsa2_swr_gpio_p) < 0 &&
  3476. is_used_wsa2_swr_gpio) {
  3477. dev_err(&pdev->dev, "%s: failed to get swr pin state\n",
  3478. __func__);
  3479. return -EPROBE_DEFER;
  3480. }
  3481. msm_cdc_pinctrl_set_wakeup_capable(
  3482. wsa2_priv->wsa2_swr_gpio_p, false);
  3483. wsa2_io_base = devm_ioremap(&pdev->dev,
  3484. wsa2_base_addr, LPASS_CDC_WSA2_MACRO_MAX_OFFSET);
  3485. if (!wsa2_io_base) {
  3486. dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);
  3487. return -EINVAL;
  3488. }
  3489. lpass_cdc_wsa2_macro_read_array(pdev, "qcom,wsa-rloads",
  3490. LPASS_CDC_WSA2_MACRO_RX1 + 1, wsa2_priv->wsa2_rload);
  3491. lpass_cdc_wsa2_macro_read_array(pdev, "qcom,wsa-system-gains",
  3492. 2 * (LPASS_CDC_WSA2_MACRO_RX1 + 1), wsa2_priv->wsa2_sys_gain);
  3493. lpass_cdc_wsa2_macro_read_array(pdev, "qcom,wsa-bat-cfgs",
  3494. LPASS_CDC_WSA2_MACRO_RX1 + 1, wsa2_priv->wsa2_bat_cfg);
  3495. wsa2_priv->wsa2_io_base = wsa2_io_base;
  3496. wsa2_priv->reset_swr = true;
  3497. INIT_WORK(&wsa2_priv->lpass_cdc_wsa2_macro_add_child_devices_work,
  3498. lpass_cdc_wsa2_macro_add_child_devices);
  3499. INIT_WORK(&wsa2_priv->lpass_cdc_wsa2_macro_cooling_work,
  3500. lpass_cdc_wsa2_macro_cooling_adjust_gain);
  3501. wsa2_priv->swr_plat_data.handle = (void *) wsa2_priv;
  3502. wsa2_priv->swr_plat_data.read = NULL;
  3503. wsa2_priv->swr_plat_data.write = NULL;
  3504. wsa2_priv->swr_plat_data.bulk_write = NULL;
  3505. wsa2_priv->swr_plat_data.clk = wsa2_swrm_clock;
  3506. wsa2_priv->swr_plat_data.core_vote = lpass_cdc_wsa2_macro_core_vote;
  3507. wsa2_priv->swr_plat_data.handle_irq = NULL;
  3508. ret = of_property_read_u32(pdev->dev.of_node, "qcom,default-clk-id",
  3509. &default_clk_id);
  3510. if (ret) {
  3511. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  3512. __func__, "qcom,mux0-clk-id");
  3513. default_clk_id = WSA2_CORE_CLK;
  3514. }
  3515. wsa2_priv->default_clk_id = default_clk_id;
  3516. dev_set_drvdata(&pdev->dev, wsa2_priv);
  3517. mutex_init(&wsa2_priv->mclk_lock);
  3518. mutex_init(&wsa2_priv->swr_clk_lock);
  3519. lpass_cdc_wsa2_macro_init_ops(&ops, wsa2_io_base);
  3520. ops.clk_id_req = wsa2_priv->default_clk_id;
  3521. ops.default_clk_id = wsa2_priv->default_clk_id;
  3522. ret = lpass_cdc_register_macro(&pdev->dev, WSA2_MACRO, &ops);
  3523. if (ret < 0) {
  3524. dev_err(&pdev->dev, "%s: register macro failed\n", __func__);
  3525. goto reg_macro_fail;
  3526. }
  3527. if (of_find_property(wsa2_priv->dev->of_node, "#cooling-cells", NULL)) {
  3528. ret = of_property_read_u32(pdev->dev.of_node,
  3529. "qcom,thermal-max-state",
  3530. &thermal_max_state);
  3531. if (ret) {
  3532. dev_info(&pdev->dev, "%s: could not find %s entry in dt\n",
  3533. __func__, "qcom,thermal-max-state");
  3534. wsa2_priv->thermal_max_state =
  3535. LPASS_CDC_WSA2_MACRO_THERMAL_MAX_STATE;
  3536. } else {
  3537. wsa2_priv->thermal_max_state = thermal_max_state;
  3538. }
  3539. wsa2_priv->tcdev = devm_thermal_of_cooling_device_register(
  3540. &pdev->dev,
  3541. wsa2_priv->dev->of_node,
  3542. "wsa2", wsa2_priv,
  3543. &wsa2_cooling_ops);
  3544. if (IS_ERR(wsa2_priv->tcdev)) {
  3545. dev_err(&pdev->dev,
  3546. "%s: failed to register wsa2 macro as cooling device\n",
  3547. __func__);
  3548. wsa2_priv->tcdev = NULL;
  3549. }
  3550. }
  3551. ret = of_property_read_u32(pdev->dev.of_node,
  3552. "qcom,noise-gate-mode", &noise_gate_mode);
  3553. if (ret) {
  3554. dev_info(&pdev->dev, "%s: could not find %s entry in dt\n",
  3555. __func__, "qcom,noise-gate-mode");
  3556. wsa2_priv->noise_gate_mode = IDLE_DETECT;
  3557. } else {
  3558. if (noise_gate_mode >= IDLE_DETECT && noise_gate_mode <= NG3)
  3559. wsa2_priv->noise_gate_mode = noise_gate_mode;
  3560. else
  3561. wsa2_priv->noise_gate_mode = IDLE_DETECT;
  3562. }
  3563. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
  3564. pm_runtime_use_autosuspend(&pdev->dev);
  3565. pm_runtime_set_suspended(&pdev->dev);
  3566. pm_suspend_ignore_children(&pdev->dev, true);
  3567. pm_runtime_enable(&pdev->dev);
  3568. schedule_work(&wsa2_priv->lpass_cdc_wsa2_macro_add_child_devices_work);
  3569. return ret;
  3570. reg_macro_fail:
  3571. mutex_destroy(&wsa2_priv->mclk_lock);
  3572. mutex_destroy(&wsa2_priv->swr_clk_lock);
  3573. return ret;
  3574. }
  3575. static int lpass_cdc_wsa2_macro_remove(struct platform_device *pdev)
  3576. {
  3577. struct lpass_cdc_wsa2_macro_priv *wsa2_priv;
  3578. u16 count = 0;
  3579. wsa2_priv = dev_get_drvdata(&pdev->dev);
  3580. if (!wsa2_priv)
  3581. return -EINVAL;
  3582. if (wsa2_priv->tcdev)
  3583. thermal_cooling_device_unregister(wsa2_priv->tcdev);
  3584. for (count = 0; count < wsa2_priv->child_count &&
  3585. count < LPASS_CDC_WSA2_MACRO_CHILD_DEVICES_MAX; count++)
  3586. platform_device_unregister(wsa2_priv->pdev_child_devices[count]);
  3587. pm_runtime_disable(&pdev->dev);
  3588. pm_runtime_set_suspended(&pdev->dev);
  3589. lpass_cdc_unregister_macro(&pdev->dev, WSA2_MACRO);
  3590. mutex_destroy(&wsa2_priv->mclk_lock);
  3591. mutex_destroy(&wsa2_priv->swr_clk_lock);
  3592. return 0;
  3593. }
  3594. static const struct of_device_id lpass_cdc_wsa2_macro_dt_match[] = {
  3595. {.compatible = "qcom,lpass-cdc-wsa2-macro"},
  3596. {}
  3597. };
  3598. static const struct dev_pm_ops lpass_cdc_dev_pm_ops = {
  3599. SET_SYSTEM_SLEEP_PM_OPS(
  3600. pm_runtime_force_suspend,
  3601. pm_runtime_force_resume
  3602. )
  3603. SET_RUNTIME_PM_OPS(
  3604. lpass_cdc_runtime_suspend,
  3605. lpass_cdc_runtime_resume,
  3606. NULL
  3607. )
  3608. };
  3609. static struct platform_driver lpass_cdc_wsa2_macro_driver = {
  3610. .driver = {
  3611. .name = "lpass_cdc_wsa2_macro",
  3612. .owner = THIS_MODULE,
  3613. .pm = &lpass_cdc_dev_pm_ops,
  3614. .of_match_table = lpass_cdc_wsa2_macro_dt_match,
  3615. .suppress_bind_attrs = true,
  3616. },
  3617. .probe = lpass_cdc_wsa2_macro_probe,
  3618. .remove = lpass_cdc_wsa2_macro_remove,
  3619. };
  3620. module_platform_driver(lpass_cdc_wsa2_macro_driver);
  3621. MODULE_DESCRIPTION("WSA2 macro driver");
  3622. MODULE_LICENSE("GPL v2");