lpass-cdc-tx-macro.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/clk.h>
  8. #include <linux/io.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/pm_runtime.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dapm.h>
  14. #include <sound/tlv.h>
  15. #include <asoc/msm-cdc-pinctrl.h>
  16. #include "lpass-cdc.h"
  17. #include "lpass-cdc-registers.h"
  18. #include "lpass-cdc-clk-rsc.h"
  19. #define AUTO_SUSPEND_DELAY 50 /* delay in msec */
  20. #define LPASS_CDC_TX_MACRO_MAX_OFFSET 0x1000
  21. #define NUM_DECIMATORS 8
  22. #define LPASS_CDC_TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  23. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  24. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  25. #define LPASS_CDC_TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  26. SNDRV_PCM_FMTBIT_S24_LE |\
  27. SNDRV_PCM_FMTBIT_S24_3LE)
  28. #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
  29. #define CF_MIN_3DB_4HZ 0x0
  30. #define CF_MIN_3DB_75HZ 0x1
  31. #define CF_MIN_3DB_150HZ 0x2
  32. #define LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0
  33. #define LPASS_CDC_TX_MACRO_MCLK_FREQ 9600000
  34. #define LPASS_CDC_TX_MACRO_TX_PATH_OFFSET \
  35. (LPASS_CDC_TX1_TX_PATH_CTL - LPASS_CDC_TX0_TX_PATH_CTL)
  36. #define LPASS_CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
  37. #define LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET 0x8
  38. #define LPASS_CDC_TX_MACRO_ADC_MODE_CFG0_SHIFT 1
  39. #define LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
  40. #define LPASS_CDC_TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
  41. #define LPASS_CDC_TX_MACRO_DMIC_HPF_DELAY_MS 300
  42. #define LPASS_CDC_TX_MACRO_AMIC_HPF_DELAY_MS 300
  43. static int tx_unmute_delay = LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS;
  44. module_param(tx_unmute_delay, int, 0664);
  45. MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path");
  46. static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
  47. static int lpass_cdc_tx_macro_hw_params(struct snd_pcm_substream *substream,
  48. struct snd_pcm_hw_params *params,
  49. struct snd_soc_dai *dai);
  50. static int lpass_cdc_tx_macro_get_channel_map(struct snd_soc_dai *dai,
  51. unsigned int *tx_num, unsigned int *tx_slot,
  52. unsigned int *rx_num, unsigned int *rx_slot);
  53. #define LPASS_CDC_TX_MACRO_SWR_STRING_LEN 80
  54. #define LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX 3
  55. enum {
  56. LPASS_CDC_TX_MACRO_AIF_INVALID = 0,
  57. LPASS_CDC_TX_MACRO_AIF1_CAP,
  58. LPASS_CDC_TX_MACRO_AIF2_CAP,
  59. LPASS_CDC_TX_MACRO_AIF3_CAP,
  60. LPASS_CDC_TX_MACRO_MAX_DAIS
  61. };
  62. enum {
  63. LPASS_CDC_TX_MACRO_DEC0,
  64. LPASS_CDC_TX_MACRO_DEC1,
  65. LPASS_CDC_TX_MACRO_DEC2,
  66. LPASS_CDC_TX_MACRO_DEC3,
  67. LPASS_CDC_TX_MACRO_DEC4,
  68. LPASS_CDC_TX_MACRO_DEC5,
  69. LPASS_CDC_TX_MACRO_DEC6,
  70. LPASS_CDC_TX_MACRO_DEC7,
  71. LPASS_CDC_TX_MACRO_DEC_MAX,
  72. };
  73. enum {
  74. LPASS_CDC_TX_MACRO_CLK_DIV_2,
  75. LPASS_CDC_TX_MACRO_CLK_DIV_3,
  76. LPASS_CDC_TX_MACRO_CLK_DIV_4,
  77. LPASS_CDC_TX_MACRO_CLK_DIV_6,
  78. LPASS_CDC_TX_MACRO_CLK_DIV_8,
  79. LPASS_CDC_TX_MACRO_CLK_DIV_16,
  80. };
  81. enum {
  82. MSM_DMIC,
  83. SWR_MIC,
  84. ANC_FB_TUNE1
  85. };
  86. enum {
  87. TX_MCLK,
  88. VA_MCLK,
  89. };
  90. struct lpass_cdc_tx_macro_reg_mask_val {
  91. u16 reg;
  92. u8 mask;
  93. u8 val;
  94. };
  95. struct tx_mute_work {
  96. struct lpass_cdc_tx_macro_priv *tx_priv;
  97. u32 decimator;
  98. struct delayed_work dwork;
  99. };
  100. struct hpf_work {
  101. struct lpass_cdc_tx_macro_priv *tx_priv;
  102. u8 decimator;
  103. u8 hpf_cut_off_freq;
  104. struct delayed_work dwork;
  105. };
  106. struct lpass_cdc_tx_macro_priv {
  107. struct device *dev;
  108. bool dec_active[NUM_DECIMATORS];
  109. int tx_mclk_users;
  110. bool dapm_mclk_enable;
  111. struct mutex mclk_lock;
  112. struct mutex wlock;
  113. struct snd_soc_component *component;
  114. struct hpf_work tx_hpf_work[NUM_DECIMATORS];
  115. struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
  116. u16 dmic_clk_div;
  117. u32 version;
  118. unsigned long active_ch_mask[LPASS_CDC_TX_MACRO_MAX_DAIS];
  119. unsigned long active_ch_cnt[LPASS_CDC_TX_MACRO_MAX_DAIS];
  120. char __iomem *tx_io_base;
  121. struct platform_device *pdev_child_devices
  122. [LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX];
  123. int child_count;
  124. bool bcs_enable;
  125. int dec_mode[NUM_DECIMATORS];
  126. int bcs_ch;
  127. bool bcs_clk_en;
  128. bool hs_slow_insert_complete;
  129. int pcm_rate[NUM_DECIMATORS];
  130. bool swr_dmic_enable;
  131. int wlock_holders;
  132. };
  133. static int lpass_cdc_tx_macro_wake_enable(struct lpass_cdc_tx_macro_priv *tx_priv,
  134. bool wake_enable)
  135. {
  136. int ret = 0;
  137. mutex_lock(&tx_priv->wlock);
  138. if (wake_enable) {
  139. if (tx_priv->wlock_holders++ == 0) {
  140. dev_dbg(tx_priv->dev, "%s: pm wake\n", __func__);
  141. pm_stay_awake(tx_priv->dev);
  142. }
  143. } else {
  144. if (--tx_priv->wlock_holders == 0) {
  145. dev_dbg(tx_priv->dev, "%s: pm release\n", __func__);
  146. pm_relax(tx_priv->dev);
  147. }
  148. if (tx_priv->wlock_holders < 0)
  149. tx_priv->wlock_holders = 0;
  150. }
  151. mutex_unlock(&tx_priv->wlock);
  152. return ret;
  153. }
  154. static bool lpass_cdc_tx_macro_get_data(struct snd_soc_component *component,
  155. struct device **tx_dev,
  156. struct lpass_cdc_tx_macro_priv **tx_priv,
  157. const char *func_name)
  158. {
  159. *tx_dev = lpass_cdc_get_device_ptr(component->dev, TX_MACRO);
  160. if (!(*tx_dev)) {
  161. dev_err_ratelimited(component->dev,
  162. "%s: null device for macro!\n", func_name);
  163. return false;
  164. }
  165. *tx_priv = dev_get_drvdata((*tx_dev));
  166. if (!(*tx_priv)) {
  167. dev_err_ratelimited(component->dev,
  168. "%s: priv is null for macro!\n", func_name);
  169. return false;
  170. }
  171. if (!(*tx_priv)->component) {
  172. dev_err_ratelimited(component->dev,
  173. "%s: tx_priv->component not initialized!\n", func_name);
  174. return false;
  175. }
  176. return true;
  177. }
  178. static int lpass_cdc_tx_macro_mclk_enable(
  179. struct lpass_cdc_tx_macro_priv *tx_priv,
  180. bool mclk_enable)
  181. {
  182. struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL);
  183. int ret = 0;
  184. if (regmap == NULL) {
  185. dev_err_ratelimited(tx_priv->dev, "%s: regmap is NULL\n", __func__);
  186. return -EINVAL;
  187. }
  188. dev_dbg(tx_priv->dev, "%s: mclk_enable = %u,clk_users= %d\n",
  189. __func__, mclk_enable, tx_priv->tx_mclk_users);
  190. mutex_lock(&tx_priv->mclk_lock);
  191. if (mclk_enable) {
  192. ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev,
  193. TX_CORE_CLK,
  194. TX_CORE_CLK,
  195. true);
  196. if (ret < 0) {
  197. dev_err_ratelimited(tx_priv->dev,
  198. "%s: request clock enable failed\n",
  199. __func__);
  200. goto exit;
  201. }
  202. lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev,
  203. true);
  204. regcache_mark_dirty(regmap);
  205. regcache_sync_region(regmap,
  206. TX_START_OFFSET,
  207. TX_MAX_OFFSET);
  208. if (tx_priv->tx_mclk_users == 0) {
  209. regmap_update_bits(regmap,
  210. LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
  211. 0x01, 0x01);
  212. regmap_update_bits(regmap,
  213. LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
  214. 0x01, 0x01);
  215. }
  216. tx_priv->tx_mclk_users++;
  217. } else {
  218. if (tx_priv->tx_mclk_users <= 0) {
  219. dev_err_ratelimited(tx_priv->dev, "%s: clock already disabled\n",
  220. __func__);
  221. tx_priv->tx_mclk_users = 0;
  222. goto exit;
  223. }
  224. tx_priv->tx_mclk_users--;
  225. if (tx_priv->tx_mclk_users == 0) {
  226. regmap_update_bits(regmap,
  227. LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
  228. 0x01, 0x00);
  229. regmap_update_bits(regmap,
  230. LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
  231. 0x01, 0x00);
  232. }
  233. lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev,
  234. false);
  235. lpass_cdc_clk_rsc_request_clock(tx_priv->dev,
  236. TX_CORE_CLK,
  237. TX_CORE_CLK,
  238. false);
  239. }
  240. exit:
  241. mutex_unlock(&tx_priv->mclk_lock);
  242. return ret;
  243. }
  244. static int __lpass_cdc_tx_macro_mclk_enable(struct snd_soc_component *component,
  245. bool enable)
  246. {
  247. struct device *tx_dev = NULL;
  248. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  249. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  250. return -EINVAL;
  251. return lpass_cdc_tx_macro_mclk_enable(tx_priv, enable);
  252. }
  253. static int lpass_cdc_tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
  254. struct snd_kcontrol *kcontrol, int event)
  255. {
  256. struct snd_soc_component *component =
  257. snd_soc_dapm_to_component(w->dapm);
  258. int ret = 0;
  259. struct device *tx_dev = NULL;
  260. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  261. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  262. return -EINVAL;
  263. dev_dbg(tx_dev, "%s: event = %d\n", __func__, event);
  264. switch (event) {
  265. case SND_SOC_DAPM_PRE_PMU:
  266. ret = lpass_cdc_tx_macro_mclk_enable(tx_priv, 1);
  267. if (ret)
  268. tx_priv->dapm_mclk_enable = false;
  269. else
  270. tx_priv->dapm_mclk_enable = true;
  271. break;
  272. case SND_SOC_DAPM_POST_PMD:
  273. if (tx_priv->dapm_mclk_enable)
  274. ret = lpass_cdc_tx_macro_mclk_enable(tx_priv, 0);
  275. break;
  276. default:
  277. dev_err_ratelimited(tx_priv->dev,
  278. "%s: invalid DAPM event %d\n", __func__, event);
  279. ret = -EINVAL;
  280. }
  281. return ret;
  282. }
  283. static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component,
  284. u16 event, u32 data)
  285. {
  286. struct device *tx_dev = NULL;
  287. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  288. int ret = 0;
  289. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  290. return -EINVAL;
  291. switch (event) {
  292. case LPASS_CDC_MACRO_EVT_SSR_DOWN:
  293. if ((!pm_runtime_enabled(tx_dev) ||
  294. !pm_runtime_suspended(tx_dev))) {
  295. ret = lpass_cdc_runtime_suspend(tx_dev);
  296. if (!ret) {
  297. pm_runtime_disable(tx_dev);
  298. pm_runtime_set_suspended(tx_dev);
  299. pm_runtime_enable(tx_dev);
  300. }
  301. }
  302. break;
  303. case LPASS_CDC_MACRO_EVT_SSR_UP:
  304. break;
  305. case LPASS_CDC_MACRO_EVT_CLK_RESET:
  306. lpass_cdc_rsc_clk_reset(tx_dev, TX_CORE_CLK);
  307. break;
  308. case LPASS_CDC_MACRO_EVT_BCS_CLK_OFF:
  309. if (tx_priv->bcs_clk_en)
  310. snd_soc_component_update_bits(component,
  311. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, data << 6);
  312. if (data)
  313. tx_priv->hs_slow_insert_complete = true;
  314. else
  315. tx_priv->hs_slow_insert_complete = false;
  316. break;
  317. default:
  318. pr_debug("%s Invalid Event\n", __func__);
  319. break;
  320. }
  321. return 0;
  322. }
  323. static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
  324. {
  325. u16 adc_mux_reg = 0;
  326. bool ret = false;
  327. struct device *tx_dev = NULL;
  328. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  329. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  330. return ret;
  331. adc_mux_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  332. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  333. if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
  334. if (!tx_priv->swr_dmic_enable)
  335. return true;
  336. }
  337. return ret;
  338. }
  339. static void lpass_cdc_tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
  340. {
  341. struct delayed_work *hpf_delayed_work = NULL;
  342. struct hpf_work *hpf_work = NULL;
  343. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  344. struct snd_soc_component *component = NULL;
  345. u16 dec_cfg_reg = 0, hpf_gate_reg = 0;
  346. u8 hpf_cut_off_freq = 0;
  347. u16 adc_reg = 0, adc_n = 0;
  348. hpf_delayed_work = to_delayed_work(work);
  349. hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
  350. tx_priv = hpf_work->tx_priv;
  351. component = tx_priv->component;
  352. hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
  353. dec_cfg_reg = LPASS_CDC_TX0_TX_PATH_CFG0 +
  354. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  355. hpf_gate_reg = LPASS_CDC_TX0_TX_PATH_SEC2 +
  356. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  357. dev_dbg(component->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",
  358. __func__, hpf_work->decimator, hpf_cut_off_freq);
  359. if (is_amic_enabled(component, hpf_work->decimator)) {
  360. adc_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  361. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * hpf_work->decimator;
  362. adc_n = snd_soc_component_read(component, adc_reg) &
  363. LPASS_CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
  364. /* analog mic clear TX hold */
  365. lpass_cdc_clear_amic_tx_hold(component->dev, adc_n);
  366. snd_soc_component_update_bits(component,
  367. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  368. hpf_cut_off_freq << 5);
  369. snd_soc_component_update_bits(component, hpf_gate_reg,
  370. 0x03, 0x02);
  371. /* Add delay between toggle hpf gate based on sample rate */
  372. switch (tx_priv->pcm_rate[hpf_work->decimator]) {
  373. case 0:
  374. usleep_range(125, 130);
  375. break;
  376. case 1:
  377. usleep_range(62, 65);
  378. break;
  379. case 3:
  380. usleep_range(31, 32);
  381. break;
  382. case 4:
  383. usleep_range(20, 21);
  384. break;
  385. case 5:
  386. usleep_range(10, 11);
  387. break;
  388. case 6:
  389. usleep_range(5, 6);
  390. break;
  391. default:
  392. usleep_range(125, 130);
  393. }
  394. snd_soc_component_update_bits(component, hpf_gate_reg,
  395. 0x03, 0x01);
  396. } else {
  397. snd_soc_component_update_bits(component,
  398. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  399. hpf_cut_off_freq << 5);
  400. snd_soc_component_update_bits(component, hpf_gate_reg,
  401. 0x02, 0x02);
  402. /* Minimum 1 clk cycle delay is required as per HW spec */
  403. usleep_range(1000, 1010);
  404. snd_soc_component_update_bits(component, hpf_gate_reg,
  405. 0x02, 0x00);
  406. }
  407. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  408. }
  409. static void lpass_cdc_tx_macro_mute_update_callback(struct work_struct *work)
  410. {
  411. struct tx_mute_work *tx_mute_dwork = NULL;
  412. struct snd_soc_component *component = NULL;
  413. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  414. struct delayed_work *delayed_work = NULL;
  415. u16 tx_vol_ctl_reg = 0;
  416. u8 decimator = 0;
  417. delayed_work = to_delayed_work(work);
  418. tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
  419. tx_priv = tx_mute_dwork->tx_priv;
  420. component = tx_priv->component;
  421. decimator = tx_mute_dwork->decimator;
  422. tx_vol_ctl_reg =
  423. LPASS_CDC_TX0_TX_PATH_CTL +
  424. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  425. snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x10, 0x00);
  426. dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n",
  427. __func__, decimator);
  428. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  429. }
  430. static int lpass_cdc_tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
  431. struct snd_ctl_elem_value *ucontrol)
  432. {
  433. struct snd_soc_dapm_widget *widget =
  434. snd_soc_dapm_kcontrol_widget(kcontrol);
  435. struct snd_soc_component *component =
  436. snd_soc_dapm_to_component(widget->dapm);
  437. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  438. unsigned int val = 0;
  439. u16 mic_sel_reg = 0;
  440. u16 dmic_clk_reg = 0;
  441. struct device *tx_dev = NULL;
  442. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  443. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  444. return -EINVAL;
  445. val = ucontrol->value.enumerated.item[0];
  446. if (val > e->items - 1)
  447. return -EINVAL;
  448. dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__,
  449. widget->name, val);
  450. switch (e->reg) {
  451. case LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0:
  452. mic_sel_reg = LPASS_CDC_TX0_TX_PATH_CFG0;
  453. break;
  454. case LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0:
  455. mic_sel_reg = LPASS_CDC_TX1_TX_PATH_CFG0;
  456. break;
  457. case LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0:
  458. mic_sel_reg = LPASS_CDC_TX2_TX_PATH_CFG0;
  459. break;
  460. case LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0:
  461. mic_sel_reg = LPASS_CDC_TX3_TX_PATH_CFG0;
  462. break;
  463. case LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
  464. mic_sel_reg = LPASS_CDC_TX4_TX_PATH_CFG0;
  465. break;
  466. case LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
  467. mic_sel_reg = LPASS_CDC_TX5_TX_PATH_CFG0;
  468. break;
  469. case LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
  470. mic_sel_reg = LPASS_CDC_TX6_TX_PATH_CFG0;
  471. break;
  472. case LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
  473. mic_sel_reg = LPASS_CDC_TX7_TX_PATH_CFG0;
  474. break;
  475. default:
  476. dev_err_ratelimited(component->dev, "%s: e->reg: 0x%x not expected\n",
  477. __func__, e->reg);
  478. return -EINVAL;
  479. }
  480. if (strnstr(widget->name, "SMIC", strlen(widget->name))) {
  481. if (val != 0) {
  482. if (!tx_priv->swr_dmic_enable) {
  483. snd_soc_component_update_bits(component,
  484. mic_sel_reg,
  485. 1 << 7, 0x0 << 7);
  486. } else {
  487. snd_soc_component_update_bits(component,
  488. mic_sel_reg,
  489. 1 << 7, 0x1 << 7);
  490. snd_soc_component_update_bits(component,
  491. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  492. 0x80, 0x00);
  493. dmic_clk_reg =
  494. LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL +
  495. ((val - 5)/2) * 4;
  496. snd_soc_component_update_bits(component,
  497. dmic_clk_reg,
  498. 0x0E, tx_priv->dmic_clk_div << 0x1);
  499. }
  500. }
  501. } else {
  502. /* DMIC selected */
  503. if (val != 0)
  504. snd_soc_component_update_bits(component, mic_sel_reg,
  505. 1 << 7, 1 << 7);
  506. }
  507. return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  508. }
  509. static int lpass_cdc_tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
  510. struct snd_ctl_elem_value *ucontrol)
  511. {
  512. struct snd_soc_dapm_widget *widget =
  513. snd_soc_dapm_kcontrol_widget(kcontrol);
  514. struct snd_soc_component *component =
  515. snd_soc_dapm_to_component(widget->dapm);
  516. struct soc_multi_mixer_control *mixer =
  517. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  518. u32 dai_id = widget->shift;
  519. u32 dec_id = mixer->shift;
  520. struct device *tx_dev = NULL;
  521. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  522. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  523. return -EINVAL;
  524. if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id]))
  525. ucontrol->value.integer.value[0] = 1;
  526. else
  527. ucontrol->value.integer.value[0] = 0;
  528. return 0;
  529. }
  530. static int lpass_cdc_tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
  531. struct snd_ctl_elem_value *ucontrol)
  532. {
  533. struct snd_soc_dapm_widget *widget =
  534. snd_soc_dapm_kcontrol_widget(kcontrol);
  535. struct snd_soc_component *component =
  536. snd_soc_dapm_to_component(widget->dapm);
  537. struct snd_soc_dapm_update *update = NULL;
  538. struct soc_multi_mixer_control *mixer =
  539. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  540. u32 dai_id = widget->shift;
  541. u32 dec_id = mixer->shift;
  542. u32 enable = ucontrol->value.integer.value[0];
  543. struct device *tx_dev = NULL;
  544. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  545. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  546. return -EINVAL;
  547. if (enable) {
  548. if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) {
  549. dev_err(component->dev, "%s: channel is already enabled, dec_id = %d, dai_id = %d\n",
  550. __func__, dec_id, dai_id);
  551. } else {
  552. set_bit(dec_id, &tx_priv->active_ch_mask[dai_id]);
  553. tx_priv->active_ch_cnt[dai_id]++;
  554. }
  555. } else {
  556. if (!test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) {
  557. dev_err(component->dev, "%s: channel is already disabled, dec_id = %d, dai_id = %d\n",
  558. __func__, dec_id, dai_id);
  559. } else {
  560. tx_priv->active_ch_cnt[dai_id]--;
  561. clear_bit(dec_id, &tx_priv->active_ch_mask[dai_id]);
  562. }
  563. }
  564. snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
  565. return 0;
  566. }
  567. static inline int lpass_cdc_tx_macro_path_get(const char *wname,
  568. unsigned int *path_num)
  569. {
  570. int ret = 0;
  571. char *widget_name = NULL;
  572. char *w_name = NULL;
  573. char *path_num_char = NULL;
  574. char *path_name = NULL;
  575. widget_name = kstrndup(wname, 10, GFP_KERNEL);
  576. if (!widget_name)
  577. return -EINVAL;
  578. w_name = widget_name;
  579. path_name = strsep(&widget_name, " ");
  580. if (!path_name) {
  581. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  582. __func__, widget_name);
  583. ret = -EINVAL;
  584. goto err;
  585. }
  586. path_num_char = strpbrk(path_name, "01234567");
  587. if (!path_num_char) {
  588. pr_err_ratelimited("%s: tx path index not found\n",
  589. __func__);
  590. ret = -EINVAL;
  591. goto err;
  592. }
  593. ret = kstrtouint(path_num_char, 10, path_num);
  594. if (ret < 0)
  595. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  596. __func__, w_name);
  597. err:
  598. kfree(w_name);
  599. return ret;
  600. }
  601. static int lpass_cdc_tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
  602. struct snd_ctl_elem_value *ucontrol)
  603. {
  604. struct snd_soc_component *component =
  605. snd_soc_kcontrol_component(kcontrol);
  606. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  607. struct device *tx_dev = NULL;
  608. int ret = 0;
  609. int path = 0;
  610. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  611. return -EINVAL;
  612. ret = lpass_cdc_tx_macro_path_get(kcontrol->id.name, &path);
  613. if (ret)
  614. return ret;
  615. ucontrol->value.integer.value[0] = tx_priv->dec_mode[path];
  616. return 0;
  617. }
  618. static int lpass_cdc_tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
  619. struct snd_ctl_elem_value *ucontrol)
  620. {
  621. struct snd_soc_component *component =
  622. snd_soc_kcontrol_component(kcontrol);
  623. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  624. struct device *tx_dev = NULL;
  625. int value = ucontrol->value.integer.value[0];
  626. int ret = 0;
  627. int path = 0;
  628. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  629. return -EINVAL;
  630. ret = lpass_cdc_tx_macro_path_get(kcontrol->id.name, &path);
  631. if (ret)
  632. return ret;
  633. tx_priv->dec_mode[path] = value;
  634. return 0;
  635. }
  636. static int lpass_cdc_tx_macro_bcs_ch_get(struct snd_kcontrol *kcontrol,
  637. struct snd_ctl_elem_value *ucontrol)
  638. {
  639. struct snd_soc_component *component =
  640. snd_soc_kcontrol_component(kcontrol);
  641. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  642. struct device *tx_dev = NULL;
  643. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  644. return -EINVAL;
  645. ucontrol->value.enumerated.item[0] = tx_priv->bcs_ch;
  646. return 0;
  647. }
  648. static int lpass_cdc_tx_macro_bcs_ch_put(struct snd_kcontrol *kcontrol,
  649. struct snd_ctl_elem_value *ucontrol)
  650. {
  651. struct snd_soc_component *component =
  652. snd_soc_kcontrol_component(kcontrol);
  653. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  654. struct device *tx_dev = NULL;
  655. int value = ucontrol->value.enumerated.item[0];
  656. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  657. return -EINVAL;
  658. tx_priv->bcs_ch = value;
  659. return 0;
  660. }
  661. static int lpass_cdc_tx_macro_swr_dmic_get(struct snd_kcontrol *kcontrol,
  662. struct snd_ctl_elem_value *ucontrol)
  663. {
  664. struct snd_soc_component *component =
  665. snd_soc_kcontrol_component(kcontrol);
  666. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  667. struct device *tx_dev = NULL;
  668. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  669. return -EINVAL;
  670. ucontrol->value.integer.value[0] = tx_priv->swr_dmic_enable;
  671. return 0;
  672. }
  673. static int lpass_cdc_tx_macro_swr_dmic_put(struct snd_kcontrol *kcontrol,
  674. struct snd_ctl_elem_value *ucontrol)
  675. {
  676. struct snd_soc_component *component =
  677. snd_soc_kcontrol_component(kcontrol);
  678. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  679. struct device *tx_dev = NULL;
  680. int value = ucontrol->value.integer.value[0];
  681. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  682. return -EINVAL;
  683. tx_priv->swr_dmic_enable = value;
  684. return 0;
  685. }
  686. static int lpass_cdc_tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
  687. struct snd_ctl_elem_value *ucontrol)
  688. {
  689. struct snd_soc_component *component =
  690. snd_soc_kcontrol_component(kcontrol);
  691. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  692. struct device *tx_dev = NULL;
  693. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  694. return -EINVAL;
  695. ucontrol->value.integer.value[0] = tx_priv->bcs_enable;
  696. return 0;
  697. }
  698. static int lpass_cdc_tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
  699. struct snd_ctl_elem_value *ucontrol)
  700. {
  701. struct snd_soc_component *component =
  702. snd_soc_kcontrol_component(kcontrol);
  703. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  704. struct device *tx_dev = NULL;
  705. int value = ucontrol->value.integer.value[0];
  706. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  707. return -EINVAL;
  708. tx_priv->bcs_enable = value;
  709. return 0;
  710. }
  711. static const char * const bcs_ch_sel_mux_text[] = {
  712. "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
  713. "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
  714. "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11",
  715. };
  716. static const struct soc_enum bcs_ch_sel_mux_enum =
  717. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(bcs_ch_sel_mux_text),
  718. bcs_ch_sel_mux_text);
  719. static int lpass_cdc_tx_macro_get_bcs_ch_sel(struct snd_kcontrol *kcontrol,
  720. struct snd_ctl_elem_value *ucontrol)
  721. {
  722. struct snd_soc_component *component =
  723. snd_soc_kcontrol_component(kcontrol);
  724. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  725. struct device *tx_dev = NULL;
  726. int value = 0;
  727. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  728. return -EINVAL;
  729. value = (snd_soc_component_read(component,
  730. LPASS_CDC_VA_TOP_CSR_SWR_CTRL)) & 0x0F;
  731. ucontrol->value.integer.value[0] = value;
  732. return 0;
  733. }
  734. static int lpass_cdc_tx_macro_put_bcs_ch_sel(struct snd_kcontrol *kcontrol,
  735. struct snd_ctl_elem_value *ucontrol)
  736. {
  737. struct snd_soc_component *component =
  738. snd_soc_kcontrol_component(kcontrol);
  739. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  740. struct device *tx_dev = NULL;
  741. int value;
  742. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  743. return -EINVAL;
  744. if (ucontrol->value.integer.value[0] < 0 ||
  745. ucontrol->value.integer.value[0] > ARRAY_SIZE(bcs_ch_sel_mux_text))
  746. return -EINVAL;
  747. value = ucontrol->value.integer.value[0];
  748. snd_soc_component_update_bits(component,
  749. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F, value);
  750. return 0;
  751. }
  752. static int lpass_cdc_tx_macro_enable_dmic(struct snd_soc_dapm_widget *w,
  753. struct snd_kcontrol *kcontrol, int event, u16 adc_mux0_cfg)
  754. {
  755. struct snd_soc_component *component =
  756. snd_soc_dapm_to_component(w->dapm);
  757. unsigned int dmic = 0;
  758. dmic = (snd_soc_component_read(component, adc_mux0_cfg) >> 4) - 1;
  759. dev_dbg(component->dev, "%s: event %d DMIC%d\n",
  760. __func__, event, dmic);
  761. switch (event) {
  762. case SND_SOC_DAPM_PRE_PMU:
  763. lpass_cdc_dmic_clk_enable(component, dmic, DMIC_TX, true);
  764. break;
  765. case SND_SOC_DAPM_POST_PMD:
  766. lpass_cdc_dmic_clk_enable(component, dmic, DMIC_TX, false);
  767. break;
  768. }
  769. return 0;
  770. }
  771. static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
  772. struct snd_kcontrol *kcontrol, int event)
  773. {
  774. struct snd_soc_component *component =
  775. snd_soc_dapm_to_component(w->dapm);
  776. unsigned int decimator = 0;
  777. u16 tx_vol_ctl_reg = 0;
  778. u16 dec_cfg_reg = 0;
  779. u16 hpf_gate_reg = 0;
  780. u16 tx_gain_ctl_reg = 0;
  781. u16 tx_fs_reg = 0;
  782. u8 hpf_cut_off_freq = 0;
  783. u16 adc_mux_reg = 0;
  784. u16 adc_mux0_reg = 0;
  785. int hpf_delay = LPASS_CDC_TX_MACRO_DMIC_HPF_DELAY_MS;
  786. int unmute_delay = LPASS_CDC_TX_MACRO_DMIC_UNMUTE_DELAY_MS;
  787. struct device *tx_dev = NULL;
  788. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  789. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  790. return -EINVAL;
  791. decimator = w->shift;
  792. dev_dbg(component->dev, "%s(): widget = %s decimator = %u\n", __func__,
  793. w->name, decimator);
  794. tx_vol_ctl_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  795. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  796. hpf_gate_reg = LPASS_CDC_TX0_TX_PATH_SEC2 +
  797. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  798. dec_cfg_reg = LPASS_CDC_TX0_TX_PATH_CFG0 +
  799. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  800. tx_gain_ctl_reg = LPASS_CDC_TX0_TX_VOL_CTL +
  801. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  802. adc_mux_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  803. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  804. adc_mux0_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  805. LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  806. tx_fs_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  807. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  808. tx_priv->pcm_rate[decimator] = (snd_soc_component_read(component,
  809. tx_fs_reg) & 0x0F);
  810. if(!is_amic_enabled(component, decimator))
  811. lpass_cdc_tx_macro_enable_dmic(w, kcontrol, event, adc_mux0_reg);
  812. switch (event) {
  813. case SND_SOC_DAPM_PRE_PMU:
  814. snd_soc_component_update_bits(component,
  815. dec_cfg_reg, 0x06, tx_priv->dec_mode[decimator] <<
  816. LPASS_CDC_TX_MACRO_ADC_MODE_CFG0_SHIFT);
  817. /* Enable TX PGA Mute */
  818. snd_soc_component_update_bits(component,
  819. tx_vol_ctl_reg, 0x10, 0x10);
  820. break;
  821. case SND_SOC_DAPM_POST_PMU:
  822. snd_soc_component_update_bits(component,
  823. tx_vol_ctl_reg, 0x20, 0x20);
  824. if (!is_amic_enabled(component, decimator)) {
  825. snd_soc_component_update_bits(component,
  826. hpf_gate_reg, 0x01, 0x00);
  827. /*
  828. * Minimum 1 clk cycle delay is required as per HW spec
  829. */
  830. usleep_range(1000, 1010);
  831. }
  832. hpf_cut_off_freq = (
  833. snd_soc_component_read(component, dec_cfg_reg) &
  834. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  835. tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq =
  836. hpf_cut_off_freq;
  837. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
  838. snd_soc_component_update_bits(component, dec_cfg_reg,
  839. TX_HPF_CUT_OFF_FREQ_MASK,
  840. CF_MIN_3DB_150HZ << 5);
  841. if (is_amic_enabled(component, decimator)) {
  842. hpf_delay = LPASS_CDC_TX_MACRO_AMIC_HPF_DELAY_MS;
  843. unmute_delay = LPASS_CDC_TX_MACRO_AMIC_UNMUTE_DELAY_MS;
  844. }
  845. if (tx_unmute_delay < unmute_delay)
  846. tx_unmute_delay = unmute_delay;
  847. lpass_cdc_tx_macro_wake_enable(tx_priv, 1);
  848. /* schedule work queue to Remove Mute */
  849. queue_delayed_work(system_freezable_wq,
  850. &tx_priv->tx_mute_dwork[decimator].dwork,
  851. msecs_to_jiffies(tx_unmute_delay));
  852. if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq !=
  853. CF_MIN_3DB_150HZ) {
  854. lpass_cdc_tx_macro_wake_enable(tx_priv, 1);
  855. queue_delayed_work(system_freezable_wq,
  856. &tx_priv->tx_hpf_work[decimator].dwork,
  857. msecs_to_jiffies(hpf_delay));
  858. snd_soc_component_update_bits(component,
  859. hpf_gate_reg, 0x03, 0x02);
  860. if (!is_amic_enabled(component, decimator))
  861. snd_soc_component_update_bits(component,
  862. hpf_gate_reg, 0x03, 0x00);
  863. snd_soc_component_update_bits(component,
  864. hpf_gate_reg, 0x03, 0x01);
  865. /*
  866. * 6ms delay is required as per HW spec
  867. */
  868. usleep_range(6000, 6010);
  869. }
  870. /* apply gain after decimator is enabled */
  871. snd_soc_component_write(component, tx_gain_ctl_reg,
  872. snd_soc_component_read(component,
  873. tx_gain_ctl_reg));
  874. if (tx_priv->bcs_enable) {
  875. snd_soc_component_update_bits(component,
  876. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F,
  877. tx_priv->bcs_ch);
  878. snd_soc_component_update_bits(component, dec_cfg_reg,
  879. 0x01, 0x01);
  880. tx_priv->bcs_clk_en = true;
  881. if (tx_priv->hs_slow_insert_complete)
  882. snd_soc_component_update_bits(component,
  883. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40,
  884. 0x40);
  885. }
  886. break;
  887. case SND_SOC_DAPM_PRE_PMD:
  888. hpf_cut_off_freq =
  889. tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq;
  890. snd_soc_component_update_bits(component,
  891. tx_vol_ctl_reg, 0x10, 0x10);
  892. if (cancel_delayed_work_sync(
  893. &tx_priv->tx_hpf_work[decimator].dwork)) {
  894. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
  895. snd_soc_component_update_bits(
  896. component, dec_cfg_reg,
  897. TX_HPF_CUT_OFF_FREQ_MASK,
  898. hpf_cut_off_freq << 5);
  899. if (is_amic_enabled(component, decimator))
  900. snd_soc_component_update_bits(component,
  901. hpf_gate_reg,
  902. 0x03, 0x02);
  903. else
  904. snd_soc_component_update_bits(component,
  905. hpf_gate_reg,
  906. 0x03, 0x03);
  907. /*
  908. * Minimum 1 clk cycle delay is required
  909. * as per HW spec
  910. */
  911. usleep_range(1000, 1010);
  912. snd_soc_component_update_bits(component,
  913. hpf_gate_reg,
  914. 0x03, 0x01);
  915. }
  916. }
  917. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  918. cancel_delayed_work_sync(
  919. &tx_priv->tx_mute_dwork[decimator].dwork);
  920. lpass_cdc_tx_macro_wake_enable(tx_priv, 0);
  921. if (snd_soc_component_read(component, adc_mux_reg)
  922. & SWR_MIC)
  923. snd_soc_component_update_bits(component,
  924. LPASS_CDC_TX_TOP_CSR_SWR_CTRL,
  925. 0x01, 0x00);
  926. break;
  927. case SND_SOC_DAPM_POST_PMD:
  928. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  929. 0x20, 0x00);
  930. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  931. 0x40, 0x40);
  932. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  933. 0x40, 0x00);
  934. snd_soc_component_update_bits(component,
  935. dec_cfg_reg, 0x06, 0x00);
  936. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  937. 0x10, 0x00);
  938. snd_soc_component_update_bits(component, tx_fs_reg,
  939. 0x0F, 0x04);
  940. if (tx_priv->bcs_enable) {
  941. snd_soc_component_update_bits(component, dec_cfg_reg,
  942. 0x01, 0x00);
  943. snd_soc_component_update_bits(component,
  944. LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, 0x00);
  945. tx_priv->bcs_clk_en = false;
  946. snd_soc_component_update_bits(component,
  947. LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F,
  948. 0x00);
  949. }
  950. break;
  951. }
  952. return 0;
  953. }
  954. static int lpass_cdc_tx_macro_enable_micbias(struct snd_soc_dapm_widget *w,
  955. struct snd_kcontrol *kcontrol, int event)
  956. {
  957. return 0;
  958. }
  959. /* Cutoff frequency for high pass filter */
  960. static const char * const cf_text[] = {
  961. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
  962. };
  963. static SOC_ENUM_SINGLE_DECL(cf_dec0_enum, LPASS_CDC_TX0_TX_PATH_CFG0, 5,
  964. cf_text);
  965. static SOC_ENUM_SINGLE_DECL(cf_dec1_enum, LPASS_CDC_TX1_TX_PATH_CFG0, 5,
  966. cf_text);
  967. static SOC_ENUM_SINGLE_DECL(cf_dec2_enum, LPASS_CDC_TX2_TX_PATH_CFG0, 5,
  968. cf_text);
  969. static SOC_ENUM_SINGLE_DECL(cf_dec3_enum, LPASS_CDC_TX3_TX_PATH_CFG0, 5,
  970. cf_text);
  971. static SOC_ENUM_SINGLE_DECL(cf_dec4_enum, LPASS_CDC_TX4_TX_PATH_CFG0, 5,
  972. cf_text);
  973. static SOC_ENUM_SINGLE_DECL(cf_dec5_enum, LPASS_CDC_TX5_TX_PATH_CFG0, 5,
  974. cf_text);
  975. static SOC_ENUM_SINGLE_DECL(cf_dec6_enum, LPASS_CDC_TX6_TX_PATH_CFG0, 5,
  976. cf_text);
  977. static SOC_ENUM_SINGLE_DECL(cf_dec7_enum, LPASS_CDC_TX7_TX_PATH_CFG0, 5,
  978. cf_text);
  979. static int lpass_cdc_tx_macro_hw_params(struct snd_pcm_substream *substream,
  980. struct snd_pcm_hw_params *params,
  981. struct snd_soc_dai *dai)
  982. {
  983. int tx_fs_rate = -EINVAL;
  984. struct snd_soc_component *component = dai->component;
  985. u32 decimator = 0;
  986. u32 sample_rate = 0;
  987. u16 tx_fs_reg = 0;
  988. struct device *tx_dev = NULL;
  989. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  990. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  991. return -EINVAL;
  992. pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
  993. dai->name, dai->id, params_rate(params),
  994. params_channels(params));
  995. sample_rate = params_rate(params);
  996. switch (sample_rate) {
  997. case 8000:
  998. tx_fs_rate = 0;
  999. break;
  1000. case 16000:
  1001. tx_fs_rate = 1;
  1002. break;
  1003. case 32000:
  1004. tx_fs_rate = 3;
  1005. break;
  1006. case 48000:
  1007. tx_fs_rate = 4;
  1008. break;
  1009. case 96000:
  1010. tx_fs_rate = 5;
  1011. break;
  1012. case 192000:
  1013. tx_fs_rate = 6;
  1014. break;
  1015. case 384000:
  1016. tx_fs_rate = 7;
  1017. break;
  1018. default:
  1019. dev_err_ratelimited(component->dev, "%s: Invalid TX sample rate: %d\n",
  1020. __func__, params_rate(params));
  1021. return -EINVAL;
  1022. }
  1023. for_each_set_bit(decimator, &tx_priv->active_ch_mask[dai->id],
  1024. LPASS_CDC_TX_MACRO_DEC_MAX) {
  1025. if (decimator >= 0) {
  1026. tx_fs_reg = LPASS_CDC_TX0_TX_PATH_CTL +
  1027. LPASS_CDC_TX_MACRO_TX_PATH_OFFSET * decimator;
  1028. dev_dbg(component->dev, "%s: set DEC%u rate to %u\n",
  1029. __func__, decimator, sample_rate);
  1030. snd_soc_component_update_bits(component, tx_fs_reg,
  1031. 0x0F, tx_fs_rate);
  1032. } else {
  1033. dev_err_ratelimited(component->dev,
  1034. "%s: ERROR: Invalid decimator: %d\n",
  1035. __func__, decimator);
  1036. return -EINVAL;
  1037. }
  1038. }
  1039. return 0;
  1040. }
  1041. static int lpass_cdc_tx_macro_get_channel_map(struct snd_soc_dai *dai,
  1042. unsigned int *tx_num, unsigned int *tx_slot,
  1043. unsigned int *rx_num, unsigned int *rx_slot)
  1044. {
  1045. struct snd_soc_component *component = dai->component;
  1046. struct device *tx_dev = NULL;
  1047. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1048. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1049. return -EINVAL;
  1050. switch (dai->id) {
  1051. case LPASS_CDC_TX_MACRO_AIF1_CAP:
  1052. case LPASS_CDC_TX_MACRO_AIF2_CAP:
  1053. case LPASS_CDC_TX_MACRO_AIF3_CAP:
  1054. *tx_slot = tx_priv->active_ch_mask[dai->id];
  1055. *tx_num = tx_priv->active_ch_cnt[dai->id];
  1056. break;
  1057. default:
  1058. dev_err_ratelimited(tx_dev, "%s: Invalid AIF\n", __func__);
  1059. break;
  1060. }
  1061. return 0;
  1062. }
  1063. static struct snd_soc_dai_ops lpass_cdc_tx_macro_dai_ops = {
  1064. .hw_params = lpass_cdc_tx_macro_hw_params,
  1065. .get_channel_map = lpass_cdc_tx_macro_get_channel_map,
  1066. };
  1067. static struct snd_soc_dai_driver lpass_cdc_tx_macro_dai[] = {
  1068. {
  1069. .name = "tx_macro_tx1",
  1070. .id = LPASS_CDC_TX_MACRO_AIF1_CAP,
  1071. .capture = {
  1072. .stream_name = "TX_AIF1 Capture",
  1073. .rates = LPASS_CDC_TX_MACRO_RATES,
  1074. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1075. .rate_max = 192000,
  1076. .rate_min = 8000,
  1077. .channels_min = 1,
  1078. .channels_max = 8,
  1079. },
  1080. .ops = &lpass_cdc_tx_macro_dai_ops,
  1081. },
  1082. {
  1083. .name = "tx_macro_tx2",
  1084. .id = LPASS_CDC_TX_MACRO_AIF2_CAP,
  1085. .capture = {
  1086. .stream_name = "TX_AIF2 Capture",
  1087. .rates = LPASS_CDC_TX_MACRO_RATES,
  1088. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1089. .rate_max = 192000,
  1090. .rate_min = 8000,
  1091. .channels_min = 1,
  1092. .channels_max = 8,
  1093. },
  1094. .ops = &lpass_cdc_tx_macro_dai_ops,
  1095. },
  1096. {
  1097. .name = "tx_macro_tx3",
  1098. .id = LPASS_CDC_TX_MACRO_AIF3_CAP,
  1099. .capture = {
  1100. .stream_name = "TX_AIF3 Capture",
  1101. .rates = LPASS_CDC_TX_MACRO_RATES,
  1102. .formats = LPASS_CDC_TX_MACRO_FORMATS,
  1103. .rate_max = 192000,
  1104. .rate_min = 8000,
  1105. .channels_min = 1,
  1106. .channels_max = 8,
  1107. },
  1108. .ops = &lpass_cdc_tx_macro_dai_ops,
  1109. },
  1110. };
  1111. #define STRING(name) #name
  1112. #define LPASS_CDC_TX_MACRO_DAPM_ENUM(name, reg, offset, text) \
  1113. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1114. static const struct snd_kcontrol_new name##_mux = \
  1115. SOC_DAPM_ENUM(STRING(name), name##_enum)
  1116. #define LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
  1117. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1118. static const struct snd_kcontrol_new name##_mux = \
  1119. SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
  1120. #define LPASS_CDC_TX_MACRO_DAPM_MUX(name, shift, kctl) \
  1121. SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
  1122. static const char * const adc_mux_text[] = {
  1123. "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
  1124. };
  1125. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1,
  1126. 0, adc_mux_text);
  1127. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1,
  1128. 0, adc_mux_text);
  1129. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1,
  1130. 0, adc_mux_text);
  1131. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1,
  1132. 0, adc_mux_text);
  1133. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1,
  1134. 0, adc_mux_text);
  1135. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1,
  1136. 0, adc_mux_text);
  1137. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1,
  1138. 0, adc_mux_text);
  1139. LPASS_CDC_TX_MACRO_DAPM_ENUM(tx_dec7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1,
  1140. 0, adc_mux_text);
  1141. static const char * const dmic_mux_text[] = {
  1142. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
  1143. "DMIC4", "DMIC5", "DMIC6", "DMIC7"
  1144. };
  1145. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0,
  1146. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1147. lpass_cdc_tx_macro_put_dec_enum);
  1148. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0,
  1149. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1150. lpass_cdc_tx_macro_put_dec_enum);
  1151. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0,
  1152. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1153. lpass_cdc_tx_macro_put_dec_enum);
  1154. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0,
  1155. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1156. lpass_cdc_tx_macro_put_dec_enum);
  1157. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0,
  1158. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1159. lpass_cdc_tx_macro_put_dec_enum);
  1160. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0,
  1161. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1162. lpass_cdc_tx_macro_put_dec_enum);
  1163. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0,
  1164. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1165. lpass_cdc_tx_macro_put_dec_enum);
  1166. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0,
  1167. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1168. lpass_cdc_tx_macro_put_dec_enum);
  1169. static const char * const smic_mux_text[] = {
  1170. "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
  1171. "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
  1172. "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11"
  1173. };
  1174. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0,
  1175. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1176. lpass_cdc_tx_macro_put_dec_enum);
  1177. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic1, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0,
  1178. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1179. lpass_cdc_tx_macro_put_dec_enum);
  1180. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0,
  1181. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1182. lpass_cdc_tx_macro_put_dec_enum);
  1183. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic3, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0,
  1184. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1185. lpass_cdc_tx_macro_put_dec_enum);
  1186. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic4, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0,
  1187. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1188. lpass_cdc_tx_macro_put_dec_enum);
  1189. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic5, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0,
  1190. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1191. lpass_cdc_tx_macro_put_dec_enum);
  1192. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic6, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0,
  1193. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1194. lpass_cdc_tx_macro_put_dec_enum);
  1195. LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0,
  1196. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1197. lpass_cdc_tx_macro_put_dec_enum);
  1198. static const char * const dec_mode_mux_text[] = {
  1199. "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
  1200. };
  1201. static const struct soc_enum dec_mode_mux_enum =
  1202. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dec_mode_mux_text),
  1203. dec_mode_mux_text);
  1204. static const char * const bcs_ch_enum_text[] = {
  1205. "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", "CH8", "CH9",
  1206. "CH10", "CH11",
  1207. };
  1208. static const struct soc_enum bcs_ch_enum =
  1209. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(bcs_ch_enum_text),
  1210. bcs_ch_enum_text);
  1211. static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
  1212. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1213. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1214. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1215. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1216. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1217. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1218. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1219. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1220. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1221. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1222. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1223. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1224. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1225. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1226. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1227. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1228. };
  1229. static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
  1230. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1231. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1232. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1233. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1234. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1235. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1236. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1237. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1238. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1239. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1240. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1241. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1242. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1243. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1244. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1245. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1246. };
  1247. static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
  1248. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0,
  1249. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1250. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0,
  1251. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1252. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0,
  1253. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1254. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0,
  1255. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1256. SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC4, 1, 0,
  1257. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1258. SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC5, 1, 0,
  1259. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1260. SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC6, 1, 0,
  1261. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1262. SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC7, 1, 0,
  1263. lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put),
  1264. };
  1265. static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets[] = {
  1266. SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
  1267. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF1_CAP, 0),
  1268. SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
  1269. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF2_CAP, 0),
  1270. SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
  1271. SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF3_CAP, 0),
  1272. SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM,
  1273. LPASS_CDC_TX_MACRO_AIF1_CAP, 0,
  1274. tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
  1275. SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM,
  1276. LPASS_CDC_TX_MACRO_AIF2_CAP, 0,
  1277. tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
  1278. SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM,
  1279. LPASS_CDC_TX_MACRO_AIF3_CAP, 0,
  1280. tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
  1281. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0),
  1282. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1),
  1283. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2),
  1284. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3),
  1285. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4),
  1286. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5),
  1287. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6),
  1288. LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7),
  1289. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0),
  1290. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1),
  1291. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2),
  1292. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3),
  1293. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4),
  1294. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5),
  1295. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6),
  1296. LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7),
  1297. SND_SOC_DAPM_SUPPLY("TX MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1298. lpass_cdc_tx_macro_enable_micbias,
  1299. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1300. SND_SOC_DAPM_ADC("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0),
  1301. SND_SOC_DAPM_ADC("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0),
  1302. SND_SOC_DAPM_ADC("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0),
  1303. SND_SOC_DAPM_ADC("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0),
  1304. SND_SOC_DAPM_ADC("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0),
  1305. SND_SOC_DAPM_ADC("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0),
  1306. SND_SOC_DAPM_ADC("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0),
  1307. SND_SOC_DAPM_ADC("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0),
  1308. SND_SOC_DAPM_INPUT("TX SWR_INPUT"),
  1309. SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
  1310. LPASS_CDC_TX_MACRO_DEC0, 0,
  1311. &tx_dec0_mux, lpass_cdc_tx_macro_enable_dec,
  1312. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1313. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1314. SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
  1315. LPASS_CDC_TX_MACRO_DEC1, 0,
  1316. &tx_dec1_mux, lpass_cdc_tx_macro_enable_dec,
  1317. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1318. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1319. SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
  1320. LPASS_CDC_TX_MACRO_DEC2, 0,
  1321. &tx_dec2_mux, lpass_cdc_tx_macro_enable_dec,
  1322. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1323. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1324. SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
  1325. LPASS_CDC_TX_MACRO_DEC3, 0,
  1326. &tx_dec3_mux, lpass_cdc_tx_macro_enable_dec,
  1327. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1328. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1329. SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
  1330. LPASS_CDC_TX_MACRO_DEC4, 0,
  1331. &tx_dec4_mux, lpass_cdc_tx_macro_enable_dec,
  1332. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1333. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1334. SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
  1335. LPASS_CDC_TX_MACRO_DEC5, 0,
  1336. &tx_dec5_mux, lpass_cdc_tx_macro_enable_dec,
  1337. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1338. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1339. SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
  1340. LPASS_CDC_TX_MACRO_DEC6, 0,
  1341. &tx_dec6_mux, lpass_cdc_tx_macro_enable_dec,
  1342. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1343. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1344. SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
  1345. LPASS_CDC_TX_MACRO_DEC7, 0,
  1346. &tx_dec7_mux, lpass_cdc_tx_macro_enable_dec,
  1347. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1348. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1349. SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
  1350. lpass_cdc_tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1351. };
  1352. static const struct snd_soc_dapm_route tx_audio_map[] = {
  1353. {"TX_AIF1 CAP", NULL, "TX_MCLK"},
  1354. {"TX_AIF2 CAP", NULL, "TX_MCLK"},
  1355. {"TX_AIF3 CAP", NULL, "TX_MCLK"},
  1356. {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
  1357. {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
  1358. {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
  1359. {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1360. {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1361. {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1362. {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1363. {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1364. {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1365. {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1366. {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1367. {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1368. {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1369. {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1370. {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1371. {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1372. {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1373. {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1374. {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1375. {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
  1376. {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
  1377. {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
  1378. {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
  1379. {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
  1380. {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
  1381. {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
  1382. {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
  1383. {"TX DEC0 MUX", NULL, "TX_MCLK"},
  1384. {"TX DEC1 MUX", NULL, "TX_MCLK"},
  1385. {"TX DEC2 MUX", NULL, "TX_MCLK"},
  1386. {"TX DEC3 MUX", NULL, "TX_MCLK"},
  1387. {"TX DEC4 MUX", NULL, "TX_MCLK"},
  1388. {"TX DEC5 MUX", NULL, "TX_MCLK"},
  1389. {"TX DEC6 MUX", NULL, "TX_MCLK"},
  1390. {"TX DEC7 MUX", NULL, "TX_MCLK"},
  1391. {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
  1392. {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
  1393. {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
  1394. {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
  1395. {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
  1396. {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
  1397. {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
  1398. {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
  1399. {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
  1400. {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
  1401. {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT"},
  1402. {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT"},
  1403. {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT"},
  1404. {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT"},
  1405. {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT"},
  1406. {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT"},
  1407. {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT"},
  1408. {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT"},
  1409. {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT"},
  1410. {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT"},
  1411. {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT"},
  1412. {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT"},
  1413. {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
  1414. {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
  1415. {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
  1416. {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
  1417. {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
  1418. {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
  1419. {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
  1420. {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
  1421. {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
  1422. {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
  1423. {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT"},
  1424. {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT"},
  1425. {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT"},
  1426. {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT"},
  1427. {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT"},
  1428. {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT"},
  1429. {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT"},
  1430. {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT"},
  1431. {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT"},
  1432. {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT"},
  1433. {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT"},
  1434. {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT"},
  1435. {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
  1436. {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
  1437. {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
  1438. {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
  1439. {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
  1440. {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
  1441. {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
  1442. {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
  1443. {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
  1444. {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
  1445. {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT"},
  1446. {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT"},
  1447. {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT"},
  1448. {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT"},
  1449. {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT"},
  1450. {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT"},
  1451. {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT"},
  1452. {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT"},
  1453. {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT"},
  1454. {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT"},
  1455. {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT"},
  1456. {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT"},
  1457. {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
  1458. {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
  1459. {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
  1460. {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
  1461. {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
  1462. {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
  1463. {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
  1464. {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
  1465. {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
  1466. {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
  1467. {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT"},
  1468. {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT"},
  1469. {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT"},
  1470. {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT"},
  1471. {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT"},
  1472. {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT"},
  1473. {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT"},
  1474. {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT"},
  1475. {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT"},
  1476. {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT"},
  1477. {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT"},
  1478. {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT"},
  1479. {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
  1480. {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
  1481. {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
  1482. {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
  1483. {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
  1484. {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
  1485. {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
  1486. {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
  1487. {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
  1488. {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
  1489. {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT"},
  1490. {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT"},
  1491. {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT"},
  1492. {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT"},
  1493. {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT"},
  1494. {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT"},
  1495. {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT"},
  1496. {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT"},
  1497. {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT"},
  1498. {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT"},
  1499. {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT"},
  1500. {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT"},
  1501. {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
  1502. {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
  1503. {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
  1504. {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
  1505. {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
  1506. {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
  1507. {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
  1508. {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
  1509. {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
  1510. {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
  1511. {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT"},
  1512. {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT"},
  1513. {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT"},
  1514. {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT"},
  1515. {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT"},
  1516. {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT"},
  1517. {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT"},
  1518. {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT"},
  1519. {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT"},
  1520. {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT"},
  1521. {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT"},
  1522. {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT"},
  1523. {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
  1524. {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
  1525. {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
  1526. {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
  1527. {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
  1528. {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
  1529. {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
  1530. {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
  1531. {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
  1532. {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
  1533. {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT"},
  1534. {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT"},
  1535. {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT"},
  1536. {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT"},
  1537. {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT"},
  1538. {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT"},
  1539. {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT"},
  1540. {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT"},
  1541. {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT"},
  1542. {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT"},
  1543. {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT"},
  1544. {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT"},
  1545. {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
  1546. {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
  1547. {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
  1548. {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
  1549. {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
  1550. {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
  1551. {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
  1552. {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
  1553. {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
  1554. {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
  1555. {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT"},
  1556. {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT"},
  1557. {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT"},
  1558. {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT"},
  1559. {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT"},
  1560. {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT"},
  1561. {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT"},
  1562. {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT"},
  1563. {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT"},
  1564. {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT"},
  1565. {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT"},
  1566. {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT"},
  1567. };
  1568. static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls[] = {
  1569. SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
  1570. LPASS_CDC_TX0_TX_VOL_CTL,
  1571. -84, 40, digital_gain),
  1572. SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
  1573. LPASS_CDC_TX1_TX_VOL_CTL,
  1574. -84, 40, digital_gain),
  1575. SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
  1576. LPASS_CDC_TX2_TX_VOL_CTL,
  1577. -84, 40, digital_gain),
  1578. SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
  1579. LPASS_CDC_TX3_TX_VOL_CTL,
  1580. -84, 40, digital_gain),
  1581. SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
  1582. LPASS_CDC_TX4_TX_VOL_CTL,
  1583. -84, 40, digital_gain),
  1584. SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
  1585. LPASS_CDC_TX5_TX_VOL_CTL,
  1586. -84, 40, digital_gain),
  1587. SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
  1588. LPASS_CDC_TX6_TX_VOL_CTL,
  1589. -84, 40, digital_gain),
  1590. SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
  1591. LPASS_CDC_TX7_TX_VOL_CTL,
  1592. -84, 40, digital_gain),
  1593. SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum,
  1594. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1595. SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum,
  1596. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1597. SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum,
  1598. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1599. SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum,
  1600. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1601. SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum,
  1602. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1603. SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum,
  1604. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1605. SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum,
  1606. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1607. SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum,
  1608. lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put),
  1609. SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
  1610. SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
  1611. SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
  1612. SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
  1613. SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
  1614. SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
  1615. SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
  1616. SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
  1617. SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
  1618. lpass_cdc_tx_macro_get_bcs, lpass_cdc_tx_macro_set_bcs),
  1619. SOC_SINGLE_EXT("TX_SWR_DMIC Enable", SND_SOC_NOPM, 0, 1, 0,
  1620. lpass_cdc_tx_macro_swr_dmic_get, lpass_cdc_tx_macro_swr_dmic_put),
  1621. SOC_ENUM_EXT("BCS Channel", bcs_ch_enum,
  1622. lpass_cdc_tx_macro_bcs_ch_get, lpass_cdc_tx_macro_bcs_ch_put),
  1623. SOC_ENUM_EXT("BCS CH_SEL", bcs_ch_sel_mux_enum,
  1624. lpass_cdc_tx_macro_get_bcs_ch_sel, lpass_cdc_tx_macro_put_bcs_ch_sel),
  1625. };
  1626. static int lpass_cdc_tx_macro_clk_div_get(struct snd_soc_component *component)
  1627. {
  1628. struct device *tx_dev = NULL;
  1629. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1630. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1631. return -EINVAL;
  1632. return (int)tx_priv->dmic_clk_div;
  1633. }
  1634. static int lpass_cdc_tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
  1635. struct lpass_cdc_tx_macro_priv *tx_priv)
  1636. {
  1637. u32 div_factor = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1638. u32 mclk_rate = LPASS_CDC_TX_MACRO_MCLK_FREQ;
  1639. if (dmic_sample_rate == LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED ||
  1640. mclk_rate % dmic_sample_rate != 0)
  1641. goto undefined_rate;
  1642. div_factor = mclk_rate / dmic_sample_rate;
  1643. switch (div_factor) {
  1644. case 2:
  1645. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1646. break;
  1647. case 3:
  1648. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_3;
  1649. break;
  1650. case 4:
  1651. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_4;
  1652. break;
  1653. case 6:
  1654. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_6;
  1655. break;
  1656. case 8:
  1657. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_8;
  1658. break;
  1659. case 16:
  1660. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_16;
  1661. break;
  1662. default:
  1663. /* Any other DIV factor is invalid */
  1664. goto undefined_rate;
  1665. }
  1666. /* Valid dmic DIV factors */
  1667. dev_dbg(tx_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
  1668. __func__, div_factor, mclk_rate);
  1669. return dmic_sample_rate;
  1670. undefined_rate:
  1671. dev_dbg(tx_priv->dev, "%s: Invalid rate %d, for mclk %d\n",
  1672. __func__, dmic_sample_rate, mclk_rate);
  1673. dmic_sample_rate = LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED;
  1674. return dmic_sample_rate;
  1675. }
  1676. static const struct lpass_cdc_tx_macro_reg_mask_val
  1677. lpass_cdc_tx_macro_reg_init[] = {
  1678. {LPASS_CDC_TX0_TX_PATH_SEC7, 0x3F, 0x0A},
  1679. };
  1680. static int lpass_cdc_tx_macro_init(struct snd_soc_component *component)
  1681. {
  1682. struct snd_soc_dapm_context *dapm =
  1683. snd_soc_component_get_dapm(component);
  1684. int ret = 0, i = 0;
  1685. struct device *tx_dev = NULL;
  1686. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1687. tx_dev = lpass_cdc_get_device_ptr(component->dev, TX_MACRO);
  1688. if (!tx_dev) {
  1689. dev_err(component->dev,
  1690. "%s: null device for macro!\n", __func__);
  1691. return -EINVAL;
  1692. }
  1693. tx_priv = dev_get_drvdata(tx_dev);
  1694. if (!tx_priv) {
  1695. dev_err(component->dev,
  1696. "%s: priv is null for macro!\n", __func__);
  1697. return -EINVAL;
  1698. }
  1699. tx_priv->version = lpass_cdc_get_version(tx_dev);
  1700. ret = snd_soc_dapm_new_controls(dapm, lpass_cdc_tx_macro_dapm_widgets,
  1701. ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets));
  1702. if (ret < 0) {
  1703. dev_err(tx_dev, "%s: Failed to add controls\n",
  1704. __func__);
  1705. return ret;
  1706. }
  1707. ret = snd_soc_dapm_add_routes(dapm, tx_audio_map,
  1708. ARRAY_SIZE(tx_audio_map));
  1709. if (ret < 0) {
  1710. dev_err(tx_dev, "%s: Failed to add routes\n",
  1711. __func__);
  1712. return ret;
  1713. }
  1714. ret = snd_soc_dapm_new_widgets(dapm->card);
  1715. if (ret < 0) {
  1716. dev_err(tx_dev, "%s: Failed to add widgets\n", __func__);
  1717. return ret;
  1718. }
  1719. ret = snd_soc_add_component_controls(component,
  1720. lpass_cdc_tx_macro_snd_controls,
  1721. ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls));
  1722. if (ret < 0) {
  1723. dev_err(tx_dev, "%s: Failed to add snd_ctls\n",
  1724. __func__);
  1725. return ret;
  1726. }
  1727. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF1 Capture");
  1728. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF2 Capture");
  1729. snd_soc_dapm_ignore_suspend(dapm, "TX_AIF3 Capture");
  1730. snd_soc_dapm_ignore_suspend(dapm, "TX SWR_INPUT");
  1731. snd_soc_dapm_sync(dapm);
  1732. for (i = 0; i < NUM_DECIMATORS; i++) {
  1733. tx_priv->tx_hpf_work[i].tx_priv = tx_priv;
  1734. tx_priv->tx_hpf_work[i].decimator = i;
  1735. INIT_DELAYED_WORK(&tx_priv->tx_hpf_work[i].dwork,
  1736. lpass_cdc_tx_macro_tx_hpf_corner_freq_callback);
  1737. }
  1738. for (i = 0; i < NUM_DECIMATORS; i++) {
  1739. tx_priv->tx_mute_dwork[i].tx_priv = tx_priv;
  1740. tx_priv->tx_mute_dwork[i].decimator = i;
  1741. INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork,
  1742. lpass_cdc_tx_macro_mute_update_callback);
  1743. }
  1744. tx_priv->component = component;
  1745. for (i = 0; i < ARRAY_SIZE(lpass_cdc_tx_macro_reg_init); i++)
  1746. snd_soc_component_update_bits(component,
  1747. lpass_cdc_tx_macro_reg_init[i].reg,
  1748. lpass_cdc_tx_macro_reg_init[i].mask,
  1749. lpass_cdc_tx_macro_reg_init[i].val);
  1750. return 0;
  1751. }
  1752. static int lpass_cdc_tx_macro_deinit(struct snd_soc_component *component)
  1753. {
  1754. struct device *tx_dev = NULL;
  1755. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1756. if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
  1757. return -EINVAL;
  1758. tx_priv->component = NULL;
  1759. return 0;
  1760. }
  1761. static void lpass_cdc_tx_macro_init_ops(struct macro_ops *ops,
  1762. char __iomem *tx_io_base)
  1763. {
  1764. memset(ops, 0, sizeof(struct macro_ops));
  1765. ops->init = lpass_cdc_tx_macro_init;
  1766. ops->exit = lpass_cdc_tx_macro_deinit;
  1767. ops->io_base = tx_io_base;
  1768. ops->dai_ptr = lpass_cdc_tx_macro_dai;
  1769. ops->num_dais = ARRAY_SIZE(lpass_cdc_tx_macro_dai);
  1770. ops->event_handler = lpass_cdc_tx_macro_event_handler;
  1771. ops->clk_div_get = lpass_cdc_tx_macro_clk_div_get;
  1772. ops->clk_enable = __lpass_cdc_tx_macro_mclk_enable;
  1773. }
  1774. static int lpass_cdc_tx_macro_probe(struct platform_device *pdev)
  1775. {
  1776. struct macro_ops ops = {0};
  1777. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1778. u32 tx_base_addr = 0, sample_rate = 0;
  1779. char __iomem *tx_io_base = NULL;
  1780. int ret = 0;
  1781. const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate";
  1782. if (!lpass_cdc_is_va_macro_registered(&pdev->dev)) {
  1783. dev_err(&pdev->dev,
  1784. "%s: va-macro not registered yet, defer\n", __func__);
  1785. return -EPROBE_DEFER;
  1786. }
  1787. tx_priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_tx_macro_priv),
  1788. GFP_KERNEL);
  1789. if (!tx_priv)
  1790. return -ENOMEM;
  1791. platform_set_drvdata(pdev, tx_priv);
  1792. tx_priv->dev = &pdev->dev;
  1793. ret = of_property_read_u32(pdev->dev.of_node, "reg",
  1794. &tx_base_addr);
  1795. if (ret) {
  1796. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  1797. __func__, "reg");
  1798. return ret;
  1799. }
  1800. dev_set_drvdata(&pdev->dev, tx_priv);
  1801. tx_io_base = devm_ioremap(&pdev->dev,
  1802. tx_base_addr, LPASS_CDC_TX_MACRO_MAX_OFFSET);
  1803. if (!tx_io_base) {
  1804. dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);
  1805. return -ENOMEM;
  1806. }
  1807. tx_priv->tx_io_base = tx_io_base;
  1808. tx_priv->swr_dmic_enable = false;
  1809. tx_priv->wlock_holders = 0;
  1810. ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate,
  1811. &sample_rate);
  1812. if (ret) {
  1813. dev_err(&pdev->dev,
  1814. "%s: could not find sample_rate entry in dt\n",
  1815. __func__);
  1816. tx_priv->dmic_clk_div = LPASS_CDC_TX_MACRO_CLK_DIV_2;
  1817. } else {
  1818. if (lpass_cdc_tx_macro_validate_dmic_sample_rate(
  1819. sample_rate, tx_priv) == LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED)
  1820. return -EINVAL;
  1821. }
  1822. mutex_init(&tx_priv->mclk_lock);
  1823. mutex_init(&tx_priv->wlock);
  1824. lpass_cdc_tx_macro_init_ops(&ops, tx_io_base);
  1825. ops.clk_id_req = TX_CORE_CLK;
  1826. ops.default_clk_id = TX_CORE_CLK;
  1827. ret = lpass_cdc_register_macro(&pdev->dev, TX_MACRO, &ops);
  1828. if (ret) {
  1829. dev_err(&pdev->dev,
  1830. "%s: register macro failed\n", __func__);
  1831. goto err_reg_macro;
  1832. }
  1833. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
  1834. pm_runtime_use_autosuspend(&pdev->dev);
  1835. pm_runtime_set_suspended(&pdev->dev);
  1836. pm_suspend_ignore_children(&pdev->dev, true);
  1837. pm_runtime_enable(&pdev->dev);
  1838. return 0;
  1839. err_reg_macro:
  1840. mutex_destroy(&tx_priv->mclk_lock);
  1841. mutex_destroy(&tx_priv->wlock);
  1842. return ret;
  1843. }
  1844. static int lpass_cdc_tx_macro_remove(struct platform_device *pdev)
  1845. {
  1846. struct lpass_cdc_tx_macro_priv *tx_priv = NULL;
  1847. tx_priv = platform_get_drvdata(pdev);
  1848. if (!tx_priv)
  1849. return -EINVAL;
  1850. pm_runtime_disable(&pdev->dev);
  1851. pm_runtime_set_suspended(&pdev->dev);
  1852. mutex_destroy(&tx_priv->mclk_lock);
  1853. mutex_destroy(&tx_priv->wlock);
  1854. lpass_cdc_unregister_macro(&pdev->dev, TX_MACRO);
  1855. return 0;
  1856. }
  1857. static const struct of_device_id lpass_cdc_tx_macro_dt_match[] = {
  1858. {.compatible = "qcom,lpass-cdc-tx-macro"},
  1859. {}
  1860. };
  1861. static const struct dev_pm_ops lpass_cdc_dev_pm_ops = {
  1862. SET_SYSTEM_SLEEP_PM_OPS(
  1863. pm_runtime_force_suspend,
  1864. pm_runtime_force_resume
  1865. )
  1866. SET_RUNTIME_PM_OPS(
  1867. lpass_cdc_runtime_suspend,
  1868. lpass_cdc_runtime_resume,
  1869. NULL
  1870. )
  1871. };
  1872. static struct platform_driver lpass_cdc_tx_macro_driver = {
  1873. .driver = {
  1874. .name = "lpass_cdc_tx_macro",
  1875. .owner = THIS_MODULE,
  1876. .pm = &lpass_cdc_dev_pm_ops,
  1877. .of_match_table = lpass_cdc_tx_macro_dt_match,
  1878. .suppress_bind_attrs = true,
  1879. },
  1880. .probe = lpass_cdc_tx_macro_probe,
  1881. .remove = lpass_cdc_tx_macro_remove,
  1882. };
  1883. module_platform_driver(lpass_cdc_tx_macro_driver);
  1884. MODULE_DESCRIPTION("TX macro driver");
  1885. MODULE_LICENSE("GPL v2");