holi.c 191 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <linux/nvmem-consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <soc/snd_event.h>
  24. #include <dsp/audio_notifier.h>
  25. #include <soc/swr-common.h>
  26. #include <dsp/q6afe-v2.h>
  27. #include <dsp/q6core.h>
  28. #include <soc/soundwire.h>
  29. #include "device_event.h"
  30. #include "msm-pcm-routing-v2.h"
  31. #include "asoc/msm-cdc-pinctrl.h"
  32. #include "asoc/wcd-mbhc-v2.h"
  33. #include "codecs/wsa881x-analog.h"
  34. #include "codecs/wcd937x/wcd937x-mbhc.h"
  35. #include "codecs/wcd937x/wcd937x.h"
  36. #include "codecs/wcd938x/wcd938x-mbhc.h"
  37. #include "codecs/wcd938x/wcd938x.h"
  38. #include "codecs/bolero/bolero-cdc.h"
  39. #include <dt-bindings/sound/audio-codec-port-types.h>
  40. #include "holi-port-config.h"
  41. #include "msm_holi_dailink.h"
  42. #define DRV_NAME "holi-asoc-snd"
  43. #define __CHIPSET__ "HOLI "
  44. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  45. #define SAMPLING_RATE_8KHZ 8000
  46. #define SAMPLING_RATE_11P025KHZ 11025
  47. #define SAMPLING_RATE_16KHZ 16000
  48. #define SAMPLING_RATE_22P05KHZ 22050
  49. #define SAMPLING_RATE_32KHZ 32000
  50. #define SAMPLING_RATE_44P1KHZ 44100
  51. #define SAMPLING_RATE_48KHZ 48000
  52. #define SAMPLING_RATE_88P2KHZ 88200
  53. #define SAMPLING_RATE_96KHZ 96000
  54. #define SAMPLING_RATE_176P4KHZ 176400
  55. #define SAMPLING_RATE_192KHZ 192000
  56. #define SAMPLING_RATE_352P8KHZ 352800
  57. #define SAMPLING_RATE_384KHZ 384000
  58. #define IS_FRACTIONAL(x) \
  59. ((x == SAMPLING_RATE_11P025KHZ) || (x == SAMPLING_RATE_22P05KHZ) || \
  60. (x == SAMPLING_RATE_44P1KHZ) || (x == SAMPLING_RATE_88P2KHZ) || \
  61. (x == SAMPLING_RATE_176P4KHZ) || (x == SAMPLING_RATE_352P8KHZ))
  62. #define IS_MSM_INTERFACE_MI2S(x) \
  63. ((x == PRIM_MI2S) || (x == SEC_MI2S) || (x == TERT_MI2S))
  64. #define WCD9XXX_MBHC_DEF_RLOADS 5
  65. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  66. #define CODEC_EXT_CLK_RATE 9600000
  67. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  68. #define DEV_NAME_STR_LEN 32
  69. #define WCD_MBHC_HS_V_MAX 1600
  70. #define TDM_CHANNEL_MAX 8
  71. #define DEV_NAME_STR_LEN 32
  72. /* time in us to ensure LPM doesn't go in C3/C4 */
  73. #define MSM_LL_QOS_VALUE 300
  74. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  75. #define WCN_CDC_SLIM_RX_CH_MAX 2
  76. #define WCN_CDC_SLIM_TX_CH_MAX 2
  77. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  78. enum {
  79. RX_PATH = 0,
  80. TX_PATH,
  81. MAX_PATH,
  82. };
  83. enum {
  84. TDM_0 = 0,
  85. TDM_1,
  86. TDM_2,
  87. TDM_3,
  88. TDM_4,
  89. TDM_5,
  90. TDM_6,
  91. TDM_7,
  92. TDM_PORT_MAX,
  93. };
  94. #define TDM_MAX_SLOTS 8
  95. #define TDM_SLOT_WIDTH_BITS 32
  96. enum {
  97. TDM_PRI = 0,
  98. TDM_SEC,
  99. TDM_TERT,
  100. TDM_QUAT,
  101. TDM_INTERFACE_MAX,
  102. };
  103. enum {
  104. PRIM_AUX_PCM = 0,
  105. SEC_AUX_PCM,
  106. TERT_AUX_PCM,
  107. QUAT_AUX_PCM,
  108. AUX_PCM_MAX,
  109. };
  110. enum {
  111. PRIM_MI2S = 0,
  112. SEC_MI2S,
  113. TERT_MI2S,
  114. QUAT_MI2S,
  115. MI2S_MAX,
  116. };
  117. enum {
  118. RX_CDC_DMA_RX_0 = 0,
  119. RX_CDC_DMA_RX_1,
  120. RX_CDC_DMA_RX_2,
  121. RX_CDC_DMA_RX_3,
  122. RX_CDC_DMA_RX_5,
  123. RX_CDC_DMA_RX_6,
  124. CDC_DMA_RX_MAX,
  125. };
  126. enum {
  127. TX_CDC_DMA_TX_0 = 0,
  128. TX_CDC_DMA_TX_3,
  129. TX_CDC_DMA_TX_4,
  130. VA_CDC_DMA_TX_0,
  131. VA_CDC_DMA_TX_1,
  132. VA_CDC_DMA_TX_2,
  133. CDC_DMA_TX_MAX,
  134. };
  135. enum {
  136. SLIM_RX_7 = 0,
  137. SLIM_RX_MAX,
  138. };
  139. enum {
  140. SLIM_TX_7 = 0,
  141. SLIM_TX_8,
  142. SLIM_TX_MAX,
  143. };
  144. enum {
  145. AFE_LOOPBACK_TX_IDX = 0,
  146. AFE_LOOPBACK_TX_IDX_MAX,
  147. };
  148. struct msm_asoc_mach_data {
  149. struct snd_info_entry *codec_root;
  150. int usbc_en2_gpio; /* used by gpio driver API */
  151. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  153. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  154. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  155. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  156. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  157. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  158. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  159. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  160. bool is_afe_config_done;
  161. struct device_node *fsa_handle;
  162. struct clk *lpass_audio_hw_vote;
  163. int core_audio_vote_count;
  164. u32 wcd_disabled;
  165. };
  166. struct tdm_port {
  167. u32 mode;
  168. u32 channel;
  169. };
  170. struct tdm_dev_config {
  171. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  172. };
  173. struct dev_config {
  174. u32 sample_rate;
  175. u32 bit_format;
  176. u32 channels;
  177. };
  178. /* Default configuration of slimbus channels */
  179. static struct dev_config slim_rx_cfg[] = {
  180. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  181. };
  182. static struct dev_config slim_tx_cfg[] = {
  183. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  184. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  185. };
  186. static struct dev_config usb_rx_cfg = {
  187. .sample_rate = SAMPLING_RATE_48KHZ,
  188. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  189. .channels = 2,
  190. };
  191. static struct dev_config usb_tx_cfg = {
  192. .sample_rate = SAMPLING_RATE_48KHZ,
  193. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  194. .channels = 1,
  195. };
  196. static struct dev_config proxy_rx_cfg = {
  197. .sample_rate = SAMPLING_RATE_48KHZ,
  198. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  199. .channels = 2,
  200. };
  201. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  202. {
  203. AFE_API_VERSION_I2S_CONFIG,
  204. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  205. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  206. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  207. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  208. 0,
  209. },
  210. {
  211. AFE_API_VERSION_I2S_CONFIG,
  212. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  213. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  214. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  215. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  216. 0,
  217. },
  218. {
  219. AFE_API_VERSION_I2S_CONFIG,
  220. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  221. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  222. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  223. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  224. 0,
  225. },
  226. {
  227. AFE_API_VERSION_I2S_CONFIG,
  228. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  229. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  230. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  231. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  232. 0,
  233. },
  234. };
  235. struct mi2s_conf {
  236. struct mutex lock;
  237. u32 ref_cnt;
  238. u32 msm_is_mi2s_master;
  239. };
  240. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  241. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  242. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  243. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  244. };
  245. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  246. /* Default configuration of TDM channels */
  247. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  248. { /* PRI TDM */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  257. },
  258. { /* SEC TDM */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  267. },
  268. { /* TERT TDM */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  277. },
  278. { /* QUAT TDM */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  287. },
  288. };
  289. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  290. { /* PRI TDM */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  299. },
  300. { /* SEC TDM */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  309. },
  310. { /* TERT TDM */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  319. },
  320. { /* QUAT TDM */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  328. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  329. },
  330. };
  331. /* Default configuration of AUX PCM channels */
  332. static struct dev_config aux_pcm_rx_cfg[] = {
  333. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  337. };
  338. static struct dev_config aux_pcm_tx_cfg[] = {
  339. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  340. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  343. };
  344. /* Default configuration of MI2S channels */
  345. static struct dev_config mi2s_rx_cfg[] = {
  346. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. };
  351. static struct dev_config mi2s_tx_cfg[] = {
  352. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  353. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  354. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  355. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  356. };
  357. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  358. { /* PRI TDM */
  359. { {0, 4, 0xFFFF} }, /* RX_0 */
  360. { {8, 12, 0xFFFF} }, /* RX_1 */
  361. { {16, 20, 0xFFFF} }, /* RX_2 */
  362. { {24, 28, 0xFFFF} }, /* RX_3 */
  363. { {0xFFFF} }, /* RX_4 */
  364. { {0xFFFF} }, /* RX_5 */
  365. { {0xFFFF} }, /* RX_6 */
  366. { {0xFFFF} }, /* RX_7 */
  367. },
  368. {
  369. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  370. { {8, 12, 0xFFFF} }, /* TX_1 */
  371. { {16, 20, 0xFFFF} }, /* TX_2 */
  372. { {24, 28, 0xFFFF} }, /* TX_3 */
  373. { {0xFFFF} }, /* TX_4 */
  374. { {0xFFFF} }, /* TX_5 */
  375. { {0xFFFF} }, /* TX_6 */
  376. { {0xFFFF} }, /* TX_7 */
  377. },
  378. };
  379. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  380. { /* SEC TDM */
  381. { {0, 4, 0xFFFF} }, /* RX_0 */
  382. { {8, 12, 0xFFFF} }, /* RX_1 */
  383. { {16, 20, 0xFFFF} }, /* RX_2 */
  384. { {24, 28, 0xFFFF} }, /* RX_3 */
  385. { {0xFFFF} }, /* RX_4 */
  386. { {0xFFFF} }, /* RX_5 */
  387. { {0xFFFF} }, /* RX_6 */
  388. { {0xFFFF} }, /* RX_7 */
  389. },
  390. {
  391. { {0, 4, 0xFFFF} }, /* TX_0 */
  392. { {8, 12, 0xFFFF} }, /* TX_1 */
  393. { {16, 20, 0xFFFF} }, /* TX_2 */
  394. { {24, 28, 0xFFFF} }, /* TX_3 */
  395. { {0xFFFF} }, /* TX_4 */
  396. { {0xFFFF} }, /* TX_5 */
  397. { {0xFFFF} }, /* TX_6 */
  398. { {0xFFFF} }, /* TX_7 */
  399. },
  400. };
  401. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  402. { /* TERT TDM */
  403. { {0, 4, 0xFFFF} }, /* RX_0 */
  404. { {8, 12, 0xFFFF} }, /* RX_1 */
  405. { {16, 20, 0xFFFF} }, /* RX_2 */
  406. { {24, 28, 0xFFFF} }, /* RX_3 */
  407. { {0xFFFF} }, /* RX_4 */
  408. { {0xFFFF} }, /* RX_5 */
  409. { {0xFFFF} }, /* RX_6 */
  410. { {0xFFFF} }, /* RX_7 */
  411. },
  412. {
  413. { {0, 4, 0xFFFF} }, /* TX_0 */
  414. { {8, 12, 0xFFFF} }, /* TX_1 */
  415. { {16, 20, 0xFFFF} }, /* TX_2 */
  416. { {24, 28, 0xFFFF} }, /* TX_3 */
  417. { {0xFFFF} }, /* TX_4 */
  418. { {0xFFFF} }, /* TX_5 */
  419. { {0xFFFF} }, /* TX_6 */
  420. { {0xFFFF} }, /* TX_7 */
  421. },
  422. };
  423. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  424. { /* QUAT TDM */
  425. { {0, 4, 0xFFFF} }, /* RX_0 */
  426. { {8, 12, 0xFFFF} }, /* RX_1 */
  427. { {16, 20, 0xFFFF} }, /* RX_2 */
  428. { {24, 28, 0xFFFF} }, /* RX_3 */
  429. { {0xFFFF} }, /* RX_4 */
  430. { {0xFFFF} }, /* RX_5 */
  431. { {0xFFFF} }, /* RX_6 */
  432. { {0xFFFF} }, /* RX_7 */
  433. },
  434. {
  435. { {0, 4, 0xFFFF} }, /* TX_0 */
  436. { {8, 12, 0xFFFF} }, /* TX_1 */
  437. { {16, 20, 0xFFFF} }, /* TX_2 */
  438. { {24, 28, 0xFFFF} }, /* TX_3 */
  439. { {0xFFFF} }, /* TX_4 */
  440. { {0xFFFF} }, /* TX_5 */
  441. { {0xFFFF} }, /* TX_6 */
  442. { {0xFFFF} }, /* TX_7 */
  443. },
  444. };
  445. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  446. pri_tdm_dev_config,
  447. sec_tdm_dev_config,
  448. tert_tdm_dev_config,
  449. quat_tdm_dev_config,
  450. };
  451. /* Default configuration of Codec DMA Interface RX */
  452. static struct dev_config cdc_dma_rx_cfg[] = {
  453. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  454. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  455. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  456. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  457. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  458. [RX_CDC_DMA_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  459. };
  460. /* Default configuration of Codec DMA Interface TX */
  461. static struct dev_config cdc_dma_tx_cfg[] = {
  462. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  463. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  464. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  465. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  466. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  467. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  468. };
  469. static struct dev_config afe_loopback_tx_cfg[] = {
  470. [AFE_LOOPBACK_TX_IDX] =
  471. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  472. };
  473. static int msm_vi_feed_tx_ch = 2;
  474. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  475. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  476. "S32_LE"};
  477. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  478. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  479. "Six", "Seven", "Eight"};
  480. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  481. "KHZ_16", "KHZ_22P05",
  482. "KHZ_32", "KHZ_44P1", "KHZ_48",
  483. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  484. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  485. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  486. "Five", "Six", "Seven",
  487. "Eight"};
  488. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  489. "KHZ_48", "KHZ_176P4",
  490. "KHZ_352P8"};
  491. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  492. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  493. "Five", "Six", "Seven", "Eight"};
  494. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  495. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  496. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  497. "KHZ_48", "KHZ_88P2", "KHZ_96",
  498. "KHZ_176P4", "KHZ_192", "KHZ_352P8",
  499. "KHZ_384"};
  500. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  501. "Five", "Six", "Seven",
  502. "Eight"};
  503. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  504. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  505. "Five", "Six", "Seven",
  506. "Eight"};
  507. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  508. "KHZ_16", "KHZ_22P05",
  509. "KHZ_32", "KHZ_44P1", "KHZ_48",
  510. "KHZ_88P2", "KHZ_96",
  511. "KHZ_176P4", "KHZ_192",
  512. "KHZ_352P8", "KHZ_384"};
  513. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  514. "KHZ_16", "KHZ_22P05",
  515. "KHZ_32", "KHZ_44P1", "KHZ_48",
  516. "KHZ_88P2", "KHZ_96",
  517. "KHZ_176P4", "KHZ_192"};
  518. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  519. "KHZ_44P1", "KHZ_48",
  520. "KHZ_88P2", "KHZ_96"};
  521. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  522. "KHZ_44P1", "KHZ_48",
  523. "KHZ_88P2", "KHZ_96"};
  524. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  525. "KHZ_44P1", "KHZ_48",
  526. "KHZ_88P2", "KHZ_96"};
  527. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  528. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  589. cdc_dma_sample_rate_text);
  590. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  591. cdc_dma_sample_rate_text);
  592. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  593. cdc_dma_sample_rate_text);
  594. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  595. cdc_dma_sample_rate_text);
  596. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  597. cdc_dma_sample_rate_text);
  598. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  599. cdc_dma_sample_rate_text);
  600. /* WCD9380 */
  601. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  602. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  604. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  606. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_format, cdc80_bit_format_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  608. cdc80_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  610. cdc80_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  612. cdc80_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  614. cdc80_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  616. cdc80_dma_sample_rate_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_sample_rate,
  618. cdc80_dma_sample_rate_text);
  619. /* WCD9385 */
  620. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_format, bit_format_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  627. cdc_dma_sample_rate_text);
  628. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  629. cdc_dma_sample_rate_text);
  630. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  631. cdc_dma_sample_rate_text);
  632. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  633. cdc_dma_sample_rate_text);
  634. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  635. cdc_dma_sample_rate_text);
  636. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_sample_rate,
  637. cdc_dma_sample_rate_text);
  638. /* WCD937x */
  639. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  640. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  641. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  642. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  643. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  644. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  645. cdc_dma_sample_rate_text);
  646. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  647. cdc_dma_sample_rate_text);
  648. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  649. cdc_dma_sample_rate_text);
  650. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  651. cdc_dma_sample_rate_text);
  652. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  653. cdc_dma_sample_rate_text);
  654. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  655. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  656. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  657. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  658. static bool is_initial_boot;
  659. static bool codec_reg_done;
  660. static struct snd_soc_card snd_soc_card_holi_msm;
  661. static int dmic_0_1_gpio_cnt;
  662. static int dmic_2_3_gpio_cnt;
  663. static int dmic_4_5_gpio_cnt;
  664. static void *def_wcd_mbhc_cal(void);
  665. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *);
  666. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *);
  667. /*
  668. * Need to report LINEIN
  669. * if R/L channel impedance is larger than 5K ohm
  670. */
  671. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  672. .read_fw_bin = false,
  673. .calibration = NULL,
  674. .detect_extn_cable = true,
  675. .mono_stero_detection = false,
  676. .swap_gnd_mic = NULL,
  677. .hs_ext_micbias = true,
  678. .key_code[0] = KEY_MEDIA,
  679. .key_code[1] = KEY_VOICECOMMAND,
  680. .key_code[2] = KEY_VOLUMEUP,
  681. .key_code[3] = KEY_VOLUMEDOWN,
  682. .key_code[4] = 0,
  683. .key_code[5] = 0,
  684. .key_code[6] = 0,
  685. .key_code[7] = 0,
  686. .linein_th = 5000,
  687. .moisture_en = false,
  688. .mbhc_micbias = MIC_BIAS_2,
  689. .anc_micbias = MIC_BIAS_2,
  690. .enable_anc_mic_detect = false,
  691. .moisture_duty_cycle_en = true,
  692. };
  693. /* set audio task affinity to core 1 & 2 */
  694. static const unsigned int audio_core_list[] = {1, 2};
  695. static cpumask_t audio_cpu_map = CPU_MASK_NONE;
  696. static struct dev_pm_qos_request *msm_audio_req = NULL;
  697. static unsigned int qos_client_active_cnt = 0;
  698. static void msm_audio_add_qos_request()
  699. {
  700. int i;
  701. int cpu = 0;
  702. msm_audio_req = kzalloc(sizeof(struct dev_pm_qos_request) * NR_CPUS,
  703. GFP_KERNEL);
  704. if (!msm_audio_req) {
  705. pr_err("%s failed to alloc mem for qos req.\n", __func__);
  706. return;
  707. }
  708. for (i = 0; i < ARRAY_SIZE(audio_core_list); i++) {
  709. if (audio_core_list[i] >= NR_CPUS)
  710. pr_err("%s incorrect cpu id: %d specified.\n",
  711. __func__, audio_core_list[i]);
  712. else
  713. cpumask_set_cpu(audio_core_list[i], &audio_cpu_map);
  714. }
  715. for_each_cpu(cpu, &audio_cpu_map) {
  716. dev_pm_qos_add_request(get_cpu_device(cpu),
  717. &msm_audio_req[cpu],
  718. DEV_PM_QOS_RESUME_LATENCY,
  719. PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE);
  720. pr_debug("%s set cpu affinity to core %d.\n", __func__, cpu);
  721. }
  722. }
  723. static void msm_audio_remove_qos_request()
  724. {
  725. int cpu = 0;
  726. if (msm_audio_req) {
  727. for_each_cpu(cpu, &audio_cpu_map) {
  728. dev_pm_qos_remove_request(
  729. &msm_audio_req[cpu]);
  730. pr_debug("%s remove cpu affinity of core %d.\n",
  731. __func__, cpu);
  732. }
  733. kfree(msm_audio_req);
  734. }
  735. }
  736. static void msm_audio_update_qos_request(u32 latency)
  737. {
  738. int cpu = 0;
  739. if (msm_audio_req) {
  740. for_each_cpu(cpu, &audio_cpu_map) {
  741. dev_pm_qos_update_request(
  742. &msm_audio_req[cpu], latency);
  743. pr_debug("%s update latency of core %d to %ul.\n",
  744. __func__, cpu, latency);
  745. }
  746. }
  747. }
  748. static inline int param_is_mask(int p)
  749. {
  750. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  751. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  752. }
  753. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  754. int n)
  755. {
  756. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  757. }
  758. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  759. unsigned int bit)
  760. {
  761. if (bit >= SNDRV_MASK_MAX)
  762. return;
  763. if (param_is_mask(n)) {
  764. struct snd_mask *m = param_to_mask(p, n);
  765. m->bits[0] = 0;
  766. m->bits[1] = 0;
  767. m->bits[bit >> 5] |= (1 << (bit & 31));
  768. }
  769. }
  770. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  771. struct snd_ctl_elem_value *ucontrol)
  772. {
  773. int sample_rate_val = 0;
  774. switch (usb_rx_cfg.sample_rate) {
  775. case SAMPLING_RATE_384KHZ:
  776. sample_rate_val = 12;
  777. break;
  778. case SAMPLING_RATE_352P8KHZ:
  779. sample_rate_val = 11;
  780. break;
  781. case SAMPLING_RATE_192KHZ:
  782. sample_rate_val = 10;
  783. break;
  784. case SAMPLING_RATE_176P4KHZ:
  785. sample_rate_val = 9;
  786. break;
  787. case SAMPLING_RATE_96KHZ:
  788. sample_rate_val = 8;
  789. break;
  790. case SAMPLING_RATE_88P2KHZ:
  791. sample_rate_val = 7;
  792. break;
  793. case SAMPLING_RATE_48KHZ:
  794. sample_rate_val = 6;
  795. break;
  796. case SAMPLING_RATE_44P1KHZ:
  797. sample_rate_val = 5;
  798. break;
  799. case SAMPLING_RATE_32KHZ:
  800. sample_rate_val = 4;
  801. break;
  802. case SAMPLING_RATE_22P05KHZ:
  803. sample_rate_val = 3;
  804. break;
  805. case SAMPLING_RATE_16KHZ:
  806. sample_rate_val = 2;
  807. break;
  808. case SAMPLING_RATE_11P025KHZ:
  809. sample_rate_val = 1;
  810. break;
  811. case SAMPLING_RATE_8KHZ:
  812. default:
  813. sample_rate_val = 0;
  814. break;
  815. }
  816. ucontrol->value.integer.value[0] = sample_rate_val;
  817. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  818. usb_rx_cfg.sample_rate);
  819. return 0;
  820. }
  821. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  822. struct snd_ctl_elem_value *ucontrol)
  823. {
  824. switch (ucontrol->value.integer.value[0]) {
  825. case 12:
  826. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  827. break;
  828. case 11:
  829. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  830. break;
  831. case 10:
  832. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  833. break;
  834. case 9:
  835. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  836. break;
  837. case 8:
  838. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  839. break;
  840. case 7:
  841. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  842. break;
  843. case 6:
  844. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  845. break;
  846. case 5:
  847. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  848. break;
  849. case 4:
  850. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  851. break;
  852. case 3:
  853. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  854. break;
  855. case 2:
  856. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  857. break;
  858. case 1:
  859. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  860. break;
  861. case 0:
  862. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  863. break;
  864. default:
  865. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  866. break;
  867. }
  868. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  869. __func__, ucontrol->value.integer.value[0],
  870. usb_rx_cfg.sample_rate);
  871. return 0;
  872. }
  873. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  874. struct snd_ctl_elem_value *ucontrol)
  875. {
  876. int sample_rate_val = 0;
  877. switch (usb_tx_cfg.sample_rate) {
  878. case SAMPLING_RATE_384KHZ:
  879. sample_rate_val = 12;
  880. break;
  881. case SAMPLING_RATE_352P8KHZ:
  882. sample_rate_val = 11;
  883. break;
  884. case SAMPLING_RATE_192KHZ:
  885. sample_rate_val = 10;
  886. break;
  887. case SAMPLING_RATE_176P4KHZ:
  888. sample_rate_val = 9;
  889. break;
  890. case SAMPLING_RATE_96KHZ:
  891. sample_rate_val = 8;
  892. break;
  893. case SAMPLING_RATE_88P2KHZ:
  894. sample_rate_val = 7;
  895. break;
  896. case SAMPLING_RATE_48KHZ:
  897. sample_rate_val = 6;
  898. break;
  899. case SAMPLING_RATE_44P1KHZ:
  900. sample_rate_val = 5;
  901. break;
  902. case SAMPLING_RATE_32KHZ:
  903. sample_rate_val = 4;
  904. break;
  905. case SAMPLING_RATE_22P05KHZ:
  906. sample_rate_val = 3;
  907. break;
  908. case SAMPLING_RATE_16KHZ:
  909. sample_rate_val = 2;
  910. break;
  911. case SAMPLING_RATE_11P025KHZ:
  912. sample_rate_val = 1;
  913. break;
  914. case SAMPLING_RATE_8KHZ:
  915. sample_rate_val = 0;
  916. break;
  917. default:
  918. sample_rate_val = 6;
  919. break;
  920. }
  921. ucontrol->value.integer.value[0] = sample_rate_val;
  922. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  923. usb_tx_cfg.sample_rate);
  924. return 0;
  925. }
  926. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_value *ucontrol)
  928. {
  929. switch (ucontrol->value.integer.value[0]) {
  930. case 12:
  931. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  932. break;
  933. case 11:
  934. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  935. break;
  936. case 10:
  937. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  938. break;
  939. case 9:
  940. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  941. break;
  942. case 8:
  943. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  944. break;
  945. case 7:
  946. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  947. break;
  948. case 6:
  949. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  950. break;
  951. case 5:
  952. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  953. break;
  954. case 4:
  955. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  956. break;
  957. case 3:
  958. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  959. break;
  960. case 2:
  961. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  962. break;
  963. case 1:
  964. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  965. break;
  966. case 0:
  967. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  968. break;
  969. default:
  970. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  971. break;
  972. }
  973. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  974. __func__, ucontrol->value.integer.value[0],
  975. usb_tx_cfg.sample_rate);
  976. return 0;
  977. }
  978. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  979. struct snd_ctl_elem_value *ucontrol)
  980. {
  981. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  982. afe_loopback_tx_cfg[0].channels);
  983. ucontrol->value.enumerated.item[0] =
  984. afe_loopback_tx_cfg[0].channels - 1;
  985. return 0;
  986. }
  987. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  988. struct snd_ctl_elem_value *ucontrol)
  989. {
  990. afe_loopback_tx_cfg[0].channels =
  991. ucontrol->value.enumerated.item[0] + 1;
  992. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  993. afe_loopback_tx_cfg[0].channels);
  994. return 1;
  995. }
  996. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  997. struct snd_ctl_elem_value *ucontrol)
  998. {
  999. switch (usb_rx_cfg.bit_format) {
  1000. case SNDRV_PCM_FORMAT_S32_LE:
  1001. ucontrol->value.integer.value[0] = 3;
  1002. break;
  1003. case SNDRV_PCM_FORMAT_S24_3LE:
  1004. ucontrol->value.integer.value[0] = 2;
  1005. break;
  1006. case SNDRV_PCM_FORMAT_S24_LE:
  1007. ucontrol->value.integer.value[0] = 1;
  1008. break;
  1009. case SNDRV_PCM_FORMAT_S16_LE:
  1010. default:
  1011. ucontrol->value.integer.value[0] = 0;
  1012. break;
  1013. }
  1014. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1015. __func__, usb_rx_cfg.bit_format,
  1016. ucontrol->value.integer.value[0]);
  1017. return 0;
  1018. }
  1019. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1020. struct snd_ctl_elem_value *ucontrol)
  1021. {
  1022. int rc = 0;
  1023. switch (ucontrol->value.integer.value[0]) {
  1024. case 3:
  1025. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1026. break;
  1027. case 2:
  1028. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1029. break;
  1030. case 1:
  1031. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1032. break;
  1033. case 0:
  1034. default:
  1035. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1036. break;
  1037. }
  1038. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1039. __func__, usb_rx_cfg.bit_format,
  1040. ucontrol->value.integer.value[0]);
  1041. return rc;
  1042. }
  1043. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1044. struct snd_ctl_elem_value *ucontrol)
  1045. {
  1046. switch (usb_tx_cfg.bit_format) {
  1047. case SNDRV_PCM_FORMAT_S32_LE:
  1048. ucontrol->value.integer.value[0] = 3;
  1049. break;
  1050. case SNDRV_PCM_FORMAT_S24_3LE:
  1051. ucontrol->value.integer.value[0] = 2;
  1052. break;
  1053. case SNDRV_PCM_FORMAT_S24_LE:
  1054. ucontrol->value.integer.value[0] = 1;
  1055. break;
  1056. case SNDRV_PCM_FORMAT_S16_LE:
  1057. default:
  1058. ucontrol->value.integer.value[0] = 0;
  1059. break;
  1060. }
  1061. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1062. __func__, usb_tx_cfg.bit_format,
  1063. ucontrol->value.integer.value[0]);
  1064. return 0;
  1065. }
  1066. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1067. struct snd_ctl_elem_value *ucontrol)
  1068. {
  1069. int rc = 0;
  1070. switch (ucontrol->value.integer.value[0]) {
  1071. case 3:
  1072. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1073. break;
  1074. case 2:
  1075. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1076. break;
  1077. case 1:
  1078. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1079. break;
  1080. case 0:
  1081. default:
  1082. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1083. break;
  1084. }
  1085. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1086. __func__, usb_tx_cfg.bit_format,
  1087. ucontrol->value.integer.value[0]);
  1088. return rc;
  1089. }
  1090. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1091. struct snd_ctl_elem_value *ucontrol)
  1092. {
  1093. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1094. usb_rx_cfg.channels);
  1095. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1096. return 0;
  1097. }
  1098. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1099. struct snd_ctl_elem_value *ucontrol)
  1100. {
  1101. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1102. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1103. return 1;
  1104. }
  1105. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1106. struct snd_ctl_elem_value *ucontrol)
  1107. {
  1108. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1109. usb_tx_cfg.channels);
  1110. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1111. return 0;
  1112. }
  1113. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1114. struct snd_ctl_elem_value *ucontrol)
  1115. {
  1116. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1117. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1118. return 1;
  1119. }
  1120. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1121. struct snd_ctl_elem_value *ucontrol)
  1122. {
  1123. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1124. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1125. ucontrol->value.integer.value[0]);
  1126. return 0;
  1127. }
  1128. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1129. struct snd_ctl_elem_value *ucontrol)
  1130. {
  1131. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1132. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1133. return 1;
  1134. }
  1135. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1136. struct snd_ctl_elem_value *ucontrol)
  1137. {
  1138. pr_debug("%s: proxy_rx channels = %d\n",
  1139. __func__, proxy_rx_cfg.channels);
  1140. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1141. return 0;
  1142. }
  1143. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1144. struct snd_ctl_elem_value *ucontrol)
  1145. {
  1146. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1147. pr_debug("%s: proxy_rx channels = %d\n",
  1148. __func__, proxy_rx_cfg.channels);
  1149. return 1;
  1150. }
  1151. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1152. struct tdm_port *port)
  1153. {
  1154. if (port) {
  1155. if (strnstr(kcontrol->id.name, "PRI",
  1156. sizeof(kcontrol->id.name))) {
  1157. port->mode = TDM_PRI;
  1158. } else if (strnstr(kcontrol->id.name, "SEC",
  1159. sizeof(kcontrol->id.name))) {
  1160. port->mode = TDM_SEC;
  1161. } else if (strnstr(kcontrol->id.name, "TERT",
  1162. sizeof(kcontrol->id.name))) {
  1163. port->mode = TDM_TERT;
  1164. } else if (strnstr(kcontrol->id.name, "QUAT",
  1165. sizeof(kcontrol->id.name))) {
  1166. port->mode = TDM_QUAT;
  1167. } else {
  1168. pr_err("%s: unsupported mode in: %s\n",
  1169. __func__, kcontrol->id.name);
  1170. return -EINVAL;
  1171. }
  1172. if (strnstr(kcontrol->id.name, "RX_0",
  1173. sizeof(kcontrol->id.name)) ||
  1174. strnstr(kcontrol->id.name, "TX_0",
  1175. sizeof(kcontrol->id.name))) {
  1176. port->channel = TDM_0;
  1177. } else if (strnstr(kcontrol->id.name, "RX_1",
  1178. sizeof(kcontrol->id.name)) ||
  1179. strnstr(kcontrol->id.name, "TX_1",
  1180. sizeof(kcontrol->id.name))) {
  1181. port->channel = TDM_1;
  1182. } else if (strnstr(kcontrol->id.name, "RX_2",
  1183. sizeof(kcontrol->id.name)) ||
  1184. strnstr(kcontrol->id.name, "TX_2",
  1185. sizeof(kcontrol->id.name))) {
  1186. port->channel = TDM_2;
  1187. } else if (strnstr(kcontrol->id.name, "RX_3",
  1188. sizeof(kcontrol->id.name)) ||
  1189. strnstr(kcontrol->id.name, "TX_3",
  1190. sizeof(kcontrol->id.name))) {
  1191. port->channel = TDM_3;
  1192. } else if (strnstr(kcontrol->id.name, "RX_4",
  1193. sizeof(kcontrol->id.name)) ||
  1194. strnstr(kcontrol->id.name, "TX_4",
  1195. sizeof(kcontrol->id.name))) {
  1196. port->channel = TDM_4;
  1197. } else if (strnstr(kcontrol->id.name, "RX_5",
  1198. sizeof(kcontrol->id.name)) ||
  1199. strnstr(kcontrol->id.name, "TX_5",
  1200. sizeof(kcontrol->id.name))) {
  1201. port->channel = TDM_5;
  1202. } else if (strnstr(kcontrol->id.name, "RX_6",
  1203. sizeof(kcontrol->id.name)) ||
  1204. strnstr(kcontrol->id.name, "TX_6",
  1205. sizeof(kcontrol->id.name))) {
  1206. port->channel = TDM_6;
  1207. } else if (strnstr(kcontrol->id.name, "RX_7",
  1208. sizeof(kcontrol->id.name)) ||
  1209. strnstr(kcontrol->id.name, "TX_7",
  1210. sizeof(kcontrol->id.name))) {
  1211. port->channel = TDM_7;
  1212. } else {
  1213. pr_err("%s: unsupported channel in: %s\n",
  1214. __func__, kcontrol->id.name);
  1215. return -EINVAL;
  1216. }
  1217. } else {
  1218. return -EINVAL;
  1219. }
  1220. return 0;
  1221. }
  1222. static int tdm_get_sample_rate(int value)
  1223. {
  1224. int sample_rate = 0;
  1225. switch (value) {
  1226. case 0:
  1227. sample_rate = SAMPLING_RATE_8KHZ;
  1228. break;
  1229. case 1:
  1230. sample_rate = SAMPLING_RATE_16KHZ;
  1231. break;
  1232. case 2:
  1233. sample_rate = SAMPLING_RATE_32KHZ;
  1234. break;
  1235. case 3:
  1236. sample_rate = SAMPLING_RATE_48KHZ;
  1237. break;
  1238. case 4:
  1239. sample_rate = SAMPLING_RATE_176P4KHZ;
  1240. break;
  1241. case 5:
  1242. sample_rate = SAMPLING_RATE_352P8KHZ;
  1243. break;
  1244. default:
  1245. sample_rate = SAMPLING_RATE_48KHZ;
  1246. break;
  1247. }
  1248. return sample_rate;
  1249. }
  1250. static int tdm_get_sample_rate_val(int sample_rate)
  1251. {
  1252. int sample_rate_val = 0;
  1253. switch (sample_rate) {
  1254. case SAMPLING_RATE_8KHZ:
  1255. sample_rate_val = 0;
  1256. break;
  1257. case SAMPLING_RATE_16KHZ:
  1258. sample_rate_val = 1;
  1259. break;
  1260. case SAMPLING_RATE_32KHZ:
  1261. sample_rate_val = 2;
  1262. break;
  1263. case SAMPLING_RATE_48KHZ:
  1264. sample_rate_val = 3;
  1265. break;
  1266. case SAMPLING_RATE_176P4KHZ:
  1267. sample_rate_val = 4;
  1268. break;
  1269. case SAMPLING_RATE_352P8KHZ:
  1270. sample_rate_val = 5;
  1271. break;
  1272. default:
  1273. sample_rate_val = 3;
  1274. break;
  1275. }
  1276. return sample_rate_val;
  1277. }
  1278. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1279. struct snd_ctl_elem_value *ucontrol)
  1280. {
  1281. struct tdm_port port;
  1282. int ret = tdm_get_port_idx(kcontrol, &port);
  1283. if (ret) {
  1284. pr_err("%s: unsupported control: %s\n",
  1285. __func__, kcontrol->id.name);
  1286. } else {
  1287. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1288. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1289. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1290. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1291. ucontrol->value.enumerated.item[0]);
  1292. }
  1293. return ret;
  1294. }
  1295. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1296. struct snd_ctl_elem_value *ucontrol)
  1297. {
  1298. struct tdm_port port;
  1299. int ret = tdm_get_port_idx(kcontrol, &port);
  1300. if (ret) {
  1301. pr_err("%s: unsupported control: %s\n",
  1302. __func__, kcontrol->id.name);
  1303. } else {
  1304. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1305. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1306. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1307. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1308. ucontrol->value.enumerated.item[0]);
  1309. }
  1310. return ret;
  1311. }
  1312. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1313. struct snd_ctl_elem_value *ucontrol)
  1314. {
  1315. struct tdm_port port;
  1316. int ret = tdm_get_port_idx(kcontrol, &port);
  1317. if (ret) {
  1318. pr_err("%s: unsupported control: %s\n",
  1319. __func__, kcontrol->id.name);
  1320. } else {
  1321. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1322. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1323. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1324. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1325. ucontrol->value.enumerated.item[0]);
  1326. }
  1327. return ret;
  1328. }
  1329. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1330. struct snd_ctl_elem_value *ucontrol)
  1331. {
  1332. struct tdm_port port;
  1333. int ret = tdm_get_port_idx(kcontrol, &port);
  1334. if (ret) {
  1335. pr_err("%s: unsupported control: %s\n",
  1336. __func__, kcontrol->id.name);
  1337. } else {
  1338. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1339. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1340. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1341. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1342. ucontrol->value.enumerated.item[0]);
  1343. }
  1344. return ret;
  1345. }
  1346. static int tdm_get_format(int value)
  1347. {
  1348. int format = 0;
  1349. switch (value) {
  1350. case 0:
  1351. format = SNDRV_PCM_FORMAT_S16_LE;
  1352. break;
  1353. case 1:
  1354. format = SNDRV_PCM_FORMAT_S24_LE;
  1355. break;
  1356. case 2:
  1357. format = SNDRV_PCM_FORMAT_S32_LE;
  1358. break;
  1359. default:
  1360. format = SNDRV_PCM_FORMAT_S16_LE;
  1361. break;
  1362. }
  1363. return format;
  1364. }
  1365. static int tdm_get_format_val(int format)
  1366. {
  1367. int value = 0;
  1368. switch (format) {
  1369. case SNDRV_PCM_FORMAT_S16_LE:
  1370. value = 0;
  1371. break;
  1372. case SNDRV_PCM_FORMAT_S24_LE:
  1373. value = 1;
  1374. break;
  1375. case SNDRV_PCM_FORMAT_S32_LE:
  1376. value = 2;
  1377. break;
  1378. default:
  1379. value = 0;
  1380. break;
  1381. }
  1382. return value;
  1383. }
  1384. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1385. struct snd_ctl_elem_value *ucontrol)
  1386. {
  1387. struct tdm_port port;
  1388. int ret = tdm_get_port_idx(kcontrol, &port);
  1389. if (ret) {
  1390. pr_err("%s: unsupported control: %s\n",
  1391. __func__, kcontrol->id.name);
  1392. } else {
  1393. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1394. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1395. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1396. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1397. ucontrol->value.enumerated.item[0]);
  1398. }
  1399. return ret;
  1400. }
  1401. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. struct tdm_port port;
  1405. int ret = tdm_get_port_idx(kcontrol, &port);
  1406. if (ret) {
  1407. pr_err("%s: unsupported control: %s\n",
  1408. __func__, kcontrol->id.name);
  1409. } else {
  1410. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1411. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1412. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1413. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1414. ucontrol->value.enumerated.item[0]);
  1415. }
  1416. return ret;
  1417. }
  1418. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1419. struct snd_ctl_elem_value *ucontrol)
  1420. {
  1421. struct tdm_port port;
  1422. int ret = tdm_get_port_idx(kcontrol, &port);
  1423. if (ret) {
  1424. pr_err("%s: unsupported control: %s\n",
  1425. __func__, kcontrol->id.name);
  1426. } else {
  1427. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1428. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1429. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1430. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1431. ucontrol->value.enumerated.item[0]);
  1432. }
  1433. return ret;
  1434. }
  1435. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1436. struct snd_ctl_elem_value *ucontrol)
  1437. {
  1438. struct tdm_port port;
  1439. int ret = tdm_get_port_idx(kcontrol, &port);
  1440. if (ret) {
  1441. pr_err("%s: unsupported control: %s\n",
  1442. __func__, kcontrol->id.name);
  1443. } else {
  1444. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1445. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1446. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1447. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1448. ucontrol->value.enumerated.item[0]);
  1449. }
  1450. return ret;
  1451. }
  1452. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1453. struct snd_ctl_elem_value *ucontrol)
  1454. {
  1455. struct tdm_port port;
  1456. int ret = tdm_get_port_idx(kcontrol, &port);
  1457. if (ret) {
  1458. pr_err("%s: unsupported control: %s\n",
  1459. __func__, kcontrol->id.name);
  1460. } else {
  1461. ucontrol->value.enumerated.item[0] =
  1462. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1463. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1464. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1465. ucontrol->value.enumerated.item[0]);
  1466. }
  1467. return ret;
  1468. }
  1469. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1470. struct snd_ctl_elem_value *ucontrol)
  1471. {
  1472. struct tdm_port port;
  1473. int ret = tdm_get_port_idx(kcontrol, &port);
  1474. if (ret) {
  1475. pr_err("%s: unsupported control: %s\n",
  1476. __func__, kcontrol->id.name);
  1477. } else {
  1478. tdm_rx_cfg[port.mode][port.channel].channels =
  1479. ucontrol->value.enumerated.item[0] + 1;
  1480. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1481. tdm_rx_cfg[port.mode][port.channel].channels,
  1482. ucontrol->value.enumerated.item[0] + 1);
  1483. }
  1484. return ret;
  1485. }
  1486. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct tdm_port port;
  1490. int ret = tdm_get_port_idx(kcontrol, &port);
  1491. if (ret) {
  1492. pr_err("%s: unsupported control: %s\n",
  1493. __func__, kcontrol->id.name);
  1494. } else {
  1495. ucontrol->value.enumerated.item[0] =
  1496. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1497. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1498. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1499. ucontrol->value.enumerated.item[0]);
  1500. }
  1501. return ret;
  1502. }
  1503. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1504. struct snd_ctl_elem_value *ucontrol)
  1505. {
  1506. struct tdm_port port;
  1507. int ret = tdm_get_port_idx(kcontrol, &port);
  1508. if (ret) {
  1509. pr_err("%s: unsupported control: %s\n",
  1510. __func__, kcontrol->id.name);
  1511. } else {
  1512. tdm_tx_cfg[port.mode][port.channel].channels =
  1513. ucontrol->value.enumerated.item[0] + 1;
  1514. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1515. tdm_tx_cfg[port.mode][port.channel].channels,
  1516. ucontrol->value.enumerated.item[0] + 1);
  1517. }
  1518. return ret;
  1519. }
  1520. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1521. struct snd_ctl_elem_value *ucontrol)
  1522. {
  1523. int slot_index = 0;
  1524. int interface = ucontrol->value.integer.value[0];
  1525. int channel = ucontrol->value.integer.value[1];
  1526. unsigned int offset_val = 0;
  1527. unsigned int *slot_offset = NULL;
  1528. struct tdm_dev_config *config = NULL;
  1529. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1530. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1531. return -EINVAL;
  1532. }
  1533. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1534. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1535. return -EINVAL;
  1536. }
  1537. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1538. interface, channel);
  1539. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1540. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1541. slot_offset = config->tdm_slot_offset;
  1542. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1543. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1544. slot_index];
  1545. /* Offset value can only be 0, 4, 8, ..28 */
  1546. if (offset_val % 4 == 0 && offset_val <= 28)
  1547. slot_offset[slot_index] = offset_val;
  1548. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1549. slot_index, slot_offset[slot_index]);
  1550. }
  1551. return 0;
  1552. }
  1553. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1554. {
  1555. int idx = 0;
  1556. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1557. sizeof("PRIM_AUX_PCM"))) {
  1558. idx = PRIM_AUX_PCM;
  1559. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1560. sizeof("SEC_AUX_PCM"))) {
  1561. idx = SEC_AUX_PCM;
  1562. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1563. sizeof("TERT_AUX_PCM"))) {
  1564. idx = TERT_AUX_PCM;
  1565. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1566. sizeof("QUAT_AUX_PCM"))) {
  1567. idx = QUAT_AUX_PCM;
  1568. } else {
  1569. pr_err("%s: unsupported port: %s\n",
  1570. __func__, kcontrol->id.name);
  1571. idx = -EINVAL;
  1572. }
  1573. return idx;
  1574. }
  1575. static int aux_pcm_get_sample_rate(int value)
  1576. {
  1577. int sample_rate = 0;
  1578. switch (value) {
  1579. case 1:
  1580. sample_rate = SAMPLING_RATE_16KHZ;
  1581. break;
  1582. case 0:
  1583. default:
  1584. sample_rate = SAMPLING_RATE_8KHZ;
  1585. break;
  1586. }
  1587. return sample_rate;
  1588. }
  1589. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1590. {
  1591. int sample_rate_val = 0;
  1592. switch (sample_rate) {
  1593. case SAMPLING_RATE_16KHZ:
  1594. sample_rate_val = 1;
  1595. break;
  1596. case SAMPLING_RATE_8KHZ:
  1597. default:
  1598. sample_rate_val = 0;
  1599. break;
  1600. }
  1601. return sample_rate_val;
  1602. }
  1603. static int mi2s_auxpcm_get_format(int value)
  1604. {
  1605. int format = 0;
  1606. switch (value) {
  1607. case 0:
  1608. format = SNDRV_PCM_FORMAT_S16_LE;
  1609. break;
  1610. case 1:
  1611. format = SNDRV_PCM_FORMAT_S24_LE;
  1612. break;
  1613. case 2:
  1614. format = SNDRV_PCM_FORMAT_S24_3LE;
  1615. break;
  1616. case 3:
  1617. format = SNDRV_PCM_FORMAT_S32_LE;
  1618. break;
  1619. default:
  1620. format = SNDRV_PCM_FORMAT_S16_LE;
  1621. break;
  1622. }
  1623. return format;
  1624. }
  1625. static int mi2s_auxpcm_get_format_value(int format)
  1626. {
  1627. int value = 0;
  1628. switch (format) {
  1629. case SNDRV_PCM_FORMAT_S16_LE:
  1630. value = 0;
  1631. break;
  1632. case SNDRV_PCM_FORMAT_S24_LE:
  1633. value = 1;
  1634. break;
  1635. case SNDRV_PCM_FORMAT_S24_3LE:
  1636. value = 2;
  1637. break;
  1638. case SNDRV_PCM_FORMAT_S32_LE:
  1639. value = 3;
  1640. break;
  1641. default:
  1642. value = 0;
  1643. break;
  1644. }
  1645. return value;
  1646. }
  1647. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1648. struct snd_ctl_elem_value *ucontrol)
  1649. {
  1650. int idx = aux_pcm_get_port_idx(kcontrol);
  1651. if (idx < 0)
  1652. return idx;
  1653. ucontrol->value.enumerated.item[0] =
  1654. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1655. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1656. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1657. ucontrol->value.enumerated.item[0]);
  1658. return 0;
  1659. }
  1660. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1661. struct snd_ctl_elem_value *ucontrol)
  1662. {
  1663. int idx = aux_pcm_get_port_idx(kcontrol);
  1664. if (idx < 0)
  1665. return idx;
  1666. aux_pcm_rx_cfg[idx].sample_rate =
  1667. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1668. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1669. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1670. ucontrol->value.enumerated.item[0]);
  1671. return 0;
  1672. }
  1673. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1674. struct snd_ctl_elem_value *ucontrol)
  1675. {
  1676. int idx = aux_pcm_get_port_idx(kcontrol);
  1677. if (idx < 0)
  1678. return idx;
  1679. ucontrol->value.enumerated.item[0] =
  1680. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1681. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1682. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1683. ucontrol->value.enumerated.item[0]);
  1684. return 0;
  1685. }
  1686. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1687. struct snd_ctl_elem_value *ucontrol)
  1688. {
  1689. int idx = aux_pcm_get_port_idx(kcontrol);
  1690. if (idx < 0)
  1691. return idx;
  1692. aux_pcm_tx_cfg[idx].sample_rate =
  1693. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1694. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1695. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1696. ucontrol->value.enumerated.item[0]);
  1697. return 0;
  1698. }
  1699. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. int idx = aux_pcm_get_port_idx(kcontrol);
  1703. if (idx < 0)
  1704. return idx;
  1705. ucontrol->value.enumerated.item[0] =
  1706. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1707. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1708. idx, aux_pcm_rx_cfg[idx].bit_format,
  1709. ucontrol->value.enumerated.item[0]);
  1710. return 0;
  1711. }
  1712. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1713. struct snd_ctl_elem_value *ucontrol)
  1714. {
  1715. int idx = aux_pcm_get_port_idx(kcontrol);
  1716. if (idx < 0)
  1717. return idx;
  1718. aux_pcm_rx_cfg[idx].bit_format =
  1719. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1720. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1721. idx, aux_pcm_rx_cfg[idx].bit_format,
  1722. ucontrol->value.enumerated.item[0]);
  1723. return 0;
  1724. }
  1725. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1726. struct snd_ctl_elem_value *ucontrol)
  1727. {
  1728. int idx = aux_pcm_get_port_idx(kcontrol);
  1729. if (idx < 0)
  1730. return idx;
  1731. ucontrol->value.enumerated.item[0] =
  1732. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1733. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1734. idx, aux_pcm_tx_cfg[idx].bit_format,
  1735. ucontrol->value.enumerated.item[0]);
  1736. return 0;
  1737. }
  1738. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. int idx = aux_pcm_get_port_idx(kcontrol);
  1742. if (idx < 0)
  1743. return idx;
  1744. aux_pcm_tx_cfg[idx].bit_format =
  1745. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1746. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1747. idx, aux_pcm_tx_cfg[idx].bit_format,
  1748. ucontrol->value.enumerated.item[0]);
  1749. return 0;
  1750. }
  1751. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1752. {
  1753. int idx = 0;
  1754. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1755. sizeof("PRIM_MI2S_RX"))) {
  1756. idx = PRIM_MI2S;
  1757. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1758. sizeof("SEC_MI2S_RX"))) {
  1759. idx = SEC_MI2S;
  1760. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1761. sizeof("TERT_MI2S_RX"))) {
  1762. idx = TERT_MI2S;
  1763. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1764. sizeof("QUAT_MI2S_RX"))) {
  1765. idx = QUAT_MI2S;
  1766. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1767. sizeof("PRIM_MI2S_TX"))) {
  1768. idx = PRIM_MI2S;
  1769. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1770. sizeof("SEC_MI2S_TX"))) {
  1771. idx = SEC_MI2S;
  1772. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1773. sizeof("TERT_MI2S_TX"))) {
  1774. idx = TERT_MI2S;
  1775. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1776. sizeof("QUAT_MI2S_TX"))) {
  1777. idx = QUAT_MI2S;
  1778. } else {
  1779. pr_err("%s: unsupported channel: %s\n",
  1780. __func__, kcontrol->id.name);
  1781. idx = -EINVAL;
  1782. }
  1783. return idx;
  1784. }
  1785. static int mi2s_get_sample_rate(int value)
  1786. {
  1787. int sample_rate = 0;
  1788. switch (value) {
  1789. case 0:
  1790. sample_rate = SAMPLING_RATE_8KHZ;
  1791. break;
  1792. case 1:
  1793. sample_rate = SAMPLING_RATE_11P025KHZ;
  1794. break;
  1795. case 2:
  1796. sample_rate = SAMPLING_RATE_16KHZ;
  1797. break;
  1798. case 3:
  1799. sample_rate = SAMPLING_RATE_22P05KHZ;
  1800. break;
  1801. case 4:
  1802. sample_rate = SAMPLING_RATE_32KHZ;
  1803. break;
  1804. case 5:
  1805. sample_rate = SAMPLING_RATE_44P1KHZ;
  1806. break;
  1807. case 6:
  1808. sample_rate = SAMPLING_RATE_48KHZ;
  1809. break;
  1810. case 7:
  1811. sample_rate = SAMPLING_RATE_88P2KHZ;
  1812. break;
  1813. case 8:
  1814. sample_rate = SAMPLING_RATE_96KHZ;
  1815. break;
  1816. case 9:
  1817. sample_rate = SAMPLING_RATE_176P4KHZ;
  1818. break;
  1819. case 10:
  1820. sample_rate = SAMPLING_RATE_192KHZ;
  1821. break;
  1822. case 11:
  1823. sample_rate = SAMPLING_RATE_352P8KHZ;
  1824. break;
  1825. case 12:
  1826. sample_rate = SAMPLING_RATE_384KHZ;
  1827. break;
  1828. default:
  1829. sample_rate = SAMPLING_RATE_48KHZ;
  1830. break;
  1831. }
  1832. return sample_rate;
  1833. }
  1834. static int mi2s_get_sample_rate_val(int sample_rate)
  1835. {
  1836. int sample_rate_val = 0;
  1837. switch (sample_rate) {
  1838. case SAMPLING_RATE_8KHZ:
  1839. sample_rate_val = 0;
  1840. break;
  1841. case SAMPLING_RATE_11P025KHZ:
  1842. sample_rate_val = 1;
  1843. break;
  1844. case SAMPLING_RATE_16KHZ:
  1845. sample_rate_val = 2;
  1846. break;
  1847. case SAMPLING_RATE_22P05KHZ:
  1848. sample_rate_val = 3;
  1849. break;
  1850. case SAMPLING_RATE_32KHZ:
  1851. sample_rate_val = 4;
  1852. break;
  1853. case SAMPLING_RATE_44P1KHZ:
  1854. sample_rate_val = 5;
  1855. break;
  1856. case SAMPLING_RATE_48KHZ:
  1857. sample_rate_val = 6;
  1858. break;
  1859. case SAMPLING_RATE_88P2KHZ:
  1860. sample_rate_val = 7;
  1861. break;
  1862. case SAMPLING_RATE_96KHZ:
  1863. sample_rate_val = 8;
  1864. break;
  1865. case SAMPLING_RATE_176P4KHZ:
  1866. sample_rate_val = 9;
  1867. break;
  1868. case SAMPLING_RATE_192KHZ:
  1869. sample_rate_val = 10;
  1870. break;
  1871. case SAMPLING_RATE_352P8KHZ:
  1872. sample_rate_val = 11;
  1873. break;
  1874. case SAMPLING_RATE_384KHZ:
  1875. sample_rate_val = 12;
  1876. break;
  1877. default:
  1878. sample_rate_val = 6;
  1879. break;
  1880. }
  1881. return sample_rate_val;
  1882. }
  1883. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1884. struct snd_ctl_elem_value *ucontrol)
  1885. {
  1886. int idx = mi2s_get_port_idx(kcontrol);
  1887. if (idx < 0)
  1888. return idx;
  1889. ucontrol->value.enumerated.item[0] =
  1890. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1891. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1892. idx, mi2s_rx_cfg[idx].sample_rate,
  1893. ucontrol->value.enumerated.item[0]);
  1894. return 0;
  1895. }
  1896. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1897. struct snd_ctl_elem_value *ucontrol)
  1898. {
  1899. int idx = mi2s_get_port_idx(kcontrol);
  1900. if (idx < 0)
  1901. return idx;
  1902. mi2s_rx_cfg[idx].sample_rate =
  1903. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1904. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1905. idx, mi2s_rx_cfg[idx].sample_rate,
  1906. ucontrol->value.enumerated.item[0]);
  1907. return 0;
  1908. }
  1909. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1910. struct snd_ctl_elem_value *ucontrol)
  1911. {
  1912. int idx = mi2s_get_port_idx(kcontrol);
  1913. if (idx < 0)
  1914. return idx;
  1915. ucontrol->value.enumerated.item[0] =
  1916. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1917. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1918. idx, mi2s_tx_cfg[idx].sample_rate,
  1919. ucontrol->value.enumerated.item[0]);
  1920. return 0;
  1921. }
  1922. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1923. struct snd_ctl_elem_value *ucontrol)
  1924. {
  1925. int idx = mi2s_get_port_idx(kcontrol);
  1926. if (idx < 0)
  1927. return idx;
  1928. mi2s_tx_cfg[idx].sample_rate =
  1929. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1930. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1931. idx, mi2s_tx_cfg[idx].sample_rate,
  1932. ucontrol->value.enumerated.item[0]);
  1933. return 0;
  1934. }
  1935. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1936. struct snd_ctl_elem_value *ucontrol)
  1937. {
  1938. int idx = mi2s_get_port_idx(kcontrol);
  1939. if (idx < 0)
  1940. return idx;
  1941. ucontrol->value.enumerated.item[0] =
  1942. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1943. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1944. idx, mi2s_rx_cfg[idx].bit_format,
  1945. ucontrol->value.enumerated.item[0]);
  1946. return 0;
  1947. }
  1948. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1949. struct snd_ctl_elem_value *ucontrol)
  1950. {
  1951. int idx = mi2s_get_port_idx(kcontrol);
  1952. if (idx < 0)
  1953. return idx;
  1954. mi2s_rx_cfg[idx].bit_format =
  1955. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1956. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1957. idx, mi2s_rx_cfg[idx].bit_format,
  1958. ucontrol->value.enumerated.item[0]);
  1959. return 0;
  1960. }
  1961. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1962. struct snd_ctl_elem_value *ucontrol)
  1963. {
  1964. int idx = mi2s_get_port_idx(kcontrol);
  1965. if (idx < 0)
  1966. return idx;
  1967. ucontrol->value.enumerated.item[0] =
  1968. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1969. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1970. idx, mi2s_tx_cfg[idx].bit_format,
  1971. ucontrol->value.enumerated.item[0]);
  1972. return 0;
  1973. }
  1974. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1975. struct snd_ctl_elem_value *ucontrol)
  1976. {
  1977. int idx = mi2s_get_port_idx(kcontrol);
  1978. if (idx < 0)
  1979. return idx;
  1980. mi2s_tx_cfg[idx].bit_format =
  1981. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1982. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1983. idx, mi2s_tx_cfg[idx].bit_format,
  1984. ucontrol->value.enumerated.item[0]);
  1985. return 0;
  1986. }
  1987. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1988. struct snd_ctl_elem_value *ucontrol)
  1989. {
  1990. int idx = mi2s_get_port_idx(kcontrol);
  1991. if (idx < 0)
  1992. return idx;
  1993. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1994. idx, mi2s_rx_cfg[idx].channels);
  1995. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1996. return 0;
  1997. }
  1998. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1999. struct snd_ctl_elem_value *ucontrol)
  2000. {
  2001. int idx = mi2s_get_port_idx(kcontrol);
  2002. if (idx < 0)
  2003. return idx;
  2004. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2005. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2006. idx, mi2s_rx_cfg[idx].channels);
  2007. return 1;
  2008. }
  2009. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2010. struct snd_ctl_elem_value *ucontrol)
  2011. {
  2012. int idx = mi2s_get_port_idx(kcontrol);
  2013. if (idx < 0)
  2014. return idx;
  2015. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2016. idx, mi2s_tx_cfg[idx].channels);
  2017. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2018. return 0;
  2019. }
  2020. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2021. struct snd_ctl_elem_value *ucontrol)
  2022. {
  2023. int idx = mi2s_get_port_idx(kcontrol);
  2024. if (idx < 0)
  2025. return idx;
  2026. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2027. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2028. idx, mi2s_tx_cfg[idx].channels);
  2029. return 1;
  2030. }
  2031. static int msm_get_port_id(int be_id)
  2032. {
  2033. int afe_port_id = 0;
  2034. switch (be_id) {
  2035. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2036. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2037. break;
  2038. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2039. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2040. break;
  2041. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2042. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2043. break;
  2044. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2045. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2046. break;
  2047. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2048. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2049. break;
  2050. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2051. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2052. break;
  2053. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2054. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2055. break;
  2056. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2057. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2058. break;
  2059. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2060. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2061. break;
  2062. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2063. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2064. break;
  2065. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2066. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2067. break;
  2068. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2069. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_0;
  2070. break;
  2071. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2072. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_0;
  2073. break;
  2074. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2075. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_1;
  2076. break;
  2077. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_1:
  2078. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_1;
  2079. break;
  2080. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2081. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_2;
  2082. break;
  2083. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_2:
  2084. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_2;
  2085. break;
  2086. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2087. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_3;
  2088. break;
  2089. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2090. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_3;
  2091. break;
  2092. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  2093. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_4;
  2094. break;
  2095. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2096. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_4;
  2097. break;
  2098. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2099. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_5;
  2100. break;
  2101. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_5:
  2102. afe_port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_5;
  2103. break;
  2104. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2105. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_6;
  2106. break;
  2107. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_7:
  2108. afe_port_id = AFE_PORT_ID_RX_CODEC_DMA_RX_7;
  2109. break;
  2110. default:
  2111. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2112. afe_port_id = -EINVAL;
  2113. }
  2114. return afe_port_id;
  2115. }
  2116. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2117. {
  2118. u32 bit_per_sample = 0;
  2119. switch (bit_format) {
  2120. case SNDRV_PCM_FORMAT_S32_LE:
  2121. case SNDRV_PCM_FORMAT_S24_3LE:
  2122. case SNDRV_PCM_FORMAT_S24_LE:
  2123. bit_per_sample = 32;
  2124. break;
  2125. case SNDRV_PCM_FORMAT_S16_LE:
  2126. default:
  2127. bit_per_sample = 16;
  2128. break;
  2129. }
  2130. return bit_per_sample;
  2131. }
  2132. static void update_mi2s_clk_val(int dai_id, int stream)
  2133. {
  2134. u32 bit_per_sample = 0;
  2135. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2136. bit_per_sample =
  2137. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2138. mi2s_clk[dai_id].clk_freq_in_hz =
  2139. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2140. } else {
  2141. bit_per_sample =
  2142. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2143. mi2s_clk[dai_id].clk_freq_in_hz =
  2144. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2145. }
  2146. }
  2147. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2148. {
  2149. int ret = 0;
  2150. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2151. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2152. int port_id = 0;
  2153. int index = cpu_dai->id;
  2154. port_id = msm_get_port_id(rtd->dai_link->id);
  2155. if (port_id < 0) {
  2156. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2157. ret = port_id;
  2158. goto err;
  2159. }
  2160. if (enable) {
  2161. update_mi2s_clk_val(index, substream->stream);
  2162. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2163. mi2s_clk[index].clk_freq_in_hz);
  2164. }
  2165. mi2s_clk[index].enable = enable;
  2166. ret = afe_set_lpass_clock_v2(port_id,
  2167. &mi2s_clk[index]);
  2168. if (ret < 0) {
  2169. dev_err(rtd->card->dev,
  2170. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2171. __func__, port_id, ret);
  2172. goto err;
  2173. }
  2174. err:
  2175. return ret;
  2176. }
  2177. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2178. {
  2179. int idx = 0;
  2180. if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2181. sizeof("RX_CDC_DMA_RX_0")))
  2182. idx = RX_CDC_DMA_RX_0;
  2183. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2184. sizeof("RX_CDC_DMA_RX_1")))
  2185. idx = RX_CDC_DMA_RX_1;
  2186. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2187. sizeof("RX_CDC_DMA_RX_2")))
  2188. idx = RX_CDC_DMA_RX_2;
  2189. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2190. sizeof("RX_CDC_DMA_RX_3")))
  2191. idx = RX_CDC_DMA_RX_3;
  2192. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2193. sizeof("RX_CDC_DMA_RX_5")))
  2194. idx = RX_CDC_DMA_RX_5;
  2195. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_6",
  2196. sizeof("RX_CDC_DMA_RX_6")))
  2197. idx = RX_CDC_DMA_RX_6;
  2198. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2199. sizeof("TX_CDC_DMA_TX_0")))
  2200. idx = TX_CDC_DMA_TX_0;
  2201. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2202. sizeof("TX_CDC_DMA_TX_3")))
  2203. idx = TX_CDC_DMA_TX_3;
  2204. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2205. sizeof("TX_CDC_DMA_TX_4")))
  2206. idx = TX_CDC_DMA_TX_4;
  2207. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2208. sizeof("VA_CDC_DMA_TX_0")))
  2209. idx = VA_CDC_DMA_TX_0;
  2210. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2211. sizeof("VA_CDC_DMA_TX_1")))
  2212. idx = VA_CDC_DMA_TX_1;
  2213. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2214. sizeof("VA_CDC_DMA_TX_2")))
  2215. idx = VA_CDC_DMA_TX_2;
  2216. else {
  2217. pr_err("%s: unsupported channel: %s\n",
  2218. __func__, kcontrol->id.name);
  2219. return -EINVAL;
  2220. }
  2221. return idx;
  2222. }
  2223. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2224. struct snd_ctl_elem_value *ucontrol)
  2225. {
  2226. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2227. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2228. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2229. return ch_num;
  2230. }
  2231. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2232. cdc_dma_rx_cfg[ch_num].channels - 1);
  2233. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2234. return 0;
  2235. }
  2236. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2237. struct snd_ctl_elem_value *ucontrol)
  2238. {
  2239. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2240. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2241. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2242. return ch_num;
  2243. }
  2244. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2245. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2246. cdc_dma_rx_cfg[ch_num].channels);
  2247. return 1;
  2248. }
  2249. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2250. struct snd_ctl_elem_value *ucontrol)
  2251. {
  2252. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2253. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2254. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2255. return ch_num;
  2256. }
  2257. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2258. case SNDRV_PCM_FORMAT_S32_LE:
  2259. ucontrol->value.integer.value[0] = 3;
  2260. break;
  2261. case SNDRV_PCM_FORMAT_S24_3LE:
  2262. ucontrol->value.integer.value[0] = 2;
  2263. break;
  2264. case SNDRV_PCM_FORMAT_S24_LE:
  2265. ucontrol->value.integer.value[0] = 1;
  2266. break;
  2267. case SNDRV_PCM_FORMAT_S16_LE:
  2268. default:
  2269. ucontrol->value.integer.value[0] = 0;
  2270. break;
  2271. }
  2272. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2273. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2274. ucontrol->value.integer.value[0]);
  2275. return 0;
  2276. }
  2277. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2278. struct snd_ctl_elem_value *ucontrol)
  2279. {
  2280. int rc = 0;
  2281. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2282. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2283. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2284. return ch_num;
  2285. }
  2286. switch (ucontrol->value.integer.value[0]) {
  2287. case 3:
  2288. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2289. break;
  2290. case 2:
  2291. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2292. break;
  2293. case 1:
  2294. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2295. break;
  2296. case 0:
  2297. default:
  2298. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2299. break;
  2300. }
  2301. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2302. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2303. ucontrol->value.integer.value[0]);
  2304. return rc;
  2305. }
  2306. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2307. {
  2308. int sample_rate_val = 0;
  2309. switch (sample_rate) {
  2310. case SAMPLING_RATE_8KHZ:
  2311. sample_rate_val = 0;
  2312. break;
  2313. case SAMPLING_RATE_11P025KHZ:
  2314. sample_rate_val = 1;
  2315. break;
  2316. case SAMPLING_RATE_16KHZ:
  2317. sample_rate_val = 2;
  2318. break;
  2319. case SAMPLING_RATE_22P05KHZ:
  2320. sample_rate_val = 3;
  2321. break;
  2322. case SAMPLING_RATE_32KHZ:
  2323. sample_rate_val = 4;
  2324. break;
  2325. case SAMPLING_RATE_44P1KHZ:
  2326. sample_rate_val = 5;
  2327. break;
  2328. case SAMPLING_RATE_48KHZ:
  2329. sample_rate_val = 6;
  2330. break;
  2331. case SAMPLING_RATE_88P2KHZ:
  2332. sample_rate_val = 7;
  2333. break;
  2334. case SAMPLING_RATE_96KHZ:
  2335. sample_rate_val = 8;
  2336. break;
  2337. case SAMPLING_RATE_176P4KHZ:
  2338. sample_rate_val = 9;
  2339. break;
  2340. case SAMPLING_RATE_192KHZ:
  2341. sample_rate_val = 10;
  2342. break;
  2343. case SAMPLING_RATE_352P8KHZ:
  2344. sample_rate_val = 11;
  2345. break;
  2346. case SAMPLING_RATE_384KHZ:
  2347. sample_rate_val = 12;
  2348. break;
  2349. default:
  2350. sample_rate_val = 6;
  2351. break;
  2352. }
  2353. return sample_rate_val;
  2354. }
  2355. static int cdc_dma_get_sample_rate(int value)
  2356. {
  2357. int sample_rate = 0;
  2358. switch (value) {
  2359. case 0:
  2360. sample_rate = SAMPLING_RATE_8KHZ;
  2361. break;
  2362. case 1:
  2363. sample_rate = SAMPLING_RATE_11P025KHZ;
  2364. break;
  2365. case 2:
  2366. sample_rate = SAMPLING_RATE_16KHZ;
  2367. break;
  2368. case 3:
  2369. sample_rate = SAMPLING_RATE_22P05KHZ;
  2370. break;
  2371. case 4:
  2372. sample_rate = SAMPLING_RATE_32KHZ;
  2373. break;
  2374. case 5:
  2375. sample_rate = SAMPLING_RATE_44P1KHZ;
  2376. break;
  2377. case 6:
  2378. sample_rate = SAMPLING_RATE_48KHZ;
  2379. break;
  2380. case 7:
  2381. sample_rate = SAMPLING_RATE_88P2KHZ;
  2382. break;
  2383. case 8:
  2384. sample_rate = SAMPLING_RATE_96KHZ;
  2385. break;
  2386. case 9:
  2387. sample_rate = SAMPLING_RATE_176P4KHZ;
  2388. break;
  2389. case 10:
  2390. sample_rate = SAMPLING_RATE_192KHZ;
  2391. break;
  2392. case 11:
  2393. sample_rate = SAMPLING_RATE_352P8KHZ;
  2394. break;
  2395. case 12:
  2396. sample_rate = SAMPLING_RATE_384KHZ;
  2397. break;
  2398. default:
  2399. sample_rate = SAMPLING_RATE_48KHZ;
  2400. break;
  2401. }
  2402. return sample_rate;
  2403. }
  2404. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2405. struct snd_ctl_elem_value *ucontrol)
  2406. {
  2407. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2408. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2409. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2410. return ch_num;
  2411. }
  2412. ucontrol->value.enumerated.item[0] =
  2413. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2414. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2415. cdc_dma_rx_cfg[ch_num].sample_rate);
  2416. return 0;
  2417. }
  2418. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2419. struct snd_ctl_elem_value *ucontrol)
  2420. {
  2421. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2422. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2423. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2424. return ch_num;
  2425. }
  2426. cdc_dma_rx_cfg[ch_num].sample_rate =
  2427. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2428. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2429. __func__, ucontrol->value.enumerated.item[0],
  2430. cdc_dma_rx_cfg[ch_num].sample_rate);
  2431. return 0;
  2432. }
  2433. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2434. struct snd_ctl_elem_value *ucontrol)
  2435. {
  2436. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2437. if (ch_num < 0) {
  2438. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2439. return ch_num;
  2440. }
  2441. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2442. cdc_dma_tx_cfg[ch_num].channels);
  2443. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2444. return 0;
  2445. }
  2446. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2447. struct snd_ctl_elem_value *ucontrol)
  2448. {
  2449. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2450. if (ch_num < 0) {
  2451. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2452. return ch_num;
  2453. }
  2454. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2455. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2456. cdc_dma_tx_cfg[ch_num].channels);
  2457. return 1;
  2458. }
  2459. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2460. struct snd_ctl_elem_value *ucontrol)
  2461. {
  2462. int sample_rate_val;
  2463. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2464. if (ch_num < 0) {
  2465. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2466. return ch_num;
  2467. }
  2468. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2469. case SAMPLING_RATE_384KHZ:
  2470. sample_rate_val = 12;
  2471. break;
  2472. case SAMPLING_RATE_352P8KHZ:
  2473. sample_rate_val = 11;
  2474. break;
  2475. case SAMPLING_RATE_192KHZ:
  2476. sample_rate_val = 10;
  2477. break;
  2478. case SAMPLING_RATE_176P4KHZ:
  2479. sample_rate_val = 9;
  2480. break;
  2481. case SAMPLING_RATE_96KHZ:
  2482. sample_rate_val = 8;
  2483. break;
  2484. case SAMPLING_RATE_88P2KHZ:
  2485. sample_rate_val = 7;
  2486. break;
  2487. case SAMPLING_RATE_48KHZ:
  2488. sample_rate_val = 6;
  2489. break;
  2490. case SAMPLING_RATE_44P1KHZ:
  2491. sample_rate_val = 5;
  2492. break;
  2493. case SAMPLING_RATE_32KHZ:
  2494. sample_rate_val = 4;
  2495. break;
  2496. case SAMPLING_RATE_22P05KHZ:
  2497. sample_rate_val = 3;
  2498. break;
  2499. case SAMPLING_RATE_16KHZ:
  2500. sample_rate_val = 2;
  2501. break;
  2502. case SAMPLING_RATE_11P025KHZ:
  2503. sample_rate_val = 1;
  2504. break;
  2505. case SAMPLING_RATE_8KHZ:
  2506. sample_rate_val = 0;
  2507. break;
  2508. default:
  2509. sample_rate_val = 6;
  2510. break;
  2511. }
  2512. ucontrol->value.integer.value[0] = sample_rate_val;
  2513. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2514. cdc_dma_tx_cfg[ch_num].sample_rate);
  2515. return 0;
  2516. }
  2517. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2518. struct snd_ctl_elem_value *ucontrol)
  2519. {
  2520. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2521. if (ch_num < 0) {
  2522. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2523. return ch_num;
  2524. }
  2525. switch (ucontrol->value.integer.value[0]) {
  2526. case 12:
  2527. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2528. break;
  2529. case 11:
  2530. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2531. break;
  2532. case 10:
  2533. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2534. break;
  2535. case 9:
  2536. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2537. break;
  2538. case 8:
  2539. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2540. break;
  2541. case 7:
  2542. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2543. break;
  2544. case 6:
  2545. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2546. break;
  2547. case 5:
  2548. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2549. break;
  2550. case 4:
  2551. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2552. break;
  2553. case 3:
  2554. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2555. break;
  2556. case 2:
  2557. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2558. break;
  2559. case 1:
  2560. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2561. break;
  2562. case 0:
  2563. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2564. break;
  2565. default:
  2566. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2567. break;
  2568. }
  2569. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2570. __func__, ucontrol->value.integer.value[0],
  2571. cdc_dma_tx_cfg[ch_num].sample_rate);
  2572. return 0;
  2573. }
  2574. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2575. struct snd_ctl_elem_value *ucontrol)
  2576. {
  2577. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2578. if (ch_num < 0) {
  2579. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2580. return ch_num;
  2581. }
  2582. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2583. case SNDRV_PCM_FORMAT_S32_LE:
  2584. ucontrol->value.integer.value[0] = 3;
  2585. break;
  2586. case SNDRV_PCM_FORMAT_S24_3LE:
  2587. ucontrol->value.integer.value[0] = 2;
  2588. break;
  2589. case SNDRV_PCM_FORMAT_S24_LE:
  2590. ucontrol->value.integer.value[0] = 1;
  2591. break;
  2592. case SNDRV_PCM_FORMAT_S16_LE:
  2593. default:
  2594. ucontrol->value.integer.value[0] = 0;
  2595. break;
  2596. }
  2597. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2598. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2599. ucontrol->value.integer.value[0]);
  2600. return 0;
  2601. }
  2602. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2603. struct snd_ctl_elem_value *ucontrol)
  2604. {
  2605. int rc = 0;
  2606. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2607. if (ch_num < 0) {
  2608. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2609. return ch_num;
  2610. }
  2611. switch (ucontrol->value.integer.value[0]) {
  2612. case 3:
  2613. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2614. break;
  2615. case 2:
  2616. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2617. break;
  2618. case 1:
  2619. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2620. break;
  2621. case 0:
  2622. default:
  2623. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2624. break;
  2625. }
  2626. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2627. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2628. ucontrol->value.integer.value[0]);
  2629. return rc;
  2630. }
  2631. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2632. {
  2633. int idx = 0;
  2634. switch (be_id) {
  2635. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2636. idx = RX_CDC_DMA_RX_0;
  2637. break;
  2638. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2639. idx = RX_CDC_DMA_RX_1;
  2640. break;
  2641. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2642. idx = RX_CDC_DMA_RX_2;
  2643. break;
  2644. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2645. idx = RX_CDC_DMA_RX_3;
  2646. break;
  2647. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2648. idx = RX_CDC_DMA_RX_5;
  2649. break;
  2650. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  2651. idx = RX_CDC_DMA_RX_6;
  2652. break;
  2653. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2654. idx = TX_CDC_DMA_TX_0;
  2655. break;
  2656. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2657. idx = TX_CDC_DMA_TX_3;
  2658. break;
  2659. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2660. idx = TX_CDC_DMA_TX_4;
  2661. break;
  2662. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2663. idx = VA_CDC_DMA_TX_0;
  2664. break;
  2665. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2666. idx = VA_CDC_DMA_TX_1;
  2667. break;
  2668. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2669. idx = VA_CDC_DMA_TX_2;
  2670. break;
  2671. default:
  2672. idx = RX_CDC_DMA_RX_0;
  2673. break;
  2674. }
  2675. return idx;
  2676. }
  2677. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2678. struct snd_ctl_elem_value *ucontrol)
  2679. {
  2680. /*
  2681. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2682. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2683. * value.
  2684. */
  2685. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2686. case SAMPLING_RATE_96KHZ:
  2687. ucontrol->value.integer.value[0] = 5;
  2688. break;
  2689. case SAMPLING_RATE_88P2KHZ:
  2690. ucontrol->value.integer.value[0] = 4;
  2691. break;
  2692. case SAMPLING_RATE_48KHZ:
  2693. ucontrol->value.integer.value[0] = 3;
  2694. break;
  2695. case SAMPLING_RATE_44P1KHZ:
  2696. ucontrol->value.integer.value[0] = 2;
  2697. break;
  2698. case SAMPLING_RATE_16KHZ:
  2699. ucontrol->value.integer.value[0] = 1;
  2700. break;
  2701. case SAMPLING_RATE_8KHZ:
  2702. default:
  2703. ucontrol->value.integer.value[0] = 0;
  2704. break;
  2705. }
  2706. pr_debug("%s: sample rate = %d\n", __func__,
  2707. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2708. return 0;
  2709. }
  2710. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2711. struct snd_ctl_elem_value *ucontrol)
  2712. {
  2713. switch (ucontrol->value.integer.value[0]) {
  2714. case 1:
  2715. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2716. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2717. break;
  2718. case 2:
  2719. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2720. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2721. break;
  2722. case 3:
  2723. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2724. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2725. break;
  2726. case 4:
  2727. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2728. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2729. break;
  2730. case 5:
  2731. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2732. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2733. break;
  2734. case 0:
  2735. default:
  2736. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2737. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2738. break;
  2739. }
  2740. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2741. __func__,
  2742. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2743. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2744. ucontrol->value.enumerated.item[0]);
  2745. return 0;
  2746. }
  2747. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2748. struct snd_ctl_elem_value *ucontrol)
  2749. {
  2750. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2751. case SAMPLING_RATE_96KHZ:
  2752. ucontrol->value.integer.value[0] = 5;
  2753. break;
  2754. case SAMPLING_RATE_88P2KHZ:
  2755. ucontrol->value.integer.value[0] = 4;
  2756. break;
  2757. case SAMPLING_RATE_48KHZ:
  2758. ucontrol->value.integer.value[0] = 3;
  2759. break;
  2760. case SAMPLING_RATE_44P1KHZ:
  2761. ucontrol->value.integer.value[0] = 2;
  2762. break;
  2763. case SAMPLING_RATE_16KHZ:
  2764. ucontrol->value.integer.value[0] = 1;
  2765. break;
  2766. case SAMPLING_RATE_8KHZ:
  2767. default:
  2768. ucontrol->value.integer.value[0] = 0;
  2769. break;
  2770. }
  2771. pr_debug("%s: sample rate rx = %d\n", __func__,
  2772. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2773. return 0;
  2774. }
  2775. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2776. struct snd_ctl_elem_value *ucontrol)
  2777. {
  2778. switch (ucontrol->value.integer.value[0]) {
  2779. case 1:
  2780. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2781. break;
  2782. case 2:
  2783. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2784. break;
  2785. case 3:
  2786. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2787. break;
  2788. case 4:
  2789. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2790. break;
  2791. case 5:
  2792. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2793. break;
  2794. case 0:
  2795. default:
  2796. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2797. break;
  2798. }
  2799. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2800. __func__,
  2801. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2802. ucontrol->value.enumerated.item[0]);
  2803. return 0;
  2804. }
  2805. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2806. struct snd_ctl_elem_value *ucontrol)
  2807. {
  2808. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2809. case SAMPLING_RATE_96KHZ:
  2810. ucontrol->value.integer.value[0] = 5;
  2811. break;
  2812. case SAMPLING_RATE_88P2KHZ:
  2813. ucontrol->value.integer.value[0] = 4;
  2814. break;
  2815. case SAMPLING_RATE_48KHZ:
  2816. ucontrol->value.integer.value[0] = 3;
  2817. break;
  2818. case SAMPLING_RATE_44P1KHZ:
  2819. ucontrol->value.integer.value[0] = 2;
  2820. break;
  2821. case SAMPLING_RATE_16KHZ:
  2822. ucontrol->value.integer.value[0] = 1;
  2823. break;
  2824. case SAMPLING_RATE_8KHZ:
  2825. default:
  2826. ucontrol->value.integer.value[0] = 0;
  2827. break;
  2828. }
  2829. pr_debug("%s: sample rate tx = %d\n", __func__,
  2830. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2831. return 0;
  2832. }
  2833. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2834. struct snd_ctl_elem_value *ucontrol)
  2835. {
  2836. switch (ucontrol->value.integer.value[0]) {
  2837. case 1:
  2838. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2839. break;
  2840. case 2:
  2841. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2842. break;
  2843. case 3:
  2844. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2845. break;
  2846. case 4:
  2847. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2848. break;
  2849. case 5:
  2850. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2851. break;
  2852. case 0:
  2853. default:
  2854. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2855. break;
  2856. }
  2857. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2858. __func__,
  2859. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2860. ucontrol->value.enumerated.item[0]);
  2861. return 0;
  2862. }
  2863. static const struct snd_kcontrol_new msm_int_wcd937x_snd_controls[] = {
  2864. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2865. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2866. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2867. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2868. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2869. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2870. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2871. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2872. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2873. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2874. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2875. rx_cdc_dma_rx_0_sample_rate,
  2876. cdc_dma_rx_sample_rate_get,
  2877. cdc_dma_rx_sample_rate_put),
  2878. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2879. rx_cdc_dma_rx_1_sample_rate,
  2880. cdc_dma_rx_sample_rate_get,
  2881. cdc_dma_rx_sample_rate_put),
  2882. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2883. rx_cdc_dma_rx_2_sample_rate,
  2884. cdc_dma_rx_sample_rate_get,
  2885. cdc_dma_rx_sample_rate_put),
  2886. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2887. rx_cdc_dma_rx_3_sample_rate,
  2888. cdc_dma_rx_sample_rate_get,
  2889. cdc_dma_rx_sample_rate_put),
  2890. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2891. rx_cdc_dma_rx_5_sample_rate,
  2892. cdc_dma_rx_sample_rate_get,
  2893. cdc_dma_rx_sample_rate_put),
  2894. };
  2895. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2896. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2897. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2898. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2899. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2900. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2901. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2902. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2903. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2904. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2905. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2906. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Channels", rx_cdc_dma_rx_6_chs,
  2907. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2908. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2909. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2910. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2911. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2912. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2913. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2914. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2915. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2916. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2917. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2918. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2919. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2920. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2921. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2922. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2923. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2924. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2925. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2926. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2927. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2928. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2929. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2930. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2931. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2932. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2933. tx_cdc_dma_tx_0_sample_rate,
  2934. cdc_dma_tx_sample_rate_get,
  2935. cdc_dma_tx_sample_rate_put),
  2936. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2937. tx_cdc_dma_tx_3_sample_rate,
  2938. cdc_dma_tx_sample_rate_get,
  2939. cdc_dma_tx_sample_rate_put),
  2940. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2941. tx_cdc_dma_tx_4_sample_rate,
  2942. cdc_dma_tx_sample_rate_get,
  2943. cdc_dma_tx_sample_rate_put),
  2944. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2945. va_cdc_dma_tx_0_sample_rate,
  2946. cdc_dma_tx_sample_rate_get,
  2947. cdc_dma_tx_sample_rate_put),
  2948. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2949. va_cdc_dma_tx_1_sample_rate,
  2950. cdc_dma_tx_sample_rate_get,
  2951. cdc_dma_tx_sample_rate_put),
  2952. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2953. va_cdc_dma_tx_2_sample_rate,
  2954. cdc_dma_tx_sample_rate_get,
  2955. cdc_dma_tx_sample_rate_put),
  2956. };
  2957. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  2958. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  2959. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2960. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  2961. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2962. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  2963. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2964. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  2965. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2966. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  2967. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2968. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc80_dma_rx_6_format,
  2969. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2970. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2971. rx_cdc80_dma_rx_0_sample_rate,
  2972. cdc_dma_rx_sample_rate_get,
  2973. cdc_dma_rx_sample_rate_put),
  2974. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2975. rx_cdc80_dma_rx_1_sample_rate,
  2976. cdc_dma_rx_sample_rate_get,
  2977. cdc_dma_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2979. rx_cdc80_dma_rx_2_sample_rate,
  2980. cdc_dma_rx_sample_rate_get,
  2981. cdc_dma_rx_sample_rate_put),
  2982. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2983. rx_cdc80_dma_rx_3_sample_rate,
  2984. cdc_dma_rx_sample_rate_get,
  2985. cdc_dma_rx_sample_rate_put),
  2986. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2987. rx_cdc80_dma_rx_5_sample_rate,
  2988. cdc_dma_rx_sample_rate_get,
  2989. cdc_dma_rx_sample_rate_put),
  2990. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  2991. rx_cdc80_dma_rx_6_sample_rate,
  2992. cdc_dma_rx_sample_rate_get,
  2993. cdc_dma_rx_sample_rate_put),
  2994. };
  2995. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  2996. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  2997. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2998. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  2999. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3000. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3001. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3002. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3003. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3004. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3005. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3006. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc85_dma_rx_6_format,
  3007. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3008. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3009. rx_cdc85_dma_rx_0_sample_rate,
  3010. cdc_dma_rx_sample_rate_get,
  3011. cdc_dma_rx_sample_rate_put),
  3012. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3013. rx_cdc85_dma_rx_1_sample_rate,
  3014. cdc_dma_rx_sample_rate_get,
  3015. cdc_dma_rx_sample_rate_put),
  3016. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3017. rx_cdc85_dma_rx_2_sample_rate,
  3018. cdc_dma_rx_sample_rate_get,
  3019. cdc_dma_rx_sample_rate_put),
  3020. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3021. rx_cdc85_dma_rx_3_sample_rate,
  3022. cdc_dma_rx_sample_rate_get,
  3023. cdc_dma_rx_sample_rate_put),
  3024. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3025. rx_cdc85_dma_rx_5_sample_rate,
  3026. cdc_dma_rx_sample_rate_get,
  3027. cdc_dma_rx_sample_rate_put),
  3028. SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate",
  3029. rx_cdc85_dma_rx_6_sample_rate,
  3030. cdc_dma_rx_sample_rate_get,
  3031. cdc_dma_rx_sample_rate_put),
  3032. };
  3033. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3034. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3035. usb_audio_rx_sample_rate_get,
  3036. usb_audio_rx_sample_rate_put),
  3037. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3038. usb_audio_tx_sample_rate_get,
  3039. usb_audio_tx_sample_rate_put),
  3040. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3041. tdm_rx_sample_rate_get,
  3042. tdm_rx_sample_rate_put),
  3043. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3044. tdm_rx_sample_rate_get,
  3045. tdm_rx_sample_rate_put),
  3046. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3047. tdm_rx_sample_rate_get,
  3048. tdm_rx_sample_rate_put),
  3049. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3050. tdm_rx_sample_rate_get,
  3051. tdm_rx_sample_rate_put),
  3052. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3053. tdm_tx_sample_rate_get,
  3054. tdm_tx_sample_rate_put),
  3055. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3056. tdm_tx_sample_rate_get,
  3057. tdm_tx_sample_rate_put),
  3058. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3059. tdm_tx_sample_rate_get,
  3060. tdm_tx_sample_rate_put),
  3061. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3062. tdm_tx_sample_rate_get,
  3063. tdm_tx_sample_rate_put),
  3064. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3065. aux_pcm_rx_sample_rate_get,
  3066. aux_pcm_rx_sample_rate_put),
  3067. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3068. aux_pcm_rx_sample_rate_get,
  3069. aux_pcm_rx_sample_rate_put),
  3070. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3071. aux_pcm_rx_sample_rate_get,
  3072. aux_pcm_rx_sample_rate_put),
  3073. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3074. aux_pcm_rx_sample_rate_get,
  3075. aux_pcm_rx_sample_rate_put),
  3076. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3077. aux_pcm_tx_sample_rate_get,
  3078. aux_pcm_tx_sample_rate_put),
  3079. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3080. aux_pcm_tx_sample_rate_get,
  3081. aux_pcm_tx_sample_rate_put),
  3082. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3083. aux_pcm_tx_sample_rate_get,
  3084. aux_pcm_tx_sample_rate_put),
  3085. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3086. aux_pcm_tx_sample_rate_get,
  3087. aux_pcm_tx_sample_rate_put),
  3088. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3089. mi2s_rx_sample_rate_get,
  3090. mi2s_rx_sample_rate_put),
  3091. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3092. mi2s_rx_sample_rate_get,
  3093. mi2s_rx_sample_rate_put),
  3094. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3095. mi2s_rx_sample_rate_get,
  3096. mi2s_rx_sample_rate_put),
  3097. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3098. mi2s_rx_sample_rate_get,
  3099. mi2s_rx_sample_rate_put),
  3100. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3101. mi2s_tx_sample_rate_get,
  3102. mi2s_tx_sample_rate_put),
  3103. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3104. mi2s_tx_sample_rate_get,
  3105. mi2s_tx_sample_rate_put),
  3106. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3107. mi2s_tx_sample_rate_get,
  3108. mi2s_tx_sample_rate_put),
  3109. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3110. mi2s_tx_sample_rate_get,
  3111. mi2s_tx_sample_rate_put),
  3112. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3113. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3114. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3115. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3116. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3117. tdm_rx_format_get,
  3118. tdm_rx_format_put),
  3119. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3120. tdm_rx_format_get,
  3121. tdm_rx_format_put),
  3122. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3123. tdm_rx_format_get,
  3124. tdm_rx_format_put),
  3125. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3126. tdm_rx_format_get,
  3127. tdm_rx_format_put),
  3128. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3129. tdm_tx_format_get,
  3130. tdm_tx_format_put),
  3131. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3132. tdm_tx_format_get,
  3133. tdm_tx_format_put),
  3134. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3135. tdm_tx_format_get,
  3136. tdm_tx_format_put),
  3137. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3138. tdm_tx_format_get,
  3139. tdm_tx_format_put),
  3140. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3141. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3142. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3143. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3144. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3145. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3146. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3147. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3148. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3149. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3150. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3151. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3152. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3153. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3154. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3155. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3156. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3157. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3158. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3159. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3160. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3161. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3162. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3163. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3164. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3165. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3166. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3167. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3168. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3169. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3170. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3171. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3172. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3173. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3174. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3175. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3176. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3177. proxy_rx_ch_get, proxy_rx_ch_put),
  3178. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3179. tdm_rx_ch_get,
  3180. tdm_rx_ch_put),
  3181. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3182. tdm_rx_ch_get,
  3183. tdm_rx_ch_put),
  3184. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3185. tdm_rx_ch_get,
  3186. tdm_rx_ch_put),
  3187. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3188. tdm_rx_ch_get,
  3189. tdm_rx_ch_put),
  3190. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3191. tdm_tx_ch_get,
  3192. tdm_tx_ch_put),
  3193. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3194. tdm_tx_ch_get,
  3195. tdm_tx_ch_put),
  3196. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3197. tdm_tx_ch_get,
  3198. tdm_tx_ch_put),
  3199. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3200. tdm_tx_ch_get,
  3201. tdm_tx_ch_put),
  3202. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3203. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3204. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3205. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3206. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3207. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3208. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3209. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3210. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3211. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3212. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3213. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3214. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3215. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3216. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3217. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3218. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3219. msm_bt_sample_rate_get,
  3220. msm_bt_sample_rate_put),
  3221. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3222. msm_bt_sample_rate_rx_get,
  3223. msm_bt_sample_rate_rx_put),
  3224. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3225. msm_bt_sample_rate_tx_get,
  3226. msm_bt_sample_rate_tx_put),
  3227. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3228. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3229. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3230. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3231. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3232. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3233. };
  3234. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3235. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3236. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3237. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3238. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3239. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3240. aux_pcm_rx_sample_rate_get,
  3241. aux_pcm_rx_sample_rate_put),
  3242. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3243. aux_pcm_tx_sample_rate_get,
  3244. aux_pcm_tx_sample_rate_put),
  3245. };
  3246. static int holi_send_island_va_config(int32_t be_id)
  3247. {
  3248. int rc = 0;
  3249. int port_id = 0xFFFF;
  3250. port_id = msm_get_port_id(be_id);
  3251. if (port_id < 0) {
  3252. pr_err("%s: Invalid island interface, be_id: %d\n",
  3253. __func__, be_id);
  3254. rc = -EINVAL;
  3255. } else {
  3256. /*
  3257. * send island mode config
  3258. * This should be the first configuration
  3259. */
  3260. rc = afe_send_port_island_mode(port_id);
  3261. if (rc)
  3262. pr_err("%s: afe send island mode failed %d\n",
  3263. __func__, rc);
  3264. }
  3265. return rc;
  3266. }
  3267. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3268. struct snd_pcm_hw_params *params)
  3269. {
  3270. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3271. struct snd_interval *rate = hw_param_interval(params,
  3272. SNDRV_PCM_HW_PARAM_RATE);
  3273. struct snd_interval *channels = hw_param_interval(params,
  3274. SNDRV_PCM_HW_PARAM_CHANNELS);
  3275. int idx = 0, rc = 0;
  3276. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3277. __func__, dai_link->id, params_format(params),
  3278. params_rate(params));
  3279. switch (dai_link->id) {
  3280. case MSM_BACKEND_DAI_USB_RX:
  3281. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3282. usb_rx_cfg.bit_format);
  3283. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3284. channels->min = channels->max = usb_rx_cfg.channels;
  3285. break;
  3286. case MSM_BACKEND_DAI_USB_TX:
  3287. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3288. usb_tx_cfg.bit_format);
  3289. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3290. channels->min = channels->max = usb_tx_cfg.channels;
  3291. break;
  3292. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3293. channels->min = channels->max = proxy_rx_cfg.channels;
  3294. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3295. break;
  3296. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3297. channels->min = channels->max =
  3298. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3299. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3300. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3301. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3302. break;
  3303. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3304. channels->min = channels->max =
  3305. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3306. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3307. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3308. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3309. break;
  3310. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3311. channels->min = channels->max =
  3312. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3313. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3314. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3315. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3316. break;
  3317. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3318. channels->min = channels->max =
  3319. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3320. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3321. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3322. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3323. break;
  3324. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3325. channels->min = channels->max =
  3326. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3327. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3328. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3329. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3330. break;
  3331. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3332. channels->min = channels->max =
  3333. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3334. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3335. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3336. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3337. break;
  3338. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3339. channels->min = channels->max =
  3340. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3341. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3342. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3343. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3344. break;
  3345. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3346. channels->min = channels->max =
  3347. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3348. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3349. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3350. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3351. break;
  3352. case MSM_BACKEND_DAI_AUXPCM_RX:
  3353. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3354. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3355. rate->min = rate->max =
  3356. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3357. channels->min = channels->max =
  3358. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3359. break;
  3360. case MSM_BACKEND_DAI_AUXPCM_TX:
  3361. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3362. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3363. rate->min = rate->max =
  3364. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3365. channels->min = channels->max =
  3366. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3367. break;
  3368. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3369. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3370. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3371. rate->min = rate->max =
  3372. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3373. channels->min = channels->max =
  3374. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3375. break;
  3376. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3377. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3378. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3379. rate->min = rate->max =
  3380. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3381. channels->min = channels->max =
  3382. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3383. break;
  3384. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3385. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3386. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3387. rate->min = rate->max =
  3388. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3389. channels->min = channels->max =
  3390. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3391. break;
  3392. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3393. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3394. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3395. rate->min = rate->max =
  3396. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3397. channels->min = channels->max =
  3398. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3399. break;
  3400. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3401. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3402. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3403. rate->min = rate->max =
  3404. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3405. channels->min = channels->max =
  3406. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3407. break;
  3408. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3409. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3410. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3411. rate->min = rate->max =
  3412. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3413. channels->min = channels->max =
  3414. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3415. break;
  3416. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3417. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3418. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3419. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3420. channels->min = channels->max =
  3421. mi2s_rx_cfg[PRIM_MI2S].channels;
  3422. break;
  3423. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3424. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3425. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3426. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3427. channels->min = channels->max =
  3428. mi2s_tx_cfg[PRIM_MI2S].channels;
  3429. break;
  3430. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3431. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3432. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3433. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3434. channels->min = channels->max =
  3435. mi2s_rx_cfg[SEC_MI2S].channels;
  3436. break;
  3437. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3438. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3439. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3440. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3441. channels->min = channels->max =
  3442. mi2s_tx_cfg[SEC_MI2S].channels;
  3443. break;
  3444. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3445. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3446. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3447. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3448. channels->min = channels->max =
  3449. mi2s_rx_cfg[TERT_MI2S].channels;
  3450. break;
  3451. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3452. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3453. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3454. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3455. channels->min = channels->max =
  3456. mi2s_tx_cfg[TERT_MI2S].channels;
  3457. break;
  3458. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3459. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3460. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3461. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3462. channels->min = channels->max =
  3463. mi2s_rx_cfg[QUAT_MI2S].channels;
  3464. break;
  3465. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3466. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3467. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3468. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3469. channels->min = channels->max =
  3470. mi2s_tx_cfg[QUAT_MI2S].channels;
  3471. break;
  3472. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3473. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3474. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3475. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3476. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3477. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3478. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3479. cdc_dma_rx_cfg[idx].bit_format);
  3480. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3481. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3482. break;
  3483. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3484. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3485. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3486. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3487. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3488. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3489. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3490. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3491. cdc_dma_tx_cfg[idx].bit_format);
  3492. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3493. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3494. break;
  3495. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3496. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3497. slim_rx_cfg[SLIM_RX_7].bit_format);
  3498. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3499. channels->min = channels->max =
  3500. slim_rx_cfg[SLIM_RX_7].channels;
  3501. break;
  3502. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3503. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3504. slim_tx_cfg[SLIM_TX_7].bit_format);
  3505. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3506. channels->min = channels->max =
  3507. slim_tx_cfg[SLIM_TX_7].channels;
  3508. break;
  3509. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3510. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3511. channels->min = channels->max =
  3512. slim_tx_cfg[SLIM_TX_8].channels;
  3513. break;
  3514. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3515. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3516. afe_loopback_tx_cfg[idx].bit_format);
  3517. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3518. channels->min = channels->max =
  3519. afe_loopback_tx_cfg[idx].channels;
  3520. break;
  3521. default:
  3522. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3523. break;
  3524. }
  3525. return rc;
  3526. }
  3527. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
  3528. bool active)
  3529. {
  3530. struct snd_soc_card *card = component->card;
  3531. struct msm_asoc_mach_data *pdata =
  3532. snd_soc_card_get_drvdata(card);
  3533. if (!pdata->fsa_handle)
  3534. return false;
  3535. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3536. }
  3537. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3538. {
  3539. int value = 0;
  3540. bool ret = false;
  3541. struct snd_soc_card *card;
  3542. struct msm_asoc_mach_data *pdata;
  3543. if (!component) {
  3544. pr_err("%s component is NULL\n", __func__);
  3545. return false;
  3546. }
  3547. card = component->card;
  3548. pdata = snd_soc_card_get_drvdata(card);
  3549. if (!pdata)
  3550. return false;
  3551. if (wcd_mbhc_cfg.enable_usbc_analog)
  3552. return msm_usbc_swap_gnd_mic(component, active);
  3553. /* if usbc is not defined, swap using us_euro_gpio_p */
  3554. if (pdata->us_euro_gpio_p) {
  3555. value = msm_cdc_pinctrl_get_state(
  3556. pdata->us_euro_gpio_p);
  3557. if (value)
  3558. msm_cdc_pinctrl_select_sleep_state(
  3559. pdata->us_euro_gpio_p);
  3560. else
  3561. msm_cdc_pinctrl_select_active_state(
  3562. pdata->us_euro_gpio_p);
  3563. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3564. __func__, value, !value);
  3565. ret = true;
  3566. }
  3567. return ret;
  3568. }
  3569. static int holi_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3570. struct snd_pcm_hw_params *params)
  3571. {
  3572. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3573. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3574. int ret = 0;
  3575. int slot_width = TDM_SLOT_WIDTH_BITS;
  3576. int channels, slots = TDM_MAX_SLOTS;
  3577. unsigned int slot_mask, rate, clk_freq;
  3578. unsigned int *slot_offset;
  3579. struct tdm_dev_config *config;
  3580. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  3581. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3582. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  3583. pr_err("%s: dai id 0x%x not supported\n",
  3584. __func__, cpu_dai->id);
  3585. return -EINVAL;
  3586. }
  3587. /* RX or TX */
  3588. path_dir = cpu_dai->id % MAX_PATH;
  3589. /* PRI, SEC, TERT, QUAT ... */
  3590. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  3591. / (MAX_PATH * TDM_PORT_MAX);
  3592. /* 0, 1, 2, .. 7 */
  3593. channel_interface =
  3594. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  3595. % TDM_PORT_MAX;
  3596. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  3597. __func__, path_dir, interface, channel_interface);
  3598. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  3599. (path_dir * TDM_PORT_MAX) + channel_interface;
  3600. slot_offset = config->tdm_slot_offset;
  3601. if (path_dir)
  3602. channels = tdm_tx_cfg[interface][channel_interface].channels;
  3603. else
  3604. channels = tdm_rx_cfg[interface][channel_interface].channels;
  3605. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3606. /*2 slot config - bits 0 and 1 set for the first two slots */
  3607. slot_mask = 0x0000FFFF >> (16 - slots);
  3608. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  3609. __func__, slot_width, slots, slot_mask);
  3610. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3611. slots, slot_width);
  3612. if (ret < 0) {
  3613. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3614. __func__, ret);
  3615. goto end;
  3616. }
  3617. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  3618. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3619. 0, NULL, channels, slot_offset);
  3620. if (ret < 0) {
  3621. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3622. __func__, ret);
  3623. goto end;
  3624. }
  3625. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3626. /*2 slot config - bits 0 and 1 set for the first two slots */
  3627. slot_mask = 0x0000FFFF >> (16 - slots);
  3628. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  3629. __func__, slot_width, slots, slot_mask);
  3630. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3631. slots, slot_width);
  3632. if (ret < 0) {
  3633. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3634. __func__, ret);
  3635. goto end;
  3636. }
  3637. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  3638. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3639. channels, slot_offset, 0, NULL);
  3640. if (ret < 0) {
  3641. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3642. __func__, ret);
  3643. goto end;
  3644. }
  3645. } else {
  3646. ret = -EINVAL;
  3647. pr_err("%s: invalid use case, err:%d\n",
  3648. __func__, ret);
  3649. goto end;
  3650. }
  3651. rate = params_rate(params);
  3652. clk_freq = rate * slot_width * slots;
  3653. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3654. if (ret < 0)
  3655. pr_err("%s: failed to set tdm clk, err:%d\n",
  3656. __func__, ret);
  3657. end:
  3658. return ret;
  3659. }
  3660. static int msm_get_tdm_mode(u32 port_id)
  3661. {
  3662. int tdm_mode;
  3663. switch (port_id) {
  3664. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3665. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3666. tdm_mode = TDM_PRI;
  3667. break;
  3668. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3669. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3670. tdm_mode = TDM_SEC;
  3671. break;
  3672. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3673. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3674. tdm_mode = TDM_TERT;
  3675. break;
  3676. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3677. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3678. tdm_mode = TDM_QUAT;
  3679. break;
  3680. default:
  3681. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3682. tdm_mode = -EINVAL;
  3683. }
  3684. return tdm_mode;
  3685. }
  3686. static int holi_tdm_snd_startup(struct snd_pcm_substream *substream)
  3687. {
  3688. int ret = 0;
  3689. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3690. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3691. struct snd_soc_card *card = rtd->card;
  3692. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3693. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3694. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3695. ret = -EINVAL;
  3696. pr_err("%s: Invalid TDM interface %d\n",
  3697. __func__, ret);
  3698. return ret;
  3699. }
  3700. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3701. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3702. == 0) {
  3703. ret = msm_cdc_pinctrl_select_active_state(
  3704. pdata->mi2s_gpio_p[tdm_mode]);
  3705. if (ret) {
  3706. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3707. __func__, ret);
  3708. goto done;
  3709. }
  3710. }
  3711. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3712. }
  3713. done:
  3714. return ret;
  3715. }
  3716. static void holi_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3717. {
  3718. int ret = 0;
  3719. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3720. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3721. struct snd_soc_card *card = rtd->card;
  3722. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3723. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3724. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3725. ret = -EINVAL;
  3726. pr_err("%s: Invalid TDM interface %d\n",
  3727. __func__, ret);
  3728. return;
  3729. }
  3730. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3731. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3732. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3733. == 0) {
  3734. ret = msm_cdc_pinctrl_select_sleep_state(
  3735. pdata->mi2s_gpio_p[tdm_mode]);
  3736. if (ret)
  3737. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3738. __func__, ret);
  3739. }
  3740. }
  3741. }
  3742. static int holi_aux_snd_startup(struct snd_pcm_substream *substream)
  3743. {
  3744. int ret = 0;
  3745. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3746. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3747. struct snd_soc_card *card = rtd->card;
  3748. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3749. u32 aux_mode = cpu_dai->id - 1;
  3750. if (aux_mode >= AUX_PCM_MAX) {
  3751. ret = -EINVAL;
  3752. pr_err("%s: Invalid AUX interface %d\n",
  3753. __func__, ret);
  3754. return ret;
  3755. }
  3756. if (pdata->mi2s_gpio_p[aux_mode]) {
  3757. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3758. == 0) {
  3759. ret = msm_cdc_pinctrl_select_active_state(
  3760. pdata->mi2s_gpio_p[aux_mode]);
  3761. if (ret) {
  3762. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3763. __func__, ret);
  3764. goto done;
  3765. }
  3766. }
  3767. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3768. }
  3769. done:
  3770. return ret;
  3771. }
  3772. static void holi_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3773. {
  3774. int ret = 0;
  3775. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3776. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3777. struct snd_soc_card *card = rtd->card;
  3778. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3779. u32 aux_mode = cpu_dai->id - 1;
  3780. if (aux_mode >= AUX_PCM_MAX) {
  3781. pr_err("%s: Invalid AUX interface %d\n",
  3782. __func__, ret);
  3783. return;
  3784. }
  3785. if (pdata->mi2s_gpio_p[aux_mode]) {
  3786. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3787. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3788. == 0) {
  3789. ret = msm_cdc_pinctrl_select_sleep_state(
  3790. pdata->mi2s_gpio_p[aux_mode]);
  3791. if (ret)
  3792. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  3793. __func__, ret);
  3794. }
  3795. }
  3796. }
  3797. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  3798. {
  3799. int ret = 0;
  3800. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3801. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3802. switch (dai_link->id) {
  3803. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3804. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3805. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3806. ret = holi_send_island_va_config(dai_link->id);
  3807. if (ret)
  3808. pr_err("%s: send island va cfg failed, err: %d\n",
  3809. __func__, ret);
  3810. break;
  3811. }
  3812. return ret;
  3813. }
  3814. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3815. struct snd_pcm_hw_params *params)
  3816. {
  3817. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3818. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3819. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3820. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3821. int ret = 0;
  3822. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3823. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3824. u32 user_set_tx_ch = 0;
  3825. u32 user_set_rx_ch = 0;
  3826. u32 ch_id;
  3827. ret = snd_soc_dai_get_channel_map(codec_dai,
  3828. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3829. &rx_ch_cdc_dma);
  3830. if (ret < 0) {
  3831. pr_err("%s: failed to get codec chan map, err:%d\n",
  3832. __func__, ret);
  3833. goto err;
  3834. }
  3835. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3836. switch (dai_link->id) {
  3837. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3838. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3839. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3840. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3841. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3842. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3843. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6:
  3844. {
  3845. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3846. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3847. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3848. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3849. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3850. user_set_rx_ch, &rx_ch_cdc_dma);
  3851. if (ret < 0) {
  3852. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3853. __func__, ret);
  3854. goto err;
  3855. }
  3856. }
  3857. break;
  3858. }
  3859. } else {
  3860. switch (dai_link->id) {
  3861. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3862. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3863. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3864. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3865. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3866. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3867. {
  3868. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3869. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3870. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3871. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3872. }
  3873. break;
  3874. }
  3875. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3876. &tx_ch_cdc_dma, 0, 0);
  3877. if (ret < 0) {
  3878. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3879. __func__, ret);
  3880. goto err;
  3881. }
  3882. }
  3883. err:
  3884. return ret;
  3885. }
  3886. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3887. {
  3888. (void)substream;
  3889. qos_client_active_cnt++;
  3890. if (qos_client_active_cnt == 1)
  3891. msm_audio_update_qos_request(MSM_LL_QOS_VALUE);
  3892. return 0;
  3893. }
  3894. static void msm_fe_qos_shutdown(struct snd_pcm_substream *substream)
  3895. {
  3896. (void)substream;
  3897. if (qos_client_active_cnt > 0)
  3898. qos_client_active_cnt--;
  3899. if (qos_client_active_cnt == 0)
  3900. msm_audio_update_qos_request(PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE);
  3901. }
  3902. void mi2s_disable_audio_vote(struct snd_pcm_substream *substream)
  3903. {
  3904. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3905. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3906. int index = cpu_dai->id;
  3907. struct snd_soc_card *card = rtd->card;
  3908. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3909. int sample_rate = 0;
  3910. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3911. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3912. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3913. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3914. } else {
  3915. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3916. return;
  3917. }
  3918. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3919. if (pdata->lpass_audio_hw_vote != NULL) {
  3920. if (--pdata->core_audio_vote_count == 0) {
  3921. clk_disable_unprepare(
  3922. pdata->lpass_audio_hw_vote);
  3923. } else if (pdata->core_audio_vote_count < 0) {
  3924. pr_err("%s: audio vote mismatch\n", __func__);
  3925. pdata->core_audio_vote_count = 0;
  3926. }
  3927. } else {
  3928. pr_err("%s: Invalid lpass audio hw node\n", __func__);
  3929. }
  3930. }
  3931. }
  3932. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3933. {
  3934. int ret = 0;
  3935. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3936. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3937. int index = cpu_dai->id;
  3938. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3939. struct snd_soc_card *card = rtd->card;
  3940. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3941. int sample_rate = 0;
  3942. dev_dbg(rtd->card->dev,
  3943. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3944. __func__, substream->name, substream->stream,
  3945. cpu_dai->name, cpu_dai->id);
  3946. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3947. ret = -EINVAL;
  3948. dev_err(rtd->card->dev,
  3949. "%s: CPU DAI id (%d) out of range\n",
  3950. __func__, cpu_dai->id);
  3951. goto err;
  3952. }
  3953. /*
  3954. * Mutex protection in case the same MI2S
  3955. * interface using for both TX and RX so
  3956. * that the same clock won't be enable twice.
  3957. */
  3958. mutex_lock(&mi2s_intf_conf[index].lock);
  3959. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3960. sample_rate = mi2s_rx_cfg[index].sample_rate;
  3961. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3962. sample_rate = mi2s_tx_cfg[index].sample_rate;
  3963. } else {
  3964. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  3965. ret = -EINVAL;
  3966. goto vote_err;
  3967. }
  3968. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  3969. if (pdata->lpass_audio_hw_vote == NULL) {
  3970. dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n",
  3971. __func__);
  3972. ret = -EINVAL;
  3973. goto vote_err;
  3974. }
  3975. if (pdata->core_audio_vote_count == 0) {
  3976. ret = clk_prepare_enable(pdata->lpass_audio_hw_vote);
  3977. if (ret < 0) {
  3978. dev_err(rtd->card->dev, "%s: audio vote error\n",
  3979. __func__);
  3980. goto vote_err;
  3981. }
  3982. }
  3983. pdata->core_audio_vote_count++;
  3984. }
  3985. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3986. /* Check if msm needs to provide the clock to the interface */
  3987. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3988. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3989. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3990. }
  3991. ret = msm_mi2s_set_sclk(substream, true);
  3992. if (ret < 0) {
  3993. dev_err(rtd->card->dev,
  3994. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3995. __func__, ret);
  3996. goto clean_up;
  3997. }
  3998. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3999. if (ret < 0) {
  4000. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4001. __func__, index, ret);
  4002. goto clk_off;
  4003. }
  4004. if (pdata->mi2s_gpio_p[index]) {
  4005. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4006. == 0) {
  4007. ret = msm_cdc_pinctrl_select_active_state(
  4008. pdata->mi2s_gpio_p[index]);
  4009. if (ret) {
  4010. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4011. __func__, ret);
  4012. goto clk_off;
  4013. }
  4014. }
  4015. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4016. }
  4017. }
  4018. clk_off:
  4019. if (ret < 0)
  4020. msm_mi2s_set_sclk(substream, false);
  4021. clean_up:
  4022. if (ret < 0) {
  4023. mi2s_intf_conf[index].ref_cnt--;
  4024. mi2s_disable_audio_vote(substream);
  4025. }
  4026. vote_err:
  4027. mutex_unlock(&mi2s_intf_conf[index].lock);
  4028. err:
  4029. return ret;
  4030. }
  4031. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4032. {
  4033. int ret = 0;
  4034. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4035. int index = rtd->cpu_dai->id;
  4036. struct snd_soc_card *card = rtd->card;
  4037. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4038. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4039. substream->name, substream->stream);
  4040. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4041. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4042. return;
  4043. }
  4044. mutex_lock(&mi2s_intf_conf[index].lock);
  4045. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4046. if (pdata->mi2s_gpio_p[index]) {
  4047. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4048. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4049. == 0) {
  4050. ret = msm_cdc_pinctrl_select_sleep_state(
  4051. pdata->mi2s_gpio_p[index]);
  4052. if (ret)
  4053. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4054. __func__, ret);
  4055. }
  4056. }
  4057. ret = msm_mi2s_set_sclk(substream, false);
  4058. if (ret < 0)
  4059. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4060. __func__, index, ret);
  4061. }
  4062. mi2s_disable_audio_vote(substream);
  4063. mutex_unlock(&mi2s_intf_conf[index].lock);
  4064. }
  4065. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4066. struct snd_pcm_hw_params *params)
  4067. {
  4068. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4069. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4070. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4071. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4072. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4073. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4074. int ret = 0;
  4075. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4076. codec_dai->name, codec_dai->id);
  4077. ret = snd_soc_dai_get_channel_map(codec_dai,
  4078. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4079. if (ret) {
  4080. dev_err(rtd->dev,
  4081. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4082. __func__, ret);
  4083. goto err;
  4084. }
  4085. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4086. __func__, tx_ch_cnt, dai_link->id);
  4087. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4088. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4089. if (ret)
  4090. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4091. __func__, ret);
  4092. err:
  4093. return ret;
  4094. }
  4095. static struct snd_soc_ops holi_aux_be_ops = {
  4096. .startup = holi_aux_snd_startup,
  4097. .shutdown = holi_aux_snd_shutdown
  4098. };
  4099. static struct snd_soc_ops holi_tdm_be_ops = {
  4100. .hw_params = holi_tdm_snd_hw_params,
  4101. .startup = holi_tdm_snd_startup,
  4102. .shutdown = holi_tdm_snd_shutdown
  4103. };
  4104. static struct snd_soc_ops msm_mi2s_be_ops = {
  4105. .startup = msm_mi2s_snd_startup,
  4106. .shutdown = msm_mi2s_snd_shutdown,
  4107. };
  4108. static struct snd_soc_ops msm_fe_qos_ops = {
  4109. .prepare = msm_fe_qos_prepare,
  4110. .shutdown = msm_fe_qos_shutdown,
  4111. };
  4112. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4113. .startup = msm_snd_cdc_dma_startup,
  4114. .hw_params = msm_snd_cdc_dma_hw_params,
  4115. };
  4116. static struct snd_soc_ops msm_wcn_ops_lito = {
  4117. .hw_params = msm_wcn_hw_params_lito,
  4118. };
  4119. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4120. struct snd_kcontrol *kcontrol, int event)
  4121. {
  4122. struct msm_asoc_mach_data *pdata = NULL;
  4123. struct snd_soc_component *component =
  4124. snd_soc_dapm_to_component(w->dapm);
  4125. int ret = 0;
  4126. u32 dmic_idx;
  4127. int *dmic_gpio_cnt;
  4128. struct device_node *dmic_gpio;
  4129. char *wname;
  4130. wname = strpbrk(w->name, "012345");
  4131. if (!wname) {
  4132. dev_err(component->dev, "%s: widget not found\n", __func__);
  4133. return -EINVAL;
  4134. }
  4135. ret = kstrtouint(wname, 10, &dmic_idx);
  4136. if (ret < 0) {
  4137. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4138. __func__);
  4139. return -EINVAL;
  4140. }
  4141. pdata = snd_soc_card_get_drvdata(component->card);
  4142. switch (dmic_idx) {
  4143. case 0:
  4144. case 1:
  4145. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4146. dmic_gpio = pdata->dmic01_gpio_p;
  4147. break;
  4148. case 2:
  4149. case 3:
  4150. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4151. dmic_gpio = pdata->dmic23_gpio_p;
  4152. break;
  4153. case 4:
  4154. case 5:
  4155. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4156. dmic_gpio = pdata->dmic45_gpio_p;
  4157. break;
  4158. default:
  4159. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4160. __func__);
  4161. return -EINVAL;
  4162. }
  4163. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4164. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4165. switch (event) {
  4166. case SND_SOC_DAPM_PRE_PMU:
  4167. (*dmic_gpio_cnt)++;
  4168. if (*dmic_gpio_cnt == 1) {
  4169. ret = msm_cdc_pinctrl_select_active_state(
  4170. dmic_gpio);
  4171. if (ret < 0) {
  4172. pr_err("%s: gpio set cannot be activated %sd",
  4173. __func__, "dmic_gpio");
  4174. return ret;
  4175. }
  4176. }
  4177. break;
  4178. case SND_SOC_DAPM_POST_PMD:
  4179. (*dmic_gpio_cnt)--;
  4180. if (*dmic_gpio_cnt == 0) {
  4181. ret = msm_cdc_pinctrl_select_sleep_state(
  4182. dmic_gpio);
  4183. if (ret < 0) {
  4184. pr_err("%s: gpio set cannot be de-activated %sd",
  4185. __func__, "dmic_gpio");
  4186. return ret;
  4187. }
  4188. }
  4189. break;
  4190. default:
  4191. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4192. return -EINVAL;
  4193. }
  4194. return 0;
  4195. }
  4196. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4197. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4198. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4199. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4200. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4201. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4202. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4203. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4204. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4205. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4206. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4207. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4208. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4209. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4210. };
  4211. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4212. {
  4213. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4214. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4215. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4216. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4217. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4218. }
  4219. static struct snd_info_entry *msm_snd_info_create_subdir(struct module *mod,
  4220. const char *name,
  4221. struct snd_info_entry *parent)
  4222. {
  4223. struct snd_info_entry *entry;
  4224. entry = snd_info_create_module_entry(mod, name, parent);
  4225. if (!entry)
  4226. return NULL;
  4227. entry->mode = S_IFDIR | 0555;
  4228. if (snd_info_register(entry) < 0) {
  4229. snd_info_free_entry(entry);
  4230. return NULL;
  4231. }
  4232. return entry;
  4233. }
  4234. static void *def_wcd_mbhc_cal(void)
  4235. {
  4236. void *wcd_mbhc_cal;
  4237. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4238. u16 *btn_high;
  4239. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4240. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4241. if (!wcd_mbhc_cal)
  4242. return NULL;
  4243. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4244. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4245. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4246. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4247. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4248. btn_high[0] = 75;
  4249. btn_high[1] = 150;
  4250. btn_high[2] = 237;
  4251. btn_high[3] = 500;
  4252. btn_high[4] = 500;
  4253. btn_high[5] = 500;
  4254. btn_high[6] = 500;
  4255. btn_high[7] = 500;
  4256. return wcd_mbhc_cal;
  4257. }
  4258. /* Digital audio interface glue - connects codec <---> CPU */
  4259. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4260. /* FrontEnd DAI Links */
  4261. {/* hw:x,0 */
  4262. .name = MSM_DAILINK_NAME(Media1),
  4263. .stream_name = "MultiMedia1",
  4264. .dynamic = 1,
  4265. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4266. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4267. #endif /* CONFIG_AUDIO_QGKI */
  4268. .dpcm_playback = 1,
  4269. .dpcm_capture = 1,
  4270. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4271. SND_SOC_DPCM_TRIGGER_POST},
  4272. .ignore_suspend = 1,
  4273. /* this dainlink has playback support */
  4274. .ignore_pmdown_time = 1,
  4275. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  4276. SND_SOC_DAILINK_REG(multimedia1),
  4277. },
  4278. {/* hw:x,1 */
  4279. .name = MSM_DAILINK_NAME(Media2),
  4280. .stream_name = "MultiMedia2",
  4281. .dynamic = 1,
  4282. .dpcm_playback = 1,
  4283. .dpcm_capture = 1,
  4284. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4285. SND_SOC_DPCM_TRIGGER_POST},
  4286. .ignore_suspend = 1,
  4287. /* this dainlink has playback support */
  4288. .ignore_pmdown_time = 1,
  4289. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4290. SND_SOC_DAILINK_REG(multimedia2),
  4291. },
  4292. {/* hw:x,2 */
  4293. .name = "VoiceMMode1",
  4294. .stream_name = "VoiceMMode1",
  4295. .dynamic = 1,
  4296. .dpcm_playback = 1,
  4297. .dpcm_capture = 1,
  4298. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4299. SND_SOC_DPCM_TRIGGER_POST},
  4300. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4301. .ignore_suspend = 1,
  4302. .ignore_pmdown_time = 1,
  4303. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4304. SND_SOC_DAILINK_REG(voicemmode1),
  4305. },
  4306. {/* hw:x,3 */
  4307. .name = "MSM VoIP",
  4308. .stream_name = "VoIP",
  4309. .dynamic = 1,
  4310. .dpcm_playback = 1,
  4311. .dpcm_capture = 1,
  4312. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4313. SND_SOC_DPCM_TRIGGER_POST},
  4314. .ignore_suspend = 1,
  4315. /* this dainlink has playback support */
  4316. .ignore_pmdown_time = 1,
  4317. .id = MSM_FRONTEND_DAI_VOIP,
  4318. SND_SOC_DAILINK_REG(msmvoip),
  4319. },
  4320. {/* hw:x,4 */
  4321. .name = MSM_DAILINK_NAME(ULL),
  4322. .stream_name = "MultiMedia3",
  4323. .dynamic = 1,
  4324. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4325. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4326. #endif /* CONFIG_AUDIO_QGKI */
  4327. .dpcm_playback = 1,
  4328. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4329. SND_SOC_DPCM_TRIGGER_POST},
  4330. .ignore_suspend = 1,
  4331. /* this dainlink has playback support */
  4332. .ignore_pmdown_time = 1,
  4333. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4334. SND_SOC_DAILINK_REG(multimedia3),
  4335. },
  4336. {/* hw:x,5 */
  4337. .name = "MSM AFE-PCM RX",
  4338. .stream_name = "AFE-PROXY RX",
  4339. .dpcm_playback = 1,
  4340. .ignore_suspend = 1,
  4341. /* this dainlink has playback support */
  4342. .ignore_pmdown_time = 1,
  4343. SND_SOC_DAILINK_REG(afepcm_rx),
  4344. },
  4345. {/* hw:x,6 */
  4346. .name = "MSM AFE-PCM TX",
  4347. .stream_name = "AFE-PROXY TX",
  4348. .dpcm_capture = 1,
  4349. .ignore_suspend = 1,
  4350. SND_SOC_DAILINK_REG(afepcm_tx),
  4351. },
  4352. {/* hw:x,7 */
  4353. .name = MSM_DAILINK_NAME(Compress1),
  4354. .stream_name = "Compress1",
  4355. .dynamic = 1,
  4356. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4357. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4358. #endif /* CONFIG_AUDIO_QGKI */
  4359. .dpcm_playback = 1,
  4360. .dpcm_capture = 1,
  4361. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4362. SND_SOC_DPCM_TRIGGER_POST},
  4363. .ignore_suspend = 1,
  4364. .ignore_pmdown_time = 1,
  4365. /* this dainlink has playback support */
  4366. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4367. SND_SOC_DAILINK_REG(multimedia4),
  4368. },
  4369. /* Hostless PCM purpose */
  4370. {/* hw:x,8 */
  4371. .name = "AUXPCM Hostless",
  4372. .stream_name = "AUXPCM Hostless",
  4373. .dynamic = 1,
  4374. .dpcm_playback = 1,
  4375. .dpcm_capture = 1,
  4376. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4377. SND_SOC_DPCM_TRIGGER_POST},
  4378. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4379. .ignore_suspend = 1,
  4380. /* this dainlink has playback support */
  4381. .ignore_pmdown_time = 1,
  4382. SND_SOC_DAILINK_REG(auxpcm_hostless),
  4383. },
  4384. {/* hw:x,9 */
  4385. .name = MSM_DAILINK_NAME(LowLatency),
  4386. .stream_name = "MultiMedia5",
  4387. .dynamic = 1,
  4388. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4389. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4390. #endif /* CONFIG_AUDIO_QGKI */
  4391. .dpcm_playback = 1,
  4392. .dpcm_capture = 1,
  4393. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4394. SND_SOC_DPCM_TRIGGER_POST},
  4395. .ignore_suspend = 1,
  4396. /* this dainlink has playback support */
  4397. .ignore_pmdown_time = 1,
  4398. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4399. .ops = &msm_fe_qos_ops,
  4400. SND_SOC_DAILINK_REG(multimedia5),
  4401. },
  4402. {/* hw:x,10 */
  4403. .name = "Listen 1 Audio Service",
  4404. .stream_name = "Listen 1 Audio Service",
  4405. .dynamic = 1,
  4406. .dpcm_capture = 1,
  4407. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4408. SND_SOC_DPCM_TRIGGER_POST },
  4409. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4410. .ignore_suspend = 1,
  4411. .id = MSM_FRONTEND_DAI_LSM1,
  4412. SND_SOC_DAILINK_REG(listen1),
  4413. },
  4414. /* Multiple Tunnel instances */
  4415. {/* hw:x,11 */
  4416. .name = MSM_DAILINK_NAME(Compress2),
  4417. .stream_name = "Compress2",
  4418. .dynamic = 1,
  4419. .dpcm_playback = 1,
  4420. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4421. SND_SOC_DPCM_TRIGGER_POST},
  4422. .ignore_suspend = 1,
  4423. .ignore_pmdown_time = 1,
  4424. /* this dainlink has playback support */
  4425. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4426. SND_SOC_DAILINK_REG(multimedia7),
  4427. },
  4428. {/* hw:x,12 */
  4429. .name = MSM_DAILINK_NAME(MultiMedia10),
  4430. .stream_name = "MultiMedia10",
  4431. .dynamic = 1,
  4432. .dpcm_playback = 1,
  4433. .dpcm_capture = 1,
  4434. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4435. SND_SOC_DPCM_TRIGGER_POST},
  4436. .ignore_suspend = 1,
  4437. .ignore_pmdown_time = 1,
  4438. /* this dainlink has playback support */
  4439. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4440. SND_SOC_DAILINK_REG(multimedia10),
  4441. },
  4442. {/* hw:x,13 */
  4443. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4444. .stream_name = "MM_NOIRQ",
  4445. .dynamic = 1,
  4446. .dpcm_playback = 1,
  4447. .dpcm_capture = 1,
  4448. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4449. SND_SOC_DPCM_TRIGGER_POST},
  4450. .ignore_suspend = 1,
  4451. .ignore_pmdown_time = 1,
  4452. /* this dainlink has playback support */
  4453. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4454. .ops = &msm_fe_qos_ops,
  4455. SND_SOC_DAILINK_REG(multimedia8),
  4456. },
  4457. /* HDMI Hostless */
  4458. {/* hw:x,14 */
  4459. .name = "HDMI_RX_HOSTLESS",
  4460. .stream_name = "HDMI_RX_HOSTLESS",
  4461. .dynamic = 1,
  4462. .dpcm_playback = 1,
  4463. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4464. SND_SOC_DPCM_TRIGGER_POST},
  4465. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4466. .ignore_suspend = 1,
  4467. .ignore_pmdown_time = 1,
  4468. SND_SOC_DAILINK_REG(hdmi_rx_hostless),
  4469. },
  4470. {/* hw:x,15 */
  4471. .name = "VoiceMMode2",
  4472. .stream_name = "VoiceMMode2",
  4473. .dynamic = 1,
  4474. .dpcm_playback = 1,
  4475. .dpcm_capture = 1,
  4476. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4477. SND_SOC_DPCM_TRIGGER_POST},
  4478. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4479. .ignore_suspend = 1,
  4480. .ignore_pmdown_time = 1,
  4481. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4482. SND_SOC_DAILINK_REG(voicemmode2),
  4483. },
  4484. /* LSM FE */
  4485. {/* hw:x,16 */
  4486. .name = "Listen 2 Audio Service",
  4487. .stream_name = "Listen 2 Audio Service",
  4488. .dynamic = 1,
  4489. .dpcm_capture = 1,
  4490. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4491. SND_SOC_DPCM_TRIGGER_POST },
  4492. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4493. .ignore_suspend = 1,
  4494. .id = MSM_FRONTEND_DAI_LSM2,
  4495. SND_SOC_DAILINK_REG(listen2),
  4496. },
  4497. {/* hw:x,17 */
  4498. .name = "Listen 3 Audio Service",
  4499. .stream_name = "Listen 3 Audio Service",
  4500. .dynamic = 1,
  4501. .dpcm_capture = 1,
  4502. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4503. SND_SOC_DPCM_TRIGGER_POST },
  4504. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4505. .ignore_suspend = 1,
  4506. .id = MSM_FRONTEND_DAI_LSM3,
  4507. SND_SOC_DAILINK_REG(listen3),
  4508. },
  4509. {/* hw:x,18 */
  4510. .name = "Listen 4 Audio Service",
  4511. .stream_name = "Listen 4 Audio Service",
  4512. .dynamic = 1,
  4513. .dpcm_capture = 1,
  4514. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4515. SND_SOC_DPCM_TRIGGER_POST },
  4516. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4517. .ignore_suspend = 1,
  4518. .id = MSM_FRONTEND_DAI_LSM4,
  4519. SND_SOC_DAILINK_REG(listen4),
  4520. },
  4521. {/* hw:x,19 */
  4522. .name = "Listen 5 Audio Service",
  4523. .stream_name = "Listen 5 Audio Service",
  4524. .dynamic = 1,
  4525. .dpcm_capture = 1,
  4526. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4527. SND_SOC_DPCM_TRIGGER_POST },
  4528. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4529. .ignore_suspend = 1,
  4530. .id = MSM_FRONTEND_DAI_LSM5,
  4531. SND_SOC_DAILINK_REG(listen5),
  4532. },
  4533. {/* hw:x,20 */
  4534. .name = "Listen 6 Audio Service",
  4535. .stream_name = "Listen 6 Audio Service",
  4536. .dynamic = 1,
  4537. .dpcm_capture = 1,
  4538. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4539. SND_SOC_DPCM_TRIGGER_POST },
  4540. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4541. .ignore_suspend = 1,
  4542. .id = MSM_FRONTEND_DAI_LSM6,
  4543. SND_SOC_DAILINK_REG(listen6),
  4544. },
  4545. {/* hw:x,21 */
  4546. .name = "Listen 7 Audio Service",
  4547. .stream_name = "Listen 7 Audio Service",
  4548. .dynamic = 1,
  4549. .dpcm_capture = 1,
  4550. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4551. SND_SOC_DPCM_TRIGGER_POST },
  4552. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4553. .ignore_suspend = 1,
  4554. .id = MSM_FRONTEND_DAI_LSM7,
  4555. SND_SOC_DAILINK_REG(listen7),
  4556. },
  4557. {/* hw:x,22 */
  4558. .name = "Listen 8 Audio Service",
  4559. .stream_name = "Listen 8 Audio Service",
  4560. .dynamic = 1,
  4561. .dpcm_capture = 1,
  4562. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4563. SND_SOC_DPCM_TRIGGER_POST },
  4564. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4565. .ignore_suspend = 1,
  4566. .id = MSM_FRONTEND_DAI_LSM8,
  4567. SND_SOC_DAILINK_REG(listen8),
  4568. },
  4569. {/* hw:x,23 */
  4570. .name = MSM_DAILINK_NAME(Media9),
  4571. .stream_name = "MultiMedia9",
  4572. .dynamic = 1,
  4573. .dpcm_playback = 1,
  4574. .dpcm_capture = 1,
  4575. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4576. SND_SOC_DPCM_TRIGGER_POST},
  4577. .ignore_suspend = 1,
  4578. /* this dainlink has playback support */
  4579. .ignore_pmdown_time = 1,
  4580. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4581. SND_SOC_DAILINK_REG(multimedia9),
  4582. },
  4583. {/* hw:x,24 */
  4584. .name = MSM_DAILINK_NAME(Compress4),
  4585. .stream_name = "Compress4",
  4586. .dynamic = 1,
  4587. .dpcm_playback = 1,
  4588. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4589. SND_SOC_DPCM_TRIGGER_POST},
  4590. .ignore_suspend = 1,
  4591. .ignore_pmdown_time = 1,
  4592. /* this dainlink has playback support */
  4593. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4594. SND_SOC_DAILINK_REG(multimedia11),
  4595. },
  4596. {/* hw:x,25 */
  4597. .name = MSM_DAILINK_NAME(Compress5),
  4598. .stream_name = "Compress5",
  4599. .dynamic = 1,
  4600. .dpcm_playback = 1,
  4601. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4602. SND_SOC_DPCM_TRIGGER_POST},
  4603. .ignore_suspend = 1,
  4604. .ignore_pmdown_time = 1,
  4605. /* this dainlink has playback support */
  4606. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4607. SND_SOC_DAILINK_REG(multimedia12),
  4608. },
  4609. {/* hw:x,26 */
  4610. .name = MSM_DAILINK_NAME(Compress6),
  4611. .stream_name = "Compress6",
  4612. .dynamic = 1,
  4613. .dpcm_playback = 1,
  4614. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4615. SND_SOC_DPCM_TRIGGER_POST},
  4616. .ignore_suspend = 1,
  4617. .ignore_pmdown_time = 1,
  4618. /* this dainlink has playback support */
  4619. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4620. SND_SOC_DAILINK_REG(multimedia13),
  4621. },
  4622. {/* hw:x,27 */
  4623. .name = MSM_DAILINK_NAME(Compress7),
  4624. .stream_name = "Compress7",
  4625. .dynamic = 1,
  4626. .dpcm_playback = 1,
  4627. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4628. SND_SOC_DPCM_TRIGGER_POST},
  4629. .ignore_suspend = 1,
  4630. .ignore_pmdown_time = 1,
  4631. /* this dainlink has playback support */
  4632. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4633. SND_SOC_DAILINK_REG(multimedia14),
  4634. },
  4635. {/* hw:x,28 */
  4636. .name = MSM_DAILINK_NAME(Compress8),
  4637. .stream_name = "Compress8",
  4638. .dynamic = 1,
  4639. .dpcm_playback = 1,
  4640. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4641. SND_SOC_DPCM_TRIGGER_POST},
  4642. .ignore_suspend = 1,
  4643. .ignore_pmdown_time = 1,
  4644. /* this dainlink has playback support */
  4645. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4646. SND_SOC_DAILINK_REG(multimedia15),
  4647. },
  4648. {/* hw:x,29 */
  4649. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4650. .stream_name = "MM_NOIRQ_2",
  4651. .dynamic = 1,
  4652. .dpcm_playback = 1,
  4653. .dpcm_capture = 1,
  4654. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4655. SND_SOC_DPCM_TRIGGER_POST},
  4656. .ignore_suspend = 1,
  4657. .ignore_pmdown_time = 1,
  4658. /* this dainlink has playback support */
  4659. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4660. .ops = &msm_fe_qos_ops,
  4661. SND_SOC_DAILINK_REG(multimedia16),
  4662. },
  4663. {/* hw:x,30 */
  4664. .name = "CDC_DMA Hostless",
  4665. .stream_name = "CDC_DMA Hostless",
  4666. .dynamic = 1,
  4667. .dpcm_playback = 1,
  4668. .dpcm_capture = 1,
  4669. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4670. SND_SOC_DPCM_TRIGGER_POST},
  4671. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4672. .ignore_suspend = 1,
  4673. /* this dailink has playback support */
  4674. .ignore_pmdown_time = 1,
  4675. SND_SOC_DAILINK_REG(cdcdma_hostless),
  4676. },
  4677. {/* hw:x,31 */
  4678. .name = "TX3_CDC_DMA Hostless",
  4679. .stream_name = "TX3_CDC_DMA Hostless",
  4680. .dynamic = 1,
  4681. .dpcm_capture = 1,
  4682. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4683. SND_SOC_DPCM_TRIGGER_POST},
  4684. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4685. .ignore_suspend = 1,
  4686. SND_SOC_DAILINK_REG(tx3_cdcdma_hostless),
  4687. },
  4688. {/* hw:x,32 */
  4689. .name = "Tertiary MI2S TX_Hostless",
  4690. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4691. .dynamic = 1,
  4692. .dpcm_capture = 1,
  4693. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4694. SND_SOC_DPCM_TRIGGER_POST},
  4695. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4696. .ignore_suspend = 1,
  4697. .ignore_pmdown_time = 1,
  4698. SND_SOC_DAILINK_REG(tert_mi2s_tx_hostless),
  4699. },
  4700. };
  4701. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4702. {/* hw:x,33 */
  4703. .name = MSM_DAILINK_NAME(ASM Loopback),
  4704. .stream_name = "MultiMedia6",
  4705. .dynamic = 1,
  4706. .dpcm_playback = 1,
  4707. .dpcm_capture = 1,
  4708. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4709. SND_SOC_DPCM_TRIGGER_POST},
  4710. .ignore_suspend = 1,
  4711. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4712. .ignore_pmdown_time = 1,
  4713. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4714. SND_SOC_DAILINK_REG(multimedia6),
  4715. },
  4716. {/* hw:x,34 */
  4717. .name = "USB Audio Hostless",
  4718. .stream_name = "USB Audio Hostless",
  4719. .dynamic = 1,
  4720. .dpcm_playback = 1,
  4721. .dpcm_capture = 1,
  4722. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4723. SND_SOC_DPCM_TRIGGER_POST},
  4724. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4725. .ignore_suspend = 1,
  4726. .ignore_pmdown_time = 1,
  4727. SND_SOC_DAILINK_REG(usbaudio_hostless),
  4728. },
  4729. {/* hw:x,35 */
  4730. .name = "SLIMBUS_7 Hostless",
  4731. .stream_name = "SLIMBUS_7 Hostless",
  4732. .dynamic = 1,
  4733. .dpcm_capture = 1,
  4734. .dpcm_playback = 1,
  4735. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4736. SND_SOC_DPCM_TRIGGER_POST},
  4737. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4738. .ignore_suspend = 1,
  4739. .ignore_pmdown_time = 1,
  4740. SND_SOC_DAILINK_REG(slimbus7_hostless),
  4741. },
  4742. {/* hw:x,36 */
  4743. .name = "Compress Capture",
  4744. .stream_name = "Compress9",
  4745. .dynamic = 1,
  4746. .dpcm_capture = 1,
  4747. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4748. SND_SOC_DPCM_TRIGGER_POST},
  4749. .ignore_suspend = 1,
  4750. .ignore_pmdown_time = 1,
  4751. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4752. SND_SOC_DAILINK_REG(multimedia17),
  4753. },
  4754. {/* hw:x,37 */
  4755. .name = "SLIMBUS_8 Hostless",
  4756. .stream_name = "SLIMBUS_8 Hostless",
  4757. .dynamic = 1,
  4758. .dpcm_capture = 1,
  4759. .dpcm_playback = 1,
  4760. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4761. SND_SOC_DPCM_TRIGGER_POST},
  4762. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4763. .ignore_suspend = 1,
  4764. .ignore_pmdown_time = 1,
  4765. SND_SOC_DAILINK_REG(slimbus8_hostless),
  4766. },
  4767. {/* hw:x,38 */
  4768. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  4769. .stream_name = "TX CDC DMA5 Capture",
  4770. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  4771. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4772. .ignore_suspend = 1,
  4773. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4774. .ops = &msm_cdc_dma_be_ops,
  4775. SND_SOC_DAILINK_REG(tx_cdcdma5_tx),
  4776. },
  4777. {/* hw:x,39 */
  4778. .name = MSM_DAILINK_NAME(Media31),
  4779. .stream_name = "MultiMedia31",
  4780. .dynamic = 1,
  4781. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4782. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4783. #endif /* CONFIG_AUDIO_QGKI */
  4784. .dpcm_playback = 1,
  4785. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4786. SND_SOC_DPCM_TRIGGER_POST},
  4787. .ignore_suspend = 1,
  4788. /* this dainlink has playback support */
  4789. .ignore_pmdown_time = 1,
  4790. .id = MSM_FRONTEND_DAI_MULTIMEDIA31,
  4791. SND_SOC_DAILINK_REG(multimedia31),
  4792. },
  4793. {/* hw:x,40 */
  4794. .name = MSM_DAILINK_NAME(Media32),
  4795. .stream_name = "MultiMedia32",
  4796. .dynamic = 1,
  4797. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4798. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4799. #endif /* CONFIG_AUDIO_QGKI */
  4800. .dpcm_playback = 1,
  4801. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4802. SND_SOC_DPCM_TRIGGER_POST},
  4803. .ignore_suspend = 1,
  4804. /* this dainlink has playback support */
  4805. .ignore_pmdown_time = 1,
  4806. .id = MSM_FRONTEND_DAI_MULTIMEDIA32,
  4807. SND_SOC_DAILINK_REG(multimedia32),
  4808. },
  4809. {/* hw:x,41 */
  4810. .name = "MSM AFE-PCM TX1",
  4811. .stream_name = "AFE-PROXY TX1",
  4812. .dpcm_capture = 1,
  4813. .ignore_suspend = 1,
  4814. SND_SOC_DAILINK_REG(afepcm_tx1),
  4815. },
  4816. };
  4817. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4818. /* Backend AFE DAI Links */
  4819. {
  4820. .name = LPASS_BE_AFE_PCM_RX,
  4821. .stream_name = "AFE Playback",
  4822. .no_pcm = 1,
  4823. .dpcm_playback = 1,
  4824. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4825. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4826. /* this dainlink has playback support */
  4827. .ignore_pmdown_time = 1,
  4828. .ignore_suspend = 1,
  4829. SND_SOC_DAILINK_REG(afe_pcm_rx),
  4830. },
  4831. {
  4832. .name = LPASS_BE_AFE_PCM_TX,
  4833. .stream_name = "AFE Capture",
  4834. .no_pcm = 1,
  4835. .dpcm_capture = 1,
  4836. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4837. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4838. .ignore_suspend = 1,
  4839. SND_SOC_DAILINK_REG(afe_pcm_tx),
  4840. },
  4841. /* Incall Record Uplink BACK END DAI Link */
  4842. {
  4843. .name = LPASS_BE_INCALL_RECORD_TX,
  4844. .stream_name = "Voice Uplink Capture",
  4845. .no_pcm = 1,
  4846. .dpcm_capture = 1,
  4847. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4849. .ignore_suspend = 1,
  4850. SND_SOC_DAILINK_REG(incall_record_tx),
  4851. },
  4852. /* Incall Record Downlink BACK END DAI Link */
  4853. {
  4854. .name = LPASS_BE_INCALL_RECORD_RX,
  4855. .stream_name = "Voice Downlink Capture",
  4856. .no_pcm = 1,
  4857. .dpcm_capture = 1,
  4858. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4859. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4860. .ignore_suspend = 1,
  4861. SND_SOC_DAILINK_REG(incall_record_rx),
  4862. },
  4863. /* Incall Music BACK END DAI Link */
  4864. {
  4865. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4866. .stream_name = "Voice Farend Playback",
  4867. .no_pcm = 1,
  4868. .dpcm_playback = 1,
  4869. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4870. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4871. .ignore_suspend = 1,
  4872. .ignore_pmdown_time = 1,
  4873. SND_SOC_DAILINK_REG(voice_playback_tx),
  4874. },
  4875. /* Incall Music 2 BACK END DAI Link */
  4876. {
  4877. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4878. .stream_name = "Voice2 Farend Playback",
  4879. .no_pcm = 1,
  4880. .dpcm_playback = 1,
  4881. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4882. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4883. .ignore_suspend = 1,
  4884. .ignore_pmdown_time = 1,
  4885. SND_SOC_DAILINK_REG(voice2_playback_tx),
  4886. },
  4887. /* Proxy Tx BACK END DAI Link */
  4888. {
  4889. .name = LPASS_BE_PROXY_TX,
  4890. .stream_name = "Proxy Capture",
  4891. .no_pcm = 1,
  4892. .dpcm_capture = 1,
  4893. .id = MSM_BACKEND_DAI_PROXY_TX,
  4894. .ignore_suspend = 1,
  4895. SND_SOC_DAILINK_REG(proxy_tx),
  4896. },
  4897. /* Proxy Rx BACK END DAI Link */
  4898. {
  4899. .name = LPASS_BE_PROXY_RX,
  4900. .stream_name = "Proxy Playback",
  4901. .no_pcm = 1,
  4902. .dpcm_playback = 1,
  4903. .id = MSM_BACKEND_DAI_PROXY_RX,
  4904. .ignore_pmdown_time = 1,
  4905. .ignore_suspend = 1,
  4906. SND_SOC_DAILINK_REG(proxy_rx),
  4907. },
  4908. {
  4909. .name = LPASS_BE_USB_AUDIO_RX,
  4910. .stream_name = "USB Audio Playback",
  4911. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  4912. .dynamic_be = 1,
  4913. #endif /* CONFIG_AUDIO_QGKI */
  4914. .no_pcm = 1,
  4915. .dpcm_playback = 1,
  4916. .id = MSM_BACKEND_DAI_USB_RX,
  4917. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4918. .ignore_pmdown_time = 1,
  4919. .ignore_suspend = 1,
  4920. SND_SOC_DAILINK_REG(usb_audio_rx),
  4921. },
  4922. {
  4923. .name = LPASS_BE_USB_AUDIO_TX,
  4924. .stream_name = "USB Audio Capture",
  4925. .no_pcm = 1,
  4926. .dpcm_capture = 1,
  4927. .id = MSM_BACKEND_DAI_USB_TX,
  4928. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4929. .ignore_suspend = 1,
  4930. SND_SOC_DAILINK_REG(usb_audio_tx),
  4931. },
  4932. {
  4933. .name = LPASS_BE_PRI_TDM_RX_0,
  4934. .stream_name = "Primary TDM0 Playback",
  4935. .no_pcm = 1,
  4936. .dpcm_playback = 1,
  4937. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4939. .ops = &holi_tdm_be_ops,
  4940. .ignore_suspend = 1,
  4941. .ignore_pmdown_time = 1,
  4942. SND_SOC_DAILINK_REG(pri_tdm_rx_0),
  4943. },
  4944. {
  4945. .name = LPASS_BE_PRI_TDM_TX_0,
  4946. .stream_name = "Primary TDM0 Capture",
  4947. .no_pcm = 1,
  4948. .dpcm_capture = 1,
  4949. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4950. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4951. .ops = &holi_tdm_be_ops,
  4952. .ignore_suspend = 1,
  4953. SND_SOC_DAILINK_REG(pri_tdm_tx_0),
  4954. },
  4955. {
  4956. .name = LPASS_BE_SEC_TDM_RX_0,
  4957. .stream_name = "Secondary TDM0 Playback",
  4958. .no_pcm = 1,
  4959. .dpcm_playback = 1,
  4960. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4961. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4962. .ops = &holi_tdm_be_ops,
  4963. .ignore_suspend = 1,
  4964. .ignore_pmdown_time = 1,
  4965. SND_SOC_DAILINK_REG(sec_tdm_rx_0),
  4966. },
  4967. {
  4968. .name = LPASS_BE_SEC_TDM_TX_0,
  4969. .stream_name = "Secondary TDM0 Capture",
  4970. .no_pcm = 1,
  4971. .dpcm_capture = 1,
  4972. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4973. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4974. .ops = &holi_tdm_be_ops,
  4975. .ignore_suspend = 1,
  4976. SND_SOC_DAILINK_REG(sec_tdm_tx_0),
  4977. },
  4978. {
  4979. .name = LPASS_BE_TERT_TDM_RX_0,
  4980. .stream_name = "Tertiary TDM0 Playback",
  4981. .no_pcm = 1,
  4982. .dpcm_playback = 1,
  4983. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4984. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4985. .ops = &holi_tdm_be_ops,
  4986. .ignore_suspend = 1,
  4987. .ignore_pmdown_time = 1,
  4988. SND_SOC_DAILINK_REG(tert_tdm_rx_0),
  4989. },
  4990. {
  4991. .name = LPASS_BE_TERT_TDM_TX_0,
  4992. .stream_name = "Tertiary TDM0 Capture",
  4993. .no_pcm = 1,
  4994. .dpcm_capture = 1,
  4995. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4996. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4997. .ops = &holi_tdm_be_ops,
  4998. .ignore_suspend = 1,
  4999. SND_SOC_DAILINK_REG(tert_tdm_tx_0),
  5000. },
  5001. {
  5002. .name = LPASS_BE_QUAT_TDM_RX_0,
  5003. .stream_name = "Quaternary TDM0 Playback",
  5004. .no_pcm = 1,
  5005. .dpcm_playback = 1,
  5006. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5007. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5008. .ops = &holi_tdm_be_ops,
  5009. .ignore_suspend = 1,
  5010. .ignore_pmdown_time = 1,
  5011. SND_SOC_DAILINK_REG(quat_tdm_rx_0),
  5012. },
  5013. {
  5014. .name = LPASS_BE_QUAT_TDM_TX_0,
  5015. .stream_name = "Quaternary TDM0 Capture",
  5016. .no_pcm = 1,
  5017. .dpcm_capture = 1,
  5018. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5019. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5020. .ops = &holi_tdm_be_ops,
  5021. .ignore_suspend = 1,
  5022. SND_SOC_DAILINK_REG(quat_tdm_tx_0),
  5023. },
  5024. };
  5025. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5026. {
  5027. .name = LPASS_BE_SLIMBUS_7_RX,
  5028. .stream_name = "Slimbus7 Playback",
  5029. .no_pcm = 1,
  5030. .dpcm_playback = 1,
  5031. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5032. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5033. .init = &msm_wcn_init_lito,
  5034. .ops = &msm_wcn_ops_lito,
  5035. /* dai link has playback support */
  5036. .ignore_pmdown_time = 1,
  5037. .ignore_suspend = 1,
  5038. SND_SOC_DAILINK_REG(slimbus_7_rx),
  5039. },
  5040. {
  5041. .name = LPASS_BE_SLIMBUS_7_TX,
  5042. .stream_name = "Slimbus7 Capture",
  5043. .no_pcm = 1,
  5044. .dpcm_capture = 1,
  5045. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5046. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5047. .ops = &msm_wcn_ops_lito,
  5048. .ignore_suspend = 1,
  5049. SND_SOC_DAILINK_REG(slimbus_7_tx),
  5050. },
  5051. {
  5052. .name = LPASS_BE_SLIMBUS_8_TX,
  5053. .stream_name = "Slimbus8 Capture",
  5054. .no_pcm = 1,
  5055. .dpcm_capture = 1,
  5056. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5057. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5058. .ops = &msm_wcn_ops_lito,
  5059. .ignore_suspend = 1,
  5060. SND_SOC_DAILINK_REG(slimbus_8_tx),
  5061. },
  5062. };
  5063. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5064. {
  5065. .name = LPASS_BE_PRI_MI2S_RX,
  5066. .stream_name = "Primary MI2S Playback",
  5067. .no_pcm = 1,
  5068. .dpcm_playback = 1,
  5069. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5070. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5071. .ops = &msm_mi2s_be_ops,
  5072. .ignore_suspend = 1,
  5073. .ignore_pmdown_time = 1,
  5074. SND_SOC_DAILINK_REG(pri_mi2s_rx),
  5075. },
  5076. {
  5077. .name = LPASS_BE_PRI_MI2S_TX,
  5078. .stream_name = "Primary MI2S Capture",
  5079. .no_pcm = 1,
  5080. .dpcm_capture = 1,
  5081. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5082. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5083. .ops = &msm_mi2s_be_ops,
  5084. .ignore_suspend = 1,
  5085. SND_SOC_DAILINK_REG(pri_mi2s_tx),
  5086. },
  5087. {
  5088. .name = LPASS_BE_SEC_MI2S_RX,
  5089. .stream_name = "Secondary MI2S Playback",
  5090. .no_pcm = 1,
  5091. .dpcm_playback = 1,
  5092. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5093. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5094. .ops = &msm_mi2s_be_ops,
  5095. .ignore_suspend = 1,
  5096. .ignore_pmdown_time = 1,
  5097. SND_SOC_DAILINK_REG(sec_mi2s_rx),
  5098. },
  5099. {
  5100. .name = LPASS_BE_SEC_MI2S_TX,
  5101. .stream_name = "Secondary MI2S Capture",
  5102. .no_pcm = 1,
  5103. .dpcm_capture = 1,
  5104. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5105. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5106. .ops = &msm_mi2s_be_ops,
  5107. .ignore_suspend = 1,
  5108. SND_SOC_DAILINK_REG(sec_mi2s_tx),
  5109. },
  5110. {
  5111. .name = LPASS_BE_TERT_MI2S_RX,
  5112. .stream_name = "Tertiary MI2S Playback",
  5113. .no_pcm = 1,
  5114. .dpcm_playback = 1,
  5115. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5116. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5117. .ops = &msm_mi2s_be_ops,
  5118. .ignore_suspend = 1,
  5119. .ignore_pmdown_time = 1,
  5120. SND_SOC_DAILINK_REG(tert_mi2s_rx),
  5121. },
  5122. {
  5123. .name = LPASS_BE_TERT_MI2S_TX,
  5124. .stream_name = "Tertiary MI2S Capture",
  5125. .no_pcm = 1,
  5126. .dpcm_capture = 1,
  5127. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5128. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5129. .ops = &msm_mi2s_be_ops,
  5130. .ignore_suspend = 1,
  5131. SND_SOC_DAILINK_REG(tert_mi2s_tx),
  5132. },
  5133. {
  5134. .name = LPASS_BE_QUAT_MI2S_RX,
  5135. .stream_name = "Quaternary MI2S Playback",
  5136. .no_pcm = 1,
  5137. .dpcm_playback = 1,
  5138. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5139. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5140. .ops = &msm_mi2s_be_ops,
  5141. .ignore_suspend = 1,
  5142. .ignore_pmdown_time = 1,
  5143. SND_SOC_DAILINK_REG(quat_mi2s_rx),
  5144. },
  5145. {
  5146. .name = LPASS_BE_QUAT_MI2S_TX,
  5147. .stream_name = "Quaternary MI2S Capture",
  5148. .no_pcm = 1,
  5149. .dpcm_capture = 1,
  5150. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5151. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5152. .ops = &msm_mi2s_be_ops,
  5153. .ignore_suspend = 1,
  5154. SND_SOC_DAILINK_REG(quat_mi2s_tx),
  5155. },
  5156. };
  5157. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5158. /* Primary AUX PCM Backend DAI Links */
  5159. {
  5160. .name = LPASS_BE_AUXPCM_RX,
  5161. .stream_name = "AUX PCM Playback",
  5162. .no_pcm = 1,
  5163. .dpcm_playback = 1,
  5164. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5165. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5166. .ops = &holi_aux_be_ops,
  5167. .ignore_pmdown_time = 1,
  5168. .ignore_suspend = 1,
  5169. SND_SOC_DAILINK_REG(auxpcm_rx),
  5170. },
  5171. {
  5172. .name = LPASS_BE_AUXPCM_TX,
  5173. .stream_name = "AUX PCM Capture",
  5174. .no_pcm = 1,
  5175. .dpcm_capture = 1,
  5176. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5177. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5178. .ops = &holi_aux_be_ops,
  5179. .ignore_suspend = 1,
  5180. SND_SOC_DAILINK_REG(auxpcm_tx),
  5181. },
  5182. /* Secondary AUX PCM Backend DAI Links */
  5183. {
  5184. .name = LPASS_BE_SEC_AUXPCM_RX,
  5185. .stream_name = "Sec AUX PCM Playback",
  5186. .no_pcm = 1,
  5187. .dpcm_playback = 1,
  5188. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5189. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5190. .ops = &holi_aux_be_ops,
  5191. .ignore_pmdown_time = 1,
  5192. .ignore_suspend = 1,
  5193. SND_SOC_DAILINK_REG(sec_auxpcm_rx),
  5194. },
  5195. {
  5196. .name = LPASS_BE_SEC_AUXPCM_TX,
  5197. .stream_name = "Sec AUX PCM Capture",
  5198. .no_pcm = 1,
  5199. .dpcm_capture = 1,
  5200. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5201. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5202. .ops = &holi_aux_be_ops,
  5203. .ignore_suspend = 1,
  5204. SND_SOC_DAILINK_REG(sec_auxpcm_tx),
  5205. },
  5206. /* Tertiary AUX PCM Backend DAI Links */
  5207. {
  5208. .name = LPASS_BE_TERT_AUXPCM_RX,
  5209. .stream_name = "Tert AUX PCM Playback",
  5210. .no_pcm = 1,
  5211. .dpcm_playback = 1,
  5212. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5213. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5214. .ops = &holi_aux_be_ops,
  5215. .ignore_suspend = 1,
  5216. SND_SOC_DAILINK_REG(tert_auxpcm_rx),
  5217. },
  5218. {
  5219. .name = LPASS_BE_TERT_AUXPCM_TX,
  5220. .stream_name = "Tert AUX PCM Capture",
  5221. .no_pcm = 1,
  5222. .dpcm_capture = 1,
  5223. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5224. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5225. .ops = &holi_aux_be_ops,
  5226. .ignore_suspend = 1,
  5227. SND_SOC_DAILINK_REG(tert_auxpcm_tx),
  5228. },
  5229. /* Quaternary AUX PCM Backend DAI Links */
  5230. {
  5231. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5232. .stream_name = "Quat AUX PCM Playback",
  5233. .no_pcm = 1,
  5234. .dpcm_playback = 1,
  5235. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5236. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5237. .ops = &holi_aux_be_ops,
  5238. .ignore_suspend = 1,
  5239. SND_SOC_DAILINK_REG(quat_auxpcm_rx),
  5240. },
  5241. {
  5242. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5243. .stream_name = "Quat AUX PCM Capture",
  5244. .no_pcm = 1,
  5245. .dpcm_capture = 1,
  5246. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5247. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5248. .ops = &holi_aux_be_ops,
  5249. .ignore_suspend = 1,
  5250. SND_SOC_DAILINK_REG(quat_auxpcm_tx),
  5251. },
  5252. };
  5253. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5254. /* RX CDC DMA Backend DAI Links */
  5255. {
  5256. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5257. .stream_name = "RX CDC DMA0 Playback",
  5258. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5259. .dynamic_be = 1,
  5260. #endif /* CONFIG_AUDIO_QGKI */
  5261. .no_pcm = 1,
  5262. .dpcm_playback = 1,
  5263. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5264. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5265. .ignore_pmdown_time = 1,
  5266. .ignore_suspend = 1,
  5267. .ops = &msm_cdc_dma_be_ops,
  5268. SND_SOC_DAILINK_REG(rx_dma_rx0),
  5269. .init = &msm_aux_codec_init,
  5270. },
  5271. {
  5272. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5273. .stream_name = "RX CDC DMA1 Playback",
  5274. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5275. .dynamic_be = 1,
  5276. #endif /* CONFIG_AUDIO_QGKI */
  5277. .no_pcm = 1,
  5278. .dpcm_playback = 1,
  5279. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5280. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5281. .ignore_pmdown_time = 1,
  5282. .ignore_suspend = 1,
  5283. .ops = &msm_cdc_dma_be_ops,
  5284. SND_SOC_DAILINK_REG(rx_dma_rx1),
  5285. },
  5286. {
  5287. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5288. .stream_name = "RX CDC DMA2 Playback",
  5289. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5290. .dynamic_be = 1,
  5291. #endif /* CONFIG_AUDIO_QGKI */
  5292. .no_pcm = 1,
  5293. .dpcm_playback = 1,
  5294. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5295. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5296. .ignore_pmdown_time = 1,
  5297. .ignore_suspend = 1,
  5298. .ops = &msm_cdc_dma_be_ops,
  5299. SND_SOC_DAILINK_REG(rx_dma_rx2),
  5300. },
  5301. {
  5302. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5303. .stream_name = "RX CDC DMA3 Playback",
  5304. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5305. .dynamic_be = 1,
  5306. #endif /* CONFIG_AUDIO_QGKI */
  5307. .no_pcm = 1,
  5308. .dpcm_playback = 1,
  5309. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5310. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5311. .ignore_pmdown_time = 1,
  5312. .ignore_suspend = 1,
  5313. .ops = &msm_cdc_dma_be_ops,
  5314. SND_SOC_DAILINK_REG(rx_dma_rx3),
  5315. },
  5316. /* TX CDC DMA Backend DAI Links */
  5317. {
  5318. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5319. .stream_name = "TX CDC DMA3 Capture",
  5320. .no_pcm = 1,
  5321. .dpcm_capture = 1,
  5322. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5323. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5324. .ignore_suspend = 1,
  5325. .ops = &msm_cdc_dma_be_ops,
  5326. SND_SOC_DAILINK_REG(tx_dma_tx3),
  5327. },
  5328. {
  5329. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5330. .stream_name = "TX CDC DMA4 Capture",
  5331. .no_pcm = 1,
  5332. .dpcm_capture = 1,
  5333. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5334. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5335. .ignore_suspend = 1,
  5336. .ops = &msm_cdc_dma_be_ops,
  5337. SND_SOC_DAILINK_REG(tx_dma_tx4),
  5338. },
  5339. };
  5340. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5341. {
  5342. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5343. .stream_name = "VA CDC DMA0 Capture",
  5344. .no_pcm = 1,
  5345. .dpcm_capture = 1,
  5346. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5347. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5348. .ignore_suspend = 1,
  5349. .ops = &msm_cdc_dma_be_ops,
  5350. SND_SOC_DAILINK_REG(va_dma_tx0),
  5351. .init = &msm_int_audrx_init,
  5352. },
  5353. {
  5354. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5355. .stream_name = "VA CDC DMA1 Capture",
  5356. .no_pcm = 1,
  5357. .dpcm_capture = 1,
  5358. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5359. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5360. .ignore_suspend = 1,
  5361. .ops = &msm_cdc_dma_be_ops,
  5362. SND_SOC_DAILINK_REG(va_dma_tx1),
  5363. },
  5364. {
  5365. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5366. .stream_name = "VA CDC DMA2 Capture",
  5367. .no_pcm = 1,
  5368. .dpcm_capture = 1,
  5369. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5370. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5371. .ignore_suspend = 1,
  5372. .ops = &msm_cdc_dma_be_ops,
  5373. SND_SOC_DAILINK_REG(va_dma_tx2),
  5374. },
  5375. };
  5376. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5377. {
  5378. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5379. .stream_name = "AFE Loopback Capture",
  5380. .no_pcm = 1,
  5381. .dpcm_capture = 1,
  5382. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5383. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5384. .ignore_pmdown_time = 1,
  5385. .ignore_suspend = 1,
  5386. SND_SOC_DAILINK_REG(afe_loopback_tx),
  5387. },
  5388. };
  5389. static struct snd_soc_dai_link msm_holi_dai_links[
  5390. ARRAY_SIZE(msm_common_dai_links) +
  5391. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5392. ARRAY_SIZE(msm_common_be_dai_links) +
  5393. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5394. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5395. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5396. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5397. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5398. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  5399. static int msm_populate_dai_link_component_of_node(
  5400. struct snd_soc_card *card)
  5401. {
  5402. int i, j, index, ret = 0;
  5403. struct device *cdev = card->dev;
  5404. struct snd_soc_dai_link *dai_link = card->dai_link;
  5405. struct device_node *np = NULL;
  5406. int codecs_enabled = 0;
  5407. struct snd_soc_dai_link_component *codecs_comp = NULL;
  5408. if (!cdev) {
  5409. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5410. return -ENODEV;
  5411. }
  5412. for (i = 0; i < card->num_links; i++) {
  5413. if (dai_link[i].platforms->of_node && dai_link[i].cpus->of_node)
  5414. continue;
  5415. /* populate platform_of_node for snd card dai links */
  5416. if (dai_link[i].platforms->name &&
  5417. !dai_link[i].platforms->of_node) {
  5418. index = of_property_match_string(cdev->of_node,
  5419. "asoc-platform-names",
  5420. dai_link[i].platforms->name);
  5421. if (index < 0) {
  5422. dev_err(cdev, "%s: No match found for platform name: %s\n",
  5423. __func__, dai_link[i].platforms->name);
  5424. ret = index;
  5425. goto err;
  5426. }
  5427. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5428. index);
  5429. if (!np) {
  5430. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  5431. __func__, dai_link[i].platforms->name,
  5432. index);
  5433. ret = -ENODEV;
  5434. goto err;
  5435. }
  5436. dai_link[i].platforms->of_node = np;
  5437. dai_link[i].platforms->name = NULL;
  5438. }
  5439. /* populate cpu_of_node for snd card dai links */
  5440. if (dai_link[i].cpus->dai_name && !dai_link[i].cpus->of_node) {
  5441. index = of_property_match_string(cdev->of_node,
  5442. "asoc-cpu-names",
  5443. dai_link[i].cpus->dai_name);
  5444. if (index >= 0) {
  5445. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5446. index);
  5447. if (!np) {
  5448. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  5449. __func__,
  5450. dai_link[i].cpus->dai_name);
  5451. ret = -ENODEV;
  5452. goto err;
  5453. }
  5454. dai_link[i].cpus->of_node = np;
  5455. dai_link[i].cpus->dai_name = NULL;
  5456. }
  5457. }
  5458. /* populate codec_of_node for snd card dai links */
  5459. if (dai_link[i].num_codecs > 0) {
  5460. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5461. if (dai_link[i].codecs[j].of_node ||
  5462. !dai_link[i].codecs[j].name)
  5463. continue;
  5464. index = of_property_match_string(cdev->of_node,
  5465. "asoc-codec-names",
  5466. dai_link[i].codecs[j].name);
  5467. if (index < 0)
  5468. continue;
  5469. np = of_parse_phandle(cdev->of_node,
  5470. "asoc-codec",
  5471. index);
  5472. if (!np) {
  5473. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  5474. __func__,
  5475. dai_link[i].codecs[j].name);
  5476. ret = -ENODEV;
  5477. goto err;
  5478. }
  5479. dai_link[i].codecs[j].of_node = np;
  5480. dai_link[i].codecs[j].name = NULL;
  5481. }
  5482. }
  5483. }
  5484. /* In multi-codec scenario, check if codecs are enabled for this platform */
  5485. for (i = 0; i < card->num_links; i++) {
  5486. codecs_enabled = 0;
  5487. if (dai_link[i].num_codecs > 1) {
  5488. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5489. if (!dai_link[i].codecs[j].of_node)
  5490. continue;
  5491. np = dai_link[i].codecs[j].of_node;
  5492. if (!of_device_is_available(np)) {
  5493. dev_err(cdev, "%s: codec is disabled: %s\n",
  5494. __func__,
  5495. np->full_name);
  5496. dai_link[i].codecs[j].of_node = NULL;
  5497. continue;
  5498. }
  5499. codecs_enabled++;
  5500. }
  5501. if (codecs_enabled > 0 &&
  5502. codecs_enabled < dai_link[i].num_codecs) {
  5503. codecs_comp = devm_kzalloc(cdev,
  5504. sizeof(struct snd_soc_dai_link_component)
  5505. * codecs_enabled, GFP_KERNEL);
  5506. if (!codecs_comp) {
  5507. dev_err(cdev, "%s: %s dailink codec component alloc failed\n",
  5508. __func__, dai_link[i].name);
  5509. ret = -ENOMEM;
  5510. goto err;
  5511. }
  5512. index = 0;
  5513. for (j = 0; j < dai_link[i].num_codecs; j++) {
  5514. if (dai_link[i].codecs[j].of_node) {
  5515. codecs_comp[index].of_node =
  5516. dai_link[i].codecs[j].of_node;
  5517. codecs_comp[index].dai_name =
  5518. dai_link[i].codecs[j].dai_name;
  5519. codecs_comp[index].name = NULL;
  5520. index++;
  5521. }
  5522. }
  5523. dai_link[i].codecs = codecs_comp;
  5524. dai_link[i].num_codecs = codecs_enabled;
  5525. }
  5526. }
  5527. }
  5528. err:
  5529. return ret;
  5530. }
  5531. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5532. {
  5533. int ret = -EINVAL;
  5534. struct snd_soc_component *component =
  5535. snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5536. if (!component) {
  5537. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  5538. return ret;
  5539. }
  5540. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5541. ARRAY_SIZE(msm_snd_controls));
  5542. if (ret < 0) {
  5543. dev_err(component->dev,
  5544. "%s: add_codec_controls failed, err = %d\n",
  5545. __func__, ret);
  5546. return ret;
  5547. }
  5548. return ret;
  5549. }
  5550. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5551. struct snd_pcm_hw_params *params)
  5552. {
  5553. return 0;
  5554. }
  5555. static struct snd_soc_ops msm_stub_be_ops = {
  5556. .hw_params = msm_snd_stub_hw_params,
  5557. };
  5558. struct snd_soc_card snd_soc_card_stub_msm = {
  5559. .name = "holi-stub-snd-card",
  5560. };
  5561. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5562. /* FrontEnd DAI Links */
  5563. {
  5564. .name = "MSMSTUB Media1",
  5565. .stream_name = "MultiMedia1",
  5566. .dynamic = 1,
  5567. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5568. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5569. #endif /* CONFIG_AUDIO_QGKI */
  5570. .dpcm_playback = 1,
  5571. .dpcm_capture = 1,
  5572. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5573. SND_SOC_DPCM_TRIGGER_POST},
  5574. .ignore_suspend = 1,
  5575. /* this dainlink has playback support */
  5576. .ignore_pmdown_time = 1,
  5577. .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
  5578. SND_SOC_DAILINK_REG(multimedia1),
  5579. },
  5580. };
  5581. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5582. /* Backend DAI Links */
  5583. {
  5584. .name = LPASS_BE_AUXPCM_RX,
  5585. .stream_name = "AUX PCM Playback",
  5586. .no_pcm = 1,
  5587. .dpcm_playback = 1,
  5588. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5589. .init = &msm_audrx_stub_init,
  5590. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5591. .ignore_pmdown_time = 1,
  5592. .ignore_suspend = 1,
  5593. .ops = &msm_stub_be_ops,
  5594. SND_SOC_DAILINK_REG(auxpcm_rx),
  5595. },
  5596. {
  5597. .name = LPASS_BE_AUXPCM_TX,
  5598. .stream_name = "AUX PCM Capture",
  5599. .no_pcm = 1,
  5600. .dpcm_capture = 1,
  5601. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5602. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5603. .ignore_suspend = 1,
  5604. .ops = &msm_stub_be_ops,
  5605. SND_SOC_DAILINK_REG(auxpcm_tx),
  5606. },
  5607. };
  5608. static struct snd_soc_dai_link msm_stub_dai_links[
  5609. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5610. ARRAY_SIZE(msm_stub_be_dai_links)];
  5611. static const struct of_device_id holi_asoc_machine_of_match[] = {
  5612. { .compatible = "qcom,holi-asoc-snd",
  5613. .data = "codec"},
  5614. { .compatible = "qcom,holi-asoc-snd-stub",
  5615. .data = "stub_codec"},
  5616. {},
  5617. };
  5618. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5619. {
  5620. struct snd_soc_card *card = NULL;
  5621. struct snd_soc_dai_link *dailink = NULL;
  5622. int len_1 = 0;
  5623. int len_2 = 0;
  5624. int total_links = 0;
  5625. int rc = 0;
  5626. u32 mi2s_audio_intf = 0;
  5627. u32 auxpcm_audio_intf = 0;
  5628. u32 val = 0;
  5629. u32 wcn_btfm_intf = 0;
  5630. const struct of_device_id *match;
  5631. match = of_match_node(holi_asoc_machine_of_match, dev->of_node);
  5632. if (!match) {
  5633. dev_err(dev, "%s: No DT match found for sound card\n",
  5634. __func__);
  5635. return NULL;
  5636. }
  5637. if (!strcmp(match->data, "codec")) {
  5638. card = &snd_soc_card_holi_msm;
  5639. memcpy(msm_holi_dai_links + total_links,
  5640. msm_common_dai_links,
  5641. sizeof(msm_common_dai_links));
  5642. total_links += ARRAY_SIZE(msm_common_dai_links);
  5643. memcpy(msm_holi_dai_links + total_links,
  5644. msm_common_misc_fe_dai_links,
  5645. sizeof(msm_common_misc_fe_dai_links));
  5646. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5647. memcpy(msm_holi_dai_links + total_links,
  5648. msm_common_be_dai_links,
  5649. sizeof(msm_common_be_dai_links));
  5650. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5651. memcpy(msm_holi_dai_links + total_links,
  5652. msm_rx_tx_cdc_dma_be_dai_links,
  5653. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5654. total_links +=
  5655. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  5656. memcpy(msm_holi_dai_links + total_links,
  5657. msm_va_cdc_dma_be_dai_links,
  5658. sizeof(msm_va_cdc_dma_be_dai_links));
  5659. total_links +=
  5660. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5661. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5662. &mi2s_audio_intf);
  5663. if (rc) {
  5664. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5665. __func__);
  5666. } else {
  5667. if (mi2s_audio_intf) {
  5668. memcpy(msm_holi_dai_links + total_links,
  5669. msm_mi2s_be_dai_links,
  5670. sizeof(msm_mi2s_be_dai_links));
  5671. total_links +=
  5672. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5673. }
  5674. }
  5675. rc = of_property_read_u32(dev->of_node,
  5676. "qcom,auxpcm-audio-intf",
  5677. &auxpcm_audio_intf);
  5678. if (rc) {
  5679. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5680. __func__);
  5681. } else {
  5682. if (auxpcm_audio_intf) {
  5683. memcpy(msm_holi_dai_links + total_links,
  5684. msm_auxpcm_be_dai_links,
  5685. sizeof(msm_auxpcm_be_dai_links));
  5686. total_links +=
  5687. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5688. }
  5689. }
  5690. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5691. &val);
  5692. if (!rc && val) {
  5693. memcpy(msm_holi_dai_links + total_links,
  5694. msm_afe_rxtx_lb_be_dai_link,
  5695. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5696. total_links +=
  5697. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5698. }
  5699. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5700. &wcn_btfm_intf);
  5701. if (rc) {
  5702. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5703. __func__);
  5704. } else {
  5705. if (wcn_btfm_intf) {
  5706. memcpy(msm_holi_dai_links + total_links,
  5707. msm_wcn_btfm_be_dai_links,
  5708. sizeof(msm_wcn_btfm_be_dai_links));
  5709. total_links +=
  5710. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5711. }
  5712. }
  5713. dailink = msm_holi_dai_links;
  5714. } else if (!strcmp(match->data, "stub_codec")) {
  5715. card = &snd_soc_card_stub_msm;
  5716. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5717. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5718. memcpy(msm_stub_dai_links,
  5719. msm_stub_fe_dai_links,
  5720. sizeof(msm_stub_fe_dai_links));
  5721. memcpy(msm_stub_dai_links + len_1,
  5722. msm_stub_be_dai_links,
  5723. sizeof(msm_stub_be_dai_links));
  5724. dailink = msm_stub_dai_links;
  5725. total_links = len_2;
  5726. }
  5727. if (card) {
  5728. card->dai_link = dailink;
  5729. card->num_links = total_links;
  5730. }
  5731. return card;
  5732. }
  5733. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  5734. {
  5735. struct snd_soc_component *component = NULL;
  5736. struct snd_soc_dapm_context *dapm = NULL;
  5737. struct snd_card *card = NULL;
  5738. struct snd_info_entry *entry = NULL;
  5739. struct msm_asoc_mach_data *pdata =
  5740. snd_soc_card_get_drvdata(rtd->card);
  5741. int ret = 0;
  5742. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5743. if (!component) {
  5744. pr_err("%s: could not find component for bolero_codec\n",
  5745. __func__);
  5746. return ret;
  5747. }
  5748. dapm = snd_soc_component_get_dapm(component);
  5749. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  5750. ARRAY_SIZE(msm_int_snd_controls));
  5751. if (ret < 0) {
  5752. pr_err("%s: add_component_controls failed: %d\n",
  5753. __func__, ret);
  5754. return ret;
  5755. }
  5756. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  5757. ARRAY_SIZE(msm_common_snd_controls));
  5758. if (ret < 0) {
  5759. pr_err("%s: add common snd controls failed: %d\n",
  5760. __func__, ret);
  5761. return ret;
  5762. }
  5763. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  5764. ARRAY_SIZE(msm_int_dapm_widgets));
  5765. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  5766. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  5767. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  5768. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  5769. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  5770. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  5771. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  5772. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  5773. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  5774. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  5775. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  5776. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  5777. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  5778. snd_soc_dapm_sync(dapm);
  5779. card = rtd->card->snd_card;
  5780. if (!pdata->codec_root) {
  5781. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5782. card->proc_root);
  5783. if (!entry) {
  5784. pr_debug("%s: Cannot create codecs module entry\n",
  5785. __func__);
  5786. ret = 0;
  5787. goto err;
  5788. }
  5789. pdata->codec_root = entry;
  5790. }
  5791. bolero_info_create_codec_entry(pdata->codec_root, component);
  5792. bolero_register_wake_irq(component, false);
  5793. codec_reg_done = true;
  5794. err:
  5795. return ret;
  5796. }
  5797. static int msm_aux_codec_init(struct snd_soc_pcm_runtime *rtd)
  5798. {
  5799. struct snd_soc_component *bolero_component = NULL;
  5800. struct snd_soc_component *component = NULL;
  5801. struct snd_soc_dapm_context *dapm = NULL;
  5802. int ret = 0;
  5803. int codec_variant = -1;
  5804. void *mbhc_calibration;
  5805. struct snd_info_entry *entry;
  5806. struct snd_card *card = NULL;
  5807. struct msm_asoc_mach_data *pdata;
  5808. bool is_wcd938x = false;
  5809. pdata = snd_soc_card_get_drvdata(rtd->card);
  5810. if(!pdata)
  5811. return -EINVAL;
  5812. bolero_component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5813. if (!bolero_component) {
  5814. pr_err("%s: could not find component for bolero_codec\n",
  5815. __func__);
  5816. return -EINVAL;
  5817. }
  5818. if (pdata->wcd_disabled) {
  5819. bolero_set_port_map(bolero_component,
  5820. ARRAY_SIZE(sm_port_map), sm_port_map);
  5821. return 0;
  5822. }
  5823. component = snd_soc_rtdcom_lookup(rtd, WCD938X_DRV_NAME);
  5824. if (!component)
  5825. component = snd_soc_rtdcom_lookup(rtd, WCD937X_DRV_NAME);
  5826. else
  5827. is_wcd938x = true;
  5828. if (!component) {
  5829. pr_err("%s component is NULL\n", __func__);
  5830. return -EINVAL;
  5831. }
  5832. dapm = snd_soc_component_get_dapm(component);
  5833. card = component->card->snd_card;
  5834. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5835. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5836. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5837. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5838. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5839. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5840. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5841. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5842. snd_soc_dapm_sync(dapm);
  5843. if (!pdata->codec_root) {
  5844. entry = msm_snd_info_create_subdir(card->module, "codecs",
  5845. card->proc_root);
  5846. if (!entry) {
  5847. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5848. __func__);
  5849. ret = 0;
  5850. goto mbhc_cfg_cal;
  5851. }
  5852. pdata->codec_root = entry;
  5853. }
  5854. if (!strncmp(component->driver->name, WCD937X_DRV_NAME, 13)) {
  5855. wcd937x_info_create_codec_entry(pdata->codec_root, component);
  5856. ret = snd_soc_add_component_controls(component,
  5857. msm_int_wcd937x_snd_controls,
  5858. ARRAY_SIZE(msm_int_wcd937x_snd_controls));
  5859. bolero_set_port_map(bolero_component,
  5860. ARRAY_SIZE(sm_port_map_wcd937x), sm_port_map_wcd937x);
  5861. } else if (!strncmp(component->driver->name, WCD938X_DRV_NAME, 13)) {
  5862. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  5863. codec_variant = wcd938x_get_codec_variant(component);
  5864. dev_dbg(component->dev, "%s: variant %d\n",
  5865. __func__, codec_variant);
  5866. if (codec_variant == WCD9380)
  5867. ret = snd_soc_add_component_controls(component,
  5868. msm_int_wcd9380_snd_controls,
  5869. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  5870. else if (codec_variant == WCD9385)
  5871. ret = snd_soc_add_component_controls(component,
  5872. msm_int_wcd9385_snd_controls,
  5873. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  5874. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5875. sm_port_map);
  5876. } else {
  5877. bolero_set_port_map(bolero_component, ARRAY_SIZE(sm_port_map),
  5878. sm_port_map);
  5879. }
  5880. if (ret < 0) {
  5881. dev_err(component->dev,
  5882. "%s: add codec specific snd controls failed: %d\n",
  5883. __func__, ret);
  5884. return ret;
  5885. }
  5886. mbhc_cfg_cal:
  5887. mbhc_calibration = def_wcd_mbhc_cal();
  5888. if (!mbhc_calibration)
  5889. return -ENOMEM;
  5890. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5891. if (is_wcd938x)
  5892. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5893. else
  5894. ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5895. if (ret) {
  5896. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5897. __func__, ret);
  5898. goto err_hs_detect;
  5899. }
  5900. return 0;
  5901. err_hs_detect:
  5902. kfree(mbhc_calibration);
  5903. return ret;
  5904. }
  5905. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5906. {
  5907. int count = 0;
  5908. u32 mi2s_master_slave[MI2S_MAX];
  5909. int ret = 0;
  5910. for (count = 0; count < MI2S_MAX; count++) {
  5911. mutex_init(&mi2s_intf_conf[count].lock);
  5912. mi2s_intf_conf[count].ref_cnt = 0;
  5913. }
  5914. ret = of_property_read_u32_array(pdev->dev.of_node,
  5915. "qcom,msm-mi2s-master",
  5916. mi2s_master_slave, MI2S_MAX);
  5917. if (ret) {
  5918. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5919. __func__);
  5920. } else {
  5921. for (count = 0; count < MI2S_MAX; count++) {
  5922. mi2s_intf_conf[count].msm_is_mi2s_master =
  5923. mi2s_master_slave[count];
  5924. }
  5925. }
  5926. }
  5927. static void msm_i2s_auxpcm_deinit(void)
  5928. {
  5929. int count = 0;
  5930. for (count = 0; count < MI2S_MAX; count++) {
  5931. mutex_destroy(&mi2s_intf_conf[count].lock);
  5932. mi2s_intf_conf[count].ref_cnt = 0;
  5933. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5934. }
  5935. }
  5936. static int holi_ssr_enable(struct device *dev, void *data)
  5937. {
  5938. struct platform_device *pdev = to_platform_device(dev);
  5939. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5940. int ret = 0;
  5941. if (!card) {
  5942. dev_err(dev, "%s: card is NULL\n", __func__);
  5943. ret = -EINVAL;
  5944. goto err;
  5945. }
  5946. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5947. /* TODO */
  5948. dev_dbg(dev, "%s: TODO \n", __func__);
  5949. }
  5950. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5951. snd_soc_card_change_online_state(card, 1);
  5952. #endif /* CONFIG_AUDIO_QGKI */
  5953. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5954. err:
  5955. return ret;
  5956. }
  5957. static void holi_ssr_disable(struct device *dev, void *data)
  5958. {
  5959. struct platform_device *pdev = to_platform_device(dev);
  5960. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5961. if (!card) {
  5962. dev_err(dev, "%s: card is NULL\n", __func__);
  5963. return;
  5964. }
  5965. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5966. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  5967. snd_soc_card_change_online_state(card, 0);
  5968. #endif /* CONFIG_AUDIO_QGKI */
  5969. if (!strcmp(card->name, "holi-stub-snd-card")) {
  5970. /* TODO */
  5971. dev_dbg(dev, "%s: TODO \n", __func__);
  5972. }
  5973. }
  5974. static const struct snd_event_ops holi_ssr_ops = {
  5975. .enable = holi_ssr_enable,
  5976. .disable = holi_ssr_disable,
  5977. };
  5978. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5979. {
  5980. struct device_node *node = data;
  5981. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5982. __func__, dev->of_node, node);
  5983. return (dev->of_node && dev->of_node == node);
  5984. }
  5985. static int msm_audio_ssr_register(struct device *dev)
  5986. {
  5987. struct device_node *np = dev->of_node;
  5988. struct snd_event_clients *ssr_clients = NULL;
  5989. struct device_node *node = NULL;
  5990. int ret = 0;
  5991. int i = 0;
  5992. for (i = 0; ; i++) {
  5993. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5994. if (!node)
  5995. break;
  5996. snd_event_mstr_add_client(&ssr_clients,
  5997. msm_audio_ssr_compare, node);
  5998. }
  5999. ret = snd_event_master_register(dev, &holi_ssr_ops,
  6000. ssr_clients, NULL);
  6001. if (!ret)
  6002. snd_event_notify(dev, SND_EVENT_UP);
  6003. return ret;
  6004. }
  6005. static int msm_asoc_parse_soundcard_name(struct platform_device *pdev,
  6006. struct snd_soc_card *card)
  6007. {
  6008. struct nvmem_cell *cell;
  6009. size_t len;
  6010. u32 *buf;
  6011. u32 adsp_var_idx = 0;
  6012. int ret = 0;
  6013. /* get adsp variant idx */
  6014. cell = nvmem_cell_get(&pdev->dev, "adsp_variant");
  6015. if (IS_ERR_OR_NULL(cell)) {
  6016. dev_dbg(&pdev->dev, "%s: FAILED to get nvmem cell \n", __func__);
  6017. goto parse;
  6018. }
  6019. buf = nvmem_cell_read(cell, &len);
  6020. nvmem_cell_put(cell);
  6021. if (IS_ERR_OR_NULL(buf)) {
  6022. dev_dbg(&pdev->dev, "%s: FAILED to read nvmem cell \n", __func__);
  6023. goto parse;
  6024. }
  6025. if (len <= 0 || len > sizeof(u32)) {
  6026. dev_dbg(&pdev->dev, "%s: nvmem cell length out of range: %d\n",
  6027. __func__, len);
  6028. kfree(buf);
  6029. goto parse;
  6030. }
  6031. memcpy(&adsp_var_idx, buf, len);
  6032. kfree(buf);
  6033. parse:
  6034. if(adsp_var_idx == 1)
  6035. ret = snd_soc_of_parse_card_name(card, "qcom,sku-model");
  6036. else
  6037. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6038. if (ret)
  6039. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  6040. __func__, ret);
  6041. return ret;
  6042. }
  6043. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6044. {
  6045. struct snd_soc_card *card = NULL;
  6046. struct msm_asoc_mach_data *pdata = NULL;
  6047. const char *mbhc_audio_jack_type = NULL;
  6048. int ret = 0;
  6049. uint index = 0;
  6050. struct clk *lpass_audio_hw_vote = NULL;
  6051. if (!pdev->dev.of_node) {
  6052. dev_err(&pdev->dev,
  6053. "%s: No platform supplied from device tree\n", __func__);
  6054. return -EINVAL;
  6055. }
  6056. pdata = devm_kzalloc(&pdev->dev,
  6057. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6058. if (!pdata)
  6059. return -ENOMEM;
  6060. of_property_read_u32(pdev->dev.of_node,
  6061. "qcom,wcd-disabled",
  6062. &pdata->wcd_disabled);
  6063. card = populate_snd_card_dailinks(&pdev->dev);
  6064. if (!card) {
  6065. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6066. ret = -EINVAL;
  6067. goto err;
  6068. }
  6069. card->dev = &pdev->dev;
  6070. platform_set_drvdata(pdev, card);
  6071. snd_soc_card_set_drvdata(card, pdata);
  6072. ret = msm_asoc_parse_soundcard_name(pdev, card);
  6073. if (ret) {
  6074. dev_err(&pdev->dev, "%s: parse soundcard name failed, err:%d\n",
  6075. __func__, ret);
  6076. goto err;
  6077. }
  6078. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6079. if (ret) {
  6080. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  6081. __func__, ret);
  6082. goto err;
  6083. }
  6084. ret = msm_populate_dai_link_component_of_node(card);
  6085. if (ret) {
  6086. ret = -EPROBE_DEFER;
  6087. goto err;
  6088. }
  6089. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6090. if (ret == -EPROBE_DEFER) {
  6091. if (codec_reg_done)
  6092. ret = -EINVAL;
  6093. goto err;
  6094. } else if (ret) {
  6095. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  6096. __func__, ret);
  6097. goto err;
  6098. }
  6099. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  6100. __func__, card->name);
  6101. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6102. "qcom,hph-en1-gpio", 0);
  6103. if (!pdata->hph_en1_gpio_p) {
  6104. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6105. __func__, "qcom,hph-en1-gpio",
  6106. pdev->dev.of_node->full_name);
  6107. }
  6108. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6109. "qcom,hph-en0-gpio", 0);
  6110. if (!pdata->hph_en0_gpio_p) {
  6111. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6112. __func__, "qcom,hph-en0-gpio",
  6113. pdev->dev.of_node->full_name);
  6114. }
  6115. ret = of_property_read_string(pdev->dev.of_node,
  6116. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6117. if (ret) {
  6118. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6119. __func__, "qcom,mbhc-audio-jack-type",
  6120. pdev->dev.of_node->full_name);
  6121. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6122. } else {
  6123. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6124. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6125. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6126. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6127. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6128. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6129. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6130. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6131. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6132. } else {
  6133. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6134. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6135. }
  6136. }
  6137. /*
  6138. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6139. * entry is not found in DT file as some targets do not support
  6140. * US-Euro detection
  6141. */
  6142. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6143. "qcom,us-euro-gpios", 0);
  6144. if (!pdata->us_euro_gpio_p) {
  6145. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6146. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6147. } else {
  6148. dev_dbg(&pdev->dev, "%s detected\n",
  6149. "qcom,us-euro-gpios");
  6150. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6151. }
  6152. if (wcd_mbhc_cfg.enable_usbc_analog)
  6153. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6154. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6155. "fsa4480-i2c-handle", 0);
  6156. if (!pdata->fsa_handle)
  6157. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6158. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6159. msm_i2s_auxpcm_init(pdev);
  6160. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6161. "qcom,cdc-dmic01-gpios",
  6162. 0);
  6163. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6164. "qcom,cdc-dmic23-gpios",
  6165. 0);
  6166. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6167. "qcom,cdc-dmic45-gpios",
  6168. 0);
  6169. if (pdata->dmic01_gpio_p)
  6170. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  6171. if (pdata->dmic23_gpio_p)
  6172. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  6173. if (pdata->dmic45_gpio_p)
  6174. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  6175. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6176. "qcom,pri-mi2s-gpios", 0);
  6177. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6178. "qcom,sec-mi2s-gpios", 0);
  6179. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6180. "qcom,tert-mi2s-gpios", 0);
  6181. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6182. "qcom,quat-mi2s-gpios", 0);
  6183. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  6184. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  6185. /* Register LPASS audio hw vote */
  6186. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  6187. if (IS_ERR(lpass_audio_hw_vote)) {
  6188. ret = PTR_ERR(lpass_audio_hw_vote);
  6189. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  6190. __func__, "lpass_audio_hw_vote", ret);
  6191. lpass_audio_hw_vote = NULL;
  6192. ret = 0;
  6193. }
  6194. pdata->lpass_audio_hw_vote = lpass_audio_hw_vote;
  6195. pdata->core_audio_vote_count = 0;
  6196. ret = msm_audio_ssr_register(&pdev->dev);
  6197. if (ret)
  6198. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6199. __func__, ret);
  6200. is_initial_boot = true;
  6201. /* Add QoS request for audio tasks */
  6202. msm_audio_add_qos_request();
  6203. return 0;
  6204. err:
  6205. devm_kfree(&pdev->dev, pdata);
  6206. return ret;
  6207. }
  6208. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6209. {
  6210. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6211. snd_event_master_deregister(&pdev->dev);
  6212. snd_soc_unregister_card(card);
  6213. msm_i2s_auxpcm_deinit();
  6214. msm_audio_remove_qos_request();
  6215. return 0;
  6216. }
  6217. static struct platform_driver holi_asoc_machine_driver = {
  6218. .driver = {
  6219. .name = DRV_NAME,
  6220. .owner = THIS_MODULE,
  6221. .pm = &snd_soc_pm_ops,
  6222. .of_match_table = holi_asoc_machine_of_match,
  6223. .suppress_bind_attrs = true,
  6224. },
  6225. .probe = msm_asoc_machine_probe,
  6226. .remove = msm_asoc_machine_remove,
  6227. };
  6228. module_platform_driver(holi_asoc_machine_driver);
  6229. MODULE_SOFTDEP("pre: bt_fm_slim");
  6230. MODULE_DESCRIPTION("ALSA SoC msm");
  6231. MODULE_LICENSE("GPL v2");
  6232. MODULE_ALIAS("platform:" DRV_NAME);
  6233. MODULE_DEVICE_TABLE(of, holi_asoc_machine_of_match);