hal_rh_generic_api.h 64 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RH_GENERIC_API_H_
  20. #define _HAL_RH_GENERIC_API_H_
  21. #include "hal_tx.h"
  22. #include "hal_rh_tx.h"
  23. #include "hal_rh_rx.h"
  24. #ifdef QCA_UNDECODED_METADATA_SUPPORT
  25. static inline void
  26. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  27. struct hal_rx_ppdu_info *ppdu_info){
  28. switch (hal->target_type) {
  29. case TARGET_TYPE_QCN9000:
  30. ppdu_info->rx_status.phyrx_abort =
  31. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2,
  32. PHYRX_ABORT_REQUEST_INFO_VALID);
  33. ppdu_info->rx_status.phyrx_abort_reason =
  34. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11,
  35. PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON);
  36. break;
  37. default:
  38. break;
  39. }
  40. }
  41. static inline void
  42. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  43. uint8_t *ht_sig_info)
  44. {
  45. ppdu_info->rx_status.ht_length =
  46. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH);
  47. ppdu_info->rx_status.smoothing =
  48. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING);
  49. ppdu_info->rx_status.not_sounding =
  50. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING);
  51. ppdu_info->rx_status.aggregation =
  52. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION);
  53. ppdu_info->rx_status.ht_stbc =
  54. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC);
  55. ppdu_info->rx_status.ht_crc =
  56. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC);
  57. }
  58. static inline void
  59. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  60. uint8_t *l_sig_a_info)
  61. {
  62. ppdu_info->rx_status.l_sig_length =
  63. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH);
  64. ppdu_info->rx_status.l_sig_a_parity =
  65. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY);
  66. ppdu_info->rx_status.l_sig_a_pkt_type =
  67. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE);
  68. ppdu_info->rx_status.l_sig_a_implicit_sounding =
  69. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0,
  70. CAPTURED_IMPLICIT_SOUNDING);
  71. }
  72. static inline void
  73. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  74. uint8_t *vht_sig_a_info)
  75. {
  76. ppdu_info->rx_status.vht_no_txop_ps =
  77. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  78. TXOP_PS_NOT_ALLOWED);
  79. ppdu_info->rx_status.vht_crc =
  80. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC);
  81. }
  82. static inline void
  83. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  84. uint8_t *he_sig_a_su_info) {
  85. ppdu_info->rx_status.he_crc =
  86. HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC);
  87. }
  88. static inline void
  89. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  90. uint8_t *he_sig_a_mu_dl_info) {
  91. ppdu_info->rx_status.he_crc =
  92. HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC);
  93. }
  94. #else
  95. static inline void
  96. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  97. struct hal_rx_ppdu_info *ppdu_info)
  98. {
  99. }
  100. static inline void
  101. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  102. uint8_t *ht_sig_info)
  103. {
  104. }
  105. static inline void
  106. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  107. uint8_t *l_sig_a_info)
  108. {
  109. }
  110. static inline void
  111. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  112. uint8_t *vht_sig_a_info)
  113. {
  114. }
  115. static inline void
  116. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  117. uint8_t *he_sig_a_su_info)
  118. {
  119. }
  120. static inline void
  121. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  122. uint8_t *he_sig_a_mu_dl_info)
  123. {
  124. }
  125. #endif /* QCA_UNDECODED_METADATA_SUPPORT */
  126. /**
  127. * hal_tx_desc_set_buf_addr_generic_rh - Fill Buffer Address information
  128. * in Tx Descriptor
  129. * @desc: Handle to Tx Descriptor
  130. * @paddr: Physical Address
  131. * @rbm_id: Return Buffer Manager ID
  132. * @desc_id: Descriptor ID
  133. * @type: 0 - Address points to a MSDU buffer
  134. * 1 - Address points to MSDU extension descriptor
  135. *
  136. * Return: void
  137. */
  138. static inline void
  139. hal_tx_desc_set_buf_addr_generic_rh(void *desc, dma_addr_t paddr,
  140. uint8_t rbm_id, uint32_t desc_id,
  141. uint8_t type)
  142. {
  143. /* Set buffer_addr_info.buffer_addr_31_0 */
  144. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
  145. BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
  146. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
  147. /* Set buffer_addr_info.buffer_addr_39_32 */
  148. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  149. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  150. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  151. (((uint64_t)paddr) >> 32));
  152. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  153. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  154. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  155. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
  156. RETURN_BUFFER_MANAGER, rbm_id);
  157. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  158. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  159. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  160. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  161. desc_id);
  162. /* Set Buffer or Ext Descriptor Type */
  163. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
  164. BUF_OR_EXT_DESC_TYPE) |=
  165. HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
  166. }
  167. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  168. /**
  169. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  170. * @tlv_tag: Taf of the TLVs
  171. * @rx_tlv: the pointer to the TLVs
  172. * @ppdu_info: pointer to ppdu_info
  173. *
  174. * Return: true if the tlv is handled, false if not
  175. */
  176. static inline bool
  177. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  178. struct hal_rx_ppdu_info *ppdu_info)
  179. {
  180. uint32_t value;
  181. switch (tlv_tag) {
  182. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  183. {
  184. uint8_t *he_sig_a_mu_ul_info =
  185. (uint8_t *)rx_tlv +
  186. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0,
  187. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  188. ppdu_info->rx_status.he_flags = 1;
  189. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  190. FORMAT_INDICATION);
  191. if (value == 0) {
  192. ppdu_info->rx_status.he_data1 =
  193. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  194. } else {
  195. ppdu_info->rx_status.he_data1 =
  196. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  197. }
  198. /* data1 */
  199. ppdu_info->rx_status.he_data1 |=
  200. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  201. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  202. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  203. /* data2 */
  204. ppdu_info->rx_status.he_data2 |=
  205. QDF_MON_STATUS_TXOP_KNOWN;
  206. /*data3*/
  207. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  208. HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID);
  209. ppdu_info->rx_status.he_data3 = value;
  210. /* 1 for UL and 0 for DL */
  211. value = 1;
  212. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  213. ppdu_info->rx_status.he_data3 |= value;
  214. /*data4*/
  215. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  216. SPATIAL_REUSE);
  217. ppdu_info->rx_status.he_data4 = value;
  218. /*data5*/
  219. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  220. HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW);
  221. ppdu_info->rx_status.he_data5 = value;
  222. ppdu_info->rx_status.bw = value;
  223. /*data6*/
  224. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1,
  225. TXOP_DURATION);
  226. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  227. ppdu_info->rx_status.he_data6 |= value;
  228. return true;
  229. }
  230. default:
  231. return false;
  232. }
  233. }
  234. #else
  235. static inline bool
  236. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  237. struct hal_rx_ppdu_info *ppdu_info)
  238. {
  239. return false;
  240. }
  241. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  242. #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \
  243. defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  244. static inline void
  245. hal_rx_handle_mu_ul_info(void *rx_tlv,
  246. struct mon_rx_user_status *mon_rx_user_status)
  247. {
  248. mon_rx_user_status->mu_ul_user_v0_word0 =
  249. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11,
  250. SW_RESPONSE_REFERENCE_PTR);
  251. mon_rx_user_status->mu_ul_user_v0_word1 =
  252. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22,
  253. SW_RESPONSE_REFERENCE_PTR_EXT);
  254. }
  255. static inline void
  256. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  257. struct mon_rx_user_status *mon_rx_user_status)
  258. {
  259. uint32_t mpdu_ok_byte_count;
  260. uint32_t mpdu_err_byte_count;
  261. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  262. RX_PPDU_END_USER_STATS_17,
  263. MPDU_OK_BYTE_COUNT);
  264. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  265. RX_PPDU_END_USER_STATS_19,
  266. MPDU_ERR_BYTE_COUNT);
  267. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  268. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  269. }
  270. #else
  271. static inline void
  272. hal_rx_handle_mu_ul_info(void *rx_tlv,
  273. struct mon_rx_user_status *mon_rx_user_status)
  274. {
  275. }
  276. static inline void
  277. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  278. struct mon_rx_user_status *mon_rx_user_status)
  279. {
  280. struct hal_rx_ppdu_info *ppdu_info =
  281. (struct hal_rx_ppdu_info *)ppduinfo;
  282. /* HKV1: doesn't support mpdu byte count */
  283. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  284. mon_rx_user_status->mpdu_err_byte_count = 0;
  285. }
  286. #endif
  287. static inline void
  288. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  289. struct mon_rx_user_status *mon_rx_user_status)
  290. {
  291. struct mon_rx_info *mon_rx_info;
  292. struct mon_rx_user_info *mon_rx_user_info;
  293. struct hal_rx_ppdu_info *ppdu_info =
  294. (struct hal_rx_ppdu_info *)ppduinfo;
  295. mon_rx_info = &ppdu_info->rx_info;
  296. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  297. mon_rx_user_info->qos_control_info_valid =
  298. mon_rx_info->qos_control_info_valid;
  299. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  300. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  301. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  302. mon_rx_user_status->tcp_msdu_count =
  303. ppdu_info->rx_status.tcp_msdu_count;
  304. mon_rx_user_status->udp_msdu_count =
  305. ppdu_info->rx_status.udp_msdu_count;
  306. mon_rx_user_status->other_msdu_count =
  307. ppdu_info->rx_status.other_msdu_count;
  308. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  309. mon_rx_user_status->frame_control_info_valid =
  310. ppdu_info->rx_status.frame_control_info_valid;
  311. mon_rx_user_status->data_sequence_control_info_valid =
  312. ppdu_info->rx_status.data_sequence_control_info_valid;
  313. mon_rx_user_status->first_data_seq_ctrl =
  314. ppdu_info->rx_status.first_data_seq_ctrl;
  315. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  316. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  317. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  318. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  319. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  320. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  321. mon_rx_user_status->mpdu_cnt_fcs_ok =
  322. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  323. mon_rx_user_status->mpdu_cnt_fcs_err =
  324. ppdu_info->com_info.mpdu_cnt_fcs_err;
  325. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  326. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  327. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  328. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  329. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  330. }
  331. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \
  332. ppdu_info, rssi_info_tlv) \
  333. { \
  334. ppdu_info->rx_status.rssi_chain[chain][0] = \
  335. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  336. RSSI_PRI20_CHAIN##chain); \
  337. ppdu_info->rx_status.rssi_chain[chain][1] = \
  338. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  339. RSSI_EXT20_CHAIN##chain); \
  340. ppdu_info->rx_status.rssi_chain[chain][2] = \
  341. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  342. RSSI_EXT40_LOW20_CHAIN##chain); \
  343. ppdu_info->rx_status.rssi_chain[chain][3] = \
  344. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  345. RSSI_EXT40_HIGH20_CHAIN##chain); \
  346. ppdu_info->rx_status.rssi_chain[chain][4] = \
  347. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  348. RSSI_EXT80_LOW20_CHAIN##chain); \
  349. ppdu_info->rx_status.rssi_chain[chain][5] = \
  350. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  351. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  352. ppdu_info->rx_status.rssi_chain[chain][6] = \
  353. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  354. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  355. ppdu_info->rx_status.rssi_chain[chain][7] = \
  356. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  357. RSSI_EXT80_HIGH20_CHAIN##chain); \
  358. } \
  359. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  360. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \
  361. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \
  362. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \
  363. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \
  364. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \
  365. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \
  366. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \
  367. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \
  368. static inline uint32_t
  369. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  370. uint8_t *rssi_info_tlv)
  371. {
  372. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  373. return 0;
  374. }
  375. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  376. static inline void
  377. hal_get_qos_control(void *rx_tlv,
  378. struct hal_rx_ppdu_info *ppdu_info)
  379. {
  380. ppdu_info->rx_info.qos_control_info_valid =
  381. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  382. QOS_CONTROL_INFO_VALID);
  383. if (ppdu_info->rx_info.qos_control_info_valid)
  384. ppdu_info->rx_info.qos_control =
  385. HAL_RX_GET(rx_tlv,
  386. RX_PPDU_END_USER_STATS_5,
  387. QOS_CONTROL_FIELD);
  388. }
  389. static inline void
  390. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  391. struct hal_rx_ppdu_info *ppdu_info)
  392. {
  393. if ((ppdu_info->sw_frame_group_id
  394. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  395. (ppdu_info->sw_frame_group_id ==
  396. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  397. ppdu_info->rx_info.mac_addr1_valid =
  398. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  399. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  400. HAL_RX_GET(rx_mpdu_start,
  401. RX_MPDU_INFO_15,
  402. MAC_ADDR_AD1_31_0);
  403. if (ppdu_info->sw_frame_group_id ==
  404. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  405. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  406. HAL_RX_GET(rx_mpdu_start,
  407. RX_MPDU_INFO_16,
  408. MAC_ADDR_AD1_47_32);
  409. }
  410. }
  411. }
  412. #else
  413. static inline void
  414. hal_get_qos_control(void *rx_tlv,
  415. struct hal_rx_ppdu_info *ppdu_info)
  416. {
  417. }
  418. static inline void
  419. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  420. struct hal_rx_ppdu_info *ppdu_info)
  421. {
  422. }
  423. #endif
  424. #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
  425. static inline void
  426. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  427. struct hal_rx_ppdu_info *ppdu_info)
  428. {
  429. uint16_t frame_ctrl;
  430. uint8_t fc_type;
  431. if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) {
  432. frame_ctrl = HAL_RX_GET(rx_mpdu_start,
  433. RX_MPDU_INFO_14,
  434. MPDU_FRAME_CONTROL_FIELD);
  435. fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
  436. if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
  437. ppdu_info->frm_type_info.rx_mgmt_cnt++;
  438. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
  439. ppdu_info->frm_type_info.rx_ctrl_cnt++;
  440. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
  441. ppdu_info->frm_type_info.rx_data_cnt++;
  442. }
  443. }
  444. #else
  445. static inline void
  446. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  447. struct hal_rx_ppdu_info *ppdu_info)
  448. {
  449. }
  450. #endif
  451. /**
  452. * hal_rx_status_get_tlv_info_generic_rh() - process receive info TLV
  453. * @rx_tlv_hdr: pointer to TLV header
  454. * @ppduinfo: pointer to ppdu_info
  455. * @hal_soc_hdl: HAL SOC handle
  456. * @nbuf: pkt buffer
  457. *
  458. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  459. */
  460. static inline uint32_t
  461. hal_rx_status_get_tlv_info_generic_rh(void *rx_tlv_hdr, void *ppduinfo,
  462. hal_soc_handle_t hal_soc_hdl,
  463. qdf_nbuf_t nbuf)
  464. {
  465. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  466. uint32_t tlv_tag, user_id, tlv_len, value;
  467. uint8_t group_id = 0;
  468. uint8_t he_dcm = 0;
  469. uint8_t he_stbc = 0;
  470. uint16_t he_gi = 0;
  471. uint16_t he_ltf = 0;
  472. void *rx_tlv;
  473. bool unhandled = false;
  474. struct mon_rx_user_status *mon_rx_user_status;
  475. struct hal_rx_ppdu_info *ppdu_info =
  476. (struct hal_rx_ppdu_info *)ppduinfo;
  477. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  478. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  479. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  480. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  481. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  482. rx_tlv, tlv_len);
  483. switch (tlv_tag) {
  484. case WIFIRX_PPDU_START_E:
  485. {
  486. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  487. HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID)))
  488. hal_err("Matching ppdu_id(%u) detected",
  489. ppdu_info->com_info.last_ppdu_id);
  490. /* Reset ppdu_info before processing the ppdu */
  491. qdf_mem_zero(ppdu_info,
  492. sizeof(struct hal_rx_ppdu_info));
  493. ppdu_info->com_info.last_ppdu_id =
  494. ppdu_info->com_info.ppdu_id =
  495. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  496. PHY_PPDU_ID);
  497. /* channel number is set in PHY meta data */
  498. ppdu_info->rx_status.chan_num =
  499. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  500. SW_PHY_META_DATA) & 0x0000FFFF);
  501. ppdu_info->rx_status.chan_freq =
  502. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  503. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  504. if (ppdu_info->rx_status.chan_num) {
  505. ppdu_info->rx_status.chan_freq =
  506. hal_rx_radiotap_num_to_freq(
  507. ppdu_info->rx_status.chan_num,
  508. ppdu_info->rx_status.chan_freq);
  509. }
  510. ppdu_info->com_info.ppdu_timestamp =
  511. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  512. PPDU_START_TIMESTAMP);
  513. ppdu_info->rx_status.ppdu_timestamp =
  514. ppdu_info->com_info.ppdu_timestamp;
  515. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  516. break;
  517. }
  518. case WIFIRX_PPDU_START_USER_INFO_E:
  519. break;
  520. case WIFIRX_PPDU_END_E:
  521. dp_nofl_debug("[%s][%d] ppdu_end_e len=%d",
  522. __func__, __LINE__, tlv_len);
  523. /* This is followed by sub-TLVs of PPDU_END */
  524. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  525. break;
  526. case WIFIPHYRX_PKT_END_E:
  527. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  528. break;
  529. case WIFIRXPCU_PPDU_END_INFO_E:
  530. ppdu_info->rx_status.rx_antenna =
  531. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA);
  532. ppdu_info->rx_status.tsft =
  533. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  534. WB_TIMESTAMP_UPPER_32);
  535. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  536. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  537. WB_TIMESTAMP_LOWER_32);
  538. ppdu_info->rx_status.duration =
  539. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  540. RX_PPDU_DURATION);
  541. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  542. hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info);
  543. break;
  544. /*
  545. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  546. * for MU, based on num users we see this tlv that many times.
  547. */
  548. case WIFIRX_PPDU_END_USER_STATS_E:
  549. {
  550. unsigned long tid = 0;
  551. uint16_t seq = 0;
  552. ppdu_info->rx_status.ast_index =
  553. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  554. AST_INDEX);
  555. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  556. RECEIVED_QOS_DATA_TID_BITMAP);
  557. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  558. sizeof(tid) * 8);
  559. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  560. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  561. ppdu_info->rx_status.tcp_msdu_count =
  562. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  563. TCP_MSDU_COUNT) +
  564. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  565. TCP_ACK_MSDU_COUNT);
  566. ppdu_info->rx_status.udp_msdu_count =
  567. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  568. UDP_MSDU_COUNT);
  569. ppdu_info->rx_status.other_msdu_count =
  570. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  571. OTHER_MSDU_COUNT);
  572. if (ppdu_info->sw_frame_group_id
  573. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  574. ppdu_info->rx_status.frame_control_info_valid =
  575. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  576. FRAME_CONTROL_INFO_VALID);
  577. if (ppdu_info->rx_status.frame_control_info_valid)
  578. ppdu_info->rx_status.frame_control =
  579. HAL_RX_GET(rx_tlv,
  580. RX_PPDU_END_USER_STATS_4,
  581. FRAME_CONTROL_FIELD);
  582. hal_get_qos_control(rx_tlv, ppdu_info);
  583. }
  584. ppdu_info->rx_status.data_sequence_control_info_valid =
  585. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  586. DATA_SEQUENCE_CONTROL_INFO_VALID);
  587. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  588. FIRST_DATA_SEQ_CTRL);
  589. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  590. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  591. ppdu_info->rx_status.preamble_type =
  592. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  593. HT_CONTROL_FIELD_PKT_TYPE);
  594. switch (ppdu_info->rx_status.preamble_type) {
  595. case HAL_RX_PKT_TYPE_11N:
  596. ppdu_info->rx_status.ht_flags = 1;
  597. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  598. break;
  599. case HAL_RX_PKT_TYPE_11AC:
  600. ppdu_info->rx_status.vht_flags = 1;
  601. break;
  602. case HAL_RX_PKT_TYPE_11AX:
  603. ppdu_info->rx_status.he_flags = 1;
  604. break;
  605. default:
  606. break;
  607. }
  608. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  609. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  610. MPDU_CNT_FCS_OK);
  611. ppdu_info->com_info.mpdu_cnt_fcs_err =
  612. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  613. MPDU_CNT_FCS_ERR);
  614. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  615. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  616. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  617. else
  618. ppdu_info->rx_status.rs_flags &=
  619. (~IEEE80211_AMPDU_FLAG);
  620. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  621. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7,
  622. FCS_OK_BITMAP_31_0);
  623. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  624. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8,
  625. FCS_OK_BITMAP_63_32);
  626. if (user_id < HAL_MAX_UL_MU_USERS) {
  627. mon_rx_user_status =
  628. &ppdu_info->rx_user_status[user_id];
  629. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  630. ppdu_info->com_info.num_users++;
  631. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  632. user_id,
  633. mon_rx_user_status);
  634. }
  635. break;
  636. }
  637. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  638. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  639. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1,
  640. FCS_OK_BITMAP_95_64);
  641. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  642. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2,
  643. FCS_OK_BITMAP_127_96);
  644. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  645. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3,
  646. FCS_OK_BITMAP_159_128);
  647. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  648. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4,
  649. FCS_OK_BITMAP_191_160);
  650. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  651. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5,
  652. FCS_OK_BITMAP_223_192);
  653. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  654. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6,
  655. FCS_OK_BITMAP_255_224);
  656. break;
  657. case WIFIRX_PPDU_END_STATUS_DONE_E:
  658. return HAL_TLV_STATUS_PPDU_DONE;
  659. case WIFIDUMMY_E:
  660. return HAL_TLV_STATUS_BUF_DONE;
  661. case WIFIPHYRX_HT_SIG_E:
  662. {
  663. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  664. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  665. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  666. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  667. FEC_CODING);
  668. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  669. 1 : 0;
  670. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  671. HT_SIG_INFO_0, MCS);
  672. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  673. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  674. HT_SIG_INFO_0, CBW);
  675. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  676. HT_SIG_INFO_1, SHORT_GI);
  677. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  678. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  679. HT_SIG_SU_NSS_SHIFT) + 1;
  680. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  681. hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info);
  682. break;
  683. }
  684. case WIFIPHYRX_L_SIG_B_E:
  685. {
  686. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  687. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  688. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  689. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  690. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  691. switch (value) {
  692. case 1:
  693. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  694. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  695. break;
  696. case 2:
  697. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  698. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  699. break;
  700. case 3:
  701. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  702. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  703. break;
  704. case 4:
  705. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  706. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  707. break;
  708. case 5:
  709. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  710. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  711. break;
  712. case 6:
  713. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  714. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  715. break;
  716. case 7:
  717. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  718. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  719. break;
  720. default:
  721. break;
  722. }
  723. ppdu_info->rx_status.cck_flag = 1;
  724. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  725. break;
  726. }
  727. case WIFIPHYRX_L_SIG_A_E:
  728. {
  729. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  730. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  731. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  732. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  733. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  734. switch (value) {
  735. case 8:
  736. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  737. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  738. break;
  739. case 9:
  740. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  741. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  742. break;
  743. case 10:
  744. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  745. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  746. break;
  747. case 11:
  748. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  749. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  750. break;
  751. case 12:
  752. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  753. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  754. break;
  755. case 13:
  756. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  757. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  758. break;
  759. case 14:
  760. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  761. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  762. break;
  763. case 15:
  764. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  765. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  766. break;
  767. default:
  768. break;
  769. }
  770. ppdu_info->rx_status.ofdm_flag = 1;
  771. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  772. hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info);
  773. break;
  774. }
  775. case WIFIPHYRX_VHT_SIG_A_E:
  776. {
  777. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  778. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  779. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  780. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  781. SU_MU_CODING);
  782. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  783. 1 : 0;
  784. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  785. GROUP_ID);
  786. ppdu_info->rx_status.vht_flag_values5 = group_id;
  787. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  788. VHT_SIG_A_INFO_1, MCS);
  789. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  790. VHT_SIG_A_INFO_1, GI_SETTING);
  791. switch (hal->target_type) {
  792. case TARGET_TYPE_QCA8074:
  793. case TARGET_TYPE_QCA8074V2:
  794. case TARGET_TYPE_QCA6018:
  795. case TARGET_TYPE_QCA5018:
  796. case TARGET_TYPE_QCN9000:
  797. case TARGET_TYPE_QCN6122:
  798. #ifdef QCA_WIFI_QCA6390
  799. case TARGET_TYPE_QCA6390:
  800. #endif
  801. case TARGET_TYPE_QCA6490:
  802. ppdu_info->rx_status.is_stbc =
  803. HAL_RX_GET(vht_sig_a_info,
  804. VHT_SIG_A_INFO_0, STBC);
  805. value = HAL_RX_GET(vht_sig_a_info,
  806. VHT_SIG_A_INFO_0, N_STS);
  807. value = value & VHT_SIG_SU_NSS_MASK;
  808. if (ppdu_info->rx_status.is_stbc && (value > 0))
  809. value = ((value + 1) >> 1) - 1;
  810. ppdu_info->rx_status.nss =
  811. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  812. break;
  813. case TARGET_TYPE_QCA6290:
  814. #if !defined(QCA_WIFI_QCA6290_11AX)
  815. ppdu_info->rx_status.is_stbc =
  816. HAL_RX_GET(vht_sig_a_info,
  817. VHT_SIG_A_INFO_0, STBC);
  818. value = HAL_RX_GET(vht_sig_a_info,
  819. VHT_SIG_A_INFO_0, N_STS);
  820. value = value & VHT_SIG_SU_NSS_MASK;
  821. if (ppdu_info->rx_status.is_stbc && (value > 0))
  822. value = ((value + 1) >> 1) - 1;
  823. ppdu_info->rx_status.nss =
  824. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  825. #else
  826. ppdu_info->rx_status.nss = 0;
  827. #endif
  828. break;
  829. case TARGET_TYPE_QCA6750:
  830. ppdu_info->rx_status.nss = 0;
  831. break;
  832. default:
  833. break;
  834. }
  835. ppdu_info->rx_status.vht_flag_values3[0] =
  836. (((ppdu_info->rx_status.mcs) << 4)
  837. | ppdu_info->rx_status.nss);
  838. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  839. VHT_SIG_A_INFO_0, BANDWIDTH);
  840. ppdu_info->rx_status.vht_flag_values2 =
  841. ppdu_info->rx_status.bw;
  842. ppdu_info->rx_status.vht_flag_values4 =
  843. HAL_RX_GET(vht_sig_a_info,
  844. VHT_SIG_A_INFO_1, SU_MU_CODING);
  845. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  846. VHT_SIG_A_INFO_1, BEAMFORMED);
  847. if (group_id == 0 || group_id == 63)
  848. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  849. else
  850. ppdu_info->rx_status.reception_type =
  851. HAL_RX_TYPE_MU_MIMO;
  852. hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info);
  853. break;
  854. }
  855. case WIFIPHYRX_HE_SIG_A_SU_E:
  856. {
  857. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  858. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  859. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  860. ppdu_info->rx_status.he_flags = 1;
  861. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  862. FORMAT_INDICATION);
  863. if (value == 0) {
  864. ppdu_info->rx_status.he_data1 =
  865. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  866. } else {
  867. ppdu_info->rx_status.he_data1 =
  868. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  869. }
  870. /* data1 */
  871. ppdu_info->rx_status.he_data1 |=
  872. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  873. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  874. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  875. QDF_MON_STATUS_HE_MCS_KNOWN |
  876. QDF_MON_STATUS_HE_DCM_KNOWN |
  877. QDF_MON_STATUS_HE_CODING_KNOWN |
  878. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  879. QDF_MON_STATUS_HE_STBC_KNOWN |
  880. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  881. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  882. /* data2 */
  883. ppdu_info->rx_status.he_data2 =
  884. QDF_MON_STATUS_HE_GI_KNOWN;
  885. ppdu_info->rx_status.he_data2 |=
  886. QDF_MON_STATUS_TXBF_KNOWN |
  887. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  888. QDF_MON_STATUS_TXOP_KNOWN |
  889. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  890. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  891. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  892. /* data3 */
  893. value = HAL_RX_GET(he_sig_a_su_info,
  894. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  895. ppdu_info->rx_status.he_data3 = value;
  896. value = HAL_RX_GET(he_sig_a_su_info,
  897. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  898. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  899. ppdu_info->rx_status.he_data3 |= value;
  900. value = HAL_RX_GET(he_sig_a_su_info,
  901. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  902. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  903. ppdu_info->rx_status.he_data3 |= value;
  904. value = HAL_RX_GET(he_sig_a_su_info,
  905. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  906. ppdu_info->rx_status.mcs = value;
  907. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  908. ppdu_info->rx_status.he_data3 |= value;
  909. value = HAL_RX_GET(he_sig_a_su_info,
  910. HE_SIG_A_SU_INFO_0, DCM);
  911. he_dcm = value;
  912. value = value << QDF_MON_STATUS_DCM_SHIFT;
  913. ppdu_info->rx_status.he_data3 |= value;
  914. value = HAL_RX_GET(he_sig_a_su_info,
  915. HE_SIG_A_SU_INFO_1, CODING);
  916. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  917. 1 : 0;
  918. value = value << QDF_MON_STATUS_CODING_SHIFT;
  919. ppdu_info->rx_status.he_data3 |= value;
  920. value = HAL_RX_GET(he_sig_a_su_info,
  921. HE_SIG_A_SU_INFO_1,
  922. LDPC_EXTRA_SYMBOL);
  923. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  924. ppdu_info->rx_status.he_data3 |= value;
  925. value = HAL_RX_GET(he_sig_a_su_info,
  926. HE_SIG_A_SU_INFO_1, STBC);
  927. he_stbc = value;
  928. value = value << QDF_MON_STATUS_STBC_SHIFT;
  929. ppdu_info->rx_status.he_data3 |= value;
  930. /* data4 */
  931. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  932. SPATIAL_REUSE);
  933. ppdu_info->rx_status.he_data4 = value;
  934. /* data5 */
  935. value = HAL_RX_GET(he_sig_a_su_info,
  936. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  937. ppdu_info->rx_status.he_data5 = value;
  938. ppdu_info->rx_status.bw = value;
  939. value = HAL_RX_GET(he_sig_a_su_info,
  940. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  941. switch (value) {
  942. case 0:
  943. he_gi = HE_GI_0_8;
  944. he_ltf = HE_LTF_1_X;
  945. break;
  946. case 1:
  947. he_gi = HE_GI_0_8;
  948. he_ltf = HE_LTF_2_X;
  949. break;
  950. case 2:
  951. he_gi = HE_GI_1_6;
  952. he_ltf = HE_LTF_2_X;
  953. break;
  954. case 3:
  955. if (he_dcm && he_stbc) {
  956. he_gi = HE_GI_0_8;
  957. he_ltf = HE_LTF_4_X;
  958. } else {
  959. he_gi = HE_GI_3_2;
  960. he_ltf = HE_LTF_4_X;
  961. }
  962. break;
  963. }
  964. ppdu_info->rx_status.sgi = he_gi;
  965. ppdu_info->rx_status.ltf_size = he_ltf;
  966. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  967. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  968. ppdu_info->rx_status.he_data5 |= value;
  969. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  970. ppdu_info->rx_status.he_data5 |= value;
  971. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  972. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  973. ppdu_info->rx_status.he_data5 |= value;
  974. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  975. PACKET_EXTENSION_A_FACTOR);
  976. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  977. ppdu_info->rx_status.he_data5 |= value;
  978. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  979. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  980. ppdu_info->rx_status.he_data5 |= value;
  981. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  982. PACKET_EXTENSION_PE_DISAMBIGUITY);
  983. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  984. ppdu_info->rx_status.he_data5 |= value;
  985. /* data6 */
  986. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  987. value++;
  988. ppdu_info->rx_status.nss = value;
  989. ppdu_info->rx_status.he_data6 = value;
  990. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  991. DOPPLER_INDICATION);
  992. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  993. ppdu_info->rx_status.he_data6 |= value;
  994. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  995. TXOP_DURATION);
  996. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  997. ppdu_info->rx_status.he_data6 |= value;
  998. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  999. HE_SIG_A_SU_INFO_1, TXBF);
  1000. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  1001. hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info);
  1002. break;
  1003. }
  1004. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  1005. {
  1006. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  1007. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  1008. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  1009. ppdu_info->rx_status.he_mu_flags = 1;
  1010. /* HE Flags */
  1011. /*data1*/
  1012. ppdu_info->rx_status.he_data1 =
  1013. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1014. ppdu_info->rx_status.he_data1 |=
  1015. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  1016. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  1017. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  1018. QDF_MON_STATUS_HE_STBC_KNOWN |
  1019. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  1020. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  1021. /* data2 */
  1022. ppdu_info->rx_status.he_data2 =
  1023. QDF_MON_STATUS_HE_GI_KNOWN;
  1024. ppdu_info->rx_status.he_data2 |=
  1025. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  1026. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  1027. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  1028. QDF_MON_STATUS_TXOP_KNOWN |
  1029. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  1030. /*data3*/
  1031. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1032. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  1033. ppdu_info->rx_status.he_data3 = value;
  1034. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1035. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  1036. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  1037. ppdu_info->rx_status.he_data3 |= value;
  1038. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1039. HE_SIG_A_MU_DL_INFO_1,
  1040. LDPC_EXTRA_SYMBOL);
  1041. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  1042. ppdu_info->rx_status.he_data3 |= value;
  1043. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1044. HE_SIG_A_MU_DL_INFO_1, STBC);
  1045. he_stbc = value;
  1046. value = value << QDF_MON_STATUS_STBC_SHIFT;
  1047. ppdu_info->rx_status.he_data3 |= value;
  1048. /*data4*/
  1049. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1050. SPATIAL_REUSE);
  1051. ppdu_info->rx_status.he_data4 = value;
  1052. /*data5*/
  1053. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1054. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1055. ppdu_info->rx_status.he_data5 = value;
  1056. ppdu_info->rx_status.bw = value;
  1057. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1058. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  1059. switch (value) {
  1060. case 0:
  1061. he_gi = HE_GI_0_8;
  1062. he_ltf = HE_LTF_4_X;
  1063. break;
  1064. case 1:
  1065. he_gi = HE_GI_0_8;
  1066. he_ltf = HE_LTF_2_X;
  1067. break;
  1068. case 2:
  1069. he_gi = HE_GI_1_6;
  1070. he_ltf = HE_LTF_2_X;
  1071. break;
  1072. case 3:
  1073. he_gi = HE_GI_3_2;
  1074. he_ltf = HE_LTF_4_X;
  1075. break;
  1076. }
  1077. ppdu_info->rx_status.sgi = he_gi;
  1078. ppdu_info->rx_status.ltf_size = he_ltf;
  1079. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  1080. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  1081. ppdu_info->rx_status.he_data5 |= value;
  1082. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  1083. ppdu_info->rx_status.he_data5 |= value;
  1084. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1085. HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
  1086. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  1087. ppdu_info->rx_status.he_data5 |= value;
  1088. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1089. PACKET_EXTENSION_A_FACTOR);
  1090. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  1091. ppdu_info->rx_status.he_data5 |= value;
  1092. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1093. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1094. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  1095. ppdu_info->rx_status.he_data5 |= value;
  1096. /*data6*/
  1097. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1098. DOPPLER_INDICATION);
  1099. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  1100. ppdu_info->rx_status.he_data6 |= value;
  1101. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1102. TXOP_DURATION);
  1103. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1104. ppdu_info->rx_status.he_data6 |= value;
  1105. /* HE-MU Flags */
  1106. /* HE-MU-flags1 */
  1107. ppdu_info->rx_status.he_flags1 =
  1108. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1109. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1110. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1111. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1112. QDF_MON_STATUS_RU_0_KNOWN;
  1113. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1114. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  1115. ppdu_info->rx_status.he_flags1 |= value;
  1116. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1117. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  1118. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1119. ppdu_info->rx_status.he_flags1 |= value;
  1120. /* HE-MU-flags2 */
  1121. ppdu_info->rx_status.he_flags2 =
  1122. QDF_MON_STATUS_BW_KNOWN;
  1123. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1124. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1125. ppdu_info->rx_status.he_flags2 |= value;
  1126. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1127. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  1128. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1129. ppdu_info->rx_status.he_flags2 |= value;
  1130. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1131. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  1132. value = value - 1;
  1133. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1134. ppdu_info->rx_status.he_flags2 |= value;
  1135. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1136. hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info,
  1137. he_sig_a_mu_dl_info);
  1138. break;
  1139. }
  1140. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1141. {
  1142. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1143. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1144. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1145. ppdu_info->rx_status.he_sig_b_common_known |=
  1146. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1147. /* TODO: Check on the availability of other fields in
  1148. * sig_b_common
  1149. */
  1150. value = HAL_RX_GET(he_sig_b1_mu_info,
  1151. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  1152. ppdu_info->rx_status.he_RU[0] = value;
  1153. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1154. break;
  1155. }
  1156. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1157. {
  1158. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1159. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1160. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1161. /*
  1162. * Not all "HE" fields can be updated from
  1163. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1164. * to populate rest of the "HE" fields for MU scenarios.
  1165. */
  1166. /* HE-data1 */
  1167. ppdu_info->rx_status.he_data1 |=
  1168. QDF_MON_STATUS_HE_MCS_KNOWN |
  1169. QDF_MON_STATUS_HE_CODING_KNOWN;
  1170. /* HE-data2 */
  1171. /* HE-data3 */
  1172. value = HAL_RX_GET(he_sig_b2_mu_info,
  1173. HE_SIG_B2_MU_INFO_0, STA_MCS);
  1174. ppdu_info->rx_status.mcs = value;
  1175. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1176. ppdu_info->rx_status.he_data3 |= value;
  1177. value = HAL_RX_GET(he_sig_b2_mu_info,
  1178. HE_SIG_B2_MU_INFO_0, STA_CODING);
  1179. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1180. ppdu_info->rx_status.he_data3 |= value;
  1181. /* HE-data4 */
  1182. value = HAL_RX_GET(he_sig_b2_mu_info,
  1183. HE_SIG_B2_MU_INFO_0, STA_ID);
  1184. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1185. ppdu_info->rx_status.he_data4 |= value;
  1186. /* HE-data5 */
  1187. /* HE-data6 */
  1188. value = HAL_RX_GET(he_sig_b2_mu_info,
  1189. HE_SIG_B2_MU_INFO_0, NSTS);
  1190. /* value n indicates n+1 spatial streams */
  1191. value++;
  1192. ppdu_info->rx_status.nss = value;
  1193. ppdu_info->rx_status.he_data6 |= value;
  1194. break;
  1195. }
  1196. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1197. {
  1198. uint8_t *he_sig_b2_ofdma_info =
  1199. (uint8_t *)rx_tlv +
  1200. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1201. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1202. /*
  1203. * Not all "HE" fields can be updated from
  1204. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1205. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1206. */
  1207. /* HE-data1 */
  1208. ppdu_info->rx_status.he_data1 |=
  1209. QDF_MON_STATUS_HE_MCS_KNOWN |
  1210. QDF_MON_STATUS_HE_DCM_KNOWN |
  1211. QDF_MON_STATUS_HE_CODING_KNOWN;
  1212. /* HE-data2 */
  1213. ppdu_info->rx_status.he_data2 |=
  1214. QDF_MON_STATUS_TXBF_KNOWN;
  1215. /* HE-data3 */
  1216. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1217. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  1218. ppdu_info->rx_status.mcs = value;
  1219. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1220. ppdu_info->rx_status.he_data3 |= value;
  1221. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1222. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  1223. he_dcm = value;
  1224. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1225. ppdu_info->rx_status.he_data3 |= value;
  1226. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1227. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  1228. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1229. ppdu_info->rx_status.he_data3 |= value;
  1230. /* HE-data4 */
  1231. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1232. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1233. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1234. ppdu_info->rx_status.he_data4 |= value;
  1235. /* HE-data5 */
  1236. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1237. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1238. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1239. ppdu_info->rx_status.he_data5 |= value;
  1240. /* HE-data6 */
  1241. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1242. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1243. /* value n indicates n+1 spatial streams */
  1244. value++;
  1245. ppdu_info->rx_status.nss = value;
  1246. ppdu_info->rx_status.he_data6 |= value;
  1247. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1248. break;
  1249. }
  1250. case WIFIPHYRX_RSSI_LEGACY_E:
  1251. {
  1252. uint8_t reception_type;
  1253. int8_t rssi_value;
  1254. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1255. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1256. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1257. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1258. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1259. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1260. ppdu_info->rx_status.he_re = 0;
  1261. reception_type = HAL_RX_GET(rx_tlv,
  1262. PHYRX_RSSI_LEGACY_0,
  1263. RECEPTION_TYPE);
  1264. switch (reception_type) {
  1265. case QDF_RECEPTION_TYPE_ULOFMDA:
  1266. ppdu_info->rx_status.reception_type =
  1267. HAL_RX_TYPE_MU_OFDMA;
  1268. ppdu_info->rx_status.ulofdma_flag = 1;
  1269. ppdu_info->rx_status.he_data1 =
  1270. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1271. break;
  1272. case QDF_RECEPTION_TYPE_ULMIMO:
  1273. ppdu_info->rx_status.reception_type =
  1274. HAL_RX_TYPE_MU_MIMO;
  1275. ppdu_info->rx_status.he_data1 =
  1276. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1277. break;
  1278. default:
  1279. ppdu_info->rx_status.reception_type =
  1280. HAL_RX_TYPE_SU;
  1281. break;
  1282. }
  1283. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1284. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1285. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1286. ppdu_info->rx_status.rssi[0] = rssi_value;
  1287. dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1288. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1289. RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1);
  1290. ppdu_info->rx_status.rssi[1] = rssi_value;
  1291. dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1292. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1293. RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2);
  1294. ppdu_info->rx_status.rssi[2] = rssi_value;
  1295. dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1296. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1297. RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3);
  1298. ppdu_info->rx_status.rssi[3] = rssi_value;
  1299. dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1300. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1301. RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4);
  1302. ppdu_info->rx_status.rssi[4] = rssi_value;
  1303. dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1304. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1305. RECEIVE_RSSI_INFO_10,
  1306. RSSI_PRI20_CHAIN5);
  1307. ppdu_info->rx_status.rssi[5] = rssi_value;
  1308. dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1309. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1310. RECEIVE_RSSI_INFO_12,
  1311. RSSI_PRI20_CHAIN6);
  1312. ppdu_info->rx_status.rssi[6] = rssi_value;
  1313. dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1314. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1315. RECEIVE_RSSI_INFO_14,
  1316. RSSI_PRI20_CHAIN7);
  1317. ppdu_info->rx_status.rssi[7] = rssi_value;
  1318. dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1319. break;
  1320. }
  1321. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1322. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1323. ppdu_info);
  1324. break;
  1325. case WIFIRX_HEADER_E:
  1326. {
  1327. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1328. if (ppdu_info->fcs_ok_cnt >=
  1329. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1330. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1331. ppdu_info->fcs_ok_cnt);
  1332. break;
  1333. }
  1334. /* Update first_msdu_payload for every mpdu and increment
  1335. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1336. */
  1337. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1338. rx_tlv;
  1339. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1340. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1341. ppdu_info->msdu_info.payload_len = tlv_len;
  1342. ppdu_info->user_id = user_id;
  1343. ppdu_info->hdr_len = tlv_len;
  1344. ppdu_info->data = rx_tlv;
  1345. ppdu_info->data += 4;
  1346. /* for every RX_HEADER TLV increment mpdu_cnt */
  1347. com_info->mpdu_cnt++;
  1348. return HAL_TLV_STATUS_HEADER;
  1349. }
  1350. case WIFIRX_MPDU_START_E:
  1351. {
  1352. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1353. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start);
  1354. uint8_t filter_category = 0;
  1355. hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info);
  1356. ppdu_info->nac_info.fc_valid =
  1357. HAL_RX_GET_FC_VALID(rx_mpdu_start);
  1358. ppdu_info->nac_info.to_ds_flag =
  1359. HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start);
  1360. ppdu_info->nac_info.frame_control =
  1361. HAL_RX_GET(rx_mpdu_start,
  1362. RX_MPDU_INFO_14,
  1363. MPDU_FRAME_CONTROL_FIELD);
  1364. ppdu_info->sw_frame_group_id =
  1365. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start);
  1366. ppdu_info->rx_user_status[user_id].sw_peer_id =
  1367. HAL_RX_GET_SW_PEER_ID(rx_mpdu_start);
  1368. if (ppdu_info->sw_frame_group_id ==
  1369. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1370. ppdu_info->rx_status.frame_control_info_valid =
  1371. ppdu_info->nac_info.fc_valid;
  1372. ppdu_info->rx_status.frame_control =
  1373. ppdu_info->nac_info.frame_control;
  1374. }
  1375. hal_get_mac_addr1(rx_mpdu_start,
  1376. ppdu_info);
  1377. ppdu_info->nac_info.mac_addr2_valid =
  1378. HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start);
  1379. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1380. HAL_RX_GET(rx_mpdu_start,
  1381. RX_MPDU_INFO_16,
  1382. MAC_ADDR_AD2_15_0);
  1383. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1384. HAL_RX_GET(rx_mpdu_start,
  1385. RX_MPDU_INFO_17,
  1386. MAC_ADDR_AD2_47_16);
  1387. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1388. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1389. ppdu_info->rx_status.ppdu_len =
  1390. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1391. MPDU_LENGTH);
  1392. } else {
  1393. ppdu_info->rx_status.ppdu_len +=
  1394. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1395. MPDU_LENGTH);
  1396. }
  1397. filter_category =
  1398. HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start);
  1399. if (filter_category == 0)
  1400. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1401. else if (filter_category == 1)
  1402. ppdu_info->rx_status.monitor_direct_used = 1;
  1403. ppdu_info->nac_info.mcast_bcast =
  1404. HAL_RX_GET(rx_mpdu_start,
  1405. RX_MPDU_INFO_13,
  1406. MCAST_BCAST);
  1407. break;
  1408. }
  1409. case WIFIRX_MPDU_END_E:
  1410. ppdu_info->user_id = user_id;
  1411. ppdu_info->fcs_err =
  1412. HAL_RX_GET(rx_tlv, RX_MPDU_END_1,
  1413. FCS_ERR);
  1414. return HAL_TLV_STATUS_MPDU_END;
  1415. case WIFIRX_MSDU_END_E:
  1416. if (user_id < HAL_MAX_UL_MU_USERS) {
  1417. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1418. HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv);
  1419. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1420. HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv);
  1421. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1422. HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1423. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1424. HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv);
  1425. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1426. HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv);
  1427. }
  1428. return HAL_TLV_STATUS_MSDU_END;
  1429. case 0:
  1430. return HAL_TLV_STATUS_PPDU_DONE;
  1431. default:
  1432. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1433. unhandled = false;
  1434. else
  1435. unhandled = true;
  1436. break;
  1437. }
  1438. if (!unhandled)
  1439. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1440. "%s TLV type: %d, TLV len:%d %s",
  1441. __func__, tlv_tag, tlv_len,
  1442. unhandled == true ? "unhandled" : "");
  1443. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1444. rx_tlv, tlv_len);
  1445. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1446. }
  1447. /**
  1448. * hal_rx_dump_mpdu_start_tlv_generic_rh: dump RX mpdu_start TLV in structured
  1449. * human readable format.
  1450. * @mpdustart: pointer the rx_attention TLV in pkt.
  1451. * @dbg_level: log level.
  1452. *
  1453. * Return: void
  1454. */
  1455. static inline void hal_rx_dump_mpdu_start_tlv_generic_rh(void *mpdustart,
  1456. uint8_t dbg_level)
  1457. {
  1458. struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
  1459. struct rx_mpdu_info *mpdu_info =
  1460. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  1461. hal_verbose_debug(
  1462. "rx_mpdu_start tlv (1/5) - "
  1463. "rxpcu_mpdu_filter_in_category: %x "
  1464. "sw_frame_group_id: %x "
  1465. "ndp_frame: %x "
  1466. "phy_err: %x "
  1467. "phy_err_during_mpdu_header: %x "
  1468. "protocol_version_err: %x "
  1469. "ast_based_lookup_valid: %x "
  1470. "phy_ppdu_id: %x "
  1471. "ast_index: %x "
  1472. "sw_peer_id: %x "
  1473. "mpdu_frame_control_valid: %x "
  1474. "mpdu_duration_valid: %x "
  1475. "mac_addr_ad1_valid: %x "
  1476. "mac_addr_ad2_valid: %x "
  1477. "mac_addr_ad3_valid: %x "
  1478. "mac_addr_ad4_valid: %x "
  1479. "mpdu_sequence_control_valid: %x "
  1480. "mpdu_qos_control_valid: %x "
  1481. "mpdu_ht_control_valid: %x "
  1482. "frame_encryption_info_valid: %x ",
  1483. mpdu_info->rxpcu_mpdu_filter_in_category,
  1484. mpdu_info->sw_frame_group_id,
  1485. mpdu_info->ndp_frame,
  1486. mpdu_info->phy_err,
  1487. mpdu_info->phy_err_during_mpdu_header,
  1488. mpdu_info->protocol_version_err,
  1489. mpdu_info->ast_based_lookup_valid,
  1490. mpdu_info->phy_ppdu_id,
  1491. mpdu_info->ast_index,
  1492. mpdu_info->sw_peer_id,
  1493. mpdu_info->mpdu_frame_control_valid,
  1494. mpdu_info->mpdu_duration_valid,
  1495. mpdu_info->mac_addr_ad1_valid,
  1496. mpdu_info->mac_addr_ad2_valid,
  1497. mpdu_info->mac_addr_ad3_valid,
  1498. mpdu_info->mac_addr_ad4_valid,
  1499. mpdu_info->mpdu_sequence_control_valid,
  1500. mpdu_info->mpdu_qos_control_valid,
  1501. mpdu_info->mpdu_ht_control_valid,
  1502. mpdu_info->frame_encryption_info_valid);
  1503. hal_verbose_debug(
  1504. "rx_mpdu_start tlv (2/5) - "
  1505. "fr_ds: %x "
  1506. "to_ds: %x "
  1507. "encrypted: %x "
  1508. "mpdu_retry: %x "
  1509. "mpdu_sequence_number: %x "
  1510. "epd_en: %x "
  1511. "all_frames_shall_be_encrypted: %x "
  1512. "encrypt_type: %x "
  1513. "bssid_hit: %x "
  1514. "bssid_number: %x "
  1515. "tid: %x "
  1516. "pn_31_0: %x "
  1517. "pn_63_32: %x "
  1518. "pn_95_64: %x "
  1519. "pn_127_96: %x "
  1520. "peer_meta_data: %x "
  1521. "rxpt_classify_info.reo_destination_indication: %x "
  1522. "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x "
  1523. "rx_reo_queue_desc_addr_31_0: %x ",
  1524. mpdu_info->fr_ds,
  1525. mpdu_info->to_ds,
  1526. mpdu_info->encrypted,
  1527. mpdu_info->mpdu_retry,
  1528. mpdu_info->mpdu_sequence_number,
  1529. mpdu_info->epd_en,
  1530. mpdu_info->all_frames_shall_be_encrypted,
  1531. mpdu_info->encrypt_type,
  1532. mpdu_info->bssid_hit,
  1533. mpdu_info->bssid_number,
  1534. mpdu_info->tid,
  1535. mpdu_info->pn_31_0,
  1536. mpdu_info->pn_63_32,
  1537. mpdu_info->pn_95_64,
  1538. mpdu_info->pn_127_96,
  1539. mpdu_info->peer_meta_data,
  1540. mpdu_info->rxpt_classify_info_details.reo_destination_indication,
  1541. mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
  1542. mpdu_info->rx_reo_queue_desc_addr_31_0);
  1543. hal_verbose_debug(
  1544. "rx_mpdu_start tlv (3/5) - "
  1545. "rx_reo_queue_desc_addr_39_32: %x "
  1546. "receive_queue_number: %x "
  1547. "pre_delim_err_warning: %x "
  1548. "first_delim_err: %x "
  1549. "key_id_octet: %x "
  1550. "new_peer_entry: %x "
  1551. "decrypt_needed: %x "
  1552. "decap_type: %x "
  1553. "rx_insert_vlan_c_tag_padding: %x "
  1554. "rx_insert_vlan_s_tag_padding: %x "
  1555. "strip_vlan_c_tag_decap: %x "
  1556. "strip_vlan_s_tag_decap: %x "
  1557. "pre_delim_count: %x "
  1558. "ampdu_flag: %x "
  1559. "bar_frame: %x "
  1560. "mpdu_length: %x "
  1561. "first_mpdu: %x "
  1562. "mcast_bcast: %x "
  1563. "ast_index_not_found: %x "
  1564. "ast_index_timeout: %x ",
  1565. mpdu_info->rx_reo_queue_desc_addr_39_32,
  1566. mpdu_info->receive_queue_number,
  1567. mpdu_info->pre_delim_err_warning,
  1568. mpdu_info->first_delim_err,
  1569. mpdu_info->key_id_octet,
  1570. mpdu_info->new_peer_entry,
  1571. mpdu_info->decrypt_needed,
  1572. mpdu_info->decap_type,
  1573. mpdu_info->rx_insert_vlan_c_tag_padding,
  1574. mpdu_info->rx_insert_vlan_s_tag_padding,
  1575. mpdu_info->strip_vlan_c_tag_decap,
  1576. mpdu_info->strip_vlan_s_tag_decap,
  1577. mpdu_info->pre_delim_count,
  1578. mpdu_info->ampdu_flag,
  1579. mpdu_info->bar_frame,
  1580. mpdu_info->mpdu_length,
  1581. mpdu_info->first_mpdu,
  1582. mpdu_info->mcast_bcast,
  1583. mpdu_info->ast_index_not_found,
  1584. mpdu_info->ast_index_timeout);
  1585. hal_verbose_debug(
  1586. "rx_mpdu_start tlv (4/5) - "
  1587. "power_mgmt: %x "
  1588. "non_qos: %x "
  1589. "null_data: %x "
  1590. "mgmt_type: %x "
  1591. "ctrl_type: %x "
  1592. "more_data: %x "
  1593. "eosp: %x "
  1594. "fragment_flag: %x "
  1595. "order: %x "
  1596. "u_apsd_trigger: %x "
  1597. "encrypt_required: %x "
  1598. "directed: %x "
  1599. "mpdu_frame_control_field: %x "
  1600. "mpdu_duration_field: %x "
  1601. "mac_addr_ad1_31_0: %x "
  1602. "mac_addr_ad1_47_32: %x "
  1603. "mac_addr_ad2_15_0: %x "
  1604. "mac_addr_ad2_47_16: %x "
  1605. "mac_addr_ad3_31_0: %x "
  1606. "mac_addr_ad3_47_32: %x ",
  1607. mpdu_info->power_mgmt,
  1608. mpdu_info->non_qos,
  1609. mpdu_info->null_data,
  1610. mpdu_info->mgmt_type,
  1611. mpdu_info->ctrl_type,
  1612. mpdu_info->more_data,
  1613. mpdu_info->eosp,
  1614. mpdu_info->fragment_flag,
  1615. mpdu_info->order,
  1616. mpdu_info->u_apsd_trigger,
  1617. mpdu_info->encrypt_required,
  1618. mpdu_info->directed,
  1619. mpdu_info->mpdu_frame_control_field,
  1620. mpdu_info->mpdu_duration_field,
  1621. mpdu_info->mac_addr_ad1_31_0,
  1622. mpdu_info->mac_addr_ad1_47_32,
  1623. mpdu_info->mac_addr_ad2_15_0,
  1624. mpdu_info->mac_addr_ad2_47_16,
  1625. mpdu_info->mac_addr_ad3_31_0,
  1626. mpdu_info->mac_addr_ad3_47_32);
  1627. hal_verbose_debug(
  1628. "rx_mpdu_start tlv (5/5) - "
  1629. "mpdu_sequence_control_field: %x "
  1630. "mac_addr_ad4_31_0: %x "
  1631. "mac_addr_ad4_47_32: %x "
  1632. "mpdu_qos_control_field: %x "
  1633. "mpdu_ht_control_field: %x ",
  1634. mpdu_info->mpdu_sequence_control_field,
  1635. mpdu_info->mac_addr_ad4_31_0,
  1636. mpdu_info->mac_addr_ad4_47_32,
  1637. mpdu_info->mpdu_qos_control_field,
  1638. mpdu_info->mpdu_ht_control_field);
  1639. }
  1640. static void
  1641. hal_tx_set_pcp_tid_map_generic_rh(struct hal_soc *soc, uint8_t *map)
  1642. {
  1643. }
  1644. static void
  1645. hal_tx_update_pcp_tid_generic_rh(struct hal_soc *soc,
  1646. uint8_t pcp, uint8_t tid)
  1647. {
  1648. }
  1649. static void
  1650. hal_tx_update_tidmap_prty_generic_rh(struct hal_soc *soc, uint8_t value)
  1651. {
  1652. }
  1653. /**
  1654. * hal_rx_msdu_packet_metadata_get_generic_rh(): API to get the
  1655. * msdu information from rx_msdu_end TLV
  1656. *
  1657. * @buf: pointer to the start of RX PKT TLV headers
  1658. * @pkt_msdu_metadata: pointer to the msdu metadata
  1659. */
  1660. static void
  1661. hal_rx_msdu_packet_metadata_get_generic_rh(uint8_t *buf,
  1662. void *pkt_msdu_metadata)
  1663. {
  1664. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1665. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1666. struct hal_rx_msdu_metadata *msdu_metadata =
  1667. (struct hal_rx_msdu_metadata *)pkt_msdu_metadata;
  1668. msdu_metadata->l3_hdr_pad =
  1669. HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  1670. msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  1671. msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1672. msdu_metadata->sa_sw_peer_id =
  1673. HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1674. }
  1675. /**
  1676. * hal_rx_msdu_end_offset_get_generic(): API to get the
  1677. * msdu_end structure offset rx_pkt_tlv structure
  1678. *
  1679. * NOTE: API returns offset of msdu_end TLV from structure
  1680. * rx_pkt_tlvs
  1681. */
  1682. static uint32_t hal_rx_msdu_end_offset_get_generic(void)
  1683. {
  1684. return RX_PKT_TLV_OFFSET(msdu_end_tlv);
  1685. }
  1686. /**
  1687. * hal_rx_attn_offset_get_generic(): API to get the
  1688. * msdu_end structure offset rx_pkt_tlv structure
  1689. *
  1690. * NOTE: API returns offset of attn TLV from structure
  1691. * rx_pkt_tlvs
  1692. */
  1693. static uint32_t hal_rx_attn_offset_get_generic(void)
  1694. {
  1695. return RX_PKT_TLV_OFFSET(attn_tlv);
  1696. }
  1697. /**
  1698. * hal_rx_msdu_start_offset_get_generic(): API to get the
  1699. * msdu_start structure offset rx_pkt_tlv structure
  1700. *
  1701. * NOTE: API returns offset of attn TLV from structure
  1702. * rx_pkt_tlvs
  1703. */
  1704. static uint32_t hal_rx_msdu_start_offset_get_generic(void)
  1705. {
  1706. return RX_PKT_TLV_OFFSET(msdu_start_tlv);
  1707. }
  1708. /**
  1709. * hal_rx_mpdu_start_offset_get_generic(): API to get the
  1710. * mpdu_start structure offset rx_pkt_tlv structure
  1711. *
  1712. * NOTE: API returns offset of attn TLV from structure
  1713. * rx_pkt_tlvs
  1714. */
  1715. static uint32_t hal_rx_mpdu_start_offset_get_generic(void)
  1716. {
  1717. return RX_PKT_TLV_OFFSET(mpdu_start_tlv);
  1718. }
  1719. /**
  1720. * hal_rx_mpdu_end_offset_get_generic(): API to get the
  1721. * mpdu_end structure offset rx_pkt_tlv structure
  1722. *
  1723. * NOTE: API returns offset of attn TLV from structure
  1724. * rx_pkt_tlvs
  1725. */
  1726. static uint32_t hal_rx_mpdu_end_offset_get_generic(void)
  1727. {
  1728. return RX_PKT_TLV_OFFSET(mpdu_end_tlv);
  1729. }
  1730. #ifndef NO_RX_PKT_HDR_TLV
  1731. static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
  1732. {
  1733. return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
  1734. }
  1735. #endif
  1736. #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
  1737. /**
  1738. * hal_tx_desc_set_search_type_generic_rh - Set the search type value
  1739. * @desc: Handle to Tx Descriptor
  1740. * @search_type: search type
  1741. * 0 – Normal search
  1742. * 1 – Index based address search
  1743. * 2 – Index based flow search
  1744. *
  1745. * Return: void
  1746. */
  1747. static inline
  1748. void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
  1749. {
  1750. HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
  1751. HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
  1752. }
  1753. #else
  1754. static inline
  1755. void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
  1756. {
  1757. }
  1758. #endif
  1759. #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
  1760. /**
  1761. * hal_tx_desc_set_search_index_generic_rh - Set the search index value
  1762. * @desc: Handle to Tx Descriptor
  1763. * @search_index: The index that will be used for index based address or
  1764. * flow search. The field is valid when 'search_type' is
  1765. * 1 0r 2
  1766. *
  1767. * Return: void
  1768. */
  1769. static inline
  1770. void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
  1771. {
  1772. HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
  1773. HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
  1774. }
  1775. #else
  1776. static inline
  1777. void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
  1778. {
  1779. }
  1780. #endif
  1781. #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
  1782. /**
  1783. * hal_tx_desc_set_cache_set_num_generic_rh - Set the cache-set-num value
  1784. * @desc: Handle to Tx Descriptor
  1785. * @cache_num: Cache set number that should be used to cache the index
  1786. * based search results, for address and flow search.
  1787. * This value should be equal to LSB four bits of the hash value
  1788. * of match data, in case of search index points to an entry
  1789. * which may be used in content based search also. The value can
  1790. * be anything when the entry pointed by search index will not be
  1791. * used for content based search.
  1792. *
  1793. * Return: void
  1794. */
  1795. static inline
  1796. void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
  1797. {
  1798. HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
  1799. HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
  1800. }
  1801. #else
  1802. static inline
  1803. void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
  1804. {
  1805. }
  1806. #endif
  1807. #ifdef WLAN_SUPPORT_RX_FISA
  1808. /**
  1809. * hal_rx_flow_get_tuple_info_rh() - Setup a flow search entry in HW FST
  1810. * @rx_fst: Pointer to the Rx Flow Search Table
  1811. * @hal_hash: HAL 5 tuple hash
  1812. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  1813. *
  1814. * Return: Success/Failure
  1815. */
  1816. static void *
  1817. hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
  1818. uint8_t *flow_tuple_info)
  1819. {
  1820. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1821. void *hal_fse = NULL;
  1822. struct hal_flow_tuple_info *tuple_info
  1823. = (struct hal_flow_tuple_info *)flow_tuple_info;
  1824. hal_fse = (uint8_t *)fst->base_vaddr +
  1825. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  1826. if (!hal_fse || !tuple_info)
  1827. return NULL;
  1828. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  1829. return NULL;
  1830. tuple_info->src_ip_127_96 =
  1831. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1832. RX_FLOW_SEARCH_ENTRY_0,
  1833. SRC_IP_127_96));
  1834. tuple_info->src_ip_95_64 =
  1835. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1836. RX_FLOW_SEARCH_ENTRY_1,
  1837. SRC_IP_95_64));
  1838. tuple_info->src_ip_63_32 =
  1839. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1840. RX_FLOW_SEARCH_ENTRY_2,
  1841. SRC_IP_63_32));
  1842. tuple_info->src_ip_31_0 =
  1843. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1844. RX_FLOW_SEARCH_ENTRY_3,
  1845. SRC_IP_31_0));
  1846. tuple_info->dest_ip_127_96 =
  1847. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1848. RX_FLOW_SEARCH_ENTRY_4,
  1849. DEST_IP_127_96));
  1850. tuple_info->dest_ip_95_64 =
  1851. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1852. RX_FLOW_SEARCH_ENTRY_5,
  1853. DEST_IP_95_64));
  1854. tuple_info->dest_ip_63_32 =
  1855. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1856. RX_FLOW_SEARCH_ENTRY_6,
  1857. DEST_IP_63_32));
  1858. tuple_info->dest_ip_31_0 =
  1859. qdf_ntohl(HAL_GET_FLD(hal_fse,
  1860. RX_FLOW_SEARCH_ENTRY_7,
  1861. DEST_IP_31_0));
  1862. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  1863. RX_FLOW_SEARCH_ENTRY_8,
  1864. DEST_PORT);
  1865. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  1866. RX_FLOW_SEARCH_ENTRY_8,
  1867. SRC_PORT);
  1868. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  1869. RX_FLOW_SEARCH_ENTRY_9,
  1870. L4_PROTOCOL);
  1871. return hal_fse;
  1872. }
  1873. /**
  1874. * hal_rx_flow_delete_entry_rh() - Setup a flow search entry in HW FST
  1875. * @rx_fst: Pointer to the Rx Flow Search Table
  1876. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  1877. *
  1878. * Return: Success/Failure
  1879. */
  1880. static QDF_STATUS
  1881. hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
  1882. {
  1883. uint8_t *fse = (uint8_t *)hal_rx_fse;
  1884. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  1885. return QDF_STATUS_E_NOENT;
  1886. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1887. return QDF_STATUS_SUCCESS;
  1888. }
  1889. /**
  1890. * hal_rx_fst_get_fse_size_rh() - Retrieve the size of each entry
  1891. *
  1892. * Return: size of each entry/flow in Rx FST
  1893. */
  1894. static inline uint32_t
  1895. hal_rx_fst_get_fse_size_rh(void)
  1896. {
  1897. return HAL_RX_FST_ENTRY_SIZE;
  1898. }
  1899. #else
  1900. static inline void *
  1901. hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
  1902. uint8_t *flow_tuple_info)
  1903. {
  1904. return NULL;
  1905. }
  1906. static inline QDF_STATUS
  1907. hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
  1908. {
  1909. return QDF_STATUS_SUCCESS;
  1910. }
  1911. static inline uint32_t
  1912. hal_rx_fst_get_fse_size_rh(void)
  1913. {
  1914. return 0;
  1915. }
  1916. #endif /* WLAN_SUPPORT_RX_FISA */
  1917. /**
  1918. * hal_rx_get_frame_ctrl_field_rh(): Function to retrieve frame control field
  1919. *
  1920. * @buf: Network buffer
  1921. *
  1922. * Returns: rx more fragment bit
  1923. */
  1924. static uint16_t hal_rx_get_frame_ctrl_field_rh(uint8_t *buf)
  1925. {
  1926. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1927. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  1928. uint16_t frame_ctrl = 0;
  1929. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  1930. return frame_ctrl;
  1931. }
  1932. #endif /* _HAL_RH_GENERIC_API_H_ */