rx_reo_queue_ext.h 79 KB

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  1. /*
  2. * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RX_REO_QUEUE_EXT_H_
  17. #define _RX_REO_QUEUE_EXT_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #include "uniform_descriptor_header.h"
  21. #include "rx_mpdu_link_ptr.h"
  22. // ################ START SUMMARY #################
  23. //
  24. // Dword Fields
  25. // 0 struct uniform_descriptor_header descriptor_header;
  26. // 1 reserved_1a[31:0]
  27. // 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0;
  28. // 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1;
  29. // 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2;
  30. // 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3;
  31. // 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4;
  32. // 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5;
  33. // 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6;
  34. // 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7;
  35. // 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8;
  36. // 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9;
  37. // 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10;
  38. // 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11;
  39. // 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12;
  40. // 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13;
  41. // 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14;
  42. //
  43. // ################ END SUMMARY #################
  44. #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
  45. struct rx_reo_queue_ext {
  46. struct uniform_descriptor_header descriptor_header;
  47. uint32_t reserved_1a : 32; //[31:0]
  48. struct rx_mpdu_link_ptr mpdu_link_pointer_0;
  49. struct rx_mpdu_link_ptr mpdu_link_pointer_1;
  50. struct rx_mpdu_link_ptr mpdu_link_pointer_2;
  51. struct rx_mpdu_link_ptr mpdu_link_pointer_3;
  52. struct rx_mpdu_link_ptr mpdu_link_pointer_4;
  53. struct rx_mpdu_link_ptr mpdu_link_pointer_5;
  54. struct rx_mpdu_link_ptr mpdu_link_pointer_6;
  55. struct rx_mpdu_link_ptr mpdu_link_pointer_7;
  56. struct rx_mpdu_link_ptr mpdu_link_pointer_8;
  57. struct rx_mpdu_link_ptr mpdu_link_pointer_9;
  58. struct rx_mpdu_link_ptr mpdu_link_pointer_10;
  59. struct rx_mpdu_link_ptr mpdu_link_pointer_11;
  60. struct rx_mpdu_link_ptr mpdu_link_pointer_12;
  61. struct rx_mpdu_link_ptr mpdu_link_pointer_13;
  62. struct rx_mpdu_link_ptr mpdu_link_pointer_14;
  63. };
  64. /*
  65. struct uniform_descriptor_header descriptor_header
  66. Details about which module owns this struct.
  67. Note that sub field Buffer_type shall be set to
  68. Receive_REO_queue_ext_descriptor
  69. reserved_1a
  70. <legal 0>
  71. struct rx_mpdu_link_ptr mpdu_link_pointer_0
  72. Consumer: REO
  73. Producer: REO
  74. Pointer to the next MPDU_link descriptor in the MPDU
  75. queue
  76. struct rx_mpdu_link_ptr mpdu_link_pointer_1
  77. Consumer: REO
  78. Producer: REO
  79. Pointer to the next MPDU_link descriptor in the MPDU
  80. queue
  81. struct rx_mpdu_link_ptr mpdu_link_pointer_2
  82. Consumer: REO
  83. Producer: REO
  84. Pointer to the next MPDU_link descriptor in the MPDU
  85. queue
  86. struct rx_mpdu_link_ptr mpdu_link_pointer_3
  87. Consumer: REO
  88. Producer: REO
  89. Pointer to the next MPDU_link descriptor in the MPDU
  90. queue
  91. struct rx_mpdu_link_ptr mpdu_link_pointer_4
  92. Consumer: REO
  93. Producer: REO
  94. Pointer to the next MPDU_link descriptor in the MPDU
  95. queue
  96. struct rx_mpdu_link_ptr mpdu_link_pointer_5
  97. Consumer: REO
  98. Producer: REO
  99. Pointer to the next MPDU_link descriptor in the MPDU
  100. queue
  101. struct rx_mpdu_link_ptr mpdu_link_pointer_6
  102. Consumer: REO
  103. Producer: REO
  104. Pointer to the next MPDU_link descriptor in the MPDU
  105. queue
  106. struct rx_mpdu_link_ptr mpdu_link_pointer_7
  107. Consumer: REO
  108. Producer: REO
  109. Pointer to the next MPDU_link descriptor in the MPDU
  110. queue
  111. struct rx_mpdu_link_ptr mpdu_link_pointer_8
  112. Consumer: REO
  113. Producer: REO
  114. Pointer to the next MPDU_link descriptor in the MPDU
  115. queue
  116. struct rx_mpdu_link_ptr mpdu_link_pointer_9
  117. Consumer: REO
  118. Producer: REO
  119. Pointer to the next MPDU_link descriptor in the MPDU
  120. queue
  121. struct rx_mpdu_link_ptr mpdu_link_pointer_10
  122. Consumer: REO
  123. Producer: REO
  124. Pointer to the next MPDU_link descriptor in the MPDU
  125. queue
  126. struct rx_mpdu_link_ptr mpdu_link_pointer_11
  127. Consumer: REO
  128. Producer: REO
  129. Pointer to the next MPDU_link descriptor in the MPDU
  130. queue
  131. struct rx_mpdu_link_ptr mpdu_link_pointer_12
  132. Consumer: REO
  133. Producer: REO
  134. Pointer to the next MPDU_link descriptor in the MPDU
  135. queue
  136. struct rx_mpdu_link_ptr mpdu_link_pointer_13
  137. Consumer: REO
  138. Producer: REO
  139. Pointer to the next MPDU_link descriptor in the MPDU
  140. queue
  141. struct rx_mpdu_link_ptr mpdu_link_pointer_14
  142. Consumer: REO
  143. Producer: REO
  144. Pointer to the next MPDU_link descriptor in the MPDU
  145. queue
  146. */
  147. /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */
  148. /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER
  149. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  150. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  151. The owner of this data structure:
  152. <enum 0 WBM_owned> Buffer Manager currently owns this
  153. data structure.
  154. <enum 1 SW_OR_FW_owned> Software of FW currently owns
  155. this data structure.
  156. <enum 2 TQM_owned> Transmit Queue Manager currently owns
  157. this data structure.
  158. <enum 3 RXDMA_owned> Receive DMA currently owns this
  159. data structure.
  160. <enum 4 REO_owned> Reorder currently owns this data
  161. structure.
  162. <enum 5 SWITCH_owned> SWITCH currently owns this data
  163. structure.
  164. <legal 0-5>
  165. */
  166. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
  167. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0
  168. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
  169. /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE
  170. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  171. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  172. Field describing what contents format is of this
  173. descriptor
  174. <enum 0 Transmit_MSDU_Link_descriptor >
  175. <enum 1 Transmit_MPDU_Link_descriptor >
  176. <enum 2 Transmit_MPDU_Queue_head_descriptor>
  177. <enum 3 Transmit_MPDU_Queue_ext_descriptor>
  178. <enum 4 Transmit_flow_descriptor>
  179. <enum 5 Transmit_buffer > NOT TO BE USED:
  180. <enum 6 Receive_MSDU_Link_descriptor >
  181. <enum 7 Receive_MPDU_Link_descriptor >
  182. <enum 8 Receive_REO_queue_descriptor >
  183. <enum 9 Receive_REO_queue_ext_descriptor >
  184. <enum 10 Receive_buffer >
  185. <enum 11 Idle_link_list_entry>
  186. <legal 0-11>
  187. */
  188. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
  189. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
  190. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
  191. /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A
  192. <legal 0>
  193. */
  194. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
  195. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
  196. #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
  197. /* Description RX_REO_QUEUE_EXT_1_RESERVED_1A
  198. <legal 0>
  199. */
  200. #define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004
  201. #define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0
  202. #define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff
  203. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */
  204. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  205. /* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  206. Address (lower 32 bits) of the MSDU buffer OR
  207. MSDU_EXTENSION descriptor OR Link Descriptor
  208. In case of 'NULL' pointer, this field is set to 0
  209. <legal all>
  210. */
  211. #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
  212. #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  213. #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  214. /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  215. Address (upper 8 bits) of the MSDU buffer OR
  216. MSDU_EXTENSION descriptor OR Link Descriptor
  217. In case of 'NULL' pointer, this field is set to 0
  218. <legal all>
  219. */
  220. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
  221. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  222. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  223. /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  224. Consumer: WBM
  225. Producer: SW/FW
  226. In case of 'NULL' pointer, this field is set to 0
  227. Indicates to which buffer manager the buffer OR
  228. MSDU_EXTENSION descriptor OR link descriptor that is being
  229. pointed to shall be returned after the frame has been
  230. processed. It is used by WBM for routing purposes.
  231. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  232. to the WMB buffer idle list
  233. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  234. returned to the WMB idle link descriptor idle list
  235. <enum 2 FW_BM> This buffer shall be returned to the FW
  236. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  237. ring 0
  238. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  239. ring 1
  240. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  241. ring 2
  242. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  243. ring 3
  244. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  245. ring 4
  246. <legal all>
  247. */
  248. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
  249. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  250. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  251. /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  252. Cookie field exclusively used by SW.
  253. In case of 'NULL' pointer, this field is set to 0
  254. HW ignores the contents, accept that it passes the
  255. programmed value on to other descriptors together with the
  256. physical address
  257. Field can be used by SW to for example associate the
  258. buffers physical address with the virtual address
  259. The bit definitions as used by SW are within SW HLD
  260. specification
  261. NOTE:
  262. The three most significant bits can have a special
  263. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  264. STRUCT, and field transmit_bw_restriction is set
  265. In case of NON punctured transmission:
  266. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  267. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  268. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  269. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  270. In case of punctured transmission:
  271. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  272. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  273. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  274. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  275. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  276. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  277. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  278. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  279. Note: a punctured transmission is indicated by the
  280. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  281. TLV
  282. <legal all>
  283. */
  284. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
  285. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  286. #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  287. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */
  288. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  289. /* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  290. Address (lower 32 bits) of the MSDU buffer OR
  291. MSDU_EXTENSION descriptor OR Link Descriptor
  292. In case of 'NULL' pointer, this field is set to 0
  293. <legal all>
  294. */
  295. #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
  296. #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  297. #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  298. /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  299. Address (upper 8 bits) of the MSDU buffer OR
  300. MSDU_EXTENSION descriptor OR Link Descriptor
  301. In case of 'NULL' pointer, this field is set to 0
  302. <legal all>
  303. */
  304. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
  305. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  306. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  307. /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  308. Consumer: WBM
  309. Producer: SW/FW
  310. In case of 'NULL' pointer, this field is set to 0
  311. Indicates to which buffer manager the buffer OR
  312. MSDU_EXTENSION descriptor OR link descriptor that is being
  313. pointed to shall be returned after the frame has been
  314. processed. It is used by WBM for routing purposes.
  315. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  316. to the WMB buffer idle list
  317. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  318. returned to the WMB idle link descriptor idle list
  319. <enum 2 FW_BM> This buffer shall be returned to the FW
  320. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  321. ring 0
  322. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  323. ring 1
  324. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  325. ring 2
  326. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  327. ring 3
  328. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  329. ring 4
  330. <legal all>
  331. */
  332. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
  333. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  334. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  335. /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  336. Cookie field exclusively used by SW.
  337. In case of 'NULL' pointer, this field is set to 0
  338. HW ignores the contents, accept that it passes the
  339. programmed value on to other descriptors together with the
  340. physical address
  341. Field can be used by SW to for example associate the
  342. buffers physical address with the virtual address
  343. The bit definitions as used by SW are within SW HLD
  344. specification
  345. NOTE:
  346. The three most significant bits can have a special
  347. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  348. STRUCT, and field transmit_bw_restriction is set
  349. In case of NON punctured transmission:
  350. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  351. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  352. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  353. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  354. In case of punctured transmission:
  355. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  356. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  357. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  358. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  359. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  360. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  361. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  362. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  363. Note: a punctured transmission is indicated by the
  364. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  365. TLV
  366. <legal all>
  367. */
  368. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
  369. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  370. #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  371. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */
  372. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  373. /* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  374. Address (lower 32 bits) of the MSDU buffer OR
  375. MSDU_EXTENSION descriptor OR Link Descriptor
  376. In case of 'NULL' pointer, this field is set to 0
  377. <legal all>
  378. */
  379. #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
  380. #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  381. #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  382. /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  383. Address (upper 8 bits) of the MSDU buffer OR
  384. MSDU_EXTENSION descriptor OR Link Descriptor
  385. In case of 'NULL' pointer, this field is set to 0
  386. <legal all>
  387. */
  388. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
  389. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  390. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  391. /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  392. Consumer: WBM
  393. Producer: SW/FW
  394. In case of 'NULL' pointer, this field is set to 0
  395. Indicates to which buffer manager the buffer OR
  396. MSDU_EXTENSION descriptor OR link descriptor that is being
  397. pointed to shall be returned after the frame has been
  398. processed. It is used by WBM for routing purposes.
  399. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  400. to the WMB buffer idle list
  401. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  402. returned to the WMB idle link descriptor idle list
  403. <enum 2 FW_BM> This buffer shall be returned to the FW
  404. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  405. ring 0
  406. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  407. ring 1
  408. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  409. ring 2
  410. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  411. ring 3
  412. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  413. ring 4
  414. <legal all>
  415. */
  416. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
  417. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  418. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  419. /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  420. Cookie field exclusively used by SW.
  421. In case of 'NULL' pointer, this field is set to 0
  422. HW ignores the contents, accept that it passes the
  423. programmed value on to other descriptors together with the
  424. physical address
  425. Field can be used by SW to for example associate the
  426. buffers physical address with the virtual address
  427. The bit definitions as used by SW are within SW HLD
  428. specification
  429. NOTE:
  430. The three most significant bits can have a special
  431. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  432. STRUCT, and field transmit_bw_restriction is set
  433. In case of NON punctured transmission:
  434. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  435. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  436. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  437. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  438. In case of punctured transmission:
  439. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  440. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  441. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  442. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  443. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  444. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  445. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  446. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  447. Note: a punctured transmission is indicated by the
  448. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  449. TLV
  450. <legal all>
  451. */
  452. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
  453. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  454. #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  455. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */
  456. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  457. /* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  458. Address (lower 32 bits) of the MSDU buffer OR
  459. MSDU_EXTENSION descriptor OR Link Descriptor
  460. In case of 'NULL' pointer, this field is set to 0
  461. <legal all>
  462. */
  463. #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
  464. #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  465. #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  466. /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  467. Address (upper 8 bits) of the MSDU buffer OR
  468. MSDU_EXTENSION descriptor OR Link Descriptor
  469. In case of 'NULL' pointer, this field is set to 0
  470. <legal all>
  471. */
  472. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
  473. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  474. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  475. /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  476. Consumer: WBM
  477. Producer: SW/FW
  478. In case of 'NULL' pointer, this field is set to 0
  479. Indicates to which buffer manager the buffer OR
  480. MSDU_EXTENSION descriptor OR link descriptor that is being
  481. pointed to shall be returned after the frame has been
  482. processed. It is used by WBM for routing purposes.
  483. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  484. to the WMB buffer idle list
  485. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  486. returned to the WMB idle link descriptor idle list
  487. <enum 2 FW_BM> This buffer shall be returned to the FW
  488. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  489. ring 0
  490. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  491. ring 1
  492. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  493. ring 2
  494. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  495. ring 3
  496. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  497. ring 4
  498. <legal all>
  499. */
  500. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
  501. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  502. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  503. /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  504. Cookie field exclusively used by SW.
  505. In case of 'NULL' pointer, this field is set to 0
  506. HW ignores the contents, accept that it passes the
  507. programmed value on to other descriptors together with the
  508. physical address
  509. Field can be used by SW to for example associate the
  510. buffers physical address with the virtual address
  511. The bit definitions as used by SW are within SW HLD
  512. specification
  513. NOTE:
  514. The three most significant bits can have a special
  515. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  516. STRUCT, and field transmit_bw_restriction is set
  517. In case of NON punctured transmission:
  518. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  519. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  520. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  521. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  522. In case of punctured transmission:
  523. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  524. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  525. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  526. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  527. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  528. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  529. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  530. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  531. Note: a punctured transmission is indicated by the
  532. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  533. TLV
  534. <legal all>
  535. */
  536. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
  537. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  538. #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  539. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */
  540. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  541. /* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  542. Address (lower 32 bits) of the MSDU buffer OR
  543. MSDU_EXTENSION descriptor OR Link Descriptor
  544. In case of 'NULL' pointer, this field is set to 0
  545. <legal all>
  546. */
  547. #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
  548. #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  549. #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  550. /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  551. Address (upper 8 bits) of the MSDU buffer OR
  552. MSDU_EXTENSION descriptor OR Link Descriptor
  553. In case of 'NULL' pointer, this field is set to 0
  554. <legal all>
  555. */
  556. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
  557. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  558. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  559. /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  560. Consumer: WBM
  561. Producer: SW/FW
  562. In case of 'NULL' pointer, this field is set to 0
  563. Indicates to which buffer manager the buffer OR
  564. MSDU_EXTENSION descriptor OR link descriptor that is being
  565. pointed to shall be returned after the frame has been
  566. processed. It is used by WBM for routing purposes.
  567. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  568. to the WMB buffer idle list
  569. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  570. returned to the WMB idle link descriptor idle list
  571. <enum 2 FW_BM> This buffer shall be returned to the FW
  572. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  573. ring 0
  574. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  575. ring 1
  576. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  577. ring 2
  578. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  579. ring 3
  580. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  581. ring 4
  582. <legal all>
  583. */
  584. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
  585. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  586. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  587. /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  588. Cookie field exclusively used by SW.
  589. In case of 'NULL' pointer, this field is set to 0
  590. HW ignores the contents, accept that it passes the
  591. programmed value on to other descriptors together with the
  592. physical address
  593. Field can be used by SW to for example associate the
  594. buffers physical address with the virtual address
  595. The bit definitions as used by SW are within SW HLD
  596. specification
  597. NOTE:
  598. The three most significant bits can have a special
  599. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  600. STRUCT, and field transmit_bw_restriction is set
  601. In case of NON punctured transmission:
  602. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  603. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  604. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  605. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  606. In case of punctured transmission:
  607. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  608. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  609. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  610. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  611. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  612. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  613. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  614. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  615. Note: a punctured transmission is indicated by the
  616. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  617. TLV
  618. <legal all>
  619. */
  620. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
  621. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  622. #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  623. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */
  624. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  625. /* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  626. Address (lower 32 bits) of the MSDU buffer OR
  627. MSDU_EXTENSION descriptor OR Link Descriptor
  628. In case of 'NULL' pointer, this field is set to 0
  629. <legal all>
  630. */
  631. #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
  632. #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  633. #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  634. /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  635. Address (upper 8 bits) of the MSDU buffer OR
  636. MSDU_EXTENSION descriptor OR Link Descriptor
  637. In case of 'NULL' pointer, this field is set to 0
  638. <legal all>
  639. */
  640. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
  641. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  642. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  643. /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  644. Consumer: WBM
  645. Producer: SW/FW
  646. In case of 'NULL' pointer, this field is set to 0
  647. Indicates to which buffer manager the buffer OR
  648. MSDU_EXTENSION descriptor OR link descriptor that is being
  649. pointed to shall be returned after the frame has been
  650. processed. It is used by WBM for routing purposes.
  651. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  652. to the WMB buffer idle list
  653. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  654. returned to the WMB idle link descriptor idle list
  655. <enum 2 FW_BM> This buffer shall be returned to the FW
  656. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  657. ring 0
  658. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  659. ring 1
  660. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  661. ring 2
  662. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  663. ring 3
  664. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  665. ring 4
  666. <legal all>
  667. */
  668. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
  669. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  670. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  671. /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  672. Cookie field exclusively used by SW.
  673. In case of 'NULL' pointer, this field is set to 0
  674. HW ignores the contents, accept that it passes the
  675. programmed value on to other descriptors together with the
  676. physical address
  677. Field can be used by SW to for example associate the
  678. buffers physical address with the virtual address
  679. The bit definitions as used by SW are within SW HLD
  680. specification
  681. NOTE:
  682. The three most significant bits can have a special
  683. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  684. STRUCT, and field transmit_bw_restriction is set
  685. In case of NON punctured transmission:
  686. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  687. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  688. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  689. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  690. In case of punctured transmission:
  691. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  692. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  693. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  694. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  695. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  696. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  697. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  698. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  699. Note: a punctured transmission is indicated by the
  700. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  701. TLV
  702. <legal all>
  703. */
  704. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
  705. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  706. #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  707. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */
  708. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  709. /* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  710. Address (lower 32 bits) of the MSDU buffer OR
  711. MSDU_EXTENSION descriptor OR Link Descriptor
  712. In case of 'NULL' pointer, this field is set to 0
  713. <legal all>
  714. */
  715. #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
  716. #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  717. #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  718. /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  719. Address (upper 8 bits) of the MSDU buffer OR
  720. MSDU_EXTENSION descriptor OR Link Descriptor
  721. In case of 'NULL' pointer, this field is set to 0
  722. <legal all>
  723. */
  724. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
  725. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  726. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  727. /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  728. Consumer: WBM
  729. Producer: SW/FW
  730. In case of 'NULL' pointer, this field is set to 0
  731. Indicates to which buffer manager the buffer OR
  732. MSDU_EXTENSION descriptor OR link descriptor that is being
  733. pointed to shall be returned after the frame has been
  734. processed. It is used by WBM for routing purposes.
  735. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  736. to the WMB buffer idle list
  737. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  738. returned to the WMB idle link descriptor idle list
  739. <enum 2 FW_BM> This buffer shall be returned to the FW
  740. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  741. ring 0
  742. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  743. ring 1
  744. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  745. ring 2
  746. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  747. ring 3
  748. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  749. ring 4
  750. <legal all>
  751. */
  752. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
  753. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  754. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  755. /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  756. Cookie field exclusively used by SW.
  757. In case of 'NULL' pointer, this field is set to 0
  758. HW ignores the contents, accept that it passes the
  759. programmed value on to other descriptors together with the
  760. physical address
  761. Field can be used by SW to for example associate the
  762. buffers physical address with the virtual address
  763. The bit definitions as used by SW are within SW HLD
  764. specification
  765. NOTE:
  766. The three most significant bits can have a special
  767. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  768. STRUCT, and field transmit_bw_restriction is set
  769. In case of NON punctured transmission:
  770. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  771. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  772. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  773. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  774. In case of punctured transmission:
  775. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  776. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  777. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  778. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  779. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  780. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  781. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  782. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  783. Note: a punctured transmission is indicated by the
  784. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  785. TLV
  786. <legal all>
  787. */
  788. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
  789. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  790. #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  791. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */
  792. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  793. /* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  794. Address (lower 32 bits) of the MSDU buffer OR
  795. MSDU_EXTENSION descriptor OR Link Descriptor
  796. In case of 'NULL' pointer, this field is set to 0
  797. <legal all>
  798. */
  799. #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
  800. #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  801. #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  802. /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  803. Address (upper 8 bits) of the MSDU buffer OR
  804. MSDU_EXTENSION descriptor OR Link Descriptor
  805. In case of 'NULL' pointer, this field is set to 0
  806. <legal all>
  807. */
  808. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
  809. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  810. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  811. /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  812. Consumer: WBM
  813. Producer: SW/FW
  814. In case of 'NULL' pointer, this field is set to 0
  815. Indicates to which buffer manager the buffer OR
  816. MSDU_EXTENSION descriptor OR link descriptor that is being
  817. pointed to shall be returned after the frame has been
  818. processed. It is used by WBM for routing purposes.
  819. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  820. to the WMB buffer idle list
  821. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  822. returned to the WMB idle link descriptor idle list
  823. <enum 2 FW_BM> This buffer shall be returned to the FW
  824. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  825. ring 0
  826. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  827. ring 1
  828. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  829. ring 2
  830. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  831. ring 3
  832. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  833. ring 4
  834. <legal all>
  835. */
  836. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
  837. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  838. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  839. /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  840. Cookie field exclusively used by SW.
  841. In case of 'NULL' pointer, this field is set to 0
  842. HW ignores the contents, accept that it passes the
  843. programmed value on to other descriptors together with the
  844. physical address
  845. Field can be used by SW to for example associate the
  846. buffers physical address with the virtual address
  847. The bit definitions as used by SW are within SW HLD
  848. specification
  849. NOTE:
  850. The three most significant bits can have a special
  851. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  852. STRUCT, and field transmit_bw_restriction is set
  853. In case of NON punctured transmission:
  854. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  855. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  856. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  857. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  858. In case of punctured transmission:
  859. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  860. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  861. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  862. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  863. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  864. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  865. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  866. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  867. Note: a punctured transmission is indicated by the
  868. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  869. TLV
  870. <legal all>
  871. */
  872. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
  873. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  874. #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  875. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */
  876. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  877. /* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  878. Address (lower 32 bits) of the MSDU buffer OR
  879. MSDU_EXTENSION descriptor OR Link Descriptor
  880. In case of 'NULL' pointer, this field is set to 0
  881. <legal all>
  882. */
  883. #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
  884. #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  885. #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  886. /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  887. Address (upper 8 bits) of the MSDU buffer OR
  888. MSDU_EXTENSION descriptor OR Link Descriptor
  889. In case of 'NULL' pointer, this field is set to 0
  890. <legal all>
  891. */
  892. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
  893. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  894. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  895. /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  896. Consumer: WBM
  897. Producer: SW/FW
  898. In case of 'NULL' pointer, this field is set to 0
  899. Indicates to which buffer manager the buffer OR
  900. MSDU_EXTENSION descriptor OR link descriptor that is being
  901. pointed to shall be returned after the frame has been
  902. processed. It is used by WBM for routing purposes.
  903. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  904. to the WMB buffer idle list
  905. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  906. returned to the WMB idle link descriptor idle list
  907. <enum 2 FW_BM> This buffer shall be returned to the FW
  908. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  909. ring 0
  910. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  911. ring 1
  912. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  913. ring 2
  914. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  915. ring 3
  916. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  917. ring 4
  918. <legal all>
  919. */
  920. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
  921. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  922. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  923. /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  924. Cookie field exclusively used by SW.
  925. In case of 'NULL' pointer, this field is set to 0
  926. HW ignores the contents, accept that it passes the
  927. programmed value on to other descriptors together with the
  928. physical address
  929. Field can be used by SW to for example associate the
  930. buffers physical address with the virtual address
  931. The bit definitions as used by SW are within SW HLD
  932. specification
  933. NOTE:
  934. The three most significant bits can have a special
  935. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  936. STRUCT, and field transmit_bw_restriction is set
  937. In case of NON punctured transmission:
  938. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  939. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  940. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  941. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  942. In case of punctured transmission:
  943. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  944. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  945. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  946. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  947. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  948. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  949. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  950. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  951. Note: a punctured transmission is indicated by the
  952. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  953. TLV
  954. <legal all>
  955. */
  956. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
  957. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  958. #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  959. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */
  960. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  961. /* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  962. Address (lower 32 bits) of the MSDU buffer OR
  963. MSDU_EXTENSION descriptor OR Link Descriptor
  964. In case of 'NULL' pointer, this field is set to 0
  965. <legal all>
  966. */
  967. #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
  968. #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  969. #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  970. /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  971. Address (upper 8 bits) of the MSDU buffer OR
  972. MSDU_EXTENSION descriptor OR Link Descriptor
  973. In case of 'NULL' pointer, this field is set to 0
  974. <legal all>
  975. */
  976. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
  977. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  978. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  979. /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  980. Consumer: WBM
  981. Producer: SW/FW
  982. In case of 'NULL' pointer, this field is set to 0
  983. Indicates to which buffer manager the buffer OR
  984. MSDU_EXTENSION descriptor OR link descriptor that is being
  985. pointed to shall be returned after the frame has been
  986. processed. It is used by WBM for routing purposes.
  987. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  988. to the WMB buffer idle list
  989. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  990. returned to the WMB idle link descriptor idle list
  991. <enum 2 FW_BM> This buffer shall be returned to the FW
  992. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  993. ring 0
  994. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  995. ring 1
  996. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  997. ring 2
  998. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  999. ring 3
  1000. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1001. ring 4
  1002. <legal all>
  1003. */
  1004. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
  1005. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1006. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1007. /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1008. Cookie field exclusively used by SW.
  1009. In case of 'NULL' pointer, this field is set to 0
  1010. HW ignores the contents, accept that it passes the
  1011. programmed value on to other descriptors together with the
  1012. physical address
  1013. Field can be used by SW to for example associate the
  1014. buffers physical address with the virtual address
  1015. The bit definitions as used by SW are within SW HLD
  1016. specification
  1017. NOTE:
  1018. The three most significant bits can have a special
  1019. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1020. STRUCT, and field transmit_bw_restriction is set
  1021. In case of NON punctured transmission:
  1022. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1023. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1024. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1025. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1026. In case of punctured transmission:
  1027. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1028. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1029. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1030. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1031. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1032. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1033. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1034. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1035. Note: a punctured transmission is indicated by the
  1036. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1037. TLV
  1038. <legal all>
  1039. */
  1040. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
  1041. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1042. #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1043. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */
  1044. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  1045. /* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  1046. Address (lower 32 bits) of the MSDU buffer OR
  1047. MSDU_EXTENSION descriptor OR Link Descriptor
  1048. In case of 'NULL' pointer, this field is set to 0
  1049. <legal all>
  1050. */
  1051. #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
  1052. #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  1053. #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  1054. /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  1055. Address (upper 8 bits) of the MSDU buffer OR
  1056. MSDU_EXTENSION descriptor OR Link Descriptor
  1057. In case of 'NULL' pointer, this field is set to 0
  1058. <legal all>
  1059. */
  1060. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
  1061. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  1062. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  1063. /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  1064. Consumer: WBM
  1065. Producer: SW/FW
  1066. In case of 'NULL' pointer, this field is set to 0
  1067. Indicates to which buffer manager the buffer OR
  1068. MSDU_EXTENSION descriptor OR link descriptor that is being
  1069. pointed to shall be returned after the frame has been
  1070. processed. It is used by WBM for routing purposes.
  1071. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  1072. to the WMB buffer idle list
  1073. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  1074. returned to the WMB idle link descriptor idle list
  1075. <enum 2 FW_BM> This buffer shall be returned to the FW
  1076. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  1077. ring 0
  1078. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  1079. ring 1
  1080. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  1081. ring 2
  1082. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  1083. ring 3
  1084. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1085. ring 4
  1086. <legal all>
  1087. */
  1088. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
  1089. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1090. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1091. /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1092. Cookie field exclusively used by SW.
  1093. In case of 'NULL' pointer, this field is set to 0
  1094. HW ignores the contents, accept that it passes the
  1095. programmed value on to other descriptors together with the
  1096. physical address
  1097. Field can be used by SW to for example associate the
  1098. buffers physical address with the virtual address
  1099. The bit definitions as used by SW are within SW HLD
  1100. specification
  1101. NOTE:
  1102. The three most significant bits can have a special
  1103. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1104. STRUCT, and field transmit_bw_restriction is set
  1105. In case of NON punctured transmission:
  1106. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1107. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1108. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1109. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1110. In case of punctured transmission:
  1111. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1112. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1113. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1114. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1115. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1116. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1117. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1118. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1119. Note: a punctured transmission is indicated by the
  1120. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1121. TLV
  1122. <legal all>
  1123. */
  1124. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
  1125. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1126. #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1127. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */
  1128. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  1129. /* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  1130. Address (lower 32 bits) of the MSDU buffer OR
  1131. MSDU_EXTENSION descriptor OR Link Descriptor
  1132. In case of 'NULL' pointer, this field is set to 0
  1133. <legal all>
  1134. */
  1135. #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
  1136. #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  1137. #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  1138. /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  1139. Address (upper 8 bits) of the MSDU buffer OR
  1140. MSDU_EXTENSION descriptor OR Link Descriptor
  1141. In case of 'NULL' pointer, this field is set to 0
  1142. <legal all>
  1143. */
  1144. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
  1145. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  1146. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  1147. /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  1148. Consumer: WBM
  1149. Producer: SW/FW
  1150. In case of 'NULL' pointer, this field is set to 0
  1151. Indicates to which buffer manager the buffer OR
  1152. MSDU_EXTENSION descriptor OR link descriptor that is being
  1153. pointed to shall be returned after the frame has been
  1154. processed. It is used by WBM for routing purposes.
  1155. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  1156. to the WMB buffer idle list
  1157. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  1158. returned to the WMB idle link descriptor idle list
  1159. <enum 2 FW_BM> This buffer shall be returned to the FW
  1160. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  1161. ring 0
  1162. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  1163. ring 1
  1164. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  1165. ring 2
  1166. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  1167. ring 3
  1168. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1169. ring 4
  1170. <legal all>
  1171. */
  1172. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
  1173. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1174. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1175. /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1176. Cookie field exclusively used by SW.
  1177. In case of 'NULL' pointer, this field is set to 0
  1178. HW ignores the contents, accept that it passes the
  1179. programmed value on to other descriptors together with the
  1180. physical address
  1181. Field can be used by SW to for example associate the
  1182. buffers physical address with the virtual address
  1183. The bit definitions as used by SW are within SW HLD
  1184. specification
  1185. NOTE:
  1186. The three most significant bits can have a special
  1187. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1188. STRUCT, and field transmit_bw_restriction is set
  1189. In case of NON punctured transmission:
  1190. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1191. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1192. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1193. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1194. In case of punctured transmission:
  1195. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1196. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1197. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1198. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1199. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1200. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1201. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1202. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1203. Note: a punctured transmission is indicated by the
  1204. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1205. TLV
  1206. <legal all>
  1207. */
  1208. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
  1209. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1210. #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1211. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */
  1212. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  1213. /* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  1214. Address (lower 32 bits) of the MSDU buffer OR
  1215. MSDU_EXTENSION descriptor OR Link Descriptor
  1216. In case of 'NULL' pointer, this field is set to 0
  1217. <legal all>
  1218. */
  1219. #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
  1220. #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  1221. #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  1222. /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  1223. Address (upper 8 bits) of the MSDU buffer OR
  1224. MSDU_EXTENSION descriptor OR Link Descriptor
  1225. In case of 'NULL' pointer, this field is set to 0
  1226. <legal all>
  1227. */
  1228. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
  1229. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  1230. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  1231. /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  1232. Consumer: WBM
  1233. Producer: SW/FW
  1234. In case of 'NULL' pointer, this field is set to 0
  1235. Indicates to which buffer manager the buffer OR
  1236. MSDU_EXTENSION descriptor OR link descriptor that is being
  1237. pointed to shall be returned after the frame has been
  1238. processed. It is used by WBM for routing purposes.
  1239. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  1240. to the WMB buffer idle list
  1241. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  1242. returned to the WMB idle link descriptor idle list
  1243. <enum 2 FW_BM> This buffer shall be returned to the FW
  1244. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  1245. ring 0
  1246. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  1247. ring 1
  1248. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  1249. ring 2
  1250. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  1251. ring 3
  1252. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1253. ring 4
  1254. <legal all>
  1255. */
  1256. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
  1257. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1258. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1259. /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1260. Cookie field exclusively used by SW.
  1261. In case of 'NULL' pointer, this field is set to 0
  1262. HW ignores the contents, accept that it passes the
  1263. programmed value on to other descriptors together with the
  1264. physical address
  1265. Field can be used by SW to for example associate the
  1266. buffers physical address with the virtual address
  1267. The bit definitions as used by SW are within SW HLD
  1268. specification
  1269. NOTE:
  1270. The three most significant bits can have a special
  1271. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1272. STRUCT, and field transmit_bw_restriction is set
  1273. In case of NON punctured transmission:
  1274. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1275. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1276. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1277. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1278. In case of punctured transmission:
  1279. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1280. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1281. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1282. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1283. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1284. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1285. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1286. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1287. Note: a punctured transmission is indicated by the
  1288. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1289. TLV
  1290. <legal all>
  1291. */
  1292. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
  1293. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1294. #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1295. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */
  1296. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  1297. /* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  1298. Address (lower 32 bits) of the MSDU buffer OR
  1299. MSDU_EXTENSION descriptor OR Link Descriptor
  1300. In case of 'NULL' pointer, this field is set to 0
  1301. <legal all>
  1302. */
  1303. #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
  1304. #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  1305. #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  1306. /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  1307. Address (upper 8 bits) of the MSDU buffer OR
  1308. MSDU_EXTENSION descriptor OR Link Descriptor
  1309. In case of 'NULL' pointer, this field is set to 0
  1310. <legal all>
  1311. */
  1312. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
  1313. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  1314. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  1315. /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  1316. Consumer: WBM
  1317. Producer: SW/FW
  1318. In case of 'NULL' pointer, this field is set to 0
  1319. Indicates to which buffer manager the buffer OR
  1320. MSDU_EXTENSION descriptor OR link descriptor that is being
  1321. pointed to shall be returned after the frame has been
  1322. processed. It is used by WBM for routing purposes.
  1323. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  1324. to the WMB buffer idle list
  1325. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  1326. returned to the WMB idle link descriptor idle list
  1327. <enum 2 FW_BM> This buffer shall be returned to the FW
  1328. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  1329. ring 0
  1330. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  1331. ring 1
  1332. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  1333. ring 2
  1334. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  1335. ring 3
  1336. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1337. ring 4
  1338. <legal all>
  1339. */
  1340. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
  1341. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1342. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1343. /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1344. Cookie field exclusively used by SW.
  1345. In case of 'NULL' pointer, this field is set to 0
  1346. HW ignores the contents, accept that it passes the
  1347. programmed value on to other descriptors together with the
  1348. physical address
  1349. Field can be used by SW to for example associate the
  1350. buffers physical address with the virtual address
  1351. The bit definitions as used by SW are within SW HLD
  1352. specification
  1353. NOTE:
  1354. The three most significant bits can have a special
  1355. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1356. STRUCT, and field transmit_bw_restriction is set
  1357. In case of NON punctured transmission:
  1358. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1359. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1360. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1361. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1362. In case of punctured transmission:
  1363. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1364. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1365. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1366. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1367. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1368. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1369. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1370. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1371. Note: a punctured transmission is indicated by the
  1372. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1373. TLV
  1374. <legal all>
  1375. */
  1376. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
  1377. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1378. #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1379. /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */
  1380. /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
  1381. /* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  1382. Address (lower 32 bits) of the MSDU buffer OR
  1383. MSDU_EXTENSION descriptor OR Link Descriptor
  1384. In case of 'NULL' pointer, this field is set to 0
  1385. <legal all>
  1386. */
  1387. #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
  1388. #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  1389. #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  1390. /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  1391. Address (upper 8 bits) of the MSDU buffer OR
  1392. MSDU_EXTENSION descriptor OR Link Descriptor
  1393. In case of 'NULL' pointer, this field is set to 0
  1394. <legal all>
  1395. */
  1396. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
  1397. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  1398. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  1399. /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  1400. Consumer: WBM
  1401. Producer: SW/FW
  1402. In case of 'NULL' pointer, this field is set to 0
  1403. Indicates to which buffer manager the buffer OR
  1404. MSDU_EXTENSION descriptor OR link descriptor that is being
  1405. pointed to shall be returned after the frame has been
  1406. processed. It is used by WBM for routing purposes.
  1407. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  1408. to the WMB buffer idle list
  1409. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  1410. returned to the WMB idle link descriptor idle list
  1411. <enum 2 FW_BM> This buffer shall be returned to the FW
  1412. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  1413. ring 0
  1414. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  1415. ring 1
  1416. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  1417. ring 2
  1418. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  1419. ring 3
  1420. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  1421. ring 4
  1422. <legal all>
  1423. */
  1424. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
  1425. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  1426. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  1427. /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  1428. Cookie field exclusively used by SW.
  1429. In case of 'NULL' pointer, this field is set to 0
  1430. HW ignores the contents, accept that it passes the
  1431. programmed value on to other descriptors together with the
  1432. physical address
  1433. Field can be used by SW to for example associate the
  1434. buffers physical address with the virtual address
  1435. The bit definitions as used by SW are within SW HLD
  1436. specification
  1437. NOTE:
  1438. The three most significant bits can have a special
  1439. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  1440. STRUCT, and field transmit_bw_restriction is set
  1441. In case of NON punctured transmission:
  1442. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  1443. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  1444. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  1445. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  1446. In case of punctured transmission:
  1447. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  1448. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  1449. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  1450. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  1451. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  1452. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  1453. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  1454. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  1455. Note: a punctured transmission is indicated by the
  1456. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  1457. TLV
  1458. <legal all>
  1459. */
  1460. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
  1461. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  1462. #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  1463. #endif // _RX_REO_QUEUE_EXT_H_