rx_msdu_end.h 44 KB

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  1. /*
  2. * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RX_MSDU_END_H_
  17. #define _RX_MSDU_END_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. // ################ START SUMMARY #################
  21. //
  22. // Dword Fields
  23. // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
  24. // 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30]
  25. // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], reserved_2a[31:16]
  26. // 3 rule_indication_31_0[31:0]
  27. // 4 rule_indication_63_32[31:0]
  28. // 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16]
  29. // 6 ipv6_options_crc[31:0]
  30. // 7 tcp_seq_number[31:0]
  31. // 8 tcp_ack_number[31:0]
  32. // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16]
  33. // 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], reserved_10a[31:30]
  34. // 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16]
  35. // 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26]
  36. // 13 fse_metadata[31:0]
  37. // 14 cce_metadata[15:0], sa_sw_peer_id[31:16]
  38. // 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10]
  39. // 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
  40. //
  41. // ################ END SUMMARY #################
  42. #define NUM_OF_DWORDS_RX_MSDU_END 17
  43. struct rx_msdu_end {
  44. uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
  45. sw_frame_group_id : 7, //[8:2]
  46. reserved_0 : 7, //[15:9]
  47. phy_ppdu_id : 16; //[31:16]
  48. uint32_t ip_hdr_chksum : 16, //[15:0]
  49. reported_mpdu_length : 14, //[29:16]
  50. reserved_1a : 2; //[31:30]
  51. uint32_t key_id_octet : 8, //[7:0]
  52. cce_super_rule : 6, //[13:8]
  53. cce_classify_not_done_truncate : 1, //[14]
  54. cce_classify_not_done_cce_dis : 1, //[15]
  55. reserved_2a : 16; //[31:16]
  56. uint32_t rule_indication_31_0 : 32; //[31:0]
  57. uint32_t rule_indication_63_32 : 32; //[31:0]
  58. uint32_t da_offset : 6, //[5:0]
  59. sa_offset : 6, //[11:6]
  60. da_offset_valid : 1, //[12]
  61. sa_offset_valid : 1, //[13]
  62. reserved_5a : 2, //[15:14]
  63. l3_type : 16; //[31:16]
  64. uint32_t ipv6_options_crc : 32; //[31:0]
  65. uint32_t tcp_seq_number : 32; //[31:0]
  66. uint32_t tcp_ack_number : 32; //[31:0]
  67. uint32_t tcp_flag : 9, //[8:0]
  68. lro_eligible : 1, //[9]
  69. reserved_9a : 6, //[15:10]
  70. window_size : 16; //[31:16]
  71. uint32_t tcp_udp_chksum : 16, //[15:0]
  72. sa_idx_timeout : 1, //[16]
  73. da_idx_timeout : 1, //[17]
  74. msdu_limit_error : 1, //[18]
  75. flow_idx_timeout : 1, //[19]
  76. flow_idx_invalid : 1, //[20]
  77. wifi_parser_error : 1, //[21]
  78. amsdu_parser_error : 1, //[22]
  79. sa_is_valid : 1, //[23]
  80. da_is_valid : 1, //[24]
  81. da_is_mcbc : 1, //[25]
  82. l3_header_padding : 2, //[27:26]
  83. first_msdu : 1, //[28]
  84. last_msdu : 1, //[29]
  85. reserved_10a : 2; //[31:30]
  86. uint32_t sa_idx : 16, //[15:0]
  87. da_idx_or_sw_peer_id : 16; //[31:16]
  88. uint32_t msdu_drop : 1, //[0]
  89. reo_destination_indication : 5, //[5:1]
  90. flow_idx : 20, //[25:6]
  91. reserved_12a : 6; //[31:26]
  92. uint32_t fse_metadata : 32; //[31:0]
  93. uint32_t cce_metadata : 16, //[15:0]
  94. sa_sw_peer_id : 16; //[31:16]
  95. uint32_t aggregation_count : 8, //[7:0]
  96. flow_aggregation_continuation : 1, //[8]
  97. fisa_timeout : 1, //[9]
  98. reserved_15a : 22; //[31:10]
  99. uint32_t cumulative_l4_checksum : 16, //[15:0]
  100. cumulative_ip_length : 16; //[31:16]
  101. };
  102. /*
  103. rxpcu_mpdu_filter_in_category
  104. Field indicates what the reason was that this MPDU frame
  105. was allowed to come into the receive path by RXPCU
  106. <enum 0 rxpcu_filter_pass> This MPDU passed the normal
  107. frame filter programming of rxpcu
  108. <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
  109. regular frame filter and would have been dropped, were it
  110. not for the frame fitting into the 'monitor_client'
  111. category.
  112. <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
  113. regular frame filter and also did not pass the
  114. rxpcu_monitor_client filter. It would have been dropped
  115. accept that it did pass the 'monitor_other' category.
  116. <legal 0-2>
  117. sw_frame_group_id
  118. SW processes frames based on certain classifications.
  119. This field indicates to what sw classification this MPDU is
  120. mapped.
  121. The classification is given in priority order
  122. <enum 0 sw_frame_group_NDP_frame>
  123. <enum 1 sw_frame_group_Multicast_data>
  124. <enum 2 sw_frame_group_Unicast_data>
  125. <enum 3 sw_frame_group_Null_data > This includes mpdus
  126. of type Data Null as well as QoS Data Null
  127. <enum 4 sw_frame_group_mgmt_0000 >
  128. <enum 5 sw_frame_group_mgmt_0001 >
  129. <enum 6 sw_frame_group_mgmt_0010 >
  130. <enum 7 sw_frame_group_mgmt_0011 >
  131. <enum 8 sw_frame_group_mgmt_0100 >
  132. <enum 9 sw_frame_group_mgmt_0101 >
  133. <enum 10 sw_frame_group_mgmt_0110 >
  134. <enum 11 sw_frame_group_mgmt_0111 >
  135. <enum 12 sw_frame_group_mgmt_1000 >
  136. <enum 13 sw_frame_group_mgmt_1001 >
  137. <enum 14 sw_frame_group_mgmt_1010 >
  138. <enum 15 sw_frame_group_mgmt_1011 >
  139. <enum 16 sw_frame_group_mgmt_1100 >
  140. <enum 17 sw_frame_group_mgmt_1101 >
  141. <enum 18 sw_frame_group_mgmt_1110 >
  142. <enum 19 sw_frame_group_mgmt_1111 >
  143. <enum 20 sw_frame_group_ctrl_0000 >
  144. <enum 21 sw_frame_group_ctrl_0001 >
  145. <enum 22 sw_frame_group_ctrl_0010 >
  146. <enum 23 sw_frame_group_ctrl_0011 >
  147. <enum 24 sw_frame_group_ctrl_0100 >
  148. <enum 25 sw_frame_group_ctrl_0101 >
  149. <enum 26 sw_frame_group_ctrl_0110 >
  150. <enum 27 sw_frame_group_ctrl_0111 >
  151. <enum 28 sw_frame_group_ctrl_1000 >
  152. <enum 29 sw_frame_group_ctrl_1001 >
  153. <enum 30 sw_frame_group_ctrl_1010 >
  154. <enum 31 sw_frame_group_ctrl_1011 >
  155. <enum 32 sw_frame_group_ctrl_1100 >
  156. <enum 33 sw_frame_group_ctrl_1101 >
  157. <enum 34 sw_frame_group_ctrl_1110 >
  158. <enum 35 sw_frame_group_ctrl_1111 >
  159. <enum 36 sw_frame_group_unsupported> This covers type 3
  160. and protocol version != 0
  161. <legal 0-37>
  162. reserved_0
  163. <legal 0>
  164. phy_ppdu_id
  165. A ppdu counter value that PHY increments for every PPDU
  166. received. The counter value wraps around
  167. <legal all>
  168. ip_hdr_chksum
  169. This can include the IP header checksum or the pseudo
  170. header checksum used by TCP/UDP checksum.
  171. (with the first byte in the MSB and the second byte in
  172. the LSB, i.e. requiring a byte-swap for little-endian FW/SW
  173. w.r.t. the byte order in a packet)
  174. reported_mpdu_length
  175. MPDU length before decapsulation. Only valid when
  176. first_msdu is set. This field is taken directly from the
  177. length field of the A-MPDU delimiter or the preamble length
  178. field for non-A-MPDU frames.
  179. reserved_1a
  180. <legal 0>
  181. key_id_octet
  182. The key ID octet from the IV. Only valid when
  183. first_msdu is set.
  184. cce_super_rule
  185. Indicates the super filter rule
  186. cce_classify_not_done_truncate
  187. Classification failed due to truncated frame
  188. cce_classify_not_done_cce_dis
  189. Classification failed due to CCE global disable
  190. reserved_2a
  191. <legal 0>
  192. rule_indication_31_0
  193. Bitmap indicating which of rules 31-0 have matched
  194. rule_indication_63_32
  195. Bitmap indicating which of rules 63-32 have matched
  196. da_offset
  197. Offset into MSDU buffer for DA
  198. sa_offset
  199. Offset into MSDU buffer for SA
  200. da_offset_valid
  201. da_offset field is valid. This will be set to 0 in case
  202. of a dynamic A-MSDU when DA is compressed
  203. sa_offset_valid
  204. sa_offset field is valid. This will be set to 0 in case
  205. of a dynamic A-MSDU when SA is compressed
  206. reserved_5a
  207. <legal 0>
  208. l3_type
  209. The 16-bit type value indicating the type of L3 later
  210. extracted from LLC/SNAP, set to zero if SNAP is not
  211. available
  212. ipv6_options_crc
  213. 32 bit CRC computed out of IP v6 extension headers
  214. tcp_seq_number
  215. TCP sequence number (as a number assembled from a TCP
  216. packet in big-endian order, i.e. requiring a byte-swap for
  217. little-endian FW/SW w.r.t. the byte order in a packet)
  218. tcp_ack_number
  219. TCP acknowledge number (as a number assembled from a TCP
  220. packet in big-endian order, i.e. requiring a byte-swap for
  221. little-endian FW/SW w.r.t. the byte order in a packet)
  222. tcp_flag
  223. TCP flags
  224. {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
  225. in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
  226. i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
  227. the byte order in a packet)
  228. lro_eligible
  229. Computed out of TCP and IP fields to indicate that this
  230. MSDU is eligible for LRO
  231. reserved_9a
  232. NOTE: DO not assign a field... Internally used in
  233. RXOLE..
  234. <legal 0>
  235. window_size
  236. TCP receive window size (as a number assembled from a
  237. TCP packet in big-endian order, i.e. requiring a byte-swap
  238. for little-endian FW/SW w.r.t. the byte order in a packet)
  239. tcp_udp_chksum
  240. The value of the computed TCP/UDP checksum. A mode bit
  241. selects whether this checksum is the full checksum or the
  242. partial checksum which does not include the pseudo header.
  243. (with the first byte in the MSB and the second byte in the
  244. LSB, i.e. requiring a byte-swap for little-endian FW/SW
  245. w.r.t. the byte order in a packet)
  246. sa_idx_timeout
  247. Indicates an unsuccessful MAC source address search due
  248. to the expiring of the search timer.
  249. da_idx_timeout
  250. Indicates an unsuccessful MAC destination address search
  251. due to the expiring of the search timer.
  252. msdu_limit_error
  253. Indicates that the MSDU threshold was exceeded and thus
  254. all the rest of the MSDUs will not be scattered and will not
  255. be decapsulated but will be DMA'ed in RAW format as a single
  256. MSDU buffer
  257. flow_idx_timeout
  258. Indicates an unsuccessful flow search due to the
  259. expiring of the search timer.
  260. <legal all>
  261. flow_idx_invalid
  262. flow id is not valid
  263. <legal all>
  264. wifi_parser_error
  265. Indicates that the WiFi frame has one of the following
  266. errors
  267. o has less than minimum allowed bytes as per standard
  268. o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
  269. <legal all>
  270. amsdu_parser_error
  271. A-MSDU could not be properly de-agregated.
  272. <legal all>
  273. sa_is_valid
  274. Indicates that OLE found a valid SA entry
  275. da_is_valid
  276. Indicates that OLE found a valid DA entry
  277. da_is_mcbc
  278. Field Only valid if da_is_valid is set
  279. Indicates the DA address was a Multicast of Broadcast
  280. address.
  281. l3_header_padding
  282. Number of bytes padded to make sure that the L3 header
  283. will always start of a Dword boundary
  284. first_msdu
  285. Indicates the first MSDU of A-MSDU. If both first_msdu
  286. and last_msdu are set in the MSDU then this is a
  287. non-aggregated MSDU frame: normal MPDU. Interior MSDU in an
  288. A-MSDU shall have both first_mpdu and last_mpdu bits set to
  289. 0.
  290. last_msdu
  291. Indicates the last MSDU of the A-MSDU. MPDU end status
  292. is only valid when last_msdu is set.
  293. reserved_10a
  294. <legal 0>
  295. sa_idx
  296. The offset in the address table which matches the MAC
  297. source address.
  298. da_idx_or_sw_peer_id
  299. Based on a register configuration in RXOLE, this field
  300. will contain:
  301. The offset in the address table which matches the MAC
  302. destination address
  303. OR:
  304. sw_peer_id from the address search entry corresponding
  305. to the destination address of the MSDU
  306. msdu_drop
  307. When set, REO shall drop this MSDU and not forward it to
  308. any other ring...
  309. <legal all>
  310. reo_destination_indication
  311. The ID of the REO exit ring where the MSDU frame shall
  312. push after (MPDU level) reordering has finished.
  313. <enum 0 reo_destination_tcl> Reo will push the frame
  314. into the REO2TCL ring
  315. <enum 1 reo_destination_sw1> Reo will push the frame
  316. into the REO2SW1 ring
  317. <enum 2 reo_destination_sw2> Reo will push the frame
  318. into the REO2SW2 ring
  319. <enum 3 reo_destination_sw3> Reo will push the frame
  320. into the REO2SW3 ring
  321. <enum 4 reo_destination_sw4> Reo will push the frame
  322. into the REO2SW4 ring
  323. <enum 5 reo_destination_release> Reo will push the frame
  324. into the REO_release ring
  325. <enum 6 reo_destination_fw> Reo will push the frame into
  326. the REO2FW ring
  327. <enum 7 reo_destination_sw5> Reo will push the frame
  328. into the REO2SW5 ring (REO remaps this in chips without
  329. REO2SW5 ring, e.g. Pine)
  330. <enum 8 reo_destination_sw6> Reo will push the frame
  331. into the REO2SW6 ring (REO remaps this in chips without
  332. REO2SW6 ring, e.g. Pine)
  333. <enum 9 reo_destination_9> REO remaps this <enum 10
  334. reo_destination_10> REO remaps this
  335. <enum 11 reo_destination_11> REO remaps this
  336. <enum 12 reo_destination_12> REO remaps this <enum 13
  337. reo_destination_13> REO remaps this
  338. <enum 14 reo_destination_14> REO remaps this
  339. <enum 15 reo_destination_15> REO remaps this
  340. <enum 16 reo_destination_16> REO remaps this
  341. <enum 17 reo_destination_17> REO remaps this
  342. <enum 18 reo_destination_18> REO remaps this
  343. <enum 19 reo_destination_19> REO remaps this
  344. <enum 20 reo_destination_20> REO remaps this
  345. <enum 21 reo_destination_21> REO remaps this
  346. <enum 22 reo_destination_22> REO remaps this
  347. <enum 23 reo_destination_23> REO remaps this
  348. <enum 24 reo_destination_24> REO remaps this
  349. <enum 25 reo_destination_25> REO remaps this
  350. <enum 26 reo_destination_26> REO remaps this
  351. <enum 27 reo_destination_27> REO remaps this
  352. <enum 28 reo_destination_28> REO remaps this
  353. <enum 29 reo_destination_29> REO remaps this
  354. <enum 30 reo_destination_30> REO remaps this
  355. <enum 31 reo_destination_31> REO remaps this
  356. <legal all>
  357. flow_idx
  358. Flow table index
  359. <legal all>
  360. reserved_12a
  361. <legal 0>
  362. fse_metadata
  363. FSE related meta data:
  364. <legal all>
  365. cce_metadata
  366. CCE related meta data:
  367. <legal all>
  368. sa_sw_peer_id
  369. sw_peer_id from the address search entry corresponding
  370. to the source address of the MSDU
  371. <legal all>
  372. aggregation_count
  373. FISA: Number of MSDU's aggregated so far
  374. Set to zero in chips not supporting FISA, e.g. Pine
  375. <legal all>
  376. flow_aggregation_continuation
  377. FISA: To indicate that this MSDU can be aggregated with
  378. the previous packet with the same flow id
  379. Set to zero in chips not supporting FISA, e.g. Pine
  380. <legal all>
  381. fisa_timeout
  382. FISA: To indicate that the aggregation has restarted for
  383. this flow due to timeout
  384. Set to zero in chips not supporting FISA, e.g. Pine
  385. <legal all>
  386. reserved_15a
  387. <legal 0>
  388. cumulative_l4_checksum
  389. FISA: checksum for MSDU's that is part of this flow
  390. aggregated so far
  391. Set to zero in chips not supporting FISA, e.g. Pine
  392. <legal all>
  393. cumulative_ip_length
  394. FISA: Total MSDU length that is part of this flow
  395. aggregated so far
  396. Set to zero in chips not supporting FISA, e.g. Pine
  397. <legal all>
  398. */
  399. /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
  400. Field indicates what the reason was that this MPDU frame
  401. was allowed to come into the receive path by RXPCU
  402. <enum 0 rxpcu_filter_pass> This MPDU passed the normal
  403. frame filter programming of rxpcu
  404. <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
  405. regular frame filter and would have been dropped, were it
  406. not for the frame fitting into the 'monitor_client'
  407. category.
  408. <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
  409. regular frame filter and also did not pass the
  410. rxpcu_monitor_client filter. It would have been dropped
  411. accept that it did pass the 'monitor_other' category.
  412. <legal 0-2>
  413. */
  414. #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
  415. #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  416. #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
  417. /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID
  418. SW processes frames based on certain classifications.
  419. This field indicates to what sw classification this MPDU is
  420. mapped.
  421. The classification is given in priority order
  422. <enum 0 sw_frame_group_NDP_frame>
  423. <enum 1 sw_frame_group_Multicast_data>
  424. <enum 2 sw_frame_group_Unicast_data>
  425. <enum 3 sw_frame_group_Null_data > This includes mpdus
  426. of type Data Null as well as QoS Data Null
  427. <enum 4 sw_frame_group_mgmt_0000 >
  428. <enum 5 sw_frame_group_mgmt_0001 >
  429. <enum 6 sw_frame_group_mgmt_0010 >
  430. <enum 7 sw_frame_group_mgmt_0011 >
  431. <enum 8 sw_frame_group_mgmt_0100 >
  432. <enum 9 sw_frame_group_mgmt_0101 >
  433. <enum 10 sw_frame_group_mgmt_0110 >
  434. <enum 11 sw_frame_group_mgmt_0111 >
  435. <enum 12 sw_frame_group_mgmt_1000 >
  436. <enum 13 sw_frame_group_mgmt_1001 >
  437. <enum 14 sw_frame_group_mgmt_1010 >
  438. <enum 15 sw_frame_group_mgmt_1011 >
  439. <enum 16 sw_frame_group_mgmt_1100 >
  440. <enum 17 sw_frame_group_mgmt_1101 >
  441. <enum 18 sw_frame_group_mgmt_1110 >
  442. <enum 19 sw_frame_group_mgmt_1111 >
  443. <enum 20 sw_frame_group_ctrl_0000 >
  444. <enum 21 sw_frame_group_ctrl_0001 >
  445. <enum 22 sw_frame_group_ctrl_0010 >
  446. <enum 23 sw_frame_group_ctrl_0011 >
  447. <enum 24 sw_frame_group_ctrl_0100 >
  448. <enum 25 sw_frame_group_ctrl_0101 >
  449. <enum 26 sw_frame_group_ctrl_0110 >
  450. <enum 27 sw_frame_group_ctrl_0111 >
  451. <enum 28 sw_frame_group_ctrl_1000 >
  452. <enum 29 sw_frame_group_ctrl_1001 >
  453. <enum 30 sw_frame_group_ctrl_1010 >
  454. <enum 31 sw_frame_group_ctrl_1011 >
  455. <enum 32 sw_frame_group_ctrl_1100 >
  456. <enum 33 sw_frame_group_ctrl_1101 >
  457. <enum 34 sw_frame_group_ctrl_1110 >
  458. <enum 35 sw_frame_group_ctrl_1111 >
  459. <enum 36 sw_frame_group_unsupported> This covers type 3
  460. and protocol version != 0
  461. <legal 0-37>
  462. */
  463. #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
  464. #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2
  465. #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
  466. /* Description RX_MSDU_END_0_RESERVED_0
  467. <legal 0>
  468. */
  469. #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000
  470. #define RX_MSDU_END_0_RESERVED_0_LSB 9
  471. #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00
  472. /* Description RX_MSDU_END_0_PHY_PPDU_ID
  473. A ppdu counter value that PHY increments for every PPDU
  474. received. The counter value wraps around
  475. <legal all>
  476. */
  477. #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
  478. #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16
  479. #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
  480. /* Description RX_MSDU_END_1_IP_HDR_CHKSUM
  481. This can include the IP header checksum or the pseudo
  482. header checksum used by TCP/UDP checksum.
  483. (with the first byte in the MSB and the second byte in
  484. the LSB, i.e. requiring a byte-swap for little-endian FW/SW
  485. w.r.t. the byte order in a packet)
  486. */
  487. #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004
  488. #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0
  489. #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff
  490. /* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH
  491. MPDU length before decapsulation. Only valid when
  492. first_msdu is set. This field is taken directly from the
  493. length field of the A-MPDU delimiter or the preamble length
  494. field for non-A-MPDU frames.
  495. */
  496. #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004
  497. #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16
  498. #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000
  499. /* Description RX_MSDU_END_1_RESERVED_1A
  500. <legal 0>
  501. */
  502. #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004
  503. #define RX_MSDU_END_1_RESERVED_1A_LSB 30
  504. #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000
  505. /* Description RX_MSDU_END_2_KEY_ID_OCTET
  506. The key ID octet from the IV. Only valid when
  507. first_msdu is set.
  508. */
  509. #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008
  510. #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0
  511. #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff
  512. /* Description RX_MSDU_END_2_CCE_SUPER_RULE
  513. Indicates the super filter rule
  514. */
  515. #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008
  516. #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8
  517. #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00
  518. /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE
  519. Classification failed due to truncated frame
  520. */
  521. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008
  522. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
  523. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000
  524. /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS
  525. Classification failed due to CCE global disable
  526. */
  527. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008
  528. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
  529. #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000
  530. /* Description RX_MSDU_END_2_RESERVED_2A
  531. <legal 0>
  532. */
  533. #define RX_MSDU_END_2_RESERVED_2A_OFFSET 0x00000008
  534. #define RX_MSDU_END_2_RESERVED_2A_LSB 16
  535. #define RX_MSDU_END_2_RESERVED_2A_MASK 0xffff0000
  536. /* Description RX_MSDU_END_3_RULE_INDICATION_31_0
  537. Bitmap indicating which of rules 31-0 have matched
  538. */
  539. #define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c
  540. #define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0
  541. #define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff
  542. /* Description RX_MSDU_END_4_RULE_INDICATION_63_32
  543. Bitmap indicating which of rules 63-32 have matched
  544. */
  545. #define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010
  546. #define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0
  547. #define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff
  548. /* Description RX_MSDU_END_5_DA_OFFSET
  549. Offset into MSDU buffer for DA
  550. */
  551. #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014
  552. #define RX_MSDU_END_5_DA_OFFSET_LSB 0
  553. #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f
  554. /* Description RX_MSDU_END_5_SA_OFFSET
  555. Offset into MSDU buffer for SA
  556. */
  557. #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014
  558. #define RX_MSDU_END_5_SA_OFFSET_LSB 6
  559. #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0
  560. /* Description RX_MSDU_END_5_DA_OFFSET_VALID
  561. da_offset field is valid. This will be set to 0 in case
  562. of a dynamic A-MSDU when DA is compressed
  563. */
  564. #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014
  565. #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12
  566. #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000
  567. /* Description RX_MSDU_END_5_SA_OFFSET_VALID
  568. sa_offset field is valid. This will be set to 0 in case
  569. of a dynamic A-MSDU when SA is compressed
  570. */
  571. #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014
  572. #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13
  573. #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000
  574. /* Description RX_MSDU_END_5_RESERVED_5A
  575. <legal 0>
  576. */
  577. #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014
  578. #define RX_MSDU_END_5_RESERVED_5A_LSB 14
  579. #define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000
  580. /* Description RX_MSDU_END_5_L3_TYPE
  581. The 16-bit type value indicating the type of L3 later
  582. extracted from LLC/SNAP, set to zero if SNAP is not
  583. available
  584. */
  585. #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014
  586. #define RX_MSDU_END_5_L3_TYPE_LSB 16
  587. #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000
  588. /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC
  589. 32 bit CRC computed out of IP v6 extension headers
  590. */
  591. #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018
  592. #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0
  593. #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff
  594. /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER
  595. TCP sequence number (as a number assembled from a TCP
  596. packet in big-endian order, i.e. requiring a byte-swap for
  597. little-endian FW/SW w.r.t. the byte order in a packet)
  598. */
  599. #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c
  600. #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0
  601. #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff
  602. /* Description RX_MSDU_END_8_TCP_ACK_NUMBER
  603. TCP acknowledge number (as a number assembled from a TCP
  604. packet in big-endian order, i.e. requiring a byte-swap for
  605. little-endian FW/SW w.r.t. the byte order in a packet)
  606. */
  607. #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020
  608. #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0
  609. #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff
  610. /* Description RX_MSDU_END_9_TCP_FLAG
  611. TCP flags
  612. {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
  613. in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
  614. i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
  615. the byte order in a packet)
  616. */
  617. #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024
  618. #define RX_MSDU_END_9_TCP_FLAG_LSB 0
  619. #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff
  620. /* Description RX_MSDU_END_9_LRO_ELIGIBLE
  621. Computed out of TCP and IP fields to indicate that this
  622. MSDU is eligible for LRO
  623. */
  624. #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024
  625. #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9
  626. #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200
  627. /* Description RX_MSDU_END_9_RESERVED_9A
  628. NOTE: DO not assign a field... Internally used in
  629. RXOLE..
  630. <legal 0>
  631. */
  632. #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024
  633. #define RX_MSDU_END_9_RESERVED_9A_LSB 10
  634. #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00
  635. /* Description RX_MSDU_END_9_WINDOW_SIZE
  636. TCP receive window size (as a number assembled from a
  637. TCP packet in big-endian order, i.e. requiring a byte-swap
  638. for little-endian FW/SW w.r.t. the byte order in a packet)
  639. */
  640. #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024
  641. #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16
  642. #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000
  643. /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM
  644. The value of the computed TCP/UDP checksum. A mode bit
  645. selects whether this checksum is the full checksum or the
  646. partial checksum which does not include the pseudo header.
  647. (with the first byte in the MSB and the second byte in the
  648. LSB, i.e. requiring a byte-swap for little-endian FW/SW
  649. w.r.t. the byte order in a packet)
  650. */
  651. #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028
  652. #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0
  653. #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff
  654. /* Description RX_MSDU_END_10_SA_IDX_TIMEOUT
  655. Indicates an unsuccessful MAC source address search due
  656. to the expiring of the search timer.
  657. */
  658. #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028
  659. #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16
  660. #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000
  661. /* Description RX_MSDU_END_10_DA_IDX_TIMEOUT
  662. Indicates an unsuccessful MAC destination address search
  663. due to the expiring of the search timer.
  664. */
  665. #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028
  666. #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17
  667. #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000
  668. /* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR
  669. Indicates that the MSDU threshold was exceeded and thus
  670. all the rest of the MSDUs will not be scattered and will not
  671. be decapsulated but will be DMA'ed in RAW format as a single
  672. MSDU buffer
  673. */
  674. #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028
  675. #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18
  676. #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000
  677. /* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT
  678. Indicates an unsuccessful flow search due to the
  679. expiring of the search timer.
  680. <legal all>
  681. */
  682. #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028
  683. #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19
  684. #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000
  685. /* Description RX_MSDU_END_10_FLOW_IDX_INVALID
  686. flow id is not valid
  687. <legal all>
  688. */
  689. #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028
  690. #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20
  691. #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000
  692. /* Description RX_MSDU_END_10_WIFI_PARSER_ERROR
  693. Indicates that the WiFi frame has one of the following
  694. errors
  695. o has less than minimum allowed bytes as per standard
  696. o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
  697. <legal all>
  698. */
  699. #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028
  700. #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21
  701. #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000
  702. /* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR
  703. A-MSDU could not be properly de-agregated.
  704. <legal all>
  705. */
  706. #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028
  707. #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22
  708. #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000
  709. /* Description RX_MSDU_END_10_SA_IS_VALID
  710. Indicates that OLE found a valid SA entry
  711. */
  712. #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028
  713. #define RX_MSDU_END_10_SA_IS_VALID_LSB 23
  714. #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000
  715. /* Description RX_MSDU_END_10_DA_IS_VALID
  716. Indicates that OLE found a valid DA entry
  717. */
  718. #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028
  719. #define RX_MSDU_END_10_DA_IS_VALID_LSB 24
  720. #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000
  721. /* Description RX_MSDU_END_10_DA_IS_MCBC
  722. Field Only valid if da_is_valid is set
  723. Indicates the DA address was a Multicast of Broadcast
  724. address.
  725. */
  726. #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028
  727. #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25
  728. #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000
  729. /* Description RX_MSDU_END_10_L3_HEADER_PADDING
  730. Number of bytes padded to make sure that the L3 header
  731. will always start of a Dword boundary
  732. */
  733. #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028
  734. #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26
  735. #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000
  736. /* Description RX_MSDU_END_10_FIRST_MSDU
  737. Indicates the first MSDU of A-MSDU. If both first_msdu
  738. and last_msdu are set in the MSDU then this is a
  739. non-aggregated MSDU frame: normal MPDU. Interior MSDU in an
  740. A-MSDU shall have both first_mpdu and last_mpdu bits set to
  741. 0.
  742. */
  743. #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028
  744. #define RX_MSDU_END_10_FIRST_MSDU_LSB 28
  745. #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000
  746. /* Description RX_MSDU_END_10_LAST_MSDU
  747. Indicates the last MSDU of the A-MSDU. MPDU end status
  748. is only valid when last_msdu is set.
  749. */
  750. #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028
  751. #define RX_MSDU_END_10_LAST_MSDU_LSB 29
  752. #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000
  753. /* Description RX_MSDU_END_10_RESERVED_10A
  754. <legal 0>
  755. */
  756. #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028
  757. #define RX_MSDU_END_10_RESERVED_10A_LSB 30
  758. #define RX_MSDU_END_10_RESERVED_10A_MASK 0xc0000000
  759. /* Description RX_MSDU_END_11_SA_IDX
  760. The offset in the address table which matches the MAC
  761. source address.
  762. */
  763. #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c
  764. #define RX_MSDU_END_11_SA_IDX_LSB 0
  765. #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff
  766. /* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID
  767. Based on a register configuration in RXOLE, this field
  768. will contain:
  769. The offset in the address table which matches the MAC
  770. destination address
  771. OR:
  772. sw_peer_id from the address search entry corresponding
  773. to the destination address of the MSDU
  774. */
  775. #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c
  776. #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16
  777. #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000
  778. /* Description RX_MSDU_END_12_MSDU_DROP
  779. When set, REO shall drop this MSDU and not forward it to
  780. any other ring...
  781. <legal all>
  782. */
  783. #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030
  784. #define RX_MSDU_END_12_MSDU_DROP_LSB 0
  785. #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001
  786. /* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION
  787. The ID of the REO exit ring where the MSDU frame shall
  788. push after (MPDU level) reordering has finished.
  789. <enum 0 reo_destination_tcl> Reo will push the frame
  790. into the REO2TCL ring
  791. <enum 1 reo_destination_sw1> Reo will push the frame
  792. into the REO2SW1 ring
  793. <enum 2 reo_destination_sw2> Reo will push the frame
  794. into the REO2SW2 ring
  795. <enum 3 reo_destination_sw3> Reo will push the frame
  796. into the REO2SW3 ring
  797. <enum 4 reo_destination_sw4> Reo will push the frame
  798. into the REO2SW4 ring
  799. <enum 5 reo_destination_release> Reo will push the frame
  800. into the REO_release ring
  801. <enum 6 reo_destination_fw> Reo will push the frame into
  802. the REO2FW ring
  803. <enum 7 reo_destination_sw5> Reo will push the frame
  804. into the REO2SW5 ring (REO remaps this in chips without
  805. REO2SW5 ring, e.g. Pine)
  806. <enum 8 reo_destination_sw6> Reo will push the frame
  807. into the REO2SW6 ring (REO remaps this in chips without
  808. REO2SW6 ring, e.g. Pine)
  809. <enum 9 reo_destination_9> REO remaps this <enum 10
  810. reo_destination_10> REO remaps this
  811. <enum 11 reo_destination_11> REO remaps this
  812. <enum 12 reo_destination_12> REO remaps this <enum 13
  813. reo_destination_13> REO remaps this
  814. <enum 14 reo_destination_14> REO remaps this
  815. <enum 15 reo_destination_15> REO remaps this
  816. <enum 16 reo_destination_16> REO remaps this
  817. <enum 17 reo_destination_17> REO remaps this
  818. <enum 18 reo_destination_18> REO remaps this
  819. <enum 19 reo_destination_19> REO remaps this
  820. <enum 20 reo_destination_20> REO remaps this
  821. <enum 21 reo_destination_21> REO remaps this
  822. <enum 22 reo_destination_22> REO remaps this
  823. <enum 23 reo_destination_23> REO remaps this
  824. <enum 24 reo_destination_24> REO remaps this
  825. <enum 25 reo_destination_25> REO remaps this
  826. <enum 26 reo_destination_26> REO remaps this
  827. <enum 27 reo_destination_27> REO remaps this
  828. <enum 28 reo_destination_28> REO remaps this
  829. <enum 29 reo_destination_29> REO remaps this
  830. <enum 30 reo_destination_30> REO remaps this
  831. <enum 31 reo_destination_31> REO remaps this
  832. <legal all>
  833. */
  834. #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030
  835. #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1
  836. #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e
  837. /* Description RX_MSDU_END_12_FLOW_IDX
  838. Flow table index
  839. <legal all>
  840. */
  841. #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030
  842. #define RX_MSDU_END_12_FLOW_IDX_LSB 6
  843. #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0
  844. /* Description RX_MSDU_END_12_RESERVED_12A
  845. <legal 0>
  846. */
  847. #define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030
  848. #define RX_MSDU_END_12_RESERVED_12A_LSB 26
  849. #define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000
  850. /* Description RX_MSDU_END_13_FSE_METADATA
  851. FSE related meta data:
  852. <legal all>
  853. */
  854. #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034
  855. #define RX_MSDU_END_13_FSE_METADATA_LSB 0
  856. #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff
  857. /* Description RX_MSDU_END_14_CCE_METADATA
  858. CCE related meta data:
  859. <legal all>
  860. */
  861. #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038
  862. #define RX_MSDU_END_14_CCE_METADATA_LSB 0
  863. #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff
  864. /* Description RX_MSDU_END_14_SA_SW_PEER_ID
  865. sw_peer_id from the address search entry corresponding
  866. to the source address of the MSDU
  867. <legal all>
  868. */
  869. #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038
  870. #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16
  871. #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000
  872. /* Description RX_MSDU_END_15_AGGREGATION_COUNT
  873. FISA: Number of MSDU's aggregated so far
  874. Set to zero in chips not supporting FISA, e.g. Pine
  875. <legal all>
  876. */
  877. #define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c
  878. #define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0
  879. #define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff
  880. /* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION
  881. FISA: To indicate that this MSDU can be aggregated with
  882. the previous packet with the same flow id
  883. Set to zero in chips not supporting FISA, e.g. Pine
  884. <legal all>
  885. */
  886. #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c
  887. #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8
  888. #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100
  889. /* Description RX_MSDU_END_15_FISA_TIMEOUT
  890. FISA: To indicate that the aggregation has restarted for
  891. this flow due to timeout
  892. Set to zero in chips not supporting FISA, e.g. Pine
  893. <legal all>
  894. */
  895. #define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c
  896. #define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9
  897. #define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200
  898. /* Description RX_MSDU_END_15_RESERVED_15A
  899. <legal 0>
  900. */
  901. #define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c
  902. #define RX_MSDU_END_15_RESERVED_15A_LSB 10
  903. #define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00
  904. /* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM
  905. FISA: checksum for MSDU's that is part of this flow
  906. aggregated so far
  907. Set to zero in chips not supporting FISA, e.g. Pine
  908. <legal all>
  909. */
  910. #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040
  911. #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0
  912. #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
  913. /* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH
  914. FISA: Total MSDU length that is part of this flow
  915. aggregated so far
  916. Set to zero in chips not supporting FISA, e.g. Pine
  917. <legal all>
  918. */
  919. #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040
  920. #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16
  921. #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
  922. #endif // _RX_MSDU_END_H_