msmhwiobase.h 17 KB

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  1. /*
  2. * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef __MSMHWIOBASE_H__
  17. #define __MSMHWIOBASE_H__
  18. /*
  19. ===========================================================================
  20. */
  21. /**
  22. @file msmhwiobase.h
  23. @brief Auto-generated HWIO base include file.
  24. */
  25. /*
  26. ===========================================================================
  27. */
  28. /*----------------------------------------------------------------------------
  29. * BASE: WCSS_WCSS
  30. *--------------------------------------------------------------------------*/
  31. #define WCSS_WCSS_BASE 0x00000000
  32. #define WCSS_WCSS_BASE_SIZE 0x01000000
  33. #define WCSS_WCSS_BASE_PHYS 0x00000000
  34. /*----------------------------------------------------------------------------
  35. * BASE: BOOT_ROM_SIZE
  36. *--------------------------------------------------------------------------*/
  37. #define BOOT_ROM_SIZE_BASE 0x00100000
  38. #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
  39. #define BOOT_ROM_SIZE_BASE_PHYS 0x00100000
  40. /*----------------------------------------------------------------------------
  41. * BASE: QDSS_STM_SIZE
  42. *--------------------------------------------------------------------------*/
  43. #define QDSS_STM_SIZE_BASE 0x00100000
  44. #define QDSS_STM_SIZE_BASE_SIZE 0x100000000
  45. #define QDSS_STM_SIZE_BASE_PHYS 0x00100000
  46. /*----------------------------------------------------------------------------
  47. * BASE: SYSTEM_IRAM_SIZE
  48. *--------------------------------------------------------------------------*/
  49. #define SYSTEM_IRAM_SIZE_BASE 0x00400000
  50. #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
  51. #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
  52. /*----------------------------------------------------------------------------
  53. * BASE: BOOT_ROM_START_ADDRESS
  54. *--------------------------------------------------------------------------*/
  55. #define BOOT_ROM_START_ADDRESS_BASE 0x00800000
  56. #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
  57. #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x00800000
  58. /*----------------------------------------------------------------------------
  59. * BASE: BOOT_ROM_END_ADDRESS
  60. *--------------------------------------------------------------------------*/
  61. #define BOOT_ROM_END_ADDRESS_BASE 0x008fffff
  62. #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
  63. #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x008fffff
  64. /*----------------------------------------------------------------------------
  65. * BASE: QDSS_STM
  66. *--------------------------------------------------------------------------*/
  67. #define QDSS_STM_BASE 0x00900000
  68. #define QDSS_STM_BASE_SIZE 0x100000000
  69. #define QDSS_STM_BASE_PHYS 0x00900000
  70. /*----------------------------------------------------------------------------
  71. * BASE: QDSS_STM_END
  72. *--------------------------------------------------------------------------*/
  73. #define QDSS_STM_END_BASE 0x009fffff
  74. #define QDSS_STM_END_BASE_SIZE 0x100000000
  75. #define QDSS_STM_END_BASE_PHYS 0x009fffff
  76. /*----------------------------------------------------------------------------
  77. * BASE: SYSTEM_IRAM_START_ADDRESS
  78. *--------------------------------------------------------------------------*/
  79. #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
  80. #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
  81. #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
  82. /*----------------------------------------------------------------------------
  83. * BASE: SYSTEM_IRAM_END_ADDRESS
  84. *--------------------------------------------------------------------------*/
  85. #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
  86. #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
  87. #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
  88. /*----------------------------------------------------------------------------
  89. * BASE: TLMM
  90. *--------------------------------------------------------------------------*/
  91. #define TLMM_BASE 0x01800000
  92. #define TLMM_BASE_SIZE 0x00300000
  93. #define TLMM_BASE_PHYS 0x01800000
  94. /*----------------------------------------------------------------------------
  95. * BASE: CORE_TOP_CSR
  96. *--------------------------------------------------------------------------*/
  97. #define CORE_TOP_CSR_BASE 0x01b00000
  98. #define CORE_TOP_CSR_BASE_SIZE 0x00040000
  99. #define CORE_TOP_CSR_BASE_PHYS 0x01b00000
  100. /*----------------------------------------------------------------------------
  101. * BASE: BLSP1_BLSP
  102. *--------------------------------------------------------------------------*/
  103. #define BLSP1_BLSP_BASE 0x01b40000
  104. #define BLSP1_BLSP_BASE_SIZE 0x00040000
  105. #define BLSP1_BLSP_BASE_PHYS 0x01b40000
  106. /*----------------------------------------------------------------------------
  107. * BASE: MEMSS_CSR
  108. *--------------------------------------------------------------------------*/
  109. #define MEMSS_CSR_BASE 0x01bc0000
  110. #define MEMSS_CSR_BASE_SIZE 0x0000001c
  111. #define MEMSS_CSR_BASE_PHYS 0x01bc0000
  112. /*----------------------------------------------------------------------------
  113. * BASE: TSENS_SROT
  114. *--------------------------------------------------------------------------*/
  115. #define TSENS_SROT_BASE 0x01bf0000
  116. #define TSENS_SROT_BASE_SIZE 0x00001000
  117. #define TSENS_SROT_BASE_PHYS 0x01bf0000
  118. /*----------------------------------------------------------------------------
  119. * BASE: TSENS_TM
  120. *--------------------------------------------------------------------------*/
  121. #define TSENS_TM_BASE 0x01bf1000
  122. #define TSENS_TM_BASE_SIZE 0x00001000
  123. #define TSENS_TM_BASE_PHYS 0x01bf1000
  124. /*----------------------------------------------------------------------------
  125. * BASE: QDSS_APB_DEC_QDSS_APB
  126. *--------------------------------------------------------------------------*/
  127. #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
  128. #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
  129. #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
  130. /*----------------------------------------------------------------------------
  131. * BASE: QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG
  132. *--------------------------------------------------------------------------*/
  133. #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01c80000
  134. #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00080000
  135. #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01c80000
  136. /*----------------------------------------------------------------------------
  137. * BASE: QDSS_WRAPPER_TOP
  138. *--------------------------------------------------------------------------*/
  139. #define QDSS_WRAPPER_TOP_BASE 0x01d00000
  140. #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
  141. #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01d00000
  142. /*----------------------------------------------------------------------------
  143. * BASE: PCIE_PCIE_TOP_WRAPPER
  144. *--------------------------------------------------------------------------*/
  145. #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
  146. #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
  147. #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
  148. /*----------------------------------------------------------------------------
  149. * BASE: SECURITY_CONTROL_WLAN
  150. *--------------------------------------------------------------------------*/
  151. #define SECURITY_CONTROL_WLAN_BASE 0x01e20000
  152. #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
  153. #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
  154. /*----------------------------------------------------------------------------
  155. * BASE: CPR_CX_CPR3
  156. *--------------------------------------------------------------------------*/
  157. #define CPR_CX_CPR3_BASE 0x01e30000
  158. #define CPR_CX_CPR3_BASE_SIZE 0x00004000
  159. #define CPR_CX_CPR3_BASE_PHYS 0x01e30000
  160. /*----------------------------------------------------------------------------
  161. * BASE: CPR_MX_CPR3
  162. *--------------------------------------------------------------------------*/
  163. #define CPR_MX_CPR3_BASE 0x01e34000
  164. #define CPR_MX_CPR3_BASE_SIZE 0x00004000
  165. #define CPR_MX_CPR3_BASE_PHYS 0x01e34000
  166. /*----------------------------------------------------------------------------
  167. * BASE: GCC_GCC
  168. *--------------------------------------------------------------------------*/
  169. #define GCC_GCC_BASE 0x01e40000
  170. #define GCC_GCC_BASE_SIZE 0x00001000
  171. #define GCC_GCC_BASE_PHYS 0x01e40000
  172. /*----------------------------------------------------------------------------
  173. * BASE: PRNG_PRNG_TOP
  174. *--------------------------------------------------------------------------*/
  175. #define PRNG_PRNG_TOP_BASE 0x01e50000
  176. #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
  177. #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
  178. /*----------------------------------------------------------------------------
  179. * BASE: PCNOC_0_BUS_TIMEOUT
  180. *--------------------------------------------------------------------------*/
  181. #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
  182. #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
  183. #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
  184. /*----------------------------------------------------------------------------
  185. * BASE: PCNOC_1_BUS_TIMEOUT
  186. *--------------------------------------------------------------------------*/
  187. #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
  188. #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
  189. #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
  190. /*----------------------------------------------------------------------------
  191. * BASE: PCNOC_2_BUS_TIMEOUT
  192. *--------------------------------------------------------------------------*/
  193. #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
  194. #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
  195. #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
  196. /*----------------------------------------------------------------------------
  197. * BASE: PCNOC_3_BUS_TIMEOUT
  198. *--------------------------------------------------------------------------*/
  199. #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
  200. #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
  201. #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
  202. /*----------------------------------------------------------------------------
  203. * BASE: SYSTEM_NOC
  204. *--------------------------------------------------------------------------*/
  205. #define SYSTEM_NOC_BASE 0x01e80000
  206. #define SYSTEM_NOC_BASE_SIZE 0x00003280
  207. #define SYSTEM_NOC_BASE_PHYS 0x01e80000
  208. /*----------------------------------------------------------------------------
  209. * BASE: PC_NOC
  210. *--------------------------------------------------------------------------*/
  211. #define PC_NOC_BASE 0x01f00000
  212. #define PC_NOC_BASE_SIZE 0x00001180
  213. #define PC_NOC_BASE_PHYS 0x01f00000
  214. /*----------------------------------------------------------------------------
  215. * BASE: WLAON_WL_AON_REG
  216. *--------------------------------------------------------------------------*/
  217. #define WLAON_WL_AON_REG_BASE 0x01f80000
  218. #define WLAON_WL_AON_REG_BASE_SIZE 0x00000704
  219. #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
  220. /*----------------------------------------------------------------------------
  221. * BASE: SYSPM_SYSPM_REG
  222. *--------------------------------------------------------------------------*/
  223. #define SYSPM_SYSPM_REG_BASE 0x01f82000
  224. #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
  225. #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
  226. /*----------------------------------------------------------------------------
  227. * BASE: PMU_WLAN_PMU
  228. *--------------------------------------------------------------------------*/
  229. #define PMU_WLAN_PMU_BASE 0x01f88000
  230. #define PMU_WLAN_PMU_BASE_SIZE 0x00000338
  231. #define PMU_WLAN_PMU_BASE_PHYS 0x01f88000
  232. /*----------------------------------------------------------------------------
  233. * BASE: PMU_NOC
  234. *--------------------------------------------------------------------------*/
  235. #define PMU_NOC_BASE 0x01f8a000
  236. #define PMU_NOC_BASE_SIZE 0x00000080
  237. #define PMU_NOC_BASE_PHYS 0x01f8a000
  238. /*----------------------------------------------------------------------------
  239. * BASE: PCIE_ATU_REGION
  240. *--------------------------------------------------------------------------*/
  241. #define PCIE_ATU_REGION_BASE 0x04000000
  242. #define PCIE_ATU_REGION_BASE_SIZE 0x100000000
  243. #define PCIE_ATU_REGION_BASE_PHYS 0x04000000
  244. /*----------------------------------------------------------------------------
  245. * BASE: PCIE_ATU_REGION_SIZE
  246. *--------------------------------------------------------------------------*/
  247. #define PCIE_ATU_REGION_SIZE_BASE 0x40000000
  248. #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
  249. #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
  250. /*----------------------------------------------------------------------------
  251. * BASE: PCIE_ATU_REGION_END
  252. *--------------------------------------------------------------------------*/
  253. #define PCIE_ATU_REGION_END_BASE 0x43ffffff
  254. #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
  255. #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
  256. #endif /* __MSMHWIOBASE_H__ */