wbm_release_ring.h 16 KB

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  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _WBM_RELEASE_RING_H_
  17. #define _WBM_RELEASE_RING_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #include "buffer_addr_info.h"
  21. #define NUM_OF_DWORDS_WBM_RELEASE_RING 8
  22. struct wbm_release_ring {
  23. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  24. struct buffer_addr_info released_buff_or_desc_addr_info;
  25. uint32_t release_source_module : 3, // [2:0]
  26. reserved_2a : 3, // [5:3]
  27. buffer_or_desc_type : 3, // [8:6]
  28. reserved_2b : 22, // [30:9]
  29. wbm_internal_error : 1; // [31:31]
  30. uint32_t reserved_3a : 32; // [31:0]
  31. uint32_t reserved_4a : 32; // [31:0]
  32. uint32_t reserved_5a : 32; // [31:0]
  33. uint32_t reserved_6a : 32; // [31:0]
  34. uint32_t reserved_7a : 28, // [27:0]
  35. looping_count : 4; // [31:28]
  36. #else
  37. struct buffer_addr_info released_buff_or_desc_addr_info;
  38. uint32_t wbm_internal_error : 1, // [31:31]
  39. reserved_2b : 22, // [30:9]
  40. buffer_or_desc_type : 3, // [8:6]
  41. reserved_2a : 3, // [5:3]
  42. release_source_module : 3; // [2:0]
  43. uint32_t reserved_3a : 32; // [31:0]
  44. uint32_t reserved_4a : 32; // [31:0]
  45. uint32_t reserved_5a : 32; // [31:0]
  46. uint32_t reserved_6a : 32; // [31:0]
  47. uint32_t looping_count : 4, // [31:28]
  48. reserved_7a : 28; // [27:0]
  49. #endif
  50. };
  51. /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO
  52. DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or
  53. a 64-bit virtual address.
  54. */
  55. /* Description BUFFER_ADDR_31_0
  56. Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
  57. descriptor OR Link Descriptor
  58. In case of 'NULL' pointer, this field is set to 0
  59. <legal all>
  60. */
  61. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  62. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  63. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
  64. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  65. /* Description BUFFER_ADDR_39_32
  66. Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
  67. descriptor OR Link Descriptor
  68. In case of 'NULL' pointer, this field is set to 0
  69. <legal all>
  70. */
  71. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  72. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  73. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
  74. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  75. /* Description RETURN_BUFFER_MANAGER
  76. Consumer: WBM
  77. Producer: SW/FW
  78. In case of 'NULL' pointer, this field is set to 0
  79. Indicates to which buffer manager the buffer OR MSDU_EXTENSION
  80. descriptor OR link descriptor that is being pointed to
  81. shall be returned after the frame has been processed. It
  82. is used by WBM for routing purposes.
  83. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  84. to the WMB buffer idle list
  85. <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
  86. to the WBM idle link descriptor idle list, where the chip
  87. 0 WBM is chosen in case of a multi-chip config
  88. <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
  89. to the chip 1 WBM idle link descriptor idle list
  90. <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
  91. to the chip 2 WBM idle link descriptor idle list
  92. <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
  93. returned to chip 3 WBM idle link descriptor idle list
  94. <enum 4 FW_BM> This buffer shall be returned to the FW
  95. <enum 5 SW0_BM> This buffer shall be returned to the SW,
  96. ring 0
  97. <enum 6 SW1_BM> This buffer shall be returned to the SW,
  98. ring 1
  99. <enum 7 SW2_BM> This buffer shall be returned to the SW,
  100. ring 2
  101. <enum 8 SW3_BM> This buffer shall be returned to the SW,
  102. ring 3
  103. <enum 9 SW4_BM> This buffer shall be returned to the SW,
  104. ring 4
  105. <enum 10 SW5_BM> This buffer shall be returned to the SW,
  106. ring 5
  107. <enum 11 SW6_BM> This buffer shall be returned to the SW,
  108. ring 6
  109. <legal 0-12>
  110. */
  111. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  112. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  113. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
  114. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
  115. /* Description SW_BUFFER_COOKIE
  116. Cookie field exclusively used by SW.
  117. In case of 'NULL' pointer, this field is set to 0
  118. HW ignores the contents, accept that it passes the programmed
  119. value on to other descriptors together with the physical
  120. address
  121. Field can be used by SW to for example associate the buffers
  122. physical address with the virtual address
  123. The bit definitions as used by SW are within SW HLD specification
  124. NOTE1:
  125. The three most significant bits can have a special meaning
  126. in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
  127. and field transmit_bw_restriction is set
  128. In case of NON punctured transmission:
  129. Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
  130. Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
  131. Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
  132. Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
  133. Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
  134. Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
  135. Sw_buffer_cookie[19:18] = 2'b11: reserved
  136. In case of punctured transmission:
  137. Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
  138. Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
  139. Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
  140. Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
  141. Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
  142. Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
  143. Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
  144. Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
  145. Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
  146. Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
  147. Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
  148. Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
  149. Sw_buffer_cookie[19:18] = 2'b11: reserved
  150. Note: a punctured transmission is indicated by the presence
  151. of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
  152. <legal all>
  153. */
  154. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  155. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
  156. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
  157. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
  158. /* Description RELEASE_SOURCE_MODULE
  159. Indicates which module initiated the release of this buffer
  160. or descriptor
  161. <enum 1 release_source_RXDMA> RXDMA released this buffer
  162. or descriptor
  163. <enum 2 release_source_REO> REO released this buffer or
  164. descriptor
  165. <enum 5 release_source_FW_RX> FW released this buffer or
  166. descriptor
  167. <enum 4 release_source_SW_RX> SW released this buffer or
  168. descriptor
  169. <enum 0 release_source_TQM> DO NOT USE
  170. <enum 3 release_source_FW_TX> DO NOT USE
  171. <enum 6 release_source_SW_TX> DO NOT USE
  172. <legal 0-6>
  173. */
  174. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
  175. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0
  176. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2
  177. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007
  178. /* Description RESERVED_2A
  179. This could be different fields depending on the structure.
  180. <legal all>
  181. */
  182. #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008
  183. #define WBM_RELEASE_RING_RESERVED_2A_LSB 3
  184. #define WBM_RELEASE_RING_RESERVED_2A_MSB 5
  185. #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038
  186. /* Description BUFFER_OR_DESC_TYPE
  187. Consumer: WBM/SW/FW
  188. Producer: SW/TQM/RXDMA/REO/SWITCH
  189. Field only valid when WBM is marked as the return_buffer_manager
  190. in the Released_Buffer_address_info
  191. Indicates that type of buffer or descriptor is being released
  192. <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer
  193. <enum 1 msdu_link_descriptor> The address points to an TX
  194. MSDU link descriptor
  195. <enum 2 mpdu_link_descriptor> The address points to an MPDU
  196. link descriptor
  197. <enum 3 msdu_ext_descriptor > The address points to an MSDU
  198. extension descriptor.
  199. In case BM finds this one in a release ring, it passes it
  200. on to FW...
  201. <enum 4 queue_ext_descriptor> The address points to an TQM
  202. queue extension descriptor. WBM should treat this is the
  203. same way as a link descriptor. That is, put the 128 byte
  204. buffer back in the link buffer idle list.
  205. TODO: Any restrictions?
  206. <legal 0-4>
  207. */
  208. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
  209. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6
  210. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8
  211. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
  212. /* Description RESERVED_2B
  213. This could be different fields depending on the structure.
  214. <legal all>
  215. */
  216. #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008
  217. #define WBM_RELEASE_RING_RESERVED_2B_LSB 9
  218. #define WBM_RELEASE_RING_RESERVED_2B_MSB 30
  219. #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00
  220. /* Description WBM_INTERNAL_ERROR
  221. Can only be set by WBM.
  222. Is set when WBM got a buffer pointer but the action was
  223. to push it to the idle link descriptor ring or do link related
  224. activity
  225. OR
  226. Is set when WBM got a link buffer pointer but the action
  227. was to push it to the buffer descriptor ring
  228. <legal all>
  229. */
  230. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008
  231. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31
  232. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31
  233. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000
  234. /* Description RESERVED_3A
  235. This could be different fields depending on the structure.
  236. <legal all>
  237. */
  238. #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c
  239. #define WBM_RELEASE_RING_RESERVED_3A_LSB 0
  240. #define WBM_RELEASE_RING_RESERVED_3A_MSB 31
  241. #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff
  242. /* Description RESERVED_4A
  243. This could be different fields depending on the structure.
  244. <legal all>
  245. */
  246. #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010
  247. #define WBM_RELEASE_RING_RESERVED_4A_LSB 0
  248. #define WBM_RELEASE_RING_RESERVED_4A_MSB 31
  249. #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff
  250. /* Description RESERVED_5A
  251. This could be different fields depending on the structure.
  252. <legal all>
  253. */
  254. #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014
  255. #define WBM_RELEASE_RING_RESERVED_5A_LSB 0
  256. #define WBM_RELEASE_RING_RESERVED_5A_MSB 31
  257. #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff
  258. /* Description RESERVED_6A
  259. This could be different fields depending on the structure.
  260. <legal all>
  261. */
  262. #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018
  263. #define WBM_RELEASE_RING_RESERVED_6A_LSB 0
  264. #define WBM_RELEASE_RING_RESERVED_6A_MSB 31
  265. #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff
  266. /* Description RESERVED_7A
  267. This could be different fields depending on the structure.
  268. <legal all>
  269. */
  270. #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c
  271. #define WBM_RELEASE_RING_RESERVED_7A_LSB 0
  272. #define WBM_RELEASE_RING_RESERVED_7A_MSB 27
  273. #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff
  274. /* Description LOOPING_COUNT
  275. Consumer: WBM/SW/FW
  276. Producer: SW/TQM/RXDMA/REO/SWITCH
  277. If WBM_internal_error is set, this descriptor is sent to
  278. the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count
  279. is used to indicate an error code.
  280. The values reported are documented further in the WBM MLD
  281. doc.
  282. If WBM_internal_error is not set, the following holds.
  283. A count value that indicates the number of times the producer
  284. of entries into the Buffer Manager Ring has looped around
  285. the ring.
  286. At initialization time, this value is set to 0. On the first
  287. loop, this value is set to 1. After the max value is reached
  288. allowed by the number of bits for this field, the count
  289. value continues with 0 again.
  290. In case SW is the consumer of the ring entries, it can use
  291. this field to figure out up to where the producer of entries
  292. has created new entries. This eliminates the need to check
  293. where the "head pointer' of the ring is located once the
  294. SW starts processing an interrupt indicating that new entries
  295. have been put into this ring...
  296. Also note that SW if it wants only needs to look at the
  297. LSB bit of this count value.
  298. <legal all>
  299. */
  300. #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c
  301. #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28
  302. #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31
  303. #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000
  304. #endif // WBM_RELEASE_RING