uniform_descriptor_header.h 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135
  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
  17. #define _UNIFORM_DESCRIPTOR_HEADER_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
  21. struct uniform_descriptor_header {
  22. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  23. uint32_t owner : 4, // [3:0]
  24. buffer_type : 4, // [7:4]
  25. tx_mpdu_queue_number : 20, // [27:8]
  26. reserved_0a : 4; // [31:28]
  27. #else
  28. uint32_t reserved_0a : 4, // [31:28]
  29. tx_mpdu_queue_number : 20, // [27:8]
  30. buffer_type : 4, // [7:4]
  31. owner : 4; // [3:0]
  32. #endif
  33. };
  34. /* Description OWNER
  35. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  36. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  37. The owner of this data structure:
  38. <enum 0 WBM_owned> Buffer Manager currently owns this data
  39. structure.
  40. <enum 1 SW_OR_FW_owned> Software of FW currently owns this
  41. data structure.
  42. <enum 2 TQM_owned> Transmit Queue Manager currently owns
  43. this data structure.
  44. <enum 3 RXDMA_owned> Receive DMA currently owns this data
  45. structure.
  46. <enum 4 REO_owned> Reorder currently owns this data structure.
  47. <enum 5 SWITCH_owned> SWITCH currently owns this data structure.
  48. <legal 0-5>
  49. */
  50. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
  51. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0
  52. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3
  53. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
  54. /* Description BUFFER_TYPE
  55. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  56. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  57. Field describing what contents format is of this descriptor
  58. <enum 0 Transmit_MSDU_Link_descriptor>
  59. <enum 1 Transmit_MPDU_Link_descriptor>
  60. <enum 2 Transmit_MPDU_Queue_head_descriptor>
  61. <enum 3 Transmit_MPDU_Queue_ext_descriptor>
  62. <enum 4 Transmit_flow_descriptor>
  63. <enum 5 Transmit_buffer> NOT TO BE USED:
  64. <enum 6 Receive_MSDU_Link_descriptor>
  65. <enum 7 Receive_MPDU_Link_descriptor>
  66. <enum 8 Receive_REO_queue_descriptor>
  67. <enum 9 Receive_REO_queue_1k_descriptor>
  68. <enum 10 Receive_REO_queue_ext_descriptor>
  69. <enum 11 Receive_buffer>
  70. <enum 12 Idle_link_list_entry>
  71. <legal 0-12>
  72. */
  73. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
  74. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
  75. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
  76. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
  77. /* Description TX_MPDU_QUEUE_NUMBER
  78. Consumer: TQM/Debug
  79. Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
  80. Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
  81. Indicates the MPDU queue ID to which this MPDU descriptor
  82. belongs
  83. Used for tracking and debugging
  84. <legal all>
  85. */
  86. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
  87. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
  88. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
  89. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
  90. /* Description RESERVED_0A
  91. <legal 0>
  92. */
  93. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
  94. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
  95. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
  96. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
  97. #endif // UNIFORM_DESCRIPTOR_HEADER