reo_unblock_cache.h 11 KB

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  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _REO_UNBLOCK_CACHE_H_
  17. #define _REO_UNBLOCK_CACHE_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #include "uniform_reo_cmd_header.h"
  21. #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
  22. #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
  23. struct reo_unblock_cache {
  24. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  25. struct uniform_reo_cmd_header cmd_header;
  26. uint32_t unblock_type : 1, // [0:0]
  27. cache_block_resource_index : 2, // [2:1]
  28. reserved_1a : 29; // [31:3]
  29. uint32_t reserved_2a : 32; // [31:0]
  30. uint32_t reserved_3a : 32; // [31:0]
  31. uint32_t reserved_4a : 32; // [31:0]
  32. uint32_t reserved_5a : 32; // [31:0]
  33. uint32_t reserved_6a : 32; // [31:0]
  34. uint32_t reserved_7a : 32; // [31:0]
  35. uint32_t reserved_8a : 32; // [31:0]
  36. uint32_t tlv64_padding : 32; // [31:0]
  37. #else
  38. struct uniform_reo_cmd_header cmd_header;
  39. uint32_t reserved_1a : 29, // [31:3]
  40. cache_block_resource_index : 2, // [2:1]
  41. unblock_type : 1; // [0:0]
  42. uint32_t reserved_2a : 32; // [31:0]
  43. uint32_t reserved_3a : 32; // [31:0]
  44. uint32_t reserved_4a : 32; // [31:0]
  45. uint32_t reserved_5a : 32; // [31:0]
  46. uint32_t reserved_6a : 32; // [31:0]
  47. uint32_t reserved_7a : 32; // [31:0]
  48. uint32_t reserved_8a : 32; // [31:0]
  49. uint32_t tlv64_padding : 32; // [31:0]
  50. #endif
  51. };
  52. /* Description CMD_HEADER
  53. Consumer: REO
  54. Producer: SW
  55. Details for command execution tracking purposes.
  56. */
  57. /* Description REO_CMD_NUMBER
  58. Consumer: REO/SW/DEBUG
  59. Producer: SW
  60. This number can be used by SW to track, identify and link
  61. the created commands with the command statusses
  62. <legal all>
  63. */
  64. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
  65. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
  66. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
  67. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
  68. /* Description REO_STATUS_REQUIRED
  69. Consumer: REO
  70. Producer: SW
  71. <enum 0 NoStatus> REO does not need to generate a status
  72. TLV for the execution of this command
  73. <enum 1 StatusRequired> REO shall generate a status TLV
  74. for the execution of this command
  75. <legal all>
  76. */
  77. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
  78. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
  79. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
  80. #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
  81. /* Description RESERVED_0A
  82. <legal 0>
  83. */
  84. #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
  85. #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
  86. #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
  87. #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
  88. /* Description UNBLOCK_TYPE
  89. Unblock type
  90. <enum 0 unblock_resource_index> Unblock a block resource,
  91. whose index is given in field 'cache_block_resource_index'.
  92. If the indicated blocking resource is not in use (=> not
  93. blocking an address at the moment), the command status
  94. will indicate an error.
  95. <enum 1 unblock_cache> The entire cache usage is unblocked.
  96. If the entire cache is not in a blocked mode at the moment
  97. this command is received, the command status will indicate
  98. an error.
  99. Note that unlocking the "entire cache" has no changes to
  100. the current settings of the blocking resource settings
  101. <legal all>
  102. */
  103. #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000
  104. #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32
  105. #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32
  106. #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000
  107. /* Description CACHE_BLOCK_RESOURCE_INDEX
  108. Field not valid when field Unblock_type is set to unblock_cache.
  109. Indicates which of the four blocking resources in REO should
  110. be released from blocking a (descriptor) address.
  111. <legal all>
  112. */
  113. #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000
  114. #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33
  115. #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34
  116. #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000
  117. /* Description RESERVED_1A
  118. <legal 0>
  119. */
  120. #define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000
  121. #define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35
  122. #define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63
  123. #define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000
  124. /* Description RESERVED_2A
  125. <legal 0>
  126. */
  127. #define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008
  128. #define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0
  129. #define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31
  130. #define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff
  131. /* Description RESERVED_3A
  132. <legal 0>
  133. */
  134. #define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
  135. #define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32
  136. #define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63
  137. #define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000
  138. /* Description RESERVED_4A
  139. <legal 0>
  140. */
  141. #define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
  142. #define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0
  143. #define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31
  144. #define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
  145. /* Description RESERVED_5A
  146. <legal 0>
  147. */
  148. #define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
  149. #define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32
  150. #define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63
  151. #define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000
  152. /* Description RESERVED_6A
  153. <legal 0>
  154. */
  155. #define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
  156. #define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0
  157. #define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31
  158. #define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
  159. /* Description RESERVED_7A
  160. <legal 0>
  161. */
  162. #define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
  163. #define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32
  164. #define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63
  165. #define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000
  166. /* Description RESERVED_8A
  167. <legal 0>
  168. */
  169. #define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
  170. #define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0
  171. #define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31
  172. #define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
  173. /* Description TLV64_PADDING
  174. Automatic DWORD padding inserted while converting TLV32
  175. to TLV64 for 64 bit ARCH
  176. <legal 0>
  177. */
  178. #define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
  179. #define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32
  180. #define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63
  181. #define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
  182. #endif // REO_UNBLOCK_CACHE