android_kernel_samsung_sm8650-modules/hw/qca9574/wcss_seq_hwiobase.h

/*
 * Copyright (c) 2021 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq  3.10 1/18/2021 
// User Name:c_bipink
//
// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////

#ifndef __WCSS_SEQ_BASE_H__
#define __WCSS_SEQ_BASE_H__

#ifdef SCALE_INCLUDES
	#include "HALhwio.h"
#else
	#include "msmhwio.h"
#endif


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcss
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_WCSS_ECAHB_OFFSET                                        0x00008000
#define SEQ_WCSS_ECAHB_TSLV_OFFSET                                   0x00009000
#define SEQ_WCSS_UMAC_NOC_OFFSET                                     0x00140000
#define SEQ_WCSS_MPSS_OFFSET                                         0x00200000
#define SEQ_WCSS_MPSS_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET          0x00200000
#define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_OFFSET                     0x00280000
#define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET          0x00281800
#define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET            0x00281c00
#define SEQ_WCSS_PHYB_OFFSET                                         0x00800000
#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET               0x00800000
#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET                     0x00880000
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET               0x00880400
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET               0x00880800
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET               0x00880c00
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET               0x00881000
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET               0x00881400
#define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET          0x00881800
#define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET            0x00881c00
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET               0x00882c00
#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET                      0x00884000
#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET                     0x00888000
#define SEQ_WCSS_PHYB_WFAX_TXBF_B_REG_MAP_OFFSET                     0x008e8000
#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET                     0x00918000
#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET                     0x00920000
#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET                     0x00928000
#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET                 0x00930000
#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET                    0x009a0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET                   0x009c0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET           0x009c0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET   0x009c0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x009c0140
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET  0x009c4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET   0x009c8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET           0x009d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET       0x009d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET    0x009d4300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET    0x009d4800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET   0x009d7c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET            0x009e0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET  0x009e0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x009e1600
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET  0x009e1640
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET  0x009e8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x009e9600
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET  0x009e9640
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET  0x009f0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x009f1600
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET  0x009f1640
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET  0x009f8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x009f9600
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET  0x009f9640
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000
#define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET                           0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET        0x00a18000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                0x00a22000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET            0x00a24000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET                 0x00a26000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET                 0x00a28000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET                 0x00a2a000
#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET                          0x00a30000
#define SEQ_WCSS_UMAC_WBM_REG_OFFSET                                 0x00a34000
#define SEQ_WCSS_UMAC_REO_REG_OFFSET                                 0x00a38000
#define SEQ_WCSS_UMAC_TQM_REG_OFFSET                                 0x00a3c000
#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET                           0x00a40000
#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET                             0x00a44000
#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET                      0x00a47000
#define SEQ_WCSS_UMAC_MAC_CCE_TCL_REG_OFFSET                         0x00a4a000
#define SEQ_WCSS_WMAC2_OFFSET                                        0x00b00000
#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET                            0x00b00000
#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET                          0x00b03000
#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET                          0x00b06000
#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET                           0x00b09000
#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET                          0x00b0c000
#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET                          0x00b0f000
#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET                           0x00b12000
#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET                          0x00b15000
#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET                   0x00b18000
#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET                            0x00b1b000
#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET                          0x00b1e000
#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET                   0x00b21000
#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET                            0x00b24000
#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET                         0x00b27000
#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET                          0x00b2a000
#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET                            0x00b30000
#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET                            0x00b33000
#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET                         0x00b36000
#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET                           0x00b39000
#define SEQ_WCSS_APB_TSLV_OFFSET                                     0x00b40000
#define SEQ_WCSS_WCMN_OFFSET                                         0x00b50000
#define SEQ_WCSS_WFSS_PMM_OFFSET                                     0x00b60000
#define SEQ_WCSS_MSIP_OFFSET                                         0x00b80000
#define SEQ_WCSS_MSIP_PLL_OFFSET                                     0x00b80000
#define SEQ_WCSS_MSIP_BIASCLKS_OFFSET                                0x00b80100
#define SEQ_WCSS_MSIP_XO_OFFSET                                      0x00b84000
#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET                                0x00b84140
#define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET              0x00b8c000
#define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH0_OFFSET                       0x00b8c100
#define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH0_OFFSET                         0x00b8c180
#define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET          0x00b8c1c0
#define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET                    0x00b8c2c0
#define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH0_OFFSET                         0x00b8c340
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET         0x00b8c400
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET          0x00b8c440
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET         0x00b8c480
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET          0x00b8c4c0
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET             0x00b8c500
#define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET                    0x00b8c600
#define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET              0x00b8c800
#define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH1_OFFSET                       0x00b8c900
#define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH1_OFFSET                         0x00b8c980
#define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET          0x00b8c9c0
#define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET                    0x00b8cac0
#define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH1_OFFSET                         0x00b8cb40
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET         0x00b8cc00
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET          0x00b8cc40
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET         0x00b8cc80
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET          0x00b8ccc0
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET             0x00b8cd00
#define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET                    0x00b8ce00
#define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET              0x00b8d000
#define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH2_OFFSET                       0x00b8d100
#define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH2_OFFSET                         0x00b8d180
#define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET          0x00b8d1c0
#define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET                    0x00b8d2c0
#define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH2_OFFSET                         0x00b8d340
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET         0x00b8d400
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET          0x00b8d440
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET         0x00b8d480
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET          0x00b8d4c0
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET             0x00b8d500
#define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET                    0x00b8d600
#define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET              0x00b8d800
#define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH3_OFFSET                       0x00b8d900
#define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH3_OFFSET                         0x00b8d980
#define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET          0x00b8d9c0
#define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET                    0x00b8dac0
#define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH3_OFFSET                         0x00b8db40
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET         0x00b8dc00
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET          0x00b8dc40
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET         0x00b8dc80
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET          0x00b8dcc0
#define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET             0x00b8dd00
#define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET                    0x00b8de00
#define SEQ_WCSS_PMM_OFFSET                                          0x00b70000
#define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
#define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET                      0x00b90000
#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET                         0x00b91000
#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET                            0x00b92000
#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET                    0x00b94000
#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET  0x00b98000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET     0x00b99000
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000
#define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET        0x00b9a000
#define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET                  0x00b9b000
#define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET                        0x00b9c000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_OFFSET                         0x00ba0000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET           0x00ba0000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00ba8000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00ba9000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET     0x00baa000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET     0x00bab000
#define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET     0x00bac000
#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bb8000
#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET                  0x00bb9000
#define SEQ_WCSS_DBG_PHYA_TRC_PHYTRC_CTRL_OFFSET                     0x00bba000
#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bc8000
#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET                  0x00bc9000
#define SEQ_WCSS_DBG_PHYB_TRC_PHYTRC_CTRL_OFFSET                     0x00bca000
#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET                        0x00bc0000
#define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET                      0x00bce000
#define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET                       0x00bf8000
#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00bf9000
#define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c10000
#define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00c20000
#define SEQ_WCSS_CC_OFFSET                                           0x00c30000
#define SEQ_WCSS_ACMT_OFFSET                                         0x00c40000
#define SEQ_WCSS_WRAPPER_ACMT_OFFSET                                 0x00c60000
#define SEQ_WCSS_Q6SS_WLAN_OFFSET                                    0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET                         0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET       0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET      0x00d80000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000
#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block mpss_top
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_MPSS_TOP_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET           0x00000000
#define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_OFFSET                      0x00080000
#define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET           0x00081800
#define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET             0x00081c00


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfax_top_b
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET              0x00000000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET                    0x00080000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET              0x00080400
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET              0x00080800
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET              0x00080c00
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET              0x00081000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET              0x00081400
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET         0x00081800
#define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET           0x00081c00
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET              0x00082c00
#define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET                     0x00084000
#define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET                    0x00088000
#define SEQ_WFAX_TOP_B_WFAX_TXBF_B_REG_MAP_OFFSET                    0x000e8000
#define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET                    0x00118000
#define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET                    0x00120000
#define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET                    0x00128000
#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET                0x00130000
#define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET                   0x001a0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET                  0x001c0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET          0x001c0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET  0x001c0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x001c0140
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x001c4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET  0x001c8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET          0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET      0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET   0x001d4300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET   0x001d4800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET  0x001d7c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET           0x001e0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x001e1600
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x001e1640
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x001e9600
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x001e9640
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x001f1600
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x001f1640
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x001f9600
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x001f9640
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block iron2g
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_IRON2G_RFA_DIG_OFFSET                                    0x00000000
#define SEQ_IRON2G_RFA_DIG_RFA_OTP_OFFSET                            0x00000000
#define SEQ_IRON2G_RFA_DIG_RFA_OTP_CTRL_OFFSET                       0x00000140
#define SEQ_IRON2G_RFA_DIG_RFA_TLMM_OFFSET                           0x00004000
#define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET                            0x00008000
#define SEQ_IRON2G_RFA_CMN_OFFSET                                    0x00014000
#define SEQ_IRON2G_RFA_CMN_AON_OFFSET                                0x00014000
#define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET                             0x00014300
#define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET                             0x00014800
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET                       0x00016000
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                     0x00016040
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET                     0x00016080
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET                       0x000160c0
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                     0x00016100
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET                       0x00016140
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_LO_OFFSET                       0x00016200
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET                       0x00016800
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                     0x00016840
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET                     0x00016880
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET                       0x000168c0
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                     0x00016900
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET                       0x00016940
#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_LO_OFFSET                       0x00016a00
#define SEQ_IRON2G_RFA_CMN_DRM_REG_OFFSET                            0x00017c00
#define SEQ_IRON2G_RFA_WL_OFFSET                                     0x00020000
#define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET                           0x00020000
#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET                         0x00020400
#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET                         0x00020800
#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH0_OFFSET                        0x00021000
#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH0_OFFSET                        0x00021180
#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH0_OFFSET                        0x00021300
#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH0_OFFSET                        0x00021480
#define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH0_OFFSET                       0x00021600
#define SEQ_IRON2G_RFA_WL_WL_LO_CH0_OFFSET                           0x00021640
#define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET                          0x00022000
#define SEQ_IRON2G_RFA_WL_WL_MEM_CH0_OFFSET                          0x00024000
#define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET                           0x00028000
#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET                         0x00028400
#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET                         0x00028800
#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH1_OFFSET                        0x00029000
#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH1_OFFSET                        0x00029180
#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH1_OFFSET                        0x00029300
#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH1_OFFSET                        0x00029480
#define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH1_OFFSET                       0x00029600
#define SEQ_IRON2G_RFA_WL_WL_LO_CH1_OFFSET                           0x00029640
#define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET                          0x0002a000
#define SEQ_IRON2G_RFA_WL_WL_MEM_CH1_OFFSET                          0x0002c000
#define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET                           0x00030000
#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET                         0x00030400
#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET                         0x00030800
#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH2_OFFSET                        0x00031000
#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH2_OFFSET                        0x00031180
#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH2_OFFSET                        0x00031300
#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH2_OFFSET                        0x00031480
#define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH2_OFFSET                       0x00031600
#define SEQ_IRON2G_RFA_WL_WL_LO_CH2_OFFSET                           0x00031640
#define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET                          0x00032000
#define SEQ_IRON2G_RFA_WL_WL_MEM_CH2_OFFSET                          0x00034000
#define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET                           0x00038000
#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET                         0x00038400
#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET                         0x00038800
#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH3_OFFSET                        0x00039000
#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH3_OFFSET                        0x00039180
#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH3_OFFSET                        0x00039300
#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH3_OFFSET                        0x00039480
#define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH3_OFFSET                       0x00039600
#define SEQ_IRON2G_RFA_WL_WL_LO_CH3_OFFSET                           0x00039640
#define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET                          0x0003a000
#define SEQ_IRON2G_RFA_WL_WL_MEM_CH3_OFFSET                          0x0003c000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_dig
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_DIG_RFA_OTP_OFFSET                                   0x00000000
#define SEQ_RFA_DIG_RFA_OTP_CTRL_OFFSET                              0x00000140
#define SEQ_RFA_DIG_RFA_TLMM_OFFSET                                  0x00004000
#define SEQ_RFA_DIG_SYSCTRL_OFFSET                                   0x00008000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_cmn
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
#define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
#define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000800
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002000
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002040
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002080
#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x000020c0
#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002100
#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x00002140
#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET                              0x00002200
#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00002800
#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00002840
#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00002880
#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x000028c0
#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00002900
#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x00002940
#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET                              0x00002a00
#define SEQ_RFA_CMN_DRM_REG_OFFSET                                   0x00003c00


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_wl
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_WL_WL_MC_CH0_OFFSET                                  0x00000000
#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET                                0x00000400
#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET                                0x00000800
#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET                               0x00001000
#define SEQ_RFA_WL_WL_RXFE5_CH0_OFFSET                               0x00001180
#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET                               0x00001300
#define SEQ_RFA_WL_WL_TXFE5_CH0_OFFSET                               0x00001480
#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET                              0x00001600
#define SEQ_RFA_WL_WL_LO_CH0_OFFSET                                  0x00001640
#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET                                 0x00002000
#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET                                 0x00004000
#define SEQ_RFA_WL_WL_MC_CH1_OFFSET                                  0x00008000
#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET                                0x00008400
#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET                                0x00008800
#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET                               0x00009000
#define SEQ_RFA_WL_WL_RXFE5_CH1_OFFSET                               0x00009180
#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET                               0x00009300
#define SEQ_RFA_WL_WL_TXFE5_CH1_OFFSET                               0x00009480
#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET                              0x00009600
#define SEQ_RFA_WL_WL_LO_CH1_OFFSET                                  0x00009640
#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET                                 0x0000a000
#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET                                 0x0000c000
#define SEQ_RFA_WL_WL_MC_CH2_OFFSET                                  0x00010000
#define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET                                0x00010400
#define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET                                0x00010800
#define SEQ_RFA_WL_WL_RXFE2_CH2_OFFSET                               0x00011000
#define SEQ_RFA_WL_WL_RXFE5_CH2_OFFSET                               0x00011180
#define SEQ_RFA_WL_WL_TXFE2_CH2_OFFSET                               0x00011300
#define SEQ_RFA_WL_WL_TXFE5_CH2_OFFSET                               0x00011480
#define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET                              0x00011600
#define SEQ_RFA_WL_WL_LO_CH2_OFFSET                                  0x00011640
#define SEQ_RFA_WL_WL_TPC_CH2_OFFSET                                 0x00012000
#define SEQ_RFA_WL_WL_MEM_CH2_OFFSET                                 0x00014000
#define SEQ_RFA_WL_WL_MC_CH3_OFFSET                                  0x00018000
#define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET                                0x00018400
#define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET                                0x00018800
#define SEQ_RFA_WL_WL_RXFE2_CH3_OFFSET                               0x00019000
#define SEQ_RFA_WL_WL_RXFE5_CH3_OFFSET                               0x00019180
#define SEQ_RFA_WL_WL_TXFE2_CH3_OFFSET                               0x00019300
#define SEQ_RFA_WL_WL_TXFE5_CH3_OFFSET                               0x00019480
#define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET                              0x00019600
#define SEQ_RFA_WL_WL_LO_CH3_OFFSET                                  0x00019640
#define SEQ_RFA_WL_WL_TPC_CH3_OFFSET                                 0x0001a000
#define SEQ_RFA_WL_WL_MEM_CH3_OFFSET                                 0x0001c000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block umac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET                        0x00000000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET     0x00018000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET                          0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET              0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET             0x00022000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET         0x00024000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET              0x00026000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET              0x00028000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET              0x0002a000
#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET                       0x00030000
#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET                              0x00034000
#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET                              0x00038000
#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET                              0x0003c000
#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET                        0x00040000
#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET                          0x00044000
#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET                   0x00047000
#define SEQ_UMAC_TOP_REG_MAC_CCE_TCL_REG_OFFSET                      0x0004a000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfss_ce_reg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET             0x00000000
#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET             0x00001000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET             0x00002000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET             0x00003000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET             0x00004000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET             0x00005000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET             0x00006000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET             0x00007000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET             0x00008000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET             0x00009000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET             0x0000a000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET             0x0000b000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET             0x0000c000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET             0x0000d000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET             0x0000e000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET             0x0000f000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET             0x00010000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET             0x00011000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET             0x00012000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET             0x00013000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET            0x00014000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET            0x00015000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET            0x00016000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET            0x00017000
#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET                    0x00018000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block cxc_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET                           0x00000000
#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                          0x00002000
#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET                      0x00004000
#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET                           0x00006000
#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET                           0x00008000
#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET                           0x0000a000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wmac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET                          0x00000000
#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET                        0x00003000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET                        0x00006000
#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET                         0x00009000
#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET                        0x0000c000
#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET                        0x0000f000
#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET                         0x00012000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET                        0x00015000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET                 0x00018000
#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0001b000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET                        0x0001e000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET                 0x00021000
#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET                          0x00024000
#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET                       0x00027000
#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET                        0x0002a000
#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET                          0x00030000
#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET                          0x00033000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET                       0x00036000
#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET                         0x00039000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block msip
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_MSIP_PLL_OFFSET                                          0x00000000
#define SEQ_MSIP_BIASCLKS_OFFSET                                     0x00000100
#define SEQ_MSIP_XO_OFFSET                                           0x00004000
#define SEQ_MSIP_MSIP_OTP_OFFSET                                     0x00004140
#define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET                   0x0000c000
#define SEQ_MSIP_RBIST_RX_PHYA_CH0_OFFSET                            0x0000c100
#define SEQ_MSIP_WL_DAC_PHYA_CH0_OFFSET                              0x0000c180
#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET               0x0000c1c0
#define SEQ_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET                         0x0000c2c0
#define SEQ_MSIP_WL_ADC_PHYA_CH0_OFFSET                              0x0000c340
#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET              0x0000c400
#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET               0x0000c440
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET              0x0000c480
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET               0x0000c4c0
#define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET                  0x0000c500
#define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET                         0x0000c600
#define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET                   0x0000c800
#define SEQ_MSIP_RBIST_RX_PHYA_CH1_OFFSET                            0x0000c900
#define SEQ_MSIP_WL_DAC_PHYA_CH1_OFFSET                              0x0000c980
#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET               0x0000c9c0
#define SEQ_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET                         0x0000cac0
#define SEQ_MSIP_WL_ADC_PHYA_CH1_OFFSET                              0x0000cb40
#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET              0x0000cc00
#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET               0x0000cc40
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET              0x0000cc80
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET               0x0000ccc0
#define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET                  0x0000cd00
#define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET                         0x0000ce00
#define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET                   0x0000d000
#define SEQ_MSIP_RBIST_RX_PHYA_CH2_OFFSET                            0x0000d100
#define SEQ_MSIP_WL_DAC_PHYA_CH2_OFFSET                              0x0000d180
#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET               0x0000d1c0
#define SEQ_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET                         0x0000d2c0
#define SEQ_MSIP_WL_ADC_PHYA_CH2_OFFSET                              0x0000d340
#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET              0x0000d400
#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET               0x0000d440
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET              0x0000d480
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET               0x0000d4c0
#define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET                  0x0000d500
#define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET                         0x0000d600
#define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET                   0x0000d800
#define SEQ_MSIP_RBIST_RX_PHYA_CH3_OFFSET                            0x0000d900
#define SEQ_MSIP_WL_DAC_PHYA_CH3_OFFSET                              0x0000d980
#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET               0x0000d9c0
#define SEQ_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET                         0x0000dac0
#define SEQ_MSIP_WL_ADC_PHYA_CH3_OFFSET                              0x0000db40
#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET              0x0000dc00
#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET               0x0000dc40
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET              0x0000dc80
#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET               0x0000dcc0
#define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET                  0x0000dd00
#define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET                         0x0000de00


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcssdbg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET                       0x00000000
#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET                          0x00001000
#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET                             0x00002000
#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET                     0x00004000
#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET                      0x00005000
#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                     0x00006000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET   0x00008000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET      0x00009000
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000
#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET         0x0000a000
#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET                   0x0000b000
#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET                         0x0000c000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_OFFSET                          0x00010000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET            0x00010000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00018000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET  0x00019000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET      0x0001a000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET      0x0001b000
#define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET      0x0001c000
#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET               0x00028000
#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET                   0x00029000
#define SEQ_WCSSDBG_PHYA_TRC_PHYTRC_CTRL_OFFSET                      0x0002a000
#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET               0x00038000
#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET                   0x00039000
#define SEQ_WCSSDBG_PHYB_TRC_PHYTRC_CTRL_OFFSET                      0x0003a000
#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET                         0x00030000
#define SEQ_WCSSDBG_PHYB_CPU0_M3_AHB_AP_OFFSET                       0x0003e000
#define SEQ_WCSSDBG_UMAC_CPU_M3_AHB_AP_OFFSET                        0x00068000
#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET                               0x00069000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block umac_dbg
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_UMAC_DBG_UNOC_UMAC_NOC_OFFSET                            0x00000000
#define SEQ_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00008000
#define SEQ_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET                  0x00009000
#define SEQ_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET                      0x0000a000
#define SEQ_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET                      0x0000b000
#define SEQ_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET                      0x0000c000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_wlan
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET                        0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET      0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET     0x00080000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000
#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET                      0x00000000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET       0x00000000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET                     0x00080000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET      0x00080000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET    0x00090000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET     0x000a0000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET             0x000a1000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET             0x000a2000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET             0x000a3000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET     0x000b0000
#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_public
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET                  0x00000000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6v67ss_private
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET                 0x00000000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET               0x00010000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET                0x00020000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET                        0x00021000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET                        0x00022000
#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET                        0x00023000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET                0x00030000
#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET       0x00030000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block q6ss_rscc
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET                                0x00000000


#endif