tcl_status_ring.h 8.8 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _TCL_STATUS_RING_H_
  6. #define _TCL_STATUS_RING_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #define NUM_OF_DWORDS_TCL_STATUS_RING 8
  10. struct tcl_status_ring {
  11. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  12. uint32_t gse_ctrl : 4,
  13. ase_fse_sel : 1,
  14. cache_op_res : 2,
  15. index_search_en : 1,
  16. msdu_cnt_n : 24;
  17. uint32_t msdu_byte_cnt_n : 32;
  18. uint32_t msdu_timestmp_n : 32;
  19. uint32_t cmd_meta_data_31_0 : 32;
  20. uint32_t cmd_meta_data_63_32 : 32;
  21. uint32_t hash_indx_val : 20,
  22. cache_set_num : 4,
  23. reserved_5a : 8;
  24. uint32_t reserved_6a : 32;
  25. uint32_t reserved_7a : 20,
  26. ring_id : 8,
  27. looping_count : 4;
  28. #else
  29. uint32_t msdu_cnt_n : 24,
  30. index_search_en : 1,
  31. cache_op_res : 2,
  32. ase_fse_sel : 1,
  33. gse_ctrl : 4;
  34. uint32_t msdu_byte_cnt_n : 32;
  35. uint32_t msdu_timestmp_n : 32;
  36. uint32_t cmd_meta_data_31_0 : 32;
  37. uint32_t cmd_meta_data_63_32 : 32;
  38. uint32_t reserved_5a : 8,
  39. cache_set_num : 4,
  40. hash_indx_val : 20;
  41. uint32_t reserved_6a : 32;
  42. uint32_t looping_count : 4,
  43. ring_id : 8,
  44. reserved_7a : 20;
  45. #endif
  46. };
  47. #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000
  48. #define TCL_STATUS_RING_GSE_CTRL_LSB 0
  49. #define TCL_STATUS_RING_GSE_CTRL_MSB 3
  50. #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f
  51. #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000
  52. #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4
  53. #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4
  54. #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010
  55. #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000
  56. #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5
  57. #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6
  58. #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060
  59. #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000
  60. #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7
  61. #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7
  62. #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080
  63. #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000
  64. #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8
  65. #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31
  66. #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00
  67. #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004
  68. #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0
  69. #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31
  70. #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff
  71. #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008
  72. #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0
  73. #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31
  74. #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff
  75. #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c
  76. #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0
  77. #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31
  78. #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff
  79. #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010
  80. #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0
  81. #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31
  82. #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff
  83. #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014
  84. #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0
  85. #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19
  86. #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff
  87. #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014
  88. #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20
  89. #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23
  90. #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000
  91. #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014
  92. #define TCL_STATUS_RING_RESERVED_5A_LSB 24
  93. #define TCL_STATUS_RING_RESERVED_5A_MSB 31
  94. #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000
  95. #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018
  96. #define TCL_STATUS_RING_RESERVED_6A_LSB 0
  97. #define TCL_STATUS_RING_RESERVED_6A_MSB 31
  98. #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff
  99. #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c
  100. #define TCL_STATUS_RING_RESERVED_7A_LSB 0
  101. #define TCL_STATUS_RING_RESERVED_7A_MSB 19
  102. #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff
  103. #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c
  104. #define TCL_STATUS_RING_RING_ID_LSB 20
  105. #define TCL_STATUS_RING_RING_ID_MSB 27
  106. #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000
  107. #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c
  108. #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28
  109. #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31
  110. #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000
  111. #endif