wbm_release_ring.h 16 KB

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  1. /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _WBM_RELEASE_RING_H_
  16. #define _WBM_RELEASE_RING_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #include "buffer_addr_info.h"
  20. #define NUM_OF_DWORDS_WBM_RELEASE_RING 8
  21. struct wbm_release_ring {
  22. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  23. struct buffer_addr_info released_buff_or_desc_addr_info;
  24. uint32_t release_source_module : 3, // [2:0]
  25. reserved_2a : 3, // [5:3]
  26. buffer_or_desc_type : 3, // [8:6]
  27. reserved_2b : 22, // [30:9]
  28. wbm_internal_error : 1; // [31:31]
  29. uint32_t reserved_3a : 32; // [31:0]
  30. uint32_t reserved_4a : 32; // [31:0]
  31. uint32_t reserved_5a : 32; // [31:0]
  32. uint32_t reserved_6a : 32; // [31:0]
  33. uint32_t reserved_7a : 28, // [27:0]
  34. looping_count : 4; // [31:28]
  35. #else
  36. struct buffer_addr_info released_buff_or_desc_addr_info;
  37. uint32_t wbm_internal_error : 1, // [31:31]
  38. reserved_2b : 22, // [30:9]
  39. buffer_or_desc_type : 3, // [8:6]
  40. reserved_2a : 3, // [5:3]
  41. release_source_module : 3; // [2:0]
  42. uint32_t reserved_3a : 32; // [31:0]
  43. uint32_t reserved_4a : 32; // [31:0]
  44. uint32_t reserved_5a : 32; // [31:0]
  45. uint32_t reserved_6a : 32; // [31:0]
  46. uint32_t looping_count : 4, // [31:28]
  47. reserved_7a : 28; // [27:0]
  48. #endif
  49. };
  50. /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO
  51. DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or
  52. a 64-bit virtual address.
  53. */
  54. /* Description BUFFER_ADDR_31_0
  55. Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
  56. descriptor OR Link Descriptor
  57. In case of 'NULL' pointer, this field is set to 0
  58. <legal all>
  59. */
  60. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  61. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  62. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
  63. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  64. /* Description BUFFER_ADDR_39_32
  65. Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
  66. descriptor OR Link Descriptor
  67. In case of 'NULL' pointer, this field is set to 0
  68. <legal all>
  69. */
  70. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  71. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  72. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
  73. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  74. /* Description RETURN_BUFFER_MANAGER
  75. Consumer: WBM
  76. Producer: SW/FW
  77. In case of 'NULL' pointer, this field is set to 0
  78. Indicates to which buffer manager the buffer OR MSDU_EXTENSION
  79. descriptor OR link descriptor that is being pointed to
  80. shall be returned after the frame has been processed. It
  81. is used by WBM for routing purposes.
  82. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  83. to the WMB buffer idle list
  84. <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
  85. to the WBM idle link descriptor idle list, where the chip
  86. 0 WBM is chosen in case of a multi-chip config
  87. <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
  88. to the chip 1 WBM idle link descriptor idle list
  89. <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
  90. to the chip 2 WBM idle link descriptor idle list
  91. <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
  92. returned to chip 3 WBM idle link descriptor idle list
  93. <enum 4 FW_BM> This buffer shall be returned to the FW
  94. <enum 5 SW0_BM> This buffer shall be returned to the SW,
  95. ring 0
  96. <enum 6 SW1_BM> This buffer shall be returned to the SW,
  97. ring 1
  98. <enum 7 SW2_BM> This buffer shall be returned to the SW,
  99. ring 2
  100. <enum 8 SW3_BM> This buffer shall be returned to the SW,
  101. ring 3
  102. <enum 9 SW4_BM> This buffer shall be returned to the SW,
  103. ring 4
  104. <enum 10 SW5_BM> This buffer shall be returned to the SW,
  105. ring 5
  106. <enum 11 SW6_BM> This buffer shall be returned to the SW,
  107. ring 6
  108. <legal 0-12>
  109. */
  110. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  111. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  112. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
  113. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
  114. /* Description SW_BUFFER_COOKIE
  115. Cookie field exclusively used by SW.
  116. In case of 'NULL' pointer, this field is set to 0
  117. HW ignores the contents, accept that it passes the programmed
  118. value on to other descriptors together with the physical
  119. address
  120. Field can be used by SW to for example associate the buffers
  121. physical address with the virtual address
  122. The bit definitions as used by SW are within SW HLD specification
  123. NOTE1:
  124. The three most significant bits can have a special meaning
  125. in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
  126. and field transmit_bw_restriction is set
  127. In case of NON punctured transmission:
  128. Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
  129. Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
  130. Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
  131. Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
  132. Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
  133. Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
  134. Sw_buffer_cookie[19:18] = 2'b11: reserved
  135. In case of punctured transmission:
  136. Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
  137. Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
  138. Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
  139. Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
  140. Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
  141. Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
  142. Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
  143. Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
  144. Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
  145. Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
  146. Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
  147. Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
  148. Sw_buffer_cookie[19:18] = 2'b11: reserved
  149. Note: a punctured transmission is indicated by the presence
  150. of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
  151. <legal all>
  152. */
  153. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  154. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
  155. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
  156. #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
  157. /* Description RELEASE_SOURCE_MODULE
  158. Indicates which module initiated the release of this buffer
  159. or descriptor
  160. <enum 1 release_source_RXDMA> RXDMA released this buffer
  161. or descriptor
  162. <enum 2 release_source_REO> REO released this buffer or
  163. descriptor
  164. <enum 5 release_source_FW_RX> FW released this buffer or
  165. descriptor
  166. <enum 4 release_source_SW_RX> SW released this buffer or
  167. descriptor
  168. <enum 0 release_source_TQM> DO NOT USE
  169. <enum 3 release_source_FW_TX> DO NOT USE
  170. <enum 6 release_source_SW_TX> DO NOT USE
  171. <legal 0-6>
  172. */
  173. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
  174. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0
  175. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2
  176. #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007
  177. /* Description RESERVED_2A
  178. This could be different fields depending on the structure.
  179. <legal all>
  180. */
  181. #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008
  182. #define WBM_RELEASE_RING_RESERVED_2A_LSB 3
  183. #define WBM_RELEASE_RING_RESERVED_2A_MSB 5
  184. #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038
  185. /* Description BUFFER_OR_DESC_TYPE
  186. Consumer: WBM/SW/FW
  187. Producer: SW/TQM/RXDMA/REO/SWITCH
  188. Field only valid when WBM is marked as the return_buffer_manager
  189. in the Released_Buffer_address_info
  190. Indicates that type of buffer or descriptor is being released
  191. <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer
  192. <enum 1 msdu_link_descriptor> The address points to an TX
  193. MSDU link descriptor
  194. <enum 2 mpdu_link_descriptor> The address points to an MPDU
  195. link descriptor
  196. <enum 3 msdu_ext_descriptor > The address points to an MSDU
  197. extension descriptor.
  198. In case BM finds this one in a release ring, it passes it
  199. on to FW...
  200. <enum 4 queue_ext_descriptor> The address points to an TQM
  201. queue extension descriptor. WBM should treat this is the
  202. same way as a link descriptor. That is, put the 128 byte
  203. buffer back in the link buffer idle list.
  204. TODO: Any restrictions?
  205. <legal 0-4>
  206. */
  207. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
  208. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6
  209. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8
  210. #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
  211. /* Description RESERVED_2B
  212. This could be different fields depending on the structure.
  213. <legal all>
  214. */
  215. #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008
  216. #define WBM_RELEASE_RING_RESERVED_2B_LSB 9
  217. #define WBM_RELEASE_RING_RESERVED_2B_MSB 30
  218. #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00
  219. /* Description WBM_INTERNAL_ERROR
  220. Can only be set by WBM.
  221. Is set when WBM got a buffer pointer but the action was
  222. to push it to the idle link descriptor ring or do link related
  223. activity
  224. OR
  225. Is set when WBM got a link buffer pointer but the action
  226. was to push it to the buffer descriptor ring
  227. <legal all>
  228. */
  229. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008
  230. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31
  231. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31
  232. #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000
  233. /* Description RESERVED_3A
  234. This could be different fields depending on the structure.
  235. <legal all>
  236. */
  237. #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c
  238. #define WBM_RELEASE_RING_RESERVED_3A_LSB 0
  239. #define WBM_RELEASE_RING_RESERVED_3A_MSB 31
  240. #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff
  241. /* Description RESERVED_4A
  242. This could be different fields depending on the structure.
  243. <legal all>
  244. */
  245. #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010
  246. #define WBM_RELEASE_RING_RESERVED_4A_LSB 0
  247. #define WBM_RELEASE_RING_RESERVED_4A_MSB 31
  248. #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff
  249. /* Description RESERVED_5A
  250. This could be different fields depending on the structure.
  251. <legal all>
  252. */
  253. #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014
  254. #define WBM_RELEASE_RING_RESERVED_5A_LSB 0
  255. #define WBM_RELEASE_RING_RESERVED_5A_MSB 31
  256. #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff
  257. /* Description RESERVED_6A
  258. This could be different fields depending on the structure.
  259. <legal all>
  260. */
  261. #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018
  262. #define WBM_RELEASE_RING_RESERVED_6A_LSB 0
  263. #define WBM_RELEASE_RING_RESERVED_6A_MSB 31
  264. #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff
  265. /* Description RESERVED_7A
  266. This could be different fields depending on the structure.
  267. <legal all>
  268. */
  269. #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c
  270. #define WBM_RELEASE_RING_RESERVED_7A_LSB 0
  271. #define WBM_RELEASE_RING_RESERVED_7A_MSB 27
  272. #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff
  273. /* Description LOOPING_COUNT
  274. Consumer: WBM/SW/FW
  275. Producer: SW/TQM/RXDMA/REO/SWITCH
  276. If WBM_internal_error is set, this descriptor is sent to
  277. the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count
  278. is used to indicate an error code.
  279. The values reported are documented further in the WBM MLD
  280. doc.
  281. If WBM_internal_error is not set, the following holds.
  282. A count value that indicates the number of times the producer
  283. of entries into the Buffer Manager Ring has looped around
  284. the ring.
  285. At initialization time, this value is set to 0. On the first
  286. loop, this value is set to 1. After the max value is reached
  287. allowed by the number of bits for this field, the count
  288. value continues with 0 again.
  289. In case SW is the consumer of the ring entries, it can use
  290. this field to figure out up to where the producer of entries
  291. has created new entries. This eliminates the need to check
  292. where the "head pointer' of the ring is located once the
  293. SW starts processing an interrupt indicating that new entries
  294. have been put into this ring...
  295. Also note that SW if it wants only needs to look at the
  296. LSB bit of this count value.
  297. <legal all>
  298. */
  299. #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c
  300. #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28
  301. #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31
  302. #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000
  303. #endif // WBM_RELEASE_RING