uniform_descriptor_header.h 5.2 KB

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  1. /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
  16. #define _UNIFORM_DESCRIPTOR_HEADER_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
  20. struct uniform_descriptor_header {
  21. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  22. uint32_t owner : 4, // [3:0]
  23. buffer_type : 4, // [7:4]
  24. tx_mpdu_queue_number : 20, // [27:8]
  25. reserved_0a : 4; // [31:28]
  26. #else
  27. uint32_t reserved_0a : 4, // [31:28]
  28. tx_mpdu_queue_number : 20, // [27:8]
  29. buffer_type : 4, // [7:4]
  30. owner : 4; // [3:0]
  31. #endif
  32. };
  33. /* Description OWNER
  34. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  35. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  36. The owner of this data structure:
  37. <enum 0 WBM_owned> Buffer Manager currently owns this data
  38. structure.
  39. <enum 1 SW_OR_FW_owned> Software of FW currently owns this
  40. data structure.
  41. <enum 2 TQM_owned> Transmit Queue Manager currently owns
  42. this data structure.
  43. <enum 3 RXDMA_owned> Receive DMA currently owns this data
  44. structure.
  45. <enum 4 REO_owned> Reorder currently owns this data structure.
  46. <enum 5 SWITCH_owned> SWITCH currently owns this data structure.
  47. <legal 0-5>
  48. */
  49. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
  50. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0
  51. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3
  52. #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
  53. /* Description BUFFER_TYPE
  54. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  55. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  56. Field describing what contents format is of this descriptor
  57. <enum 0 Transmit_MSDU_Link_descriptor>
  58. <enum 1 Transmit_MPDU_Link_descriptor>
  59. <enum 2 Transmit_MPDU_Queue_head_descriptor>
  60. <enum 3 Transmit_MPDU_Queue_ext_descriptor>
  61. <enum 4 Transmit_flow_descriptor>
  62. <enum 5 Transmit_buffer> NOT TO BE USED:
  63. <enum 6 Receive_MSDU_Link_descriptor>
  64. <enum 7 Receive_MPDU_Link_descriptor>
  65. <enum 8 Receive_REO_queue_descriptor>
  66. <enum 9 Receive_REO_queue_1k_descriptor>
  67. <enum 10 Receive_REO_queue_ext_descriptor>
  68. <enum 11 Receive_buffer>
  69. <enum 12 Idle_link_list_entry>
  70. <legal 0-12>
  71. */
  72. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
  73. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
  74. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
  75. #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
  76. /* Description TX_MPDU_QUEUE_NUMBER
  77. Consumer: TQM/Debug
  78. Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
  79. Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
  80. Indicates the MPDU queue ID to which this MPDU descriptor
  81. belongs
  82. Used for tracking and debugging
  83. Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
  84. word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
  85. for this.
  86. <legal all>
  87. */
  88. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
  89. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
  90. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
  91. #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
  92. /* Description RESERVED_0A
  93. <legal 0>
  94. */
  95. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
  96. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
  97. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
  98. #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
  99. #endif // UNIFORM_DESCRIPTOR_HEADER