received_trigger_info_details.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. /*
  2. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
  17. #define _RECEIVED_TRIGGER_INFO_DETAILS_H_
  18. #define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
  19. struct received_trigger_info_details {
  20. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  21. uint32_t trigger_type : 4,
  22. ax_trigger_source : 1,
  23. ax_trigger_type : 4,
  24. trigger_source_sta_full_aid : 13,
  25. frame_control_valid : 1,
  26. qos_control_valid : 1,
  27. he_control_info_valid : 1,
  28. __reserved_g_0005_trigger_subtype : 4,
  29. txop_sharing_mode : 2,
  30. tid_aggregation_limit_is_zero : 1;
  31. uint32_t phy_ppdu_id : 16,
  32. lsig_response_length : 12,
  33. reserved_1a : 4;
  34. uint32_t frame_control : 16,
  35. qos_control : 16;
  36. uint32_t sw_peer_id : 16,
  37. txop_sharing_allocation_duration : 9,
  38. reserved_3a : 7;
  39. uint32_t he_control : 32;
  40. #else
  41. uint32_t tid_aggregation_limit_is_zero : 1,
  42. txop_sharing_mode : 2,
  43. __reserved_g_0005_trigger_subtype : 4,
  44. he_control_info_valid : 1,
  45. qos_control_valid : 1,
  46. frame_control_valid : 1,
  47. trigger_source_sta_full_aid : 13,
  48. ax_trigger_type : 4,
  49. ax_trigger_source : 1,
  50. trigger_type : 4;
  51. uint32_t reserved_1a : 4,
  52. lsig_response_length : 12,
  53. phy_ppdu_id : 16;
  54. uint32_t qos_control : 16,
  55. frame_control : 16;
  56. uint32_t reserved_3a : 7,
  57. txop_sharing_allocation_duration : 9,
  58. sw_peer_id : 16;
  59. uint32_t he_control : 32;
  60. #endif
  61. };
  62. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
  63. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
  64. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
  65. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
  66. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
  67. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
  68. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
  69. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
  70. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
  71. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
  72. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
  73. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
  74. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
  75. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
  76. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
  77. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
  78. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
  79. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
  80. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
  81. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
  82. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
  83. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
  84. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
  85. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
  86. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
  87. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
  88. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
  89. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
  90. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
  91. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
  92. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
  93. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
  94. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000
  95. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29
  96. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30
  97. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000
  98. #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
  99. #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
  100. #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
  101. #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
  102. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
  103. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
  104. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
  105. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
  106. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
  107. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
  108. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
  109. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
  110. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
  111. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
  112. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
  113. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
  114. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
  115. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
  116. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
  117. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
  118. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
  119. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
  120. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
  121. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
  122. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
  123. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
  124. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
  125. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
  126. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
  127. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
  128. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
  129. #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
  130. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
  131. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25
  132. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
  133. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000
  134. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
  135. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
  136. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
  137. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
  138. #endif