response_start_status.h 4.3 KB

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  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RESPONSE_START_STATUS_H_
  17. #define _RESPONSE_START_STATUS_H_
  18. #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
  19. struct response_start_status {
  20. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  21. uint32_t generated_response : 3,
  22. __reserved_g_0012 : 2,
  23. trig_response_related : 1,
  24. response_sta_count : 7,
  25. reserved : 19;
  26. uint32_t phy_ppdu_id : 16,
  27. sw_peer_id : 16;
  28. #else
  29. uint32_t reserved : 19,
  30. response_sta_count : 7,
  31. trig_response_related : 1,
  32. __reserved_g_0012 : 2,
  33. generated_response : 3;
  34. uint32_t sw_peer_id : 16,
  35. phy_ppdu_id : 16;
  36. #endif
  37. };
  38. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000
  39. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
  40. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
  41. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007
  42. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000
  43. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
  44. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
  45. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020
  46. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000
  47. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
  48. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
  49. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0
  50. #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000
  51. #define RESPONSE_START_STATUS_RESERVED_LSB 13
  52. #define RESPONSE_START_STATUS_RESERVED_MSB 31
  53. #define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000
  54. #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004
  55. #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0
  56. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15
  57. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff
  58. #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004
  59. #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16
  60. #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31
  61. #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000
  62. #endif