dsi_drm.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. dsi_mode->timing.vdc_enabled = dsi_mode->priv_info->vdc_enabled;
  48. dsi_mode->timing.vdc = &dsi_mode->priv_info->vdc;
  49. dsi_mode->timing.pclk_scale = dsi_mode->priv_info->pclk_scale;
  50. }
  51. if (msm_is_mode_seamless(drm_mode))
  52. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  53. if (msm_is_mode_dynamic_fps(drm_mode))
  54. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  55. if (msm_needs_vblank_pre_modeset(drm_mode))
  56. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  57. if (msm_is_mode_seamless_dms(drm_mode))
  58. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  59. if (msm_is_mode_seamless_vrr(drm_mode))
  60. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  61. if (msm_is_mode_seamless_poms(drm_mode))
  62. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  63. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  64. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  65. dsi_mode->timing.h_sync_polarity =
  66. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  67. dsi_mode->timing.v_sync_polarity =
  68. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  69. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  70. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  71. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  72. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  73. }
  74. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  75. struct drm_display_mode *drm_mode)
  76. {
  77. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  78. memset(drm_mode, 0, sizeof(*drm_mode));
  79. drm_mode->hdisplay = dsi_mode->timing.h_active;
  80. drm_mode->hsync_start = drm_mode->hdisplay +
  81. dsi_mode->timing.h_front_porch;
  82. drm_mode->hsync_end = drm_mode->hsync_start +
  83. dsi_mode->timing.h_sync_width;
  84. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  85. drm_mode->hskew = dsi_mode->timing.h_skew;
  86. drm_mode->vdisplay = dsi_mode->timing.v_active;
  87. drm_mode->vsync_start = drm_mode->vdisplay +
  88. dsi_mode->timing.v_front_porch;
  89. drm_mode->vsync_end = drm_mode->vsync_start +
  90. dsi_mode->timing.v_sync_width;
  91. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  92. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  93. drm_mode->clock = dsi_mode->pixel_clk_khz;
  94. drm_mode->private = (int *)dsi_mode->priv_info;
  95. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  96. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  97. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  98. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  99. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  100. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  101. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  102. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  103. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  104. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  105. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  106. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  107. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  108. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  109. if (dsi_mode->timing.h_sync_polarity)
  110. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  111. if (dsi_mode->timing.v_sync_polarity)
  112. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  113. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  114. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  115. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  116. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  117. /* set mode name */
  118. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  119. drm_mode->hdisplay, drm_mode->vdisplay,
  120. drm_mode->vrefresh, drm_mode->clock,
  121. video_mode ? "vid" : "cmd");
  122. }
  123. static int dsi_bridge_attach(struct drm_bridge *bridge)
  124. {
  125. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  126. if (!bridge) {
  127. DSI_ERR("Invalid params\n");
  128. return -EINVAL;
  129. }
  130. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  131. return 0;
  132. }
  133. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  134. {
  135. int rc = 0;
  136. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  137. if (!bridge) {
  138. DSI_ERR("Invalid params\n");
  139. return;
  140. }
  141. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  142. DSI_ERR("Incorrect bridge details\n");
  143. return;
  144. }
  145. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  146. /* By this point mode should have been validated through mode_fixup */
  147. rc = dsi_display_set_mode(c_bridge->display,
  148. &(c_bridge->dsi_mode), 0x0);
  149. if (rc) {
  150. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  151. c_bridge->id, rc);
  152. return;
  153. }
  154. if (c_bridge->dsi_mode.dsi_mode_flags &
  155. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  156. DSI_MODE_FLAG_DYN_CLK)) {
  157. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  158. return;
  159. }
  160. SDE_ATRACE_BEGIN("dsi_display_prepare");
  161. rc = dsi_display_prepare(c_bridge->display);
  162. if (rc) {
  163. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  164. c_bridge->id, rc);
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. return;
  167. }
  168. SDE_ATRACE_END("dsi_display_prepare");
  169. SDE_ATRACE_BEGIN("dsi_display_enable");
  170. rc = dsi_display_enable(c_bridge->display);
  171. if (rc) {
  172. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  173. c_bridge->id, rc);
  174. (void)dsi_display_unprepare(c_bridge->display);
  175. }
  176. SDE_ATRACE_END("dsi_display_enable");
  177. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  178. if (rc)
  179. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  180. rc);
  181. }
  182. static void dsi_bridge_enable(struct drm_bridge *bridge)
  183. {
  184. int rc = 0;
  185. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  186. struct dsi_display *display;
  187. if (!bridge) {
  188. DSI_ERR("Invalid params\n");
  189. return;
  190. }
  191. if (c_bridge->dsi_mode.dsi_mode_flags &
  192. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  193. DSI_MODE_FLAG_DYN_CLK)) {
  194. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  195. return;
  196. }
  197. display = c_bridge->display;
  198. rc = dsi_display_post_enable(display);
  199. if (rc)
  200. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  201. c_bridge->id, rc);
  202. if (display && display->drm_conn) {
  203. sde_connector_helper_bridge_enable(display->drm_conn);
  204. if (c_bridge->dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)
  205. sde_connector_schedule_status_work(display->drm_conn,
  206. true);
  207. }
  208. }
  209. static void dsi_bridge_disable(struct drm_bridge *bridge)
  210. {
  211. int rc = 0;
  212. int private_flags;
  213. struct dsi_display *display;
  214. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  215. if (!bridge) {
  216. DSI_ERR("Invalid params\n");
  217. return;
  218. }
  219. display = c_bridge->display;
  220. private_flags =
  221. bridge->encoder->crtc->state->adjusted_mode.private_flags;
  222. if (display && display->drm_conn) {
  223. display->poms_pending =
  224. private_flags & MSM_MODE_FLAG_SEAMLESS_POMS;
  225. sde_connector_helper_bridge_disable(display->drm_conn);
  226. }
  227. rc = dsi_display_pre_disable(c_bridge->display);
  228. if (rc) {
  229. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  230. c_bridge->id, rc);
  231. }
  232. }
  233. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  234. {
  235. int rc = 0;
  236. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  237. if (!bridge) {
  238. DSI_ERR("Invalid params\n");
  239. return;
  240. }
  241. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  242. SDE_ATRACE_BEGIN("dsi_display_disable");
  243. rc = dsi_display_disable(c_bridge->display);
  244. if (rc) {
  245. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  246. c_bridge->id, rc);
  247. SDE_ATRACE_END("dsi_display_disable");
  248. return;
  249. }
  250. SDE_ATRACE_END("dsi_display_disable");
  251. rc = dsi_display_unprepare(c_bridge->display);
  252. if (rc) {
  253. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  254. c_bridge->id, rc);
  255. SDE_ATRACE_END("dsi_bridge_post_disable");
  256. return;
  257. }
  258. SDE_ATRACE_END("dsi_bridge_post_disable");
  259. }
  260. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  261. const struct drm_display_mode *mode,
  262. const struct drm_display_mode *adjusted_mode)
  263. {
  264. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  265. if (!bridge || !mode || !adjusted_mode) {
  266. DSI_ERR("Invalid params\n");
  267. return;
  268. }
  269. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  270. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  271. /* restore bit_clk_rate also for dynamic clk use cases */
  272. c_bridge->dsi_mode.timing.clk_rate_hz =
  273. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  274. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  275. }
  276. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  277. const struct drm_display_mode *mode,
  278. struct drm_display_mode *adjusted_mode)
  279. {
  280. int rc = 0;
  281. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  282. struct dsi_display *display;
  283. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  284. struct drm_crtc_state *crtc_state;
  285. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  286. if (!bridge || !mode || !adjusted_mode) {
  287. DSI_ERR("Invalid params\n");
  288. return false;
  289. }
  290. display = c_bridge->display;
  291. if (!display) {
  292. DSI_ERR("Invalid params\n");
  293. return false;
  294. }
  295. /*
  296. * if no timing defined in panel, it must be external mode
  297. * and we'll use empty priv info to populate the mode
  298. */
  299. if (display->panel && !display->panel->num_timing_nodes) {
  300. *adjusted_mode = *mode;
  301. adjusted_mode->private = (int *)&default_priv_info;
  302. adjusted_mode->private_flags = 0;
  303. return true;
  304. }
  305. convert_to_dsi_mode(mode, &dsi_mode);
  306. /*
  307. * retrieve dsi mode from dsi driver's cache since not safe to take
  308. * the drm mode config mutex in all paths
  309. */
  310. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  311. if (rc)
  312. return rc;
  313. /* propagate the private info to the adjusted_mode derived dsi mode */
  314. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  315. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  316. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  317. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  318. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  319. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  320. if (rc) {
  321. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  322. return false;
  323. }
  324. if (bridge->encoder && bridge->encoder->crtc &&
  325. crtc_state->crtc) {
  326. const struct drm_display_mode *cur_mode =
  327. &crtc_state->crtc->state->mode;
  328. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  329. cur_dsi_mode.timing.dsc_enabled =
  330. dsi_mode.priv_info->dsc_enabled;
  331. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  332. rc = dsi_display_validate_mode_change(c_bridge->display,
  333. &cur_dsi_mode, &dsi_mode);
  334. if (rc) {
  335. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  336. c_bridge->display->name, rc);
  337. return false;
  338. }
  339. /* No panel mode switch when drm pipeline is changing */
  340. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  341. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  342. (crtc_state->enable ==
  343. crtc_state->crtc->state->enable))
  344. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  345. /* No DMS/VRR when drm pipeline is changing */
  346. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  347. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  348. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  349. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  350. (!crtc_state->active_changed ||
  351. display->is_cont_splash_enabled))
  352. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  353. }
  354. /* Reject seamless transition when active changed */
  355. if (crtc_state->active_changed &&
  356. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  357. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS) ||
  358. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))) {
  359. DSI_INFO("seamless upon active changed 0x%x %d\n",
  360. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  361. return false;
  362. }
  363. /* convert back to drm mode, propagating the private info & flags */
  364. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  365. return true;
  366. }
  367. u64 dsi_drm_find_bit_clk_rate(void *display,
  368. const struct drm_display_mode *drm_mode)
  369. {
  370. int i = 0, count = 0;
  371. struct dsi_display *dsi_display = display;
  372. struct dsi_display_mode *dsi_mode;
  373. u64 bit_clk_rate = 0;
  374. if (!dsi_display || !drm_mode)
  375. return 0;
  376. dsi_display_get_mode_count(dsi_display, &count);
  377. for (i = 0; i < count; i++) {
  378. dsi_mode = &dsi_display->modes[i];
  379. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  380. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  381. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  382. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  383. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  384. break;
  385. }
  386. }
  387. return bit_clk_rate;
  388. }
  389. int dsi_conn_get_mode_info(struct drm_connector *connector,
  390. const struct drm_display_mode *drm_mode,
  391. struct msm_mode_info *mode_info,
  392. void *display, const struct msm_resource_caps_info *avail_res)
  393. {
  394. struct dsi_display_mode dsi_mode;
  395. struct dsi_mode_info *timing;
  396. int src_bpp, tar_bpp;
  397. if (!drm_mode || !mode_info)
  398. return -EINVAL;
  399. convert_to_dsi_mode(drm_mode, &dsi_mode);
  400. if (!dsi_mode.priv_info)
  401. return -EINVAL;
  402. memset(mode_info, 0, sizeof(*mode_info));
  403. timing = &dsi_mode.timing;
  404. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  405. mode_info->vtotal = DSI_V_TOTAL(timing);
  406. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  407. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  408. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  409. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  410. mode_info->mdp_transfer_time_us =
  411. dsi_mode.priv_info->mdp_transfer_time_us;
  412. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  413. sizeof(struct msm_display_topology));
  414. if (dsi_mode.priv_info->dsc_enabled) {
  415. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  416. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  417. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  418. sizeof(dsi_mode.priv_info->dsc));
  419. } else if (dsi_mode.priv_info->vdc_enabled) {
  420. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  421. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  422. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode.priv_info->vdc,
  423. sizeof(dsi_mode.priv_info->vdc));
  424. }
  425. if (mode_info->comp_info.comp_type) {
  426. tar_bpp = dsi_mode.priv_info->pclk_scale.numer;
  427. src_bpp = dsi_mode.priv_info->pclk_scale.denom;
  428. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  429. tar_bpp);
  430. mode_info->wide_bus_en = dsi_mode.priv_info->widebus_support;
  431. }
  432. if (dsi_mode.priv_info->roi_caps.enabled) {
  433. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  434. sizeof(dsi_mode.priv_info->roi_caps));
  435. }
  436. return 0;
  437. }
  438. static const struct drm_bridge_funcs dsi_bridge_ops = {
  439. .attach = dsi_bridge_attach,
  440. .mode_fixup = dsi_bridge_mode_fixup,
  441. .pre_enable = dsi_bridge_pre_enable,
  442. .enable = dsi_bridge_enable,
  443. .disable = dsi_bridge_disable,
  444. .post_disable = dsi_bridge_post_disable,
  445. .mode_set = dsi_bridge_mode_set,
  446. };
  447. int dsi_conn_set_info_blob(struct drm_connector *connector,
  448. void *info, void *display, struct msm_mode_info *mode_info)
  449. {
  450. struct dsi_display *dsi_display = display;
  451. struct dsi_panel *panel;
  452. enum dsi_pixel_format fmt;
  453. u32 bpp;
  454. if (!info || !dsi_display)
  455. return -EINVAL;
  456. dsi_display->drm_conn = connector;
  457. sde_kms_info_add_keystr(info,
  458. "display type", dsi_display->display_type);
  459. switch (dsi_display->type) {
  460. case DSI_DISPLAY_SINGLE:
  461. sde_kms_info_add_keystr(info, "display config",
  462. "single display");
  463. break;
  464. case DSI_DISPLAY_EXT_BRIDGE:
  465. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  466. break;
  467. case DSI_DISPLAY_SPLIT:
  468. sde_kms_info_add_keystr(info, "display config",
  469. "split display");
  470. break;
  471. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  472. sde_kms_info_add_keystr(info, "display config",
  473. "split ext bridge");
  474. break;
  475. default:
  476. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  477. break;
  478. }
  479. if (!dsi_display->panel) {
  480. DSI_DEBUG("invalid panel data\n");
  481. goto end;
  482. }
  483. panel = dsi_display->panel;
  484. sde_kms_info_add_keystr(info, "panel name", panel->name);
  485. switch (panel->panel_mode) {
  486. case DSI_OP_VIDEO_MODE:
  487. sde_kms_info_add_keystr(info, "panel mode", "video");
  488. sde_kms_info_add_keystr(info, "qsync support",
  489. panel->qsync_min_fps ? "true" : "false");
  490. break;
  491. case DSI_OP_CMD_MODE:
  492. sde_kms_info_add_keystr(info, "panel mode", "command");
  493. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  494. mode_info->mdp_transfer_time_us);
  495. sde_kms_info_add_keystr(info, "qsync support",
  496. panel->qsync_min_fps ? "true" : "false");
  497. break;
  498. default:
  499. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  500. break;
  501. }
  502. sde_kms_info_add_keystr(info, "dfps support",
  503. panel->dfps_caps.dfps_support ? "true" : "false");
  504. if (panel->dfps_caps.dfps_support) {
  505. sde_kms_info_add_keyint(info, "min_fps",
  506. panel->dfps_caps.min_refresh_rate);
  507. sde_kms_info_add_keyint(info, "max_fps",
  508. panel->dfps_caps.max_refresh_rate);
  509. }
  510. sde_kms_info_add_keystr(info, "dyn bitclk support",
  511. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  512. switch (panel->phy_props.rotation) {
  513. case DSI_PANEL_ROTATE_NONE:
  514. sde_kms_info_add_keystr(info, "panel orientation", "none");
  515. break;
  516. case DSI_PANEL_ROTATE_H_FLIP:
  517. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  518. break;
  519. case DSI_PANEL_ROTATE_V_FLIP:
  520. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  521. break;
  522. case DSI_PANEL_ROTATE_HV_FLIP:
  523. sde_kms_info_add_keystr(info, "panel orientation",
  524. "horz & vert flip");
  525. break;
  526. default:
  527. DSI_DEBUG("invalid panel rotation:%d\n",
  528. panel->phy_props.rotation);
  529. break;
  530. }
  531. switch (panel->bl_config.type) {
  532. case DSI_BACKLIGHT_PWM:
  533. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  534. break;
  535. case DSI_BACKLIGHT_WLED:
  536. sde_kms_info_add_keystr(info, "backlight type", "wled");
  537. break;
  538. case DSI_BACKLIGHT_DCS:
  539. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  540. break;
  541. default:
  542. DSI_DEBUG("invalid panel backlight type:%d\n",
  543. panel->bl_config.type);
  544. break;
  545. }
  546. if (panel->spr_info.enable)
  547. sde_kms_info_add_keystr(info, "spr_pack_type",
  548. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  549. if (mode_info && mode_info->roi_caps.enabled) {
  550. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  551. mode_info->roi_caps.num_roi);
  552. sde_kms_info_add_keyint(info, "partial_update_xstart",
  553. mode_info->roi_caps.align.xstart_pix_align);
  554. sde_kms_info_add_keyint(info, "partial_update_walign",
  555. mode_info->roi_caps.align.width_pix_align);
  556. sde_kms_info_add_keyint(info, "partial_update_wmin",
  557. mode_info->roi_caps.align.min_width);
  558. sde_kms_info_add_keyint(info, "partial_update_ystart",
  559. mode_info->roi_caps.align.ystart_pix_align);
  560. sde_kms_info_add_keyint(info, "partial_update_halign",
  561. mode_info->roi_caps.align.height_pix_align);
  562. sde_kms_info_add_keyint(info, "partial_update_hmin",
  563. mode_info->roi_caps.align.min_height);
  564. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  565. mode_info->roi_caps.merge_rois);
  566. }
  567. fmt = dsi_display->config.common_config.dst_format;
  568. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  569. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  570. end:
  571. return 0;
  572. }
  573. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  574. bool force,
  575. void *display)
  576. {
  577. enum drm_connector_status status = connector_status_unknown;
  578. struct msm_display_info info;
  579. int rc;
  580. if (!conn || !display)
  581. return status;
  582. /* get display dsi_info */
  583. memset(&info, 0x0, sizeof(info));
  584. rc = dsi_display_get_info(conn, &info, display);
  585. if (rc) {
  586. DSI_ERR("failed to get display info, rc=%d\n", rc);
  587. return connector_status_disconnected;
  588. }
  589. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  590. status = (info.is_connected ? connector_status_connected :
  591. connector_status_disconnected);
  592. else
  593. status = connector_status_connected;
  594. conn->display_info.width_mm = info.width_mm;
  595. conn->display_info.height_mm = info.height_mm;
  596. return status;
  597. }
  598. void dsi_connector_put_modes(struct drm_connector *connector,
  599. void *display)
  600. {
  601. struct drm_display_mode *drm_mode;
  602. struct dsi_display_mode dsi_mode;
  603. struct dsi_display *dsi_display;
  604. if (!connector || !display)
  605. return;
  606. list_for_each_entry(drm_mode, &connector->modes, head) {
  607. convert_to_dsi_mode(drm_mode, &dsi_mode);
  608. dsi_display_put_mode(display, &dsi_mode);
  609. }
  610. /* free the display structure modes also */
  611. dsi_display = display;
  612. kfree(dsi_display->modes);
  613. dsi_display->modes = NULL;
  614. }
  615. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  616. {
  617. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  618. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  619. u32 dtd_size = 18;
  620. u32 header_size = sizeof(standard_header);
  621. if (!name)
  622. return -EINVAL;
  623. /* Fill standard header */
  624. memcpy(dtd, standard_header, header_size);
  625. dtd_size -= header_size;
  626. dtd_size = min_t(u32, dtd_size, strlen(name));
  627. memcpy(dtd + header_size, name, dtd_size);
  628. return 0;
  629. }
  630. static void dsi_drm_update_dtd(struct edid *edid,
  631. struct dsi_display_mode *modes, u32 modes_count)
  632. {
  633. u32 i;
  634. u32 count = min_t(u32, modes_count, 3);
  635. for (i = 0; i < count; i++) {
  636. struct detailed_timing *dtd = &edid->detailed_timings[i];
  637. struct dsi_display_mode *mode = &modes[i];
  638. struct dsi_mode_info *timing = &mode->timing;
  639. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  640. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  641. timing->h_back_porch;
  642. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  643. timing->v_back_porch;
  644. u32 h_img = 0, v_img = 0;
  645. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  646. pd->hactive_lo = timing->h_active & 0xFF;
  647. pd->hblank_lo = h_blank & 0xFF;
  648. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  649. ((timing->h_active >> 8) & 0xF) << 4;
  650. pd->vactive_lo = timing->v_active & 0xFF;
  651. pd->vblank_lo = v_blank & 0xFF;
  652. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  653. ((timing->v_active >> 8) & 0xF) << 4;
  654. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  655. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  656. pd->vsync_offset_pulse_width_lo =
  657. ((timing->v_front_porch & 0xF) << 4) |
  658. (timing->v_sync_width & 0xF);
  659. pd->hsync_vsync_offset_pulse_width_hi =
  660. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  661. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  662. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  663. (((timing->v_sync_width >> 4) & 0x3) << 0);
  664. pd->width_mm_lo = h_img & 0xFF;
  665. pd->height_mm_lo = v_img & 0xFF;
  666. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  667. ((v_img >> 8) & 0xF);
  668. pd->hborder = 0;
  669. pd->vborder = 0;
  670. pd->misc = 0;
  671. }
  672. }
  673. static void dsi_drm_update_checksum(struct edid *edid)
  674. {
  675. u8 *data = (u8 *)edid;
  676. u32 i, sum = 0;
  677. for (i = 0; i < EDID_LENGTH - 1; i++)
  678. sum += data[i];
  679. edid->checksum = 0x100 - (sum & 0xFF);
  680. }
  681. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  682. const struct msm_resource_caps_info *avail_res)
  683. {
  684. int rc, i;
  685. u32 count = 0, edid_size;
  686. struct dsi_display_mode *modes = NULL;
  687. struct drm_display_mode drm_mode;
  688. struct dsi_display *display = data;
  689. struct edid edid;
  690. unsigned int width_mm = connector->display_info.width_mm;
  691. unsigned int height_mm = connector->display_info.height_mm;
  692. const u8 edid_buf[EDID_LENGTH] = {
  693. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  694. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  695. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  696. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  697. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  698. 0x01, 0x01, 0x01, 0x01,
  699. };
  700. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  701. memcpy(&edid, edid_buf, edid_size);
  702. rc = dsi_display_get_mode_count(display, &count);
  703. if (rc) {
  704. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  705. goto end;
  706. }
  707. rc = dsi_display_get_modes(display, &modes);
  708. if (rc) {
  709. DSI_ERR("failed to get modes, rc=%d\n", rc);
  710. count = 0;
  711. goto end;
  712. }
  713. for (i = 0; i < count; i++) {
  714. struct drm_display_mode *m;
  715. memset(&drm_mode, 0x0, sizeof(drm_mode));
  716. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  717. m = drm_mode_duplicate(connector->dev, &drm_mode);
  718. if (!m) {
  719. DSI_ERR("failed to add mode %ux%u\n",
  720. drm_mode.hdisplay,
  721. drm_mode.vdisplay);
  722. count = -ENOMEM;
  723. goto end;
  724. }
  725. m->width_mm = connector->display_info.width_mm;
  726. m->height_mm = connector->display_info.height_mm;
  727. if (display->cmdline_timing != NO_OVERRIDE) {
  728. /* get the preferred mode from dsi display mode */
  729. if (modes[i].is_preferred)
  730. m->type |= DRM_MODE_TYPE_PREFERRED;
  731. } else if (i == 0) {
  732. /* set the first mode in list as preferred */
  733. m->type |= DRM_MODE_TYPE_PREFERRED;
  734. }
  735. drm_mode_probed_add(connector, m);
  736. }
  737. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  738. if (rc) {
  739. count = 0;
  740. goto end;
  741. }
  742. edid.width_cm = (connector->display_info.width_mm) / 10;
  743. edid.height_cm = (connector->display_info.height_mm) / 10;
  744. dsi_drm_update_dtd(&edid, modes, count);
  745. dsi_drm_update_checksum(&edid);
  746. rc = drm_connector_update_edid_property(connector, &edid);
  747. if (rc)
  748. count = 0;
  749. /*
  750. * DRM EDID structure maintains panel physical dimensions in
  751. * centimeters, we will be losing the precision anything below cm.
  752. * Changing DRM framework will effect other clients at this
  753. * moment, overriding the values back to millimeter.
  754. */
  755. connector->display_info.width_mm = width_mm;
  756. connector->display_info.height_mm = height_mm;
  757. end:
  758. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  759. return count;
  760. }
  761. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  762. struct drm_display_mode *mode,
  763. void *display, const struct msm_resource_caps_info *avail_res)
  764. {
  765. struct dsi_display_mode dsi_mode;
  766. int rc;
  767. if (!connector || !mode) {
  768. DSI_ERR("Invalid params\n");
  769. return MODE_ERROR;
  770. }
  771. convert_to_dsi_mode(mode, &dsi_mode);
  772. rc = dsi_display_validate_mode(display, &dsi_mode,
  773. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  774. if (rc) {
  775. DSI_ERR("mode not supported, rc=%d\n", rc);
  776. return MODE_BAD;
  777. }
  778. return MODE_OK;
  779. }
  780. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  781. void *display,
  782. struct msm_display_kickoff_params *params)
  783. {
  784. if (!connector || !display || !params) {
  785. DSI_ERR("Invalid params\n");
  786. return -EINVAL;
  787. }
  788. return dsi_display_pre_kickoff(connector, display, params);
  789. }
  790. int dsi_conn_prepare_commit(void *display,
  791. struct msm_display_conn_params *params)
  792. {
  793. if (!display || !params) {
  794. pr_err("Invalid params\n");
  795. return -EINVAL;
  796. }
  797. return dsi_display_pre_commit(display, params);
  798. }
  799. void dsi_conn_enable_event(struct drm_connector *connector,
  800. uint32_t event_idx, bool enable, void *display)
  801. {
  802. struct dsi_event_cb_info event_info;
  803. memset(&event_info, 0, sizeof(event_info));
  804. event_info.event_cb = sde_connector_trigger_event;
  805. event_info.event_usr_ptr = connector;
  806. dsi_display_enable_event(connector, display,
  807. event_idx, &event_info, enable);
  808. }
  809. int dsi_conn_post_kickoff(struct drm_connector *connector,
  810. struct msm_display_conn_params *params)
  811. {
  812. struct drm_encoder *encoder;
  813. struct dsi_bridge *c_bridge;
  814. struct dsi_display_mode adj_mode;
  815. struct dsi_display *display;
  816. struct dsi_display_ctrl *m_ctrl, *ctrl;
  817. int i, rc = 0, ctrl_version;
  818. bool enable;
  819. struct dsi_dyn_clk_caps *dyn_clk_caps;
  820. if (!connector || !connector->state) {
  821. DSI_ERR("invalid connector or connector state\n");
  822. return -EINVAL;
  823. }
  824. encoder = connector->state->best_encoder;
  825. if (!encoder) {
  826. DSI_DEBUG("best encoder is not available\n");
  827. return 0;
  828. }
  829. c_bridge = to_dsi_bridge(encoder->bridge);
  830. adj_mode = c_bridge->dsi_mode;
  831. display = c_bridge->display;
  832. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  833. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  834. m_ctrl = &display->ctrl[display->clk_master_idx];
  835. ctrl_version = m_ctrl->ctrl->version;
  836. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  837. if (rc) {
  838. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  839. display->name, rc);
  840. return -EINVAL;
  841. }
  842. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  843. (dyn_clk_caps->maintain_const_fps)) {
  844. display_for_each_ctrl(i, display) {
  845. ctrl = &display->ctrl[i];
  846. rc = dsi_ctrl_wait4dynamic_refresh_done(
  847. ctrl->ctrl);
  848. if (rc)
  849. DSI_ERR("wait4dfps refresh failed\n");
  850. }
  851. }
  852. /* Update the rest of the controllers */
  853. display_for_each_ctrl(i, display) {
  854. ctrl = &display->ctrl[i];
  855. if (!ctrl->ctrl || (ctrl == m_ctrl))
  856. continue;
  857. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  858. if (rc) {
  859. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  860. display->name, rc);
  861. return -EINVAL;
  862. }
  863. }
  864. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  865. }
  866. /* ensure dynamic clk switch flag is reset */
  867. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  868. if (params->qsync_update) {
  869. enable = (params->qsync_mode > 0) ? true : false;
  870. display_for_each_ctrl(i, display)
  871. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  872. }
  873. return 0;
  874. }
  875. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  876. struct drm_device *dev,
  877. struct drm_encoder *encoder)
  878. {
  879. int rc = 0;
  880. struct dsi_bridge *bridge;
  881. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  882. if (!bridge) {
  883. rc = -ENOMEM;
  884. goto error;
  885. }
  886. bridge->display = display;
  887. bridge->base.funcs = &dsi_bridge_ops;
  888. bridge->base.encoder = encoder;
  889. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  890. if (rc) {
  891. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  892. goto error_free_bridge;
  893. }
  894. encoder->bridge = &bridge->base;
  895. return bridge;
  896. error_free_bridge:
  897. kfree(bridge);
  898. error:
  899. return ERR_PTR(rc);
  900. }
  901. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  902. {
  903. if (bridge && bridge->base.encoder)
  904. bridge->base.encoder->bridge = NULL;
  905. kfree(bridge);
  906. }