dp_main.c 176 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include "dp_ipa.h"
  52. #ifdef CONFIG_MCL
  53. static void dp_service_mon_rings(void *arg);
  54. #ifndef REMOVE_PKT_LOG
  55. #include <pktlog_ac_api.h>
  56. #include <pktlog_ac.h>
  57. static void dp_pkt_log_con_service(struct cdp_pdev *ppdev, void *scn);
  58. #endif
  59. #endif
  60. static void dp_pktlogmod_exit(struct dp_pdev *handle);
  61. #define DP_INTR_POLL_TIMER_MS 10
  62. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  63. #define DP_MCS_LENGTH (6*MAX_MCS)
  64. #define DP_NSS_LENGTH (6*SS_COUNT)
  65. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  66. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  67. #define DP_MAX_MCS_STRING_LEN 30
  68. #define DP_CURR_FW_STATS_AVAIL 19
  69. #define DP_HTT_DBG_EXT_STATS_MAX 256
  70. #ifdef IPA_OFFLOAD
  71. /* Exclude IPA rings from the interrupt context */
  72. #define TX_RING_MASK_VAL 0xb
  73. #define RX_RING_MASK_VAL 0x7
  74. #else
  75. #define TX_RING_MASK_VAL 0xF
  76. #define RX_RING_MASK_VAL 0xF
  77. #endif
  78. bool rx_hash = 1;
  79. qdf_declare_param(rx_hash, bool);
  80. #define STR_MAXLEN 64
  81. #define DP_PPDU_STATS_CFG_ALL 0xffff
  82. /**
  83. * default_dscp_tid_map - Default DSCP-TID mapping
  84. *
  85. * DSCP TID AC
  86. * 000000 0 WME_AC_BE
  87. * 001000 1 WME_AC_BK
  88. * 010000 1 WME_AC_BK
  89. * 011000 0 WME_AC_BE
  90. * 100000 5 WME_AC_VI
  91. * 101000 5 WME_AC_VI
  92. * 110000 6 WME_AC_VO
  93. * 111000 6 WME_AC_VO
  94. */
  95. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  96. 0, 0, 0, 0, 0, 0, 0, 0,
  97. 1, 1, 1, 1, 1, 1, 1, 1,
  98. 1, 1, 1, 1, 1, 1, 1, 1,
  99. 0, 0, 0, 0, 0, 0, 0, 0,
  100. 5, 5, 5, 5, 5, 5, 5, 5,
  101. 5, 5, 5, 5, 5, 5, 5, 5,
  102. 6, 6, 6, 6, 6, 6, 6, 6,
  103. 6, 6, 6, 6, 6, 6, 6, 6,
  104. };
  105. /*
  106. * struct dp_rate_debug
  107. *
  108. * @mcs_type: print string for a given mcs
  109. * @valid: valid mcs rate?
  110. */
  111. struct dp_rate_debug {
  112. char mcs_type[DP_MAX_MCS_STRING_LEN];
  113. uint8_t valid;
  114. };
  115. #define MCS_VALID 1
  116. #define MCS_INVALID 0
  117. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  118. {
  119. {"CCK 11 Mbps Long ", MCS_VALID},
  120. {"CCK 5.5 Mbps Long ", MCS_VALID},
  121. {"CCK 2 Mbps Long ", MCS_VALID},
  122. {"CCK 1 Mbps Long ", MCS_VALID},
  123. {"CCK 11 Mbps Short ", MCS_VALID},
  124. {"CCK 5.5 Mbps Short", MCS_VALID},
  125. {"CCK 2 Mbps Short ", MCS_VALID},
  126. {"INVALID ", MCS_INVALID},
  127. {"INVALID ", MCS_INVALID},
  128. {"INVALID ", MCS_INVALID},
  129. {"INVALID ", MCS_INVALID},
  130. {"INVALID ", MCS_INVALID},
  131. {"INVALID ", MCS_VALID},
  132. },
  133. {
  134. {"OFDM 48 Mbps", MCS_VALID},
  135. {"OFDM 24 Mbps", MCS_VALID},
  136. {"OFDM 12 Mbps", MCS_VALID},
  137. {"OFDM 6 Mbps ", MCS_VALID},
  138. {"OFDM 54 Mbps", MCS_VALID},
  139. {"OFDM 36 Mbps", MCS_VALID},
  140. {"OFDM 18 Mbps", MCS_VALID},
  141. {"OFDM 9 Mbps ", MCS_VALID},
  142. {"INVALID ", MCS_INVALID},
  143. {"INVALID ", MCS_INVALID},
  144. {"INVALID ", MCS_INVALID},
  145. {"INVALID ", MCS_INVALID},
  146. {"INVALID ", MCS_VALID},
  147. },
  148. {
  149. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  150. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  151. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  152. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  153. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  154. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  155. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  156. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  157. {"INVALID ", MCS_INVALID},
  158. {"INVALID ", MCS_INVALID},
  159. {"INVALID ", MCS_INVALID},
  160. {"INVALID ", MCS_INVALID},
  161. {"INVALID ", MCS_VALID},
  162. },
  163. {
  164. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  165. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  166. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  167. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  168. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  169. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  170. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  171. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  172. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  173. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  174. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  175. {"VHT MCS 11 (1024-QAM 5/6)", MCS_VALID},
  176. {"INVALID ", MCS_VALID},
  177. },
  178. {
  179. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  180. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  181. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  182. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  183. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  184. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  185. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  186. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  187. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  188. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  189. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  190. {"HE MCS 11 (1024-QAM 5/6)", MCS_VALID},
  191. {"INVALID ", MCS_VALID},
  192. }
  193. };
  194. /**
  195. * @brief Cpu ring map types
  196. */
  197. enum dp_cpu_ring_map_types {
  198. DP_DEFAULT_MAP,
  199. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  200. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  201. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  202. DP_CPU_RING_MAP_MAX
  203. };
  204. /**
  205. * @brief Cpu to tx ring map
  206. */
  207. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  208. {0x0, 0x1, 0x2, 0x0},
  209. {0x1, 0x2, 0x1, 0x2},
  210. {0x0, 0x2, 0x0, 0x2},
  211. {0x2, 0x2, 0x2, 0x2}
  212. };
  213. /**
  214. * @brief Select the type of statistics
  215. */
  216. enum dp_stats_type {
  217. STATS_FW = 0,
  218. STATS_HOST = 1,
  219. STATS_TYPE_MAX = 2,
  220. };
  221. /**
  222. * @brief General Firmware statistics options
  223. *
  224. */
  225. enum dp_fw_stats {
  226. TXRX_FW_STATS_INVALID = -1,
  227. };
  228. /**
  229. * dp_stats_mapping_table - Firmware and Host statistics
  230. * currently supported
  231. */
  232. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  233. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  243. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  244. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  245. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  246. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  247. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  248. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  249. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  250. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  251. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  252. /* Last ENUM for HTT FW STATS */
  253. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  254. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  255. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  256. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  257. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  258. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  259. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  260. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  261. };
  262. /**
  263. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  264. * @ring_num: ring num of the ring being queried
  265. * @grp_mask: the grp_mask array for the ring type in question.
  266. *
  267. * The grp_mask array is indexed by group number and the bit fields correspond
  268. * to ring numbers. We are finding which interrupt group a ring belongs to.
  269. *
  270. * Return: the index in the grp_mask array with the ring number.
  271. * -QDF_STATUS_E_NOENT if no entry is found
  272. */
  273. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  274. {
  275. int ext_group_num;
  276. int mask = 1 << ring_num;
  277. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  278. ext_group_num++) {
  279. if (mask & grp_mask[ext_group_num])
  280. return ext_group_num;
  281. }
  282. return -QDF_STATUS_E_NOENT;
  283. }
  284. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  285. enum hal_ring_type ring_type,
  286. int ring_num)
  287. {
  288. int *grp_mask;
  289. switch (ring_type) {
  290. case WBM2SW_RELEASE:
  291. /* dp_tx_comp_handler - soc->tx_comp_ring */
  292. if (ring_num < 3)
  293. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  294. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  295. else if (ring_num == 3) {
  296. /* sw treats this as a separate ring type */
  297. grp_mask = &soc->wlan_cfg_ctx->
  298. int_rx_wbm_rel_ring_mask[0];
  299. ring_num = 0;
  300. } else {
  301. qdf_assert(0);
  302. return -QDF_STATUS_E_NOENT;
  303. }
  304. break;
  305. case REO_EXCEPTION:
  306. /* dp_rx_err_process - &soc->reo_exception_ring */
  307. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  308. break;
  309. case REO_DST:
  310. /* dp_rx_process - soc->reo_dest_ring */
  311. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  312. break;
  313. case REO_STATUS:
  314. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  315. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  316. break;
  317. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  318. case RXDMA_MONITOR_STATUS:
  319. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  320. case RXDMA_MONITOR_DST:
  321. /* dp_mon_process */
  322. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  323. break;
  324. case RXDMA_DST:
  325. /* dp_rxdma_err_process */
  326. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  327. break;
  328. case RXDMA_BUF:
  329. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  330. break;
  331. case RXDMA_MONITOR_BUF:
  332. /* TODO: support low_thresh interrupt */
  333. return -QDF_STATUS_E_NOENT;
  334. break;
  335. case TCL_DATA:
  336. case TCL_CMD:
  337. case REO_CMD:
  338. case SW2WBM_RELEASE:
  339. case WBM_IDLE_LINK:
  340. /* normally empty SW_TO_HW rings */
  341. return -QDF_STATUS_E_NOENT;
  342. break;
  343. case TCL_STATUS:
  344. case REO_REINJECT:
  345. /* misc unused rings */
  346. return -QDF_STATUS_E_NOENT;
  347. break;
  348. case CE_SRC:
  349. case CE_DST:
  350. case CE_DST_STATUS:
  351. /* CE_rings - currently handled by hif */
  352. default:
  353. return -QDF_STATUS_E_NOENT;
  354. break;
  355. }
  356. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  357. }
  358. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  359. *ring_params, int ring_type, int ring_num)
  360. {
  361. int msi_group_number;
  362. int msi_data_count;
  363. int ret;
  364. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  365. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  366. &msi_data_count, &msi_data_start,
  367. &msi_irq_start);
  368. if (ret)
  369. return;
  370. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  371. ring_num);
  372. if (msi_group_number < 0) {
  373. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  374. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  375. ring_type, ring_num);
  376. ring_params->msi_addr = 0;
  377. ring_params->msi_data = 0;
  378. return;
  379. }
  380. if (msi_group_number > msi_data_count) {
  381. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  382. FL("2 msi_groups will share an msi; msi_group_num %d"),
  383. msi_group_number);
  384. QDF_ASSERT(0);
  385. }
  386. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  387. ring_params->msi_addr = addr_low;
  388. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  389. ring_params->msi_data = (msi_group_number % msi_data_count)
  390. + msi_data_start;
  391. ring_params->flags |= HAL_SRNG_MSI_INTR;
  392. }
  393. /**
  394. * dp_print_ast_stats() - Dump AST table contents
  395. * @soc: Datapath soc handle
  396. *
  397. * return void
  398. */
  399. #ifdef FEATURE_WDS
  400. static void dp_print_ast_stats(struct dp_soc *soc)
  401. {
  402. uint8_t i;
  403. uint8_t num_entries = 0;
  404. struct dp_vdev *vdev;
  405. struct dp_pdev *pdev;
  406. struct dp_peer *peer;
  407. struct dp_ast_entry *ase, *tmp_ase;
  408. DP_PRINT_STATS("AST Stats:");
  409. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  410. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  411. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  412. DP_PRINT_STATS("AST Table:");
  413. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  414. pdev = soc->pdev_list[i];
  415. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  416. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  417. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  418. DP_PRINT_STATS("%6d mac_addr = %pM"
  419. " peer_mac_addr = %pM"
  420. " type = %d"
  421. " next_hop = %d"
  422. " is_active = %d"
  423. " is_bss = %d",
  424. ++num_entries,
  425. ase->mac_addr.raw,
  426. ase->peer->mac_addr.raw,
  427. ase->type,
  428. ase->next_hop,
  429. ase->is_active,
  430. ase->is_bss);
  431. }
  432. }
  433. }
  434. }
  435. }
  436. #else
  437. static void dp_print_ast_stats(struct dp_soc *soc)
  438. {
  439. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  440. return;
  441. }
  442. #endif
  443. /*
  444. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  445. */
  446. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  447. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  448. {
  449. void *hal_soc = soc->hal_soc;
  450. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  451. /* TODO: See if we should get align size from hal */
  452. uint32_t ring_base_align = 8;
  453. struct hal_srng_params ring_params;
  454. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  455. /* TODO: Currently hal layer takes care of endianness related settings.
  456. * See if these settings need to passed from DP layer
  457. */
  458. ring_params.flags = 0;
  459. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  460. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  461. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  462. srng->hal_srng = NULL;
  463. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  464. srng->num_entries = num_entries;
  465. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  466. soc->osdev, soc->osdev->dev, srng->alloc_size,
  467. &(srng->base_paddr_unaligned));
  468. if (!srng->base_vaddr_unaligned) {
  469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  470. FL("alloc failed - ring_type: %d, ring_num %d"),
  471. ring_type, ring_num);
  472. return QDF_STATUS_E_NOMEM;
  473. }
  474. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  475. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  476. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  477. ((unsigned long)(ring_params.ring_base_vaddr) -
  478. (unsigned long)srng->base_vaddr_unaligned);
  479. ring_params.num_entries = num_entries;
  480. if (soc->intr_mode == DP_INTR_MSI) {
  481. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  483. FL("Using MSI for ring_type: %d, ring_num %d"),
  484. ring_type, ring_num);
  485. } else {
  486. ring_params.msi_data = 0;
  487. ring_params.msi_addr = 0;
  488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  489. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  490. ring_type, ring_num);
  491. }
  492. /*
  493. * Setup interrupt timer and batch counter thresholds for
  494. * interrupt mitigation based on ring type
  495. */
  496. if (ring_type == REO_DST) {
  497. ring_params.intr_timer_thres_us =
  498. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  499. ring_params.intr_batch_cntr_thres_entries =
  500. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  501. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  502. ring_params.intr_timer_thres_us =
  503. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  504. ring_params.intr_batch_cntr_thres_entries =
  505. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  506. } else {
  507. ring_params.intr_timer_thres_us =
  508. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  509. ring_params.intr_batch_cntr_thres_entries =
  510. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  511. }
  512. /* Enable low threshold interrupts for rx buffer rings (regular and
  513. * monitor buffer rings.
  514. * TODO: See if this is required for any other ring
  515. */
  516. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  517. /* TODO: Setting low threshold to 1/8th of ring size
  518. * see if this needs to be configurable
  519. */
  520. ring_params.low_threshold = num_entries >> 3;
  521. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  522. ring_params.intr_timer_thres_us = 0x1000;
  523. }
  524. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  525. mac_id, &ring_params);
  526. return 0;
  527. }
  528. /**
  529. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  530. * Any buffers allocated and attached to ring entries are expected to be freed
  531. * before calling this function.
  532. */
  533. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  534. int ring_type, int ring_num)
  535. {
  536. if (!srng->hal_srng) {
  537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  538. FL("Ring type: %d, num:%d not setup"),
  539. ring_type, ring_num);
  540. return;
  541. }
  542. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  543. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  544. srng->alloc_size,
  545. srng->base_vaddr_unaligned,
  546. srng->base_paddr_unaligned, 0);
  547. srng->hal_srng = NULL;
  548. }
  549. /* TODO: Need this interface from HIF */
  550. void *hif_get_hal_handle(void *hif_handle);
  551. /*
  552. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  553. * @dp_ctx: DP SOC handle
  554. * @budget: Number of frames/descriptors that can be processed in one shot
  555. *
  556. * Return: remaining budget/quota for the soc device
  557. */
  558. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  559. {
  560. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  561. struct dp_soc *soc = int_ctx->soc;
  562. int ring = 0;
  563. uint32_t work_done = 0;
  564. int budget = dp_budget;
  565. uint8_t tx_mask = int_ctx->tx_ring_mask;
  566. uint8_t rx_mask = int_ctx->rx_ring_mask;
  567. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  568. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  569. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  570. uint32_t remaining_quota = dp_budget;
  571. struct dp_pdev *pdev = NULL;
  572. /* Process Tx completion interrupts first to return back buffers */
  573. while (tx_mask) {
  574. if (tx_mask & 0x1) {
  575. work_done = dp_tx_comp_handler(soc,
  576. soc->tx_comp_ring[ring].hal_srng,
  577. remaining_quota);
  578. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  579. "tx mask 0x%x ring %d, budget %d, work_done %d",
  580. tx_mask, ring, budget, work_done);
  581. budget -= work_done;
  582. if (budget <= 0)
  583. goto budget_done;
  584. remaining_quota = budget;
  585. }
  586. tx_mask = tx_mask >> 1;
  587. ring++;
  588. }
  589. /* Process REO Exception ring interrupt */
  590. if (rx_err_mask) {
  591. work_done = dp_rx_err_process(soc,
  592. soc->reo_exception_ring.hal_srng,
  593. remaining_quota);
  594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  595. "REO Exception Ring: work_done %d budget %d",
  596. work_done, budget);
  597. budget -= work_done;
  598. if (budget <= 0) {
  599. goto budget_done;
  600. }
  601. remaining_quota = budget;
  602. }
  603. /* Process Rx WBM release ring interrupt */
  604. if (rx_wbm_rel_mask) {
  605. work_done = dp_rx_wbm_err_process(soc,
  606. soc->rx_rel_ring.hal_srng, remaining_quota);
  607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  608. "WBM Release Ring: work_done %d budget %d",
  609. work_done, budget);
  610. budget -= work_done;
  611. if (budget <= 0) {
  612. goto budget_done;
  613. }
  614. remaining_quota = budget;
  615. }
  616. /* Process Rx interrupts */
  617. if (rx_mask) {
  618. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  619. if (rx_mask & (1 << ring)) {
  620. work_done = dp_rx_process(int_ctx,
  621. soc->reo_dest_ring[ring].hal_srng,
  622. remaining_quota);
  623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  624. "rx mask 0x%x ring %d, work_done %d budget %d",
  625. rx_mask, ring, work_done, budget);
  626. budget -= work_done;
  627. if (budget <= 0)
  628. goto budget_done;
  629. remaining_quota = budget;
  630. }
  631. }
  632. for (ring = 0; ring < MAX_RX_MAC_RINGS; ring++) {
  633. /* Need to check on this, why is required */
  634. work_done = dp_rxdma_err_process(soc, ring,
  635. remaining_quota);
  636. budget -= work_done;
  637. }
  638. }
  639. if (reo_status_mask)
  640. dp_reo_status_ring_handler(soc);
  641. /* Process LMAC interrupts */
  642. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  643. pdev = soc->pdev_list[ring];
  644. if (pdev == NULL)
  645. continue;
  646. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  647. work_done = dp_mon_process(soc, ring, remaining_quota);
  648. budget -= work_done;
  649. if (budget <= 0)
  650. goto budget_done;
  651. remaining_quota = budget;
  652. }
  653. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  654. work_done = dp_rxdma_err_process(soc, ring,
  655. remaining_quota);
  656. budget -= work_done;
  657. if (budget <= 0)
  658. goto budget_done;
  659. remaining_quota = budget;
  660. }
  661. if (int_ctx->host2rxdma_ring_mask & (1 << ring)) {
  662. union dp_rx_desc_list_elem_t *desc_list = NULL;
  663. union dp_rx_desc_list_elem_t *tail = NULL;
  664. struct dp_srng *rx_refill_buf_ring =
  665. &pdev->rx_refill_buf_ring;
  666. DP_STATS_INC(pdev, replenish.low_thresh_intrs, 1);
  667. dp_rx_buffers_replenish(soc, ring,
  668. rx_refill_buf_ring,
  669. &soc->rx_desc_buf[ring], 0,
  670. &desc_list, &tail, HAL_RX_BUF_RBM_SW3_BM);
  671. }
  672. }
  673. qdf_lro_flush(int_ctx->lro_ctx);
  674. budget_done:
  675. return dp_budget - budget;
  676. }
  677. #ifdef DP_INTR_POLL_BASED
  678. /* dp_interrupt_timer()- timer poll for interrupts
  679. *
  680. * @arg: SoC Handle
  681. *
  682. * Return:
  683. *
  684. */
  685. static void dp_interrupt_timer(void *arg)
  686. {
  687. struct dp_soc *soc = (struct dp_soc *) arg;
  688. int i;
  689. if (qdf_atomic_read(&soc->cmn_init_done)) {
  690. for (i = 0;
  691. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  692. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  693. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  694. }
  695. }
  696. /*
  697. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  698. * @txrx_soc: DP SOC handle
  699. *
  700. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  701. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  702. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  703. *
  704. * Return: 0 for success. nonzero for failure.
  705. */
  706. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  707. {
  708. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  709. int i;
  710. soc->intr_mode = DP_INTR_POLL;
  711. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  712. soc->intr_ctx[i].dp_intr_id = i;
  713. soc->intr_ctx[i].tx_ring_mask =
  714. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  715. soc->intr_ctx[i].rx_ring_mask =
  716. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  717. soc->intr_ctx[i].rx_mon_ring_mask =
  718. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  719. soc->intr_ctx[i].rx_err_ring_mask =
  720. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  721. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  722. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  723. soc->intr_ctx[i].reo_status_ring_mask =
  724. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  725. soc->intr_ctx[i].rxdma2host_ring_mask =
  726. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  727. soc->intr_ctx[i].soc = soc;
  728. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  729. }
  730. qdf_timer_init(soc->osdev, &soc->int_timer,
  731. dp_interrupt_timer, (void *)soc,
  732. QDF_TIMER_TYPE_WAKE_APPS);
  733. return QDF_STATUS_SUCCESS;
  734. }
  735. #if defined(CONFIG_MCL)
  736. extern int con_mode_monitor;
  737. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  738. /*
  739. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  740. * @txrx_soc: DP SOC handle
  741. *
  742. * Call the appropriate attach function based on the mode of operation.
  743. * This is a WAR for enabling monitor mode.
  744. *
  745. * Return: 0 for success. nonzero for failure.
  746. */
  747. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  748. {
  749. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  750. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  751. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  752. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  753. "%s: Poll mode", __func__);
  754. return dp_soc_interrupt_attach_poll(txrx_soc);
  755. } else {
  756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  757. "%s: Interrupt mode", __func__);
  758. return dp_soc_interrupt_attach(txrx_soc);
  759. }
  760. }
  761. #else
  762. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  763. {
  764. return dp_soc_interrupt_attach_poll(txrx_soc);
  765. }
  766. #endif
  767. #endif
  768. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  769. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  770. {
  771. int j;
  772. int num_irq = 0;
  773. int tx_mask =
  774. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  775. int rx_mask =
  776. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  777. int rx_mon_mask =
  778. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  779. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  780. soc->wlan_cfg_ctx, intr_ctx_num);
  781. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  782. soc->wlan_cfg_ctx, intr_ctx_num);
  783. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  784. soc->wlan_cfg_ctx, intr_ctx_num);
  785. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  786. soc->wlan_cfg_ctx, intr_ctx_num);
  787. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  788. soc->wlan_cfg_ctx, intr_ctx_num);
  789. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  790. if (tx_mask & (1 << j)) {
  791. irq_id_map[num_irq++] =
  792. (wbm2host_tx_completions_ring1 - j);
  793. }
  794. if (rx_mask & (1 << j)) {
  795. irq_id_map[num_irq++] =
  796. (reo2host_destination_ring1 - j);
  797. }
  798. if (rxdma2host_ring_mask & (1 << j)) {
  799. irq_id_map[num_irq++] =
  800. rxdma2host_destination_ring_mac1 -
  801. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  802. }
  803. if (host2rxdma_ring_mask & (1 << j)) {
  804. irq_id_map[num_irq++] =
  805. host2rxdma_host_buf_ring_mac1 -
  806. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  807. }
  808. if (rx_mon_mask & (1 << j)) {
  809. irq_id_map[num_irq++] =
  810. ppdu_end_interrupts_mac1 -
  811. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  812. }
  813. if (rx_wbm_rel_ring_mask & (1 << j))
  814. irq_id_map[num_irq++] = wbm2host_rx_release;
  815. if (rx_err_ring_mask & (1 << j))
  816. irq_id_map[num_irq++] = reo2host_exception;
  817. if (reo_status_ring_mask & (1 << j))
  818. irq_id_map[num_irq++] = reo2host_status;
  819. }
  820. *num_irq_r = num_irq;
  821. }
  822. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  823. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  824. int msi_vector_count, int msi_vector_start)
  825. {
  826. int tx_mask = wlan_cfg_get_tx_ring_mask(
  827. soc->wlan_cfg_ctx, intr_ctx_num);
  828. int rx_mask = wlan_cfg_get_rx_ring_mask(
  829. soc->wlan_cfg_ctx, intr_ctx_num);
  830. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  831. soc->wlan_cfg_ctx, intr_ctx_num);
  832. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  833. soc->wlan_cfg_ctx, intr_ctx_num);
  834. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  835. soc->wlan_cfg_ctx, intr_ctx_num);
  836. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  837. soc->wlan_cfg_ctx, intr_ctx_num);
  838. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  839. soc->wlan_cfg_ctx, intr_ctx_num);
  840. unsigned int vector =
  841. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  842. int num_irq = 0;
  843. soc->intr_mode = DP_INTR_MSI;
  844. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  845. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  846. irq_id_map[num_irq++] =
  847. pld_get_msi_irq(soc->osdev->dev, vector);
  848. *num_irq_r = num_irq;
  849. }
  850. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  851. int *irq_id_map, int *num_irq)
  852. {
  853. int msi_vector_count, ret;
  854. uint32_t msi_base_data, msi_vector_start;
  855. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  856. &msi_vector_count,
  857. &msi_base_data,
  858. &msi_vector_start);
  859. if (ret)
  860. return dp_soc_interrupt_map_calculate_integrated(soc,
  861. intr_ctx_num, irq_id_map, num_irq);
  862. else
  863. dp_soc_interrupt_map_calculate_msi(soc,
  864. intr_ctx_num, irq_id_map, num_irq,
  865. msi_vector_count, msi_vector_start);
  866. }
  867. /*
  868. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  869. * @txrx_soc: DP SOC handle
  870. *
  871. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  872. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  873. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  874. *
  875. * Return: 0 for success. nonzero for failure.
  876. */
  877. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  878. {
  879. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  880. int i = 0;
  881. int num_irq = 0;
  882. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  883. int ret = 0;
  884. /* Map of IRQ ids registered with one interrupt context */
  885. int irq_id_map[HIF_MAX_GRP_IRQ];
  886. int tx_mask =
  887. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  888. int rx_mask =
  889. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  890. int rx_mon_mask =
  891. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  892. int rx_err_ring_mask =
  893. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  894. int rx_wbm_rel_ring_mask =
  895. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  896. int reo_status_ring_mask =
  897. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  898. int rxdma2host_ring_mask =
  899. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  900. int host2rxdma_ring_mask =
  901. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  902. soc->intr_ctx[i].dp_intr_id = i;
  903. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  904. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  905. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  906. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  907. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  908. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  909. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  910. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  911. soc->intr_ctx[i].soc = soc;
  912. num_irq = 0;
  913. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  914. &num_irq);
  915. ret = hif_register_ext_group(soc->hif_handle,
  916. num_irq, irq_id_map, dp_service_srngs,
  917. &soc->intr_ctx[i], "dp_intr",
  918. HIF_EXEC_NAPI_TYPE, QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  919. if (ret) {
  920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  921. FL("failed, ret = %d"), ret);
  922. return QDF_STATUS_E_FAILURE;
  923. }
  924. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  925. }
  926. hif_configure_ext_group_interrupts(soc->hif_handle);
  927. return QDF_STATUS_SUCCESS;
  928. }
  929. /*
  930. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  931. * @txrx_soc: DP SOC handle
  932. *
  933. * Return: void
  934. */
  935. static void dp_soc_interrupt_detach(void *txrx_soc)
  936. {
  937. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  938. int i;
  939. if (soc->intr_mode == DP_INTR_POLL) {
  940. qdf_timer_stop(&soc->int_timer);
  941. qdf_timer_free(&soc->int_timer);
  942. } else {
  943. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  944. }
  945. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  946. soc->intr_ctx[i].tx_ring_mask = 0;
  947. soc->intr_ctx[i].rx_ring_mask = 0;
  948. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  949. soc->intr_ctx[i].rx_err_ring_mask = 0;
  950. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  951. soc->intr_ctx[i].reo_status_ring_mask = 0;
  952. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  953. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  954. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  955. }
  956. }
  957. #define AVG_MAX_MPDUS_PER_TID 128
  958. #define AVG_TIDS_PER_CLIENT 2
  959. #define AVG_FLOWS_PER_TID 2
  960. #define AVG_MSDUS_PER_FLOW 128
  961. #define AVG_MSDUS_PER_MPDU 4
  962. /*
  963. * Allocate and setup link descriptor pool that will be used by HW for
  964. * various link and queue descriptors and managed by WBM
  965. */
  966. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  967. {
  968. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  969. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  970. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  971. uint32_t num_mpdus_per_link_desc =
  972. hal_num_mpdus_per_link_desc(soc->hal_soc);
  973. uint32_t num_msdus_per_link_desc =
  974. hal_num_msdus_per_link_desc(soc->hal_soc);
  975. uint32_t num_mpdu_links_per_queue_desc =
  976. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  977. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  978. uint32_t total_link_descs, total_mem_size;
  979. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  980. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  981. uint32_t num_link_desc_banks;
  982. uint32_t last_bank_size = 0;
  983. uint32_t entry_size, num_entries;
  984. int i;
  985. uint32_t desc_id = 0;
  986. /* Only Tx queue descriptors are allocated from common link descriptor
  987. * pool Rx queue descriptors are not included in this because (REO queue
  988. * extension descriptors) they are expected to be allocated contiguously
  989. * with REO queue descriptors
  990. */
  991. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  992. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  993. num_mpdu_queue_descs = num_mpdu_link_descs /
  994. num_mpdu_links_per_queue_desc;
  995. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  996. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  997. num_msdus_per_link_desc;
  998. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  999. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1000. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1001. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1002. /* Round up to power of 2 */
  1003. total_link_descs = 1;
  1004. while (total_link_descs < num_entries)
  1005. total_link_descs <<= 1;
  1006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1007. FL("total_link_descs: %u, link_desc_size: %d"),
  1008. total_link_descs, link_desc_size);
  1009. total_mem_size = total_link_descs * link_desc_size;
  1010. total_mem_size += link_desc_align;
  1011. if (total_mem_size <= max_alloc_size) {
  1012. num_link_desc_banks = 0;
  1013. last_bank_size = total_mem_size;
  1014. } else {
  1015. num_link_desc_banks = (total_mem_size) /
  1016. (max_alloc_size - link_desc_align);
  1017. last_bank_size = total_mem_size %
  1018. (max_alloc_size - link_desc_align);
  1019. }
  1020. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1021. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1022. total_mem_size, num_link_desc_banks);
  1023. for (i = 0; i < num_link_desc_banks; i++) {
  1024. soc->link_desc_banks[i].base_vaddr_unaligned =
  1025. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1026. max_alloc_size,
  1027. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1028. soc->link_desc_banks[i].size = max_alloc_size;
  1029. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1030. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1031. ((unsigned long)(
  1032. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1033. link_desc_align));
  1034. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1035. soc->link_desc_banks[i].base_paddr_unaligned) +
  1036. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1037. (unsigned long)(
  1038. soc->link_desc_banks[i].base_vaddr_unaligned));
  1039. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1040. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1041. FL("Link descriptor memory alloc failed"));
  1042. goto fail;
  1043. }
  1044. }
  1045. if (last_bank_size) {
  1046. /* Allocate last bank in case total memory required is not exact
  1047. * multiple of max_alloc_size
  1048. */
  1049. soc->link_desc_banks[i].base_vaddr_unaligned =
  1050. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1051. last_bank_size,
  1052. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1053. soc->link_desc_banks[i].size = last_bank_size;
  1054. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1055. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1056. ((unsigned long)(
  1057. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1058. link_desc_align));
  1059. soc->link_desc_banks[i].base_paddr =
  1060. (unsigned long)(
  1061. soc->link_desc_banks[i].base_paddr_unaligned) +
  1062. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1063. (unsigned long)(
  1064. soc->link_desc_banks[i].base_vaddr_unaligned));
  1065. }
  1066. /* Allocate and setup link descriptor idle list for HW internal use */
  1067. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1068. total_mem_size = entry_size * total_link_descs;
  1069. if (total_mem_size <= max_alloc_size) {
  1070. void *desc;
  1071. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1072. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1074. FL("Link desc idle ring setup failed"));
  1075. goto fail;
  1076. }
  1077. hal_srng_access_start_unlocked(soc->hal_soc,
  1078. soc->wbm_idle_link_ring.hal_srng);
  1079. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1080. soc->link_desc_banks[i].base_paddr; i++) {
  1081. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1082. ((unsigned long)(
  1083. soc->link_desc_banks[i].base_vaddr) -
  1084. (unsigned long)(
  1085. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1086. / link_desc_size;
  1087. unsigned long paddr = (unsigned long)(
  1088. soc->link_desc_banks[i].base_paddr);
  1089. while (num_entries && (desc = hal_srng_src_get_next(
  1090. soc->hal_soc,
  1091. soc->wbm_idle_link_ring.hal_srng))) {
  1092. hal_set_link_desc_addr(desc,
  1093. LINK_DESC_COOKIE(desc_id, i), paddr);
  1094. num_entries--;
  1095. desc_id++;
  1096. paddr += link_desc_size;
  1097. }
  1098. }
  1099. hal_srng_access_end_unlocked(soc->hal_soc,
  1100. soc->wbm_idle_link_ring.hal_srng);
  1101. } else {
  1102. uint32_t num_scatter_bufs;
  1103. uint32_t num_entries_per_buf;
  1104. uint32_t rem_entries;
  1105. uint8_t *scatter_buf_ptr;
  1106. uint16_t scatter_buf_num;
  1107. soc->wbm_idle_scatter_buf_size =
  1108. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1109. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1110. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1111. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1112. soc->hal_soc, total_mem_size,
  1113. soc->wbm_idle_scatter_buf_size);
  1114. for (i = 0; i < num_scatter_bufs; i++) {
  1115. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1116. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1117. soc->wbm_idle_scatter_buf_size,
  1118. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1119. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1120. QDF_TRACE(QDF_MODULE_ID_DP,
  1121. QDF_TRACE_LEVEL_ERROR,
  1122. FL("Scatter list memory alloc failed"));
  1123. goto fail;
  1124. }
  1125. }
  1126. /* Populate idle list scatter buffers with link descriptor
  1127. * pointers
  1128. */
  1129. scatter_buf_num = 0;
  1130. scatter_buf_ptr = (uint8_t *)(
  1131. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1132. rem_entries = num_entries_per_buf;
  1133. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1134. soc->link_desc_banks[i].base_paddr; i++) {
  1135. uint32_t num_link_descs =
  1136. (soc->link_desc_banks[i].size -
  1137. ((unsigned long)(
  1138. soc->link_desc_banks[i].base_vaddr) -
  1139. (unsigned long)(
  1140. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1141. / link_desc_size;
  1142. unsigned long paddr = (unsigned long)(
  1143. soc->link_desc_banks[i].base_paddr);
  1144. while (num_link_descs) {
  1145. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1146. LINK_DESC_COOKIE(desc_id, i), paddr);
  1147. num_link_descs--;
  1148. desc_id++;
  1149. paddr += link_desc_size;
  1150. rem_entries--;
  1151. if (rem_entries) {
  1152. scatter_buf_ptr += entry_size;
  1153. } else {
  1154. rem_entries = num_entries_per_buf;
  1155. scatter_buf_num++;
  1156. if (scatter_buf_num >= num_scatter_bufs)
  1157. break;
  1158. scatter_buf_ptr = (uint8_t *)(
  1159. soc->wbm_idle_scatter_buf_base_vaddr[
  1160. scatter_buf_num]);
  1161. }
  1162. }
  1163. }
  1164. /* Setup link descriptor idle list in HW */
  1165. hal_setup_link_idle_list(soc->hal_soc,
  1166. soc->wbm_idle_scatter_buf_base_paddr,
  1167. soc->wbm_idle_scatter_buf_base_vaddr,
  1168. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1169. (uint32_t)(scatter_buf_ptr -
  1170. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1171. scatter_buf_num-1])), total_link_descs);
  1172. }
  1173. return 0;
  1174. fail:
  1175. if (soc->wbm_idle_link_ring.hal_srng) {
  1176. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1177. WBM_IDLE_LINK, 0);
  1178. }
  1179. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1180. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1181. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1182. soc->wbm_idle_scatter_buf_size,
  1183. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1184. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1185. }
  1186. }
  1187. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1188. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1189. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1190. soc->link_desc_banks[i].size,
  1191. soc->link_desc_banks[i].base_vaddr_unaligned,
  1192. soc->link_desc_banks[i].base_paddr_unaligned,
  1193. 0);
  1194. }
  1195. }
  1196. return QDF_STATUS_E_FAILURE;
  1197. }
  1198. /*
  1199. * Free link descriptor pool that was setup HW
  1200. */
  1201. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1202. {
  1203. int i;
  1204. if (soc->wbm_idle_link_ring.hal_srng) {
  1205. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1206. WBM_IDLE_LINK, 0);
  1207. }
  1208. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1209. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1210. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1211. soc->wbm_idle_scatter_buf_size,
  1212. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1213. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1214. }
  1215. }
  1216. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1217. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1218. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1219. soc->link_desc_banks[i].size,
  1220. soc->link_desc_banks[i].base_vaddr_unaligned,
  1221. soc->link_desc_banks[i].base_paddr_unaligned,
  1222. 0);
  1223. }
  1224. }
  1225. }
  1226. /* TODO: Following should be configurable */
  1227. #define WBM_RELEASE_RING_SIZE 64
  1228. #define TCL_CMD_RING_SIZE 32
  1229. #define TCL_STATUS_RING_SIZE 32
  1230. #if defined(QCA_WIFI_QCA6290)
  1231. #define REO_DST_RING_SIZE 1024
  1232. #else
  1233. #define REO_DST_RING_SIZE 2048
  1234. #endif
  1235. #define REO_REINJECT_RING_SIZE 32
  1236. #define RX_RELEASE_RING_SIZE 1024
  1237. #define REO_EXCEPTION_RING_SIZE 128
  1238. #define REO_CMD_RING_SIZE 32
  1239. #define REO_STATUS_RING_SIZE 32
  1240. #define RXDMA_BUF_RING_SIZE 1024
  1241. #define RXDMA_REFILL_RING_SIZE 4096
  1242. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1243. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1244. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1245. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1246. #define RXDMA_ERR_DST_RING_SIZE 1024
  1247. /*
  1248. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1249. * @soc: Datapath SOC handle
  1250. *
  1251. * This is a timer function used to age out stale WDS nodes from
  1252. * AST table
  1253. */
  1254. #ifdef FEATURE_WDS
  1255. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1256. {
  1257. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1258. struct dp_pdev *pdev;
  1259. struct dp_vdev *vdev;
  1260. struct dp_peer *peer;
  1261. struct dp_ast_entry *ase, *temp_ase;
  1262. int i;
  1263. qdf_spin_lock_bh(&soc->ast_lock);
  1264. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1265. pdev = soc->pdev_list[i];
  1266. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1267. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1268. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1269. /*
  1270. * Do not expire static ast entries
  1271. */
  1272. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1273. continue;
  1274. if (ase->is_active) {
  1275. ase->is_active = FALSE;
  1276. continue;
  1277. }
  1278. DP_STATS_INC(soc, ast.aged_out, 1);
  1279. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1280. pdev->osif_pdev,
  1281. ase->mac_addr.raw);
  1282. dp_peer_del_ast(soc, ase);
  1283. }
  1284. }
  1285. }
  1286. }
  1287. qdf_spin_unlock_bh(&soc->ast_lock);
  1288. if (qdf_atomic_read(&soc->cmn_init_done))
  1289. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1290. }
  1291. /*
  1292. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1293. * @soc: Datapath SOC handle
  1294. *
  1295. * Return: None
  1296. */
  1297. static void dp_soc_wds_attach(struct dp_soc *soc)
  1298. {
  1299. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1300. dp_wds_aging_timer_fn, (void *)soc,
  1301. QDF_TIMER_TYPE_WAKE_APPS);
  1302. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1303. }
  1304. /*
  1305. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1306. * @txrx_soc: DP SOC handle
  1307. *
  1308. * Return: None
  1309. */
  1310. static void dp_soc_wds_detach(struct dp_soc *soc)
  1311. {
  1312. qdf_timer_stop(&soc->wds_aging_timer);
  1313. qdf_timer_free(&soc->wds_aging_timer);
  1314. }
  1315. #else
  1316. static void dp_soc_wds_attach(struct dp_soc *soc)
  1317. {
  1318. }
  1319. static void dp_soc_wds_detach(struct dp_soc *soc)
  1320. {
  1321. }
  1322. #endif
  1323. /*
  1324. * dp_soc_reset_ring_map() - Reset cpu ring map
  1325. * @soc: Datapath soc handler
  1326. *
  1327. * This api resets the default cpu ring map
  1328. */
  1329. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1330. {
  1331. uint8_t i;
  1332. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1333. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1334. if (nss_config == 1) {
  1335. /*
  1336. * Setting Tx ring map for one nss offloaded radio
  1337. */
  1338. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1339. } else if (nss_config == 2) {
  1340. /*
  1341. * Setting Tx ring for two nss offloaded radios
  1342. */
  1343. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1344. } else {
  1345. /*
  1346. * Setting Tx ring map for all nss offloaded radios
  1347. */
  1348. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1349. }
  1350. }
  1351. }
  1352. /*
  1353. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1354. * @dp_soc - DP soc handle
  1355. * @ring_type - ring type
  1356. * @ring_num - ring_num
  1357. *
  1358. * return 0 or 1
  1359. */
  1360. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1361. {
  1362. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1363. uint8_t status = 0;
  1364. switch (ring_type) {
  1365. case WBM2SW_RELEASE:
  1366. case REO_DST:
  1367. case RXDMA_BUF:
  1368. status = ((nss_config) & (1 << ring_num));
  1369. break;
  1370. default:
  1371. break;
  1372. }
  1373. return status;
  1374. }
  1375. /*
  1376. * dp_soc_reset_intr_mask() - reset interrupt mask
  1377. * @dp_soc - DP Soc handle
  1378. *
  1379. * Return: Return void
  1380. */
  1381. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1382. {
  1383. uint8_t j;
  1384. int *grp_mask = NULL;
  1385. int group_number, mask, num_ring;
  1386. /* number of tx ring */
  1387. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1388. /*
  1389. * group mask for tx completion ring.
  1390. */
  1391. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1392. /* loop and reset the mask for only offloaded ring */
  1393. for (j = 0; j < num_ring; j++) {
  1394. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1395. continue;
  1396. }
  1397. /*
  1398. * Group number corresponding to tx offloaded ring.
  1399. */
  1400. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1401. if (group_number < 0) {
  1402. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1403. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1404. WBM2SW_RELEASE, j);
  1405. return;
  1406. }
  1407. /* reset the tx mask for offloaded ring */
  1408. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1409. mask &= (~(1 << j));
  1410. /*
  1411. * reset the interrupt mask for offloaded ring.
  1412. */
  1413. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1414. }
  1415. /* number of rx rings */
  1416. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1417. /*
  1418. * group mask for reo destination ring.
  1419. */
  1420. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1421. /* loop and reset the mask for only offloaded ring */
  1422. for (j = 0; j < num_ring; j++) {
  1423. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1424. continue;
  1425. }
  1426. /*
  1427. * Group number corresponding to rx offloaded ring.
  1428. */
  1429. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1430. if (group_number < 0) {
  1431. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1432. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1433. REO_DST, j);
  1434. return;
  1435. }
  1436. /* set the interrupt mask for offloaded ring */
  1437. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1438. mask &= (~(1 << j));
  1439. /*
  1440. * set the interrupt mask to zero for rx offloaded radio.
  1441. */
  1442. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1443. }
  1444. /*
  1445. * group mask for Rx buffer refill ring
  1446. */
  1447. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  1448. /* loop and reset the mask for only offloaded ring */
  1449. for (j = 0; j < MAX_PDEV_CNT; j++) {
  1450. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  1451. continue;
  1452. }
  1453. /*
  1454. * Group number corresponding to rx offloaded ring.
  1455. */
  1456. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1457. if (group_number < 0) {
  1458. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1459. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1460. REO_DST, j);
  1461. return;
  1462. }
  1463. /* set the interrupt mask for offloaded ring */
  1464. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1465. group_number);
  1466. mask &= (~(1 << j));
  1467. /*
  1468. * set the interrupt mask to zero for rx offloaded radio.
  1469. */
  1470. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1471. group_number, mask);
  1472. }
  1473. }
  1474. #ifdef IPA_OFFLOAD
  1475. /**
  1476. * dp_reo_remap_config() - configure reo remap register value based
  1477. * nss configuration.
  1478. * based on offload_radio value below remap configuration
  1479. * get applied.
  1480. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1481. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1482. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1483. * 3 - both Radios handled by NSS (remap not required)
  1484. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1485. *
  1486. * @remap1: output parameter indicates reo remap 1 register value
  1487. * @remap2: output parameter indicates reo remap 2 register value
  1488. * Return: bool type, true if remap is configured else false.
  1489. */
  1490. static bool dp_reo_remap_config(struct dp_soc *soc,
  1491. uint32_t *remap1,
  1492. uint32_t *remap2)
  1493. {
  1494. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1495. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1496. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1497. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1498. return true;
  1499. }
  1500. #else
  1501. static bool dp_reo_remap_config(struct dp_soc *soc,
  1502. uint32_t *remap1,
  1503. uint32_t *remap2)
  1504. {
  1505. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1506. switch (offload_radio) {
  1507. case 0:
  1508. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1509. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1510. (0x3 << 18) | (0x4 << 21)) << 8;
  1511. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1512. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1513. (0x3 << 18) | (0x4 << 21)) << 8;
  1514. break;
  1515. case 1:
  1516. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1517. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1518. (0x2 << 18) | (0x3 << 21)) << 8;
  1519. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1520. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1521. (0x4 << 18) | (0x2 << 21)) << 8;
  1522. break;
  1523. case 2:
  1524. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1525. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1526. (0x1 << 18) | (0x3 << 21)) << 8;
  1527. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1528. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1529. (0x4 << 18) | (0x1 << 21)) << 8;
  1530. break;
  1531. case 3:
  1532. /* return false if both radios are offloaded to NSS */
  1533. return false;
  1534. }
  1535. return true;
  1536. }
  1537. #endif
  1538. /*
  1539. * dp_soc_cmn_setup() - Common SoC level initializion
  1540. * @soc: Datapath SOC handle
  1541. *
  1542. * This is an internal function used to setup common SOC data structures,
  1543. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1544. */
  1545. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1546. {
  1547. int i;
  1548. struct hal_reo_params reo_params;
  1549. int tx_ring_size;
  1550. int tx_comp_ring_size;
  1551. if (qdf_atomic_read(&soc->cmn_init_done))
  1552. return 0;
  1553. if (dp_peer_find_attach(soc))
  1554. goto fail0;
  1555. if (dp_hw_link_desc_pool_setup(soc))
  1556. goto fail1;
  1557. /* Setup SRNG rings */
  1558. /* Common rings */
  1559. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1560. WBM_RELEASE_RING_SIZE)) {
  1561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1562. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1563. goto fail1;
  1564. }
  1565. soc->num_tcl_data_rings = 0;
  1566. /* Tx data rings */
  1567. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1568. soc->num_tcl_data_rings =
  1569. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1570. tx_comp_ring_size =
  1571. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1572. tx_ring_size =
  1573. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1574. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1575. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1576. TCL_DATA, i, 0, tx_ring_size)) {
  1577. QDF_TRACE(QDF_MODULE_ID_DP,
  1578. QDF_TRACE_LEVEL_ERROR,
  1579. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1580. goto fail1;
  1581. }
  1582. /*
  1583. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1584. * count
  1585. */
  1586. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1587. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1588. QDF_TRACE(QDF_MODULE_ID_DP,
  1589. QDF_TRACE_LEVEL_ERROR,
  1590. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1591. goto fail1;
  1592. }
  1593. }
  1594. } else {
  1595. /* This will be incremented during per pdev ring setup */
  1596. soc->num_tcl_data_rings = 0;
  1597. }
  1598. if (dp_tx_soc_attach(soc)) {
  1599. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1600. FL("dp_tx_soc_attach failed"));
  1601. goto fail1;
  1602. }
  1603. /* TCL command and status rings */
  1604. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1605. TCL_CMD_RING_SIZE)) {
  1606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1607. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1608. goto fail1;
  1609. }
  1610. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1611. TCL_STATUS_RING_SIZE)) {
  1612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1613. FL("dp_srng_setup failed for tcl_status_ring"));
  1614. goto fail1;
  1615. }
  1616. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1617. * descriptors
  1618. */
  1619. /* Rx data rings */
  1620. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1621. soc->num_reo_dest_rings =
  1622. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1623. QDF_TRACE(QDF_MODULE_ID_DP,
  1624. QDF_TRACE_LEVEL_ERROR,
  1625. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1626. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1627. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1628. i, 0, REO_DST_RING_SIZE)) {
  1629. QDF_TRACE(QDF_MODULE_ID_DP,
  1630. QDF_TRACE_LEVEL_ERROR,
  1631. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1632. goto fail1;
  1633. }
  1634. }
  1635. } else {
  1636. /* This will be incremented during per pdev ring setup */
  1637. soc->num_reo_dest_rings = 0;
  1638. }
  1639. /* LMAC RxDMA to SW Rings configuration */
  1640. if (!wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  1641. /* Only valid for MCL */
  1642. struct dp_pdev *pdev = soc->pdev_list[0];
  1643. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  1644. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[i],
  1645. RXDMA_DST, 0, i, RXDMA_ERR_DST_RING_SIZE)) {
  1646. QDF_TRACE(QDF_MODULE_ID_DP,
  1647. QDF_TRACE_LEVEL_ERROR,
  1648. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  1649. goto fail1;
  1650. }
  1651. }
  1652. }
  1653. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1654. /* REO reinjection ring */
  1655. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1656. REO_REINJECT_RING_SIZE)) {
  1657. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1658. FL("dp_srng_setup failed for reo_reinject_ring"));
  1659. goto fail1;
  1660. }
  1661. /* Rx release ring */
  1662. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1663. RX_RELEASE_RING_SIZE)) {
  1664. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1665. FL("dp_srng_setup failed for rx_rel_ring"));
  1666. goto fail1;
  1667. }
  1668. /* Rx exception ring */
  1669. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1670. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1671. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1672. FL("dp_srng_setup failed for reo_exception_ring"));
  1673. goto fail1;
  1674. }
  1675. /* REO command and status rings */
  1676. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1677. REO_CMD_RING_SIZE)) {
  1678. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1679. FL("dp_srng_setup failed for reo_cmd_ring"));
  1680. goto fail1;
  1681. }
  1682. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1683. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1684. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1685. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1686. REO_STATUS_RING_SIZE)) {
  1687. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1688. FL("dp_srng_setup failed for reo_status_ring"));
  1689. goto fail1;
  1690. }
  1691. qdf_spinlock_create(&soc->ast_lock);
  1692. dp_soc_wds_attach(soc);
  1693. /* Reset the cpu ring map if radio is NSS offloaded */
  1694. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1695. dp_soc_reset_cpu_ring_map(soc);
  1696. dp_soc_reset_intr_mask(soc);
  1697. }
  1698. /* Setup HW REO */
  1699. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1700. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1701. /*
  1702. * Reo ring remap is not required if both radios
  1703. * are offloaded to NSS
  1704. */
  1705. if (!dp_reo_remap_config(soc,
  1706. &reo_params.remap1,
  1707. &reo_params.remap2))
  1708. goto out;
  1709. reo_params.rx_hash_enabled = true;
  1710. }
  1711. out:
  1712. hal_reo_setup(soc->hal_soc, &reo_params);
  1713. qdf_atomic_set(&soc->cmn_init_done, 1);
  1714. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1715. return 0;
  1716. fail1:
  1717. /*
  1718. * Cleanup will be done as part of soc_detach, which will
  1719. * be called on pdev attach failure
  1720. */
  1721. fail0:
  1722. return QDF_STATUS_E_FAILURE;
  1723. }
  1724. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1725. static void dp_lro_hash_setup(struct dp_soc *soc)
  1726. {
  1727. struct cdp_lro_hash_config lro_hash;
  1728. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1729. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1730. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1731. FL("LRO disabled RX hash disabled"));
  1732. return;
  1733. }
  1734. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1735. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1736. lro_hash.lro_enable = 1;
  1737. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1738. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1739. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1740. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1741. }
  1742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1743. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1744. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1745. LRO_IPV4_SEED_ARR_SZ));
  1746. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1747. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1748. LRO_IPV6_SEED_ARR_SZ));
  1749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1750. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1751. lro_hash.lro_enable, lro_hash.tcp_flag,
  1752. lro_hash.tcp_flag_mask);
  1753. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1754. QDF_TRACE_LEVEL_ERROR,
  1755. (void *)lro_hash.toeplitz_hash_ipv4,
  1756. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1757. LRO_IPV4_SEED_ARR_SZ));
  1758. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1759. QDF_TRACE_LEVEL_ERROR,
  1760. (void *)lro_hash.toeplitz_hash_ipv6,
  1761. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1762. LRO_IPV6_SEED_ARR_SZ));
  1763. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1764. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1765. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1766. (soc->osif_soc, &lro_hash);
  1767. }
  1768. /*
  1769. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1770. * @soc: data path SoC handle
  1771. * @pdev: Physical device handle
  1772. *
  1773. * Return: 0 - success, > 0 - failure
  1774. */
  1775. #ifdef QCA_HOST2FW_RXBUF_RING
  1776. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1777. struct dp_pdev *pdev)
  1778. {
  1779. int max_mac_rings =
  1780. wlan_cfg_get_num_mac_rings
  1781. (pdev->wlan_cfg_ctx);
  1782. int i;
  1783. for (i = 0; i < max_mac_rings; i++) {
  1784. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1785. "%s: pdev_id %d mac_id %d\n",
  1786. __func__, pdev->pdev_id, i);
  1787. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1788. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1789. QDF_TRACE(QDF_MODULE_ID_DP,
  1790. QDF_TRACE_LEVEL_ERROR,
  1791. FL("failed rx mac ring setup"));
  1792. return QDF_STATUS_E_FAILURE;
  1793. }
  1794. }
  1795. return QDF_STATUS_SUCCESS;
  1796. }
  1797. #else
  1798. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1799. struct dp_pdev *pdev)
  1800. {
  1801. return QDF_STATUS_SUCCESS;
  1802. }
  1803. #endif
  1804. /**
  1805. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1806. * @pdev - DP_PDEV handle
  1807. *
  1808. * Return: void
  1809. */
  1810. static inline void
  1811. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1812. {
  1813. uint8_t map_id;
  1814. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1815. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1816. sizeof(default_dscp_tid_map));
  1817. }
  1818. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1819. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1820. pdev->dscp_tid_map[map_id],
  1821. map_id);
  1822. }
  1823. }
  1824. /*
  1825. * dp_pdev_attach_wifi3() - attach txrx pdev
  1826. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1827. * @txrx_soc: Datapath SOC handle
  1828. * @htc_handle: HTC handle for host-target interface
  1829. * @qdf_osdev: QDF OS device
  1830. * @pdev_id: PDEV ID
  1831. *
  1832. * Return: DP PDEV handle on success, NULL on failure
  1833. */
  1834. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1835. struct cdp_cfg *ctrl_pdev,
  1836. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1837. {
  1838. int tx_ring_size;
  1839. int tx_comp_ring_size;
  1840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1841. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1842. if (!pdev) {
  1843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1844. FL("DP PDEV memory allocation failed"));
  1845. goto fail0;
  1846. }
  1847. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1848. if (!pdev->wlan_cfg_ctx) {
  1849. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1850. FL("pdev cfg_attach failed"));
  1851. qdf_mem_free(pdev);
  1852. goto fail0;
  1853. }
  1854. /*
  1855. * set nss pdev config based on soc config
  1856. */
  1857. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1858. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1859. pdev->soc = soc;
  1860. pdev->osif_pdev = ctrl_pdev;
  1861. pdev->pdev_id = pdev_id;
  1862. soc->pdev_list[pdev_id] = pdev;
  1863. soc->pdev_count++;
  1864. TAILQ_INIT(&pdev->vdev_list);
  1865. pdev->vdev_count = 0;
  1866. qdf_spinlock_create(&pdev->tx_mutex);
  1867. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1868. TAILQ_INIT(&pdev->neighbour_peers_list);
  1869. if (dp_soc_cmn_setup(soc)) {
  1870. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1871. FL("dp_soc_cmn_setup failed"));
  1872. goto fail1;
  1873. }
  1874. /* Setup per PDEV TCL rings if configured */
  1875. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1876. tx_ring_size =
  1877. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1878. tx_comp_ring_size =
  1879. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1880. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1881. pdev_id, pdev_id, tx_ring_size)) {
  1882. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1883. FL("dp_srng_setup failed for tcl_data_ring"));
  1884. goto fail1;
  1885. }
  1886. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1887. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1888. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1889. FL("dp_srng_setup failed for tx_comp_ring"));
  1890. goto fail1;
  1891. }
  1892. soc->num_tcl_data_rings++;
  1893. }
  1894. /* Tx specific init */
  1895. if (dp_tx_pdev_attach(pdev)) {
  1896. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1897. FL("dp_tx_pdev_attach failed"));
  1898. goto fail1;
  1899. }
  1900. /* Setup per PDEV REO rings if configured */
  1901. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1902. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1903. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1904. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1905. FL("dp_srng_setup failed for reo_dest_ringn"));
  1906. goto fail1;
  1907. }
  1908. soc->num_reo_dest_rings++;
  1909. }
  1910. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1911. RXDMA_REFILL_RING_SIZE)) {
  1912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1913. FL("dp_srng_setup failed rx refill ring"));
  1914. goto fail1;
  1915. }
  1916. if (dp_rxdma_ring_setup(soc, pdev)) {
  1917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1918. FL("RXDMA ring config failed"));
  1919. goto fail1;
  1920. }
  1921. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1922. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1923. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1924. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1925. goto fail1;
  1926. }
  1927. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1928. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1929. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1930. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1931. goto fail1;
  1932. }
  1933. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1934. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1935. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1937. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1938. goto fail1;
  1939. }
  1940. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1941. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1942. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1943. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1944. goto fail1;
  1945. }
  1946. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  1947. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[0], RXDMA_DST,
  1948. 0, pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1949. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1950. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  1951. goto fail1;
  1952. }
  1953. }
  1954. /* Setup second Rx refill buffer ring */
  1955. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2,
  1956. pdev->pdev_id, RXDMA_REFILL_RING_SIZE)) {
  1957. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1958. FL("dp_srng_setup failed second rx refill ring"));
  1959. goto fail1;
  1960. }
  1961. if (dp_ipa_ring_resource_setup(soc, pdev))
  1962. goto fail1;
  1963. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1964. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1965. FL("dp_ipa_uc_attach failed"));
  1966. goto fail1;
  1967. }
  1968. /* Rx specific init */
  1969. if (dp_rx_pdev_attach(pdev)) {
  1970. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1971. FL("dp_rx_pdev_attach failed"));
  1972. goto fail0;
  1973. }
  1974. DP_STATS_INIT(pdev);
  1975. /* Monitor filter init */
  1976. pdev->mon_filter_mode = MON_FILTER_ALL;
  1977. pdev->fp_mgmt_filter = FILTER_MGMT_ALL;
  1978. pdev->fp_ctrl_filter = FILTER_CTRL_ALL;
  1979. pdev->fp_data_filter = FILTER_DATA_ALL;
  1980. pdev->mo_mgmt_filter = FILTER_MGMT_ALL;
  1981. pdev->mo_ctrl_filter = FILTER_CTRL_ALL;
  1982. pdev->mo_data_filter = FILTER_DATA_ALL;
  1983. #ifndef CONFIG_WIN
  1984. /* MCL */
  1985. dp_local_peer_id_pool_init(pdev);
  1986. #endif
  1987. dp_dscp_tid_map_setup(pdev);
  1988. /* Rx monitor mode specific init */
  1989. if (dp_rx_pdev_mon_attach(pdev)) {
  1990. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1991. "dp_rx_pdev_attach failed\n");
  1992. goto fail1;
  1993. }
  1994. if (dp_wdi_event_attach(pdev)) {
  1995. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1996. "dp_wdi_evet_attach failed\n");
  1997. goto fail1;
  1998. }
  1999. /* set the reo destination during initialization */
  2000. pdev->reo_dest = pdev->pdev_id + 1;
  2001. return (struct cdp_pdev *)pdev;
  2002. fail1:
  2003. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2004. fail0:
  2005. return NULL;
  2006. }
  2007. /*
  2008. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2009. * @soc: data path SoC handle
  2010. * @pdev: Physical device handle
  2011. *
  2012. * Return: void
  2013. */
  2014. #ifdef QCA_HOST2FW_RXBUF_RING
  2015. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2016. struct dp_pdev *pdev)
  2017. {
  2018. int max_mac_rings =
  2019. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2020. int i;
  2021. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2022. max_mac_rings : MAX_RX_MAC_RINGS;
  2023. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2024. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2025. RXDMA_BUF, 1);
  2026. qdf_timer_free(&soc->mon_reap_timer);
  2027. }
  2028. #else
  2029. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2030. struct dp_pdev *pdev)
  2031. {
  2032. }
  2033. #endif
  2034. /*
  2035. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2036. * @pdev: device object
  2037. *
  2038. * Return: void
  2039. */
  2040. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2041. {
  2042. struct dp_neighbour_peer *peer = NULL;
  2043. struct dp_neighbour_peer *temp_peer = NULL;
  2044. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2045. neighbour_peer_list_elem, temp_peer) {
  2046. /* delete this peer from the list */
  2047. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2048. peer, neighbour_peer_list_elem);
  2049. qdf_mem_free(peer);
  2050. }
  2051. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2052. }
  2053. /*
  2054. * dp_pdev_detach_wifi3() - detach txrx pdev
  2055. * @txrx_pdev: Datapath PDEV handle
  2056. * @force: Force detach
  2057. *
  2058. */
  2059. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2060. {
  2061. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2062. struct dp_soc *soc = pdev->soc;
  2063. dp_wdi_event_detach(pdev);
  2064. dp_tx_pdev_detach(pdev);
  2065. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2066. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2067. TCL_DATA, pdev->pdev_id);
  2068. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2069. WBM2SW_RELEASE, pdev->pdev_id);
  2070. }
  2071. dp_pktlogmod_exit(pdev);
  2072. dp_rx_pdev_detach(pdev);
  2073. dp_rx_pdev_mon_detach(pdev);
  2074. dp_neighbour_peers_detach(pdev);
  2075. qdf_spinlock_destroy(&pdev->tx_mutex);
  2076. dp_ipa_uc_detach(soc, pdev);
  2077. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2);
  2078. /* Cleanup per PDEV REO rings if configured */
  2079. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2080. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2081. REO_DST, pdev->pdev_id);
  2082. }
  2083. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2084. dp_rxdma_ring_cleanup(soc, pdev);
  2085. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2086. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2087. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2088. RXDMA_MONITOR_STATUS, 0);
  2089. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2090. RXDMA_MONITOR_DESC, 0);
  2091. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  2092. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring[0], RXDMA_DST, 0);
  2093. } else {
  2094. int i;
  2095. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2096. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring[i],
  2097. RXDMA_DST, 0);
  2098. }
  2099. soc->pdev_list[pdev->pdev_id] = NULL;
  2100. soc->pdev_count--;
  2101. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2102. qdf_mem_free(pdev);
  2103. }
  2104. /*
  2105. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2106. * @soc: DP SOC handle
  2107. */
  2108. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2109. {
  2110. struct reo_desc_list_node *desc;
  2111. struct dp_rx_tid *rx_tid;
  2112. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2113. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2114. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2115. rx_tid = &desc->rx_tid;
  2116. qdf_mem_unmap_nbytes_single(soc->osdev,
  2117. rx_tid->hw_qdesc_paddr,
  2118. QDF_DMA_BIDIRECTIONAL,
  2119. rx_tid->hw_qdesc_alloc_size);
  2120. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2121. qdf_mem_free(desc);
  2122. }
  2123. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2124. qdf_list_destroy(&soc->reo_desc_freelist);
  2125. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2126. }
  2127. /*
  2128. * dp_soc_detach_wifi3() - Detach txrx SOC
  2129. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2130. */
  2131. static void dp_soc_detach_wifi3(void *txrx_soc)
  2132. {
  2133. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2134. int i;
  2135. qdf_atomic_set(&soc->cmn_init_done, 0);
  2136. qdf_flush_work(&soc->htt_stats.work);
  2137. qdf_disable_work(&soc->htt_stats.work);
  2138. /* Free pending htt stats messages */
  2139. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2140. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2141. if (soc->pdev_list[i])
  2142. dp_pdev_detach_wifi3(
  2143. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2144. }
  2145. dp_peer_find_detach(soc);
  2146. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2147. * SW descriptors
  2148. */
  2149. /* Free the ring memories */
  2150. /* Common rings */
  2151. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2152. dp_tx_soc_detach(soc);
  2153. /* Tx data rings */
  2154. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2155. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2156. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2157. TCL_DATA, i);
  2158. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2159. WBM2SW_RELEASE, i);
  2160. }
  2161. }
  2162. /* TCL command and status rings */
  2163. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2164. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2165. /* Rx data rings */
  2166. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2167. soc->num_reo_dest_rings =
  2168. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2169. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2170. /* TODO: Get number of rings and ring sizes
  2171. * from wlan_cfg
  2172. */
  2173. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2174. REO_DST, i);
  2175. }
  2176. }
  2177. /* REO reinjection ring */
  2178. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2179. /* Rx release ring */
  2180. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2181. /* Rx exception ring */
  2182. /* TODO: Better to store ring_type and ring_num in
  2183. * dp_srng during setup
  2184. */
  2185. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2186. /* REO command and status rings */
  2187. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2188. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2189. dp_hw_link_desc_pool_cleanup(soc);
  2190. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2191. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2192. htt_soc_detach(soc->htt_handle);
  2193. dp_reo_cmdlist_destroy(soc);
  2194. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2195. dp_reo_desc_freelist_destroy(soc);
  2196. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2197. dp_soc_wds_detach(soc);
  2198. qdf_spinlock_destroy(&soc->ast_lock);
  2199. qdf_mem_free(soc);
  2200. }
  2201. /*
  2202. * dp_rxdma_ring_config() - configure the RX DMA rings
  2203. *
  2204. * This function is used to configure the MAC rings.
  2205. * On MCL host provides buffers in Host2FW ring
  2206. * FW refills (copies) buffers to the ring and updates
  2207. * ring_idx in register
  2208. *
  2209. * @soc: data path SoC handle
  2210. *
  2211. * Return: void
  2212. */
  2213. #ifdef QCA_HOST2FW_RXBUF_RING
  2214. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2215. {
  2216. int i;
  2217. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2218. struct dp_pdev *pdev = soc->pdev_list[i];
  2219. if (pdev) {
  2220. int mac_id = 0;
  2221. int j;
  2222. bool dbs_enable = 0;
  2223. int max_mac_rings =
  2224. wlan_cfg_get_num_mac_rings
  2225. (pdev->wlan_cfg_ctx);
  2226. htt_srng_setup(soc->htt_handle, 0,
  2227. pdev->rx_refill_buf_ring.hal_srng,
  2228. RXDMA_BUF);
  2229. if (pdev->rx_refill_buf_ring2.hal_srng)
  2230. htt_srng_setup(soc->htt_handle, 0,
  2231. pdev->rx_refill_buf_ring2.hal_srng,
  2232. RXDMA_BUF);
  2233. if (soc->cdp_soc.ol_ops->
  2234. is_hw_dbs_2x2_capable) {
  2235. dbs_enable = soc->cdp_soc.ol_ops->
  2236. is_hw_dbs_2x2_capable(soc->psoc);
  2237. }
  2238. if (dbs_enable) {
  2239. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2240. QDF_TRACE_LEVEL_ERROR,
  2241. FL("DBS enabled max_mac_rings %d\n"),
  2242. max_mac_rings);
  2243. } else {
  2244. max_mac_rings = 1;
  2245. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2246. QDF_TRACE_LEVEL_ERROR,
  2247. FL("DBS disabled, max_mac_rings %d\n"),
  2248. max_mac_rings);
  2249. }
  2250. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2251. FL("pdev_id %d max_mac_rings %d\n"),
  2252. pdev->pdev_id, max_mac_rings);
  2253. for (j = 0; j < max_mac_rings; j++) {
  2254. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2255. QDF_TRACE_LEVEL_ERROR,
  2256. FL("mac_id %d\n"), mac_id);
  2257. htt_srng_setup(soc->htt_handle, mac_id,
  2258. pdev->rx_mac_buf_ring[j]
  2259. .hal_srng,
  2260. RXDMA_BUF);
  2261. htt_srng_setup(soc->htt_handle, mac_id,
  2262. pdev->rxdma_err_dst_ring[j]
  2263. .hal_srng,
  2264. RXDMA_DST);
  2265. mac_id++;
  2266. }
  2267. /* Configure monitor mode rings */
  2268. htt_srng_setup(soc->htt_handle, i,
  2269. pdev->rxdma_mon_buf_ring.hal_srng,
  2270. RXDMA_MONITOR_BUF);
  2271. htt_srng_setup(soc->htt_handle, i,
  2272. pdev->rxdma_mon_dst_ring.hal_srng,
  2273. RXDMA_MONITOR_DST);
  2274. htt_srng_setup(soc->htt_handle, i,
  2275. pdev->rxdma_mon_status_ring.hal_srng,
  2276. RXDMA_MONITOR_STATUS);
  2277. htt_srng_setup(soc->htt_handle, i,
  2278. pdev->rxdma_mon_desc_ring.hal_srng,
  2279. RXDMA_MONITOR_DESC);
  2280. }
  2281. }
  2282. /*
  2283. * Timer to reap rxdma status rings.
  2284. * Needed until we enable ppdu end interrupts
  2285. */
  2286. qdf_timer_init(soc->osdev, &soc->mon_reap_timer,
  2287. dp_service_mon_rings, (void *)soc,
  2288. QDF_TIMER_TYPE_WAKE_APPS);
  2289. soc->reap_timer_init = 1;
  2290. }
  2291. #else
  2292. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2293. {
  2294. int i;
  2295. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2296. struct dp_pdev *pdev = soc->pdev_list[i];
  2297. if (pdev) {
  2298. int ring_idx = dp_get_ring_id_for_mac_id(soc, i);
  2299. htt_srng_setup(soc->htt_handle, i,
  2300. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2301. htt_srng_setup(soc->htt_handle, i,
  2302. pdev->rxdma_mon_buf_ring.hal_srng,
  2303. RXDMA_MONITOR_BUF);
  2304. htt_srng_setup(soc->htt_handle, i,
  2305. pdev->rxdma_mon_dst_ring.hal_srng,
  2306. RXDMA_MONITOR_DST);
  2307. htt_srng_setup(soc->htt_handle, i,
  2308. pdev->rxdma_mon_status_ring.hal_srng,
  2309. RXDMA_MONITOR_STATUS);
  2310. htt_srng_setup(soc->htt_handle, i,
  2311. pdev->rxdma_mon_desc_ring.hal_srng,
  2312. RXDMA_MONITOR_DESC);
  2313. htt_srng_setup(soc->htt_handle, i,
  2314. pdev->rxdma_err_dst_ring[ring_idx].hal_srng,
  2315. RXDMA_DST);
  2316. }
  2317. }
  2318. }
  2319. #endif
  2320. /*
  2321. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2322. * @txrx_soc: Datapath SOC handle
  2323. */
  2324. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2325. {
  2326. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2327. htt_soc_attach_target(soc->htt_handle);
  2328. dp_rxdma_ring_config(soc);
  2329. DP_STATS_INIT(soc);
  2330. /* initialize work queue for stats processing */
  2331. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2332. return 0;
  2333. }
  2334. /*
  2335. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2336. * @txrx_soc: Datapath SOC handle
  2337. */
  2338. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2339. {
  2340. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2341. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2342. }
  2343. /*
  2344. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2345. * @txrx_soc: Datapath SOC handle
  2346. * @nss_cfg: nss config
  2347. */
  2348. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2349. {
  2350. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2351. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2352. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2353. FL("nss-wifi<0> nss config is enabled"));
  2354. }
  2355. /*
  2356. * dp_vdev_attach_wifi3() - attach txrx vdev
  2357. * @txrx_pdev: Datapath PDEV handle
  2358. * @vdev_mac_addr: MAC address of the virtual interface
  2359. * @vdev_id: VDEV Id
  2360. * @wlan_op_mode: VDEV operating mode
  2361. *
  2362. * Return: DP VDEV handle on success, NULL on failure
  2363. */
  2364. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2365. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2366. {
  2367. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2368. struct dp_soc *soc = pdev->soc;
  2369. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2370. int tx_ring_size;
  2371. if (!vdev) {
  2372. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2373. FL("DP VDEV memory allocation failed"));
  2374. goto fail0;
  2375. }
  2376. vdev->pdev = pdev;
  2377. vdev->vdev_id = vdev_id;
  2378. vdev->opmode = op_mode;
  2379. vdev->osdev = soc->osdev;
  2380. vdev->osif_rx = NULL;
  2381. vdev->osif_rsim_rx_decap = NULL;
  2382. vdev->osif_get_key = NULL;
  2383. vdev->osif_rx_mon = NULL;
  2384. vdev->osif_tx_free_ext = NULL;
  2385. vdev->osif_vdev = NULL;
  2386. vdev->delete.pending = 0;
  2387. vdev->safemode = 0;
  2388. vdev->drop_unenc = 1;
  2389. vdev->sec_type = cdp_sec_type_none;
  2390. #ifdef notyet
  2391. vdev->filters_num = 0;
  2392. #endif
  2393. qdf_mem_copy(
  2394. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2395. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2396. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2397. vdev->dscp_tid_map_id = 0;
  2398. vdev->mcast_enhancement_en = 0;
  2399. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2400. /* TODO: Initialize default HTT meta data that will be used in
  2401. * TCL descriptors for packets transmitted from this VDEV
  2402. */
  2403. TAILQ_INIT(&vdev->peer_list);
  2404. /* add this vdev into the pdev's list */
  2405. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2406. pdev->vdev_count++;
  2407. dp_tx_vdev_attach(vdev);
  2408. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2409. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2410. goto fail1;
  2411. if ((soc->intr_mode == DP_INTR_POLL) &&
  2412. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2413. if (pdev->vdev_count == 1)
  2414. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2415. }
  2416. dp_lro_hash_setup(soc);
  2417. /* LRO */
  2418. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2419. wlan_op_mode_sta == vdev->opmode)
  2420. vdev->lro_enable = true;
  2421. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2422. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2424. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2425. DP_STATS_INIT(vdev);
  2426. return (struct cdp_vdev *)vdev;
  2427. fail1:
  2428. dp_tx_vdev_detach(vdev);
  2429. qdf_mem_free(vdev);
  2430. fail0:
  2431. return NULL;
  2432. }
  2433. /**
  2434. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2435. * @vdev: Datapath VDEV handle
  2436. * @osif_vdev: OSIF vdev handle
  2437. * @txrx_ops: Tx and Rx operations
  2438. *
  2439. * Return: DP VDEV handle on success, NULL on failure
  2440. */
  2441. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2442. void *osif_vdev,
  2443. struct ol_txrx_ops *txrx_ops)
  2444. {
  2445. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2446. vdev->osif_vdev = osif_vdev;
  2447. vdev->osif_rx = txrx_ops->rx.rx;
  2448. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2449. vdev->osif_get_key = txrx_ops->get_key;
  2450. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2451. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2452. #ifdef notyet
  2453. #if ATH_SUPPORT_WAPI
  2454. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2455. #endif
  2456. #endif
  2457. #ifdef UMAC_SUPPORT_PROXY_ARP
  2458. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2459. #endif
  2460. vdev->me_convert = txrx_ops->me_convert;
  2461. /* TODO: Enable the following once Tx code is integrated */
  2462. txrx_ops->tx.tx = dp_tx_send;
  2463. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2464. "DP Vdev Register success");
  2465. }
  2466. /*
  2467. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2468. * @txrx_vdev: Datapath VDEV handle
  2469. * @callback: Callback OL_IF on completion of detach
  2470. * @cb_context: Callback context
  2471. *
  2472. */
  2473. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2474. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2475. {
  2476. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2477. struct dp_pdev *pdev = vdev->pdev;
  2478. struct dp_soc *soc = pdev->soc;
  2479. /* preconditions */
  2480. qdf_assert(vdev);
  2481. /* remove the vdev from its parent pdev's list */
  2482. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2483. /*
  2484. * Use peer_ref_mutex while accessing peer_list, in case
  2485. * a peer is in the process of being removed from the list.
  2486. */
  2487. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2488. /* check that the vdev has no peers allocated */
  2489. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2490. /* debug print - will be removed later */
  2491. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2492. FL("not deleting vdev object %pK (%pM)"
  2493. "until deletion finishes for all its peers"),
  2494. vdev, vdev->mac_addr.raw);
  2495. /* indicate that the vdev needs to be deleted */
  2496. vdev->delete.pending = 1;
  2497. vdev->delete.callback = callback;
  2498. vdev->delete.context = cb_context;
  2499. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2500. return;
  2501. }
  2502. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2503. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2504. vdev->vdev_id);
  2505. dp_tx_vdev_detach(vdev);
  2506. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2507. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2508. qdf_mem_free(vdev);
  2509. if (callback)
  2510. callback(cb_context);
  2511. }
  2512. /*
  2513. * dp_peer_create_wifi3() - attach txrx peer
  2514. * @txrx_vdev: Datapath VDEV handle
  2515. * @peer_mac_addr: Peer MAC address
  2516. *
  2517. * Return: DP peeer handle on success, NULL on failure
  2518. */
  2519. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2520. uint8_t *peer_mac_addr)
  2521. {
  2522. struct dp_peer *peer;
  2523. int i;
  2524. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2525. struct dp_pdev *pdev;
  2526. struct dp_soc *soc;
  2527. /* preconditions */
  2528. qdf_assert(vdev);
  2529. qdf_assert(peer_mac_addr);
  2530. pdev = vdev->pdev;
  2531. soc = pdev->soc;
  2532. #ifdef notyet
  2533. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2534. soc->mempool_ol_ath_peer);
  2535. #else
  2536. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2537. #endif
  2538. if (!peer)
  2539. return NULL; /* failure */
  2540. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2541. TAILQ_INIT(&peer->ast_entry_list);
  2542. /* store provided params */
  2543. peer->vdev = vdev;
  2544. dp_peer_add_ast(soc, peer, peer_mac_addr, dp_ast_type_static);
  2545. qdf_spinlock_create(&peer->peer_info_lock);
  2546. qdf_mem_copy(
  2547. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2548. /* TODO: See of rx_opt_proc is really required */
  2549. peer->rx_opt_proc = soc->rx_opt_proc;
  2550. /* initialize the peer_id */
  2551. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2552. peer->peer_ids[i] = HTT_INVALID_PEER;
  2553. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2554. qdf_atomic_init(&peer->ref_cnt);
  2555. /* keep one reference for attach */
  2556. qdf_atomic_inc(&peer->ref_cnt);
  2557. /* add this peer into the vdev's list */
  2558. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2559. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2560. /* TODO: See if hash based search is required */
  2561. dp_peer_find_hash_add(soc, peer);
  2562. /* Initialize the peer state */
  2563. peer->state = OL_TXRX_PEER_STATE_DISC;
  2564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2565. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2566. vdev, peer, peer->mac_addr.raw,
  2567. qdf_atomic_read(&peer->ref_cnt));
  2568. /*
  2569. * For every peer MAp message search and set if bss_peer
  2570. */
  2571. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2572. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2573. "vdev bss_peer!!!!");
  2574. peer->bss_peer = 1;
  2575. vdev->vap_bss_peer = peer;
  2576. }
  2577. #ifndef CONFIG_WIN
  2578. dp_local_peer_id_alloc(pdev, peer);
  2579. #endif
  2580. DP_STATS_INIT(peer);
  2581. return (void *)peer;
  2582. }
  2583. /*
  2584. * dp_peer_setup_wifi3() - initialize the peer
  2585. * @vdev_hdl: virtual device object
  2586. * @peer: Peer object
  2587. *
  2588. * Return: void
  2589. */
  2590. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2591. {
  2592. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2593. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2594. struct dp_pdev *pdev;
  2595. struct dp_soc *soc;
  2596. bool hash_based = 0;
  2597. enum cdp_host_reo_dest_ring reo_dest;
  2598. /* preconditions */
  2599. qdf_assert(vdev);
  2600. qdf_assert(peer);
  2601. pdev = vdev->pdev;
  2602. soc = pdev->soc;
  2603. dp_peer_rx_init(pdev, peer);
  2604. peer->last_assoc_rcvd = 0;
  2605. peer->last_disassoc_rcvd = 0;
  2606. peer->last_deauth_rcvd = 0;
  2607. /*
  2608. * hash based steering is disabled for Radios which are offloaded
  2609. * to NSS
  2610. */
  2611. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2612. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2614. FL("hash based steering for pdev: %d is %d\n"),
  2615. pdev->pdev_id, hash_based);
  2616. /*
  2617. * Below line of code will ensure the proper reo_dest ring is choosen
  2618. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2619. */
  2620. reo_dest = pdev->reo_dest;
  2621. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2622. /* TODO: Check the destination ring number to be passed to FW */
  2623. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2624. pdev->osif_pdev, peer->mac_addr.raw,
  2625. peer->vdev->vdev_id, hash_based, reo_dest);
  2626. }
  2627. return;
  2628. }
  2629. /*
  2630. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2631. * @vdev_handle: virtual device object
  2632. * @htt_pkt_type: type of pkt
  2633. *
  2634. * Return: void
  2635. */
  2636. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2637. enum htt_cmn_pkt_type val)
  2638. {
  2639. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2640. vdev->tx_encap_type = val;
  2641. }
  2642. /*
  2643. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2644. * @vdev_handle: virtual device object
  2645. * @htt_pkt_type: type of pkt
  2646. *
  2647. * Return: void
  2648. */
  2649. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2650. enum htt_cmn_pkt_type val)
  2651. {
  2652. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2653. vdev->rx_decap_type = val;
  2654. }
  2655. /*
  2656. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2657. * @pdev_handle: physical device object
  2658. * @val: reo destination ring index (1 - 4)
  2659. *
  2660. * Return: void
  2661. */
  2662. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2663. enum cdp_host_reo_dest_ring val)
  2664. {
  2665. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2666. if (pdev)
  2667. pdev->reo_dest = val;
  2668. }
  2669. /*
  2670. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2671. * @pdev_handle: physical device object
  2672. *
  2673. * Return: reo destination ring index
  2674. */
  2675. static enum cdp_host_reo_dest_ring
  2676. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2677. {
  2678. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2679. if (pdev)
  2680. return pdev->reo_dest;
  2681. else
  2682. return cdp_host_reo_dest_ring_unknown;
  2683. }
  2684. #ifdef QCA_SUPPORT_SON
  2685. static void dp_son_peer_authorize(struct dp_peer *peer)
  2686. {
  2687. struct dp_soc *soc;
  2688. soc = peer->vdev->pdev->soc;
  2689. peer->peer_bs_inact_flag = 0;
  2690. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2691. return;
  2692. }
  2693. #else
  2694. static void dp_son_peer_authorize(struct dp_peer *peer)
  2695. {
  2696. return;
  2697. }
  2698. #endif
  2699. /*
  2700. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2701. * @pdev_handle: device object
  2702. * @val: value to be set
  2703. *
  2704. * Return: void
  2705. */
  2706. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2707. uint32_t val)
  2708. {
  2709. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2710. /* Enable/Disable smart mesh filtering. This flag will be checked
  2711. * during rx processing to check if packets are from NAC clients.
  2712. */
  2713. pdev->filter_neighbour_peers = val;
  2714. return 0;
  2715. }
  2716. /*
  2717. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2718. * address for smart mesh filtering
  2719. * @pdev_handle: device object
  2720. * @cmd: Add/Del command
  2721. * @macaddr: nac client mac address
  2722. *
  2723. * Return: void
  2724. */
  2725. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2726. uint32_t cmd, uint8_t *macaddr)
  2727. {
  2728. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2729. struct dp_neighbour_peer *peer = NULL;
  2730. if (!macaddr)
  2731. goto fail0;
  2732. /* Store address of NAC (neighbour peer) which will be checked
  2733. * against TA of received packets.
  2734. */
  2735. if (cmd == DP_NAC_PARAM_ADD) {
  2736. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2737. sizeof(*peer));
  2738. if (!peer) {
  2739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2740. FL("DP neighbour peer node memory allocation failed"));
  2741. goto fail0;
  2742. }
  2743. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2744. macaddr, DP_MAC_ADDR_LEN);
  2745. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2746. /* add this neighbour peer into the list */
  2747. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2748. neighbour_peer_list_elem);
  2749. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2750. return 1;
  2751. } else if (cmd == DP_NAC_PARAM_DEL) {
  2752. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2753. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2754. neighbour_peer_list_elem) {
  2755. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2756. macaddr, DP_MAC_ADDR_LEN)) {
  2757. /* delete this peer from the list */
  2758. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2759. peer, neighbour_peer_list_elem);
  2760. qdf_mem_free(peer);
  2761. break;
  2762. }
  2763. }
  2764. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2765. return 1;
  2766. }
  2767. fail0:
  2768. return 0;
  2769. }
  2770. /*
  2771. * dp_get_sec_type() - Get the security type
  2772. * @peer: Datapath peer handle
  2773. * @sec_idx: Security id (mcast, ucast)
  2774. *
  2775. * return sec_type: Security type
  2776. */
  2777. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2778. {
  2779. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2780. return dpeer->security[sec_idx].sec_type;
  2781. }
  2782. /*
  2783. * dp_peer_authorize() - authorize txrx peer
  2784. * @peer_handle: Datapath peer handle
  2785. * @authorize
  2786. *
  2787. */
  2788. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2789. {
  2790. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2791. struct dp_soc *soc;
  2792. if (peer != NULL) {
  2793. soc = peer->vdev->pdev->soc;
  2794. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2795. dp_son_peer_authorize(peer);
  2796. peer->authorize = authorize ? 1 : 0;
  2797. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2798. }
  2799. }
  2800. /*
  2801. * dp_peer_unref_delete() - unref and delete peer
  2802. * @peer_handle: Datapath peer handle
  2803. *
  2804. */
  2805. void dp_peer_unref_delete(void *peer_handle)
  2806. {
  2807. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2808. struct dp_vdev *vdev = peer->vdev;
  2809. struct dp_pdev *pdev = vdev->pdev;
  2810. struct dp_soc *soc = pdev->soc;
  2811. struct dp_peer *tmppeer;
  2812. int found = 0;
  2813. uint16_t peer_id;
  2814. /*
  2815. * Hold the lock all the way from checking if the peer ref count
  2816. * is zero until the peer references are removed from the hash
  2817. * table and vdev list (if the peer ref count is zero).
  2818. * This protects against a new HL tx operation starting to use the
  2819. * peer object just after this function concludes it's done being used.
  2820. * Furthermore, the lock needs to be held while checking whether the
  2821. * vdev's list of peers is empty, to make sure that list is not modified
  2822. * concurrently with the empty check.
  2823. */
  2824. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2825. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2826. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2827. peer, qdf_atomic_read(&peer->ref_cnt));
  2828. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2829. peer_id = peer->peer_ids[0];
  2830. /*
  2831. * Make sure that the reference to the peer in
  2832. * peer object map is removed
  2833. */
  2834. if (peer_id != HTT_INVALID_PEER)
  2835. soc->peer_id_to_obj_map[peer_id] = NULL;
  2836. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2837. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2838. /* remove the reference to the peer from the hash table */
  2839. dp_peer_find_hash_remove(soc, peer);
  2840. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2841. if (tmppeer == peer) {
  2842. found = 1;
  2843. break;
  2844. }
  2845. }
  2846. if (found) {
  2847. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2848. peer_list_elem);
  2849. } else {
  2850. /*Ignoring the remove operation as peer not found*/
  2851. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2852. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2853. peer, vdev, &peer->vdev->peer_list);
  2854. }
  2855. /* cleanup the peer data */
  2856. dp_peer_cleanup(vdev, peer);
  2857. /* check whether the parent vdev has no peers left */
  2858. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2859. /*
  2860. * Now that there are no references to the peer, we can
  2861. * release the peer reference lock.
  2862. */
  2863. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2864. /*
  2865. * Check if the parent vdev was waiting for its peers
  2866. * to be deleted, in order for it to be deleted too.
  2867. */
  2868. if (vdev->delete.pending) {
  2869. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2870. vdev->delete.callback;
  2871. void *vdev_delete_context =
  2872. vdev->delete.context;
  2873. QDF_TRACE(QDF_MODULE_ID_DP,
  2874. QDF_TRACE_LEVEL_INFO_HIGH,
  2875. FL("deleting vdev object %pK (%pM)"
  2876. " - its last peer is done"),
  2877. vdev, vdev->mac_addr.raw);
  2878. /* all peers are gone, go ahead and delete it */
  2879. qdf_mem_free(vdev);
  2880. if (vdev_delete_cb)
  2881. vdev_delete_cb(vdev_delete_context);
  2882. }
  2883. } else {
  2884. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2885. }
  2886. #ifdef notyet
  2887. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2888. #else
  2889. qdf_mem_free(peer);
  2890. #endif
  2891. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2892. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2893. vdev->vdev_id, peer->mac_addr.raw);
  2894. }
  2895. } else {
  2896. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2897. }
  2898. }
  2899. /*
  2900. * dp_peer_detach_wifi3() – Detach txrx peer
  2901. * @peer_handle: Datapath peer handle
  2902. * @bitmap: bitmap indicating special handling of request.
  2903. *
  2904. */
  2905. static void dp_peer_delete_wifi3(void *peer_handle, uint32_t bitmap)
  2906. {
  2907. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2908. /* redirect the peer's rx delivery function to point to a
  2909. * discard func
  2910. */
  2911. peer->rx_opt_proc = dp_rx_discard;
  2912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2913. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2914. #ifndef CONFIG_WIN
  2915. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2916. #endif
  2917. qdf_spinlock_destroy(&peer->peer_info_lock);
  2918. /*
  2919. * Remove the reference added during peer_attach.
  2920. * The peer will still be left allocated until the
  2921. * PEER_UNMAP message arrives to remove the other
  2922. * reference, added by the PEER_MAP message.
  2923. */
  2924. dp_peer_unref_delete(peer_handle);
  2925. }
  2926. /*
  2927. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2928. * @peer_handle: Datapath peer handle
  2929. *
  2930. */
  2931. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2932. {
  2933. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2934. return vdev->mac_addr.raw;
  2935. }
  2936. /*
  2937. * dp_vdev_set_wds() - Enable per packet stats
  2938. * @vdev_handle: DP VDEV handle
  2939. * @val: value
  2940. *
  2941. * Return: none
  2942. */
  2943. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2944. {
  2945. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2946. vdev->wds_enabled = val;
  2947. return 0;
  2948. }
  2949. /*
  2950. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2951. * @peer_handle: Datapath peer handle
  2952. *
  2953. */
  2954. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2955. uint8_t vdev_id)
  2956. {
  2957. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2958. struct dp_vdev *vdev = NULL;
  2959. if (qdf_unlikely(!pdev))
  2960. return NULL;
  2961. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2962. if (vdev->vdev_id == vdev_id)
  2963. break;
  2964. }
  2965. return (struct cdp_vdev *)vdev;
  2966. }
  2967. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2968. {
  2969. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2970. return vdev->opmode;
  2971. }
  2972. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2973. {
  2974. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2975. struct dp_pdev *pdev = vdev->pdev;
  2976. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2977. }
  2978. /**
  2979. * dp_reset_monitor_mode() - Disable monitor mode
  2980. * @pdev_handle: Datapath PDEV handle
  2981. *
  2982. * Return: 0 on success, not 0 on failure
  2983. */
  2984. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  2985. {
  2986. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2987. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2988. struct dp_soc *soc;
  2989. uint8_t pdev_id;
  2990. pdev_id = pdev->pdev_id;
  2991. soc = pdev->soc;
  2992. pdev->monitor_vdev = NULL;
  2993. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  2994. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2995. pdev->rxdma_mon_buf_ring.hal_srng,
  2996. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2997. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2998. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2999. RX_BUFFER_SIZE, &htt_tlv_filter);
  3000. return 0;
  3001. }
  3002. /**
  3003. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3004. * @vdev_handle: Datapath VDEV handle
  3005. * @smart_monitor: Flag to denote if its smart monitor mode
  3006. *
  3007. * Return: 0 on success, not 0 on failure
  3008. */
  3009. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3010. uint8_t smart_monitor)
  3011. {
  3012. /* Many monitor VAPs can exists in a system but only one can be up at
  3013. * anytime
  3014. */
  3015. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3016. struct dp_pdev *pdev;
  3017. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3018. struct dp_soc *soc;
  3019. uint8_t pdev_id;
  3020. qdf_assert(vdev);
  3021. pdev = vdev->pdev;
  3022. pdev_id = pdev->pdev_id;
  3023. soc = pdev->soc;
  3024. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3025. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3026. pdev, pdev_id, soc, vdev);
  3027. /*Check if current pdev's monitor_vdev exists */
  3028. if (pdev->monitor_vdev) {
  3029. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3030. "vdev=%pK\n", vdev);
  3031. qdf_assert(vdev);
  3032. }
  3033. pdev->monitor_vdev = vdev;
  3034. /* If smart monitor mode, do not configure monitor ring */
  3035. if (smart_monitor)
  3036. return QDF_STATUS_SUCCESS;
  3037. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_HIGH,
  3038. "MODE[%x] FP[%02x|%02x|%02x] MO[%02x|%02x|%02x]\n",
  3039. pdev->mon_filter_mode, pdev->fp_mgmt_filter,
  3040. pdev->fp_ctrl_filter, pdev->fp_data_filter,
  3041. pdev->mo_mgmt_filter, pdev->mo_ctrl_filter,
  3042. pdev->mo_data_filter);
  3043. htt_tlv_filter.mpdu_start = 1;
  3044. htt_tlv_filter.msdu_start = 1;
  3045. htt_tlv_filter.packet = 1;
  3046. htt_tlv_filter.msdu_end = 1;
  3047. htt_tlv_filter.mpdu_end = 1;
  3048. htt_tlv_filter.packet_header = 1;
  3049. htt_tlv_filter.attention = 1;
  3050. htt_tlv_filter.ppdu_start = 0;
  3051. htt_tlv_filter.ppdu_end = 0;
  3052. htt_tlv_filter.ppdu_end_user_stats = 0;
  3053. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3054. htt_tlv_filter.ppdu_end_status_done = 0;
  3055. htt_tlv_filter.header_per_msdu = 1;
  3056. htt_tlv_filter.enable_fp =
  3057. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3058. htt_tlv_filter.enable_md = 0;
  3059. htt_tlv_filter.enable_mo =
  3060. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3061. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3062. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3063. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3064. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3065. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3066. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3067. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3068. pdev->rxdma_mon_buf_ring.hal_srng,
  3069. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3070. htt_tlv_filter.mpdu_start = 1;
  3071. htt_tlv_filter.msdu_start = 1;
  3072. htt_tlv_filter.packet = 0;
  3073. htt_tlv_filter.msdu_end = 1;
  3074. htt_tlv_filter.mpdu_end = 1;
  3075. htt_tlv_filter.packet_header = 1;
  3076. htt_tlv_filter.attention = 1;
  3077. htt_tlv_filter.ppdu_start = 1;
  3078. htt_tlv_filter.ppdu_end = 1;
  3079. htt_tlv_filter.ppdu_end_user_stats = 1;
  3080. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3081. htt_tlv_filter.ppdu_end_status_done = 1;
  3082. htt_tlv_filter.header_per_msdu = 0;
  3083. htt_tlv_filter.enable_fp =
  3084. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3085. htt_tlv_filter.enable_md = 0;
  3086. htt_tlv_filter.enable_mo =
  3087. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3088. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3089. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3090. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3091. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3092. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3093. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3094. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3095. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3096. RX_BUFFER_SIZE, &htt_tlv_filter);
  3097. return QDF_STATUS_SUCCESS;
  3098. }
  3099. /**
  3100. * dp_pdev_set_advance_monitor_filter() - Set DP PDEV monitor filter
  3101. * @pdev_handle: Datapath PDEV handle
  3102. * @filter_val: Flag to select Filter for monitor mode
  3103. * Return: 0 on success, not 0 on failure
  3104. */
  3105. static int dp_pdev_set_advance_monitor_filter(struct cdp_pdev *pdev_handle,
  3106. struct cdp_monitor_filter *filter_val)
  3107. {
  3108. /* Many monitor VAPs can exists in a system but only one can be up at
  3109. * anytime
  3110. */
  3111. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3112. struct dp_vdev *vdev = pdev->monitor_vdev;
  3113. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3114. struct dp_soc *soc;
  3115. uint8_t pdev_id;
  3116. pdev_id = pdev->pdev_id;
  3117. soc = pdev->soc;
  3118. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3119. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3120. pdev, pdev_id, soc, vdev);
  3121. /*Check if current pdev's monitor_vdev exists */
  3122. if (!pdev->monitor_vdev) {
  3123. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3124. "vdev=%pK\n", vdev);
  3125. qdf_assert(vdev);
  3126. }
  3127. /* update filter mode, type in pdev structure */
  3128. pdev->mon_filter_mode = filter_val->mode;
  3129. pdev->fp_mgmt_filter = filter_val->fp_mgmt;
  3130. pdev->fp_ctrl_filter = filter_val->fp_ctrl;
  3131. pdev->fp_data_filter = filter_val->fp_data;
  3132. pdev->mo_mgmt_filter = filter_val->mo_mgmt;
  3133. pdev->mo_ctrl_filter = filter_val->mo_ctrl;
  3134. pdev->mo_data_filter = filter_val->mo_data;
  3135. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_HIGH,
  3136. "MODE[%x] FP[%02x|%02x|%02x] MO[%02x|%02x|%02x]\n",
  3137. pdev->mon_filter_mode, pdev->fp_mgmt_filter,
  3138. pdev->fp_ctrl_filter, pdev->fp_data_filter,
  3139. pdev->mo_mgmt_filter, pdev->mo_ctrl_filter,
  3140. pdev->mo_data_filter);
  3141. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3142. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3143. pdev->rxdma_mon_buf_ring.hal_srng,
  3144. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3145. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3146. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3147. RX_BUFFER_SIZE, &htt_tlv_filter);
  3148. htt_tlv_filter.mpdu_start = 1;
  3149. htt_tlv_filter.msdu_start = 1;
  3150. htt_tlv_filter.packet = 1;
  3151. htt_tlv_filter.msdu_end = 1;
  3152. htt_tlv_filter.mpdu_end = 1;
  3153. htt_tlv_filter.packet_header = 1;
  3154. htt_tlv_filter.attention = 1;
  3155. htt_tlv_filter.ppdu_start = 0;
  3156. htt_tlv_filter.ppdu_end = 0;
  3157. htt_tlv_filter.ppdu_end_user_stats = 0;
  3158. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3159. htt_tlv_filter.ppdu_end_status_done = 0;
  3160. htt_tlv_filter.header_per_msdu = 1;
  3161. htt_tlv_filter.enable_fp =
  3162. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3163. htt_tlv_filter.enable_md = 0;
  3164. htt_tlv_filter.enable_mo =
  3165. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3166. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3167. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3168. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3169. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3170. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3171. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3172. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3173. pdev->rxdma_mon_buf_ring.hal_srng, RXDMA_MONITOR_BUF,
  3174. RX_BUFFER_SIZE, &htt_tlv_filter);
  3175. htt_tlv_filter.mpdu_start = 1;
  3176. htt_tlv_filter.msdu_start = 1;
  3177. htt_tlv_filter.packet = 0;
  3178. htt_tlv_filter.msdu_end = 1;
  3179. htt_tlv_filter.mpdu_end = 1;
  3180. htt_tlv_filter.packet_header = 1;
  3181. htt_tlv_filter.attention = 1;
  3182. htt_tlv_filter.ppdu_start = 1;
  3183. htt_tlv_filter.ppdu_end = 1;
  3184. htt_tlv_filter.ppdu_end_user_stats = 1;
  3185. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3186. htt_tlv_filter.ppdu_end_status_done = 1;
  3187. htt_tlv_filter.header_per_msdu = 0;
  3188. htt_tlv_filter.enable_fp =
  3189. (pdev->mon_filter_mode & MON_FILTER_PASS) ? 1 : 0;
  3190. htt_tlv_filter.enable_md = 0;
  3191. htt_tlv_filter.enable_mo =
  3192. (pdev->mon_filter_mode & MON_FILTER_OTHER) ? 1 : 0;
  3193. htt_tlv_filter.fp_mgmt_filter = pdev->fp_mgmt_filter;
  3194. htt_tlv_filter.fp_ctrl_filter = pdev->fp_ctrl_filter;
  3195. htt_tlv_filter.fp_data_filter = pdev->fp_data_filter;
  3196. htt_tlv_filter.mo_mgmt_filter = pdev->mo_mgmt_filter;
  3197. htt_tlv_filter.mo_ctrl_filter = pdev->mo_ctrl_filter;
  3198. htt_tlv_filter.mo_data_filter = pdev->mo_data_filter;
  3199. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3200. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3201. RX_BUFFER_SIZE, &htt_tlv_filter);
  3202. return QDF_STATUS_SUCCESS;
  3203. }
  3204. #ifdef MESH_MODE_SUPPORT
  3205. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3206. {
  3207. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3209. FL("val %d"), val);
  3210. vdev->mesh_vdev = val;
  3211. }
  3212. /*
  3213. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3214. * @vdev_hdl: virtual device object
  3215. * @val: value to be set
  3216. *
  3217. * Return: void
  3218. */
  3219. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3220. {
  3221. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3223. FL("val %d"), val);
  3224. vdev->mesh_rx_filter = val;
  3225. }
  3226. #endif
  3227. /*
  3228. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  3229. * Current scope is bar recieved count
  3230. *
  3231. * @pdev_handle: DP_PDEV handle
  3232. *
  3233. * Return: void
  3234. */
  3235. #define STATS_PROC_TIMEOUT (HZ/10)
  3236. static void
  3237. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  3238. {
  3239. struct dp_vdev *vdev;
  3240. struct dp_peer *peer;
  3241. uint32_t waitcnt;
  3242. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3243. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3244. if (!peer) {
  3245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3246. FL("DP Invalid Peer refernce"));
  3247. return;
  3248. }
  3249. waitcnt = 0;
  3250. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  3251. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  3252. && waitcnt < 10) {
  3253. schedule_timeout_interruptible(
  3254. STATS_PROC_TIMEOUT);
  3255. waitcnt++;
  3256. }
  3257. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3258. }
  3259. }
  3260. }
  3261. /**
  3262. * dp_rx_bar_stats_cb(): BAR received stats callback
  3263. * @soc: SOC handle
  3264. * @cb_ctxt: Call back context
  3265. * @reo_status: Reo status
  3266. *
  3267. * return: void
  3268. */
  3269. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3270. union hal_reo_status *reo_status)
  3271. {
  3272. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3273. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3274. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3275. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3276. queue_status->header.status);
  3277. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3278. return;
  3279. }
  3280. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3281. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3282. }
  3283. /**
  3284. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3285. * @vdev: DP VDEV handle
  3286. *
  3287. * return: void
  3288. */
  3289. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3290. {
  3291. struct dp_peer *peer = NULL;
  3292. struct dp_soc *soc = vdev->pdev->soc;
  3293. int i;
  3294. uint8_t pream_type;
  3295. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3296. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3297. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3298. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3299. for (i = 0; i < MAX_MCS; i++) {
  3300. DP_STATS_AGGR(vdev, peer,
  3301. tx.pkt_type[pream_type].mcs_count[i]);
  3302. DP_STATS_AGGR(vdev, peer,
  3303. rx.pkt_type[pream_type].mcs_count[i]);
  3304. }
  3305. }
  3306. for (i = 0; i < MAX_BW; i++) {
  3307. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3308. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3309. }
  3310. for (i = 0; i < SS_COUNT; i++)
  3311. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3312. for (i = 0; i < WME_AC_MAX; i++) {
  3313. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3314. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3315. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3316. }
  3317. for (i = 0; i < MAX_GI; i++) {
  3318. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3319. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3320. }
  3321. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3322. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3323. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3324. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3325. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3326. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3327. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3328. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3329. DP_STATS_AGGR(vdev, peer, tx.retries);
  3330. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3331. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3332. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3333. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3334. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3335. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3336. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3337. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3338. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3339. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3340. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3341. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3342. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3343. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3344. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3345. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3346. peer->stats.rx.multicast.num;
  3347. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3348. peer->stats.rx.multicast.bytes;
  3349. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3350. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3351. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3352. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3353. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3354. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3355. vdev->stats.tx.last_ack_rssi =
  3356. peer->stats.tx.last_ack_rssi;
  3357. }
  3358. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3359. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3360. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3361. }
  3362. /**
  3363. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3364. * @pdev: DP PDEV handle
  3365. *
  3366. * return: void
  3367. */
  3368. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3369. {
  3370. struct dp_vdev *vdev = NULL;
  3371. uint8_t i;
  3372. uint8_t pream_type;
  3373. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3374. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3375. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3376. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3377. dp_aggregate_vdev_stats(vdev);
  3378. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3379. for (i = 0; i < MAX_MCS; i++) {
  3380. DP_STATS_AGGR(pdev, vdev,
  3381. tx.pkt_type[pream_type].mcs_count[i]);
  3382. DP_STATS_AGGR(pdev, vdev,
  3383. rx.pkt_type[pream_type].mcs_count[i]);
  3384. }
  3385. }
  3386. for (i = 0; i < MAX_BW; i++) {
  3387. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3388. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3389. }
  3390. for (i = 0; i < SS_COUNT; i++)
  3391. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3392. for (i = 0; i < WME_AC_MAX; i++) {
  3393. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3394. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3395. DP_STATS_AGGR(pdev, vdev,
  3396. tx.excess_retries_ac[i]);
  3397. }
  3398. for (i = 0; i < MAX_GI; i++) {
  3399. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3400. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3401. }
  3402. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3403. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3404. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3405. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3406. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3407. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3408. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3409. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3410. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3411. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3412. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3413. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3414. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3415. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3416. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3417. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3418. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3419. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3420. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3421. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3422. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3423. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3424. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3425. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3426. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3427. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3428. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3429. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3430. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3431. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3432. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3433. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3434. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.nawds_mcast);
  3435. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3436. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3437. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3438. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3439. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3440. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3441. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3442. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3443. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3444. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3445. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3446. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3447. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3448. DP_STATS_AGGR(pdev, vdev,
  3449. tx_i.mcast_en.dropped_map_error);
  3450. DP_STATS_AGGR(pdev, vdev,
  3451. tx_i.mcast_en.dropped_self_mac);
  3452. DP_STATS_AGGR(pdev, vdev,
  3453. tx_i.mcast_en.dropped_send_fail);
  3454. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3455. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3456. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3457. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3458. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3459. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3460. DP_STATS_AGGR(pdev, vdev, tx_i.cce_classified);
  3461. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3462. pdev->stats.tx_i.dropped.dma_error +
  3463. pdev->stats.tx_i.dropped.ring_full +
  3464. pdev->stats.tx_i.dropped.enqueue_fail +
  3465. pdev->stats.tx_i.dropped.desc_na +
  3466. pdev->stats.tx_i.dropped.res_full;
  3467. pdev->stats.tx.last_ack_rssi =
  3468. vdev->stats.tx.last_ack_rssi;
  3469. pdev->stats.tx_i.tso.num_seg =
  3470. vdev->stats.tx_i.tso.num_seg;
  3471. }
  3472. }
  3473. /**
  3474. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3475. * @pdev: DP_PDEV Handle
  3476. *
  3477. * Return:void
  3478. */
  3479. static inline void
  3480. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3481. {
  3482. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3483. DP_PRINT_STATS("Received From Stack:");
  3484. DP_PRINT_STATS(" Packets = %d",
  3485. pdev->stats.tx_i.rcvd.num);
  3486. DP_PRINT_STATS(" Bytes = %d",
  3487. pdev->stats.tx_i.rcvd.bytes);
  3488. DP_PRINT_STATS("Processed:");
  3489. DP_PRINT_STATS(" Packets = %d",
  3490. pdev->stats.tx_i.processed.num);
  3491. DP_PRINT_STATS(" Bytes = %d",
  3492. pdev->stats.tx_i.processed.bytes);
  3493. DP_PRINT_STATS("Completions:");
  3494. DP_PRINT_STATS(" Packets = %d",
  3495. pdev->stats.tx.comp_pkt.num);
  3496. DP_PRINT_STATS(" Bytes = %d",
  3497. pdev->stats.tx.comp_pkt.bytes);
  3498. DP_PRINT_STATS("Dropped:");
  3499. DP_PRINT_STATS(" Total = %d",
  3500. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3501. DP_PRINT_STATS(" Dma_map_error = %d",
  3502. pdev->stats.tx_i.dropped.dma_error);
  3503. DP_PRINT_STATS(" Ring Full = %d",
  3504. pdev->stats.tx_i.dropped.ring_full);
  3505. DP_PRINT_STATS(" Descriptor Not available = %d",
  3506. pdev->stats.tx_i.dropped.desc_na);
  3507. DP_PRINT_STATS(" HW enqueue failed= %d",
  3508. pdev->stats.tx_i.dropped.enqueue_fail);
  3509. DP_PRINT_STATS(" Resources Full = %d",
  3510. pdev->stats.tx_i.dropped.res_full);
  3511. DP_PRINT_STATS(" FW removed = %d",
  3512. pdev->stats.tx.dropped.fw_rem);
  3513. DP_PRINT_STATS(" FW removed transmitted = %d",
  3514. pdev->stats.tx.dropped.fw_rem_tx);
  3515. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3516. pdev->stats.tx.dropped.fw_rem_notx);
  3517. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3518. pdev->stats.tx.dropped.age_out);
  3519. DP_PRINT_STATS("Scatter Gather:");
  3520. DP_PRINT_STATS(" Packets = %d",
  3521. pdev->stats.tx_i.sg.sg_pkt.num);
  3522. DP_PRINT_STATS(" Bytes = %d",
  3523. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3524. DP_PRINT_STATS(" Dropped By Host = %d",
  3525. pdev->stats.tx_i.sg.dropped_host);
  3526. DP_PRINT_STATS(" Dropped By Target = %d",
  3527. pdev->stats.tx_i.sg.dropped_target);
  3528. DP_PRINT_STATS("TSO:");
  3529. DP_PRINT_STATS(" Number of Segments = %d",
  3530. pdev->stats.tx_i.tso.num_seg);
  3531. DP_PRINT_STATS(" Packets = %d",
  3532. pdev->stats.tx_i.tso.tso_pkt.num);
  3533. DP_PRINT_STATS(" Bytes = %d",
  3534. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3535. DP_PRINT_STATS(" Dropped By Host = %d",
  3536. pdev->stats.tx_i.tso.dropped_host);
  3537. DP_PRINT_STATS("Mcast Enhancement:");
  3538. DP_PRINT_STATS(" Packets = %d",
  3539. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3540. DP_PRINT_STATS(" Bytes = %d",
  3541. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3542. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3543. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3544. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3545. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3546. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3547. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3548. DP_PRINT_STATS(" Unicast sent = %d",
  3549. pdev->stats.tx_i.mcast_en.ucast);
  3550. DP_PRINT_STATS("Raw:");
  3551. DP_PRINT_STATS(" Packets = %d",
  3552. pdev->stats.tx_i.raw.raw_pkt.num);
  3553. DP_PRINT_STATS(" Bytes = %d",
  3554. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3555. DP_PRINT_STATS(" DMA map error = %d",
  3556. pdev->stats.tx_i.raw.dma_map_error);
  3557. DP_PRINT_STATS("Reinjected:");
  3558. DP_PRINT_STATS(" Packets = %d",
  3559. pdev->stats.tx_i.reinject_pkts.num);
  3560. DP_PRINT_STATS("Bytes = %d\n",
  3561. pdev->stats.tx_i.reinject_pkts.bytes);
  3562. DP_PRINT_STATS("Inspected:");
  3563. DP_PRINT_STATS(" Packets = %d",
  3564. pdev->stats.tx_i.inspect_pkts.num);
  3565. DP_PRINT_STATS(" Bytes = %d",
  3566. pdev->stats.tx_i.inspect_pkts.bytes);
  3567. DP_PRINT_STATS("Nawds Multicast:");
  3568. DP_PRINT_STATS(" Packets = %d",
  3569. pdev->stats.tx_i.nawds_mcast.num);
  3570. DP_PRINT_STATS(" Bytes = %d",
  3571. pdev->stats.tx_i.nawds_mcast.bytes);
  3572. DP_PRINT_STATS("CCE Classified:");
  3573. DP_TRACE(FATAL, " CCE Classified Packets: %u",
  3574. pdev->stats.tx_i.cce_classified);
  3575. }
  3576. /**
  3577. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3578. * @pdev: DP_PDEV Handle
  3579. *
  3580. * Return: void
  3581. */
  3582. static inline void
  3583. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3584. {
  3585. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3586. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3587. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3588. pdev->stats.rx.rcvd_reo[0].num,
  3589. pdev->stats.rx.rcvd_reo[1].num,
  3590. pdev->stats.rx.rcvd_reo[2].num,
  3591. pdev->stats.rx.rcvd_reo[3].num);
  3592. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3593. pdev->stats.rx.rcvd_reo[0].bytes,
  3594. pdev->stats.rx.rcvd_reo[1].bytes,
  3595. pdev->stats.rx.rcvd_reo[2].bytes,
  3596. pdev->stats.rx.rcvd_reo[3].bytes);
  3597. DP_PRINT_STATS("Replenished:");
  3598. DP_PRINT_STATS(" Packets = %d",
  3599. pdev->stats.replenish.pkts.num);
  3600. DP_PRINT_STATS(" Bytes = %d",
  3601. pdev->stats.replenish.pkts.bytes);
  3602. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3603. pdev->stats.buf_freelist);
  3604. DP_PRINT_STATS(" Low threshold intr = %d",
  3605. pdev->stats.replenish.low_thresh_intrs);
  3606. DP_PRINT_STATS("Dropped:");
  3607. DP_PRINT_STATS(" msdu_not_done = %d",
  3608. pdev->stats.dropped.msdu_not_done);
  3609. DP_PRINT_STATS("Sent To Stack:");
  3610. DP_PRINT_STATS(" Packets = %d",
  3611. pdev->stats.rx.to_stack.num);
  3612. DP_PRINT_STATS(" Bytes = %d",
  3613. pdev->stats.rx.to_stack.bytes);
  3614. DP_PRINT_STATS("Multicast/Broadcast:");
  3615. DP_PRINT_STATS(" Packets = %d",
  3616. pdev->stats.rx.multicast.num);
  3617. DP_PRINT_STATS(" Bytes = %d",
  3618. pdev->stats.rx.multicast.bytes);
  3619. DP_PRINT_STATS("Errors:");
  3620. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3621. pdev->stats.replenish.rxdma_err);
  3622. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3623. pdev->stats.err.desc_alloc_fail);
  3624. /* Get bar_recv_cnt */
  3625. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3626. DP_PRINT_STATS("BAR Received Count: = %d",
  3627. pdev->stats.rx.bar_recv_cnt);
  3628. }
  3629. /**
  3630. * dp_print_soc_tx_stats(): Print SOC level stats
  3631. * @soc DP_SOC Handle
  3632. *
  3633. * Return: void
  3634. */
  3635. static inline void
  3636. dp_print_soc_tx_stats(struct dp_soc *soc)
  3637. {
  3638. DP_PRINT_STATS("SOC Tx Stats:\n");
  3639. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3640. soc->stats.tx.desc_in_use);
  3641. DP_PRINT_STATS("Invalid peer:");
  3642. DP_PRINT_STATS(" Packets = %d",
  3643. soc->stats.tx.tx_invalid_peer.num);
  3644. DP_PRINT_STATS(" Bytes = %d",
  3645. soc->stats.tx.tx_invalid_peer.bytes);
  3646. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3647. soc->stats.tx.tcl_ring_full[0],
  3648. soc->stats.tx.tcl_ring_full[1],
  3649. soc->stats.tx.tcl_ring_full[2]);
  3650. }
  3651. /**
  3652. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3653. * @soc: DP_SOC Handle
  3654. *
  3655. * Return:void
  3656. */
  3657. static inline void
  3658. dp_print_soc_rx_stats(struct dp_soc *soc)
  3659. {
  3660. uint32_t i;
  3661. char reo_error[DP_REO_ERR_LENGTH];
  3662. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3663. uint8_t index = 0;
  3664. DP_PRINT_STATS("SOC Rx Stats:\n");
  3665. DP_PRINT_STATS("Errors:\n");
  3666. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3667. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3668. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3669. DP_PRINT_STATS("Invalid RBM = %d",
  3670. soc->stats.rx.err.invalid_rbm);
  3671. DP_PRINT_STATS("Invalid Vdev = %d",
  3672. soc->stats.rx.err.invalid_vdev);
  3673. DP_PRINT_STATS("Invalid Pdev = %d",
  3674. soc->stats.rx.err.invalid_pdev);
  3675. DP_PRINT_STATS("Invalid Peer = %d",
  3676. soc->stats.rx.err.rx_invalid_peer.num);
  3677. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3678. soc->stats.rx.err.hal_ring_access_fail);
  3679. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3680. index += qdf_snprint(&rxdma_error[index],
  3681. DP_RXDMA_ERR_LENGTH - index,
  3682. " %d", soc->stats.rx.err.rxdma_error[i]);
  3683. }
  3684. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3685. rxdma_error);
  3686. index = 0;
  3687. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3688. index += qdf_snprint(&reo_error[index],
  3689. DP_REO_ERR_LENGTH - index,
  3690. " %d", soc->stats.rx.err.reo_error[i]);
  3691. }
  3692. DP_PRINT_STATS("REO Error(0-14):%s",
  3693. reo_error);
  3694. }
  3695. /**
  3696. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3697. * @soc: DP_SOC handle
  3698. * @srng: DP_SRNG handle
  3699. * @ring_name: SRNG name
  3700. *
  3701. * Return: void
  3702. */
  3703. static inline void
  3704. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3705. char *ring_name)
  3706. {
  3707. uint32_t tailp;
  3708. uint32_t headp;
  3709. if (srng->hal_srng != NULL) {
  3710. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3711. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3712. ring_name, headp, tailp);
  3713. }
  3714. }
  3715. /**
  3716. * dp_print_ring_stats(): Print tail and head pointer
  3717. * @pdev: DP_PDEV handle
  3718. *
  3719. * Return:void
  3720. */
  3721. static inline void
  3722. dp_print_ring_stats(struct dp_pdev *pdev)
  3723. {
  3724. uint32_t i;
  3725. char ring_name[STR_MAXLEN + 1];
  3726. dp_print_ring_stat_from_hal(pdev->soc,
  3727. &pdev->soc->reo_exception_ring,
  3728. "Reo Exception Ring");
  3729. dp_print_ring_stat_from_hal(pdev->soc,
  3730. &pdev->soc->reo_reinject_ring,
  3731. "Reo Inject Ring");
  3732. dp_print_ring_stat_from_hal(pdev->soc,
  3733. &pdev->soc->reo_cmd_ring,
  3734. "Reo Command Ring");
  3735. dp_print_ring_stat_from_hal(pdev->soc,
  3736. &pdev->soc->reo_status_ring,
  3737. "Reo Status Ring");
  3738. dp_print_ring_stat_from_hal(pdev->soc,
  3739. &pdev->soc->rx_rel_ring,
  3740. "Rx Release ring");
  3741. dp_print_ring_stat_from_hal(pdev->soc,
  3742. &pdev->soc->tcl_cmd_ring,
  3743. "Tcl command Ring");
  3744. dp_print_ring_stat_from_hal(pdev->soc,
  3745. &pdev->soc->tcl_status_ring,
  3746. "Tcl Status Ring");
  3747. dp_print_ring_stat_from_hal(pdev->soc,
  3748. &pdev->soc->wbm_desc_rel_ring,
  3749. "Wbm Desc Rel Ring");
  3750. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3751. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3752. dp_print_ring_stat_from_hal(pdev->soc,
  3753. &pdev->soc->reo_dest_ring[i],
  3754. ring_name);
  3755. }
  3756. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3757. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3758. dp_print_ring_stat_from_hal(pdev->soc,
  3759. &pdev->soc->tcl_data_ring[i],
  3760. ring_name);
  3761. }
  3762. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3763. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3764. dp_print_ring_stat_from_hal(pdev->soc,
  3765. &pdev->soc->tx_comp_ring[i],
  3766. ring_name);
  3767. }
  3768. dp_print_ring_stat_from_hal(pdev->soc,
  3769. &pdev->rx_refill_buf_ring,
  3770. "Rx Refill Buf Ring");
  3771. dp_print_ring_stat_from_hal(pdev->soc,
  3772. &pdev->rx_refill_buf_ring2,
  3773. "Second Rx Refill Buf Ring");
  3774. dp_print_ring_stat_from_hal(pdev->soc,
  3775. &pdev->rxdma_mon_buf_ring,
  3776. "Rxdma Mon Buf Ring");
  3777. dp_print_ring_stat_from_hal(pdev->soc,
  3778. &pdev->rxdma_mon_dst_ring,
  3779. "Rxdma Mon Dst Ring");
  3780. dp_print_ring_stat_from_hal(pdev->soc,
  3781. &pdev->rxdma_mon_status_ring,
  3782. "Rxdma Mon Status Ring");
  3783. dp_print_ring_stat_from_hal(pdev->soc,
  3784. &pdev->rxdma_mon_desc_ring,
  3785. "Rxdma mon desc Ring");
  3786. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3787. snprintf(ring_name, STR_MAXLEN, "Rxdma err dst ring %d", i);
  3788. dp_print_ring_stat_from_hal(pdev->soc,
  3789. &pdev->rxdma_err_dst_ring[i],
  3790. ring_name);
  3791. }
  3792. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3793. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3794. dp_print_ring_stat_from_hal(pdev->soc,
  3795. &pdev->rx_mac_buf_ring[i],
  3796. ring_name);
  3797. }
  3798. }
  3799. /**
  3800. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3801. * @vdev: DP_VDEV handle
  3802. *
  3803. * Return:void
  3804. */
  3805. static inline void
  3806. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3807. {
  3808. struct dp_peer *peer = NULL;
  3809. DP_STATS_CLR(vdev->pdev);
  3810. DP_STATS_CLR(vdev->pdev->soc);
  3811. DP_STATS_CLR(vdev);
  3812. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3813. if (!peer)
  3814. return;
  3815. DP_STATS_CLR(peer);
  3816. }
  3817. }
  3818. /**
  3819. * dp_print_rx_rates(): Print Rx rate stats
  3820. * @vdev: DP_VDEV handle
  3821. *
  3822. * Return:void
  3823. */
  3824. static inline void
  3825. dp_print_rx_rates(struct dp_vdev *vdev)
  3826. {
  3827. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3828. uint8_t i, mcs, pkt_type;
  3829. uint8_t index = 0;
  3830. char nss[DP_NSS_LENGTH];
  3831. DP_PRINT_STATS("Rx Rate Info:\n");
  3832. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3833. index = 0;
  3834. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3835. if (!dp_rate_string[pkt_type][mcs].valid)
  3836. continue;
  3837. DP_PRINT_STATS(" %s = %d",
  3838. dp_rate_string[pkt_type][mcs].mcs_type,
  3839. pdev->stats.rx.pkt_type[pkt_type].
  3840. mcs_count[mcs]);
  3841. }
  3842. DP_PRINT_STATS("\n");
  3843. }
  3844. index = 0;
  3845. for (i = 0; i < SS_COUNT; i++) {
  3846. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3847. " %d", pdev->stats.rx.nss[i]);
  3848. }
  3849. DP_PRINT_STATS("NSS(0-7) = %s",
  3850. nss);
  3851. DP_PRINT_STATS("SGI ="
  3852. " 0.8us %d,"
  3853. " 0.4us %d,"
  3854. " 1.6us %d,"
  3855. " 3.2us %d,",
  3856. pdev->stats.rx.sgi_count[0],
  3857. pdev->stats.rx.sgi_count[1],
  3858. pdev->stats.rx.sgi_count[2],
  3859. pdev->stats.rx.sgi_count[3]);
  3860. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3861. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3862. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3863. DP_PRINT_STATS("Reception Type ="
  3864. " SU: %d,"
  3865. " MU_MIMO:%d,"
  3866. " MU_OFDMA:%d,"
  3867. " MU_OFDMA_MIMO:%d\n",
  3868. pdev->stats.rx.reception_type[0],
  3869. pdev->stats.rx.reception_type[1],
  3870. pdev->stats.rx.reception_type[2],
  3871. pdev->stats.rx.reception_type[3]);
  3872. DP_PRINT_STATS("Aggregation:\n");
  3873. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3874. pdev->stats.rx.ampdu_cnt);
  3875. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3876. pdev->stats.rx.non_ampdu_cnt);
  3877. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3878. pdev->stats.rx.amsdu_cnt);
  3879. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3880. pdev->stats.rx.non_amsdu_cnt);
  3881. }
  3882. /**
  3883. * dp_print_tx_rates(): Print tx rates
  3884. * @vdev: DP_VDEV handle
  3885. *
  3886. * Return:void
  3887. */
  3888. static inline void
  3889. dp_print_tx_rates(struct dp_vdev *vdev)
  3890. {
  3891. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3892. uint8_t mcs, pkt_type;
  3893. uint32_t index;
  3894. DP_PRINT_STATS("Tx Rate Info:\n");
  3895. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3896. index = 0;
  3897. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3898. if (!dp_rate_string[pkt_type][mcs].valid)
  3899. continue;
  3900. DP_PRINT_STATS(" %s = %d",
  3901. dp_rate_string[pkt_type][mcs].mcs_type,
  3902. pdev->stats.tx.pkt_type[pkt_type].
  3903. mcs_count[mcs]);
  3904. }
  3905. DP_PRINT_STATS("\n");
  3906. }
  3907. DP_PRINT_STATS("SGI ="
  3908. " 0.8us %d"
  3909. " 0.4us %d"
  3910. " 1.6us %d"
  3911. " 3.2us %d",
  3912. pdev->stats.tx.sgi_count[0],
  3913. pdev->stats.tx.sgi_count[1],
  3914. pdev->stats.tx.sgi_count[2],
  3915. pdev->stats.tx.sgi_count[3]);
  3916. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3917. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3918. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3919. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3920. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3921. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3922. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3923. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3924. DP_PRINT_STATS("Aggregation:\n");
  3925. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3926. pdev->stats.tx.amsdu_cnt);
  3927. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3928. pdev->stats.tx.non_amsdu_cnt);
  3929. }
  3930. /**
  3931. * dp_print_peer_stats():print peer stats
  3932. * @peer: DP_PEER handle
  3933. *
  3934. * return void
  3935. */
  3936. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3937. {
  3938. uint8_t i, mcs, pkt_type;
  3939. uint32_t index;
  3940. char nss[DP_NSS_LENGTH];
  3941. DP_PRINT_STATS("Node Tx Stats:\n");
  3942. DP_PRINT_STATS("Total Packet Completions = %d",
  3943. peer->stats.tx.comp_pkt.num);
  3944. DP_PRINT_STATS("Total Bytes Completions = %d",
  3945. peer->stats.tx.comp_pkt.bytes);
  3946. DP_PRINT_STATS("Success Packets = %d",
  3947. peer->stats.tx.tx_success.num);
  3948. DP_PRINT_STATS("Success Bytes = %d",
  3949. peer->stats.tx.tx_success.bytes);
  3950. DP_PRINT_STATS("Packets Failed = %d",
  3951. peer->stats.tx.tx_failed);
  3952. DP_PRINT_STATS("Packets In OFDMA = %d",
  3953. peer->stats.tx.ofdma);
  3954. DP_PRINT_STATS("Packets In STBC = %d",
  3955. peer->stats.tx.stbc);
  3956. DP_PRINT_STATS("Packets In LDPC = %d",
  3957. peer->stats.tx.ldpc);
  3958. DP_PRINT_STATS("Packet Retries = %d",
  3959. peer->stats.tx.retries);
  3960. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3961. peer->stats.tx.amsdu_cnt);
  3962. DP_PRINT_STATS("Last Packet RSSI = %d",
  3963. peer->stats.tx.last_ack_rssi);
  3964. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3965. peer->stats.tx.dropped.fw_rem);
  3966. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3967. peer->stats.tx.dropped.fw_rem_tx);
  3968. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3969. peer->stats.tx.dropped.fw_rem_notx);
  3970. DP_PRINT_STATS("Dropped : Age Out = %d",
  3971. peer->stats.tx.dropped.age_out);
  3972. DP_PRINT_STATS("NAWDS : ");
  3973. DP_PRINT_STATS(" Nawds multicast Drop Tx Packet = %d",
  3974. peer->stats.tx.nawds_mcast_drop);
  3975. DP_PRINT_STATS(" Nawds multicast Tx Packet Count = %d",
  3976. peer->stats.tx.nawds_mcast.num);
  3977. DP_PRINT_STATS(" Nawds multicast Tx Packet Bytes = %d",
  3978. peer->stats.tx.nawds_mcast.bytes);
  3979. DP_PRINT_STATS("Rate Info:");
  3980. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3981. index = 0;
  3982. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3983. if (!dp_rate_string[pkt_type][mcs].valid)
  3984. continue;
  3985. DP_PRINT_STATS(" %s = %d",
  3986. dp_rate_string[pkt_type][mcs].mcs_type,
  3987. peer->stats.tx.pkt_type[pkt_type].
  3988. mcs_count[mcs]);
  3989. }
  3990. DP_PRINT_STATS("\n");
  3991. }
  3992. DP_PRINT_STATS("SGI = "
  3993. " 0.8us %d"
  3994. " 0.4us %d"
  3995. " 1.6us %d"
  3996. " 3.2us %d",
  3997. peer->stats.tx.sgi_count[0],
  3998. peer->stats.tx.sgi_count[1],
  3999. peer->stats.tx.sgi_count[2],
  4000. peer->stats.tx.sgi_count[3]);
  4001. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  4002. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  4003. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  4004. DP_PRINT_STATS("Aggregation:");
  4005. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  4006. peer->stats.tx.amsdu_cnt);
  4007. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  4008. peer->stats.tx.non_amsdu_cnt);
  4009. DP_PRINT_STATS("Node Rx Stats:");
  4010. DP_PRINT_STATS("Packets Sent To Stack = %d",
  4011. peer->stats.rx.to_stack.num);
  4012. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  4013. peer->stats.rx.to_stack.bytes);
  4014. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  4015. DP_PRINT_STATS("Packets Received = %d",
  4016. peer->stats.rx.rcvd_reo[i].num);
  4017. DP_PRINT_STATS("Bytes Received = %d",
  4018. peer->stats.rx.rcvd_reo[i].bytes);
  4019. }
  4020. DP_PRINT_STATS("Multicast Packets Received = %d",
  4021. peer->stats.rx.multicast.num);
  4022. DP_PRINT_STATS("Multicast Bytes Received = %d",
  4023. peer->stats.rx.multicast.bytes);
  4024. DP_PRINT_STATS("WDS Packets Received = %d",
  4025. peer->stats.rx.wds.num);
  4026. DP_PRINT_STATS("WDS Bytes Received = %d",
  4027. peer->stats.rx.wds.bytes);
  4028. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  4029. peer->stats.rx.intra_bss.pkts.num);
  4030. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  4031. peer->stats.rx.intra_bss.pkts.bytes);
  4032. DP_PRINT_STATS("Raw Packets Received = %d",
  4033. peer->stats.rx.raw.num);
  4034. DP_PRINT_STATS("Raw Bytes Received = %d",
  4035. peer->stats.rx.raw.bytes);
  4036. DP_PRINT_STATS("Errors: MIC Errors = %d",
  4037. peer->stats.rx.err.mic_err);
  4038. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  4039. peer->stats.rx.err.decrypt_err);
  4040. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  4041. peer->stats.rx.non_ampdu_cnt);
  4042. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  4043. peer->stats.rx.ampdu_cnt);
  4044. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  4045. peer->stats.rx.non_amsdu_cnt);
  4046. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  4047. peer->stats.rx.amsdu_cnt);
  4048. DP_PRINT_STATS("NAWDS : ");
  4049. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet = %d",
  4050. peer->stats.rx.nawds_mcast_drop.num);
  4051. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet Bytes = %d",
  4052. peer->stats.rx.nawds_mcast_drop.bytes);
  4053. DP_PRINT_STATS("SGI ="
  4054. " 0.8us %d"
  4055. " 0.4us %d"
  4056. " 1.6us %d"
  4057. " 3.2us %d",
  4058. peer->stats.rx.sgi_count[0],
  4059. peer->stats.rx.sgi_count[1],
  4060. peer->stats.rx.sgi_count[2],
  4061. peer->stats.rx.sgi_count[3]);
  4062. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  4063. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  4064. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  4065. DP_PRINT_STATS("Reception Type ="
  4066. " SU %d,"
  4067. " MU_MIMO %d,"
  4068. " MU_OFDMA %d,"
  4069. " MU_OFDMA_MIMO %d",
  4070. peer->stats.rx.reception_type[0],
  4071. peer->stats.rx.reception_type[1],
  4072. peer->stats.rx.reception_type[2],
  4073. peer->stats.rx.reception_type[3]);
  4074. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4075. index = 0;
  4076. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4077. if (!dp_rate_string[pkt_type][mcs].valid)
  4078. continue;
  4079. DP_PRINT_STATS(" %s = %d",
  4080. dp_rate_string[pkt_type][mcs].mcs_type,
  4081. peer->stats.rx.pkt_type[pkt_type].
  4082. mcs_count[mcs]);
  4083. }
  4084. DP_PRINT_STATS("\n");
  4085. }
  4086. index = 0;
  4087. for (i = 0; i < SS_COUNT; i++) {
  4088. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4089. " %d", peer->stats.rx.nss[i]);
  4090. }
  4091. DP_PRINT_STATS("NSS(0-7) = %s",
  4092. nss);
  4093. DP_PRINT_STATS("Aggregation:");
  4094. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  4095. peer->stats.rx.ampdu_cnt);
  4096. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  4097. peer->stats.rx.non_ampdu_cnt);
  4098. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  4099. peer->stats.rx.amsdu_cnt);
  4100. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  4101. peer->stats.rx.non_amsdu_cnt);
  4102. }
  4103. /**
  4104. * dp_print_host_stats()- Function to print the stats aggregated at host
  4105. * @vdev_handle: DP_VDEV handle
  4106. * @type: host stats type
  4107. *
  4108. * Available Stat types
  4109. * TXRX_CLEAR_STATS : Clear the stats
  4110. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  4111. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  4112. * TXRX_TX_HOST_STATS: Print Tx Stats
  4113. * TXRX_RX_HOST_STATS: Print Rx Stats
  4114. * TXRX_AST_STATS: Print AST Stats
  4115. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  4116. *
  4117. * Return: 0 on success, print error message in case of failure
  4118. */
  4119. static int
  4120. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  4121. {
  4122. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4123. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4124. dp_aggregate_pdev_stats(pdev);
  4125. switch (type) {
  4126. case TXRX_CLEAR_STATS:
  4127. dp_txrx_host_stats_clr(vdev);
  4128. break;
  4129. case TXRX_RX_RATE_STATS:
  4130. dp_print_rx_rates(vdev);
  4131. break;
  4132. case TXRX_TX_RATE_STATS:
  4133. dp_print_tx_rates(vdev);
  4134. break;
  4135. case TXRX_TX_HOST_STATS:
  4136. dp_print_pdev_tx_stats(pdev);
  4137. dp_print_soc_tx_stats(pdev->soc);
  4138. break;
  4139. case TXRX_RX_HOST_STATS:
  4140. dp_print_pdev_rx_stats(pdev);
  4141. dp_print_soc_rx_stats(pdev->soc);
  4142. break;
  4143. case TXRX_AST_STATS:
  4144. dp_print_ast_stats(pdev->soc);
  4145. break;
  4146. case TXRX_SRNG_PTR_STATS:
  4147. dp_print_ring_stats(pdev);
  4148. break;
  4149. default:
  4150. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  4151. break;
  4152. }
  4153. return 0;
  4154. }
  4155. /*
  4156. * dp_get_host_peer_stats()- function to print peer stats
  4157. * @pdev_handle: DP_PDEV handle
  4158. * @mac_addr: mac address of the peer
  4159. *
  4160. * Return: void
  4161. */
  4162. static void
  4163. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4164. {
  4165. struct dp_peer *peer;
  4166. uint8_t local_id;
  4167. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4168. &local_id);
  4169. if (!peer) {
  4170. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4171. "%s: Invalid peer\n", __func__);
  4172. return;
  4173. }
  4174. dp_print_peer_stats(peer);
  4175. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  4176. return;
  4177. }
  4178. /*
  4179. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4180. * @pdev: DP_PDEV handle
  4181. *
  4182. * Return: void
  4183. */
  4184. static void
  4185. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4186. {
  4187. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4188. htt_tlv_filter.mpdu_start = 0;
  4189. htt_tlv_filter.msdu_start = 0;
  4190. htt_tlv_filter.packet = 0;
  4191. htt_tlv_filter.msdu_end = 0;
  4192. htt_tlv_filter.mpdu_end = 0;
  4193. htt_tlv_filter.packet_header = 1;
  4194. htt_tlv_filter.attention = 1;
  4195. htt_tlv_filter.ppdu_start = 1;
  4196. htt_tlv_filter.ppdu_end = 1;
  4197. htt_tlv_filter.ppdu_end_user_stats = 1;
  4198. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4199. htt_tlv_filter.ppdu_end_status_done = 1;
  4200. htt_tlv_filter.enable_fp = 1;
  4201. htt_tlv_filter.enable_md = 0;
  4202. htt_tlv_filter.enable_mo = 0;
  4203. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  4204. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  4205. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  4206. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  4207. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  4208. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  4209. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4210. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4211. RX_BUFFER_SIZE, &htt_tlv_filter);
  4212. }
  4213. /*
  4214. * dp_config_debug_sniffer()- API to enable/disable debug sniffer
  4215. * @pdev_handle: DP_PDEV handle
  4216. * @val: user provided value
  4217. *
  4218. * Return: void
  4219. */
  4220. static void
  4221. dp_config_debug_sniffer(struct cdp_pdev *pdev_handle, int val)
  4222. {
  4223. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4224. switch (val) {
  4225. case 0:
  4226. pdev->tx_sniffer_enable = 0;
  4227. pdev->am_copy_mode = 0;
  4228. pdev->soc->process_tx_status = 0;
  4229. if (!pdev->enhanced_stats_en)
  4230. dp_h2t_cfg_stats_msg_send(pdev, 0, pdev->pdev_id);
  4231. break;
  4232. case 1:
  4233. pdev->tx_sniffer_enable = 1;
  4234. pdev->am_copy_mode = 0;
  4235. pdev->soc->process_tx_status = 1;
  4236. dp_h2t_cfg_stats_msg_send(pdev,
  4237. DP_PPDU_STATS_CFG_ALL, pdev->pdev_id);
  4238. break;
  4239. case 2:
  4240. pdev->am_copy_mode = 1;
  4241. pdev->tx_sniffer_enable = 0;
  4242. pdev->soc->process_tx_status = 1;
  4243. dp_ppdu_ring_cfg(pdev);
  4244. dp_h2t_cfg_stats_msg_send(pdev,
  4245. DP_PPDU_STATS_CFG_ALL, pdev->pdev_id);
  4246. break;
  4247. default:
  4248. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4249. "Invalid value\n");
  4250. break;
  4251. }
  4252. }
  4253. /*
  4254. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4255. * @pdev_handle: DP_PDEV handle
  4256. *
  4257. * Return: void
  4258. */
  4259. static void
  4260. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4261. {
  4262. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4263. pdev->enhanced_stats_en = 1;
  4264. dp_ppdu_ring_cfg(pdev);
  4265. dp_h2t_cfg_stats_msg_send(pdev, 0xffff, pdev->pdev_id);
  4266. }
  4267. /*
  4268. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4269. * @pdev_handle: DP_PDEV handle
  4270. *
  4271. * Return: void
  4272. */
  4273. static void
  4274. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4275. {
  4276. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4277. pdev->enhanced_stats_en = 0;
  4278. if (!pdev->tx_sniffer_enable && !pdev->am_copy_mode)
  4279. dp_h2t_cfg_stats_msg_send(pdev, 0, pdev->pdev_id);
  4280. }
  4281. /*
  4282. * dp_get_fw_peer_stats()- function to print peer stats
  4283. * @pdev_handle: DP_PDEV handle
  4284. * @mac_addr: mac address of the peer
  4285. * @cap: Type of htt stats requested
  4286. *
  4287. * Currently Supporting only MAC ID based requests Only
  4288. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4289. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4290. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4291. *
  4292. * Return: void
  4293. */
  4294. static void
  4295. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4296. uint32_t cap)
  4297. {
  4298. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4299. int i;
  4300. uint32_t config_param0 = 0;
  4301. uint32_t config_param1 = 0;
  4302. uint32_t config_param2 = 0;
  4303. uint32_t config_param3 = 0;
  4304. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4305. config_param0 |= (1 << (cap + 1));
  4306. for (i = 0; i < HTT_PEER_STATS_MAX_TLV; i++) {
  4307. config_param1 |= (1 << i);
  4308. }
  4309. config_param2 |= (mac_addr[0] & 0x000000ff);
  4310. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4311. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4312. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4313. config_param3 |= (mac_addr[4] & 0x000000ff);
  4314. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4315. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4316. config_param0, config_param1, config_param2,
  4317. config_param3, 0);
  4318. }
  4319. /* This struct definition will be removed from here
  4320. * once it get added in FW headers*/
  4321. struct httstats_cmd_req {
  4322. uint32_t config_param0;
  4323. uint32_t config_param1;
  4324. uint32_t config_param2;
  4325. uint32_t config_param3;
  4326. int cookie;
  4327. u_int8_t stats_id;
  4328. };
  4329. /*
  4330. * dp_get_htt_stats: function to process the httstas request
  4331. * @pdev_handle: DP pdev handle
  4332. * @data: pointer to request data
  4333. * @data_len: length for request data
  4334. *
  4335. * return: void
  4336. */
  4337. static void
  4338. dp_get_htt_stats(struct cdp_pdev *pdev_handle, void *data, uint32_t data_len)
  4339. {
  4340. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4341. struct httstats_cmd_req *req = (struct httstats_cmd_req *)data;
  4342. QDF_ASSERT(data_len == sizeof(struct httstats_cmd_req));
  4343. dp_h2t_ext_stats_msg_send(pdev, req->stats_id,
  4344. req->config_param0, req->config_param1,
  4345. req->config_param2, req->config_param3,
  4346. req->cookie);
  4347. }
  4348. /*
  4349. * dp_set_pdev_param: function to set parameters in pdev
  4350. * @pdev_handle: DP pdev handle
  4351. * @param: parameter type to be set
  4352. * @val: value of parameter to be set
  4353. *
  4354. * return: void
  4355. */
  4356. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  4357. enum cdp_pdev_param_type param, uint8_t val)
  4358. {
  4359. switch (param) {
  4360. case CDP_CONFIG_DEBUG_SNIFFER:
  4361. dp_config_debug_sniffer(pdev_handle, val);
  4362. break;
  4363. default:
  4364. break;
  4365. }
  4366. }
  4367. /*
  4368. * dp_set_vdev_param: function to set parameters in vdev
  4369. * @param: parameter type to be set
  4370. * @val: value of parameter to be set
  4371. *
  4372. * return: void
  4373. */
  4374. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4375. enum cdp_vdev_param_type param, uint32_t val)
  4376. {
  4377. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4378. switch (param) {
  4379. case CDP_ENABLE_WDS:
  4380. vdev->wds_enabled = val;
  4381. break;
  4382. case CDP_ENABLE_NAWDS:
  4383. vdev->nawds_enabled = val;
  4384. break;
  4385. case CDP_ENABLE_MCAST_EN:
  4386. vdev->mcast_enhancement_en = val;
  4387. break;
  4388. case CDP_ENABLE_PROXYSTA:
  4389. vdev->proxysta_vdev = val;
  4390. break;
  4391. case CDP_UPDATE_TDLS_FLAGS:
  4392. vdev->tdls_link_connected = val;
  4393. break;
  4394. case CDP_CFG_WDS_AGING_TIMER:
  4395. if (val == 0)
  4396. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4397. else if (val != vdev->wds_aging_timer_val)
  4398. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4399. vdev->wds_aging_timer_val = val;
  4400. break;
  4401. case CDP_ENABLE_AP_BRIDGE:
  4402. if (wlan_op_mode_sta != vdev->opmode)
  4403. vdev->ap_bridge_enabled = val;
  4404. else
  4405. vdev->ap_bridge_enabled = false;
  4406. break;
  4407. case CDP_ENABLE_CIPHER:
  4408. vdev->sec_type = val;
  4409. break;
  4410. default:
  4411. break;
  4412. }
  4413. dp_tx_vdev_update_search_flags(vdev);
  4414. }
  4415. /**
  4416. * dp_peer_set_nawds: set nawds bit in peer
  4417. * @peer_handle: pointer to peer
  4418. * @value: enable/disable nawds
  4419. *
  4420. * return: void
  4421. */
  4422. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4423. {
  4424. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4425. peer->nawds_enabled = value;
  4426. }
  4427. /*
  4428. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4429. * @vdev_handle: DP_VDEV handle
  4430. * @map_id:ID of map that needs to be updated
  4431. *
  4432. * Return: void
  4433. */
  4434. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4435. uint8_t map_id)
  4436. {
  4437. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4438. vdev->dscp_tid_map_id = map_id;
  4439. return;
  4440. }
  4441. /**
  4442. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4443. * @pdev: DP_PDEV handle
  4444. * @map_id: ID of map that needs to be updated
  4445. * @tos: index value in map
  4446. * @tid: tid value passed by the user
  4447. *
  4448. * Return: void
  4449. */
  4450. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4451. uint8_t map_id, uint8_t tos, uint8_t tid)
  4452. {
  4453. uint8_t dscp;
  4454. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4455. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4456. pdev->dscp_tid_map[map_id][dscp] = tid;
  4457. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4458. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4459. map_id, dscp);
  4460. return;
  4461. }
  4462. /**
  4463. * dp_fw_stats_process(): Process TxRX FW stats request
  4464. * @vdev_handle: DP VDEV handle
  4465. * @req: stats request
  4466. *
  4467. * return: int
  4468. */
  4469. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle,
  4470. struct cdp_txrx_stats_req *req)
  4471. {
  4472. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4473. struct dp_pdev *pdev = NULL;
  4474. uint32_t stats = req->stats;
  4475. if (!vdev) {
  4476. DP_TRACE(NONE, "VDEV not found");
  4477. return 1;
  4478. }
  4479. pdev = vdev->pdev;
  4480. return dp_h2t_ext_stats_msg_send(pdev, stats, req->param0,
  4481. req->param1, req->param2, req->param3, 0);
  4482. }
  4483. /**
  4484. * dp_txrx_stats_request - function to map to firmware and host stats
  4485. * @vdev: virtual handle
  4486. * @req: stats request
  4487. *
  4488. * Return: integer
  4489. */
  4490. static int dp_txrx_stats_request(struct cdp_vdev *vdev,
  4491. struct cdp_txrx_stats_req *req)
  4492. {
  4493. int host_stats;
  4494. int fw_stats;
  4495. enum cdp_stats stats;
  4496. if (!vdev || !req) {
  4497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4498. "Invalid vdev/req instance");
  4499. return 0;
  4500. }
  4501. stats = req->stats;
  4502. if (stats >= CDP_TXRX_MAX_STATS)
  4503. return 0;
  4504. /*
  4505. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4506. * has to be updated if new FW HTT stats added
  4507. */
  4508. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4509. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4510. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4511. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4512. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4513. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4514. stats, fw_stats, host_stats);
  4515. if (fw_stats != TXRX_FW_STATS_INVALID) {
  4516. /* update request with FW stats type */
  4517. req->stats = fw_stats;
  4518. return dp_fw_stats_process(vdev, req);
  4519. }
  4520. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4521. (host_stats <= TXRX_HOST_STATS_MAX))
  4522. return dp_print_host_stats(vdev, host_stats);
  4523. else
  4524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4525. "Wrong Input for TxRx Stats");
  4526. return 0;
  4527. }
  4528. /**
  4529. * dp_txrx_stats() - function to map to firmware and host stats
  4530. * @vdev: virtual handle
  4531. * @stats: type of statistics requested
  4532. *
  4533. * Return: integer
  4534. */
  4535. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4536. {
  4537. struct cdp_txrx_stats_req req = {0,};
  4538. req.stats = stats;
  4539. return dp_txrx_stats_request(vdev, &req);
  4540. }
  4541. /*
  4542. * dp_print_napi_stats(): NAPI stats
  4543. * @soc - soc handle
  4544. */
  4545. static void dp_print_napi_stats(struct dp_soc *soc)
  4546. {
  4547. hif_print_napi_stats(soc->hif_handle);
  4548. }
  4549. /*
  4550. * dp_print_per_ring_stats(): Packet count per ring
  4551. * @soc - soc handle
  4552. */
  4553. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4554. {
  4555. uint8_t core, ring;
  4556. uint64_t total_packets;
  4557. DP_TRACE(FATAL, "Reo packets per ring:");
  4558. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4559. total_packets = 0;
  4560. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4561. for (core = 0; core < NR_CPUS; core++) {
  4562. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4563. core, soc->stats.rx.ring_packets[core][ring]);
  4564. total_packets += soc->stats.rx.ring_packets[core][ring];
  4565. }
  4566. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4567. ring, total_packets);
  4568. }
  4569. }
  4570. /*
  4571. * dp_txrx_path_stats() - Function to display dump stats
  4572. * @soc - soc handle
  4573. *
  4574. * return: none
  4575. */
  4576. static void dp_txrx_path_stats(struct dp_soc *soc)
  4577. {
  4578. uint8_t error_code;
  4579. uint8_t loop_pdev;
  4580. struct dp_pdev *pdev;
  4581. uint8_t i;
  4582. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4583. pdev = soc->pdev_list[loop_pdev];
  4584. dp_aggregate_pdev_stats(pdev);
  4585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4586. "Tx path Statistics:");
  4587. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4588. pdev->stats.tx_i.rcvd.num,
  4589. pdev->stats.tx_i.rcvd.bytes);
  4590. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4591. pdev->stats.tx_i.processed.num,
  4592. pdev->stats.tx_i.processed.bytes);
  4593. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4594. pdev->stats.tx.tx_success.num,
  4595. pdev->stats.tx.tx_success.bytes);
  4596. DP_TRACE(FATAL, "Dropped in host:");
  4597. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4598. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4599. DP_TRACE(FATAL, "Descriptor not available: %u",
  4600. pdev->stats.tx_i.dropped.desc_na);
  4601. DP_TRACE(FATAL, "Ring full: %u",
  4602. pdev->stats.tx_i.dropped.ring_full);
  4603. DP_TRACE(FATAL, "Enqueue fail: %u",
  4604. pdev->stats.tx_i.dropped.enqueue_fail);
  4605. DP_TRACE(FATAL, "DMA Error: %u",
  4606. pdev->stats.tx_i.dropped.dma_error);
  4607. DP_TRACE(FATAL, "Dropped in hardware:");
  4608. DP_TRACE(FATAL, "total packets dropped: %u",
  4609. pdev->stats.tx.tx_failed);
  4610. DP_TRACE(FATAL, "mpdu age out: %u",
  4611. pdev->stats.tx.dropped.age_out);
  4612. DP_TRACE(FATAL, "firmware removed: %u",
  4613. pdev->stats.tx.dropped.fw_rem);
  4614. DP_TRACE(FATAL, "firmware removed tx: %u",
  4615. pdev->stats.tx.dropped.fw_rem_tx);
  4616. DP_TRACE(FATAL, "firmware removed notx %u",
  4617. pdev->stats.tx.dropped.fw_rem_notx);
  4618. DP_TRACE(FATAL, "peer_invalid: %u",
  4619. pdev->soc->stats.tx.tx_invalid_peer.num);
  4620. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4621. DP_TRACE(FATAL, "Single Packet: %u",
  4622. pdev->stats.tx_comp_histogram.pkts_1);
  4623. DP_TRACE(FATAL, "2-20 Packets: %u",
  4624. pdev->stats.tx_comp_histogram.pkts_2_20);
  4625. DP_TRACE(FATAL, "21-40 Packets: %u",
  4626. pdev->stats.tx_comp_histogram.pkts_21_40);
  4627. DP_TRACE(FATAL, "41-60 Packets: %u",
  4628. pdev->stats.tx_comp_histogram.pkts_41_60);
  4629. DP_TRACE(FATAL, "61-80 Packets: %u",
  4630. pdev->stats.tx_comp_histogram.pkts_61_80);
  4631. DP_TRACE(FATAL, "81-100 Packets: %u",
  4632. pdev->stats.tx_comp_histogram.pkts_81_100);
  4633. DP_TRACE(FATAL, "101-200 Packets: %u",
  4634. pdev->stats.tx_comp_histogram.pkts_101_200);
  4635. DP_TRACE(FATAL, " 201+ Packets: %u",
  4636. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4637. DP_TRACE(FATAL, "Rx path statistics");
  4638. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4639. pdev->stats.rx.to_stack.num,
  4640. pdev->stats.rx.to_stack.bytes);
  4641. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4642. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4643. i, pdev->stats.rx.rcvd_reo[i].num,
  4644. pdev->stats.rx.rcvd_reo[i].bytes);
  4645. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4646. pdev->stats.rx.intra_bss.pkts.num,
  4647. pdev->stats.rx.intra_bss.pkts.bytes);
  4648. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4649. pdev->stats.rx.intra_bss.fail.num,
  4650. pdev->stats.rx.intra_bss.fail.bytes);
  4651. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4652. pdev->stats.rx.raw.num,
  4653. pdev->stats.rx.raw.bytes);
  4654. DP_TRACE(FATAL, "dropped: error %u msdus",
  4655. pdev->stats.rx.err.mic_err);
  4656. DP_TRACE(FATAL, "peer invalid %u",
  4657. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4658. DP_TRACE(FATAL, "Reo Statistics");
  4659. DP_TRACE(FATAL, "rbm error: %u msdus",
  4660. pdev->soc->stats.rx.err.invalid_rbm);
  4661. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4662. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4663. DP_TRACE(FATAL, "Reo errors");
  4664. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4665. error_code++) {
  4666. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4667. error_code,
  4668. pdev->soc->stats.rx.err.reo_error[error_code]);
  4669. }
  4670. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4671. error_code++) {
  4672. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4673. error_code,
  4674. pdev->soc->stats.rx.err
  4675. .rxdma_error[error_code]);
  4676. }
  4677. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4678. DP_TRACE(FATAL, "Single Packet: %u",
  4679. pdev->stats.rx_ind_histogram.pkts_1);
  4680. DP_TRACE(FATAL, "2-20 Packets: %u",
  4681. pdev->stats.rx_ind_histogram.pkts_2_20);
  4682. DP_TRACE(FATAL, "21-40 Packets: %u",
  4683. pdev->stats.rx_ind_histogram.pkts_21_40);
  4684. DP_TRACE(FATAL, "41-60 Packets: %u",
  4685. pdev->stats.rx_ind_histogram.pkts_41_60);
  4686. DP_TRACE(FATAL, "61-80 Packets: %u",
  4687. pdev->stats.rx_ind_histogram.pkts_61_80);
  4688. DP_TRACE(FATAL, "81-100 Packets: %u",
  4689. pdev->stats.rx_ind_histogram.pkts_81_100);
  4690. DP_TRACE(FATAL, "101-200 Packets: %u",
  4691. pdev->stats.rx_ind_histogram.pkts_101_200);
  4692. DP_TRACE(FATAL, " 201+ Packets: %u",
  4693. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4694. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4695. __func__,
  4696. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4697. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4698. pdev->soc->wlan_cfg_ctx->rx_hash,
  4699. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4700. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4701. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  4702. __func__,
  4703. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  4704. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  4705. #endif
  4706. }
  4707. }
  4708. /*
  4709. * dp_txrx_dump_stats() - Dump statistics
  4710. * @value - Statistics option
  4711. */
  4712. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value,
  4713. enum qdf_stats_verbosity_level level)
  4714. {
  4715. struct dp_soc *soc =
  4716. (struct dp_soc *)psoc;
  4717. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4718. if (!soc) {
  4719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4720. "%s: soc is NULL", __func__);
  4721. return QDF_STATUS_E_INVAL;
  4722. }
  4723. switch (value) {
  4724. case CDP_TXRX_PATH_STATS:
  4725. dp_txrx_path_stats(soc);
  4726. break;
  4727. case CDP_RX_RING_STATS:
  4728. dp_print_per_ring_stats(soc);
  4729. break;
  4730. case CDP_TXRX_TSO_STATS:
  4731. /* TODO: NOT IMPLEMENTED */
  4732. break;
  4733. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4734. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4735. break;
  4736. case CDP_DP_NAPI_STATS:
  4737. dp_print_napi_stats(soc);
  4738. break;
  4739. case CDP_TXRX_DESC_STATS:
  4740. /* TODO: NOT IMPLEMENTED */
  4741. break;
  4742. default:
  4743. status = QDF_STATUS_E_INVAL;
  4744. break;
  4745. }
  4746. return status;
  4747. }
  4748. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4749. /**
  4750. * dp_update_flow_control_parameters() - API to store datapath
  4751. * config parameters
  4752. * @soc: soc handle
  4753. * @cfg: ini parameter handle
  4754. *
  4755. * Return: void
  4756. */
  4757. static inline
  4758. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4759. struct cdp_config_params *params)
  4760. {
  4761. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4762. params->tx_flow_stop_queue_threshold;
  4763. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4764. params->tx_flow_start_queue_offset;
  4765. }
  4766. #else
  4767. static inline
  4768. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4769. struct cdp_config_params *params)
  4770. {
  4771. }
  4772. #endif
  4773. /**
  4774. * dp_update_config_parameters() - API to store datapath
  4775. * config parameters
  4776. * @soc: soc handle
  4777. * @cfg: ini parameter handle
  4778. *
  4779. * Return: status
  4780. */
  4781. static
  4782. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4783. struct cdp_config_params *params)
  4784. {
  4785. struct dp_soc *soc = (struct dp_soc *)psoc;
  4786. if (!(soc)) {
  4787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4788. "%s: Invalid handle", __func__);
  4789. return QDF_STATUS_E_INVAL;
  4790. }
  4791. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4792. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4793. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4794. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4795. params->tcp_udp_checksumoffload;
  4796. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4797. dp_update_flow_control_parameters(soc, params);
  4798. return QDF_STATUS_SUCCESS;
  4799. }
  4800. /**
  4801. * dp_txrx_set_wds_rx_policy() - API to store datapath
  4802. * config parameters
  4803. * @vdev_handle - datapath vdev handle
  4804. * @cfg: ini parameter handle
  4805. *
  4806. * Return: status
  4807. */
  4808. #ifdef WDS_VENDOR_EXTENSION
  4809. void
  4810. dp_txrx_set_wds_rx_policy(
  4811. struct cdp_vdev *vdev_handle,
  4812. u_int32_t val)
  4813. {
  4814. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4815. struct dp_peer *peer;
  4816. if (vdev->opmode == wlan_op_mode_ap) {
  4817. /* for ap, set it on bss_peer */
  4818. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  4819. if (peer->bss_peer) {
  4820. peer->wds_ecm.wds_rx_filter = 1;
  4821. peer->wds_ecm.wds_rx_ucast_4addr = (val & WDS_POLICY_RX_UCAST_4ADDR) ? 1:0;
  4822. peer->wds_ecm.wds_rx_mcast_4addr = (val & WDS_POLICY_RX_MCAST_4ADDR) ? 1:0;
  4823. break;
  4824. }
  4825. }
  4826. } else if (vdev->opmode == wlan_op_mode_sta) {
  4827. peer = TAILQ_FIRST(&vdev->peer_list);
  4828. peer->wds_ecm.wds_rx_filter = 1;
  4829. peer->wds_ecm.wds_rx_ucast_4addr = (val & WDS_POLICY_RX_UCAST_4ADDR) ? 1:0;
  4830. peer->wds_ecm.wds_rx_mcast_4addr = (val & WDS_POLICY_RX_MCAST_4ADDR) ? 1:0;
  4831. }
  4832. }
  4833. /**
  4834. * dp_txrx_peer_wds_tx_policy_update() - API to set tx wds policy
  4835. *
  4836. * @peer_handle - datapath peer handle
  4837. * @wds_tx_ucast: policy for unicast transmission
  4838. * @wds_tx_mcast: policy for multicast transmission
  4839. *
  4840. * Return: void
  4841. */
  4842. void
  4843. dp_txrx_peer_wds_tx_policy_update(struct cdp_peer *peer_handle,
  4844. int wds_tx_ucast, int wds_tx_mcast)
  4845. {
  4846. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4847. if (wds_tx_ucast || wds_tx_mcast) {
  4848. peer->wds_enabled = 1;
  4849. peer->wds_ecm.wds_tx_ucast_4addr = wds_tx_ucast;
  4850. peer->wds_ecm.wds_tx_mcast_4addr = wds_tx_mcast;
  4851. } else {
  4852. peer->wds_enabled = 0;
  4853. peer->wds_ecm.wds_tx_ucast_4addr = 0;
  4854. peer->wds_ecm.wds_tx_mcast_4addr = 0;
  4855. }
  4856. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4857. FL("Policy Update set to :\
  4858. peer->wds_enabled %d\
  4859. peer->wds_ecm.wds_tx_ucast_4addr %d\
  4860. peer->wds_ecm.wds_tx_mcast_4addr %d\n"),
  4861. peer->wds_enabled, peer->wds_ecm.wds_tx_ucast_4addr,
  4862. peer->wds_ecm.wds_tx_mcast_4addr);
  4863. return;
  4864. }
  4865. #endif
  4866. static struct cdp_wds_ops dp_ops_wds = {
  4867. .vdev_set_wds = dp_vdev_set_wds,
  4868. #ifdef WDS_VENDOR_EXTENSION
  4869. .txrx_set_wds_rx_policy = dp_txrx_set_wds_rx_policy,
  4870. .txrx_wds_peer_tx_policy_update = dp_txrx_peer_wds_tx_policy_update,
  4871. #endif
  4872. };
  4873. /*
  4874. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4875. * @soc - datapath soc handle
  4876. * @peer - datapath peer handle
  4877. *
  4878. * Delete the AST entries belonging to a peer
  4879. */
  4880. #ifdef FEATURE_WDS
  4881. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4882. struct dp_peer *peer)
  4883. {
  4884. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4885. qdf_spin_lock_bh(&soc->ast_lock);
  4886. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4887. if (ast_entry->next_hop) {
  4888. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4889. peer->vdev->pdev->osif_pdev,
  4890. ast_entry->mac_addr.raw);
  4891. }
  4892. dp_peer_del_ast(soc, ast_entry);
  4893. }
  4894. qdf_spin_unlock_bh(&soc->ast_lock);
  4895. }
  4896. #else
  4897. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4898. struct dp_peer *peer)
  4899. {
  4900. }
  4901. #endif
  4902. /*
  4903. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4904. * @vdev_handle - datapath vdev handle
  4905. * @callback - callback function
  4906. * @ctxt: callback context
  4907. *
  4908. */
  4909. static void
  4910. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4911. ol_txrx_data_tx_cb callback, void *ctxt)
  4912. {
  4913. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4914. vdev->tx_non_std_data_callback.func = callback;
  4915. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4916. }
  4917. #ifdef CONFIG_WIN
  4918. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4919. {
  4920. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4921. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4922. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4923. dp_peer_delete_ast_entries(soc, peer);
  4924. }
  4925. #endif
  4926. static struct cdp_cmn_ops dp_ops_cmn = {
  4927. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4928. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4929. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4930. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4931. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4932. .txrx_peer_create = dp_peer_create_wifi3,
  4933. .txrx_peer_setup = dp_peer_setup_wifi3,
  4934. #ifdef CONFIG_WIN
  4935. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4936. #else
  4937. .txrx_peer_teardown = NULL,
  4938. #endif
  4939. .txrx_peer_delete = dp_peer_delete_wifi3,
  4940. .txrx_vdev_register = dp_vdev_register_wifi3,
  4941. .txrx_soc_detach = dp_soc_detach_wifi3,
  4942. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4943. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4944. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4945. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4946. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4947. .delba_process = dp_delba_process_wifi3,
  4948. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4949. .flush_cache_rx_queue = NULL,
  4950. /* TODO: get API's for dscp-tid need to be added*/
  4951. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4952. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4953. .txrx_stats = dp_txrx_stats,
  4954. .txrx_stats_request = dp_txrx_stats_request,
  4955. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4956. .display_stats = dp_txrx_dump_stats,
  4957. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4958. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4959. #ifdef DP_INTR_POLL_BASED
  4960. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4961. #else
  4962. .txrx_intr_attach = dp_soc_interrupt_attach,
  4963. #endif
  4964. .txrx_intr_detach = dp_soc_interrupt_detach,
  4965. .set_pn_check = dp_set_pn_check_wifi3,
  4966. .update_config_parameters = dp_update_config_parameters,
  4967. /* TODO: Add other functions */
  4968. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4969. };
  4970. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4971. .txrx_peer_authorize = dp_peer_authorize,
  4972. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4973. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4974. #ifdef MESH_MODE_SUPPORT
  4975. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4976. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4977. #endif
  4978. .txrx_set_vdev_param = dp_set_vdev_param,
  4979. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4980. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4981. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4982. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4983. .txrx_update_filter_neighbour_peers =
  4984. dp_update_filter_neighbour_peers,
  4985. .txrx_get_sec_type = dp_get_sec_type,
  4986. /* TODO: Add other functions */
  4987. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4988. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4989. #ifdef WDI_EVENT_ENABLE
  4990. .txrx_get_pldev = dp_get_pldev,
  4991. #endif
  4992. .txrx_set_pdev_param = dp_set_pdev_param,
  4993. };
  4994. static struct cdp_me_ops dp_ops_me = {
  4995. #ifdef ATH_SUPPORT_IQUE
  4996. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4997. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4998. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4999. #endif
  5000. };
  5001. static struct cdp_mon_ops dp_ops_mon = {
  5002. .txrx_monitor_set_filter_ucast_data = NULL,
  5003. .txrx_monitor_set_filter_mcast_data = NULL,
  5004. .txrx_monitor_set_filter_non_data = NULL,
  5005. .txrx_monitor_get_filter_ucast_data = NULL,
  5006. .txrx_monitor_get_filter_mcast_data = NULL,
  5007. .txrx_monitor_get_filter_non_data = NULL,
  5008. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  5009. /* Added support for HK advance filter */
  5010. .txrx_set_advance_monitor_filter = dp_pdev_set_advance_monitor_filter,
  5011. };
  5012. static struct cdp_host_stats_ops dp_ops_host_stats = {
  5013. .txrx_per_peer_stats = dp_get_host_peer_stats,
  5014. .get_fw_peer_stats = dp_get_fw_peer_stats,
  5015. .get_htt_stats = dp_get_htt_stats,
  5016. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  5017. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  5018. /* TODO */
  5019. };
  5020. static struct cdp_raw_ops dp_ops_raw = {
  5021. /* TODO */
  5022. };
  5023. #ifdef CONFIG_WIN
  5024. static struct cdp_pflow_ops dp_ops_pflow = {
  5025. /* TODO */
  5026. };
  5027. #endif /* CONFIG_WIN */
  5028. #ifdef FEATURE_RUNTIME_PM
  5029. /**
  5030. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  5031. * @opaque_pdev: DP pdev context
  5032. *
  5033. * DP is ready to runtime suspend if there are no pending TX packets.
  5034. *
  5035. * Return: QDF_STATUS
  5036. */
  5037. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  5038. {
  5039. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  5040. struct dp_soc *soc = pdev->soc;
  5041. /* Call DP TX flow control API to check if there is any
  5042. pending packets */
  5043. if (soc->intr_mode == DP_INTR_POLL)
  5044. qdf_timer_stop(&soc->int_timer);
  5045. return QDF_STATUS_SUCCESS;
  5046. }
  5047. /**
  5048. * dp_runtime_resume() - ensure DP is ready to runtime resume
  5049. * @opaque_pdev: DP pdev context
  5050. *
  5051. * Resume DP for runtime PM.
  5052. *
  5053. * Return: QDF_STATUS
  5054. */
  5055. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  5056. {
  5057. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  5058. struct dp_soc *soc = pdev->soc;
  5059. void *hal_srng;
  5060. int i;
  5061. if (soc->intr_mode == DP_INTR_POLL)
  5062. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  5063. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  5064. hal_srng = soc->tcl_data_ring[i].hal_srng;
  5065. if (hal_srng) {
  5066. /* We actually only need to acquire the lock */
  5067. hal_srng_access_start(soc->hal_soc, hal_srng);
  5068. /* Update SRC ring head pointer for HW to send
  5069. all pending packets */
  5070. hal_srng_access_end(soc->hal_soc, hal_srng);
  5071. }
  5072. }
  5073. return QDF_STATUS_SUCCESS;
  5074. }
  5075. #endif /* FEATURE_RUNTIME_PM */
  5076. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  5077. {
  5078. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  5079. struct dp_soc *soc = pdev->soc;
  5080. if (soc->intr_mode == DP_INTR_POLL)
  5081. qdf_timer_stop(&soc->int_timer);
  5082. return QDF_STATUS_SUCCESS;
  5083. }
  5084. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  5085. {
  5086. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  5087. struct dp_soc *soc = pdev->soc;
  5088. if (soc->intr_mode == DP_INTR_POLL)
  5089. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  5090. return QDF_STATUS_SUCCESS;
  5091. }
  5092. #ifndef CONFIG_WIN
  5093. static struct cdp_misc_ops dp_ops_misc = {
  5094. .tx_non_std = dp_tx_non_std,
  5095. .get_opmode = dp_get_opmode,
  5096. #ifdef FEATURE_RUNTIME_PM
  5097. .runtime_suspend = dp_runtime_suspend,
  5098. .runtime_resume = dp_runtime_resume,
  5099. #endif /* FEATURE_RUNTIME_PM */
  5100. .pkt_log_init = dp_pkt_log_init,
  5101. .pkt_log_con_service = dp_pkt_log_con_service,
  5102. };
  5103. static struct cdp_flowctl_ops dp_ops_flowctl = {
  5104. /* WIFI 3.0 DP implement as required. */
  5105. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5106. .register_pause_cb = dp_txrx_register_pause_cb,
  5107. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  5108. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  5109. };
  5110. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  5111. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  5112. };
  5113. #ifdef IPA_OFFLOAD
  5114. static struct cdp_ipa_ops dp_ops_ipa = {
  5115. .ipa_get_resource = dp_ipa_get_resource,
  5116. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  5117. .ipa_op_response = dp_ipa_op_response,
  5118. .ipa_register_op_cb = dp_ipa_register_op_cb,
  5119. .ipa_get_stat = dp_ipa_get_stat,
  5120. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  5121. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  5122. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  5123. .ipa_setup = dp_ipa_setup,
  5124. .ipa_cleanup = dp_ipa_cleanup,
  5125. .ipa_setup_iface = dp_ipa_setup_iface,
  5126. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  5127. .ipa_enable_pipes = dp_ipa_enable_pipes,
  5128. .ipa_disable_pipes = dp_ipa_disable_pipes,
  5129. .ipa_set_perf_level = dp_ipa_set_perf_level
  5130. };
  5131. #endif
  5132. static struct cdp_bus_ops dp_ops_bus = {
  5133. .bus_suspend = dp_bus_suspend,
  5134. .bus_resume = dp_bus_resume
  5135. };
  5136. static struct cdp_ocb_ops dp_ops_ocb = {
  5137. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  5138. };
  5139. static struct cdp_throttle_ops dp_ops_throttle = {
  5140. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  5141. };
  5142. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  5143. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  5144. };
  5145. static struct cdp_cfg_ops dp_ops_cfg = {
  5146. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  5147. };
  5148. /*
  5149. * dp_wrapper_peer_get_ref_by_addr - wrapper function to get to peer
  5150. * @dev: physical device instance
  5151. * @peer_mac_addr: peer mac address
  5152. * @local_id: local id for the peer
  5153. * @debug_id: to track enum peer access
  5154. * Return: peer instance pointer
  5155. */
  5156. static inline void *
  5157. dp_wrapper_peer_get_ref_by_addr(struct cdp_pdev *dev, u8 *peer_mac_addr,
  5158. u8 *local_id,
  5159. enum peer_debug_id_type debug_id)
  5160. {
  5161. /*
  5162. * Currently this function does not implement the "get ref"
  5163. * functionality and is mapped to dp_find_peer_by_addr which does not
  5164. * increment the peer ref count. So the peer state is uncertain after
  5165. * calling this API. The functionality needs to be implemented.
  5166. * Accordingly the corresponding release_ref function is NULL.
  5167. */
  5168. return dp_find_peer_by_addr(dev, peer_mac_addr, local_id);
  5169. }
  5170. static struct cdp_peer_ops dp_ops_peer = {
  5171. .register_peer = dp_register_peer,
  5172. .clear_peer = dp_clear_peer,
  5173. .find_peer_by_addr = dp_find_peer_by_addr,
  5174. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  5175. .peer_get_ref_by_addr = dp_wrapper_peer_get_ref_by_addr,
  5176. .peer_release_ref = NULL,
  5177. .local_peer_id = dp_local_peer_id,
  5178. .peer_find_by_local_id = dp_peer_find_by_local_id,
  5179. .peer_state_update = dp_peer_state_update,
  5180. .get_vdevid = dp_get_vdevid,
  5181. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  5182. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  5183. .get_vdev_for_peer = dp_get_vdev_for_peer,
  5184. .get_peer_state = dp_get_peer_state,
  5185. .last_assoc_received = dp_get_last_assoc_received,
  5186. .last_disassoc_received = dp_get_last_disassoc_received,
  5187. .last_deauth_received = dp_get_last_deauth_received,
  5188. };
  5189. #endif
  5190. static struct cdp_ops dp_txrx_ops = {
  5191. .cmn_drv_ops = &dp_ops_cmn,
  5192. .ctrl_ops = &dp_ops_ctrl,
  5193. .me_ops = &dp_ops_me,
  5194. .mon_ops = &dp_ops_mon,
  5195. .host_stats_ops = &dp_ops_host_stats,
  5196. .wds_ops = &dp_ops_wds,
  5197. .raw_ops = &dp_ops_raw,
  5198. #ifdef CONFIG_WIN
  5199. .pflow_ops = &dp_ops_pflow,
  5200. #endif /* CONFIG_WIN */
  5201. #ifndef CONFIG_WIN
  5202. .misc_ops = &dp_ops_misc,
  5203. .cfg_ops = &dp_ops_cfg,
  5204. .flowctl_ops = &dp_ops_flowctl,
  5205. .l_flowctl_ops = &dp_ops_l_flowctl,
  5206. #ifdef IPA_OFFLOAD
  5207. .ipa_ops = &dp_ops_ipa,
  5208. #endif
  5209. .bus_ops = &dp_ops_bus,
  5210. .ocb_ops = &dp_ops_ocb,
  5211. .peer_ops = &dp_ops_peer,
  5212. .throttle_ops = &dp_ops_throttle,
  5213. .mob_stats_ops = &dp_ops_mob_stats,
  5214. #endif
  5215. };
  5216. /*
  5217. * dp_soc_set_txrx_ring_map()
  5218. * @dp_soc: DP handler for soc
  5219. *
  5220. * Return: Void
  5221. */
  5222. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  5223. {
  5224. uint32_t i;
  5225. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  5226. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  5227. }
  5228. }
  5229. /*
  5230. * dp_soc_attach_wifi3() - Attach txrx SOC
  5231. * @osif_soc: Opaque SOC handle from OSIF/HDD
  5232. * @htc_handle: Opaque HTC handle
  5233. * @hif_handle: Opaque HIF handle
  5234. * @qdf_osdev: QDF device
  5235. *
  5236. * Return: DP SOC handle on success, NULL on failure
  5237. */
  5238. /*
  5239. * Local prototype added to temporarily address warning caused by
  5240. * -Wmissing-prototypes. A more correct solution, namely to expose
  5241. * a prototype in an appropriate header file, will come later.
  5242. */
  5243. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  5244. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  5245. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  5246. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  5247. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  5248. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  5249. {
  5250. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  5251. if (!soc) {
  5252. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5253. FL("DP SOC memory allocation failed"));
  5254. goto fail0;
  5255. }
  5256. soc->cdp_soc.ops = &dp_txrx_ops;
  5257. soc->cdp_soc.ol_ops = ol_ops;
  5258. soc->osif_soc = osif_soc;
  5259. soc->osdev = qdf_osdev;
  5260. soc->hif_handle = hif_handle;
  5261. soc->psoc = psoc;
  5262. soc->hal_soc = hif_get_hal_handle(hif_handle);
  5263. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  5264. soc->hal_soc, qdf_osdev);
  5265. if (!soc->htt_handle) {
  5266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5267. FL("HTT attach failed"));
  5268. goto fail1;
  5269. }
  5270. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  5271. if (!soc->wlan_cfg_ctx) {
  5272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5273. FL("wlan_cfg_soc_attach failed"));
  5274. goto fail2;
  5275. }
  5276. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  5277. soc->cce_disable = false;
  5278. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  5279. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->osif_soc,
  5280. CDP_CFG_MAX_PEER_ID);
  5281. if (ret != -EINVAL) {
  5282. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  5283. }
  5284. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->osif_soc,
  5285. CDP_CFG_CCE_DISABLE);
  5286. if (ret)
  5287. soc->cce_disable = true;
  5288. }
  5289. qdf_spinlock_create(&soc->peer_ref_mutex);
  5290. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  5291. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  5292. /* fill the tx/rx cpu ring map*/
  5293. dp_soc_set_txrx_ring_map(soc);
  5294. qdf_spinlock_create(&soc->htt_stats.lock);
  5295. /* initialize work queue for stats processing */
  5296. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  5297. return (void *)soc;
  5298. fail2:
  5299. htt_soc_detach(soc->htt_handle);
  5300. fail1:
  5301. qdf_mem_free(soc);
  5302. fail0:
  5303. return NULL;
  5304. }
  5305. /*
  5306. * dp_get_pdev_for_mac_id() - Return pdev for mac_id
  5307. *
  5308. * @soc: handle to DP soc
  5309. * @mac_id: MAC id
  5310. *
  5311. * Return: Return pdev corresponding to MAC
  5312. */
  5313. void *dp_get_pdev_for_mac_id(struct dp_soc *soc, uint32_t mac_id)
  5314. {
  5315. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  5316. return soc->pdev_list[mac_id];
  5317. /* Typically for MCL as there only 1 PDEV*/
  5318. return soc->pdev_list[0];
  5319. }
  5320. /*
  5321. * dp_get_ring_id_for_mac_id() - Return pdev for mac_id
  5322. *
  5323. * @soc: handle to DP soc
  5324. * @mac_id: MAC id
  5325. *
  5326. * Return: ring id
  5327. */
  5328. int dp_get_ring_id_for_mac_id(struct dp_soc *soc, uint32_t mac_id)
  5329. {
  5330. /*
  5331. * Single pdev using both MACs will operate on both MAC rings,
  5332. * which is the case for MCL.
  5333. */
  5334. if (!wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  5335. return mac_id;
  5336. /* For WIN each PDEV will operate one ring, so index is zero. */
  5337. return 0;
  5338. }
  5339. /*
  5340. * dp_is_hw_dbs_enable() - Procedure to check if DBS is supported
  5341. * @soc: DP SoC context
  5342. * @max_mac_rings: No of MAC rings
  5343. *
  5344. * Return: None
  5345. */
  5346. static
  5347. void dp_is_hw_dbs_enable(struct dp_soc *soc,
  5348. int *max_mac_rings)
  5349. {
  5350. bool dbs_enable = false;
  5351. if (soc->cdp_soc.ol_ops->is_hw_dbs_2x2_capable)
  5352. dbs_enable = soc->cdp_soc.ol_ops->
  5353. is_hw_dbs_2x2_capable(soc->psoc);
  5354. *max_mac_rings = (dbs_enable)?(*max_mac_rings):1;
  5355. }
  5356. /*
  5357. * dp_set_pktlog_wifi3() - attach txrx vdev
  5358. * @pdev: Datapath PDEV handle
  5359. * @event: which event's notifications are being subscribed to
  5360. * @enable: WDI event subscribe or not. (True or False)
  5361. *
  5362. * Return: Success, NULL on failure
  5363. */
  5364. #ifdef WDI_EVENT_ENABLE
  5365. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  5366. bool enable)
  5367. {
  5368. struct dp_soc *soc = pdev->soc;
  5369. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  5370. int max_mac_rings = wlan_cfg_get_num_mac_rings
  5371. (pdev->wlan_cfg_ctx);
  5372. uint8_t mac_id = 0;
  5373. dp_is_hw_dbs_enable(soc, &max_mac_rings);
  5374. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  5375. FL("Max_mac_rings %d \n"),
  5376. max_mac_rings);
  5377. if (enable) {
  5378. switch (event) {
  5379. case WDI_EVENT_RX_DESC:
  5380. if (pdev->monitor_vdev) {
  5381. /* Nothing needs to be done if monitor mode is
  5382. * enabled
  5383. */
  5384. return 0;
  5385. }
  5386. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  5387. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  5388. htt_tlv_filter.mpdu_start = 1;
  5389. htt_tlv_filter.msdu_start = 1;
  5390. htt_tlv_filter.msdu_end = 1;
  5391. htt_tlv_filter.mpdu_end = 1;
  5392. htt_tlv_filter.packet_header = 1;
  5393. htt_tlv_filter.attention = 1;
  5394. htt_tlv_filter.ppdu_start = 1;
  5395. htt_tlv_filter.ppdu_end = 1;
  5396. htt_tlv_filter.ppdu_end_user_stats = 1;
  5397. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5398. htt_tlv_filter.ppdu_end_status_done = 1;
  5399. htt_tlv_filter.enable_fp = 1;
  5400. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  5401. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  5402. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  5403. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  5404. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  5405. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  5406. for (mac_id = 0; mac_id < max_mac_rings;
  5407. mac_id++) {
  5408. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5409. pdev->pdev_id + mac_id,
  5410. pdev->rxdma_mon_status_ring
  5411. .hal_srng,
  5412. RXDMA_MONITOR_STATUS,
  5413. RX_BUFFER_SIZE,
  5414. &htt_tlv_filter);
  5415. }
  5416. if (soc->reap_timer_init)
  5417. qdf_timer_mod(&soc->mon_reap_timer,
  5418. DP_INTR_POLL_TIMER_MS);
  5419. }
  5420. break;
  5421. case WDI_EVENT_LITE_RX:
  5422. if (pdev->monitor_vdev) {
  5423. /* Nothing needs to be done if monitor mode is
  5424. * enabled
  5425. */
  5426. return 0;
  5427. }
  5428. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  5429. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  5430. htt_tlv_filter.ppdu_start = 1;
  5431. htt_tlv_filter.ppdu_end = 1;
  5432. htt_tlv_filter.ppdu_end_user_stats = 1;
  5433. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5434. htt_tlv_filter.ppdu_end_status_done = 1;
  5435. htt_tlv_filter.mpdu_start = 1;
  5436. htt_tlv_filter.enable_fp = 1;
  5437. htt_tlv_filter.fp_mgmt_filter = FILTER_MGMT_ALL;
  5438. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_ALL;
  5439. htt_tlv_filter.fp_data_filter = FILTER_DATA_ALL;
  5440. htt_tlv_filter.mo_mgmt_filter = FILTER_MGMT_ALL;
  5441. htt_tlv_filter.mo_ctrl_filter = FILTER_CTRL_ALL;
  5442. htt_tlv_filter.mo_data_filter = FILTER_DATA_ALL;
  5443. for (mac_id = 0; mac_id < max_mac_rings;
  5444. mac_id++) {
  5445. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5446. pdev->pdev_id + mac_id,
  5447. pdev->rxdma_mon_status_ring
  5448. .hal_srng,
  5449. RXDMA_MONITOR_STATUS,
  5450. RX_BUFFER_SIZE_PKTLOG_LITE,
  5451. &htt_tlv_filter);
  5452. }
  5453. if (soc->reap_timer_init)
  5454. qdf_timer_mod(&soc->mon_reap_timer,
  5455. DP_INTR_POLL_TIMER_MS);
  5456. }
  5457. break;
  5458. case WDI_EVENT_LITE_T2H:
  5459. if (pdev->monitor_vdev) {
  5460. /* Nothing needs to be done if monitor mode is
  5461. * enabled
  5462. */
  5463. return 0;
  5464. }
  5465. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5466. * passing value 0xffff. Once these macros will define
  5467. * in htt header file will use proper macros
  5468. */
  5469. for (mac_id = 0; mac_id < max_mac_rings; mac_id++) {
  5470. dp_h2t_cfg_stats_msg_send(pdev, 0xffff,
  5471. pdev->pdev_id + mac_id);
  5472. }
  5473. break;
  5474. default:
  5475. /* Nothing needs to be done for other pktlog types */
  5476. break;
  5477. }
  5478. } else {
  5479. switch (event) {
  5480. case WDI_EVENT_RX_DESC:
  5481. case WDI_EVENT_LITE_RX:
  5482. if (pdev->monitor_vdev) {
  5483. /* Nothing needs to be done if monitor mode is
  5484. * enabled
  5485. */
  5486. return 0;
  5487. }
  5488. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  5489. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  5490. for (mac_id = 0; mac_id < max_mac_rings;
  5491. mac_id++) {
  5492. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5493. pdev->pdev_id + mac_id,
  5494. pdev->rxdma_mon_status_ring
  5495. .hal_srng,
  5496. RXDMA_MONITOR_STATUS,
  5497. RX_BUFFER_SIZE,
  5498. &htt_tlv_filter);
  5499. }
  5500. if (soc->reap_timer_init)
  5501. qdf_timer_stop(&soc->mon_reap_timer);
  5502. }
  5503. break;
  5504. case WDI_EVENT_LITE_T2H:
  5505. if (pdev->monitor_vdev) {
  5506. /* Nothing needs to be done if monitor mode is
  5507. * enabled
  5508. */
  5509. return 0;
  5510. }
  5511. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5512. * passing value 0. Once these macros will define in htt
  5513. * header file will use proper macros
  5514. */
  5515. for (mac_id = 0; mac_id < max_mac_rings; mac_id++) {
  5516. dp_h2t_cfg_stats_msg_send(pdev, 0,
  5517. pdev->pdev_id + mac_id);
  5518. }
  5519. break;
  5520. default:
  5521. /* Nothing needs to be done for other pktlog types */
  5522. break;
  5523. }
  5524. }
  5525. return 0;
  5526. }
  5527. #endif
  5528. #ifdef CONFIG_MCL
  5529. /*
  5530. * dp_service_mon_rings()- timer to reap monitor rings
  5531. * reqd as we are not getting ppdu end interrupts
  5532. * @arg: SoC Handle
  5533. *
  5534. * Return:
  5535. *
  5536. */
  5537. static void dp_service_mon_rings(void *arg)
  5538. {
  5539. struct dp_soc *soc = (struct dp_soc *) arg;
  5540. int ring = 0, work_done;
  5541. work_done = dp_mon_process(soc, ring, QCA_NAPI_BUDGET);
  5542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  5543. FL("Reaped %d descs from Monitor rings"), work_done);
  5544. qdf_timer_mod(&soc->mon_reap_timer, DP_INTR_POLL_TIMER_MS);
  5545. }
  5546. #ifndef REMOVE_PKT_LOG
  5547. /**
  5548. * dp_pkt_log_init() - API to initialize packet log
  5549. * @ppdev: physical device handle
  5550. * @scn: HIF context
  5551. *
  5552. * Return: none
  5553. */
  5554. void dp_pkt_log_init(struct cdp_pdev *ppdev, void *scn)
  5555. {
  5556. struct dp_pdev *handle = (struct dp_pdev *)ppdev;
  5557. if (handle->pkt_log_init) {
  5558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5559. "%s: Packet log not initialized", __func__);
  5560. return;
  5561. }
  5562. pktlog_sethandle(&handle->pl_dev, scn);
  5563. pktlog_set_callback_regtype(PKTLOG_LITE_CALLBACK_REGISTRATION);
  5564. if (pktlogmod_init(scn)) {
  5565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5566. "%s: pktlogmod_init failed", __func__);
  5567. handle->pkt_log_init = false;
  5568. } else {
  5569. handle->pkt_log_init = true;
  5570. }
  5571. }
  5572. /**
  5573. * dp_pkt_log_con_service() - connect packet log service
  5574. * @ppdev: physical device handle
  5575. * @scn: device context
  5576. *
  5577. * Return: none
  5578. */
  5579. static void dp_pkt_log_con_service(struct cdp_pdev *ppdev, void *scn)
  5580. {
  5581. struct dp_pdev *pdev = (struct dp_pdev *)ppdev;
  5582. dp_pkt_log_init((struct cdp_pdev *)pdev, scn);
  5583. pktlog_htc_attach();
  5584. }
  5585. /**
  5586. * dp_pktlogmod_exit() - API to cleanup pktlog info
  5587. * @handle: Pdev handle
  5588. *
  5589. * Return: none
  5590. */
  5591. static void dp_pktlogmod_exit(struct dp_pdev *handle)
  5592. {
  5593. void *scn = (void *)handle->soc->hif_handle;
  5594. if (!scn) {
  5595. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5596. "%s: Invalid hif(scn) handle", __func__);
  5597. return;
  5598. }
  5599. pktlogmod_exit(scn);
  5600. handle->pkt_log_init = false;
  5601. }
  5602. #endif
  5603. #else
  5604. static void dp_pktlogmod_exit(struct dp_pdev *handle) { }
  5605. #endif