hal_be_generic_api.h 116 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include "txmon_tlvs.h"
  27. /*
  28. * Debug macro to print the TLV header tag
  29. */
  30. #define SHOW_DEFINED(x) do {} while (0)
  31. #if defined(QCA_MONITOR_2_0_SUPPORT) && !defined(TX_MONITOR_WORD_MASK)
  32. typedef struct tx_fes_setup hal_tx_fes_setup_t;
  33. typedef struct tx_peer_entry hal_tx_peer_entry_t;
  34. typedef struct tx_queue_extension hal_tx_queue_ext_t;
  35. typedef struct tx_msdu_start hal_tx_msdu_start_t;
  36. typedef struct tx_mpdu_start hal_tx_mpdu_start_t;
  37. typedef struct tx_fes_status_end hal_tx_fes_status_end_t;
  38. typedef struct response_end_status hal_response_end_status_t;
  39. typedef struct tx_fes_status_prot hal_tx_fes_status_prot_t;
  40. typedef struct pcu_ppdu_setup_init hal_pcu_ppdu_setup_t;
  41. #endif
  42. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  43. static inline void
  44. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  45. struct hal_tx_completion_status *ts)
  46. {
  47. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  48. BUFFER_TIMESTAMP);
  49. }
  50. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  51. static inline void
  52. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  53. struct hal_tx_completion_status *ts)
  54. {
  55. }
  56. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  57. /**
  58. * hal_tx_comp_get_status_generic_be() - TQM Release reason
  59. * @desc: WBM descriptor
  60. * @ts1: completion ring Tx status
  61. * @hal: hal_soc
  62. *
  63. * This function will parse the WBM completion descriptor and populate in
  64. * HAL structure
  65. *
  66. * Return: none
  67. */
  68. static inline void
  69. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  70. struct hal_soc *hal)
  71. {
  72. uint8_t rate_stats_valid = 0;
  73. uint32_t rate_stats = 0;
  74. struct hal_tx_completion_status *ts =
  75. (struct hal_tx_completion_status *)ts1;
  76. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  77. TQM_STATUS_NUMBER);
  78. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  79. ACK_FRAME_RSSI);
  80. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  81. FIRST_MSDU);
  82. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  83. LAST_MSDU);
  84. #if 0
  85. // TODO - This has to be calculated form first and last msdu
  86. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  87. WBM2SW_COMPLETION_RING_TX,
  88. MSDU_PART_OF_AMSDU);
  89. #endif
  90. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  91. SW_PEER_ID);
  92. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  93. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  94. TRANSMIT_COUNT);
  95. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  96. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  97. TX_RATE_STATS_INFO_VALID, rate_stats);
  98. ts->valid = rate_stats_valid;
  99. if (rate_stats_valid) {
  100. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  101. rate_stats);
  102. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  103. TRANSMIT_PKT_TYPE, rate_stats);
  104. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  105. TRANSMIT_STBC, rate_stats);
  106. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  107. rate_stats);
  108. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  109. rate_stats);
  110. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  111. rate_stats);
  112. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  113. rate_stats);
  114. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  115. rate_stats);
  116. }
  117. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  118. ts->status = hal_tx_comp_get_release_reason(
  119. desc,
  120. hal_soc_to_hal_soc_handle(hal));
  121. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  122. TX_RATE_STATS_INFO_TX_RATE_STATS);
  123. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  124. }
  125. /**
  126. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  127. * @soc: HAL SoC context
  128. * @map: PCP-TID mapping table
  129. *
  130. * PCP are mapped to 8 TID values using TID values programmed
  131. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  132. * The mapping register has TID mapping for 8 PCP values
  133. *
  134. * Return: none
  135. */
  136. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  137. {
  138. uint32_t addr, value;
  139. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  140. MAC_TCL_REG_REG_BASE);
  141. value = (map[0] |
  142. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  143. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  144. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  145. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  146. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  147. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  148. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  149. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  150. }
  151. /**
  152. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  153. * value received from user-space
  154. * @soc: HAL SoC context
  155. * @pcp: pcp value
  156. * @tid : tid value
  157. *
  158. * Return: void
  159. */
  160. static void
  161. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  162. uint8_t pcp, uint8_t tid)
  163. {
  164. uint32_t addr, value, regval;
  165. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  166. MAC_TCL_REG_REG_BASE);
  167. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  168. /* Read back previous PCP TID config and update
  169. * with new config.
  170. */
  171. regval = HAL_REG_READ(soc, addr);
  172. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  173. regval |= value;
  174. HAL_REG_WRITE(soc, addr,
  175. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  176. }
  177. /**
  178. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  179. * @soc: HAL SoC context
  180. * @value: priority value
  181. *
  182. * Return: void
  183. */
  184. static
  185. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  186. {
  187. uint32_t addr;
  188. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  189. MAC_TCL_REG_REG_BASE);
  190. HAL_REG_WRITE(soc, addr,
  191. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  192. }
  193. /**
  194. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  195. * @rx_pkt_tlv_size: TLV size for regular RX packets
  196. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  197. *
  198. * Return: size of rx pkt tlv before the actual data
  199. */
  200. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  201. uint16_t *rx_mon_pkt_tlv_size)
  202. {
  203. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  204. /* For now mon pkt tlv is same as rx pkt tlv */
  205. *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN;
  206. }
  207. /**
  208. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  209. * @rx_fst: Pointer to the Rx Flow Search Table
  210. * @hal_hash: HAL 5 tuple hash
  211. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  212. *
  213. * Return: Success/Failure
  214. */
  215. static void *
  216. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  217. uint8_t *flow_tuple_info)
  218. {
  219. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  220. void *hal_fse = NULL;
  221. struct hal_flow_tuple_info *tuple_info
  222. = (struct hal_flow_tuple_info *)flow_tuple_info;
  223. hal_fse = (uint8_t *)fst->base_vaddr +
  224. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  225. if (!hal_fse || !tuple_info)
  226. return NULL;
  227. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  228. return NULL;
  229. tuple_info->src_ip_127_96 =
  230. qdf_ntohl(HAL_GET_FLD(hal_fse,
  231. RX_FLOW_SEARCH_ENTRY,
  232. SRC_IP_127_96));
  233. tuple_info->src_ip_95_64 =
  234. qdf_ntohl(HAL_GET_FLD(hal_fse,
  235. RX_FLOW_SEARCH_ENTRY,
  236. SRC_IP_95_64));
  237. tuple_info->src_ip_63_32 =
  238. qdf_ntohl(HAL_GET_FLD(hal_fse,
  239. RX_FLOW_SEARCH_ENTRY,
  240. SRC_IP_63_32));
  241. tuple_info->src_ip_31_0 =
  242. qdf_ntohl(HAL_GET_FLD(hal_fse,
  243. RX_FLOW_SEARCH_ENTRY,
  244. SRC_IP_31_0));
  245. tuple_info->dest_ip_127_96 =
  246. qdf_ntohl(HAL_GET_FLD(hal_fse,
  247. RX_FLOW_SEARCH_ENTRY,
  248. DEST_IP_127_96));
  249. tuple_info->dest_ip_95_64 =
  250. qdf_ntohl(HAL_GET_FLD(hal_fse,
  251. RX_FLOW_SEARCH_ENTRY,
  252. DEST_IP_95_64));
  253. tuple_info->dest_ip_63_32 =
  254. qdf_ntohl(HAL_GET_FLD(hal_fse,
  255. RX_FLOW_SEARCH_ENTRY,
  256. DEST_IP_63_32));
  257. tuple_info->dest_ip_31_0 =
  258. qdf_ntohl(HAL_GET_FLD(hal_fse,
  259. RX_FLOW_SEARCH_ENTRY,
  260. DEST_IP_31_0));
  261. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  262. RX_FLOW_SEARCH_ENTRY,
  263. DEST_PORT);
  264. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  265. RX_FLOW_SEARCH_ENTRY,
  266. SRC_PORT);
  267. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  268. RX_FLOW_SEARCH_ENTRY,
  269. L4_PROTOCOL);
  270. return hal_fse;
  271. }
  272. /**
  273. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  274. * @rx_fst: Pointer to the Rx Flow Search Table
  275. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  276. *
  277. * Return: Success/Failure
  278. */
  279. static QDF_STATUS
  280. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  281. {
  282. uint8_t *fse = (uint8_t *)hal_rx_fse;
  283. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  284. return QDF_STATUS_E_NOENT;
  285. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  286. return QDF_STATUS_SUCCESS;
  287. }
  288. /**
  289. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  290. *
  291. * Return: size of each entry/flow in Rx FST
  292. */
  293. static inline uint32_t
  294. hal_rx_fst_get_fse_size_be(void)
  295. {
  296. return HAL_RX_FST_ENTRY_SIZE;
  297. }
  298. /*
  299. * TX MONITOR
  300. */
  301. #ifdef QCA_MONITOR_2_0_SUPPORT
  302. /**
  303. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  304. * @tx_tlv_hdr: pointer to TLV header
  305. *
  306. * Return: bool based on tlv tag matches monitor buffer address tlv
  307. */
  308. static inline bool
  309. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  310. {
  311. uint32_t tlv_tag;
  312. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  313. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  314. return true;
  315. return false;
  316. }
  317. /**
  318. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  319. * @tx_tlv: pointer to TLV header
  320. * @packet_info: place holder for packet info
  321. *
  322. * Return: Address to void
  323. */
  324. static inline void
  325. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  326. {
  327. struct hal_mon_packet_info *pkt_info;
  328. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  329. pkt_info = (struct hal_mon_packet_info *)packet_info;
  330. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  331. (addr->buffer_virt_addr_31_0));
  332. pkt_info->dma_length = addr->dma_length + 1;
  333. pkt_info->msdu_continuation = addr->msdu_continuation;
  334. pkt_info->truncated = addr->truncated;
  335. }
  336. /**
  337. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  338. *
  339. * @tx_tlv: pointer to tx_fes_setup tlv header
  340. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  341. *
  342. * Return: void
  343. */
  344. static inline void
  345. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  346. struct hal_tx_ppdu_info *tx_ppdu_info)
  347. {
  348. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  349. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  350. if (tx_ppdu_info->num_users == 0)
  351. tx_ppdu_info->num_users = 1;
  352. TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  353. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  354. }
  355. /**
  356. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  357. *
  358. * @tx_tlv: pointer to tx_fes_setup tlv header
  359. *
  360. * Return: number of users
  361. */
  362. static inline uint8_t
  363. hal_txmon_get_num_users(void *tx_tlv)
  364. {
  365. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  366. return tx_fes_setup->number_of_users;
  367. }
  368. /**
  369. * hal_txmon_parse_tx_fes_status_end() - parse tx_fes_status_end tlv
  370. *
  371. * @tx_tlv: pointer to tx_fes_status_end tlv header
  372. * @ppdu_info: pointer to hal_tx_ppdu_info
  373. * @tx_status_info: pointer to hal_tx_status_info
  374. *
  375. * Return: void
  376. */
  377. static inline void
  378. hal_txmon_parse_tx_fes_status_end(void *tx_tlv,
  379. struct hal_tx_ppdu_info *ppdu_info,
  380. struct hal_tx_status_info *tx_status_info)
  381. {
  382. hal_tx_fes_status_end_t *tx_fes_end = (hal_tx_fes_status_end_t *)tx_tlv;
  383. if (tx_fes_end->phytx_abort_request_info_valid) {
  384. TXMON_STATUS_INFO(tx_status_info, phy_abort_reason) =
  385. tx_fes_end->phytx_abort_request_info_details.phytx_abort_reason;
  386. TXMON_STATUS_INFO(tx_status_info, phy_abort_user_number) =
  387. tx_fes_end->phytx_abort_request_info_details.user_number;
  388. }
  389. TXMON_STATUS_INFO(tx_status_info,
  390. response_type) = tx_fes_end->response_type;
  391. TXMON_STATUS_INFO(tx_status_info,
  392. r2r_to_follow) = tx_fes_end->r2r_end_status_to_follow;
  393. /* update phy timestamp to ppdu timestamp */
  394. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  395. (tx_fes_end->start_of_frame_timestamp_15_0 |
  396. tx_fes_end->start_of_frame_timestamp_31_16 <<
  397. HAL_TX_LSB(TX_FES_STATUS_END, START_OF_FRAME_TIMESTAMP_31_16));
  398. }
  399. /**
  400. * hal_txmon_parse_response_end_status() - parse response_end_status tlv
  401. *
  402. * @tx_tlv: pointer to response_end_status tlv header
  403. * @ppdu_info: pointer to hal_tx_ppdu_info
  404. * @tx_status_info: pointer to hal_tx_status_info
  405. *
  406. * Return: void
  407. */
  408. static inline void
  409. hal_txmon_parse_response_end_status(void *tx_tlv,
  410. struct hal_tx_ppdu_info *ppdu_info,
  411. struct hal_tx_status_info *tx_status_info)
  412. {
  413. hal_response_end_status_t *resp_end_status = NULL;
  414. resp_end_status = (hal_response_end_status_t *)tx_tlv;
  415. TXMON_HAL_STATUS(ppdu_info, bw) = resp_end_status->coex_based_tx_bw;
  416. TXMON_STATUS_INFO(tx_status_info, generated_response) =
  417. resp_end_status->generated_response;
  418. TXMON_STATUS_INFO(tx_status_info, mba_count) =
  419. resp_end_status->mba_user_count;
  420. TXMON_STATUS_INFO(tx_status_info, mba_fake_bitmap_count) =
  421. resp_end_status->mba_fake_bitmap_count;
  422. }
  423. /**
  424. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  425. *
  426. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  427. * @data_status_info: pointer to data hal_tx_status_info
  428. * @prot_status_info: pointer to protection hal_tx_status_info
  429. *
  430. * Return: void
  431. */
  432. static inline void
  433. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  434. struct hal_tx_status_info *data_status_info,
  435. struct hal_tx_status_info *prot_status_info)
  436. {
  437. hal_pcu_ppdu_setup_t *pcu_init = (hal_pcu_ppdu_setup_t *)tx_tlv;
  438. prot_status_info->protection_addr =
  439. pcu_init->use_address_fields_for_protection;
  440. /* protection frame address 1 */
  441. *(uint32_t *)&prot_status_info->addr1[0] =
  442. pcu_init->protection_frame_ad1_31_0;
  443. *(uint32_t *)&prot_status_info->addr1[4] =
  444. pcu_init->protection_frame_ad1_47_32;
  445. /* protection frame address 2 */
  446. *(uint32_t *)&prot_status_info->addr2[0] =
  447. pcu_init->protection_frame_ad2_15_0;
  448. *(uint32_t *)&prot_status_info->addr2[2] =
  449. pcu_init->protection_frame_ad2_47_16;
  450. /* protection frame address 3 */
  451. *(uint32_t *)&prot_status_info->addr3[0] =
  452. pcu_init->protection_frame_ad3_31_0;
  453. *(uint32_t *)&prot_status_info->addr3[4] =
  454. pcu_init->protection_frame_ad3_47_32;
  455. /* protection frame address 4 */
  456. *(uint32_t *)&prot_status_info->addr4[0] =
  457. pcu_init->protection_frame_ad4_15_0;
  458. *(uint32_t *)&prot_status_info->addr4[2] =
  459. pcu_init->protection_frame_ad4_47_16;
  460. }
  461. /**
  462. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  463. *
  464. * @tx_tlv: pointer to peer_entry tlv header
  465. * @user_id: user_id
  466. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  467. * @tx_status_info: pointer to hal_tx_status_info
  468. *
  469. * Return: void
  470. */
  471. static inline void
  472. hal_txmon_parse_peer_entry(void *tx_tlv,
  473. uint8_t user_id,
  474. struct hal_tx_ppdu_info *tx_ppdu_info,
  475. struct hal_tx_status_info *tx_status_info)
  476. {
  477. hal_tx_peer_entry_t *peer_entry = (hal_tx_peer_entry_t *)tx_tlv;
  478. *(uint32_t *)&tx_status_info->addr1[0] =
  479. peer_entry->mac_addr_a_31_0;
  480. *(uint32_t *)&tx_status_info->addr1[4] =
  481. peer_entry->mac_addr_a_47_32;
  482. *(uint32_t *)&tx_status_info->addr2[0] =
  483. peer_entry->mac_addr_b_15_0;
  484. *(uint32_t *)&tx_status_info->addr2[2] =
  485. peer_entry->mac_addr_b_47_16;
  486. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  487. peer_entry->sw_peer_id;
  488. }
  489. /**
  490. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  491. *
  492. * @tx_tlv: pointer to queue exten tlv header
  493. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  494. *
  495. * Return: void
  496. */
  497. static inline void
  498. hal_txmon_parse_queue_exten(void *tx_tlv,
  499. struct hal_tx_ppdu_info *tx_ppdu_info)
  500. {
  501. hal_tx_queue_ext_t *queue_ext = (hal_tx_queue_ext_t *)tx_tlv;
  502. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = queue_ext->frame_ctl;
  503. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  504. }
  505. /**
  506. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  507. *
  508. * @tx_tlv: pointer to mpdu start tlv header
  509. * @user_id: user id
  510. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  511. *
  512. * Return: void
  513. */
  514. static inline void
  515. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  516. struct hal_tx_ppdu_info *tx_ppdu_info)
  517. {
  518. hal_tx_mpdu_start_t *mpdu_start = (hal_tx_mpdu_start_t *)tx_tlv;
  519. TXMON_HAL_USER(tx_ppdu_info, user_id, start_seq) =
  520. mpdu_start->mpdu_sequence_number;
  521. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  522. }
  523. /**
  524. * hal_txmon_parse_msdu_start() - parse msdu start tlv
  525. *
  526. * @tx_tlv: pointer to msdu start tlv header
  527. * @user_id: user id
  528. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  529. *
  530. * Return: void
  531. */
  532. static inline void
  533. hal_txmon_parse_msdu_start(void *tx_tlv, uint8_t user_id,
  534. struct hal_tx_ppdu_info *tx_ppdu_info)
  535. {
  536. }
  537. /**
  538. * hal_txmon_parse_tx_fes_status_prot() - parse tx_fes_status_prot tlv
  539. *
  540. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  541. * @ppdu_info: pointer to hal_tx_ppdu_info
  542. * @tx_status_info: pointer to hal_tx_status_info
  543. *
  544. * Return: void
  545. */
  546. static inline void
  547. hal_txmon_parse_tx_fes_status_prot(void *tx_tlv,
  548. struct hal_tx_ppdu_info *ppdu_info,
  549. struct hal_tx_status_info *tx_status_info)
  550. {
  551. hal_tx_fes_status_prot_t *fes_prot = (hal_tx_fes_status_prot_t *)tx_tlv;
  552. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  553. (fes_prot->start_of_frame_timestamp_15_0 |
  554. fes_prot->start_of_frame_timestamp_31_16 << 15);
  555. }
  556. /**
  557. * get_ru_offset_from_start_index() - api to get ru offset from ru index
  558. *
  559. * @ru_size: RU size
  560. * @start_idx: Start index
  561. *
  562. * Return: uint8_t ru allocation offset
  563. */
  564. static inline
  565. uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx)
  566. {
  567. uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = {
  568. {0, 0, 0, 0, 0, 0, 0},
  569. {1, 0, 0, 0, 0, 0, 0},
  570. {2, 1, 0, 0, 0, 0, 0},
  571. {3, 1, 0, 0, 0, 0, 0},
  572. {4, 0, 0, 0, 0, 0, 0},
  573. {5, 2, 1, 0, 0, 0, 0},
  574. {6, 2, 1, 0, 0, 0, 0},
  575. {7, 3, 1, 0, 0, 0, 0},
  576. {8, 3, 1, 0, 0, 0, 0},
  577. {9, 4, 2, 1, 0, 0, 0},
  578. {10, 4, 2, 1, 0, 0, 0},
  579. {11, 5, 2, 1, 0, 0, 0},
  580. {12, 5, 2, 1, 0, 0, 0},
  581. {13, 0, 0, 1, 0, 0, 0},
  582. {14, 6, 3, 1, 0, 0, 0},
  583. {15, 6, 3, 1, 0, 0, 0},
  584. {16, 7, 3, 1, 0, 0, 0},
  585. {17, 7, 3, 1, 0, 0, 0},
  586. {18, 0, 0, 0, 0, 0, 0},
  587. {19, 8, 4, 2, 1, 0, 0},
  588. {20, 8, 4, 2, 1, 0, 0},
  589. {21, 9, 4, 2, 1, 0, 0},
  590. {22, 9, 4, 2, 1, 0, 0},
  591. {23, 0, 0, 2, 1, 0, 0},
  592. {24, 10, 5, 2, 1, 0, 0},
  593. {25, 10, 5, 2, 1, 0, 0},
  594. {26, 11, 5, 2, 1, 0, 0},
  595. {27, 11, 5, 2, 1, 0, 0},
  596. {28, 12, 6, 3, 1, 0, 0},
  597. {29, 12, 6, 3, 1, 0, 0},
  598. {30, 13, 6, 3, 1, 0, 0},
  599. {31, 13, 6, 3, 1, 0, 0},
  600. {32, 0, 0, 3, 1, 0, 0},
  601. {33, 14, 7, 3, 1, 0, 0},
  602. {34, 14, 7, 3, 1, 0, 0},
  603. {35, 15, 7, 3, 1, 0, 0},
  604. {36, 15, 7, 3, 1, 0, 0},
  605. };
  606. if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX)
  607. return 0;
  608. return ru_alloc_offset[start_idx][ru_size];
  609. }
  610. /**
  611. * hal_txmon_parse_fw2sw() - parse firmware to software tlv
  612. *
  613. * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header
  614. * @type: place where this tlv is generated
  615. * @status_info: pointer to hal_tx_status_info
  616. *
  617. * Return: void
  618. */
  619. static inline void
  620. hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type,
  621. struct hal_tx_status_info *status_info)
  622. {
  623. uint32_t *msg = (uint32_t *)tx_tlv;
  624. switch (type) {
  625. case TXMON_FW2SW_TYPE_FES_SETUP:
  626. {
  627. uint32_t schedule_id;
  628. uint16_t c_freq1;
  629. uint16_t c_freq2;
  630. uint16_t freq_mhz;
  631. uint8_t phy_mode;
  632. c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg);
  633. c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg);
  634. msg++;
  635. phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg);
  636. freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg);
  637. msg++;
  638. schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg);
  639. TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1;
  640. TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2;
  641. TXMON_STATUS_INFO(status_info, freq) = freq_mhz;
  642. TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode;
  643. TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id;
  644. break;
  645. }
  646. case TXMON_FW2SW_TYPE_FES_SETUP_USER:
  647. {
  648. break;
  649. }
  650. case TXMON_FW2SW_TYPE_FES_SETUP_EXT:
  651. {
  652. break;
  653. }
  654. };
  655. }
  656. /**
  657. * hal_txmon_parse_u_sig_hdr() - parse u_sig header information from tlv
  658. *
  659. * @tx_tlv: pointer to mactx_u_sig_eht_su_mu/tb tlv
  660. * @ppdu_info: pointer to hal_tx_ppdu_info
  661. *
  662. * Return: void
  663. */
  664. static inline void
  665. hal_txmon_parse_u_sig_hdr(void *tx_tlv, struct hal_tx_ppdu_info *ppdu_info)
  666. {
  667. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)tx_tlv;
  668. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  669. uint8_t bad_usig_crc;
  670. bad_usig_crc = HAL_TX_DESC_GET_64(tx_tlv,
  671. MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS,
  672. CRC) ? 0 : 1;
  673. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  674. QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN |
  675. QDF_MON_STATUS_USIG_BW_KNOWN |
  676. QDF_MON_STATUS_USIG_UL_DL_KNOWN |
  677. QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN |
  678. QDF_MON_STATUS_USIG_TXOP_KNOWN;
  679. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  680. (usig_1->phy_version <<
  681. QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT);
  682. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  683. (usig_1->bw << QDF_MON_STATUS_USIG_BW_SHIFT);
  684. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  685. (usig_1->ul_dl << QDF_MON_STATUS_USIG_UL_DL_SHIFT);
  686. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  687. (usig_1->bss_color <<
  688. QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT);
  689. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  690. (usig_1->txop << QDF_MON_STATUS_USIG_TXOP_SHIFT);
  691. TXMON_HAL_STATUS(ppdu_info, usig_common) |= bad_usig_crc;
  692. TXMON_HAL_STATUS(ppdu_info, bw) = usig_1->bw;
  693. TXMON_HAL_STATUS(ppdu_info, usig_flags) = 1;
  694. }
  695. /**
  696. * hal_txmon_populate_he_data_per_user() - populate he data per user
  697. *
  698. * @usr: pointer to hal_txmon_user_desc_per_user
  699. * @user_id: user index
  700. * @ppdu_info: pointer to hal_tx_ppdu_info
  701. *
  702. * Return: void
  703. */
  704. static inline void
  705. hal_txmon_populate_he_data_per_user(struct hal_txmon_user_desc_per_user *usr,
  706. uint32_t user_id,
  707. struct hal_tx_ppdu_info *ppdu_info)
  708. {
  709. uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, he_data1);
  710. uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, he_data2);
  711. uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, he_data3);
  712. uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, he_data5);
  713. uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, he_data6);
  714. /* populate */
  715. /* BEAM CHANGE */
  716. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  717. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  718. he_data5 |= (!!usr->user_bf_type << QDF_MON_STATUS_TXBF_SHIFT);
  719. he_data3 |= (!!usr->user_bf_type << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  720. /* UL/DL known */
  721. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  722. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  723. /* MCS */
  724. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  725. he_data3 |= (usr->mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  726. /* DCM */
  727. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  728. he_data3 |= (usr->dcm << QDF_MON_STATUS_DCM_SHIFT);
  729. /* LDPC EXTRA SYMB */
  730. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  731. he_data3 |= (usr->ldpc_extra_symbol <<
  732. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  733. /* RU offset and RU */
  734. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  735. he_data2 |= (get_ru_offset_from_start_index(usr->ru_size,
  736. usr->ru_start_index) <<
  737. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  738. /* Data BW and RU allocation */
  739. if (usr->ru_size < HAL_MAX_RU_INDEX) {
  740. /* update bandwidth if it is full bandwidth */
  741. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  742. he_data5 = (he_data5 & 0xFFF0) | (4 + usr->ru_size);
  743. }
  744. he_data6 |= (usr->nss & 0xF);
  745. TXMON_HAL_USER(ppdu_info, user_id, mcs) = usr->mcs;
  746. /* update stack variable to ppdu_info */
  747. TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1;
  748. TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2;
  749. TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3;
  750. TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5;
  751. TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6;
  752. }
  753. /**
  754. * hal_txmon_get_user_desc_per_user() - get mactx user desc per user from tlv
  755. *
  756. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  757. * @usr: pointer to hal_txmon_user_desc_per_user
  758. *
  759. * Return: void
  760. */
  761. static inline void
  762. hal_txmon_get_user_desc_per_user(void *tx_tlv,
  763. struct hal_txmon_user_desc_per_user *usr)
  764. {
  765. usr->psdu_length = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  766. PSDU_LENGTH);
  767. usr->ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  768. MACTX_USER_DESC_PER_USER,
  769. RU_START_INDEX);
  770. usr->ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  771. RU_SIZE);
  772. usr->ofdma_mu_mimo_enabled =
  773. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  774. OFDMA_MU_MIMO_ENABLED);
  775. usr->nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, NSS);
  776. usr->stream_offset = HAL_TX_DESC_GET_64(tx_tlv,
  777. MACTX_USER_DESC_PER_USER,
  778. STREAM_OFFSET);
  779. usr->mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  780. usr->dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  781. usr->fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  782. FEC_TYPE);
  783. usr->user_bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  784. USER_BF_TYPE);
  785. usr->drop_user_cbf = HAL_TX_DESC_GET_64(tx_tlv,
  786. MACTX_USER_DESC_PER_USER,
  787. DROP_USER_CBF);
  788. usr->ldpc_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  789. MACTX_USER_DESC_PER_USER,
  790. LDPC_EXTRA_SYMBOL);
  791. usr->force_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  792. MACTX_USER_DESC_PER_USER,
  793. FORCE_EXTRA_SYMBOL);
  794. usr->sw_peer_id = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  795. SW_PEER_ID);
  796. }
  797. /**
  798. * hal_txmon_populate_eht_sig_per_user() - populate eht sig user information
  799. *
  800. * @usr: pointer to hal_txmon_user_desc_per_user
  801. * @user_id: user index
  802. * @ppdu_info: pointer to hal_tx_ppdu_info
  803. *
  804. * Return: void
  805. */
  806. static inline void
  807. hal_txmon_populate_eht_sig_per_user(struct hal_txmon_user_desc_per_user *usr,
  808. uint32_t user_id,
  809. struct hal_tx_ppdu_info *ppdu_info)
  810. {
  811. uint32_t eht_known = 0;
  812. uint32_t eht_data[6] = {0};
  813. uint8_t i = 0;
  814. eht_known = QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN;
  815. eht_data[0] |= (usr->ldpc_extra_symbol <<
  816. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT);
  817. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  818. for (i = 0; i < 6; i++)
  819. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  820. }
  821. /**
  822. * hal_txmon_parse_user_desc_per_user() - parse mactx user desc per user
  823. *
  824. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  825. * @user_id: user index
  826. * @ppdu_info: pointer to hal_tx_ppdu_info
  827. *
  828. * Return: void
  829. */
  830. static inline void
  831. hal_txmon_parse_user_desc_per_user(void *tx_tlv, uint32_t user_id,
  832. struct hal_tx_ppdu_info *ppdu_info)
  833. {
  834. struct hal_txmon_user_desc_per_user usr_info = {0};
  835. hal_txmon_get_user_desc_per_user(tx_tlv, &usr_info);
  836. /* based on preamble type populate user desc user info */
  837. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  838. hal_txmon_populate_he_data_per_user(&usr_info,
  839. user_id, ppdu_info);
  840. hal_txmon_populate_eht_sig_per_user(&usr_info, user_id, ppdu_info);
  841. }
  842. /**
  843. * hal_txmon_get_user_desc_common() - update hal_txmon_usr_desc_common from tlv
  844. *
  845. * @tx_tlv: pointer to mactx_user_desc_common tlv
  846. * @usr_common: pointer to hal_txmon_usr_desc_common
  847. *
  848. * Return: void
  849. */
  850. static inline void
  851. hal_txmon_get_user_desc_common(void *tx_tlv,
  852. struct hal_txmon_usr_desc_common *usr_common)
  853. {
  854. usr_common->ltf_size =
  855. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, LTF_SIZE);
  856. usr_common->pkt_extn_pe =
  857. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  858. PACKET_EXTENSION_PE_DISAMBIGUITY);
  859. usr_common->a_factor =
  860. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  861. PACKET_EXTENSION_A_FACTOR);
  862. usr_common->center_ru_0 =
  863. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_0);
  864. usr_common->center_ru_1 =
  865. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_1);
  866. usr_common->num_ltf_symbols =
  867. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  868. NUM_LTF_SYMBOLS);
  869. usr_common->doppler_indication =
  870. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  871. DOPPLER_INDICATION);
  872. usr_common->spatial_reuse =
  873. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  874. SPATIAL_REUSE);
  875. usr_common->ru_channel_0[0] =
  876. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  877. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0);
  878. usr_common->ru_channel_0[1] =
  879. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  880. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1);
  881. usr_common->ru_channel_0[2] =
  882. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  883. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2);
  884. usr_common->ru_channel_0[3] =
  885. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  886. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3);
  887. usr_common->ru_channel_0[4] =
  888. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  889. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0);
  890. usr_common->ru_channel_0[5] =
  891. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  892. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1);
  893. usr_common->ru_channel_0[6] =
  894. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  895. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2);
  896. usr_common->ru_channel_0[7] =
  897. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  898. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3);
  899. usr_common->ru_channel_1[0] =
  900. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  901. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0);
  902. usr_common->ru_channel_1[1] =
  903. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  904. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1);
  905. usr_common->ru_channel_1[2] =
  906. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  907. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2);
  908. usr_common->ru_channel_1[3] =
  909. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  910. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3);
  911. usr_common->ru_channel_1[4] =
  912. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  913. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0);
  914. usr_common->ru_channel_1[5] =
  915. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  916. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1);
  917. usr_common->ru_channel_1[6] =
  918. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  919. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2);
  920. usr_common->ru_channel_1[7] =
  921. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  922. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3);
  923. }
  924. /**
  925. * hal_txmon_populate_he_data_common() - populate he data common information
  926. *
  927. * @usr_common: pointer to hal_txmon_usr_desc_common
  928. * @user_id: user index
  929. * @ppdu_info: pointer to hal_tx_ppdu_info
  930. *
  931. * Return: void
  932. */
  933. static inline void
  934. hal_txmon_populate_he_data_common(struct hal_txmon_usr_desc_common *usr_common,
  935. uint32_t user_id,
  936. struct hal_tx_ppdu_info *ppdu_info)
  937. {
  938. /* HE data 1 */
  939. TXMON_HAL_USER(ppdu_info,
  940. user_id, he_data1) |= QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  941. /* HE data 2 */
  942. TXMON_HAL_USER(ppdu_info, user_id,
  943. he_data2) |= (QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  944. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN);
  945. /* HE data 5 */
  946. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  947. (usr_common->pkt_extn_pe <<
  948. QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) |
  949. (usr_common->a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) |
  950. ((1 + usr_common->ltf_size) <<
  951. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) |
  952. (usr_common->num_ltf_symbols <<
  953. QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  954. /* HE data 6 */
  955. TXMON_HAL_USER(ppdu_info, user_id,
  956. he_data6) |= (usr_common->doppler_indication <<
  957. QDF_MON_STATUS_DOPPLER_SHIFT);
  958. }
  959. /**
  960. * hal_txmon_populate_he_mu_common() - populate he mu common information
  961. *
  962. * @usr_common: pointer to hal_txmon_usr_desc_common
  963. * @user_id: user index
  964. * @ppdu_info: pointer to hal_tx_ppdu_info
  965. *
  966. * Return: void
  967. */
  968. static inline void
  969. hal_txmon_populate_he_mu_common(struct hal_txmon_usr_desc_common *usr_common,
  970. uint32_t user_id,
  971. struct hal_tx_ppdu_info *ppdu_info)
  972. {
  973. uint16_t he_mu_flag_1 = 0;
  974. uint16_t he_mu_flag_2 = 0;
  975. uint16_t i = 0;
  976. he_mu_flag_1 |= (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  977. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  978. ((usr_common->center_ru_0 <<
  979. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) &
  980. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE));
  981. he_mu_flag_2 |= ((usr_common->center_ru_1 <<
  982. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) &
  983. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE);
  984. for (i = 0; i < usr_common->num_users; i++) {
  985. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  986. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  987. /* channel 1 */
  988. TXMON_HAL_USER(ppdu_info, i, he_RU[0]) =
  989. usr_common->ru_channel_0[0];
  990. TXMON_HAL_USER(ppdu_info, i, he_RU[1]) =
  991. usr_common->ru_channel_0[1];
  992. TXMON_HAL_USER(ppdu_info, i, he_RU[2]) =
  993. usr_common->ru_channel_0[2];
  994. TXMON_HAL_USER(ppdu_info, i, he_RU[3]) =
  995. usr_common->ru_channel_0[3];
  996. /* channel 2 */
  997. TXMON_HAL_USER(ppdu_info, i, he_RU[4]) =
  998. usr_common->ru_channel_1[0];
  999. TXMON_HAL_USER(ppdu_info, i, he_RU[5]) =
  1000. usr_common->ru_channel_1[1];
  1001. TXMON_HAL_USER(ppdu_info, i, he_RU[6]) =
  1002. usr_common->ru_channel_1[2];
  1003. TXMON_HAL_USER(ppdu_info, i, he_RU[7]) =
  1004. usr_common->ru_channel_1[3];
  1005. }
  1006. }
  1007. /**
  1008. * hal_txmon_populate_eht_sig_common() - populate eht sig common information
  1009. *
  1010. * @usr_common: pointer to hal_txmon_usr_desc_common
  1011. * @user_id: user index
  1012. * @ppdu_info: pointer to hal_tx_ppdu_info
  1013. *
  1014. * Return: void
  1015. */
  1016. static inline void
  1017. hal_txmon_populate_eht_sig_common(struct hal_txmon_usr_desc_common *usr_common,
  1018. uint32_t user_id,
  1019. struct hal_tx_ppdu_info *ppdu_info)
  1020. {
  1021. uint32_t eht_known = 0;
  1022. uint32_t eht_data[9] = {0};
  1023. uint8_t num_ru_allocation_known = 0;
  1024. uint8_t i = 0;
  1025. eht_known = (QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1026. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1027. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN |
  1028. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN |
  1029. QDF_MON_STATUS_EHT_DISREARD_KNOWN);
  1030. eht_data[0] |= (usr_common->spatial_reuse <<
  1031. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1032. eht_data[0] |= (usr_common->num_ltf_symbols <<
  1033. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1034. eht_data[0] |= (usr_common->a_factor <<
  1035. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT);
  1036. eht_data[0] |= (usr_common->pkt_extn_pe <<
  1037. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT);
  1038. eht_data[0] |= (0xF << QDF_MON_STATUS_EHT_DISREGARD_SHIFT);
  1039. switch (TXMON_HAL_STATUS(ppdu_info, bw)) {
  1040. case HAL_EHT_BW_320_2:
  1041. case HAL_EHT_BW_320_1:
  1042. num_ru_allocation_known += 4;
  1043. eht_data[3] |= (usr_common->ru_channel_0[7] <<
  1044. QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT);
  1045. eht_data[3] |= (usr_common->ru_channel_0[6] <<
  1046. QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT);
  1047. eht_data[3] |= (usr_common->ru_channel_0[5] <<
  1048. QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT);
  1049. eht_data[2] |= (usr_common->ru_channel_0[4] <<
  1050. QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT);
  1051. fallthrough;
  1052. case HAL_EHT_BW_160:
  1053. num_ru_allocation_known += 2;
  1054. eht_data[2] |= (usr_common->ru_channel_0[3] <<
  1055. QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT);
  1056. eht_data[2] |= (usr_common->ru_channel_0[2] <<
  1057. QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT);
  1058. fallthrough;
  1059. case HAL_EHT_BW_80:
  1060. num_ru_allocation_known += 1;
  1061. eht_data[1] |= (usr_common->ru_channel_0[1] <<
  1062. QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT);
  1063. fallthrough;
  1064. case HAL_EHT_BW_40:
  1065. case HAL_EHT_BW_20:
  1066. num_ru_allocation_known += 1;
  1067. eht_data[1] |= (usr_common->ru_channel_0[0] <<
  1068. QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT);
  1069. break;
  1070. default:
  1071. break;
  1072. }
  1073. eht_known |= (num_ru_allocation_known <<
  1074. QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
  1075. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  1076. for (i = 0; i < 4; i++)
  1077. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  1078. }
  1079. /**
  1080. * hal_txmon_parse_user_desc_common() - parse mactx user desc common tlv
  1081. *
  1082. * @tx_tlv: pointer to mactx_user_desc_common tlv
  1083. * @user_id: user index
  1084. * @ppdu_info: pointer to hal_tx_ppdu_info
  1085. *
  1086. * Return: void
  1087. */
  1088. static inline void
  1089. hal_txmon_parse_user_desc_common(void *tx_tlv, uint32_t user_id,
  1090. struct hal_tx_ppdu_info *ppdu_info)
  1091. {
  1092. struct hal_txmon_usr_desc_common usr_common = {0};
  1093. usr_common.num_users = TXMON_HAL(ppdu_info, num_users);
  1094. hal_txmon_get_user_desc_common(tx_tlv, &usr_common);
  1095. TXMON_HAL_STATUS(ppdu_info,
  1096. he_mu_flags) = IS_MULTI_USERS(usr_common.num_users);
  1097. switch (TXMON_HAL_STATUS(ppdu_info, preamble_type)) {
  1098. case TXMON_PKT_TYPE_11AX:
  1099. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  1100. hal_txmon_populate_he_data_common(&usr_common,
  1101. user_id, ppdu_info);
  1102. if (TXMON_HAL_STATUS(ppdu_info, he_mu_flags))
  1103. hal_txmon_populate_he_mu_common(&usr_common,
  1104. user_id, ppdu_info);
  1105. break;
  1106. case TXMON_PKT_TYPE_11BE:
  1107. hal_txmon_populate_eht_sig_common(&usr_common,
  1108. user_id, ppdu_info);
  1109. break;
  1110. }
  1111. }
  1112. /**
  1113. * hal_txmon_parse_eht_sig_non_mumimo_user_info() - parse eht sig non mumimo tlv
  1114. *
  1115. * @tx_tlv: pointer to hal_eht_sig_non_mu_mimo_user_info
  1116. * @user_id: user index
  1117. * @ppdu_info: pointer to hal_tx_ppdu_info
  1118. *
  1119. * Return: void
  1120. */
  1121. static inline void
  1122. hal_txmon_parse_eht_sig_non_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1123. struct hal_tx_ppdu_info *ppdu_info)
  1124. {
  1125. struct hal_eht_sig_non_mu_mimo_user_info *user_info;
  1126. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1127. user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tx_tlv;
  1128. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1129. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1130. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1131. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1132. QDF_MON_STATUS_EHT_USER_NSS_KNOWN |
  1133. QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN;
  1134. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1135. (user_info->sta_id <<
  1136. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1137. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1138. (user_info->mcs <<
  1139. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1140. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1141. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1142. (user_info->nss <<
  1143. QDF_MON_STATUS_EHT_USER_NSS_SHIFT);
  1144. TXMON_HAL_STATUS(ppdu_info, nss) = user_info->nss + 1;
  1145. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1146. (user_info->beamformed <<
  1147. QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT);
  1148. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1149. (user_info->coding <<
  1150. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1151. /* TODO: CRC */
  1152. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1153. }
  1154. /**
  1155. * hal_txmon_parse_eht_sig_mumimo_user_info() - parse eht sig mumimo tlv
  1156. *
  1157. * @tx_tlv: pointer to hal_eht_sig_mu_mimo_user_info
  1158. * @user_id: user index
  1159. * @ppdu_info: pointer to hal_tx_ppdu_info
  1160. *
  1161. * Return: void
  1162. */
  1163. static inline void
  1164. hal_txmon_parse_eht_sig_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1165. struct hal_tx_ppdu_info *ppdu_info)
  1166. {
  1167. struct hal_eht_sig_mu_mimo_user_info *user_info;
  1168. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1169. user_info = (struct hal_eht_sig_mu_mimo_user_info *)tx_tlv;
  1170. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1171. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1172. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1173. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1174. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN;
  1175. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1176. (user_info->sta_id <<
  1177. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1178. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1179. (user_info->mcs <<
  1180. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1181. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1182. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1183. (user_info->coding <<
  1184. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1185. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1186. (user_info->spatial_coding <<
  1187. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT);
  1188. /* TODO: CRC */
  1189. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1190. }
  1191. /**
  1192. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  1193. * from start of fes window
  1194. *
  1195. * @tx_tlv_hdr: pointer to TLV header
  1196. * @num_users: reference to number of user
  1197. *
  1198. * Return: status
  1199. */
  1200. static inline uint32_t
  1201. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  1202. {
  1203. uint32_t tlv_tag, user_id, tlv_len;
  1204. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1205. void *tx_tlv;
  1206. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1207. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  1208. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  1209. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1210. /* window starts with either initiator or response */
  1211. switch (tlv_tag) {
  1212. case WIFITX_FES_SETUP_E:
  1213. {
  1214. *num_users = hal_txmon_get_num_users(tx_tlv);
  1215. if (*num_users == 0)
  1216. *num_users = 1;
  1217. tlv_status = HAL_MON_TX_FES_SETUP;
  1218. break;
  1219. }
  1220. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  1221. {
  1222. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  1223. RX_RESPONSE_REQUIRED_INFO,
  1224. RESPONSE_STA_COUNT);
  1225. if (*num_users == 0)
  1226. *num_users = 1;
  1227. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1228. break;
  1229. }
  1230. };
  1231. return tlv_status;
  1232. }
  1233. /**
  1234. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  1235. * @data_info: populate dp_ppdu_info data
  1236. * @prot_info: populate dp_ppdu_info protection
  1237. * @tlv_tag: Tag
  1238. *
  1239. * Return: dp_tx_ppdu_info pointer
  1240. */
  1241. static inline void *
  1242. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  1243. {
  1244. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  1245. switch (tlv_tag) {
  1246. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  1247. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1248. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  1249. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  1250. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  1251. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  1252. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  1253. case WIFITX_DATA_E:/* DOWNSTREAM */
  1254. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1255. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1256. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1257. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1258. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1259. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1260. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1261. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1262. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1263. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1264. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1265. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1266. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1267. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1268. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  1269. {
  1270. return data_info;
  1271. }
  1272. }
  1273. /*
  1274. * check current prot_tlv_status is start protection
  1275. * check current tlv_tag is either start protection or end protection
  1276. */
  1277. if (TXMON_HAL(prot_ppdu_info,
  1278. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  1279. return prot_info;
  1280. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  1281. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  1282. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  1283. return prot_info;
  1284. }
  1285. return data_info;
  1286. }
  1287. /**
  1288. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  1289. * @data_ppdu_info: hal_txmon data ppdu info
  1290. * @prot_ppdu_info: hal_txmon prot ppdu info
  1291. * @data_status_info: pointer to data status info
  1292. * @prot_status_info: pointer to prot status info
  1293. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  1294. * @status_frag: qdf_frag_t buffer
  1295. *
  1296. * Return: status
  1297. */
  1298. static inline uint32_t
  1299. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  1300. void *prot_ppdu_info,
  1301. void *data_status_info,
  1302. void *prot_status_info,
  1303. void *tx_tlv_hdr,
  1304. qdf_frag_t status_frag)
  1305. {
  1306. struct hal_tx_ppdu_info *ppdu_info;
  1307. struct hal_tx_status_info *tx_status_info;
  1308. struct hal_mon_packet_info *packet_info = NULL;
  1309. uint32_t tlv_tag, user_id, tlv_len, tlv_user_id;
  1310. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1311. void *tx_tlv;
  1312. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  1313. tlv_user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr);
  1314. tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr);
  1315. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1316. /* parse tlv and populate tx_ppdu_info */
  1317. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  1318. prot_ppdu_info, tlv_tag);
  1319. tx_status_info = (ppdu_info->is_data ? data_status_info :
  1320. prot_status_info);
  1321. user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id);
  1322. switch (tlv_tag) {
  1323. /* start of initiator FES window */
  1324. case WIFITX_FES_SETUP_E:/* DOWNSTREAM - COMPACTION */
  1325. {
  1326. /* initiator PPDU window start */
  1327. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  1328. status = HAL_MON_TX_FES_SETUP;
  1329. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  1330. break;
  1331. }
  1332. /* end of initiator FES window */
  1333. case WIFITX_FES_STATUS_END_E:/* UPSTREAM - COMPACTION */
  1334. {
  1335. hal_txmon_parse_tx_fes_status_end(tx_tlv, ppdu_info,
  1336. tx_status_info);
  1337. status = HAL_MON_TX_FES_STATUS_END;
  1338. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  1339. break;
  1340. }
  1341. /* response window open */
  1342. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  1343. {
  1344. /* response PPDU window start */
  1345. uint32_t ppdu_id = 0;
  1346. uint8_t reception_type = 0;
  1347. uint8_t response_sta_count = 0;
  1348. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1349. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  1350. RX_RESPONSE_REQUIRED_INFO,
  1351. PHY_PPDU_ID);
  1352. reception_type =
  1353. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1354. SU_OR_UPLINK_MU_RECEPTION);
  1355. response_sta_count =
  1356. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1357. RESPONSE_STA_COUNT);
  1358. /* get mac address */
  1359. *(uint32_t *)&tx_status_info->addr1[0] =
  1360. HAL_TX_DESC_GET_64(tx_tlv,
  1361. RX_RESPONSE_REQUIRED_INFO,
  1362. ADDR1_31_0);
  1363. *(uint32_t *)&tx_status_info->addr1[4] =
  1364. HAL_TX_DESC_GET_64(tx_tlv,
  1365. RX_RESPONSE_REQUIRED_INFO,
  1366. ADDR1_47_32);
  1367. *(uint32_t *)&tx_status_info->addr2[0] =
  1368. HAL_TX_DESC_GET_64(tx_tlv,
  1369. RX_RESPONSE_REQUIRED_INFO,
  1370. ADDR2_15_0);
  1371. *(uint32_t *)&tx_status_info->addr2[2] =
  1372. HAL_TX_DESC_GET_64(tx_tlv,
  1373. RX_RESPONSE_REQUIRED_INFO,
  1374. ADDR2_47_16);
  1375. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  1376. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  1377. if (response_sta_count == 0)
  1378. response_sta_count = 1;
  1379. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  1380. if (reception_type)
  1381. TXMON_STATUS_INFO(tx_status_info,
  1382. transmission_type) =
  1383. TXMON_SU_TRANSMISSION;
  1384. else
  1385. TXMON_STATUS_INFO(tx_status_info,
  1386. transmission_type) =
  1387. TXMON_MU_TRANSMISSION;
  1388. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  1389. break;
  1390. }
  1391. /* Response window close */
  1392. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM - COMPACTION */
  1393. {
  1394. /* response PPDU window end */
  1395. hal_txmon_parse_response_end_status(tx_tlv, ppdu_info,
  1396. tx_status_info);
  1397. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  1398. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  1399. break;
  1400. }
  1401. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1402. {
  1403. SHOW_DEFINED(WIFITX_FLUSH_E);
  1404. break;
  1405. }
  1406. /* Downstream tlv */
  1407. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM - COMPACTION */
  1408. {
  1409. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  1410. prot_status_info);
  1411. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  1412. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  1413. break;
  1414. }
  1415. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM - COMPACTION */
  1416. {
  1417. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  1418. ppdu_info, tx_status_info);
  1419. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  1420. break;
  1421. }
  1422. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM - COMPACTION */
  1423. {
  1424. status = HAL_MON_TX_QUEUE_EXTENSION;
  1425. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  1426. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  1427. break;
  1428. }
  1429. /* payload and data frame handling */
  1430. case WIFITX_MPDU_START_E:/* DOWNSTREAM - COMPACTION */
  1431. {
  1432. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  1433. status = HAL_MON_TX_MPDU_START;
  1434. SHOW_DEFINED(WIFITX_MPDU_START_E);
  1435. break;
  1436. }
  1437. case WIFITX_MSDU_START_E:/* DOWNSTREAM - COMPACTION */
  1438. {
  1439. hal_txmon_parse_msdu_start(tx_tlv, user_id, ppdu_info);
  1440. /* we expect frame to be 802.11 frame type */
  1441. status = HAL_MON_TX_MSDU_START;
  1442. SHOW_DEFINED(WIFITX_MSDU_START_E);
  1443. break;
  1444. }
  1445. case WIFITX_DATA_E:/* DOWNSTREAM */
  1446. {
  1447. status = HAL_MON_TX_DATA;
  1448. /*
  1449. * TODO: do we need a conversion api to convert
  1450. * user_id from hw to get host user_index
  1451. */
  1452. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1453. TXMON_STATUS_INFO(tx_status_info,
  1454. buffer) = (void *)status_frag;
  1455. TXMON_STATUS_INFO(tx_status_info,
  1456. offset) = ((void *)tx_tlv -
  1457. (void *)status_frag);
  1458. TXMON_STATUS_INFO(tx_status_info,
  1459. length) = tlv_len;
  1460. /*
  1461. * reference of the status buffer will be held in
  1462. * dp_tx_update_ppdu_info_status()
  1463. */
  1464. status = HAL_MON_TX_DATA;
  1465. SHOW_DEFINED(WIFITX_DATA_E);
  1466. break;
  1467. }
  1468. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1469. {
  1470. packet_info = &ppdu_info->packet_info;
  1471. status = HAL_MON_TX_BUFFER_ADDR;
  1472. /*
  1473. * TODO: do we need a conversion api to convert
  1474. * user_id from hw to get host user_index
  1475. */
  1476. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1477. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  1478. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  1479. break;
  1480. }
  1481. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1482. {
  1483. /* no tlv content */
  1484. SHOW_DEFINED(WIFITX_MPDU_END_E);
  1485. break;
  1486. }
  1487. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1488. {
  1489. /* no tlv content */
  1490. SHOW_DEFINED(WIFITX_MSDU_END_E);
  1491. break;
  1492. }
  1493. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1494. {
  1495. /* no tlv content */
  1496. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  1497. break;
  1498. }
  1499. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1500. {
  1501. /* no tlv content */
  1502. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  1503. break;
  1504. }
  1505. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1506. {
  1507. /*
  1508. * transmitting power
  1509. * minimum transmitting power
  1510. * desired nss
  1511. * tx chain mask
  1512. * desired bw
  1513. * duration of transmit and response
  1514. *
  1515. * since most of the field we are deriving from other tlv
  1516. * we don't need to enable this in our tlv.
  1517. */
  1518. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  1519. break;
  1520. }
  1521. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1522. {
  1523. /* user tlv */
  1524. /*
  1525. * All Tx monitor will have 802.11 hdr
  1526. * we don't need to enable this TLV
  1527. */
  1528. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  1529. break;
  1530. }
  1531. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1532. {
  1533. /*
  1534. * no tlv content
  1535. *
  1536. * TLV that indicates to TXPCU that preamble phase for the NDP
  1537. * frame transmission is now over
  1538. */
  1539. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  1540. break;
  1541. }
  1542. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1543. {
  1544. /*
  1545. * no tlv content
  1546. *
  1547. * TLV indicates to the SCH that all timing critical TLV
  1548. * has been passed on to the transmit path
  1549. */
  1550. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  1551. break;
  1552. }
  1553. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1554. {
  1555. /*
  1556. * Loopback specific setup info - not needed for Tx monitor
  1557. */
  1558. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  1559. break;
  1560. }
  1561. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1562. {
  1563. /*
  1564. * no tlv content
  1565. *
  1566. * TLV indicates that other modules besides the scheduler can
  1567. * now also start generating TLV's
  1568. * prevent colliding or generating TLV's out of order
  1569. */
  1570. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1571. break;
  1572. }
  1573. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1574. {
  1575. /*
  1576. * no tlv content
  1577. *
  1578. * TLV indicates to SCH that a burst of MPDU info will
  1579. * start to come in over the TLV
  1580. */
  1581. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1582. break;
  1583. }
  1584. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1585. {
  1586. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1587. break;
  1588. }
  1589. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1590. {
  1591. /*
  1592. * no tlv content
  1593. *
  1594. * TLV indicates END of all TLV's within the scheduler TLV
  1595. */
  1596. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1597. break;
  1598. }
  1599. /* Upstream tlv */
  1600. case WIFIPDG_TX_REQ_E:
  1601. {
  1602. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1603. break;
  1604. }
  1605. case WIFITX_FES_STATUS_START_E:
  1606. {
  1607. /*
  1608. * TLV indicating that first transmission on the medium
  1609. */
  1610. uint8_t medium_prot_type = 0;
  1611. status = HAL_MON_TX_FES_STATUS_START;
  1612. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1613. TX_FES_STATUS_START,
  1614. MEDIUM_PROT_TYPE);
  1615. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1616. /* update what type of medium protection frame */
  1617. TXMON_STATUS_INFO(tx_status_info,
  1618. medium_prot_type) = medium_prot_type;
  1619. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1620. break;
  1621. }
  1622. case WIFITX_FES_STATUS_PROT_E:/* UPSTREAM - COMPACTION */
  1623. {
  1624. hal_txmon_parse_tx_fes_status_prot(tx_tlv, ppdu_info,
  1625. tx_status_info);
  1626. status = HAL_MON_TX_FES_STATUS_PROT;
  1627. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1628. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1629. break;
  1630. }
  1631. case WIFITX_FES_STATUS_START_PROT_E:
  1632. {
  1633. uint64_t tsft_64;
  1634. uint32_t response_type;
  1635. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1636. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1637. /* timestamp */
  1638. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1639. TX_FES_STATUS_START_PROT,
  1640. PROT_TIMESTAMP_LOWER_32);
  1641. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1642. TX_FES_STATUS_START_PROT,
  1643. PROT_TIMESTAMP_UPPER_32) << 32);
  1644. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1645. TX_FES_STATUS_START_PROT,
  1646. RESPONSE_TYPE);
  1647. TXMON_STATUS_INFO(tx_status_info,
  1648. response_type) = response_type;
  1649. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1650. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1651. break;
  1652. }
  1653. case WIFIPROT_TX_END_E:
  1654. {
  1655. /*
  1656. * no tlv content
  1657. *
  1658. * generated by TXPCU the moment that protection frame
  1659. * transmission has finished on the medium
  1660. */
  1661. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1662. break;
  1663. }
  1664. case WIFITX_FES_STATUS_START_PPDU_E:
  1665. {
  1666. uint64_t tsft_64;
  1667. uint8_t ndp_frame;
  1668. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1669. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1670. TX_FES_STATUS_START_PPDU,
  1671. PPDU_TIMESTAMP_LOWER_32);
  1672. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1673. TX_FES_STATUS_START_PPDU,
  1674. PPDU_TIMESTAMP_UPPER_32) << 32);
  1675. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1676. TX_FES_STATUS_START_PPDU,
  1677. NDP_FRAME);
  1678. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1679. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1680. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1681. break;
  1682. }
  1683. case WIFITX_FES_STATUS_USER_PPDU_E:
  1684. {
  1685. /* user tlv */
  1686. uint16_t duration;
  1687. uint8_t transmitted_tid;
  1688. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1689. TX_FES_STATUS_USER_PPDU,
  1690. DURATION);
  1691. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1692. TX_FES_STATUS_USER_PPDU,
  1693. TRANSMITTED_TID);
  1694. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1695. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1696. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1697. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1698. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1699. break;
  1700. }
  1701. case WIFIPPDU_TX_END_E:
  1702. {
  1703. /*
  1704. * no tlv content
  1705. *
  1706. * generated by TXPCU the moment that PPDU transmission has
  1707. * finished on the medium
  1708. */
  1709. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1710. break;
  1711. }
  1712. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1713. {
  1714. /*
  1715. * TLV contains the FES transmit result of the each
  1716. * of the MAC users. TLV are forwarded to HWSCH
  1717. */
  1718. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1719. break;
  1720. }
  1721. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1722. {
  1723. /* user tlv */
  1724. /*
  1725. * TLV generated by RXPCU and provide information related to
  1726. * the received BA or ACK frame
  1727. */
  1728. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1729. break;
  1730. }
  1731. case WIFITX_FES_STATUS_1K_BA_E:
  1732. {
  1733. /* user tlv */
  1734. /*
  1735. * TLV generated by RXPCU and providing information related
  1736. * to the received BA frame in case of 512/1024 bitmaps
  1737. */
  1738. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1739. break;
  1740. }
  1741. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1742. {
  1743. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1744. break;
  1745. }
  1746. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1747. {
  1748. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1749. break;
  1750. }
  1751. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1752. {
  1753. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1754. break;
  1755. }
  1756. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1757. {
  1758. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1759. break;
  1760. }
  1761. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1762. {
  1763. /*
  1764. * RXPCU generates this TLV when it receives a response frame
  1765. * that TXPCU pre-announced it was waiting for and in
  1766. * RXPCU_SETUP TLV, TLV generated before the
  1767. * RECEIVED_RESPONSE_INFO TLV.
  1768. *
  1769. * received info user fields are there which is not needed
  1770. * for TX monitor
  1771. */
  1772. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1773. break;
  1774. }
  1775. case WIFITXPCU_BUFFER_STATUS_E:
  1776. {
  1777. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1778. break;
  1779. }
  1780. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1781. {
  1782. /*
  1783. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1784. * for TX monitor we aren't interested in this tlv
  1785. */
  1786. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1787. break;
  1788. }
  1789. case WIFITXDMA_STOP_REQUEST_E:
  1790. {
  1791. /*
  1792. * no tlv content
  1793. *
  1794. * TLV is destined to TXDMA and informs TXDMA to stop
  1795. * pushing data into the transmit path.
  1796. */
  1797. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1798. break;
  1799. }
  1800. case WIFITX_CBF_INFO_E:
  1801. {
  1802. /*
  1803. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1804. * TXPCU to respond the CBF frame
  1805. *
  1806. * compressed beamforming pkt doesn't has mac header
  1807. * Tx monitor not interested in this pkt.
  1808. */
  1809. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1810. break;
  1811. }
  1812. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1813. {
  1814. /*
  1815. * no tlv content
  1816. *
  1817. * TLV indicates that TXPCU has finished generating the
  1818. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1819. */
  1820. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1821. break;
  1822. }
  1823. case WIFIPDG_RESPONSE_E:
  1824. {
  1825. /*
  1826. * most of the feilds are already covered in
  1827. * other TLV
  1828. * This is generated by TX_PCU to PDG to calculate
  1829. * all the PHY header info.
  1830. *
  1831. * some useful fields like min transmit power,
  1832. * rate used for transmitting packet is present.
  1833. */
  1834. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1835. break;
  1836. }
  1837. case WIFIPDG_TRIG_RESPONSE_E:
  1838. {
  1839. /* no tlv content */
  1840. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1841. break;
  1842. }
  1843. case WIFIRECEIVED_TRIGGER_INFO_E:
  1844. {
  1845. /*
  1846. * TLV generated by RXPCU to inform the scheduler that
  1847. * a trigger frame has been received
  1848. */
  1849. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1850. break;
  1851. }
  1852. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1853. {
  1854. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1855. break;
  1856. }
  1857. case WIFIRX_FRAME_BITMAP_ACK_E:
  1858. {
  1859. /* user tlv */
  1860. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1861. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1862. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1863. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1864. HAL_TX_DESC_GET_64(tx_tlv,
  1865. RX_FRAME_BITMAP_ACK,
  1866. NO_BITMAP_AVAILABLE);
  1867. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1868. HAL_TX_DESC_GET_64(tx_tlv,
  1869. RX_FRAME_BITMAP_ACK,
  1870. EXPLICIT_ACK);
  1871. /*
  1872. * get mac address, since address is received frame
  1873. * change the order and store it
  1874. */
  1875. *(uint32_t *)&tx_status_info->addr2[0] =
  1876. HAL_TX_DESC_GET_64(tx_tlv,
  1877. RX_FRAME_BITMAP_ACK,
  1878. ADDR1_31_0);
  1879. *(uint32_t *)&tx_status_info->addr2[4] =
  1880. HAL_TX_DESC_GET_64(tx_tlv,
  1881. RX_FRAME_BITMAP_ACK,
  1882. ADDR1_47_32);
  1883. *(uint32_t *)&tx_status_info->addr1[0] =
  1884. HAL_TX_DESC_GET_64(tx_tlv,
  1885. RX_FRAME_BITMAP_ACK,
  1886. ADDR2_15_0);
  1887. *(uint32_t *)&tx_status_info->addr1[2] =
  1888. HAL_TX_DESC_GET_64(tx_tlv,
  1889. RX_FRAME_BITMAP_ACK,
  1890. ADDR2_47_16);
  1891. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  1892. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  1893. EXPLICT_ACK_TYPE);
  1894. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1895. HAL_TX_DESC_GET_64(tx_tlv,
  1896. RX_FRAME_BITMAP_ACK,
  1897. BA_TID);
  1898. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1899. HAL_TX_DESC_GET_64(tx_tlv,
  1900. RX_FRAME_BITMAP_ACK,
  1901. STA_FULL_AID);
  1902. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1903. HAL_TX_DESC_GET_64(tx_tlv,
  1904. RX_FRAME_BITMAP_ACK,
  1905. BA_TS_SEQ);
  1906. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1907. HAL_TX_DESC_GET_64(tx_tlv,
  1908. RX_FRAME_BITMAP_ACK,
  1909. BA_TS_CTRL);
  1910. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1911. HAL_TX_DESC_GET_64(tx_tlv,
  1912. RX_FRAME_BITMAP_ACK,
  1913. BA_BITMAP_SIZE);
  1914. /* ba bitmap */
  1915. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1916. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1917. RX_FRAME_BITMAP_ACK,
  1918. BA_TS_BITMAP_31_0, 0), 32);
  1919. break;
  1920. }
  1921. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  1922. {
  1923. /* user tlv */
  1924. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  1925. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  1926. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1927. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1928. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  1929. BA_BITMAP_SIZE));
  1930. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1931. HAL_TX_DESC_GET_64(tx_tlv,
  1932. RX_FRAME_1K_BITMAP_ACK,
  1933. BA_TID);
  1934. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1935. HAL_TX_DESC_GET_64(tx_tlv,
  1936. RX_FRAME_1K_BITMAP_ACK,
  1937. STA_FULL_AID);
  1938. /* get mac address */
  1939. *(uint32_t *)&tx_status_info->addr1[0] =
  1940. HAL_TX_DESC_GET_64(tx_tlv,
  1941. RX_FRAME_1K_BITMAP_ACK,
  1942. ADDR1_31_0);
  1943. *(uint32_t *)&tx_status_info->addr1[4] =
  1944. HAL_TX_DESC_GET_64(tx_tlv,
  1945. RX_FRAME_1K_BITMAP_ACK,
  1946. ADDR1_47_32);
  1947. *(uint32_t *)&tx_status_info->addr2[0] =
  1948. HAL_TX_DESC_GET_64(tx_tlv,
  1949. RX_FRAME_1K_BITMAP_ACK,
  1950. ADDR2_15_0);
  1951. *(uint32_t *)&tx_status_info->addr2[2] =
  1952. HAL_TX_DESC_GET_64(tx_tlv,
  1953. RX_FRAME_1K_BITMAP_ACK,
  1954. ADDR2_47_16);
  1955. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1956. HAL_TX_DESC_GET_64(tx_tlv,
  1957. RX_FRAME_1K_BITMAP_ACK,
  1958. BA_TS_SEQ);
  1959. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1960. HAL_TX_DESC_GET_64(tx_tlv,
  1961. RX_FRAME_1K_BITMAP_ACK,
  1962. BA_TS_CTRL);
  1963. /* memcpy ba bitmap */
  1964. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1965. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1966. RX_FRAME_1K_BITMAP_ACK,
  1967. BA_TS_BITMAP_31_0, 0),
  1968. 4 << TXMON_HAL_USER(ppdu_info,
  1969. user_id, ba_bitmap_sz));
  1970. break;
  1971. }
  1972. case WIFIRESPONSE_START_STATUS_E:
  1973. {
  1974. /*
  1975. * TLV indicates which HW response the TXPCU
  1976. * started generating
  1977. *
  1978. * HW generated frames like
  1979. * ACK frame - handled
  1980. * CTS frame - handled
  1981. * BA frame - handled
  1982. * MBA frame - handled
  1983. * CBF frame - no frame header
  1984. * Trigger response - TODO
  1985. * NDP LMR - no frame header
  1986. */
  1987. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  1988. break;
  1989. }
  1990. case WIFIRX_START_PARAM_E:
  1991. {
  1992. /*
  1993. * RXPCU send this TLV after PHY RX detected a frame
  1994. * in the medium
  1995. *
  1996. * TX monitor not interested in this TLV
  1997. */
  1998. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  1999. break;
  2000. }
  2001. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  2002. {
  2003. /*
  2004. * early indication of pkt type and mcs rate
  2005. * already captured in other tlv
  2006. */
  2007. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  2008. break;
  2009. }
  2010. case WIFIRX_PM_INFO_E:
  2011. {
  2012. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  2013. break;
  2014. }
  2015. /* Active window */
  2016. case WIFITX_FLUSH_REQ_E:
  2017. {
  2018. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  2019. break;
  2020. }
  2021. case WIFICOEX_TX_STATUS_E:
  2022. {
  2023. /* duration are retrieved from coex tx status */
  2024. uint16_t duration;
  2025. uint8_t status_reason;
  2026. status = HAL_MON_COEX_TX_STATUS;
  2027. duration = HAL_TX_DESC_GET_64(tx_tlv,
  2028. COEX_TX_STATUS,
  2029. CURRENT_TX_DURATION);
  2030. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  2031. COEX_TX_STATUS,
  2032. TX_STATUS_REASON);
  2033. /* update duration */
  2034. if (status_reason == COEX_FES_TX_START ||
  2035. status_reason == COEX_RESPONSE_TX_START)
  2036. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  2037. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  2038. break;
  2039. }
  2040. case WIFIR2R_STATUS_END_E:
  2041. {
  2042. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  2043. break;
  2044. }
  2045. case WIFIRX_PREAMBLE_E:
  2046. {
  2047. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  2048. break;
  2049. }
  2050. case WIFIMACTX_SERVICE_E:
  2051. {
  2052. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  2053. break;
  2054. }
  2055. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  2056. {
  2057. struct hal_mon_usig_hdr *usig = NULL;
  2058. struct hal_mon_usig_mu *usig_mu = NULL;
  2059. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2060. usig_mu = &usig->usig_2.mu;
  2061. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2062. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2063. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2064. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2065. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2066. QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN |
  2067. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN |
  2068. QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN |
  2069. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN |
  2070. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN |
  2071. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2072. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2073. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2074. (0x1F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2075. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2076. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT);
  2077. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2078. (usig_mu->ppdu_type_comp_mode <<
  2079. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2080. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2081. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2082. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2083. (usig_mu->punc_ch_info <<
  2084. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT);
  2085. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2086. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT);
  2087. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2088. (usig_mu->eht_sig_mcs <<
  2089. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT);
  2090. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2091. (usig_mu->num_eht_sig_sym <<
  2092. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT);
  2093. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2094. (usig_mu->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2095. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2096. (usig_mu->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2097. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  2098. break;
  2099. }
  2100. case WIFIMACTX_U_SIG_EHT_TB_E:
  2101. {
  2102. struct hal_mon_usig_hdr *usig = NULL;
  2103. struct hal_mon_usig_tb *usig_tb = NULL;
  2104. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2105. usig_tb = &usig->usig_2.tb;
  2106. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2107. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2108. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2109. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2110. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2111. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN |
  2112. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN |
  2113. QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN |
  2114. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2115. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2116. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2117. (0x3F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2118. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2119. (usig_tb->ppdu_type_comp_mode <<
  2120. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2121. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2122. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2123. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2124. (usig_tb->spatial_reuse_1 <<
  2125. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT);
  2126. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2127. (usig_tb->spatial_reuse_2 <<
  2128. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT);
  2129. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2130. (0x1F << QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT);
  2131. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2132. (usig_tb->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2133. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2134. (usig_tb->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2135. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  2136. break;
  2137. }
  2138. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  2139. {
  2140. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2141. ppdu_info);
  2142. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2143. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  2144. break;
  2145. }
  2146. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  2147. {
  2148. hal_txmon_parse_eht_sig_mumimo_user_info(tx_tlv, user_id,
  2149. ppdu_info);
  2150. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2151. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  2152. break;
  2153. }
  2154. case WIFIMACTX_EHT_SIG_USR_SU_E:
  2155. {
  2156. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2157. ppdu_info);
  2158. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2159. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  2160. /* TODO: no radiotap info available */
  2161. break;
  2162. }
  2163. case WIFIMACTX_HE_SIG_A_SU_E:
  2164. {
  2165. uint16_t he_mu_flag_1 = 0;
  2166. uint16_t he_mu_flag_2 = 0;
  2167. uint16_t num_users = 0;
  2168. uint8_t mcs_of_sig_b = 0;
  2169. uint8_t dcm_of_sig_b = 0;
  2170. uint8_t sig_a_bw = 0;
  2171. uint8_t i = 0;
  2172. uint8_t bss_color_id;
  2173. uint8_t coding;
  2174. uint8_t stbc;
  2175. uint8_t a_factor;
  2176. uint8_t pe_disambiguity;
  2177. uint8_t txbf;
  2178. uint8_t txbw;
  2179. uint8_t txop;
  2180. status = HAL_MON_MACTX_HE_SIG_A_SU;
  2181. num_users = TXMON_HAL(ppdu_info, num_users);
  2182. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2183. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2184. TRANSMIT_MCS);
  2185. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2186. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2187. DCM);
  2188. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2189. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2190. TRANSMIT_BW);
  2191. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2192. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2193. BSS_COLOR_ID);
  2194. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2195. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2196. CODING);
  2197. stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2198. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2199. STBC);
  2200. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  2201. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2202. PACKET_EXTENSION_A_FACTOR);
  2203. pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv,
  2204. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2205. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2206. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2207. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2208. TXBF);
  2209. txbw = HAL_TX_DESC_GET_64(tx_tlv,
  2210. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2211. TRANSMIT_BW);
  2212. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2213. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2214. TXOP_DURATION);
  2215. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2216. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2217. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2218. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2219. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2220. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  2221. /* MCS */
  2222. he_mu_flag_1 |= mcs_of_sig_b <<
  2223. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2224. /* DCM */
  2225. he_mu_flag_1 |= dcm_of_sig_b <<
  2226. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2227. /* bandwidth */
  2228. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2229. he_mu_flag_2 |= sig_a_bw <<
  2230. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2231. TXMON_HAL_STATUS(ppdu_info,
  2232. he_mu_flags) = IS_MULTI_USERS(num_users);
  2233. for (i = 0; i < num_users; i++) {
  2234. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2235. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2236. }
  2237. /* HE data 1 */
  2238. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2239. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2240. QDF_MON_STATUS_HE_CODING_KNOWN;
  2241. /* HE data 2 */
  2242. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2243. QDF_MON_STATUS_TXBF_KNOWN |
  2244. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2245. QDF_MON_STATUS_TXOP_KNOWN |
  2246. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2247. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2248. /* HE data 3 */
  2249. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2250. bss_color_id |
  2251. (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) |
  2252. (coding << QDF_MON_STATUS_CODING_SHIFT) |
  2253. (stbc << QDF_MON_STATUS_STBC_SHIFT);
  2254. /* HE data 6 */
  2255. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2256. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2257. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  2258. break;
  2259. }
  2260. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  2261. {
  2262. uint16_t he_mu_flag_1 = 0;
  2263. uint16_t he_mu_flag_2 = 0;
  2264. uint16_t num_users = 0;
  2265. uint8_t bss_color_id;
  2266. uint8_t txop;
  2267. uint8_t mcs_of_sig_b = 0;
  2268. uint8_t dcm_of_sig_b = 0;
  2269. uint8_t sig_a_bw = 0;
  2270. uint8_t num_sig_b_symb = 0;
  2271. uint8_t comp_mode_sig_b = 0;
  2272. uint8_t punc_bw = 0;
  2273. uint8_t i = 0;
  2274. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  2275. num_users = TXMON_HAL(ppdu_info, num_users);
  2276. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2277. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2278. MCS_OF_SIG_B);
  2279. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2280. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2281. DCM_OF_SIG_B);
  2282. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2283. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2284. TRANSMIT_BW);
  2285. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  2286. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2287. NUM_SIG_B_SYMBOLS);
  2288. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2289. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2290. COMP_MODE_SIG_B);
  2291. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2292. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2293. BSS_COLOR_ID);
  2294. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2295. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2296. TXOP_DURATION);
  2297. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2298. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2299. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  2300. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2301. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2302. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2303. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  2304. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  2305. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  2306. /* MCS */
  2307. he_mu_flag_1 |= mcs_of_sig_b <<
  2308. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2309. /* DCM */
  2310. he_mu_flag_1 |= dcm_of_sig_b <<
  2311. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2312. /* Compression */
  2313. he_mu_flag_2 |= comp_mode_sig_b <<
  2314. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2315. /* bandwidth */
  2316. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2317. he_mu_flag_2 |= sig_a_bw <<
  2318. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2319. he_mu_flag_2 |= comp_mode_sig_b <<
  2320. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2321. /* number of symbol */
  2322. he_mu_flag_2 |= num_sig_b_symb <<
  2323. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  2324. /* puncture bw */
  2325. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  2326. punc_bw = sig_a_bw;
  2327. he_mu_flag_2 |=
  2328. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  2329. /* copy per user info to all user */
  2330. TXMON_HAL_STATUS(ppdu_info,
  2331. he_mu_flags) = IS_MULTI_USERS(num_users);
  2332. for (i = 0; i < num_users; i++) {
  2333. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2334. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2335. }
  2336. /* HE data 1 */
  2337. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2338. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN;
  2339. /* HE data 2 */
  2340. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2341. QDF_MON_STATUS_TXOP_KNOWN;
  2342. /* HE data 3 */
  2343. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id;
  2344. /* HE data 6 */
  2345. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2346. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2347. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  2348. break;
  2349. }
  2350. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  2351. {
  2352. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  2353. break;
  2354. }
  2355. case WIFIMACTX_HE_SIG_B1_MU_E:
  2356. {
  2357. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  2358. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  2359. break;
  2360. }
  2361. case WIFIMACTX_HE_SIG_B2_MU_E:
  2362. {
  2363. /* user tlv */
  2364. uint16_t sta_id = 0;
  2365. uint16_t sta_spatial_config = 0;
  2366. uint8_t sta_mcs = 0;
  2367. uint8_t coding = 0;
  2368. uint8_t nss = 0;
  2369. uint8_t user_order = 0;
  2370. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  2371. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2372. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2373. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2374. STA_ID);
  2375. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  2376. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2377. STA_SPATIAL_CONFIG);
  2378. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2379. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2380. STA_MCS);
  2381. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2382. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2383. STA_CODING);
  2384. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2385. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2386. NSTS) + 1;
  2387. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2388. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2389. USER_ORDER);
  2390. /* HE data 1 */
  2391. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2392. QDF_MON_STATUS_HE_MCS_KNOWN |
  2393. QDF_MON_STATUS_HE_CODING_KNOWN;
  2394. /* HE data 2 */
  2395. /* HE data 3 */
  2396. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2397. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2398. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2399. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2400. coding << QDF_MON_STATUS_CODING_SHIFT;
  2401. /* HE data 4 */
  2402. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2403. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2404. /* HE data 5 */
  2405. /* HE data 6 */
  2406. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2407. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2408. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  2409. break;
  2410. }
  2411. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  2412. {
  2413. /* user tlv */
  2414. uint8_t *he_sig_b2_ofdma_info = NULL;
  2415. uint16_t sta_id = 0;
  2416. uint8_t nss = 0;
  2417. uint8_t txbf = 0;
  2418. uint8_t sta_mcs = 0;
  2419. uint8_t sta_dcm = 0;
  2420. uint8_t coding = 0;
  2421. uint8_t user_order = 0;
  2422. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  2423. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2424. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  2425. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2426. STA_ID);
  2427. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2428. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2429. STA_ID);
  2430. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2431. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2432. NSTS);
  2433. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2434. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2435. TXBF);
  2436. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2437. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2438. STA_MCS);
  2439. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  2440. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2441. STA_DCM);
  2442. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2443. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2444. STA_CODING);
  2445. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2446. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2447. USER_ORDER);
  2448. /* HE data 1 */
  2449. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2450. QDF_MON_STATUS_HE_MCS_KNOWN |
  2451. QDF_MON_STATUS_HE_CODING_KNOWN |
  2452. QDF_MON_STATUS_HE_DCM_KNOWN;
  2453. /* HE data 2 */
  2454. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2455. QDF_MON_STATUS_TXBF_KNOWN;
  2456. /* HE data 3 */
  2457. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2458. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2459. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2460. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2461. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  2462. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2463. coding << QDF_MON_STATUS_CODING_SHIFT;
  2464. /* HE data 4 */
  2465. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2466. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2467. /* HE data 5 */
  2468. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  2469. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  2470. /* HE data 6 */
  2471. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2472. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2473. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  2474. break;
  2475. }
  2476. case WIFIMACTX_L_SIG_A_E:
  2477. {
  2478. uint8_t *l_sig_a_info = NULL;
  2479. uint8_t rate = 0;
  2480. status = HAL_MON_MACTX_L_SIG_A;
  2481. l_sig_a_info = (uint8_t *)tx_tlv +
  2482. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2483. RATE);
  2484. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2485. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2486. RATE);
  2487. switch (rate) {
  2488. case 8:
  2489. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  2490. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2491. break;
  2492. case 9:
  2493. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  2494. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2495. break;
  2496. case 10:
  2497. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  2498. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2499. break;
  2500. case 11:
  2501. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  2502. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2503. break;
  2504. case 12:
  2505. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  2506. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2507. break;
  2508. case 13:
  2509. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  2510. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2511. break;
  2512. case 14:
  2513. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  2514. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2515. break;
  2516. case 15:
  2517. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  2518. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  2519. break;
  2520. default:
  2521. break;
  2522. }
  2523. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  2524. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2525. TXMON_HAL_STATUS(ppdu_info,
  2526. l_sig_a_info) = *((uint32_t *)l_sig_a_info);
  2527. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  2528. break;
  2529. }
  2530. case WIFIMACTX_L_SIG_B_E:
  2531. {
  2532. uint8_t *l_sig_b_info = NULL;
  2533. uint8_t rate = 0;
  2534. status = HAL_MON_MACTX_L_SIG_B;
  2535. l_sig_b_info = (uint8_t *)tx_tlv +
  2536. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2537. RATE);
  2538. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2539. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2540. RATE);
  2541. switch (rate) {
  2542. case 1:
  2543. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  2544. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2545. break;
  2546. case 2:
  2547. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  2548. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2549. break;
  2550. case 3:
  2551. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  2552. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2553. break;
  2554. case 4:
  2555. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  2556. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2557. break;
  2558. case 5:
  2559. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  2560. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2561. break;
  2562. case 6:
  2563. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  2564. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2565. break;
  2566. case 7:
  2567. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  2568. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2569. break;
  2570. default:
  2571. break;
  2572. }
  2573. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  2574. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2575. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  2576. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  2577. break;
  2578. }
  2579. case WIFIMACTX_HT_SIG_E:
  2580. {
  2581. uint8_t mcs = 0;
  2582. uint8_t bw = 0;
  2583. uint8_t is_stbc = 0;
  2584. uint8_t coding = 0;
  2585. uint8_t gi = 0;
  2586. status = HAL_MON_MACTX_HT_SIG;
  2587. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  2588. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  2589. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  2590. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  2591. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  2592. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2593. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2594. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  2595. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  2596. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  2597. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2598. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2599. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  2600. break;
  2601. }
  2602. case WIFIMACTX_VHT_SIG_A_E:
  2603. {
  2604. uint8_t bandwidth = 0;
  2605. uint8_t is_stbc = 0;
  2606. uint8_t group_id = 0;
  2607. uint32_t nss_comb = 0;
  2608. uint8_t nss_su = 0;
  2609. uint8_t nss_mu[4] = {0};
  2610. uint8_t sgi = 0;
  2611. uint8_t coding = 0;
  2612. uint8_t mcs = 0;
  2613. uint8_t beamformed = 0;
  2614. uint8_t partial_aid = 0;
  2615. status = HAL_MON_MACTX_VHT_SIG_A;
  2616. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  2617. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2618. BANDWIDTH);
  2619. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2620. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2621. STBC);
  2622. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  2623. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2624. GROUP_ID);
  2625. /* nss_comb is su nss, MU nss and partial AID */
  2626. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  2627. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2628. N_STS);
  2629. /* if it is SU */
  2630. nss_su = (nss_comb & 0x7) + 1;
  2631. /* partial aid - applicable only for SU */
  2632. partial_aid = (nss_comb >> 3) & 0x1F;
  2633. /* if it is MU */
  2634. nss_mu[0] = (nss_comb & 0x7) + 1;
  2635. nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1;
  2636. nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1;
  2637. nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1;
  2638. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  2639. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2640. GI_SETTING);
  2641. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2642. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2643. SU_MU_CODING);
  2644. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2645. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2646. MCS);
  2647. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  2648. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2649. BEAMFORMED);
  2650. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2651. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2652. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  2653. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  2654. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2655. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2656. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  2657. if (group_id == 0 || group_id == 63) {
  2658. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2659. HAL_RX_TYPE_SU;
  2660. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2661. TXMON_HAL_STATUS(ppdu_info, nss) =
  2662. nss_su & VHT_SIG_SU_NSS_MASK;
  2663. TXMON_HAL_USER(ppdu_info, user_id,
  2664. vht_flag_values3[0]) = ((mcs << 4) |
  2665. nss_su);
  2666. } else {
  2667. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2668. HAL_RX_TYPE_MU_MIMO;
  2669. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2670. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  2671. nss_su & VHT_SIG_SU_NSS_MASK;
  2672. TXMON_HAL_USER(ppdu_info, user_id,
  2673. vht_flag_values3[0]) = ((mcs << 4) |
  2674. nss_su);
  2675. TXMON_HAL_USER(ppdu_info, user_id,
  2676. vht_flag_values3[1]) = ((mcs << 4) |
  2677. nss_mu[1]);
  2678. TXMON_HAL_USER(ppdu_info, user_id,
  2679. vht_flag_values3[2]) = ((mcs << 4) |
  2680. nss_mu[2]);
  2681. TXMON_HAL_USER(ppdu_info, user_id,
  2682. vht_flag_values3[3]) = ((mcs << 4) |
  2683. nss_mu[3]);
  2684. }
  2685. /* TODO: loop over multiple user */
  2686. TXMON_HAL_USER(ppdu_info, user_id,
  2687. vht_flag_values2) = bandwidth;
  2688. TXMON_HAL_USER(ppdu_info, user_id,
  2689. vht_flag_values4) = coding;
  2690. TXMON_HAL_USER(ppdu_info, user_id,
  2691. vht_flag_values5) = group_id;
  2692. TXMON_HAL_USER(ppdu_info, user_id,
  2693. vht_flag_values6) = partial_aid;
  2694. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  2695. break;
  2696. }
  2697. case WIFIMACTX_VHT_SIG_B_MU160_E:
  2698. {
  2699. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  2700. break;
  2701. }
  2702. case WIFIMACTX_VHT_SIG_B_MU80_E:
  2703. {
  2704. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  2705. break;
  2706. }
  2707. case WIFIMACTX_VHT_SIG_B_MU40_E:
  2708. {
  2709. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  2710. break;
  2711. }
  2712. case WIFIMACTX_VHT_SIG_B_MU20_E:
  2713. {
  2714. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  2715. break;
  2716. }
  2717. case WIFIMACTX_VHT_SIG_B_SU160_E:
  2718. {
  2719. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  2720. break;
  2721. }
  2722. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2723. {
  2724. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2725. break;
  2726. }
  2727. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2728. {
  2729. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2730. break;
  2731. }
  2732. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2733. {
  2734. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2735. break;
  2736. }
  2737. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2738. {
  2739. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2740. break;
  2741. }
  2742. case WIFIMACTX_USER_DESC_PER_USER_E:
  2743. {
  2744. hal_txmon_parse_user_desc_per_user(tx_tlv, user_id, ppdu_info);
  2745. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2746. break;
  2747. }
  2748. case WIFIMACTX_USER_DESC_COMMON_E:
  2749. {
  2750. hal_txmon_parse_user_desc_common(tx_tlv, user_id, ppdu_info);
  2751. /* copy per user info to all user */
  2752. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2753. break;
  2754. }
  2755. case WIFIMACTX_PHY_DESC_E:
  2756. {
  2757. /* pkt_type - preamble type */
  2758. uint32_t pkt_type = 0;
  2759. uint8_t bandwidth = 0;
  2760. uint8_t is_stbc = 0;
  2761. uint8_t is_triggered = 0;
  2762. uint8_t gi = 0;
  2763. uint8_t he_ppdu_subtype = 0;
  2764. uint32_t ltf_size = 0;
  2765. uint32_t he_data1 = 0;
  2766. uint32_t he_data2 = 0;
  2767. uint32_t he_data3 = 0;
  2768. uint32_t he_data5 = 0;
  2769. uint16_t he_mu_flag_1 = 0;
  2770. uint16_t he_mu_flag_2 = 0;
  2771. uint16_t num_users = 0;
  2772. uint8_t i = 0;
  2773. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2774. status = HAL_MON_MACTX_PHY_DESC;
  2775. num_users = TXMON_HAL(ppdu_info, num_users);
  2776. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2777. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2778. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2779. TRIGGERED);
  2780. if (!is_triggered) {
  2781. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2782. BANDWIDTH);
  2783. } else {
  2784. /*
  2785. * is_triggered, bw is minimum of AP pkt bw
  2786. * or STA bw
  2787. */
  2788. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2789. AP_PKT_BW);
  2790. }
  2791. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2792. CP_SETTING);
  2793. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2794. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2795. HE_PPDU_SUBTYPE);
  2796. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2797. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2798. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2799. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2800. switch (ppdu_info->rx_status.preamble_type) {
  2801. case TXMON_PKT_TYPE_11N_MM:
  2802. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2803. TXMON_HAL_STATUS(ppdu_info,
  2804. rtap_flags) |= HT_SGI_PRESENT;
  2805. break;
  2806. case TXMON_PKT_TYPE_11AC:
  2807. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2808. break;
  2809. case TXMON_PKT_TYPE_11AX:
  2810. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2811. break;
  2812. default:
  2813. break;
  2814. }
  2815. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2816. break;
  2817. /* update he flags */
  2818. /* PPDU FORMAT */
  2819. switch (he_ppdu_subtype) {
  2820. case TXMON_HE_SUBTYPE_SU:
  2821. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2822. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2823. break;
  2824. case TXMON_HE_SUBTYPE_TRIG:
  2825. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2826. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2827. break;
  2828. case TXMON_HE_SUBTYPE_MU:
  2829. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2830. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2831. break;
  2832. case TXMON_HE_SUBTYPE_EXT_SU:
  2833. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2834. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2835. break;
  2836. };
  2837. /* STBC */
  2838. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2839. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2840. /* GI */
  2841. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2842. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2843. /* Data BW and RU allocation */
  2844. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2845. he_data5 = (he_data5 & 0xFFF0) | bandwidth;
  2846. he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2847. he_data5 |= ((1 + ltf_size) <<
  2848. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT);
  2849. TXMON_HAL_STATUS(ppdu_info,
  2850. he_mu_flags) = IS_MULTI_USERS(num_users);
  2851. /* MAC TX PHY DESC is not a user tlv */
  2852. for (i = 0; i < num_users; i++) {
  2853. TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1;
  2854. TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2;
  2855. TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3;
  2856. TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5;
  2857. /* HE MU flags */
  2858. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2859. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2860. }
  2861. break;
  2862. }
  2863. case WIFICOEX_RX_STATUS_E:
  2864. {
  2865. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2866. break;
  2867. }
  2868. case WIFIRX_PPDU_ACK_REPORT_E:
  2869. {
  2870. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2871. break;
  2872. }
  2873. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2874. {
  2875. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2876. break;
  2877. }
  2878. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2879. {
  2880. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2881. break;
  2882. }
  2883. case WIFITXPCU_PHYTX_DEBUG32_E:
  2884. {
  2885. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  2886. break;
  2887. }
  2888. case WIFITXPCU_PREAMBLE_DONE_E:
  2889. {
  2890. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  2891. break;
  2892. }
  2893. case WIFIRX_PHY_SLEEP_E:
  2894. {
  2895. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  2896. break;
  2897. }
  2898. case WIFIRX_FRAME_BITMAP_REQ_E:
  2899. {
  2900. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  2901. break;
  2902. }
  2903. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  2904. {
  2905. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  2906. break;
  2907. }
  2908. case WIFIRX_TRIG_INFO_E:
  2909. {
  2910. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  2911. break;
  2912. }
  2913. case WIFIEXPECTED_RESPONSE_E:
  2914. {
  2915. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  2916. break;
  2917. }
  2918. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  2919. {
  2920. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  2921. break;
  2922. }
  2923. case WIFIFW2SW_MON_E:
  2924. {
  2925. /* parse fw2sw tlv */
  2926. hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info);
  2927. status = HAL_MON_TX_FW2SW;
  2928. SHOW_DEFINED(WIFIFW2SW_MON_E);
  2929. break;
  2930. }
  2931. }
  2932. return status;
  2933. }
  2934. #endif /* QCA_MONITOR_2_0_SUPPORT */
  2935. #ifdef REO_SHARED_QREF_TABLE_EN
  2936. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  2937. {
  2938. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2939. uint32_t reg_val = 0;
  2940. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2941. * of 37 peer/tids
  2942. */
  2943. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  2944. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  2945. HAL_REG_WRITE(hal,
  2946. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2947. reg_val);
  2948. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2949. * of 37 peer/tids
  2950. */
  2951. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  2952. HAL_REG_WRITE(hal,
  2953. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2954. reg_val);
  2955. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  2956. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  2957. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  2958. }
  2959. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  2960. * LUT shared by SW and HW at the index given by peer id
  2961. * and tid.
  2962. *
  2963. * @hal_soc: hal soc pointer
  2964. * @reo_qref_addr: pointer to index pointed to be peer_id
  2965. * and tid
  2966. * @tid: tid queue number
  2967. * @hw_qdesc_paddr: reo queue addr
  2968. */
  2969. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  2970. uint16_t peer_id,
  2971. int tid,
  2972. qdf_dma_addr_t hw_qdesc_paddr)
  2973. {
  2974. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2975. struct rx_reo_queue_reference *reo_qref;
  2976. uint32_t peer_tid_idx;
  2977. /* Plug hw_desc_addr in Host reo queue reference table */
  2978. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  2979. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  2980. DP_MAX_TIDS) + tid;
  2981. reo_qref = (struct rx_reo_queue_reference *)
  2982. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  2983. } else {
  2984. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  2985. reo_qref = (struct rx_reo_queue_reference *)
  2986. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  2987. }
  2988. reo_qref->rx_reo_queue_desc_addr_31_0 =
  2989. hw_qdesc_paddr & 0xffffffff;
  2990. reo_qref->rx_reo_queue_desc_addr_39_32 =
  2991. (hw_qdesc_paddr & 0xff00000000) >> 32;
  2992. if (hw_qdesc_paddr != 0)
  2993. reo_qref->receive_queue_number = tid;
  2994. else
  2995. reo_qref->receive_queue_number = 0;
  2996. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  2997. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  2998. "rx_reo_queue_desc_addr_31_0: %x,"
  2999. "rx_reo_queue_desc_addr_39_32: %x",
  3000. (void *)hw_qdesc_paddr, tid, reo_qref,
  3001. reo_qref->rx_reo_queue_desc_addr_31_0,
  3002. reo_qref->rx_reo_queue_desc_addr_39_32);
  3003. }
  3004. /**
  3005. * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue
  3006. * reference table shared between SW and HW and initialize in Qdesc Base0
  3007. * base1 registers provided by HW.
  3008. *
  3009. * @hal_soc_hdl: HAL Soc handle
  3010. * @reo_qref: REO queue reference table
  3011. *
  3012. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  3013. */
  3014. static QDF_STATUS
  3015. hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl,
  3016. struct reo_queue_ref_table *reo_qref)
  3017. {
  3018. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3019. reo_qref->reo_qref_table_en = 1;
  3020. reo_qref->mlo_reo_qref_table_vaddr =
  3021. (uint64_t *)qdf_mem_alloc_consistent(
  3022. hal->qdf_dev, hal->qdf_dev->dev,
  3023. REO_QUEUE_REF_ML_TABLE_SIZE,
  3024. &reo_qref->mlo_reo_qref_table_paddr);
  3025. if (!reo_qref->mlo_reo_qref_table_vaddr)
  3026. return QDF_STATUS_E_NOMEM;
  3027. reo_qref->non_mlo_reo_qref_table_vaddr =
  3028. (uint64_t *)qdf_mem_alloc_consistent(
  3029. hal->qdf_dev, hal->qdf_dev->dev,
  3030. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  3031. &reo_qref->non_mlo_reo_qref_table_paddr);
  3032. if (!reo_qref->non_mlo_reo_qref_table_vaddr) {
  3033. qdf_mem_free_consistent(
  3034. hal->qdf_dev, hal->qdf_dev->dev,
  3035. REO_QUEUE_REF_ML_TABLE_SIZE,
  3036. reo_qref->mlo_reo_qref_table_vaddr,
  3037. reo_qref->mlo_reo_qref_table_paddr,
  3038. 0);
  3039. reo_qref->mlo_reo_qref_table_vaddr = NULL;
  3040. return QDF_STATUS_E_NOMEM;
  3041. }
  3042. hal_verbose_debug("MLO table start paddr:%pK,"
  3043. "Non-MLO table start paddr:%pK,"
  3044. "MLO table start vaddr: %pK,"
  3045. "Non MLO table start vaddr: %pK",
  3046. (void *)reo_qref->mlo_reo_qref_table_paddr,
  3047. (void *)reo_qref->non_mlo_reo_qref_table_paddr,
  3048. reo_qref->mlo_reo_qref_table_vaddr,
  3049. reo_qref->non_mlo_reo_qref_table_vaddr);
  3050. return QDF_STATUS_SUCCESS;
  3051. }
  3052. /**
  3053. * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and
  3054. * write start addr of MLO and Non MLO table in HW
  3055. *
  3056. * @hal_soc_hdl: HAL Soc handle
  3057. * @qref_reset: reset qref LUT
  3058. *
  3059. * Return: None
  3060. */
  3061. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
  3062. int qref_reset)
  3063. {
  3064. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3065. if (qref_reset) {
  3066. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  3067. REO_QUEUE_REF_ML_TABLE_SIZE);
  3068. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  3069. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  3070. }
  3071. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  3072. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  3073. * upper 32bits only
  3074. */
  3075. HAL_REG_WRITE(hal,
  3076. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3077. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  3078. HAL_REG_WRITE(hal,
  3079. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3080. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  3081. HAL_REG_WRITE(hal,
  3082. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3083. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE,
  3084. 1));
  3085. HAL_REG_WRITE(hal,
  3086. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  3087. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  3088. 0x1fff));
  3089. }
  3090. /**
  3091. * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue
  3092. * reference table shared between SW and HW
  3093. *
  3094. * @hal_soc_hdl: HAL Soc handle
  3095. *
  3096. * Return: None
  3097. */
  3098. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  3099. {
  3100. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3101. HAL_REG_WRITE(hal,
  3102. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3103. 0);
  3104. HAL_REG_WRITE(hal,
  3105. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3106. 0);
  3107. }
  3108. #endif
  3109. /**
  3110. * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing
  3111. * @hal_soc_hdl: HAL SoC context
  3112. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  3113. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  3114. *
  3115. * Return: void
  3116. */
  3117. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  3118. static inline void
  3119. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3120. enum hal_tx_vdev_mismatch_notify
  3121. config)
  3122. {
  3123. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3124. uint32_t reg_addr, reg_val = 0;
  3125. uint32_t val = 0;
  3126. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3127. val = HAL_REG_READ(hal_soc, reg_addr);
  3128. /* reset the corresponding bits in register */
  3129. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  3130. /* set config value */
  3131. reg_val = val | (config <<
  3132. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  3133. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3134. }
  3135. #else
  3136. static inline void
  3137. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3138. enum hal_tx_vdev_mismatch_notify
  3139. config)
  3140. {
  3141. }
  3142. #endif
  3143. /**
  3144. * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing
  3145. * @hal_soc_hdl: HAL SoC context
  3146. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  3147. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  3148. *
  3149. * Return: void
  3150. */
  3151. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  3152. defined(WLAN_MCAST_MLO)
  3153. static inline void
  3154. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3155. hal_soc_handle_t hal_soc_hdl,
  3156. enum hal_tx_mcast_mlo_reinject_notify config)
  3157. {
  3158. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3159. uint32_t reg_addr, reg_val = 0;
  3160. uint32_t val = 0;
  3161. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3162. val = HAL_REG_READ(hal_soc, reg_addr);
  3163. /* reset the corresponding bits in register */
  3164. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  3165. /* set config value */
  3166. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  3167. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3168. }
  3169. #else
  3170. static inline void
  3171. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3172. hal_soc_handle_t hal_soc_hdl,
  3173. enum hal_tx_mcast_mlo_reinject_notify config)
  3174. {
  3175. }
  3176. #endif
  3177. /**
  3178. * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout
  3179. *
  3180. * @hal_soc_hdl: Opaque HAL SOC handle
  3181. * @ac: Access category
  3182. * @value: window size to get
  3183. */
  3184. static inline
  3185. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3186. uint8_t ac, uint32_t *value)
  3187. {
  3188. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3189. switch (ac) {
  3190. case WME_AC_BE:
  3191. *value = HAL_REG_READ(soc,
  3192. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3193. REO_REG_REG_BASE)) / 1000;
  3194. break;
  3195. case WME_AC_BK:
  3196. *value = HAL_REG_READ(soc,
  3197. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3198. REO_REG_REG_BASE)) / 1000;
  3199. break;
  3200. case WME_AC_VI:
  3201. *value = HAL_REG_READ(soc,
  3202. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3203. REO_REG_REG_BASE)) / 1000;
  3204. break;
  3205. case WME_AC_VO:
  3206. *value = HAL_REG_READ(soc,
  3207. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3208. REO_REG_REG_BASE)) / 1000;
  3209. break;
  3210. default:
  3211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3212. "Invalid AC: %d\n", ac);
  3213. }
  3214. }
  3215. /**
  3216. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  3217. * buffer list provided
  3218. *
  3219. * @soc: Opaque HAL SOC handle
  3220. * @scatter_bufs_base_paddr: Array of physical base addresses
  3221. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  3222. * @num_scatter_bufs: Number of scatter buffers in the above lists
  3223. * @scatter_buf_size: Size of each scatter buffer
  3224. * @last_buf_end_offset: Offset to the last entry
  3225. * @num_entries: Total entries of all scatter bufs
  3226. *
  3227. * Return: None
  3228. */
  3229. static inline void
  3230. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  3231. qdf_dma_addr_t scatter_bufs_base_paddr[],
  3232. void *scatter_bufs_base_vaddr[],
  3233. uint32_t num_scatter_bufs,
  3234. uint32_t scatter_buf_size,
  3235. uint32_t last_buf_end_offset,
  3236. uint32_t num_entries)
  3237. {
  3238. int i;
  3239. uint32_t *prev_buf_link_ptr = NULL;
  3240. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  3241. uint32_t val;
  3242. /* Link the scatter buffers */
  3243. for (i = 0; i < num_scatter_bufs; i++) {
  3244. if (i > 0) {
  3245. prev_buf_link_ptr[0] =
  3246. scatter_bufs_base_paddr[i] & 0xffffffff;
  3247. prev_buf_link_ptr[1] = HAL_SM(
  3248. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3249. BASE_ADDRESS_39_32,
  3250. ((uint64_t)(scatter_bufs_base_paddr[i])
  3251. >> 32)) | HAL_SM(
  3252. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3253. ADDRESS_MATCH_TAG,
  3254. ADDRESS_MATCH_TAG_VAL);
  3255. }
  3256. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  3257. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  3258. }
  3259. /* TBD: Register programming partly based on MLD & the rest based on
  3260. * inputs from HW team. Not complete yet.
  3261. */
  3262. reg_scatter_buf_size = (scatter_buf_size -
  3263. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  3264. reg_tot_scatter_buf_size = ((scatter_buf_size -
  3265. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  3266. HAL_REG_WRITE(soc,
  3267. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  3268. WBM_REG_REG_BASE),
  3269. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  3270. reg_scatter_buf_size) |
  3271. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  3272. 0x1));
  3273. HAL_REG_WRITE(soc,
  3274. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  3275. WBM_REG_REG_BASE),
  3276. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  3277. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  3278. reg_tot_scatter_buf_size));
  3279. HAL_REG_WRITE(soc,
  3280. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  3281. WBM_REG_REG_BASE),
  3282. scatter_bufs_base_paddr[0] & 0xffffffff);
  3283. HAL_REG_WRITE(soc,
  3284. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3285. WBM_REG_REG_BASE),
  3286. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  3287. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  3288. HAL_REG_WRITE(soc,
  3289. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3290. WBM_REG_REG_BASE),
  3291. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3292. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  3293. >> 32)) |
  3294. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3295. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  3296. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  3297. * with the upper bits of link pointer. The above write sets this field
  3298. * to zero and we are also setting the upper bits of link pointers to
  3299. * zero while setting up the link list of scatter buffers above
  3300. */
  3301. /* Setup head and tail pointers for the idle list */
  3302. HAL_REG_WRITE(soc,
  3303. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3304. WBM_REG_REG_BASE),
  3305. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  3306. HAL_REG_WRITE(soc,
  3307. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  3308. WBM_REG_REG_BASE),
  3309. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3310. BUFFER_ADDRESS_39_32,
  3311. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  3312. >> 32)) |
  3313. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3314. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  3315. HAL_REG_WRITE(soc,
  3316. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3317. WBM_REG_REG_BASE),
  3318. scatter_bufs_base_paddr[0] & 0xffffffff);
  3319. HAL_REG_WRITE(soc,
  3320. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  3321. WBM_REG_REG_BASE),
  3322. scatter_bufs_base_paddr[0] & 0xffffffff);
  3323. HAL_REG_WRITE(soc,
  3324. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  3325. WBM_REG_REG_BASE),
  3326. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3327. BUFFER_ADDRESS_39_32,
  3328. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  3329. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3330. TAIL_POINTER_OFFSET, 0));
  3331. HAL_REG_WRITE(soc,
  3332. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  3333. WBM_REG_REG_BASE),
  3334. 2 * num_entries);
  3335. /* Set RING_ID_DISABLE */
  3336. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  3337. /*
  3338. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  3339. * check the presence of the bit before toggling it.
  3340. */
  3341. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  3342. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  3343. #endif
  3344. HAL_REG_WRITE(soc,
  3345. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  3346. val);
  3347. }
  3348. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3349. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  3350. #endif
  3351. /**
  3352. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  3353. * for REO/WBM
  3354. * @hal_soc_hdl: HAL soc handle
  3355. * @cc_cfg: structure pointer for HW cookie conversion configuration
  3356. *
  3357. * Return: None
  3358. */
  3359. static inline
  3360. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  3361. struct hal_hw_cc_config *cc_cfg)
  3362. {
  3363. uint32_t reg_addr, reg_val = 0;
  3364. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3365. /* REO CFG */
  3366. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  3367. reg_val = cc_cfg->lut_base_addr_31_0;
  3368. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3369. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  3370. reg_val = 0;
  3371. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3372. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  3373. cc_cfg->cc_global_en);
  3374. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3375. SW_COOKIE_CONVERT_ENABLE,
  3376. cc_cfg->cc_global_en);
  3377. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3378. PAGE_ALIGNMENT,
  3379. cc_cfg->page_4k_align);
  3380. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3381. COOKIE_OFFSET_MSB,
  3382. cc_cfg->cookie_offset_msb);
  3383. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3384. COOKIE_PAGE_MSB,
  3385. cc_cfg->cookie_page_msb);
  3386. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3387. CMEM_LUT_BASE_ADDR_39_32,
  3388. cc_cfg->lut_base_addr_39_32);
  3389. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3390. /* WBM CFG */
  3391. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  3392. reg_val = cc_cfg->lut_base_addr_31_0;
  3393. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3394. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  3395. reg_val = 0;
  3396. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3397. PAGE_ALIGNMENT,
  3398. cc_cfg->page_4k_align);
  3399. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3400. COOKIE_OFFSET_MSB,
  3401. cc_cfg->cookie_offset_msb);
  3402. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3403. COOKIE_PAGE_MSB,
  3404. cc_cfg->cookie_page_msb);
  3405. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3406. CMEM_LUT_BASE_ADDR_39_32,
  3407. cc_cfg->lut_base_addr_39_32);
  3408. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3409. /*
  3410. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  3411. */
  3412. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  3413. reg_val = 0;
  3414. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3415. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  3416. cc_cfg->cc_global_en);
  3417. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3418. WBM2SW6_COOKIE_CONVERSION_EN,
  3419. cc_cfg->wbm2sw6_cc_en);
  3420. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3421. WBM2SW5_COOKIE_CONVERSION_EN,
  3422. cc_cfg->wbm2sw5_cc_en);
  3423. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3424. WBM2SW4_COOKIE_CONVERSION_EN,
  3425. cc_cfg->wbm2sw4_cc_en);
  3426. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3427. WBM2SW3_COOKIE_CONVERSION_EN,
  3428. cc_cfg->wbm2sw3_cc_en);
  3429. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3430. WBM2SW2_COOKIE_CONVERSION_EN,
  3431. cc_cfg->wbm2sw2_cc_en);
  3432. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3433. WBM2SW1_COOKIE_CONVERSION_EN,
  3434. cc_cfg->wbm2sw1_cc_en);
  3435. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3436. WBM2SW0_COOKIE_CONVERSION_EN,
  3437. cc_cfg->wbm2sw0_cc_en);
  3438. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3439. WBM2FW_COOKIE_CONVERSION_EN,
  3440. cc_cfg->wbm2fw_cc_en);
  3441. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3442. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  3443. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  3444. reg_val = 0;
  3445. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3446. COOKIE_DEBUG_SEL,
  3447. cc_cfg->cc_global_en);
  3448. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3449. COOKIE_CONV_INDICATION_EN,
  3450. cc_cfg->cc_global_en);
  3451. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3452. ERROR_PATH_COOKIE_CONV_EN,
  3453. cc_cfg->error_path_cookie_conv_en);
  3454. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3455. RELEASE_PATH_COOKIE_CONV_EN,
  3456. cc_cfg->release_path_cookie_conv_en);
  3457. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3458. #endif
  3459. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3460. /*
  3461. * To enable indication for HW cookie conversion done or not for
  3462. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  3463. * bit spare_control[15] should be set.
  3464. */
  3465. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  3466. reg_val = HAL_REG_READ(soc, reg_addr);
  3467. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  3468. SPARE_CONTROL,
  3469. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  3470. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3471. #endif
  3472. }
  3473. /**
  3474. * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout
  3475. * @hal_soc_hdl: Opaque HAL SOC handle
  3476. * @ac: Access category
  3477. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  3478. * @value: Input value to set
  3479. */
  3480. static inline
  3481. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3482. uint8_t ac, uint32_t value)
  3483. {
  3484. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3485. switch (ac) {
  3486. case WME_AC_BE:
  3487. HAL_REG_WRITE(soc,
  3488. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3489. REO_REG_REG_BASE),
  3490. value * 1000);
  3491. break;
  3492. case WME_AC_BK:
  3493. HAL_REG_WRITE(soc,
  3494. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3495. REO_REG_REG_BASE),
  3496. value * 1000);
  3497. break;
  3498. case WME_AC_VI:
  3499. HAL_REG_WRITE(soc,
  3500. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3501. REO_REG_REG_BASE),
  3502. value * 1000);
  3503. break;
  3504. case WME_AC_VO:
  3505. HAL_REG_WRITE(soc,
  3506. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3507. REO_REG_REG_BASE),
  3508. value * 1000);
  3509. break;
  3510. default:
  3511. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3512. "Invalid AC: %d\n", ac);
  3513. }
  3514. }
  3515. /**
  3516. * hal_tx_populate_bank_register_be() - populate the bank register with
  3517. * the software configs.
  3518. * @hal_soc_hdl: HAL soc handle
  3519. * @config: bank config
  3520. * @bank_id: bank id to be configured
  3521. *
  3522. * Returns: None
  3523. */
  3524. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  3525. static inline void
  3526. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3527. union hal_tx_bank_config *config,
  3528. uint8_t bank_id)
  3529. {
  3530. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3531. uint32_t reg_addr, reg_val = 0;
  3532. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3533. bank_id);
  3534. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3535. reg_val |= (config->encap_type <<
  3536. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3537. reg_val |= (config->encrypt_type <<
  3538. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3539. reg_val |= (config->src_buffer_swap <<
  3540. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3541. reg_val |= (config->link_meta_swap <<
  3542. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3543. reg_val |= (config->index_lookup_enable <<
  3544. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3545. reg_val |= (config->addrx_en <<
  3546. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3547. reg_val |= (config->addry_en <<
  3548. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3549. reg_val |= (config->mesh_enable <<
  3550. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3551. reg_val |= (config->vdev_id_check_en <<
  3552. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3553. reg_val |= (config->pmac_id <<
  3554. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3555. reg_val |= (config->mcast_pkt_ctrl <<
  3556. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  3557. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3558. }
  3559. #else
  3560. static inline void
  3561. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3562. union hal_tx_bank_config *config,
  3563. uint8_t bank_id)
  3564. {
  3565. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3566. uint32_t reg_addr, reg_val = 0;
  3567. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3568. bank_id);
  3569. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3570. reg_val |= (config->encap_type <<
  3571. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3572. reg_val |= (config->encrypt_type <<
  3573. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3574. reg_val |= (config->src_buffer_swap <<
  3575. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3576. reg_val |= (config->link_meta_swap <<
  3577. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3578. reg_val |= (config->index_lookup_enable <<
  3579. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3580. reg_val |= (config->addrx_en <<
  3581. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3582. reg_val |= (config->addry_en <<
  3583. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3584. reg_val |= (config->mesh_enable <<
  3585. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3586. reg_val |= (config->vdev_id_check_en <<
  3587. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3588. reg_val |= (config->pmac_id <<
  3589. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3590. reg_val |= (config->dscp_tid_map_id <<
  3591. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  3592. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3593. }
  3594. #endif
  3595. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  3596. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  3597. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  3598. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  3599. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  3600. /**
  3601. * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value
  3602. * @hal_soc_hdl: HAL SoC context
  3603. * @vdev_id: vdev identifier
  3604. * @mcast_ctrl_val: mcast ctrl value for this VAP
  3605. *
  3606. * Return: void
  3607. */
  3608. static inline void
  3609. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3610. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3611. {
  3612. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3613. uint32_t reg_addr, reg_val = 0;
  3614. uint32_t val;
  3615. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  3616. uint8_t index_in_reg =
  3617. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  3618. reg_addr =
  3619. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  3620. reg_idx);
  3621. val = HAL_REG_READ(hal_soc, reg_addr);
  3622. /* mask out other stored value */
  3623. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  3624. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  3625. reg_val = val |
  3626. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  3627. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  3628. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3629. }
  3630. #else
  3631. static inline void
  3632. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3633. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3634. {
  3635. }
  3636. #endif
  3637. #endif /* _HAL_BE_GENERIC_API_H_ */