dp_be_tx.c 57 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "hal_tx.h"
  25. #include <hal_be_api.h>
  26. #include <hal_be_tx.h>
  27. #include <dp_htt.h>
  28. #include "dp_internal.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  33. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_mutex_create(lock)
  34. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_mutex_destroy(lock)
  35. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_mutex_acquire(lock)
  36. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_mutex_release(lock)
  37. #else
  38. #define DP_TX_BANK_LOCK_CREATE(lock) qdf_spinlock_create(lock)
  39. #define DP_TX_BANK_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
  40. #define DP_TX_BANK_LOCK_ACQUIRE(lock) qdf_spin_lock_bh(lock)
  41. #define DP_TX_BANK_LOCK_RELEASE(lock) qdf_spin_unlock_bh(lock)
  42. #endif
  43. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  44. #ifdef WLAN_MCAST_MLO
  45. /* MLO peer id for reinject*/
  46. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  47. #define MAX_GSN_NUM 0x0FFF
  48. #ifdef QCA_MULTIPASS_SUPPORT
  49. #define INVALID_VLAN_ID 0xFFFF
  50. #define MULTIPASS_WITH_VLAN_ID 0xFFFE
  51. /**
  52. * struct dp_mlo_mpass_buf - Multipass buffer
  53. * @vlan_id: vlan_id of frame
  54. * @nbuf: pointer to skb buf
  55. */
  56. struct dp_mlo_mpass_buf {
  57. uint16_t vlan_id;
  58. qdf_nbuf_t nbuf;
  59. };
  60. #endif
  61. #endif
  62. #endif
  63. #define DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(_var) \
  64. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var)
  65. #define DP_TX_WBM_COMPLETION_V3_VALID_GET(_var) \
  66. HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var)
  67. #define DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(_var) \
  68. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var)
  69. #define DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(_var) \
  70. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var)
  71. #define DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(_var) \
  72. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var)
  73. #define DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(_var) \
  74. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var)
  75. #define DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(_var) \
  76. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var)
  77. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  78. #ifdef DP_TX_COMP_RING_DESC_SANITY_CHECK
  79. /*
  80. * Value to mark ring desc is invalidated by buffer_virt_addr_63_32 field
  81. * of WBM2SW ring Desc.
  82. */
  83. #define DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE 0x12121212
  84. /**
  85. * dp_tx_comp_desc_check_and_invalidate() - sanity check for ring desc and
  86. * invalidate it after each reaping
  87. * @tx_comp_hal_desc: ring desc virtual address
  88. * @r_tx_desc: pointer to current dp TX Desc pointer
  89. * @tx_desc_va: the original 64 bits Desc VA got from ring Desc
  90. * @hw_cc_done: HW cookie conversion done or not
  91. *
  92. * If HW CC is done, check the buffer_virt_addr_63_32 value to know if
  93. * ring Desc is stale or not. if HW CC is not done, then compare PA between
  94. * ring Desc and current TX desc.
  95. *
  96. * Return: QDF_STATUS_SUCCESS for success,
  97. * QDF_STATUS_E_PENDING for stale entry,
  98. * QDF_STATUS_E_INVAL for invalid entry.
  99. */
  100. static inline
  101. QDF_STATUS dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  102. struct dp_tx_desc_s **r_tx_desc,
  103. uint64_t tx_desc_va,
  104. bool hw_cc_done)
  105. {
  106. qdf_dma_addr_t desc_dma_addr;
  107. QDF_STATUS status = QDF_STATUS_SUCCESS;
  108. if (qdf_likely(hw_cc_done)) {
  109. /* Check upper 32 bits */
  110. if (DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE ==
  111. (tx_desc_va >> 32)) {
  112. *r_tx_desc = NULL;
  113. status = QDF_STATUS_E_PENDING;
  114. } else
  115. /* Invalidate the ring desc for 32 ~ 63 bits of VA */
  116. hal_tx_comp_set_desc_va_63_32(
  117. tx_comp_hal_desc,
  118. DP_TX_COMP_DESC_BUFF_VA_32BITS_HI_INVALIDATE);
  119. } else {
  120. /* Compare PA between ring desc and current TX desc stored */
  121. desc_dma_addr = hal_tx_comp_get_paddr(tx_comp_hal_desc);
  122. if (desc_dma_addr != (*r_tx_desc)->dma_addr) {
  123. *r_tx_desc = NULL;
  124. status = QDF_STATUS_E_INVAL;
  125. }
  126. }
  127. return status;
  128. }
  129. #else
  130. static inline
  131. QDF_STATUS dp_tx_comp_desc_check_and_invalidate(void *tx_comp_hal_desc,
  132. struct dp_tx_desc_s **r_tx_desc,
  133. uint64_t tx_desc_va,
  134. bool hw_cc_done)
  135. {
  136. return QDF_STATUS_SUCCESS;
  137. }
  138. #endif
  139. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  140. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  141. QDF_STATUS
  142. dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  143. void *tx_comp_hal_desc,
  144. struct dp_tx_desc_s **r_tx_desc)
  145. {
  146. uint32_t tx_desc_id;
  147. uint64_t tx_desc_va = 0;
  148. QDF_STATUS status;
  149. bool hw_cc_done =
  150. hal_tx_comp_get_cookie_convert_done(tx_comp_hal_desc);
  151. if (qdf_likely(hw_cc_done)) {
  152. /* HW cookie conversion done */
  153. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  154. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  155. } else {
  156. /* SW do cookie conversion to VA */
  157. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  158. *r_tx_desc =
  159. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  160. }
  161. status = dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  162. r_tx_desc, tx_desc_va,
  163. hw_cc_done);
  164. if (*r_tx_desc)
  165. (*r_tx_desc)->peer_id =
  166. dp_tx_comp_get_peer_id_be(soc,
  167. tx_comp_hal_desc);
  168. return status;
  169. }
  170. #else
  171. QDF_STATUS
  172. dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  173. void *tx_comp_hal_desc,
  174. struct dp_tx_desc_s **r_tx_desc)
  175. {
  176. uint64_t tx_desc_va;
  177. QDF_STATUS status;
  178. tx_desc_va = hal_tx_comp_get_desc_va(tx_comp_hal_desc);
  179. *r_tx_desc = (struct dp_tx_desc_s *)(uintptr_t)tx_desc_va;
  180. status = dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  181. r_tx_desc, tx_desc_va,
  182. true);
  183. if (*r_tx_desc)
  184. (*r_tx_desc)->peer_id =
  185. dp_tx_comp_get_peer_id_be(soc,
  186. tx_comp_hal_desc);
  187. return status;
  188. }
  189. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  190. #else
  191. QDF_STATUS
  192. dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
  193. void *tx_comp_hal_desc,
  194. struct dp_tx_desc_s **r_tx_desc)
  195. {
  196. uint32_t tx_desc_id;
  197. QDF_STATUS status;
  198. /* SW do cookie conversion to VA */
  199. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  200. *r_tx_desc =
  201. (struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
  202. status = dp_tx_comp_desc_check_and_invalidate(tx_comp_hal_desc,
  203. r_tx_desc, 0, false);
  204. if (*r_tx_desc)
  205. (*r_tx_desc)->peer_id =
  206. dp_tx_comp_get_peer_id_be(soc,
  207. tx_comp_hal_desc);
  208. return status;
  209. }
  210. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  211. static inline
  212. void dp_tx_process_mec_notify_be(struct dp_soc *soc, uint8_t *status)
  213. {
  214. struct dp_vdev *vdev;
  215. uint8_t vdev_id;
  216. uint32_t *htt_desc = (uint32_t *)status;
  217. dp_assert_always_internal(soc->mec_fw_offload);
  218. /*
  219. * Get vdev id from HTT status word in case of MEC
  220. * notification
  221. */
  222. vdev_id = DP_TX_WBM_COMPLETION_V3_VDEV_ID_GET(htt_desc[4]);
  223. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  224. return;
  225. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  226. DP_MOD_ID_HTT_COMP);
  227. if (!vdev)
  228. return;
  229. dp_tx_mec_handler(vdev, status);
  230. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  231. }
  232. void dp_tx_process_htt_completion_be(struct dp_soc *soc,
  233. struct dp_tx_desc_s *tx_desc,
  234. uint8_t *status,
  235. uint8_t ring_id)
  236. {
  237. uint8_t tx_status;
  238. struct dp_pdev *pdev;
  239. struct dp_vdev *vdev = NULL;
  240. struct hal_tx_completion_status ts = {0};
  241. uint32_t *htt_desc = (uint32_t *)status;
  242. struct dp_txrx_peer *txrx_peer;
  243. dp_txrx_ref_handle txrx_ref_handle = NULL;
  244. struct cdp_tid_tx_stats *tid_stats = NULL;
  245. struct htt_soc *htt_handle;
  246. uint8_t vdev_id;
  247. uint16_t peer_id;
  248. uint8_t xmit_type;
  249. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  250. htt_handle = (struct htt_soc *)soc->htt_handle;
  251. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  252. /*
  253. * There can be scenario where WBM consuming descriptor enqueued
  254. * from TQM2WBM first and TQM completion can happen before MEC
  255. * notification comes from FW2WBM. Avoid access any field of tx
  256. * descriptor in case of MEC notify.
  257. */
  258. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  259. return dp_tx_process_mec_notify_be(soc, status);
  260. /*
  261. * If the descriptor is already freed in vdev_detach,
  262. * continue to next descriptor
  263. */
  264. if (qdf_unlikely(!tx_desc->flags)) {
  265. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  266. tx_desc->id);
  267. return;
  268. }
  269. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  270. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  271. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  272. goto release_tx_desc;
  273. }
  274. pdev = tx_desc->pdev;
  275. if (qdf_unlikely(!pdev)) {
  276. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  277. dp_tx_comp_warn("tx_status: %u", tx_status);
  278. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  279. goto release_tx_desc;
  280. }
  281. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  282. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  283. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  284. goto release_tx_desc;
  285. }
  286. qdf_assert(tx_desc->pdev);
  287. vdev_id = tx_desc->vdev_id;
  288. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  289. DP_MOD_ID_HTT_COMP);
  290. if (qdf_unlikely(!vdev)) {
  291. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  292. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  293. goto release_tx_desc;
  294. }
  295. switch (tx_status) {
  296. case HTT_TX_FW2WBM_TX_STATUS_OK:
  297. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  298. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  299. {
  300. uint8_t tid;
  301. uint8_t transmit_cnt_valid = 0;
  302. if (DP_TX_WBM_COMPLETION_V3_VALID_GET(htt_desc[3])) {
  303. ts.peer_id =
  304. DP_TX_WBM_COMPLETION_V3_SW_PEER_ID_GET(
  305. htt_desc[3]);
  306. ts.tid =
  307. DP_TX_WBM_COMPLETION_V3_TID_NUM_GET(
  308. htt_desc[3]);
  309. } else {
  310. ts.peer_id = HTT_INVALID_PEER;
  311. ts.tid = HTT_INVALID_TID;
  312. }
  313. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  314. ts.ppdu_id =
  315. DP_TX_WBM_COMPLETION_V3_SCH_CMD_ID_GET(
  316. htt_desc[2]);
  317. ts.ack_frame_rssi =
  318. DP_TX_WBM_COMPLETION_V3_ACK_FRAME_RSSI_GET(
  319. htt_desc[2]);
  320. transmit_cnt_valid =
  321. DP_TX_WBM_COMPLETION_V3_TRANSMIT_CNT_VALID_GET(
  322. htt_desc[3]);
  323. if (transmit_cnt_valid)
  324. ts.transmit_cnt =
  325. HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(
  326. htt_desc[1]);
  327. ts.tsf = htt_desc[4];
  328. ts.first_msdu = 1;
  329. ts.last_msdu = 1;
  330. switch (tx_status) {
  331. case HTT_TX_FW2WBM_TX_STATUS_OK:
  332. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  333. break;
  334. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  335. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  336. break;
  337. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  338. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  339. break;
  340. }
  341. tid = ts.tid;
  342. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  343. tid = CDP_MAX_DATA_TIDS - 1;
  344. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  345. if (qdf_unlikely(pdev->delay_stats_flag) ||
  346. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  347. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  348. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  349. tid_stats->htt_status_cnt[tx_status]++;
  350. peer_id = dp_tx_comp_adjust_peer_id_be(soc, ts.peer_id);
  351. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  352. &txrx_ref_handle,
  353. DP_MOD_ID_HTT_COMP);
  354. if (qdf_likely(txrx_peer))
  355. dp_tx_update_peer_basic_stats(
  356. txrx_peer,
  357. qdf_nbuf_len(tx_desc->nbuf),
  358. tx_status,
  359. pdev->enhanced_stats_en);
  360. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  361. ring_id);
  362. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  363. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  364. if (qdf_likely(txrx_peer))
  365. dp_txrx_peer_unref_delete(txrx_ref_handle,
  366. DP_MOD_ID_HTT_COMP);
  367. break;
  368. }
  369. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  370. {
  371. uint8_t reinject_reason;
  372. reinject_reason =
  373. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(
  374. htt_desc[1]);
  375. dp_tx_reinject_handler(soc, vdev, tx_desc,
  376. status, reinject_reason);
  377. break;
  378. }
  379. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  380. {
  381. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  382. break;
  383. }
  384. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  385. {
  386. xmit_type = qdf_nbuf_get_vdev_xmit_type(tx_desc->nbuf);
  387. DP_STATS_INC(vdev,
  388. tx_i[xmit_type].dropped.fail_per_pkt_vdev_id_check,
  389. 1);
  390. goto release_tx_desc;
  391. }
  392. default:
  393. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  394. tx_status);
  395. goto release_tx_desc;
  396. }
  397. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  398. return;
  399. release_tx_desc:
  400. dp_tx_comp_free_buf(soc, tx_desc, false);
  401. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  402. if (vdev)
  403. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  404. }
  405. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  406. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  407. /**
  408. * dp_tx_get_rbm_id_be() - Get the RBM ID for data transmission completion.
  409. * @soc: DP soc structure pointer
  410. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  411. *
  412. * Return: RBM ID corresponding to TCL ring_id
  413. */
  414. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  415. uint8_t ring_id)
  416. {
  417. return 0;
  418. }
  419. #else
  420. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  421. uint8_t ring_id)
  422. {
  423. return (ring_id ? soc->wbm_sw0_bm_id + (ring_id - 1) :
  424. HAL_WBM_SW2_BM_ID(soc->wbm_sw0_bm_id));
  425. }
  426. #endif /*DP_TX_IMPLICIT_RBM_MAPPING*/
  427. #else
  428. static inline uint8_t dp_tx_get_rbm_id_be(struct dp_soc *soc,
  429. uint8_t tcl_index)
  430. {
  431. uint8_t rbm;
  432. rbm = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_index);
  433. dp_verbose_debug("tcl_id %u rbm %u", tcl_index, rbm);
  434. return rbm;
  435. }
  436. #endif
  437. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  438. /**
  439. * dp_tx_set_min_rates_for_critical_frames()- sets min-rates for critical pkts
  440. * @soc: DP soc structure pointer
  441. * @hal_tx_desc: HAL descriptor where fields are set
  442. * @nbuf: skb to be considered for min rates
  443. *
  444. * The function relies on upper layers to set QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL
  445. * and uses it to determine if the frame is critical. For a critical frame,
  446. * flow override bits are set to classify the frame into HW's high priority
  447. * queue. The HW will pick pre-configured min rates for such packets.
  448. *
  449. * Return: None
  450. */
  451. static void
  452. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  453. uint32_t *hal_tx_desc,
  454. qdf_nbuf_t nbuf)
  455. {
  456. /*
  457. * Critical frames should be queued to the high priority queue for the TID on
  458. * on which they are sent out (for the concerned peer).
  459. * FW is using HTT_MSDU_Q_IDX 2 for HOL (high priority) queue.
  460. * htt_msdu_idx = (2 * who_classify_info_sel) + flow_override
  461. * Hence, using who_classify_info_sel = 1, flow_override = 0 to select
  462. * HOL queue.
  463. */
  464. if (QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL(nbuf)) {
  465. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  466. hal_tx_desc_set_flow_override(hal_tx_desc, 0);
  467. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  468. hal_tx_desc_set_tx_notify_frame(hal_tx_desc,
  469. TX_SEMI_HARD_NOTIFY_E);
  470. }
  471. }
  472. #else
  473. static inline void
  474. dp_tx_set_min_rates_for_critical_frames(struct dp_soc *soc,
  475. uint32_t *hal_tx_desc_cached,
  476. qdf_nbuf_t nbuf)
  477. {
  478. }
  479. #endif
  480. #ifdef DP_TX_PACKET_INSPECT_FOR_ILP
  481. /**
  482. * dp_tx_set_particular_tx_queue() - set particular TX TQM flow queue 3 for
  483. * TX packets, currently TCP ACK only
  484. * @soc: DP soc structure pointer
  485. * @hal_tx_desc: HAL descriptor where fields are set
  486. * @nbuf: skb to be considered for particular TX queue
  487. *
  488. * Return: None
  489. */
  490. static inline
  491. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  492. uint32_t *hal_tx_desc,
  493. qdf_nbuf_t nbuf)
  494. {
  495. if (!soc->tx_ilp_enable)
  496. return;
  497. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  498. QDF_NBUF_CB_PACKET_TYPE_TCP_ACK)) {
  499. hal_tx_desc_set_flow_override_enable(hal_tx_desc, 1);
  500. hal_tx_desc_set_flow_override(hal_tx_desc, 1);
  501. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc, 1);
  502. }
  503. }
  504. #else
  505. static inline
  506. void dp_tx_set_particular_tx_queue(struct dp_soc *soc,
  507. uint32_t *hal_tx_desc,
  508. qdf_nbuf_t nbuf)
  509. {
  510. }
  511. #endif
  512. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  513. defined(WLAN_MCAST_MLO)
  514. #ifdef QCA_MULTIPASS_SUPPORT
  515. /**
  516. * dp_tx_mlo_mcast_multipass_lookup() - lookup vlan_id in mpass peer list
  517. * @be_vdev: Handle to DP be_vdev structure
  518. * @ptnr_vdev: DP ptnr_vdev handle
  519. * @arg: pointer to dp_mlo_mpass_ buf
  520. *
  521. * Return: None
  522. */
  523. static void
  524. dp_tx_mlo_mcast_multipass_lookup(struct dp_vdev_be *be_vdev,
  525. struct dp_vdev *ptnr_vdev,
  526. void *arg)
  527. {
  528. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  529. struct dp_txrx_peer *txrx_peer = NULL;
  530. struct vlan_ethhdr *veh = NULL;
  531. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(ptr->nbuf);
  532. uint16_t vlan_id = 0;
  533. bool not_vlan = ((ptnr_vdev->tx_encap_type == htt_cmn_pkt_type_raw) ||
  534. (htons(eh->ether_type) != ETH_P_8021Q));
  535. if (qdf_unlikely(not_vlan))
  536. return;
  537. veh = (struct vlan_ethhdr *)eh;
  538. vlan_id = (ntohs(veh->h_vlan_TCI) & VLAN_VID_MASK);
  539. qdf_spin_lock_bh(&ptnr_vdev->mpass_peer_mutex);
  540. TAILQ_FOREACH(txrx_peer, &ptnr_vdev->mpass_peer_list,
  541. mpass_peer_list_elem) {
  542. if (vlan_id == txrx_peer->vlan_id) {
  543. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  544. ptr->vlan_id = vlan_id;
  545. return;
  546. }
  547. }
  548. qdf_spin_unlock_bh(&ptnr_vdev->mpass_peer_mutex);
  549. }
  550. /**
  551. * dp_tx_mlo_mcast_multipass_send() - send multipass MLO Mcast packets
  552. * @be_vdev: Handle to DP be_vdev structure
  553. * @ptnr_vdev: DP ptnr_vdev handle
  554. * @arg: pointer to dp_mlo_mpass_ buf
  555. *
  556. * Return: None
  557. */
  558. static void
  559. dp_tx_mlo_mcast_multipass_send(struct dp_vdev_be *be_vdev,
  560. struct dp_vdev *ptnr_vdev,
  561. void *arg)
  562. {
  563. struct dp_mlo_mpass_buf *ptr = (struct dp_mlo_mpass_buf *)arg;
  564. struct dp_tx_msdu_info_s msdu_info;
  565. struct dp_vdev_be *be_ptnr_vdev = NULL;
  566. qdf_nbuf_t nbuf_clone;
  567. uint16_t group_key = 0;
  568. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  569. if (be_vdev != be_ptnr_vdev) {
  570. nbuf_clone = qdf_nbuf_clone(ptr->nbuf);
  571. if (qdf_unlikely(!nbuf_clone)) {
  572. dp_tx_debug("nbuf clone failed");
  573. return;
  574. }
  575. } else {
  576. nbuf_clone = ptr->nbuf;
  577. }
  578. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  579. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  580. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  581. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(ptr->nbuf);
  582. if (ptr->vlan_id == MULTIPASS_WITH_VLAN_ID) {
  583. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  584. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(
  585. msdu_info.meta_data[0], 1);
  586. } else {
  587. /* return when vlan map is not initialized */
  588. if (!ptnr_vdev->iv_vlan_map)
  589. goto nbuf_free;
  590. group_key = ptnr_vdev->iv_vlan_map[ptr->vlan_id];
  591. /*
  592. * If group key is not installed, drop the frame.
  593. */
  594. if (!group_key)
  595. goto nbuf_free;
  596. dp_tx_remove_vlan_tag(ptnr_vdev, nbuf_clone);
  597. dp_tx_add_groupkey_metadata(ptnr_vdev, &msdu_info, group_key);
  598. msdu_info.exception_fw = 1;
  599. }
  600. nbuf_clone = dp_tx_send_msdu_single(
  601. ptnr_vdev,
  602. nbuf_clone,
  603. &msdu_info,
  604. DP_MLO_MCAST_REINJECT_PEER_ID,
  605. NULL);
  606. nbuf_free:
  607. if (qdf_unlikely(nbuf_clone)) {
  608. dp_info("pkt send failed");
  609. qdf_nbuf_free(nbuf_clone);
  610. return;
  611. }
  612. }
  613. /**
  614. * dp_tx_mlo_mcast_multipass_handler - If frame needs multipass processing
  615. * @soc: DP soc handle
  616. * @vdev: DP vdev handle
  617. * @nbuf: nbuf to be enqueued
  618. *
  619. * Return: true if handling is done else false
  620. */
  621. static bool
  622. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc,
  623. struct dp_vdev *vdev,
  624. qdf_nbuf_t nbuf)
  625. {
  626. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  627. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  628. qdf_nbuf_t nbuf_copy = NULL;
  629. struct dp_mlo_mpass_buf mpass_buf;
  630. memset(&mpass_buf, 0, sizeof(struct dp_mlo_mpass_buf));
  631. mpass_buf.vlan_id = INVALID_VLAN_ID;
  632. mpass_buf.nbuf = nbuf;
  633. dp_tx_mlo_mcast_multipass_lookup(be_vdev, vdev, &mpass_buf);
  634. if (mpass_buf.vlan_id == INVALID_VLAN_ID) {
  635. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  636. dp_tx_mlo_mcast_multipass_lookup,
  637. &mpass_buf, DP_MOD_ID_TX,
  638. DP_ALL_VDEV_ITER,
  639. DP_VDEV_ITERATE_SKIP_SELF);
  640. /*
  641. * Do not drop the frame when vlan_id doesn't match.
  642. * Send the frame as it is.
  643. */
  644. if (mpass_buf.vlan_id == INVALID_VLAN_ID)
  645. return false;
  646. }
  647. /* AP can have classic clients, special clients &
  648. * classic repeaters.
  649. * 1. Classic clients & special client:
  650. * Remove vlan header, find corresponding group key
  651. * index, fill in metaheader and enqueue multicast
  652. * frame to TCL.
  653. * 2. Classic repeater:
  654. * Pass through to classic repeater with vlan tag
  655. * intact without any group key index. Hardware
  656. * will know which key to use to send frame to
  657. * repeater.
  658. */
  659. nbuf_copy = qdf_nbuf_copy(nbuf);
  660. /*
  661. * Send multicast frame to special peers even
  662. * if pass through to classic repeater fails.
  663. */
  664. if (nbuf_copy) {
  665. struct dp_mlo_mpass_buf mpass_buf_copy = {0};
  666. mpass_buf_copy.vlan_id = MULTIPASS_WITH_VLAN_ID;
  667. mpass_buf_copy.nbuf = nbuf_copy;
  668. /* send frame on partner vdevs */
  669. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  670. dp_tx_mlo_mcast_multipass_send,
  671. &mpass_buf_copy, DP_MOD_ID_TX,
  672. DP_LINK_VDEV_ITER,
  673. DP_VDEV_ITERATE_SKIP_SELF);
  674. /* send frame on mcast primary vdev */
  675. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf_copy);
  676. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  677. be_vdev->mlo_dev_ctxt->seq_num = 0;
  678. else
  679. be_vdev->mlo_dev_ctxt->seq_num++;
  680. }
  681. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  682. dp_tx_mlo_mcast_multipass_send,
  683. &mpass_buf, DP_MOD_ID_TX, DP_LINK_VDEV_ITER,
  684. DP_VDEV_ITERATE_SKIP_SELF);
  685. dp_tx_mlo_mcast_multipass_send(be_vdev, vdev, &mpass_buf);
  686. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  687. be_vdev->mlo_dev_ctxt->seq_num = 0;
  688. else
  689. be_vdev->mlo_dev_ctxt->seq_num++;
  690. return true;
  691. }
  692. #else
  693. static bool
  694. dp_tx_mlo_mcast_multipass_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  695. qdf_nbuf_t nbuf)
  696. {
  697. return false;
  698. }
  699. #endif
  700. void
  701. dp_tx_mlo_mcast_pkt_send(struct dp_vdev_be *be_vdev,
  702. struct dp_vdev *ptnr_vdev,
  703. void *arg)
  704. {
  705. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  706. qdf_nbuf_t nbuf_clone;
  707. struct dp_vdev_be *be_ptnr_vdev = NULL;
  708. struct dp_tx_msdu_info_s msdu_info;
  709. be_ptnr_vdev = dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  710. if (be_vdev != be_ptnr_vdev) {
  711. nbuf_clone = qdf_nbuf_clone(nbuf);
  712. if (qdf_unlikely(!nbuf_clone)) {
  713. dp_tx_debug("nbuf clone failed");
  714. return;
  715. }
  716. } else {
  717. nbuf_clone = nbuf;
  718. }
  719. /* NAWDS clients will accepts on 4 addr format MCAST packets
  720. * This will ensure to send packets in 4 addr format to NAWDS clients.
  721. */
  722. if (qdf_unlikely(ptnr_vdev->nawds_enabled)) {
  723. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  724. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  725. dp_tx_nawds_handler(ptnr_vdev->pdev->soc, ptnr_vdev,
  726. &msdu_info, nbuf_clone, DP_INVALID_PEER);
  727. }
  728. if (qdf_unlikely(dp_tx_proxy_arp(ptnr_vdev, nbuf_clone) !=
  729. QDF_STATUS_SUCCESS)) {
  730. qdf_nbuf_free(nbuf_clone);
  731. return;
  732. }
  733. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  734. dp_tx_get_queue(ptnr_vdev, nbuf_clone, &msdu_info.tx_queue);
  735. msdu_info.gsn = be_vdev->mlo_dev_ctxt->seq_num;
  736. msdu_info.xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf_clone);
  737. DP_STATS_INC(ptnr_vdev,
  738. tx_i[msdu_info.xmit_type].mlo_mcast.send_pkt_count, 1);
  739. nbuf_clone = dp_tx_send_msdu_single(
  740. ptnr_vdev,
  741. nbuf_clone,
  742. &msdu_info,
  743. DP_MLO_MCAST_REINJECT_PEER_ID,
  744. NULL);
  745. if (qdf_unlikely(nbuf_clone)) {
  746. DP_STATS_INC(ptnr_vdev,
  747. tx_i[msdu_info.xmit_type].mlo_mcast.fail_pkt_count,
  748. 1);
  749. dp_info("pkt send failed");
  750. qdf_nbuf_free(nbuf_clone);
  751. return;
  752. }
  753. }
  754. static inline void
  755. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  756. struct dp_vdev *vdev,
  757. struct dp_tx_msdu_info_s *msdu_info)
  758. {
  759. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, msdu_info->vdev_id);
  760. }
  761. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  762. struct dp_vdev *vdev,
  763. qdf_nbuf_t nbuf)
  764. {
  765. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  766. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  767. if (qdf_unlikely(vdev->multipass_en) &&
  768. dp_tx_mlo_mcast_multipass_handler(soc, vdev, nbuf))
  769. return;
  770. /* send frame on partner vdevs */
  771. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  772. dp_tx_mlo_mcast_pkt_send,
  773. nbuf, DP_MOD_ID_REINJECT, DP_LINK_VDEV_ITER,
  774. DP_VDEV_ITERATE_SKIP_SELF);
  775. /* send frame on mcast primary vdev */
  776. dp_tx_mlo_mcast_pkt_send(be_vdev, vdev, nbuf);
  777. if (qdf_unlikely(be_vdev->mlo_dev_ctxt->seq_num > MAX_GSN_NUM))
  778. be_vdev->mlo_dev_ctxt->seq_num = 0;
  779. else
  780. be_vdev->mlo_dev_ctxt->seq_num++;
  781. }
  782. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  783. struct dp_vdev *vdev)
  784. {
  785. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  786. if (be_vdev->mcast_primary)
  787. return true;
  788. return false;
  789. }
  790. #if defined(CONFIG_MLO_SINGLE_DEV)
  791. static void
  792. dp_tx_mlo_mcast_enhance_be(struct dp_vdev_be *be_vdev,
  793. struct dp_vdev *ptnr_vdev,
  794. void *arg)
  795. {
  796. struct dp_vdev *vdev = (struct dp_vdev *)be_vdev;
  797. qdf_nbuf_t nbuf = (qdf_nbuf_t)arg;
  798. if (vdev == ptnr_vdev)
  799. return;
  800. /*
  801. * Hold the reference to avoid free of nbuf in
  802. * dp_tx_mcast_enhance() in case of successful
  803. * conversion
  804. */
  805. qdf_nbuf_ref(nbuf);
  806. if (qdf_unlikely(!dp_tx_mcast_enhance(ptnr_vdev, nbuf)))
  807. return;
  808. qdf_nbuf_free(nbuf);
  809. }
  810. qdf_nbuf_t
  811. dp_tx_mlo_mcast_send_be(struct dp_soc *soc, struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf,
  813. struct cdp_tx_exception_metadata *tx_exc_metadata)
  814. {
  815. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  816. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  817. if (!tx_exc_metadata->is_mlo_mcast)
  818. return nbuf;
  819. if (!be_vdev->mcast_primary) {
  820. qdf_nbuf_free(nbuf);
  821. return NULL;
  822. }
  823. /*
  824. * In the single netdev model avoid reinjection path as mcast
  825. * packet is identified in upper layers while peer search to find
  826. * primary TQM based on dest mac addr
  827. *
  828. * New bonding interface added into the bridge so MCSD will update
  829. * snooping table and wifi driver populates the entries in appropriate
  830. * child net devices.
  831. */
  832. if (vdev->mcast_enhancement_en) {
  833. /*
  834. * As dp_tx_mcast_enhance() can consume the nbuf incase of
  835. * successful conversion hold the reference of nbuf.
  836. *
  837. * Hold the reference to tx on partner links
  838. */
  839. qdf_nbuf_ref(nbuf);
  840. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf))) {
  841. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  842. dp_tx_mlo_mcast_enhance_be,
  843. nbuf, DP_MOD_ID_TX,
  844. DP_ALL_VDEV_ITER,
  845. DP_VDEV_ITERATE_SKIP_SELF);
  846. qdf_nbuf_free(nbuf);
  847. return NULL;
  848. }
  849. /* release reference taken above */
  850. qdf_nbuf_free(nbuf);
  851. }
  852. dp_tx_mlo_mcast_handler_be(soc, vdev, nbuf);
  853. return NULL;
  854. }
  855. #endif
  856. #else
  857. static inline void
  858. dp_tx_vdev_id_set_hal_tx_desc(uint32_t *hal_tx_desc_cached,
  859. struct dp_vdev *vdev,
  860. struct dp_tx_msdu_info_s *msdu_info)
  861. {
  862. hal_tx_desc_set_vdev_id(hal_tx_desc_cached, vdev->vdev_id);
  863. }
  864. #endif
  865. #if defined(WLAN_FEATURE_11BE_MLO) && !defined(WLAN_MLO_MULTI_CHIP) && \
  866. !defined(WLAN_MCAST_MLO)
  867. void dp_tx_mlo_mcast_handler_be(struct dp_soc *soc,
  868. struct dp_vdev *vdev,
  869. qdf_nbuf_t nbuf)
  870. {
  871. }
  872. bool dp_tx_mlo_is_mcast_primary_be(struct dp_soc *soc,
  873. struct dp_vdev *vdev)
  874. {
  875. return false;
  876. }
  877. #endif
  878. #ifdef CONFIG_SAWF
  879. /**
  880. * dp_sawf_config_be - Configure sawf specific fields in tcl
  881. *
  882. * @soc: DP soc handle
  883. * @hal_tx_desc_cached: tx descriptor
  884. * @fw_metadata: firmware metadata
  885. * @nbuf: skb buffer
  886. * @msdu_info: msdu info
  887. *
  888. * Return: tid value in mark metadata
  889. */
  890. uint8_t dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  891. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  892. struct dp_tx_msdu_info_s *msdu_info)
  893. {
  894. uint8_t q_id = 0;
  895. uint8_t tid = HTT_TX_EXT_TID_INVALID;
  896. q_id = dp_sawf_queue_id_get(nbuf);
  897. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  898. return HTT_TX_EXT_TID_INVALID;
  899. tid = (q_id & (CDP_DATA_TID_MAX - 1));
  900. if (msdu_info)
  901. msdu_info->tid = tid;
  902. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  903. (q_id & (CDP_DATA_TID_MAX - 1)));
  904. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  905. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  906. return tid;
  907. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  908. return tid;
  909. if (fw_metadata)
  910. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  911. hal_tx_desc_set_flow_override_enable(hal_tx_desc_cached,
  912. DP_TX_FLOW_OVERRIDE_ENABLE);
  913. hal_tx_desc_set_flow_override(hal_tx_desc_cached,
  914. DP_TX_FLOW_OVERRIDE_GET(q_id));
  915. hal_tx_desc_set_who_classify_info_sel(hal_tx_desc_cached,
  916. DP_TX_WHO_CLFY_INF_SEL_GET(q_id));
  917. return tid;
  918. }
  919. #else
  920. static inline
  921. uint8_t dp_sawf_config_be(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  922. uint16_t *fw_metadata, qdf_nbuf_t nbuf,
  923. struct dp_tx_msdu_info_s *msdu_info)
  924. {
  925. return HTT_TX_EXT_TID_INVALID;
  926. }
  927. static inline
  928. QDF_STATUS dp_sawf_tx_enqueue_peer_stats(struct dp_soc *soc,
  929. struct dp_tx_desc_s *tx_desc)
  930. {
  931. return QDF_STATUS_SUCCESS;
  932. }
  933. static inline
  934. QDF_STATUS dp_sawf_tx_enqueue_fail_peer_stats(struct dp_soc *soc,
  935. struct dp_tx_desc_s *tx_desc)
  936. {
  937. return QDF_STATUS_SUCCESS;
  938. }
  939. #endif
  940. #ifdef WLAN_SUPPORT_PPEDS
  941. /**
  942. * dp_ppeds_stats() - Accounting fw2wbm_tx_drop drops in Tx path
  943. * @soc: Handle to DP Soc structure
  944. * @peer_id: Peer ID in the descriptor
  945. *
  946. * Return: NONE
  947. */
  948. static inline
  949. void dp_ppeds_stats(struct dp_soc *soc, uint16_t peer_id)
  950. {
  951. struct dp_vdev *vdev = NULL;
  952. struct dp_txrx_peer *txrx_peer = NULL;
  953. dp_txrx_ref_handle txrx_ref_handle = NULL;
  954. DP_STATS_INC(soc, tx.fw2wbm_tx_drop, 1);
  955. txrx_peer = dp_txrx_peer_get_ref_by_id(soc,
  956. peer_id,
  957. &txrx_ref_handle,
  958. DP_MOD_ID_TX_COMP);
  959. if (txrx_peer) {
  960. vdev = txrx_peer->vdev;
  961. DP_STATS_INC(vdev, tx_i[DP_XMIT_LINK].dropped.fw2wbm_tx_drop, 1);
  962. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  963. }
  964. }
  965. int dp_ppeds_tx_comp_handler(struct dp_soc_be *be_soc, uint32_t quota)
  966. {
  967. uint32_t num_avail_for_reap = 0;
  968. void *tx_comp_hal_desc;
  969. uint8_t buf_src, status = 0;
  970. uint32_t count = 0;
  971. struct dp_tx_desc_s *tx_desc = NULL;
  972. struct dp_tx_desc_s *head_desc = NULL;
  973. struct dp_tx_desc_s *tail_desc = NULL;
  974. struct dp_soc *soc = &be_soc->soc;
  975. void *last_prefetch_hw_desc = NULL;
  976. struct dp_tx_desc_s *last_prefetch_sw_desc = NULL;
  977. qdf_nbuf_t nbuf;
  978. hal_soc_handle_t hal_soc = soc->hal_soc;
  979. hal_ring_handle_t hal_ring_hdl =
  980. be_soc->ppeds_wbm_release_ring.hal_srng;
  981. struct dp_txrx_peer *txrx_peer = NULL;
  982. uint16_t peer_id = CDP_INVALID_PEER;
  983. dp_txrx_ref_handle txrx_ref_handle = NULL;
  984. struct dp_vdev *vdev = NULL;
  985. struct dp_pdev *pdev = NULL;
  986. struct dp_srng *srng;
  987. if (qdf_unlikely(dp_srng_access_start(NULL, soc, hal_ring_hdl))) {
  988. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  989. return 0;
  990. }
  991. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  992. if (num_avail_for_reap >= quota)
  993. num_avail_for_reap = quota;
  994. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  995. last_prefetch_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  996. num_avail_for_reap);
  997. srng = &be_soc->ppeds_wbm_release_ring;
  998. if (srng) {
  999. hal_update_ring_util(soc->hal_soc, srng->hal_srng,
  1000. WBM2SW_RELEASE,
  1001. &be_soc->ppeds_wbm_release_ring.stats);
  1002. }
  1003. while (qdf_likely(num_avail_for_reap--)) {
  1004. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  1005. if (qdf_unlikely(!tx_comp_hal_desc))
  1006. break;
  1007. buf_src = hal_tx_comp_get_buffer_source(hal_soc,
  1008. tx_comp_hal_desc);
  1009. if (qdf_unlikely(buf_src != HAL_TX_COMP_RELEASE_SOURCE_TQM &&
  1010. buf_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1011. dp_err("Tx comp release_src != TQM | FW but from %d",
  1012. buf_src);
  1013. dp_assert_always_internal_ds_stat(0, be_soc,
  1014. tx.tx_comp_buf_src);
  1015. continue;
  1016. }
  1017. dp_tx_comp_get_params_from_hal_desc_be(soc, tx_comp_hal_desc,
  1018. &tx_desc);
  1019. if (!tx_desc) {
  1020. dp_err("unable to retrieve tx_desc!");
  1021. dp_assert_always_internal_ds_stat(0, be_soc,
  1022. tx.tx_comp_desc_null);
  1023. continue;
  1024. }
  1025. if (qdf_unlikely(!(tx_desc->flags &
  1026. DP_TX_DESC_FLAG_ALLOCATED) ||
  1027. !(tx_desc->flags & DP_TX_DESC_FLAG_PPEDS))) {
  1028. dp_assert_always_internal_ds_stat(0, be_soc,
  1029. tx.tx_comp_invalid_flag);
  1030. continue;
  1031. }
  1032. tx_desc->buffer_src = buf_src;
  1033. if (qdf_unlikely(buf_src == HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1034. status = hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1035. if (status != HTT_TX_FW2WBM_TX_STATUS_OK)
  1036. dp_ppeds_stats(soc, tx_desc->peer_id);
  1037. nbuf = dp_ppeds_tx_desc_free(soc, tx_desc);
  1038. qdf_nbuf_free(nbuf);
  1039. } else {
  1040. tx_desc->tx_status =
  1041. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  1042. /*
  1043. * Add desc sync to account for extended statistics
  1044. * during Tx completion.
  1045. */
  1046. if (peer_id != tx_desc->peer_id) {
  1047. if (txrx_peer) {
  1048. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1049. DP_MOD_ID_TX_COMP);
  1050. txrx_peer = NULL;
  1051. vdev = NULL;
  1052. pdev = NULL;
  1053. }
  1054. peer_id = tx_desc->peer_id;
  1055. txrx_peer =
  1056. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  1057. &txrx_ref_handle,
  1058. DP_MOD_ID_TX_COMP);
  1059. if (txrx_peer) {
  1060. vdev = txrx_peer->vdev;
  1061. if (!vdev)
  1062. goto next_desc;
  1063. pdev = vdev->pdev;
  1064. if (!pdev)
  1065. goto next_desc;
  1066. dp_tx_desc_update_fast_comp_flag(soc,
  1067. tx_desc,
  1068. !pdev->enhanced_stats_en);
  1069. if (pdev->enhanced_stats_en) {
  1070. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1071. &tx_desc->comp, 1);
  1072. }
  1073. }
  1074. } else if (txrx_peer && vdev && pdev) {
  1075. dp_tx_desc_update_fast_comp_flag(soc,
  1076. tx_desc,
  1077. !pdev->enhanced_stats_en);
  1078. if (pdev->enhanced_stats_en) {
  1079. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1080. &tx_desc->comp, 1);
  1081. }
  1082. }
  1083. next_desc:
  1084. if (!head_desc) {
  1085. head_desc = tx_desc;
  1086. tail_desc = tx_desc;
  1087. }
  1088. tail_desc->next = tx_desc;
  1089. tx_desc->next = NULL;
  1090. tail_desc = tx_desc;
  1091. count++;
  1092. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  1093. num_avail_for_reap,
  1094. hal_ring_hdl,
  1095. &last_prefetch_hw_desc,
  1096. &last_prefetch_sw_desc,
  1097. NULL);
  1098. }
  1099. }
  1100. dp_srng_access_end(NULL, soc, hal_ring_hdl);
  1101. if (txrx_peer)
  1102. dp_txrx_peer_unref_delete(txrx_ref_handle,
  1103. DP_MOD_ID_TX_COMP);
  1104. if (head_desc)
  1105. dp_tx_comp_process_desc_list(soc, head_desc,
  1106. CDP_MAX_TX_COMP_PPE_RING);
  1107. return count;
  1108. }
  1109. #endif
  1110. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  1111. static inline void
  1112. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1113. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1114. uint16_t *ast_idx, uint16_t *ast_hash)
  1115. {
  1116. struct dp_peer *peer = NULL;
  1117. if (tx_exc_metadata->is_wds_extended) {
  1118. peer = dp_peer_get_ref_by_id(soc, tx_exc_metadata->peer_id,
  1119. DP_MOD_ID_TX);
  1120. if (peer) {
  1121. *ast_idx = peer->ast_idx;
  1122. *ast_hash = peer->ast_hash;
  1123. hal_tx_desc_set_index_lookup_override
  1124. (soc->hal_soc,
  1125. hal_tx_desc_cached,
  1126. 0x1);
  1127. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  1128. }
  1129. } else {
  1130. return;
  1131. }
  1132. }
  1133. #else
  1134. static inline void
  1135. dp_get_peer_from_tx_exc_meta(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  1136. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1137. uint16_t *ast_idx, uint16_t *ast_hash)
  1138. {
  1139. }
  1140. #endif
  1141. QDF_STATUS
  1142. dp_tx_hw_enqueue_be(struct dp_soc *soc, struct dp_vdev *vdev,
  1143. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1144. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1145. struct dp_tx_msdu_info_s *msdu_info)
  1146. {
  1147. void *hal_tx_desc;
  1148. uint32_t *hal_tx_desc_cached;
  1149. int coalesce = 0;
  1150. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1151. uint8_t ring_id = tx_q->ring_id;
  1152. uint8_t tid;
  1153. struct dp_vdev_be *be_vdev;
  1154. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1155. uint8_t bm_id = dp_tx_get_rbm_id_be(soc, ring_id);
  1156. hal_ring_handle_t hal_ring_hdl = NULL;
  1157. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1158. uint8_t num_desc_bytes = HAL_TX_DESC_LEN_BYTES;
  1159. uint16_t ast_idx = vdev->bss_ast_idx;
  1160. uint16_t ast_hash = vdev->bss_ast_hash;
  1161. be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1162. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1163. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1164. return QDF_STATUS_E_RESOURCES;
  1165. }
  1166. if (qdf_unlikely(tx_exc_metadata)) {
  1167. qdf_assert_always((tx_exc_metadata->tx_encap_type ==
  1168. CDP_INVALID_TX_ENCAP_TYPE) ||
  1169. (tx_exc_metadata->tx_encap_type ==
  1170. vdev->tx_encap_type));
  1171. if (tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)
  1172. qdf_assert_always((tx_exc_metadata->sec_type ==
  1173. CDP_INVALID_SEC_TYPE) ||
  1174. tx_exc_metadata->sec_type ==
  1175. vdev->sec_type);
  1176. dp_get_peer_from_tx_exc_meta(soc, (void *)cached_desc,
  1177. tx_exc_metadata,
  1178. &ast_idx, &ast_hash);
  1179. }
  1180. hal_tx_desc_cached = (void *)cached_desc;
  1181. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  1182. dp_sawf_config_be(soc, hal_tx_desc_cached,
  1183. &fw_metadata, tx_desc->nbuf, msdu_info);
  1184. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  1185. }
  1186. hal_tx_desc_set_buf_addr_be(soc->hal_soc, hal_tx_desc_cached,
  1187. tx_desc->dma_addr, bm_id, tx_desc->id,
  1188. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1189. hal_tx_desc_set_lmac_id_be(soc->hal_soc, hal_tx_desc_cached,
  1190. vdev->lmac_id);
  1191. hal_tx_desc_set_search_index_be(soc->hal_soc, hal_tx_desc_cached,
  1192. ast_idx);
  1193. /*
  1194. * Bank_ID is used as DSCP_TABLE number in beryllium
  1195. * So there is no explicit field used for DSCP_TID_TABLE_NUM.
  1196. */
  1197. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1198. (ast_hash & 0xF));
  1199. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1200. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1201. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1202. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1203. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1204. /* verify checksum offload configuration*/
  1205. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  1206. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  1207. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  1208. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1209. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1210. }
  1211. hal_tx_desc_set_bank_id(hal_tx_desc_cached, vdev->bank_id);
  1212. dp_tx_vdev_id_set_hal_tx_desc(hal_tx_desc_cached, vdev, msdu_info);
  1213. tid = msdu_info->tid;
  1214. if (tid != HTT_TX_EXT_TID_INVALID)
  1215. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1216. dp_tx_set_min_rates_for_critical_frames(soc, hal_tx_desc_cached,
  1217. tx_desc->nbuf);
  1218. dp_tx_set_particular_tx_queue(soc, hal_tx_desc_cached,
  1219. tx_desc->nbuf);
  1220. dp_tx_desc_set_ktimestamp(vdev, tx_desc);
  1221. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1222. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1223. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1224. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1225. DP_STATS_INC(vdev,
  1226. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1227. 1);
  1228. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1229. return status;
  1230. }
  1231. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1232. if (qdf_unlikely(!hal_tx_desc)) {
  1233. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1234. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1235. DP_STATS_INC(vdev,
  1236. tx_i[msdu_info->xmit_type].dropped.enqueue_fail,
  1237. 1);
  1238. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  1239. goto ring_access_fail;
  1240. }
  1241. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1242. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1243. /* Sync cached descriptor with HW */
  1244. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc, num_desc_bytes);
  1245. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  1246. msdu_info, ring_id);
  1247. DP_STATS_INC_PKT(vdev, tx_i[msdu_info->xmit_type].processed, 1,
  1248. dp_tx_get_pkt_len(tx_desc));
  1249. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  1250. dp_tx_update_stats(soc, tx_desc, ring_id);
  1251. status = QDF_STATUS_SUCCESS;
  1252. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  1253. hal_ring_hdl, soc, ring_id);
  1254. ring_access_fail:
  1255. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1256. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  1257. qdf_get_log_timestamp(), tx_desc->nbuf);
  1258. return status;
  1259. }
  1260. #ifdef IPA_OFFLOAD
  1261. static void
  1262. dp_tx_get_ipa_bank_config(struct dp_soc_be *be_soc,
  1263. union hal_tx_bank_config *bank_config)
  1264. {
  1265. bank_config->epd = 0;
  1266. bank_config->encap_type = wlan_cfg_pkt_type(be_soc->soc.wlan_cfg_ctx);
  1267. bank_config->encrypt_type = 0;
  1268. bank_config->src_buffer_swap = 0;
  1269. bank_config->link_meta_swap = 0;
  1270. bank_config->index_lookup_enable = 0;
  1271. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1272. bank_config->addrx_en = 1;
  1273. bank_config->addry_en = 1;
  1274. bank_config->mesh_enable = 0;
  1275. bank_config->dscp_tid_map_id = 0;
  1276. bank_config->vdev_id_check_en = 0;
  1277. bank_config->pmac_id = 0;
  1278. }
  1279. static void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1280. {
  1281. union hal_tx_bank_config ipa_config = {0};
  1282. int bid;
  1283. if (!wlan_cfg_is_ipa_enabled(be_soc->soc.wlan_cfg_ctx)) {
  1284. be_soc->ipa_bank_id = DP_BE_INVALID_BANK_ID;
  1285. return;
  1286. }
  1287. dp_tx_get_ipa_bank_config(be_soc, &ipa_config);
  1288. /* Let IPA use last HOST owned bank */
  1289. bid = be_soc->num_bank_profiles - 1;
  1290. be_soc->bank_profiles[bid].is_configured = true;
  1291. be_soc->bank_profiles[bid].bank_config.val = ipa_config.val;
  1292. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1293. &be_soc->bank_profiles[bid].bank_config,
  1294. bid);
  1295. qdf_atomic_inc(&be_soc->bank_profiles[bid].ref_count);
  1296. dp_info("IPA bank at slot %d config:0x%x", bid,
  1297. be_soc->bank_profiles[bid].bank_config.val);
  1298. be_soc->ipa_bank_id = bid;
  1299. }
  1300. #else /* !IPA_OFFLOAD */
  1301. static inline void dp_tx_init_ipa_bank_profile(struct dp_soc_be *be_soc)
  1302. {
  1303. }
  1304. #endif /* IPA_OFFLOAD */
  1305. QDF_STATUS dp_tx_init_bank_profiles(struct dp_soc_be *be_soc)
  1306. {
  1307. int i, num_tcl_banks;
  1308. num_tcl_banks = hal_tx_get_num_tcl_banks(be_soc->soc.hal_soc);
  1309. dp_assert_always_internal(num_tcl_banks);
  1310. be_soc->num_bank_profiles = num_tcl_banks;
  1311. be_soc->bank_profiles = qdf_mem_malloc(num_tcl_banks *
  1312. sizeof(*be_soc->bank_profiles));
  1313. if (!be_soc->bank_profiles) {
  1314. dp_err("unable to allocate memory for DP TX Profiles!");
  1315. return QDF_STATUS_E_NOMEM;
  1316. }
  1317. DP_TX_BANK_LOCK_CREATE(&be_soc->tx_bank_lock);
  1318. for (i = 0; i < num_tcl_banks; i++) {
  1319. be_soc->bank_profiles[i].is_configured = false;
  1320. qdf_atomic_init(&be_soc->bank_profiles[i].ref_count);
  1321. }
  1322. dp_info("initialized %u bank profiles", be_soc->num_bank_profiles);
  1323. dp_tx_init_ipa_bank_profile(be_soc);
  1324. return QDF_STATUS_SUCCESS;
  1325. }
  1326. void dp_tx_deinit_bank_profiles(struct dp_soc_be *be_soc)
  1327. {
  1328. qdf_mem_free(be_soc->bank_profiles);
  1329. DP_TX_BANK_LOCK_DESTROY(&be_soc->tx_bank_lock);
  1330. }
  1331. static
  1332. void dp_tx_get_vdev_bank_config(struct dp_vdev_be *be_vdev,
  1333. union hal_tx_bank_config *bank_config)
  1334. {
  1335. struct dp_vdev *vdev = &be_vdev->vdev;
  1336. bank_config->epd = 0;
  1337. bank_config->encap_type = vdev->tx_encap_type;
  1338. /* Only valid for raw frames. Needs work for RAW mode */
  1339. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) {
  1340. bank_config->encrypt_type = sec_type_map[vdev->sec_type];
  1341. } else {
  1342. bank_config->encrypt_type = 0;
  1343. }
  1344. bank_config->src_buffer_swap = 0;
  1345. bank_config->link_meta_swap = 0;
  1346. if ((vdev->search_type == HAL_TX_ADDR_INDEX_SEARCH) &&
  1347. vdev->opmode == wlan_op_mode_sta) {
  1348. bank_config->index_lookup_enable = 1;
  1349. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_MEC_NOTIFY;
  1350. bank_config->addrx_en = 0;
  1351. bank_config->addry_en = 0;
  1352. } else {
  1353. bank_config->index_lookup_enable = 0;
  1354. bank_config->mcast_pkt_ctrl = HAL_TX_MCAST_CTRL_FW_EXCEPTION;
  1355. bank_config->addrx_en =
  1356. (vdev->hal_desc_addr_search_flags &
  1357. HAL_TX_DESC_ADDRX_EN) ? 1 : 0;
  1358. bank_config->addry_en =
  1359. (vdev->hal_desc_addr_search_flags &
  1360. HAL_TX_DESC_ADDRY_EN) ? 1 : 0;
  1361. }
  1362. bank_config->mesh_enable = vdev->mesh_vdev ? 1 : 0;
  1363. bank_config->dscp_tid_map_id = vdev->dscp_tid_map_id;
  1364. /* Disabling vdev id check for now. Needs revist. */
  1365. bank_config->vdev_id_check_en = be_vdev->vdev_id_check_en;
  1366. bank_config->pmac_id = vdev->lmac_id;
  1367. }
  1368. int dp_tx_get_bank_profile(struct dp_soc_be *be_soc,
  1369. struct dp_vdev_be *be_vdev)
  1370. {
  1371. char *temp_str = "";
  1372. bool found_match = false;
  1373. int bank_id = DP_BE_INVALID_BANK_ID;
  1374. int i;
  1375. int unconfigured_slot = DP_BE_INVALID_BANK_ID;
  1376. int zero_ref_count_slot = DP_BE_INVALID_BANK_ID;
  1377. union hal_tx_bank_config vdev_config = {0};
  1378. /* convert vdev params into hal_tx_bank_config */
  1379. dp_tx_get_vdev_bank_config(be_vdev, &vdev_config);
  1380. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1381. /* go over all banks and find a matching/unconfigured/unused bank */
  1382. for (i = 0; i < be_soc->num_bank_profiles; i++) {
  1383. if (be_soc->bank_profiles[i].is_configured &&
  1384. (be_soc->bank_profiles[i].bank_config.val ^
  1385. vdev_config.val) == 0) {
  1386. found_match = true;
  1387. break;
  1388. }
  1389. if (unconfigured_slot == DP_BE_INVALID_BANK_ID &&
  1390. !be_soc->bank_profiles[i].is_configured)
  1391. unconfigured_slot = i;
  1392. else if (zero_ref_count_slot == DP_BE_INVALID_BANK_ID &&
  1393. !qdf_atomic_read(&be_soc->bank_profiles[i].ref_count))
  1394. zero_ref_count_slot = i;
  1395. }
  1396. if (found_match) {
  1397. temp_str = "matching";
  1398. bank_id = i;
  1399. goto inc_ref_and_return;
  1400. }
  1401. if (unconfigured_slot != DP_BE_INVALID_BANK_ID) {
  1402. temp_str = "unconfigured";
  1403. bank_id = unconfigured_slot;
  1404. goto configure_and_return;
  1405. }
  1406. if (zero_ref_count_slot != DP_BE_INVALID_BANK_ID) {
  1407. temp_str = "zero_ref_count";
  1408. bank_id = zero_ref_count_slot;
  1409. }
  1410. if (bank_id == DP_BE_INVALID_BANK_ID) {
  1411. dp_alert("unable to find TX bank!");
  1412. QDF_BUG(0);
  1413. return bank_id;
  1414. }
  1415. configure_and_return:
  1416. be_soc->bank_profiles[bank_id].is_configured = true;
  1417. be_soc->bank_profiles[bank_id].bank_config.val = vdev_config.val;
  1418. hal_tx_populate_bank_register(be_soc->soc.hal_soc,
  1419. &be_soc->bank_profiles[bank_id].bank_config,
  1420. bank_id);
  1421. inc_ref_and_return:
  1422. qdf_atomic_inc(&be_soc->bank_profiles[bank_id].ref_count);
  1423. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1424. dp_info("found %s slot at index %d, input:0x%x match:0x%x ref_count %u",
  1425. temp_str, bank_id, vdev_config.val,
  1426. be_soc->bank_profiles[bank_id].bank_config.val,
  1427. qdf_atomic_read(&be_soc->bank_profiles[bank_id].ref_count));
  1428. dp_info("epd:%x encap:%x encryp:%x src_buf_swap:%x link_meta_swap:%x addrx_en:%x addry_en:%x mesh_en:%x vdev_id_check:%x pmac_id:%x mcast_pkt_ctrl:%x",
  1429. be_soc->bank_profiles[bank_id].bank_config.epd,
  1430. be_soc->bank_profiles[bank_id].bank_config.encap_type,
  1431. be_soc->bank_profiles[bank_id].bank_config.encrypt_type,
  1432. be_soc->bank_profiles[bank_id].bank_config.src_buffer_swap,
  1433. be_soc->bank_profiles[bank_id].bank_config.link_meta_swap,
  1434. be_soc->bank_profiles[bank_id].bank_config.addrx_en,
  1435. be_soc->bank_profiles[bank_id].bank_config.addry_en,
  1436. be_soc->bank_profiles[bank_id].bank_config.mesh_enable,
  1437. be_soc->bank_profiles[bank_id].bank_config.vdev_id_check_en,
  1438. be_soc->bank_profiles[bank_id].bank_config.pmac_id,
  1439. be_soc->bank_profiles[bank_id].bank_config.mcast_pkt_ctrl);
  1440. return bank_id;
  1441. }
  1442. void dp_tx_put_bank_profile(struct dp_soc_be *be_soc,
  1443. struct dp_vdev_be *be_vdev)
  1444. {
  1445. DP_TX_BANK_LOCK_ACQUIRE(&be_soc->tx_bank_lock);
  1446. qdf_atomic_dec(&be_soc->bank_profiles[be_vdev->bank_id].ref_count);
  1447. DP_TX_BANK_LOCK_RELEASE(&be_soc->tx_bank_lock);
  1448. }
  1449. void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
  1450. struct dp_vdev_be *be_vdev)
  1451. {
  1452. dp_tx_put_bank_profile(be_soc, be_vdev);
  1453. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  1454. be_vdev->vdev.bank_id = be_vdev->bank_id;
  1455. }
  1456. QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
  1457. uint32_t num_elem,
  1458. uint8_t pool_id,
  1459. bool spcl_tx_desc)
  1460. {
  1461. struct dp_tx_desc_pool_s *tx_desc_pool;
  1462. struct dp_hw_cookie_conversion_t *cc_ctx;
  1463. struct dp_spt_page_desc *page_desc;
  1464. struct dp_tx_desc_s *tx_desc;
  1465. uint32_t ppt_idx = 0;
  1466. uint32_t avail_entry_index = 0;
  1467. if (!num_elem) {
  1468. dp_err("desc_num 0 !!");
  1469. return QDF_STATUS_E_FAILURE;
  1470. }
  1471. if (spcl_tx_desc) {
  1472. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  1473. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1474. } else {
  1475. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);;
  1476. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1477. }
  1478. tx_desc = tx_desc_pool->freelist;
  1479. page_desc = &cc_ctx->page_desc_base[0];
  1480. while (tx_desc) {
  1481. if (avail_entry_index == 0) {
  1482. if (ppt_idx >= cc_ctx->total_page_num) {
  1483. dp_alert("insufficient secondary page tables");
  1484. qdf_assert_always(0);
  1485. }
  1486. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  1487. }
  1488. /* put each TX Desc VA to SPT pages and
  1489. * get corresponding ID
  1490. */
  1491. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  1492. avail_entry_index,
  1493. tx_desc);
  1494. tx_desc->id =
  1495. dp_cc_desc_id_generate(page_desc->ppt_index,
  1496. avail_entry_index);
  1497. tx_desc->pool_id = pool_id;
  1498. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  1499. tx_desc = tx_desc->next;
  1500. avail_entry_index = (avail_entry_index + 1) &
  1501. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  1502. }
  1503. return QDF_STATUS_SUCCESS;
  1504. }
  1505. void dp_tx_desc_pool_deinit_be(struct dp_soc *soc,
  1506. struct dp_tx_desc_pool_s *tx_desc_pool,
  1507. uint8_t pool_id, bool spcl_tx_desc)
  1508. {
  1509. struct dp_spt_page_desc *page_desc;
  1510. int i = 0;
  1511. struct dp_hw_cookie_conversion_t *cc_ctx;
  1512. if (spcl_tx_desc)
  1513. cc_ctx = dp_get_spcl_tx_cookie_t(soc, pool_id);
  1514. else
  1515. cc_ctx = dp_get_tx_cookie_t(soc, pool_id);
  1516. for (i = 0; i < cc_ctx->total_page_num; i++) {
  1517. page_desc = &cc_ctx->page_desc_base[i];
  1518. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  1519. }
  1520. }
  1521. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1522. uint32_t dp_tx_comp_nf_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  1523. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  1524. uint32_t quota)
  1525. {
  1526. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  1527. uint32_t work_done = 0;
  1528. if (dp_srng_get_near_full_level(soc, tx_comp_ring) <
  1529. DP_SRNG_THRESH_NEAR_FULL)
  1530. return 0;
  1531. qdf_atomic_set(&tx_comp_ring->near_full, 1);
  1532. work_done++;
  1533. return work_done;
  1534. }
  1535. #endif
  1536. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1537. defined(WLAN_CONFIG_TX_DELAY)
  1538. #define PPDUID_GET_HW_LINK_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  1539. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  1540. #define HW_TX_DELAY_MAX 0x1000000
  1541. #define TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US 10
  1542. #define HW_TX_DELAY_MASK 0x1FFFFFFF
  1543. #define TX_COMPL_BUFFER_TSTAMP_US(TSTAMP) \
  1544. (((TSTAMP) << TX_COMPL_SHIFT_BUFFER_TIMESTAMP_US) & \
  1545. HW_TX_DELAY_MASK)
  1546. static inline
  1547. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1548. struct dp_vdev *vdev,
  1549. struct hal_tx_completion_status *ts,
  1550. uint32_t *delay_us)
  1551. {
  1552. uint32_t ppdu_id;
  1553. uint8_t link_id_offset, link_id_bits;
  1554. uint8_t hw_link_id;
  1555. uint32_t msdu_tqm_enqueue_tstamp_us, final_msdu_tqm_enqueue_tstamp_us;
  1556. uint32_t msdu_compl_tsf_tstamp_us, final_msdu_compl_tsf_tstamp_us;
  1557. uint32_t delay;
  1558. int32_t delta_tsf2, delta_tqm;
  1559. if (!ts->valid)
  1560. return QDF_STATUS_E_INVAL;
  1561. link_id_offset = soc->link_id_offset;
  1562. link_id_bits = soc->link_id_bits;
  1563. ppdu_id = ts->ppdu_id;
  1564. hw_link_id = PPDUID_GET_HW_LINK_ID(ppdu_id, link_id_offset,
  1565. link_id_bits);
  1566. msdu_tqm_enqueue_tstamp_us =
  1567. TX_COMPL_BUFFER_TSTAMP_US(ts->buffer_timestamp);
  1568. msdu_compl_tsf_tstamp_us = ts->tsf;
  1569. delta_tsf2 = dp_mlo_get_delta_tsf2_wrt_mlo_offset(soc, hw_link_id);
  1570. delta_tqm = dp_mlo_get_delta_tqm_wrt_mlo_offset(soc);
  1571. final_msdu_tqm_enqueue_tstamp_us = (msdu_tqm_enqueue_tstamp_us +
  1572. delta_tqm) & HW_TX_DELAY_MASK;
  1573. final_msdu_compl_tsf_tstamp_us = (msdu_compl_tsf_tstamp_us +
  1574. delta_tsf2) & HW_TX_DELAY_MASK;
  1575. delay = (final_msdu_compl_tsf_tstamp_us -
  1576. final_msdu_tqm_enqueue_tstamp_us) & HW_TX_DELAY_MASK;
  1577. if (delay > HW_TX_DELAY_MAX)
  1578. return QDF_STATUS_E_FAILURE;
  1579. if (delay_us)
  1580. *delay_us = delay;
  1581. return QDF_STATUS_SUCCESS;
  1582. }
  1583. #else
  1584. static inline
  1585. QDF_STATUS dp_mlo_compute_hw_delay_us(struct dp_soc *soc,
  1586. struct dp_vdev *vdev,
  1587. struct hal_tx_completion_status *ts,
  1588. uint32_t *delay_us)
  1589. {
  1590. return QDF_STATUS_SUCCESS;
  1591. }
  1592. #endif
  1593. QDF_STATUS dp_tx_compute_tx_delay_be(struct dp_soc *soc,
  1594. struct dp_vdev *vdev,
  1595. struct hal_tx_completion_status *ts,
  1596. uint32_t *delay_us)
  1597. {
  1598. return dp_mlo_compute_hw_delay_us(soc, vdev, ts, delay_us);
  1599. }
  1600. static inline
  1601. qdf_dma_addr_t dp_tx_nbuf_map_be(struct dp_vdev *vdev,
  1602. struct dp_tx_desc_s *tx_desc,
  1603. qdf_nbuf_t nbuf)
  1604. {
  1605. qdf_nbuf_dma_clean_range_no_dsb((void *)nbuf->data,
  1606. (void *)(nbuf->data + 256));
  1607. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1608. }
  1609. static inline
  1610. void dp_tx_nbuf_unmap_be(struct dp_soc *soc,
  1611. struct dp_tx_desc_s *desc)
  1612. {
  1613. }
  1614. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  1615. qdf_nbuf_t dp_tx_fast_send_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1616. qdf_nbuf_t nbuf)
  1617. {
  1618. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1619. struct dp_vdev *vdev = NULL;
  1620. struct dp_pdev *pdev = NULL;
  1621. struct dp_tx_desc_s *tx_desc;
  1622. uint16_t desc_pool_id;
  1623. uint16_t pkt_len;
  1624. qdf_dma_addr_t paddr;
  1625. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1626. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1627. hal_ring_handle_t hal_ring_hdl = NULL;
  1628. uint32_t *hal_tx_desc_cached;
  1629. void *hal_tx_desc;
  1630. uint8_t tid = HTT_TX_EXT_TID_INVALID;
  1631. uint8_t xmit_type = qdf_nbuf_get_vdev_xmit_type(nbuf);
  1632. uint8_t sawf_tid = HTT_TX_EXT_TID_INVALID;
  1633. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  1634. return nbuf;
  1635. vdev = soc->vdev_id_map[vdev_id];
  1636. if (qdf_unlikely(!vdev))
  1637. return nbuf;
  1638. desc_pool_id = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  1639. pkt_len = qdf_nbuf_headlen(nbuf);
  1640. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].rcvd, 1, pkt_len);
  1641. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_in_fast_xmit_flow, 1);
  1642. DP_STATS_INC(vdev, tx_i[xmit_type].rcvd_per_core[desc_pool_id], 1);
  1643. pdev = vdev->pdev;
  1644. if (dp_tx_limit_check(vdev, nbuf))
  1645. return nbuf;
  1646. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1647. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1648. tid = qdf_nbuf_get_priority(nbuf);
  1649. if (tid >= DP_TX_INVALID_QOS_TAG)
  1650. tid = HTT_TX_EXT_TID_INVALID;
  1651. }
  1652. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1653. if (qdf_unlikely(!tx_desc)) {
  1654. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.desc_na.num, 1);
  1655. DP_STATS_INC(vdev,
  1656. tx_i[xmit_type].dropped.desc_na_exc_alloc_fail.num,
  1657. 1);
  1658. return nbuf;
  1659. }
  1660. dp_tx_outstanding_inc(pdev);
  1661. /* Initialize the SW tx descriptor */
  1662. tx_desc->nbuf = nbuf;
  1663. tx_desc->frm_type = dp_tx_frm_std;
  1664. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1665. tx_desc->vdev_id = vdev_id;
  1666. tx_desc->pdev = pdev;
  1667. tx_desc->pkt_offset = 0;
  1668. tx_desc->length = pkt_len;
  1669. tx_desc->flags |= pdev->tx_fast_flag;
  1670. tx_desc->nbuf->fast_recycled = 1;
  1671. if (nbuf->is_from_recycler && nbuf->fast_xmit)
  1672. tx_desc->flags |= DP_TX_DESC_FLAG_FAST;
  1673. paddr = dp_tx_nbuf_map_be(vdev, tx_desc, nbuf);
  1674. if (!paddr) {
  1675. /* Handle failure */
  1676. dp_err("qdf_nbuf_map failed");
  1677. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.dma_error, 1);
  1678. goto release_desc;
  1679. }
  1680. tx_desc->dma_addr = paddr;
  1681. hal_tx_desc_cached = (void *)cached_desc;
  1682. hal_tx_desc_cached[0] = (uint32_t)tx_desc->dma_addr;
  1683. hal_tx_desc_cached[1] = tx_desc->id <<
  1684. TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  1685. /* bank_id */
  1686. hal_tx_desc_cached[2] = vdev->bank_id << TCL_DATA_CMD_BANK_ID_LSB;
  1687. hal_tx_desc_cached[3] = vdev->htt_tcl_metadata <<
  1688. TCL_DATA_CMD_TCL_CMD_NUMBER_LSB;
  1689. hal_tx_desc_cached[4] = tx_desc->length;
  1690. /* l3 and l4 checksum enable */
  1691. hal_tx_desc_cached[4] |= DP_TX_L3_L4_CSUM_ENABLE <<
  1692. TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB;
  1693. hal_tx_desc_cached[5] = vdev->lmac_id << TCL_DATA_CMD_PMAC_ID_LSB;
  1694. hal_tx_desc_cached[5] |= vdev->vdev_id << TCL_DATA_CMD_VDEV_ID_LSB;
  1695. if (qdf_unlikely(dp_sawf_tag_valid_get(nbuf))) {
  1696. sawf_tid = dp_sawf_config_be(soc, hal_tx_desc_cached,
  1697. NULL, nbuf, NULL);
  1698. if (sawf_tid != HTT_TX_EXT_TID_INVALID)
  1699. tid = sawf_tid;
  1700. }
  1701. if (tid != HTT_TX_EXT_TID_INVALID) {
  1702. hal_tx_desc_cached[5] |= tid << TCL_DATA_CMD_HLOS_TID_LSB;
  1703. hal_tx_desc_cached[5] |= 1 << TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB;
  1704. }
  1705. if (vdev->opmode == wlan_op_mode_sta)
  1706. hal_tx_desc_cached[6] = vdev->bss_ast_idx |
  1707. ((vdev->bss_ast_hash & 0xF) <<
  1708. TCL_DATA_CMD_CACHE_SET_NUM_LSB);
  1709. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, desc_pool_id);
  1710. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1711. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  1712. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1713. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1714. goto ring_access_fail2;
  1715. }
  1716. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1717. if (qdf_unlikely(!hal_tx_desc)) {
  1718. dp_verbose_debug("TCL ring full ring_id:%d", desc_pool_id);
  1719. DP_STATS_INC(soc, tx.tcl_ring_full[desc_pool_id], 1);
  1720. DP_STATS_INC(vdev, tx_i[xmit_type].dropped.enqueue_fail, 1);
  1721. goto ring_access_fail;
  1722. }
  1723. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1724. /* Sync cached descriptor with HW */
  1725. qdf_mem_copy(hal_tx_desc, hal_tx_desc_cached, DP_TX_FAST_DESC_SIZE);
  1726. qdf_dsb();
  1727. DP_STATS_INC_PKT(vdev, tx_i[xmit_type].processed, 1, tx_desc->length);
  1728. DP_STATS_INC(soc, tx.tcl_enq[desc_pool_id], 1);
  1729. status = QDF_STATUS_SUCCESS;
  1730. ring_access_fail:
  1731. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1732. ring_access_fail2:
  1733. if (status != QDF_STATUS_SUCCESS) {
  1734. dp_tx_nbuf_unmap_be(soc, tx_desc);
  1735. goto release_desc;
  1736. }
  1737. return NULL;
  1738. release_desc:
  1739. dp_tx_desc_release(soc, tx_desc, desc_pool_id);
  1740. return nbuf;
  1741. }
  1742. #endif
  1743. QDF_STATUS dp_tx_desc_pool_alloc_be(struct dp_soc *soc, uint32_t num_elem,
  1744. uint8_t pool_id)
  1745. {
  1746. return QDF_STATUS_SUCCESS;
  1747. }
  1748. void dp_tx_desc_pool_free_be(struct dp_soc *soc, uint8_t pool_id)
  1749. {
  1750. }